[mirror_ubuntu-hirsute-kernel.git] / drivers / mmc / host / renesas_sdhi_sys_dmac.c

// SPDX-License-Identifier: GPL-2.0
/*
 * DMA support use of SYS DMAC with SDHI SD/SDIO controller
 *
 * Copyright (C) 2016-17 Renesas Electronics Corporation
 * Copyright (C) 2016-17 Sang Engineering, Wolfram Sang
 * Copyright (C) 2017 Horms Solutions, Simon Horman
 * Copyright (C) 2010-2011 Guennadi Liakhovetski
 */

#include <linux/device.h>
#include <linux/dma-mapping.h>
#include <linux/dmaengine.h>
#include <linux/mfd/tmio.h>
#include <linux/mmc/host.h>
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/of_device.h>
#include <linux/pagemap.h>
#include <linux/scatterlist.h>
#include <linux/sys_soc.h>

#include "renesas_sdhi.h"
#include "tmio_mmc.h"

#define TMIO_MMC_MIN_DMA_LEN 8

static const struct renesas_sdhi_of_data of_default_cfg = {
	.tmio_flags = TMIO_MMC_HAS_IDLE_WAIT,
};

static const struct renesas_sdhi_of_data of_rz_compatible = {
	.tmio_flags	= TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_32BIT_DATA_PORT |
			  TMIO_MMC_HAVE_CBSY,
	.tmio_ocr_mask	= MMC_VDD_32_33,
	.capabilities	= MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ,
};

static const struct renesas_sdhi_of_data of_rcar_gen1_compatible = {
	.tmio_flags	= TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_CLK_ACTUAL,
	.capabilities	= MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ,
	.capabilities2	= MMC_CAP2_NO_WRITE_PROTECT,
};

/* Definitions for sampling clocks */
static struct renesas_sdhi_scc rcar_gen2_scc_taps[] = {
	{
		.clk_rate = 156000000,
		.tap = 0x00000703,
	},
	{
		.clk_rate = 0,
		.tap = 0x00000300,
	},
};

static const struct renesas_sdhi_of_data of_rcar_gen2_compatible = {
	.tmio_flags	= TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_CLK_ACTUAL |
			  TMIO_MMC_HAVE_CBSY | TMIO_MMC_MIN_RCAR2,
	.capabilities	= MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ |
			  MMC_CAP_CMD23,
	.capabilities2	= MMC_CAP2_NO_WRITE_PROTECT,
	.dma_buswidth	= DMA_SLAVE_BUSWIDTH_4_BYTES,
	.dma_rx_offset	= 0x2000,
	.scc_offset	= 0x0300,
	.taps		= rcar_gen2_scc_taps,
	.taps_num	= ARRAY_SIZE(rcar_gen2_scc_taps),
	.max_blk_count  = 0xffffffff,
};

/* Definitions for sampling clocks */
static struct renesas_sdhi_scc rcar_gen3_scc_taps[] = {
	{
		.clk_rate = 0,
		.tap = 0x00000300,
	},
};

static const struct renesas_sdhi_of_data of_rcar_gen3_compatible = {
	.tmio_flags	= TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_CLK_ACTUAL |
			  TMIO_MMC_HAVE_CBSY | TMIO_MMC_MIN_RCAR2,
	.capabilities	= MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ |
			  MMC_CAP_CMD23,
	.capabilities2	= MMC_CAP2_NO_WRITE_PROTECT,
	.bus_shift	= 2,
	.scc_offset	= 0x1000,
	.taps		= rcar_gen3_scc_taps,
	.taps_num	= ARRAY_SIZE(rcar_gen3_scc_taps),
};

static const struct of_device_id renesas_sdhi_sys_dmac_of_match[] = {
	{ .compatible = "renesas,sdhi-sh73a0", .data = &of_default_cfg, },
	{ .compatible = "renesas,sdhi-r8a73a4", .data = &of_default_cfg, },
	{ .compatible = "renesas,sdhi-r8a7740", .data = &of_default_cfg, },
	{ .compatible = "renesas,sdhi-r7s72100", .data = &of_rz_compatible, },
	{ .compatible = "renesas,sdhi-r8a7778", .data = &of_rcar_gen1_compatible, },
	{ .compatible = "renesas,sdhi-r8a7779", .data = &of_rcar_gen1_compatible, },
	{ .compatible = "renesas,sdhi-r8a7743", .data = &of_rcar_gen2_compatible, },
	{ .compatible = "renesas,sdhi-r8a7745", .data = &of_rcar_gen2_compatible, },
	{ .compatible = "renesas,sdhi-r8a7790", .data = &of_rcar_gen2_compatible, },
	{ .compatible = "renesas,sdhi-r8a7791", .data = &of_rcar_gen2_compatible, },
	{ .compatible = "renesas,sdhi-r8a7792", .data = &of_rcar_gen2_compatible, },
	{ .compatible = "renesas,sdhi-r8a7793", .data = &of_rcar_gen2_compatible, },
	{ .compatible = "renesas,sdhi-r8a7794", .data = &of_rcar_gen2_compatible, },
	{ .compatible = "renesas,sdhi-r8a7795", .data = &of_rcar_gen3_compatible, },
	{ .compatible = "renesas,sdhi-r8a7796", .data = &of_rcar_gen3_compatible, },
	{ .compatible = "renesas,rcar-gen1-sdhi", .data = &of_rcar_gen1_compatible, },
	{ .compatible = "renesas,rcar-gen2-sdhi", .data = &of_rcar_gen2_compatible, },
	{ .compatible = "renesas,rcar-gen3-sdhi", .data = &of_rcar_gen3_compatible, },
	{ .compatible = "renesas,sdhi-shmobile" },
	{},
};
MODULE_DEVICE_TABLE(of, renesas_sdhi_sys_dmac_of_match);

static void renesas_sdhi_sys_dmac_enable_dma(struct tmio_mmc_host *host,
					     bool enable)
{
	struct renesas_sdhi *priv = host_to_priv(host);

	if (!host->chan_tx || !host->chan_rx)
		return;

	if (priv->dma_priv.enable)
		priv->dma_priv.enable(host, enable);
}

static void renesas_sdhi_sys_dmac_abort_dma(struct tmio_mmc_host *host)
{
	renesas_sdhi_sys_dmac_enable_dma(host, false);

	if (host->chan_rx)
		dmaengine_terminate_all(host->chan_rx);
	if (host->chan_tx)
		dmaengine_terminate_all(host->chan_tx);

	renesas_sdhi_sys_dmac_enable_dma(host, true);
}

static void renesas_sdhi_sys_dmac_dataend_dma(struct tmio_mmc_host *host)
{
	struct renesas_sdhi *priv = host_to_priv(host);

	complete(&priv->dma_priv.dma_dataend);
}

static void renesas_sdhi_sys_dmac_dma_callback(void *arg)
{
	struct tmio_mmc_host *host = arg;
	struct renesas_sdhi *priv = host_to_priv(host);

	spin_lock_irq(&host->lock);

	if (!host->data)
		goto out;

	if (host->data->flags & MMC_DATA_READ)
		dma_unmap_sg(host->chan_rx->device->dev,
			     host->sg_ptr, host->sg_len,
			     DMA_FROM_DEVICE);
	else
		dma_unmap_sg(host->chan_tx->device->dev,
			     host->sg_ptr, host->sg_len,
			     DMA_TO_DEVICE);

	spin_unlock_irq(&host->lock);

	wait_for_completion(&priv->dma_priv.dma_dataend);

	spin_lock_irq(&host->lock);
	tmio_mmc_do_data_irq(host);
out:
	spin_unlock_irq(&host->lock);
}

static void renesas_sdhi_sys_dmac_start_dma_rx(struct tmio_mmc_host *host)
{
	struct renesas_sdhi *priv = host_to_priv(host);
	struct scatterlist *sg = host->sg_ptr, *sg_tmp;
	struct dma_async_tx_descriptor *desc = NULL;
	struct dma_chan *chan = host->chan_rx;
	dma_cookie_t cookie;
	int ret, i;
	bool aligned = true, multiple = true;
	unsigned int align = (1 << host->pdata->alignment_shift) - 1;

	for_each_sg(sg, sg_tmp, host->sg_len, i) {
		if (sg_tmp->offset & align)
			aligned = false;
		if (sg_tmp->length & align) {
			multiple = false;
			break;
		}
	}

	if ((!aligned && (host->sg_len > 1 || sg->length > PAGE_SIZE ||
			  (align & PAGE_MASK))) || !multiple) {
		ret = -EINVAL;
		goto pio;
	}

	if (sg->length < TMIO_MMC_MIN_DMA_LEN)
		return;

	/* The only sg element can be unaligned, use our bounce buffer then */
	if (!aligned) {
		sg_init_one(&host->bounce_sg, host->bounce_buf, sg->length);
		host->sg_ptr = &host->bounce_sg;
		sg = host->sg_ptr;
	}

	ret = dma_map_sg(chan->device->dev, sg, host->sg_len, DMA_FROM_DEVICE);
	if (ret > 0)
		desc = dmaengine_prep_slave_sg(chan, sg, ret, DMA_DEV_TO_MEM,
					       DMA_CTRL_ACK);

	if (desc) {
		reinit_completion(&priv->dma_priv.dma_dataend);
		desc->callback = renesas_sdhi_sys_dmac_dma_callback;
		desc->callback_param = host;

		cookie = dmaengine_submit(desc);
		if (cookie < 0) {
			desc = NULL;
			ret = cookie;
		}
		host->dma_on = true;
	}
pio:
	if (!desc) {
		/* DMA failed, fall back to PIO */
		renesas_sdhi_sys_dmac_enable_dma(host, false);
		if (ret >= 0)
			ret = -EIO;
		host->chan_rx = NULL;
		dma_release_channel(chan);
		/* Free the Tx channel too */
		chan = host->chan_tx;
		if (chan) {
			host->chan_tx = NULL;
			dma_release_channel(chan);
		}
		dev_warn(&host->pdev->dev,
			 "DMA failed: %d, falling back to PIO\n", ret);
	}
}

static void renesas_sdhi_sys_dmac_start_dma_tx(struct tmio_mmc_host *host)
{
	struct renesas_sdhi *priv = host_to_priv(host);
	struct scatterlist *sg = host->sg_ptr, *sg_tmp;
	struct dma_async_tx_descriptor *desc = NULL;
	struct dma_chan *chan = host->chan_tx;
	dma_cookie_t cookie;
	int ret, i;
	bool aligned = true, multiple = true;
	unsigned int align = (1 << host->pdata->alignment_shift) - 1;

	for_each_sg(sg, sg_tmp, host->sg_len, i) {
		if (sg_tmp->offset & align)
			aligned = false;
		if (sg_tmp->length & align) {
			multiple = false;
			break;
		}
	}

	if ((!aligned && (host->sg_len > 1 || sg->length > PAGE_SIZE ||
			  (align & PAGE_MASK))) || !multiple) {
		ret = -EINVAL;
		goto pio;
	}

	if (sg->length < TMIO_MMC_MIN_DMA_LEN)
		return;

	/* The only sg element can be unaligned, use our bounce buffer then */
	if (!aligned) {
		unsigned long flags;
		void *sg_vaddr = tmio_mmc_kmap_atomic(sg, &flags);

		sg_init_one(&host->bounce_sg, host->bounce_buf, sg->length);
		memcpy(host->bounce_buf, sg_vaddr, host->bounce_sg.length);
		tmio_mmc_kunmap_atomic(sg, &flags, sg_vaddr);
		host->sg_ptr = &host->bounce_sg;
		sg = host->sg_ptr;
	}

	ret = dma_map_sg(chan->device->dev, sg, host->sg_len, DMA_TO_DEVICE);
	if (ret > 0)
		desc = dmaengine_prep_slave_sg(chan, sg, ret, DMA_MEM_TO_DEV,
					       DMA_CTRL_ACK);

	if (desc) {
		reinit_completion(&priv->dma_priv.dma_dataend);
		desc->callback = renesas_sdhi_sys_dmac_dma_callback;
		desc->callback_param = host;

		cookie = dmaengine_submit(desc);
		if (cookie < 0) {
			desc = NULL;
			ret = cookie;
		}
		host->dma_on = true;
	}
pio:
	if (!desc) {
		/* DMA failed, fall back to PIO */
		renesas_sdhi_sys_dmac_enable_dma(host, false);
		if (ret >= 0)
			ret = -EIO;
		host->chan_tx = NULL;
		dma_release_channel(chan);
		/* Free the Rx channel too */
		chan = host->chan_rx;
		if (chan) {
			host->chan_rx = NULL;
			dma_release_channel(chan);
		}
		dev_warn(&host->pdev->dev,
			 "DMA failed: %d, falling back to PIO\n", ret);
	}
}

static void renesas_sdhi_sys_dmac_start_dma(struct tmio_mmc_host *host,
					    struct mmc_data *data)
{
	if (data->flags & MMC_DATA_READ) {
		if (host->chan_rx)
			renesas_sdhi_sys_dmac_start_dma_rx(host);
	} else {
		if (host->chan_tx)
			renesas_sdhi_sys_dmac_start_dma_tx(host);
	}
}

static void renesas_sdhi_sys_dmac_issue_tasklet_fn(unsigned long priv)
{
	struct tmio_mmc_host *host = (struct tmio_mmc_host *)priv;
	struct dma_chan *chan = NULL;

	spin_lock_irq(&host->lock);

	if (host->data) {
		if (host->data->flags & MMC_DATA_READ)
			chan = host->chan_rx;
		else
			chan = host->chan_tx;
	}

	spin_unlock_irq(&host->lock);

	tmio_mmc_enable_mmc_irqs(host, TMIO_STAT_DATAEND);

	if (chan)
		dma_async_issue_pending(chan);
}

static void renesas_sdhi_sys_dmac_request_dma(struct tmio_mmc_host *host,
					      struct tmio_mmc_data *pdata)
{
	struct renesas_sdhi *priv = host_to_priv(host);

	/* We can only either use DMA for both Tx and Rx or not use it at all */
	if (!host->pdev->dev.of_node &&
	    (!pdata->chan_priv_tx || !pdata->chan_priv_rx))
		return;

	if (!host->chan_tx && !host->chan_rx) {
		struct resource *res = platform_get_resource(host->pdev,
							     IORESOURCE_MEM, 0);
		struct dma_slave_config cfg = {};
		dma_cap_mask_t mask;
		int ret;

		if (!res)
			return;

		dma_cap_zero(mask);
		dma_cap_set(DMA_SLAVE, mask);

		host->chan_tx = dma_request_slave_channel_compat(mask,
					priv->dma_priv.filter, pdata->chan_priv_tx,
					&host->pdev->dev, "tx");
		dev_dbg(&host->pdev->dev, "%s: TX: got channel %p\n", __func__,
			host->chan_tx);

		if (!host->chan_tx)
			return;

		cfg.direction = DMA_MEM_TO_DEV;
		cfg.dst_addr = res->start +
			(CTL_SD_DATA_PORT << host->bus_shift);
		cfg.dst_addr_width = priv->dma_priv.dma_buswidth;
		if (!cfg.dst_addr_width)
			cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
		cfg.src_addr = 0;
		ret = dmaengine_slave_config(host->chan_tx, &cfg);
		if (ret < 0)
			goto ecfgtx;

		host->chan_rx = dma_request_slave_channel_compat(mask,
					priv->dma_priv.filter, pdata->chan_priv_rx,
					&host->pdev->dev, "rx");
		dev_dbg(&host->pdev->dev, "%s: RX: got channel %p\n", __func__,
			host->chan_rx);

		if (!host->chan_rx)
			goto ereqrx;

		cfg.direction = DMA_DEV_TO_MEM;
		cfg.src_addr = cfg.dst_addr + host->pdata->dma_rx_offset;
		cfg.src_addr_width = priv->dma_priv.dma_buswidth;
		if (!cfg.src_addr_width)
			cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
		cfg.dst_addr = 0;
		ret = dmaengine_slave_config(host->chan_rx, &cfg);
		if (ret < 0)
			goto ecfgrx;

		host->bounce_buf = (u8 *)__get_free_page(GFP_KERNEL | GFP_DMA);
		if (!host->bounce_buf)
			goto ebouncebuf;

		init_completion(&priv->dma_priv.dma_dataend);
		tasklet_init(&host->dma_issue,
			     renesas_sdhi_sys_dmac_issue_tasklet_fn,
			     (unsigned long)host);
	}

	renesas_sdhi_sys_dmac_enable_dma(host, true);

	return;

ebouncebuf:
ecfgrx:
	dma_release_channel(host->chan_rx);
	host->chan_rx = NULL;
ereqrx:
ecfgtx:
	dma_release_channel(host->chan_tx);
	host->chan_tx = NULL;
}

static void renesas_sdhi_sys_dmac_release_dma(struct tmio_mmc_host *host)
{
	if (host->chan_tx) {
		struct dma_chan *chan = host->chan_tx;

		host->chan_tx = NULL;
		dma_release_channel(chan);
	}
	if (host->chan_rx) {
		struct dma_chan *chan = host->chan_rx;

		host->chan_rx = NULL;
		dma_release_channel(chan);
	}
	if (host->bounce_buf) {
		free_pages((unsigned long)host->bounce_buf, 0);
		host->bounce_buf = NULL;
	}
}

static const struct tmio_mmc_dma_ops renesas_sdhi_sys_dmac_dma_ops = {
	.start = renesas_sdhi_sys_dmac_start_dma,
	.enable = renesas_sdhi_sys_dmac_enable_dma,
	.request = renesas_sdhi_sys_dmac_request_dma,
	.release = renesas_sdhi_sys_dmac_release_dma,
	.abort = renesas_sdhi_sys_dmac_abort_dma,
	.dataend = renesas_sdhi_sys_dmac_dataend_dma,
};

/*
 * Whitelist of specific R-Car Gen3 SoC ES versions to use this DMAC
 * implementation. Currently empty as all supported ES versions use
 * the internal DMAC.
 */
static const struct soc_device_attribute gen3_soc_whitelist[] = {
        { /* sentinel */ }
};

static int renesas_sdhi_sys_dmac_probe(struct platform_device *pdev)
{
	if (of_device_get_match_data(&pdev->dev) == &of_rcar_gen3_compatible &&
	    !soc_device_match(gen3_soc_whitelist))
		return -ENODEV;

	return renesas_sdhi_probe(pdev, &renesas_sdhi_sys_dmac_dma_ops);
}

static const struct dev_pm_ops renesas_sdhi_sys_dmac_dev_pm_ops = {
	SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
				pm_runtime_force_resume)
	SET_RUNTIME_PM_OPS(tmio_mmc_host_runtime_suspend,
			   tmio_mmc_host_runtime_resume,
			   NULL)
};

static struct platform_driver renesas_sys_dmac_sdhi_driver = {
	.driver		= {
		.name	= "sh_mobile_sdhi",
		.pm	= &renesas_sdhi_sys_dmac_dev_pm_ops,
		.of_match_table = renesas_sdhi_sys_dmac_of_match,
	},
	.probe		= renesas_sdhi_sys_dmac_probe,
	.remove		= renesas_sdhi_remove,
};

module_platform_driver(renesas_sys_dmac_sdhi_driver);

MODULE_DESCRIPTION("Renesas SDHI driver");
MODULE_AUTHOR("Magnus Damm");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("platform:sh_mobile_sdhi");
Commit	Line	Data
f707079d	1	// SPDX-License-Identifier: GPL-2.0
b6147490	2	/*
2a68ea78	3	* DMA support use of SYS DMAC with SDHI SD/SDIO controller
b6147490	4	*
87317c4d SH	5	* Copyright (C) 2016-17 Renesas Electronics Corporation
	6	* Copyright (C) 2016-17 Sang Engineering, Wolfram Sang
	7	* Copyright (C) 2017 Horms Solutions, Simon Horman
b6147490	8	* Copyright (C) 2010-2011 Guennadi Liakhovetski
b6147490 GL	9	*/
	10
	11	#include <linux/device.h>
b7f080cf	12	#include <linux/dma-mapping.h>
b6147490 GL	13	#include <linux/dmaengine.h>
	14	#include <linux/mfd/tmio.h>
	15	#include <linux/mmc/host.h>
9d08428a SH	16	#include <linux/mod_devicetable.h>
9d08428a SH	17	#include <linux/module.h>
cd09780f	18	#include <linux/of_device.h>
b6147490 GL	19	#include <linux/pagemap.h>
b6147490 GL	20	#include <linux/scatterlist.h>
cd09780f	21	#include <linux/sys_soc.h>
b6147490	22
9d08428a	23	#include "renesas_sdhi.h"
b6147490 GL	24	#include "tmio_mmc.h"
	25
	26	#define TMIO_MMC_MIN_DMA_LEN 8
	27
9d08428a SH	28	static const struct renesas_sdhi_of_data of_default_cfg = {
	29	.tmio_flags = TMIO_MMC_HAS_IDLE_WAIT,
	30	};
	31
	32	static const struct renesas_sdhi_of_data of_rz_compatible = {
92b7db8e WS	33	.tmio_flags = TMIO_MMC_HAS_IDLE_WAIT \| TMIO_MMC_32BIT_DATA_PORT \|
92b7db8e WS	34	TMIO_MMC_HAVE_CBSY,
9d08428a SH	35	.tmio_ocr_mask = MMC_VDD_32_33,
	36	.capabilities = MMC_CAP_SD_HIGHSPEED \| MMC_CAP_SDIO_IRQ,
	37	};
	38
	39	static const struct renesas_sdhi_of_data of_rcar_gen1_compatible = {
2ad1db05	40	.tmio_flags = TMIO_MMC_HAS_IDLE_WAIT \| TMIO_MMC_CLK_ACTUAL,
9d08428a	41	.capabilities = MMC_CAP_SD_HIGHSPEED \| MMC_CAP_SDIO_IRQ,
ef5332c1	42	.capabilities2 = MMC_CAP2_NO_WRITE_PROTECT,
9d08428a SH	43	};
	44
	45	/* Definitions for sampling clocks */
	46	static struct renesas_sdhi_scc rcar_gen2_scc_taps[] = {
	47	{
	48	.clk_rate = 156000000,
	49	.tap = 0x00000703,
	50	},
	51	{
	52	.clk_rate = 0,
	53	.tap = 0x00000300,
	54	},
	55	};
	56
	57	static const struct renesas_sdhi_of_data of_rcar_gen2_compatible = {
2ad1db05 MY	58	.tmio_flags = TMIO_MMC_HAS_IDLE_WAIT \| TMIO_MMC_CLK_ACTUAL \|
2ad1db05 MY	59	TMIO_MMC_HAVE_CBSY \| TMIO_MMC_MIN_RCAR2,
921579b2 WS	60	.capabilities = MMC_CAP_SD_HIGHSPEED \| MMC_CAP_SDIO_IRQ \|
921579b2 WS	61	MMC_CAP_CMD23,
ef5332c1	62	.capabilities2 = MMC_CAP2_NO_WRITE_PROTECT,
9d08428a SH	63	.dma_buswidth = DMA_SLAVE_BUSWIDTH_4_BYTES,
	64	.dma_rx_offset = 0x2000,
	65	.scc_offset = 0x0300,
	66	.taps = rcar_gen2_scc_taps,
	67	.taps_num = ARRAY_SIZE(rcar_gen2_scc_taps),
5603731a	68	.max_blk_count = 0xffffffff,
9d08428a SH	69	};
	70
	71	/* Definitions for sampling clocks */
	72	static struct renesas_sdhi_scc rcar_gen3_scc_taps[] = {
	73	{
	74	.clk_rate = 0,
	75	.tap = 0x00000300,
	76	},
	77	};
	78
	79	static const struct renesas_sdhi_of_data of_rcar_gen3_compatible = {
2ad1db05 MY	80	.tmio_flags = TMIO_MMC_HAS_IDLE_WAIT \| TMIO_MMC_CLK_ACTUAL \|
2ad1db05 MY	81	TMIO_MMC_HAVE_CBSY \| TMIO_MMC_MIN_RCAR2,
921579b2 WS	82	.capabilities = MMC_CAP_SD_HIGHSPEED \| MMC_CAP_SDIO_IRQ \|
921579b2 WS	83	MMC_CAP_CMD23,
ef5332c1	84	.capabilities2 = MMC_CAP2_NO_WRITE_PROTECT,
9d08428a SH	85	.bus_shift = 2,
	86	.scc_offset = 0x1000,
	87	.taps = rcar_gen3_scc_taps,
	88	.taps_num = ARRAY_SIZE(rcar_gen3_scc_taps),
	89	};
	90
	91	static const struct of_device_id renesas_sdhi_sys_dmac_of_match[] = {
9d08428a SH	92	{ .compatible = "renesas,sdhi-sh73a0", .data = &of_default_cfg, },
	93	{ .compatible = "renesas,sdhi-r8a73a4", .data = &of_default_cfg, },
	94	{ .compatible = "renesas,sdhi-r8a7740", .data = &of_default_cfg, },
	95	{ .compatible = "renesas,sdhi-r7s72100", .data = &of_rz_compatible, },
	96	{ .compatible = "renesas,sdhi-r8a7778", .data = &of_rcar_gen1_compatible, },
	97	{ .compatible = "renesas,sdhi-r8a7779", .data = &of_rcar_gen1_compatible, },
c16a854e BD	98	{ .compatible = "renesas,sdhi-r8a7743", .data = &of_rcar_gen2_compatible, },
c16a854e BD	99	{ .compatible = "renesas,sdhi-r8a7745", .data = &of_rcar_gen2_compatible, },
9d08428a SH	100	{ .compatible = "renesas,sdhi-r8a7790", .data = &of_rcar_gen2_compatible, },
	101	{ .compatible = "renesas,sdhi-r8a7791", .data = &of_rcar_gen2_compatible, },
	102	{ .compatible = "renesas,sdhi-r8a7792", .data = &of_rcar_gen2_compatible, },
	103	{ .compatible = "renesas,sdhi-r8a7793", .data = &of_rcar_gen2_compatible, },
	104	{ .compatible = "renesas,sdhi-r8a7794", .data = &of_rcar_gen2_compatible, },
2c907f05 NS	105	{ .compatible = "renesas,sdhi-r8a7795", .data = &of_rcar_gen3_compatible, },
2c907f05 NS	106	{ .compatible = "renesas,sdhi-r8a7796", .data = &of_rcar_gen3_compatible, },
d6dc425a SH	107	{ .compatible = "renesas,rcar-gen1-sdhi", .data = &of_rcar_gen1_compatible, },
	108	{ .compatible = "renesas,rcar-gen2-sdhi", .data = &of_rcar_gen2_compatible, },
	109	{ .compatible = "renesas,rcar-gen3-sdhi", .data = &of_rcar_gen3_compatible, },
	110	{ .compatible = "renesas,sdhi-shmobile" },
9d08428a SH	111	{},
	112	};
	113	MODULE_DEVICE_TABLE(of, renesas_sdhi_sys_dmac_of_match);
	114
c2a96987 SH	115	static void renesas_sdhi_sys_dmac_enable_dma(struct tmio_mmc_host *host,
c2a96987 SH	116	bool enable)
b6147490	117	{
058db286 MY	118	struct renesas_sdhi *priv = host_to_priv(host);
058db286 MY	119
162f43e3 GL	120	if (!host->chan_tx \|\| !host->chan_rx)
	121	return;
	122
058db286 MY	123	if (priv->dma_priv.enable)
058db286 MY	124	priv->dma_priv.enable(host, enable);
b6147490 GL	125	}
b6147490 GL	126
c2a96987	127	static void renesas_sdhi_sys_dmac_abort_dma(struct tmio_mmc_host *host)
e3de2be7	128	{
c2a96987	129	renesas_sdhi_sys_dmac_enable_dma(host, false);
e3de2be7 GL	130
	131	if (host->chan_rx)
	132	dmaengine_terminate_all(host->chan_rx);
	133	if (host->chan_tx)
	134	dmaengine_terminate_all(host->chan_tx);
	135
c2a96987	136	renesas_sdhi_sys_dmac_enable_dma(host, true);
e3de2be7 GL	137	}
e3de2be7 GL	138
92d0f925 SH	139	static void renesas_sdhi_sys_dmac_dataend_dma(struct tmio_mmc_host *host)
92d0f925 SH	140	{
90d95106 MY	141	struct renesas_sdhi *priv = host_to_priv(host);
	142
	143	complete(&priv->dma_priv.dma_dataend);
92d0f925 SH	144	}
92d0f925 SH	145
c2a96987	146	static void renesas_sdhi_sys_dmac_dma_callback(void *arg)
52ad9a8e WS	147	{
52ad9a8e WS	148	struct tmio_mmc_host *host = arg;
90d95106	149	struct renesas_sdhi *priv = host_to_priv(host);
52ad9a8e	150
52ad9a8e WS	151	spin_lock_irq(&host->lock);
	152
	153	if (!host->data)
	154	goto out;
	155
	156	if (host->data->flags & MMC_DATA_READ)
	157	dma_unmap_sg(host->chan_rx->device->dev,
	158	host->sg_ptr, host->sg_len,
	159	DMA_FROM_DEVICE);
	160	else
	161	dma_unmap_sg(host->chan_tx->device->dev,
	162	host->sg_ptr, host->sg_len,
	163	DMA_TO_DEVICE);
	164
5f07ef8f WS	165	spin_unlock_irq(&host->lock);
5f07ef8f WS	166
90d95106	167	wait_for_completion(&priv->dma_priv.dma_dataend);
5f07ef8f WS	168
5f07ef8f WS	169	spin_lock_irq(&host->lock);
52ad9a8e WS	170	tmio_mmc_do_data_irq(host);
	171	out:
	172	spin_unlock_irq(&host->lock);
	173	}
	174
c2a96987	175	static void renesas_sdhi_sys_dmac_start_dma_rx(struct tmio_mmc_host *host)
b6147490	176	{
90d95106	177	struct renesas_sdhi *priv = host_to_priv(host);
b6147490 GL	178	struct scatterlist sg = host->sg_ptr, sg_tmp;
	179	struct dma_async_tx_descriptor *desc = NULL;
	180	struct dma_chan *chan = host->chan_rx;
b6147490 GL	181	dma_cookie_t cookie;
	182	int ret, i;
	183	bool aligned = true, multiple = true;
e471df0b	184	unsigned int align = (1 << host->pdata->alignment_shift) - 1;
b6147490 GL	185
	186	for_each_sg(sg, sg_tmp, host->sg_len, i) {
	187	if (sg_tmp->offset & align)
	188	aligned = false;
	189	if (sg_tmp->length & align) {
	190	multiple = false;
	191	break;
	192	}
	193	}
	194
09cbfeaf	195	if ((!aligned && (host->sg_len > 1 \|\| sg->length > PAGE_SIZE \|\|
b6147490 GL	196	(align & PAGE_MASK))) \|\| !multiple) {
	197	ret = -EINVAL;
	198	goto pio;
	199	}
	200
d3dd5db0	201	if (sg->length < TMIO_MMC_MIN_DMA_LEN)
b6147490	202	return;
b6147490	203
b6147490 GL	204	/* The only sg element can be unaligned, use our bounce buffer then */
	205	if (!aligned) {
	206	sg_init_one(&host->bounce_sg, host->bounce_buf, sg->length);
	207	host->sg_ptr = &host->bounce_sg;
	208	sg = host->sg_ptr;
	209	}
	210
	211	ret = dma_map_sg(chan->device->dev, sg, host->sg_len, DMA_FROM_DEVICE);
	212	if (ret > 0)
2fe35968 SH	213	desc = dmaengine_prep_slave_sg(chan, sg, ret, DMA_DEV_TO_MEM,
2fe35968 SH	214	DMA_CTRL_ACK);
b6147490 GL	215
b6147490 GL	216	if (desc) {
90d95106	217	reinit_completion(&priv->dma_priv.dma_dataend);
c2a96987	218	desc->callback = renesas_sdhi_sys_dmac_dma_callback;
52ad9a8e WS	219	desc->callback_param = host;
52ad9a8e WS	220
b6147490 GL	221	cookie = dmaengine_submit(desc);
	222	if (cookie < 0) {
	223	desc = NULL;
	224	ret = cookie;
	225	}
d3dd5db0	226	host->dma_on = true;
b6147490	227	}
b6147490 GL	228	pio:
	229	if (!desc) {
	230	/* DMA failed, fall back to PIO */
c2a96987	231	renesas_sdhi_sys_dmac_enable_dma(host, false);
b6147490 GL	232	if (ret >= 0)
	233	ret = -EIO;
	234	host->chan_rx = NULL;
	235	dma_release_channel(chan);
	236	/* Free the Tx channel too */
	237	chan = host->chan_tx;
	238	if (chan) {
	239	host->chan_tx = NULL;
	240	dma_release_channel(chan);
	241	}
	242	dev_warn(&host->pdev->dev,
	243	"DMA failed: %d, falling back to PIO\n", ret);
b6147490	244	}
b6147490 GL	245	}
b6147490 GL	246
c2a96987	247	static void renesas_sdhi_sys_dmac_start_dma_tx(struct tmio_mmc_host *host)
b6147490	248	{
90d95106	249	struct renesas_sdhi *priv = host_to_priv(host);
b6147490 GL	250	struct scatterlist sg = host->sg_ptr, sg_tmp;
	251	struct dma_async_tx_descriptor *desc = NULL;
	252	struct dma_chan *chan = host->chan_tx;
b6147490 GL	253	dma_cookie_t cookie;
	254	int ret, i;
	255	bool aligned = true, multiple = true;
e471df0b	256	unsigned int align = (1 << host->pdata->alignment_shift) - 1;
b6147490 GL	257
	258	for_each_sg(sg, sg_tmp, host->sg_len, i) {
	259	if (sg_tmp->offset & align)
	260	aligned = false;
	261	if (sg_tmp->length & align) {
	262	multiple = false;
	263	break;
	264	}
	265	}
	266
09cbfeaf	267	if ((!aligned && (host->sg_len > 1 \|\| sg->length > PAGE_SIZE \|\|
b6147490 GL	268	(align & PAGE_MASK))) \|\| !multiple) {
	269	ret = -EINVAL;
	270	goto pio;
	271	}
	272
d3dd5db0	273	if (sg->length < TMIO_MMC_MIN_DMA_LEN)
b6147490	274	return;
b6147490	275
b6147490 GL	276	/* The only sg element can be unaligned, use our bounce buffer then */
	277	if (!aligned) {
	278	unsigned long flags;
	279	void *sg_vaddr = tmio_mmc_kmap_atomic(sg, &flags);
2fe35968	280
b6147490 GL	281	sg_init_one(&host->bounce_sg, host->bounce_buf, sg->length);
	282	memcpy(host->bounce_buf, sg_vaddr, host->bounce_sg.length);
	283	tmio_mmc_kunmap_atomic(sg, &flags, sg_vaddr);
	284	host->sg_ptr = &host->bounce_sg;
	285	sg = host->sg_ptr;
	286	}
	287
	288	ret = dma_map_sg(chan->device->dev, sg, host->sg_len, DMA_TO_DEVICE);
	289	if (ret > 0)
2fe35968 SH	290	desc = dmaengine_prep_slave_sg(chan, sg, ret, DMA_MEM_TO_DEV,
2fe35968 SH	291	DMA_CTRL_ACK);
b6147490 GL	292
b6147490 GL	293	if (desc) {
90d95106	294	reinit_completion(&priv->dma_priv.dma_dataend);
c2a96987	295	desc->callback = renesas_sdhi_sys_dmac_dma_callback;
52ad9a8e WS	296	desc->callback_param = host;
52ad9a8e WS	297
b6147490 GL	298	cookie = dmaengine_submit(desc);
	299	if (cookie < 0) {
	300	desc = NULL;
	301	ret = cookie;
	302	}
d3dd5db0	303	host->dma_on = true;
b6147490	304	}
b6147490 GL	305	pio:
	306	if (!desc) {
	307	/* DMA failed, fall back to PIO */
c2a96987	308	renesas_sdhi_sys_dmac_enable_dma(host, false);
b6147490 GL	309	if (ret >= 0)
	310	ret = -EIO;
	311	host->chan_tx = NULL;
	312	dma_release_channel(chan);
	313	/* Free the Rx channel too */
	314	chan = host->chan_rx;
	315	if (chan) {
	316	host->chan_rx = NULL;
	317	dma_release_channel(chan);
	318	}
	319	dev_warn(&host->pdev->dev,
	320	"DMA failed: %d, falling back to PIO\n", ret);
b6147490	321	}
b6147490 GL	322	}
b6147490 GL	323
c2a96987	324	static void renesas_sdhi_sys_dmac_start_dma(struct tmio_mmc_host *host,
2fe35968	325	struct mmc_data *data)
b6147490 GL	326	{
	327	if (data->flags & MMC_DATA_READ) {
	328	if (host->chan_rx)
c2a96987	329	renesas_sdhi_sys_dmac_start_dma_rx(host);
b6147490 GL	330	} else {
b6147490 GL	331	if (host->chan_tx)
c2a96987	332	renesas_sdhi_sys_dmac_start_dma_tx(host);
b6147490 GL	333	}
	334	}
	335
c2a96987	336	static void renesas_sdhi_sys_dmac_issue_tasklet_fn(unsigned long priv)
b6147490 GL	337	{
	338	struct tmio_mmc_host host = (struct tmio_mmc_host )priv;
	339	struct dma_chan *chan = NULL;
	340
	341	spin_lock_irq(&host->lock);
	342
b8155d3f	343	if (host->data) {
b6147490 GL	344	if (host->data->flags & MMC_DATA_READ)
	345	chan = host->chan_rx;
	346	else
	347	chan = host->chan_tx;
	348	}
	349
	350	spin_unlock_irq(&host->lock);
	351
	352	tmio_mmc_enable_mmc_irqs(host, TMIO_STAT_DATAEND);
	353
	354	if (chan)
	355	dma_async_issue_pending(chan);
	356	}
	357
c2a96987 SH	358	static void renesas_sdhi_sys_dmac_request_dma(struct tmio_mmc_host *host,
c2a96987 SH	359	struct tmio_mmc_data *pdata)
b6147490	360	{
058db286 MY	361	struct renesas_sdhi *priv = host_to_priv(host);
058db286 MY	362
b6147490	363	/* We can only either use DMA for both Tx and Rx or not use it at all */
2487e7ef MY	364	if (!host->pdev->dev.of_node &&
2487e7ef MY	365	(!pdata->chan_priv_tx \|\| !pdata->chan_priv_rx))
e6ee7182 GL	366	return;
	367
	368	if (!host->chan_tx && !host->chan_rx) {
eec95ee2 GL	369	struct resource *res = platform_get_resource(host->pdev,
	370	IORESOURCE_MEM, 0);
	371	struct dma_slave_config cfg = {};
b6147490	372	dma_cap_mask_t mask;
eec95ee2 GL	373	int ret;
	374
	375	if (!res)
	376	return;
b6147490 GL	377
	378	dma_cap_zero(mask);
	379	dma_cap_set(DMA_SLAVE, mask);
	380
87ae7bbe	381	host->chan_tx = dma_request_slave_channel_compat(mask,
058db286	382	priv->dma_priv.filter, pdata->chan_priv_tx,
87ae7bbe	383	&host->pdev->dev, "tx");
b6147490 GL	384	dev_dbg(&host->pdev->dev, "%s: TX: got channel %p\n", __func__,
	385	host->chan_tx);
	386
	387	if (!host->chan_tx)
	388	return;
	389
eec95ee2	390	cfg.direction = DMA_MEM_TO_DEV;
2fe35968 SH	391	cfg.dst_addr = res->start +
2fe35968 SH	392	(CTL_SD_DATA_PORT << host->bus_shift);
058db286	393	cfg.dst_addr_width = priv->dma_priv.dma_buswidth;
361936ef KM	394	if (!cfg.dst_addr_width)
361936ef KM	395	cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
eec95ee2 GL	396	cfg.src_addr = 0;
	397	ret = dmaengine_slave_config(host->chan_tx, &cfg);
	398	if (ret < 0)
	399	goto ecfgtx;
	400
87ae7bbe	401	host->chan_rx = dma_request_slave_channel_compat(mask,
058db286	402	priv->dma_priv.filter, pdata->chan_priv_rx,
87ae7bbe	403	&host->pdev->dev, "rx");
b6147490 GL	404	dev_dbg(&host->pdev->dev, "%s: RX: got channel %p\n", __func__,
	405	host->chan_rx);
	406
	407	if (!host->chan_rx)
	408	goto ereqrx;
	409
eec95ee2	410	cfg.direction = DMA_DEV_TO_MEM;
8b4c8f32	411	cfg.src_addr = cfg.dst_addr + host->pdata->dma_rx_offset;
058db286	412	cfg.src_addr_width = priv->dma_priv.dma_buswidth;
361936ef KM	413	if (!cfg.src_addr_width)
361936ef KM	414	cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
eec95ee2 GL	415	cfg.dst_addr = 0;
	416	ret = dmaengine_slave_config(host->chan_rx, &cfg);
	417	if (ret < 0)
	418	goto ecfgrx;
	419
b6147490 GL	420	host->bounce_buf = (u8 *)__get_free_page(GFP_KERNEL \| GFP_DMA);
	421	if (!host->bounce_buf)
	422	goto ebouncebuf;
	423
90d95106	424	init_completion(&priv->dma_priv.dma_dataend);
c2a96987 SH	425	tasklet_init(&host->dma_issue,
	426	renesas_sdhi_sys_dmac_issue_tasklet_fn,
	427	(unsigned long)host);
e6ee7182	428	}
b6147490	429
c2a96987	430	renesas_sdhi_sys_dmac_enable_dma(host, true);
e6ee7182 GL	431
e6ee7182 GL	432	return;
b6147490	433
b6147490	434	ebouncebuf:
eec95ee2	435	ecfgrx:
e6ee7182 GL	436	dma_release_channel(host->chan_rx);
e6ee7182 GL	437	host->chan_rx = NULL;
b6147490	438	ereqrx:
eec95ee2	439	ecfgtx:
e6ee7182 GL	440	dma_release_channel(host->chan_tx);
e6ee7182 GL	441	host->chan_tx = NULL;
b6147490 GL	442	}
b6147490 GL	443
c2a96987	444	static void renesas_sdhi_sys_dmac_release_dma(struct tmio_mmc_host *host)
b6147490 GL	445	{
	446	if (host->chan_tx) {
	447	struct dma_chan *chan = host->chan_tx;
2fe35968	448
b6147490 GL	449	host->chan_tx = NULL;
	450	dma_release_channel(chan);
	451	}
	452	if (host->chan_rx) {
	453	struct dma_chan *chan = host->chan_rx;
2fe35968	454
b6147490 GL	455	host->chan_rx = NULL;
	456	dma_release_channel(chan);
	457	}
	458	if (host->bounce_buf) {
	459	free_pages((unsigned long)host->bounce_buf, 0);
	460	host->bounce_buf = NULL;
	461	}
	462	}
631fa73c	463
c2a96987 SH	464	static const struct tmio_mmc_dma_ops renesas_sdhi_sys_dmac_dma_ops = {
	465	.start = renesas_sdhi_sys_dmac_start_dma,
	466	.enable = renesas_sdhi_sys_dmac_enable_dma,
	467	.request = renesas_sdhi_sys_dmac_request_dma,
	468	.release = renesas_sdhi_sys_dmac_release_dma,
	469	.abort = renesas_sdhi_sys_dmac_abort_dma,
92d0f925	470	.dataend = renesas_sdhi_sys_dmac_dataend_dma,
631fa73c SH	471	};
631fa73c SH	472
cd09780f SH	473	/*
	474	* Whitelist of specific R-Car Gen3 SoC ES versions to use this DMAC
	475	* implementation. Currently empty as all supported ES versions use
	476	* the internal DMAC.
	477	*/
	478	static const struct soc_device_attribute gen3_soc_whitelist[] = {
	479	{ /* sentinel */ }
	480	};
	481
9d08428a	482	static int renesas_sdhi_sys_dmac_probe(struct platform_device *pdev)
631fa73c	483	{
2c907f05	484	if (of_device_get_match_data(&pdev->dev) == &of_rcar_gen3_compatible &&
cd09780f SH	485	!soc_device_match(gen3_soc_whitelist))
	486	return -ENODEV;
	487
9d08428a	488	return renesas_sdhi_probe(pdev, &renesas_sdhi_sys_dmac_dma_ops);
631fa73c	489	}
9d08428a SH	490
	491	static const struct dev_pm_ops renesas_sdhi_sys_dmac_dev_pm_ops = {
	492	SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
2fe35968	493	pm_runtime_force_resume)
9d08428a	494	SET_RUNTIME_PM_OPS(tmio_mmc_host_runtime_suspend,
2fe35968 SH	495	tmio_mmc_host_runtime_resume,
2fe35968 SH	496	NULL)
9d08428a SH	497	};
	498
	499	static struct platform_driver renesas_sys_dmac_sdhi_driver = {
	500	.driver = {
	501	.name = "sh_mobile_sdhi",
	502	.pm = &renesas_sdhi_sys_dmac_dev_pm_ops,
	503	.of_match_table = renesas_sdhi_sys_dmac_of_match,
	504	},
	505	.probe = renesas_sdhi_sys_dmac_probe,
	506	.remove = renesas_sdhi_remove,
	507	};
	508
	509	module_platform_driver(renesas_sys_dmac_sdhi_driver);
	510
	511	MODULE_DESCRIPTION("Renesas SDHI driver");
	512	MODULE_AUTHOR("Magnus Damm");
	513	MODULE_LICENSE("GPL v2");
	514	MODULE_ALIAS("platform:sh_mobile_sdhi");