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aaf4989b | 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
ff984e57 WW |
2 | /* Realtek PCI-Express SD/MMC Card Interface driver |
3 | * | |
62282180 | 4 | * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved. |
ff984e57 | 5 | * |
ff984e57 WW |
6 | * Author: |
7 | * Wei WANG <wei_wang@realsil.com.cn> | |
ff984e57 WW |
8 | */ |
9 | ||
10 | #include <linux/module.h> | |
433e075c | 11 | #include <linux/slab.h> |
ff984e57 WW |
12 | #include <linux/highmem.h> |
13 | #include <linux/delay.h> | |
14 | #include <linux/platform_device.h> | |
6291e715 | 15 | #include <linux/workqueue.h> |
ff984e57 WW |
16 | #include <linux/mmc/host.h> |
17 | #include <linux/mmc/mmc.h> | |
18 | #include <linux/mmc/sd.h> | |
1dcb3579 | 19 | #include <linux/mmc/sdio.h> |
ff984e57 | 20 | #include <linux/mmc/card.h> |
e455b69d | 21 | #include <linux/rtsx_pci.h> |
ff984e57 | 22 | #include <asm/unaligned.h> |
5b4258f6 | 23 | #include <linux/pm_runtime.h> |
ff984e57 | 24 | |
ff984e57 WW |
25 | struct realtek_pci_sdmmc { |
26 | struct platform_device *pdev; | |
27 | struct rtsx_pcr *pcr; | |
28 | struct mmc_host *mmc; | |
29 | struct mmc_request *mrq; | |
6291e715 | 30 | #define SDMMC_WORKQ_NAME "rtsx_pci_sdmmc_workq" |
98fcc576 | 31 | |
6291e715 | 32 | struct work_struct work; |
98fcc576 MC |
33 | struct mutex host_mutex; |
34 | ||
ff984e57 WW |
35 | u8 ssc_depth; |
36 | unsigned int clock; | |
37 | bool vpclk; | |
38 | bool double_clk; | |
39 | bool eject; | |
40 | bool initial_mode; | |
d88691be WW |
41 | int power_state; |
42 | #define SDMMC_POWER_ON 1 | |
43 | #define SDMMC_POWER_OFF 0 | |
6291e715 | 44 | |
be186ad5 | 45 | int sg_count; |
6291e715 | 46 | s32 cookie; |
be186ad5 | 47 | int cookie_sg_count; |
6291e715 | 48 | bool using_cookie; |
ff984e57 WW |
49 | }; |
50 | ||
6b7b58f4 RF |
51 | static int sdmmc_init_sd_express(struct mmc_host *mmc, struct mmc_ios *ios); |
52 | ||
ff984e57 WW |
53 | static inline struct device *sdmmc_dev(struct realtek_pci_sdmmc *host) |
54 | { | |
55 | return &(host->pdev->dev); | |
56 | } | |
57 | ||
58 | static inline void sd_clear_error(struct realtek_pci_sdmmc *host) | |
59 | { | |
60 | rtsx_pci_write_register(host->pcr, CARD_STOP, | |
61 | SD_STOP | SD_CLR_ERR, SD_STOP | SD_CLR_ERR); | |
62 | } | |
63 | ||
64 | #ifdef DEBUG | |
755987f9 | 65 | static void dump_reg_range(struct realtek_pci_sdmmc *host, u16 start, u16 end) |
ff984e57 | 66 | { |
755987f9 MC |
67 | u16 len = end - start + 1; |
68 | int i; | |
69 | u8 data[8]; | |
70 | ||
71 | for (i = 0; i < len; i += 8) { | |
72 | int j; | |
73 | int n = min(8, len - i); | |
ff984e57 | 74 | |
755987f9 MC |
75 | memset(&data, 0, sizeof(data)); |
76 | for (j = 0; j < n; j++) | |
77 | rtsx_pci_read_register(host->pcr, start + i + j, | |
78 | data + j); | |
79 | dev_dbg(sdmmc_dev(host), "0x%04X(%d): %8ph\n", | |
80 | start + i, n, data); | |
81 | } | |
82 | } | |
ff984e57 | 83 | |
755987f9 MC |
84 | static void sd_print_debug_regs(struct realtek_pci_sdmmc *host) |
85 | { | |
86 | dump_reg_range(host, 0xFDA0, 0xFDB3); | |
87 | dump_reg_range(host, 0xFD52, 0xFD69); | |
ff984e57 WW |
88 | } |
89 | #else | |
90 | #define sd_print_debug_regs(host) | |
91 | #endif /* DEBUG */ | |
92 | ||
b22217f9 MC |
93 | static inline int sd_get_cd_int(struct realtek_pci_sdmmc *host) |
94 | { | |
95 | return rtsx_pci_readl(host->pcr, RTSX_BIPR) & SD_EXIST; | |
96 | } | |
97 | ||
2d48e5f1 MC |
98 | static void sd_cmd_set_sd_cmd(struct rtsx_pcr *pcr, struct mmc_command *cmd) |
99 | { | |
100 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CMD0, 0xFF, | |
101 | SD_CMD_START | cmd->opcode); | |
102 | rtsx_pci_write_be32(pcr, SD_CMD1, cmd->arg); | |
103 | } | |
104 | ||
105 | static void sd_cmd_set_data_len(struct rtsx_pcr *pcr, u16 blocks, u16 blksz) | |
106 | { | |
107 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BLOCK_CNT_L, 0xFF, blocks); | |
108 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BLOCK_CNT_H, 0xFF, blocks >> 8); | |
109 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BYTE_CNT_L, 0xFF, blksz); | |
110 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BYTE_CNT_H, 0xFF, blksz >> 8); | |
111 | } | |
112 | ||
113 | static int sd_response_type(struct mmc_command *cmd) | |
114 | { | |
115 | switch (mmc_resp_type(cmd)) { | |
116 | case MMC_RSP_NONE: | |
117 | return SD_RSP_TYPE_R0; | |
118 | case MMC_RSP_R1: | |
119 | return SD_RSP_TYPE_R1; | |
8c8d0ecb | 120 | case MMC_RSP_R1_NO_CRC: |
2d48e5f1 MC |
121 | return SD_RSP_TYPE_R1 | SD_NO_CHECK_CRC7; |
122 | case MMC_RSP_R1B: | |
123 | return SD_RSP_TYPE_R1b; | |
124 | case MMC_RSP_R2: | |
125 | return SD_RSP_TYPE_R2; | |
126 | case MMC_RSP_R3: | |
127 | return SD_RSP_TYPE_R3; | |
128 | default: | |
129 | return -EINVAL; | |
130 | } | |
131 | } | |
132 | ||
133 | static int sd_status_index(int resp_type) | |
134 | { | |
135 | if (resp_type == SD_RSP_TYPE_R0) | |
136 | return 0; | |
137 | else if (resp_type == SD_RSP_TYPE_R2) | |
138 | return 16; | |
139 | ||
140 | return 5; | |
141 | } | |
6291e715 MC |
142 | /* |
143 | * sd_pre_dma_transfer - do dma_map_sg() or using cookie | |
144 | * | |
145 | * @pre: if called in pre_req() | |
146 | * return: | |
147 | * 0 - do dma_map_sg() | |
148 | * 1 - using cookie | |
149 | */ | |
150 | static int sd_pre_dma_transfer(struct realtek_pci_sdmmc *host, | |
151 | struct mmc_data *data, bool pre) | |
152 | { | |
153 | struct rtsx_pcr *pcr = host->pcr; | |
154 | int read = data->flags & MMC_DATA_READ; | |
155 | int count = 0; | |
156 | int using_cookie = 0; | |
157 | ||
158 | if (!pre && data->host_cookie && data->host_cookie != host->cookie) { | |
159 | dev_err(sdmmc_dev(host), | |
160 | "error: data->host_cookie = %d, host->cookie = %d\n", | |
161 | data->host_cookie, host->cookie); | |
162 | data->host_cookie = 0; | |
163 | } | |
164 | ||
165 | if (pre || data->host_cookie != host->cookie) { | |
166 | count = rtsx_pci_dma_map_sg(pcr, data->sg, data->sg_len, read); | |
167 | } else { | |
168 | count = host->cookie_sg_count; | |
169 | using_cookie = 1; | |
170 | } | |
171 | ||
172 | if (pre) { | |
173 | host->cookie_sg_count = count; | |
174 | if (++host->cookie < 0) | |
175 | host->cookie = 1; | |
176 | data->host_cookie = host->cookie; | |
177 | } else { | |
178 | host->sg_count = count; | |
179 | } | |
180 | ||
181 | return using_cookie; | |
182 | } | |
183 | ||
d3c6aac3 | 184 | static void sdmmc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq) |
6291e715 MC |
185 | { |
186 | struct realtek_pci_sdmmc *host = mmc_priv(mmc); | |
187 | struct mmc_data *data = mrq->data; | |
188 | ||
189 | if (data->host_cookie) { | |
190 | dev_err(sdmmc_dev(host), | |
191 | "error: reset data->host_cookie = %d\n", | |
192 | data->host_cookie); | |
193 | data->host_cookie = 0; | |
194 | } | |
195 | ||
196 | sd_pre_dma_transfer(host, data, true); | |
197 | dev_dbg(sdmmc_dev(host), "pre dma sg: %d\n", host->cookie_sg_count); | |
198 | } | |
199 | ||
200 | static void sdmmc_post_req(struct mmc_host *mmc, struct mmc_request *mrq, | |
201 | int err) | |
202 | { | |
203 | struct realtek_pci_sdmmc *host = mmc_priv(mmc); | |
204 | struct rtsx_pcr *pcr = host->pcr; | |
205 | struct mmc_data *data = mrq->data; | |
206 | int read = data->flags & MMC_DATA_READ; | |
207 | ||
208 | rtsx_pci_dma_unmap_sg(pcr, data->sg, data->sg_len, read); | |
209 | data->host_cookie = 0; | |
210 | } | |
211 | ||
98fcc576 MC |
212 | static void sd_send_cmd_get_rsp(struct realtek_pci_sdmmc *host, |
213 | struct mmc_command *cmd) | |
ff984e57 WW |
214 | { |
215 | struct rtsx_pcr *pcr = host->pcr; | |
216 | u8 cmd_idx = (u8)cmd->opcode; | |
217 | u32 arg = cmd->arg; | |
218 | int err = 0; | |
219 | int timeout = 100; | |
220 | int i; | |
98fcc576 | 221 | u8 *ptr; |
2d48e5f1 MC |
222 | int rsp_type; |
223 | int stat_idx; | |
98fcc576 | 224 | bool clock_toggled = false; |
ff984e57 WW |
225 | |
226 | dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD %d, arg = 0x%08x\n", | |
227 | __func__, cmd_idx, arg); | |
228 | ||
2d48e5f1 MC |
229 | rsp_type = sd_response_type(cmd); |
230 | if (rsp_type < 0) | |
ff984e57 | 231 | goto out; |
2d48e5f1 MC |
232 | |
233 | stat_idx = sd_status_index(rsp_type); | |
ff984e57 WW |
234 | |
235 | if (rsp_type == SD_RSP_TYPE_R1b) | |
27f4bf7d | 236 | timeout = cmd->busy_timeout ? cmd->busy_timeout : 3000; |
ff984e57 WW |
237 | |
238 | if (cmd->opcode == SD_SWITCH_VOLTAGE) { | |
239 | err = rtsx_pci_write_register(pcr, SD_BUS_STAT, | |
240 | 0xFF, SD_CLK_TOGGLE_EN); | |
241 | if (err < 0) | |
242 | goto out; | |
98fcc576 MC |
243 | |
244 | clock_toggled = true; | |
ff984e57 WW |
245 | } |
246 | ||
247 | rtsx_pci_init_cmd(pcr); | |
2d48e5f1 | 248 | sd_cmd_set_sd_cmd(pcr, cmd); |
ff984e57 WW |
249 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF, rsp_type); |
250 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_DATA_SOURCE, | |
251 | 0x01, PINGPONG_BUFFER); | |
252 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER, | |
253 | 0xFF, SD_TM_CMD_RSP | SD_TRANSFER_START); | |
254 | rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER, | |
255 | SD_TRANSFER_END | SD_STAT_IDLE, | |
256 | SD_TRANSFER_END | SD_STAT_IDLE); | |
257 | ||
258 | if (rsp_type == SD_RSP_TYPE_R2) { | |
259 | /* Read data from ping-pong buffer */ | |
260 | for (i = PPBUF_BASE2; i < PPBUF_BASE2 + 16; i++) | |
261 | rtsx_pci_add_cmd(pcr, READ_REG_CMD, (u16)i, 0, 0); | |
ff984e57 WW |
262 | } else if (rsp_type != SD_RSP_TYPE_R0) { |
263 | /* Read data from SD_CMDx registers */ | |
264 | for (i = SD_CMD0; i <= SD_CMD4; i++) | |
265 | rtsx_pci_add_cmd(pcr, READ_REG_CMD, (u16)i, 0, 0); | |
ff984e57 WW |
266 | } |
267 | ||
268 | rtsx_pci_add_cmd(pcr, READ_REG_CMD, SD_STAT1, 0, 0); | |
269 | ||
98fcc576 MC |
270 | err = rtsx_pci_send_cmd(pcr, timeout); |
271 | if (err < 0) { | |
272 | sd_print_debug_regs(host); | |
273 | sd_clear_error(host); | |
274 | dev_dbg(sdmmc_dev(host), | |
275 | "rtsx_pci_send_cmd error (err = %d)\n", err); | |
ff984e57 WW |
276 | goto out; |
277 | } | |
278 | ||
279 | if (rsp_type == SD_RSP_TYPE_R0) { | |
280 | err = 0; | |
281 | goto out; | |
282 | } | |
283 | ||
284 | /* Eliminate returned value of CHECK_REG_CMD */ | |
285 | ptr = rtsx_pci_get_cmd_data(pcr) + 1; | |
286 | ||
287 | /* Check (Start,Transmission) bit of Response */ | |
288 | if ((ptr[0] & 0xC0) != 0) { | |
289 | err = -EILSEQ; | |
290 | dev_dbg(sdmmc_dev(host), "Invalid response bit\n"); | |
291 | goto out; | |
292 | } | |
293 | ||
294 | /* Check CRC7 */ | |
295 | if (!(rsp_type & SD_NO_CHECK_CRC7)) { | |
296 | if (ptr[stat_idx] & SD_CRC7_ERR) { | |
297 | err = -EILSEQ; | |
298 | dev_dbg(sdmmc_dev(host), "CRC7 error\n"); | |
299 | goto out; | |
300 | } | |
301 | } | |
302 | ||
303 | if (rsp_type == SD_RSP_TYPE_R2) { | |
d1419d50 RT |
304 | /* |
305 | * The controller offloads the last byte {CRC-7, end bit 1'b1} | |
306 | * of response type R2. Assign dummy CRC, 0, and end bit to the | |
307 | * byte(ptr[16], goes into the LSB of resp[3] later). | |
308 | */ | |
309 | ptr[16] = 1; | |
310 | ||
ff984e57 WW |
311 | for (i = 0; i < 4; i++) { |
312 | cmd->resp[i] = get_unaligned_be32(ptr + 1 + i * 4); | |
313 | dev_dbg(sdmmc_dev(host), "cmd->resp[%d] = 0x%08x\n", | |
314 | i, cmd->resp[i]); | |
315 | } | |
316 | } else { | |
317 | cmd->resp[0] = get_unaligned_be32(ptr + 1); | |
318 | dev_dbg(sdmmc_dev(host), "cmd->resp[0] = 0x%08x\n", | |
319 | cmd->resp[0]); | |
320 | } | |
321 | ||
322 | out: | |
323 | cmd->error = err; | |
1b8055b4 | 324 | |
98fcc576 MC |
325 | if (err && clock_toggled) |
326 | rtsx_pci_write_register(pcr, SD_BUS_STAT, | |
327 | SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP, 0); | |
ff984e57 WW |
328 | } |
329 | ||
56d1c0d9 MC |
330 | static int sd_read_data(struct realtek_pci_sdmmc *host, struct mmc_command *cmd, |
331 | u16 byte_cnt, u8 *buf, int buf_len, int timeout) | |
332 | { | |
333 | struct rtsx_pcr *pcr = host->pcr; | |
334 | int err; | |
335 | u8 trans_mode; | |
336 | ||
337 | dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD %d, arg = 0x%08x\n", | |
338 | __func__, cmd->opcode, cmd->arg); | |
339 | ||
340 | if (!buf) | |
341 | buf_len = 0; | |
342 | ||
343 | if (cmd->opcode == MMC_SEND_TUNING_BLOCK) | |
344 | trans_mode = SD_TM_AUTO_TUNING; | |
345 | else | |
346 | trans_mode = SD_TM_NORMAL_READ; | |
347 | ||
348 | rtsx_pci_init_cmd(pcr); | |
349 | sd_cmd_set_sd_cmd(pcr, cmd); | |
350 | sd_cmd_set_data_len(pcr, 1, byte_cnt); | |
351 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF, | |
352 | SD_CALCULATE_CRC7 | SD_CHECK_CRC16 | | |
353 | SD_NO_WAIT_BUSY_END | SD_CHECK_CRC7 | SD_RSP_LEN_6); | |
354 | if (trans_mode != SD_TM_AUTO_TUNING) | |
355 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, | |
356 | CARD_DATA_SOURCE, 0x01, PINGPONG_BUFFER); | |
357 | ||
358 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER, | |
359 | 0xFF, trans_mode | SD_TRANSFER_START); | |
360 | rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER, | |
361 | SD_TRANSFER_END, SD_TRANSFER_END); | |
362 | ||
363 | err = rtsx_pci_send_cmd(pcr, timeout); | |
364 | if (err < 0) { | |
365 | sd_print_debug_regs(host); | |
366 | dev_dbg(sdmmc_dev(host), | |
367 | "rtsx_pci_send_cmd fail (err = %d)\n", err); | |
368 | return err; | |
369 | } | |
370 | ||
371 | if (buf && buf_len) { | |
372 | err = rtsx_pci_read_ppbuf(pcr, buf, buf_len); | |
373 | if (err < 0) { | |
374 | dev_dbg(sdmmc_dev(host), | |
375 | "rtsx_pci_read_ppbuf fail (err = %d)\n", err); | |
376 | return err; | |
377 | } | |
378 | } | |
379 | ||
380 | return 0; | |
381 | } | |
382 | ||
383 | static int sd_write_data(struct realtek_pci_sdmmc *host, | |
384 | struct mmc_command *cmd, u16 byte_cnt, u8 *buf, int buf_len, | |
385 | int timeout) | |
386 | { | |
387 | struct rtsx_pcr *pcr = host->pcr; | |
388 | int err; | |
389 | ||
390 | dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD %d, arg = 0x%08x\n", | |
391 | __func__, cmd->opcode, cmd->arg); | |
392 | ||
393 | if (!buf) | |
394 | buf_len = 0; | |
395 | ||
396 | sd_send_cmd_get_rsp(host, cmd); | |
397 | if (cmd->error) | |
398 | return cmd->error; | |
399 | ||
400 | if (buf && buf_len) { | |
401 | err = rtsx_pci_write_ppbuf(pcr, buf, buf_len); | |
402 | if (err < 0) { | |
403 | dev_dbg(sdmmc_dev(host), | |
404 | "rtsx_pci_write_ppbuf fail (err = %d)\n", err); | |
405 | return err; | |
406 | } | |
407 | } | |
408 | ||
409 | rtsx_pci_init_cmd(pcr); | |
410 | sd_cmd_set_data_len(pcr, 1, byte_cnt); | |
411 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF, | |
412 | SD_CALCULATE_CRC7 | SD_CHECK_CRC16 | | |
413 | SD_NO_WAIT_BUSY_END | SD_CHECK_CRC7 | SD_RSP_LEN_0); | |
414 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER, 0xFF, | |
415 | SD_TRANSFER_START | SD_TM_AUTO_WRITE_3); | |
416 | rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER, | |
417 | SD_TRANSFER_END, SD_TRANSFER_END); | |
418 | ||
419 | err = rtsx_pci_send_cmd(pcr, timeout); | |
420 | if (err < 0) { | |
421 | sd_print_debug_regs(host); | |
422 | dev_dbg(sdmmc_dev(host), | |
423 | "rtsx_pci_send_cmd fail (err = %d)\n", err); | |
424 | return err; | |
425 | } | |
426 | ||
427 | return 0; | |
428 | } | |
429 | ||
1dcb3579 MC |
430 | static int sd_read_long_data(struct realtek_pci_sdmmc *host, |
431 | struct mmc_request *mrq) | |
ff984e57 WW |
432 | { |
433 | struct rtsx_pcr *pcr = host->pcr; | |
434 | struct mmc_host *mmc = host->mmc; | |
435 | struct mmc_card *card = mmc->card; | |
1dcb3579 | 436 | struct mmc_command *cmd = mrq->cmd; |
ff984e57 | 437 | struct mmc_data *data = mrq->data; |
71ef1ea4 | 438 | int uhs = mmc_card_uhs(card); |
1dcb3579 | 439 | u8 cfg2 = 0; |
ff984e57 | 440 | int err; |
1dcb3579 | 441 | int resp_type; |
ff984e57 WW |
442 | size_t data_len = data->blksz * data->blocks; |
443 | ||
1dcb3579 MC |
444 | dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD %d, arg = 0x%08x\n", |
445 | __func__, cmd->opcode, cmd->arg); | |
446 | ||
447 | resp_type = sd_response_type(cmd); | |
448 | if (resp_type < 0) | |
449 | return resp_type; | |
ff984e57 WW |
450 | |
451 | if (!uhs) | |
452 | cfg2 |= SD_NO_CHECK_WAIT_CRC_TO; | |
453 | ||
454 | rtsx_pci_init_cmd(pcr); | |
1dcb3579 MC |
455 | sd_cmd_set_sd_cmd(pcr, cmd); |
456 | sd_cmd_set_data_len(pcr, data->blocks, data->blksz); | |
ff984e57 WW |
457 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, IRQSTAT0, |
458 | DMA_DONE_INT, DMA_DONE_INT); | |
459 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC3, | |
1dcb3579 | 460 | 0xFF, (u8)(data_len >> 24)); |
ff984e57 | 461 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC2, |
1dcb3579 | 462 | 0xFF, (u8)(data_len >> 16)); |
ff984e57 | 463 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC1, |
1dcb3579 | 464 | 0xFF, (u8)(data_len >> 8)); |
ff984e57 | 465 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC0, 0xFF, (u8)data_len); |
1dcb3579 MC |
466 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMACTL, |
467 | 0x03 | DMA_PACK_SIZE_MASK, | |
468 | DMA_DIR_FROM_CARD | DMA_EN | DMA_512); | |
469 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_DATA_SOURCE, | |
470 | 0x01, RING_BUFFER); | |
471 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF, cfg2 | resp_type); | |
472 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER, 0xFF, | |
473 | SD_TRANSFER_START | SD_TM_AUTO_READ_2); | |
474 | rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER, | |
475 | SD_TRANSFER_END, SD_TRANSFER_END); | |
476 | rtsx_pci_send_cmd_no_wait(pcr); | |
477 | ||
478 | err = rtsx_pci_dma_transfer(pcr, data->sg, host->sg_count, 1, 10000); | |
479 | if (err < 0) { | |
480 | sd_print_debug_regs(host); | |
481 | sd_clear_error(host); | |
482 | return err; | |
ff984e57 WW |
483 | } |
484 | ||
1dcb3579 MC |
485 | return 0; |
486 | } | |
487 | ||
488 | static int sd_write_long_data(struct realtek_pci_sdmmc *host, | |
489 | struct mmc_request *mrq) | |
490 | { | |
491 | struct rtsx_pcr *pcr = host->pcr; | |
492 | struct mmc_host *mmc = host->mmc; | |
493 | struct mmc_card *card = mmc->card; | |
494 | struct mmc_command *cmd = mrq->cmd; | |
495 | struct mmc_data *data = mrq->data; | |
496 | int uhs = mmc_card_uhs(card); | |
497 | u8 cfg2; | |
498 | int err; | |
499 | size_t data_len = data->blksz * data->blocks; | |
500 | ||
501 | sd_send_cmd_get_rsp(host, cmd); | |
502 | if (cmd->error) | |
503 | return cmd->error; | |
504 | ||
505 | dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD %d, arg = 0x%08x\n", | |
506 | __func__, cmd->opcode, cmd->arg); | |
507 | ||
508 | cfg2 = SD_NO_CALCULATE_CRC7 | SD_CHECK_CRC16 | | |
509 | SD_NO_WAIT_BUSY_END | SD_NO_CHECK_CRC7 | SD_RSP_LEN_0; | |
510 | ||
511 | if (!uhs) | |
512 | cfg2 |= SD_NO_CHECK_WAIT_CRC_TO; | |
513 | ||
514 | rtsx_pci_init_cmd(pcr); | |
515 | sd_cmd_set_data_len(pcr, data->blocks, data->blksz); | |
516 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, IRQSTAT0, | |
517 | DMA_DONE_INT, DMA_DONE_INT); | |
518 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC3, | |
519 | 0xFF, (u8)(data_len >> 24)); | |
520 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC2, | |
521 | 0xFF, (u8)(data_len >> 16)); | |
522 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC1, | |
523 | 0xFF, (u8)(data_len >> 8)); | |
524 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC0, 0xFF, (u8)data_len); | |
525 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMACTL, | |
526 | 0x03 | DMA_PACK_SIZE_MASK, | |
527 | DMA_DIR_TO_CARD | DMA_EN | DMA_512); | |
ff984e57 WW |
528 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_DATA_SOURCE, |
529 | 0x01, RING_BUFFER); | |
38d324df | 530 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF, cfg2); |
ff984e57 | 531 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER, 0xFF, |
1dcb3579 | 532 | SD_TRANSFER_START | SD_TM_AUTO_WRITE_3); |
ff984e57 WW |
533 | rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER, |
534 | SD_TRANSFER_END, SD_TRANSFER_END); | |
ff984e57 | 535 | rtsx_pci_send_cmd_no_wait(pcr); |
1dcb3579 | 536 | err = rtsx_pci_dma_transfer(pcr, data->sg, host->sg_count, 0, 10000); |
c42deffd | 537 | if (err < 0) { |
98fcc576 MC |
538 | sd_clear_error(host); |
539 | return err; | |
c42deffd MC |
540 | } |
541 | ||
98fcc576 | 542 | return 0; |
c42deffd MC |
543 | } |
544 | ||
3ac5e452 TH |
545 | static inline void sd_enable_initial_mode(struct realtek_pci_sdmmc *host) |
546 | { | |
547 | rtsx_pci_write_register(host->pcr, SD_CFG1, | |
548 | SD_CLK_DIVIDE_MASK, SD_CLK_DIVIDE_128); | |
549 | } | |
550 | ||
551 | static inline void sd_disable_initial_mode(struct realtek_pci_sdmmc *host) | |
552 | { | |
553 | rtsx_pci_write_register(host->pcr, SD_CFG1, | |
554 | SD_CLK_DIVIDE_MASK, SD_CLK_DIVIDE_0); | |
555 | } | |
556 | ||
1dcb3579 MC |
557 | static int sd_rw_multi(struct realtek_pci_sdmmc *host, struct mmc_request *mrq) |
558 | { | |
559 | struct mmc_data *data = mrq->data; | |
3ac5e452 | 560 | int err; |
1dcb3579 | 561 | |
be186ad5 MC |
562 | if (host->sg_count < 0) { |
563 | data->error = host->sg_count; | |
564 | dev_dbg(sdmmc_dev(host), "%s: sg_count = %d is invalid\n", | |
565 | __func__, host->sg_count); | |
566 | return data->error; | |
567 | } | |
568 | ||
3ac5e452 TH |
569 | if (data->flags & MMC_DATA_READ) { |
570 | if (host->initial_mode) | |
571 | sd_disable_initial_mode(host); | |
1dcb3579 | 572 | |
3ac5e452 | 573 | err = sd_read_long_data(host, mrq); |
1dcb3579 | 574 | |
3ac5e452 TH |
575 | if (host->initial_mode) |
576 | sd_enable_initial_mode(host); | |
ff984e57 | 577 | |
3ac5e452 TH |
578 | return err; |
579 | } | |
580 | ||
581 | return sd_write_long_data(host, mrq); | |
ff984e57 WW |
582 | } |
583 | ||
584 | static void sd_normal_rw(struct realtek_pci_sdmmc *host, | |
585 | struct mmc_request *mrq) | |
586 | { | |
587 | struct mmc_command *cmd = mrq->cmd; | |
588 | struct mmc_data *data = mrq->data; | |
1dcb3579 | 589 | u8 *buf; |
ff984e57 WW |
590 | |
591 | buf = kzalloc(data->blksz, GFP_NOIO); | |
592 | if (!buf) { | |
593 | cmd->error = -ENOMEM; | |
594 | return; | |
595 | } | |
596 | ||
597 | if (data->flags & MMC_DATA_READ) { | |
598 | if (host->initial_mode) | |
599 | sd_disable_initial_mode(host); | |
600 | ||
1dcb3579 | 601 | cmd->error = sd_read_data(host, cmd, (u16)data->blksz, buf, |
ff984e57 WW |
602 | data->blksz, 200); |
603 | ||
604 | if (host->initial_mode) | |
605 | sd_enable_initial_mode(host); | |
606 | ||
607 | sg_copy_from_buffer(data->sg, data->sg_len, buf, data->blksz); | |
608 | } else { | |
609 | sg_copy_to_buffer(data->sg, data->sg_len, buf, data->blksz); | |
610 | ||
1dcb3579 | 611 | cmd->error = sd_write_data(host, cmd, (u16)data->blksz, buf, |
ff984e57 WW |
612 | data->blksz, 200); |
613 | } | |
614 | ||
615 | kfree(buf); | |
616 | } | |
617 | ||
84d72f9c WW |
618 | static int sd_change_phase(struct realtek_pci_sdmmc *host, |
619 | u8 sample_point, bool rx) | |
ff984e57 WW |
620 | { |
621 | struct rtsx_pcr *pcr = host->pcr; | |
4686392c | 622 | u16 SD_VP_CTL = 0; |
84d72f9c WW |
623 | dev_dbg(sdmmc_dev(host), "%s(%s): sample_point = %d\n", |
624 | __func__, rx ? "RX" : "TX", sample_point); | |
ff984e57 | 625 | |
563be8b6 | 626 | rtsx_pci_write_register(pcr, CLK_CTL, CHANGE_CLK, CHANGE_CLK); |
4686392c RW |
627 | if (rx) { |
628 | SD_VP_CTL = SD_VPRX_CTL; | |
563be8b6 | 629 | rtsx_pci_write_register(pcr, SD_VPRX_CTL, |
630 | PHASE_SELECT_MASK, sample_point); | |
4686392c RW |
631 | } else { |
632 | SD_VP_CTL = SD_VPTX_CTL; | |
563be8b6 | 633 | rtsx_pci_write_register(pcr, SD_VPTX_CTL, |
634 | PHASE_SELECT_MASK, sample_point); | |
4686392c RW |
635 | } |
636 | rtsx_pci_write_register(pcr, SD_VP_CTL, PHASE_NOT_RESET, 0); | |
637 | rtsx_pci_write_register(pcr, SD_VP_CTL, PHASE_NOT_RESET, | |
563be8b6 | 638 | PHASE_NOT_RESET); |
639 | rtsx_pci_write_register(pcr, CLK_CTL, CHANGE_CLK, 0); | |
640 | rtsx_pci_write_register(pcr, SD_CFG1, SD_ASYNC_FIFO_NOT_RST, 0); | |
ff984e57 WW |
641 | |
642 | return 0; | |
643 | } | |
644 | ||
abcc6b29 | 645 | static inline u32 test_phase_bit(u32 phase_map, unsigned int bit) |
ff984e57 | 646 | { |
abcc6b29 MC |
647 | bit %= RTSX_PHASE_MAX; |
648 | return phase_map & (1 << bit); | |
649 | } | |
ff984e57 | 650 | |
abcc6b29 MC |
651 | static int sd_get_phase_len(u32 phase_map, unsigned int start_bit) |
652 | { | |
653 | int i; | |
ff984e57 | 654 | |
abcc6b29 MC |
655 | for (i = 0; i < RTSX_PHASE_MAX; i++) { |
656 | if (test_phase_bit(phase_map, start_bit + i) == 0) | |
657 | return i; | |
ff984e57 | 658 | } |
abcc6b29 MC |
659 | return RTSX_PHASE_MAX; |
660 | } | |
ff984e57 | 661 | |
abcc6b29 MC |
662 | static u8 sd_search_final_phase(struct realtek_pci_sdmmc *host, u32 phase_map) |
663 | { | |
664 | int start = 0, len = 0; | |
665 | int start_final = 0, len_final = 0; | |
666 | u8 final_phase = 0xFF; | |
667 | ||
668 | if (phase_map == 0) { | |
669 | dev_err(sdmmc_dev(host), "phase error: [map:%x]\n", phase_map); | |
670 | return final_phase; | |
ff984e57 WW |
671 | } |
672 | ||
abcc6b29 MC |
673 | while (start < RTSX_PHASE_MAX) { |
674 | len = sd_get_phase_len(phase_map, start); | |
675 | if (len_final < len) { | |
676 | start_final = start; | |
677 | len_final = len; | |
ff984e57 | 678 | } |
abcc6b29 | 679 | start += len ? len : 1; |
ff984e57 WW |
680 | } |
681 | ||
abcc6b29 MC |
682 | final_phase = (start_final + len_final / 2) % RTSX_PHASE_MAX; |
683 | dev_dbg(sdmmc_dev(host), "phase: [map:%x] [maxlen:%d] [final:%d]\n", | |
684 | phase_map, len_final, final_phase); | |
685 | ||
ff984e57 WW |
686 | return final_phase; |
687 | } | |
688 | ||
689 | static void sd_wait_data_idle(struct realtek_pci_sdmmc *host) | |
690 | { | |
679209b3 | 691 | int i; |
ff984e57 WW |
692 | u8 val = 0; |
693 | ||
694 | for (i = 0; i < 100; i++) { | |
679209b3 | 695 | rtsx_pci_read_register(host->pcr, SD_DATA_STATE, &val); |
ff984e57 WW |
696 | if (val & SD_DATA_IDLE) |
697 | return; | |
698 | ||
699 | udelay(100); | |
700 | } | |
701 | } | |
702 | ||
703 | static int sd_tuning_rx_cmd(struct realtek_pci_sdmmc *host, | |
704 | u8 opcode, u8 sample_point) | |
705 | { | |
706 | int err; | |
c7836d15 | 707 | struct mmc_command cmd = {}; |
563be8b6 | 708 | struct rtsx_pcr *pcr = host->pcr; |
ff984e57 | 709 | |
563be8b6 | 710 | sd_change_phase(host, sample_point, true); |
711 | ||
712 | rtsx_pci_write_register(pcr, SD_CFG3, SD_RSP_80CLK_TIMEOUT_EN, | |
713 | SD_RSP_80CLK_TIMEOUT_EN); | |
ff984e57 | 714 | |
1dcb3579 MC |
715 | cmd.opcode = opcode; |
716 | err = sd_read_data(host, &cmd, 0x40, NULL, 0, 100); | |
ff984e57 WW |
717 | if (err < 0) { |
718 | /* Wait till SD DATA IDLE */ | |
719 | sd_wait_data_idle(host); | |
720 | sd_clear_error(host); | |
563be8b6 | 721 | rtsx_pci_write_register(pcr, SD_CFG3, |
722 | SD_RSP_80CLK_TIMEOUT_EN, 0); | |
ff984e57 WW |
723 | return err; |
724 | } | |
725 | ||
563be8b6 | 726 | rtsx_pci_write_register(pcr, SD_CFG3, SD_RSP_80CLK_TIMEOUT_EN, 0); |
ff984e57 WW |
727 | return 0; |
728 | } | |
729 | ||
730 | static int sd_tuning_phase(struct realtek_pci_sdmmc *host, | |
731 | u8 opcode, u32 *phase_map) | |
732 | { | |
733 | int err, i; | |
734 | u32 raw_phase_map = 0; | |
735 | ||
abcc6b29 | 736 | for (i = 0; i < RTSX_PHASE_MAX; i++) { |
ff984e57 WW |
737 | err = sd_tuning_rx_cmd(host, opcode, (u8)i); |
738 | if (err == 0) | |
739 | raw_phase_map |= 1 << i; | |
740 | } | |
741 | ||
742 | if (phase_map) | |
743 | *phase_map = raw_phase_map; | |
744 | ||
745 | return 0; | |
746 | } | |
747 | ||
748 | static int sd_tuning_rx(struct realtek_pci_sdmmc *host, u8 opcode) | |
749 | { | |
750 | int err, i; | |
751 | u32 raw_phase_map[RX_TUNING_CNT] = {0}, phase_map; | |
752 | u8 final_phase; | |
753 | ||
754 | for (i = 0; i < RX_TUNING_CNT; i++) { | |
755 | err = sd_tuning_phase(host, opcode, &(raw_phase_map[i])); | |
756 | if (err < 0) | |
757 | return err; | |
758 | ||
759 | if (raw_phase_map[i] == 0) | |
760 | break; | |
761 | } | |
762 | ||
763 | phase_map = 0xFFFFFFFF; | |
764 | for (i = 0; i < RX_TUNING_CNT; i++) { | |
765 | dev_dbg(sdmmc_dev(host), "RX raw_phase_map[%d] = 0x%08x\n", | |
766 | i, raw_phase_map[i]); | |
767 | phase_map &= raw_phase_map[i]; | |
768 | } | |
769 | dev_dbg(sdmmc_dev(host), "RX phase_map = 0x%08x\n", phase_map); | |
770 | ||
771 | if (phase_map) { | |
772 | final_phase = sd_search_final_phase(host, phase_map); | |
773 | if (final_phase == 0xFF) | |
774 | return -EINVAL; | |
775 | ||
84d72f9c | 776 | err = sd_change_phase(host, final_phase, true); |
ff984e57 WW |
777 | if (err < 0) |
778 | return err; | |
779 | } else { | |
780 | return -EINVAL; | |
781 | } | |
782 | ||
783 | return 0; | |
784 | } | |
785 | ||
1dcb3579 MC |
786 | static inline int sdio_extblock_cmd(struct mmc_command *cmd, |
787 | struct mmc_data *data) | |
788 | { | |
789 | return (cmd->opcode == SD_IO_RW_EXTENDED) && (data->blksz == 512); | |
790 | } | |
791 | ||
6291e715 | 792 | static inline int sd_rw_cmd(struct mmc_command *cmd) |
ff984e57 | 793 | { |
6291e715 MC |
794 | return mmc_op_multi(cmd->opcode) || |
795 | (cmd->opcode == MMC_READ_SINGLE_BLOCK) || | |
796 | (cmd->opcode == MMC_WRITE_BLOCK); | |
797 | } | |
798 | ||
799 | static void sd_request(struct work_struct *work) | |
800 | { | |
801 | struct realtek_pci_sdmmc *host = container_of(work, | |
802 | struct realtek_pci_sdmmc, work); | |
ff984e57 | 803 | struct rtsx_pcr *pcr = host->pcr; |
6291e715 MC |
804 | |
805 | struct mmc_host *mmc = host->mmc; | |
806 | struct mmc_request *mrq = host->mrq; | |
ff984e57 WW |
807 | struct mmc_command *cmd = mrq->cmd; |
808 | struct mmc_data *data = mrq->data; | |
72085bdc | 809 | struct device *dev = &host->pdev->dev; |
6291e715 | 810 | |
ff984e57 | 811 | unsigned int data_size = 0; |
c3481955 | 812 | int err; |
ff984e57 | 813 | |
b22217f9 | 814 | if (host->eject || !sd_get_cd_int(host)) { |
ff984e57 WW |
815 | cmd->error = -ENOMEDIUM; |
816 | goto finish; | |
817 | } | |
818 | ||
c3481955 WW |
819 | err = rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD); |
820 | if (err) { | |
821 | cmd->error = err; | |
822 | goto finish; | |
823 | } | |
824 | ||
98fcc576 MC |
825 | mutex_lock(&pcr->pcr_mutex); |
826 | ||
ff984e57 WW |
827 | rtsx_pci_start_run(pcr); |
828 | ||
829 | rtsx_pci_switch_clock(pcr, host->clock, host->ssc_depth, | |
830 | host->initial_mode, host->double_clk, host->vpclk); | |
831 | rtsx_pci_write_register(pcr, CARD_SELECT, 0x07, SD_MOD_SEL); | |
832 | rtsx_pci_write_register(pcr, CARD_SHARE_MODE, | |
833 | CARD_SHARE_MASK, CARD_SHARE_48_SD); | |
834 | ||
98fcc576 MC |
835 | mutex_lock(&host->host_mutex); |
836 | host->mrq = mrq; | |
837 | mutex_unlock(&host->host_mutex); | |
838 | ||
ff984e57 WW |
839 | if (mrq->data) |
840 | data_size = data->blocks * data->blksz; | |
841 | ||
1dcb3579 | 842 | if (!data_size) { |
98fcc576 | 843 | sd_send_cmd_get_rsp(host, cmd); |
1dcb3579 MC |
844 | } else if (sd_rw_cmd(cmd) || sdio_extblock_cmd(cmd, data)) { |
845 | cmd->error = sd_rw_multi(host, mrq); | |
846 | if (!host->using_cookie) | |
847 | sdmmc_post_req(host->mmc, host->mrq, 0); | |
ff984e57 | 848 | |
1dcb3579 MC |
849 | if (mmc_op_multi(cmd->opcode) && mrq->stop) |
850 | sd_send_cmd_get_rsp(host, mrq->stop); | |
ff984e57 WW |
851 | } else { |
852 | sd_normal_rw(host, mrq); | |
853 | } | |
98fcc576 MC |
854 | |
855 | if (mrq->data) { | |
856 | if (cmd->error || data->error) | |
857 | data->bytes_xfered = 0; | |
858 | else | |
859 | data->bytes_xfered = data->blocks * data->blksz; | |
860 | } | |
861 | ||
862 | mutex_unlock(&pcr->pcr_mutex); | |
ff984e57 WW |
863 | |
864 | finish: | |
1dcb3579 MC |
865 | if (cmd->error) { |
866 | dev_dbg(sdmmc_dev(host), "CMD %d 0x%08x error(%d)\n", | |
867 | cmd->opcode, cmd->arg, cmd->error); | |
868 | } | |
98fcc576 MC |
869 | |
870 | mutex_lock(&host->host_mutex); | |
871 | host->mrq = NULL; | |
872 | mutex_unlock(&host->host_mutex); | |
873 | ||
874 | mmc_request_done(mmc, mrq); | |
ff984e57 WW |
875 | } |
876 | ||
6291e715 MC |
877 | static void sdmmc_request(struct mmc_host *mmc, struct mmc_request *mrq) |
878 | { | |
879 | struct realtek_pci_sdmmc *host = mmc_priv(mmc); | |
880 | struct mmc_data *data = mrq->data; | |
881 | ||
882 | mutex_lock(&host->host_mutex); | |
883 | host->mrq = mrq; | |
884 | mutex_unlock(&host->host_mutex); | |
885 | ||
1dcb3579 | 886 | if (sd_rw_cmd(mrq->cmd) || sdio_extblock_cmd(mrq->cmd, data)) |
6291e715 MC |
887 | host->using_cookie = sd_pre_dma_transfer(host, data, false); |
888 | ||
6ea62579 | 889 | schedule_work(&host->work); |
6291e715 MC |
890 | } |
891 | ||
ff984e57 WW |
892 | static int sd_set_bus_width(struct realtek_pci_sdmmc *host, |
893 | unsigned char bus_width) | |
894 | { | |
895 | int err = 0; | |
896 | u8 width[] = { | |
897 | [MMC_BUS_WIDTH_1] = SD_BUS_WIDTH_1BIT, | |
898 | [MMC_BUS_WIDTH_4] = SD_BUS_WIDTH_4BIT, | |
899 | [MMC_BUS_WIDTH_8] = SD_BUS_WIDTH_8BIT, | |
900 | }; | |
901 | ||
902 | if (bus_width <= MMC_BUS_WIDTH_8) | |
903 | err = rtsx_pci_write_register(host->pcr, SD_CFG1, | |
904 | 0x03, width[bus_width]); | |
905 | ||
906 | return err; | |
907 | } | |
908 | ||
909 | static int sd_power_on(struct realtek_pci_sdmmc *host) | |
910 | { | |
911 | struct rtsx_pcr *pcr = host->pcr; | |
9ff43c7b | 912 | struct mmc_host *mmc = host->mmc; |
ff984e57 | 913 | int err; |
9ff43c7b | 914 | u32 val; |
6b7b58f4 | 915 | u8 test_mode; |
ff984e57 | 916 | |
d88691be WW |
917 | if (host->power_state == SDMMC_POWER_ON) |
918 | return 0; | |
919 | ||
12b1c5ed RW |
920 | msleep(100); |
921 | ||
ff984e57 WW |
922 | rtsx_pci_init_cmd(pcr); |
923 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_SELECT, 0x07, SD_MOD_SEL); | |
924 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_SHARE_MODE, | |
925 | CARD_SHARE_MASK, CARD_SHARE_48_SD); | |
926 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_EN, | |
927 | SD_CLK_EN, SD_CLK_EN); | |
928 | err = rtsx_pci_send_cmd(pcr, 100); | |
929 | if (err < 0) | |
930 | return err; | |
931 | ||
932 | err = rtsx_pci_card_pull_ctl_enable(pcr, RTSX_SD_CARD); | |
933 | if (err < 0) | |
934 | return err; | |
935 | ||
936 | err = rtsx_pci_card_power_on(pcr, RTSX_SD_CARD); | |
937 | if (err < 0) | |
938 | return err; | |
939 | ||
940 | err = rtsx_pci_write_register(pcr, CARD_OE, SD_OUTPUT_EN, SD_OUTPUT_EN); | |
941 | if (err < 0) | |
942 | return err; | |
943 | ||
9ff43c7b | 944 | if (PCI_PID(pcr) == PID_5261) { |
6b7b58f4 RF |
945 | /* |
946 | * If test mode is set switch to SD Express mandatorily, | |
947 | * this is only for factory testing. | |
948 | */ | |
949 | rtsx_pci_read_register(pcr, RTS5261_FW_CFG_INFO0, &test_mode); | |
950 | if (test_mode & RTS5261_FW_EXPRESS_TEST_MASK) { | |
951 | sdmmc_init_sd_express(mmc, NULL); | |
952 | return 0; | |
953 | } | |
9ff43c7b RF |
954 | if (pcr->extra_caps & EXTRA_CAPS_SD_EXPRESS) |
955 | mmc->caps2 |= MMC_CAP2_SD_EXP | MMC_CAP2_SD_EXP_1_2V; | |
956 | /* | |
957 | * HW read wp status when resuming from S3/S4, | |
958 | * and then picks SD legacy interface if it's set | |
959 | * in read-only mode. | |
960 | */ | |
961 | val = rtsx_pci_readl(pcr, RTSX_BIPR); | |
962 | if (val & SD_WRITE_PROTECT) { | |
963 | pcr->extra_caps &= ~EXTRA_CAPS_SD_EXPRESS; | |
964 | mmc->caps2 &= ~(MMC_CAP2_SD_EXP | MMC_CAP2_SD_EXP_1_2V); | |
965 | } | |
966 | } | |
967 | ||
d88691be | 968 | host->power_state = SDMMC_POWER_ON; |
ff984e57 WW |
969 | return 0; |
970 | } | |
971 | ||
972 | static int sd_power_off(struct realtek_pci_sdmmc *host) | |
973 | { | |
974 | struct rtsx_pcr *pcr = host->pcr; | |
975 | int err; | |
976 | ||
d88691be WW |
977 | host->power_state = SDMMC_POWER_OFF; |
978 | ||
ff984e57 WW |
979 | rtsx_pci_init_cmd(pcr); |
980 | ||
981 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_EN, SD_CLK_EN, 0); | |
982 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_OE, SD_OUTPUT_EN, 0); | |
983 | ||
984 | err = rtsx_pci_send_cmd(pcr, 100); | |
985 | if (err < 0) | |
986 | return err; | |
987 | ||
988 | err = rtsx_pci_card_power_off(pcr, RTSX_SD_CARD); | |
989 | if (err < 0) | |
990 | return err; | |
991 | ||
992 | return rtsx_pci_card_pull_ctl_disable(pcr, RTSX_SD_CARD); | |
993 | } | |
994 | ||
995 | static int sd_set_power_mode(struct realtek_pci_sdmmc *host, | |
996 | unsigned char power_mode) | |
997 | { | |
998 | int err; | |
999 | ||
1000 | if (power_mode == MMC_POWER_OFF) | |
1001 | err = sd_power_off(host); | |
1002 | else | |
1003 | err = sd_power_on(host); | |
1004 | ||
1005 | return err; | |
1006 | } | |
1007 | ||
84d72f9c | 1008 | static int sd_set_timing(struct realtek_pci_sdmmc *host, unsigned char timing) |
ff984e57 WW |
1009 | { |
1010 | struct rtsx_pcr *pcr = host->pcr; | |
1011 | int err = 0; | |
1012 | ||
ff984e57 WW |
1013 | rtsx_pci_init_cmd(pcr); |
1014 | ||
1015 | switch (timing) { | |
1016 | case MMC_TIMING_UHS_SDR104: | |
1017 | case MMC_TIMING_UHS_SDR50: | |
1018 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1, | |
1019 | 0x0C | SD_ASYNC_FIFO_NOT_RST, | |
1020 | SD_30_MODE | SD_ASYNC_FIFO_NOT_RST); | |
1021 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, | |
1022 | CLK_LOW_FREQ, CLK_LOW_FREQ); | |
1023 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF, | |
1024 | CRC_VAR_CLK0 | SD30_FIX_CLK | SAMPLE_VAR_CLK1); | |
1025 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0); | |
1026 | break; | |
1027 | ||
1a0ae377 | 1028 | case MMC_TIMING_MMC_DDR52: |
ff984e57 | 1029 | case MMC_TIMING_UHS_DDR50: |
ff984e57 WW |
1030 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1, |
1031 | 0x0C | SD_ASYNC_FIFO_NOT_RST, | |
1032 | SD_DDR_MODE | SD_ASYNC_FIFO_NOT_RST); | |
1033 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, | |
1034 | CLK_LOW_FREQ, CLK_LOW_FREQ); | |
1035 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF, | |
1036 | CRC_VAR_CLK0 | SD30_FIX_CLK | SAMPLE_VAR_CLK1); | |
1037 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0); | |
1038 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_PUSH_POINT_CTL, | |
1039 | DDR_VAR_TX_CMD_DAT, DDR_VAR_TX_CMD_DAT); | |
1040 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_SAMPLE_POINT_CTL, | |
1041 | DDR_VAR_RX_DAT | DDR_VAR_RX_CMD, | |
1042 | DDR_VAR_RX_DAT | DDR_VAR_RX_CMD); | |
1043 | break; | |
1044 | ||
1045 | case MMC_TIMING_MMC_HS: | |
1046 | case MMC_TIMING_SD_HS: | |
1047 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1, | |
1048 | 0x0C, SD_20_MODE); | |
1049 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, | |
1050 | CLK_LOW_FREQ, CLK_LOW_FREQ); | |
1051 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF, | |
1052 | CRC_FIX_CLK | SD30_VAR_CLK0 | SAMPLE_VAR_CLK1); | |
1053 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0); | |
1054 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_PUSH_POINT_CTL, | |
1055 | SD20_TX_SEL_MASK, SD20_TX_14_AHEAD); | |
1056 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_SAMPLE_POINT_CTL, | |
1057 | SD20_RX_SEL_MASK, SD20_RX_14_DELAY); | |
1058 | break; | |
1059 | ||
1060 | default: | |
1061 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, | |
1062 | SD_CFG1, 0x0C, SD_20_MODE); | |
1063 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, | |
1064 | CLK_LOW_FREQ, CLK_LOW_FREQ); | |
1065 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF, | |
1066 | CRC_FIX_CLK | SD30_VAR_CLK0 | SAMPLE_VAR_CLK1); | |
1067 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0); | |
1068 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, | |
1069 | SD_PUSH_POINT_CTL, 0xFF, 0); | |
1070 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_SAMPLE_POINT_CTL, | |
1071 | SD20_RX_SEL_MASK, SD20_RX_POS_EDGE); | |
1072 | break; | |
1073 | } | |
1074 | ||
1075 | err = rtsx_pci_send_cmd(pcr, 100); | |
1076 | ||
1077 | return err; | |
1078 | } | |
1079 | ||
1080 | static void sdmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) | |
1081 | { | |
1082 | struct realtek_pci_sdmmc *host = mmc_priv(mmc); | |
1083 | struct rtsx_pcr *pcr = host->pcr; | |
72085bdc | 1084 | struct device *dev = &host->pdev->dev; |
ff984e57 WW |
1085 | |
1086 | if (host->eject) | |
1087 | return; | |
1088 | ||
c3481955 WW |
1089 | if (rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD)) |
1090 | return; | |
1091 | ||
ff984e57 WW |
1092 | mutex_lock(&pcr->pcr_mutex); |
1093 | ||
1094 | rtsx_pci_start_run(pcr); | |
1095 | ||
1096 | sd_set_bus_width(host, ios->bus_width); | |
1097 | sd_set_power_mode(host, ios->power_mode); | |
84d72f9c | 1098 | sd_set_timing(host, ios->timing); |
ff984e57 WW |
1099 | |
1100 | host->vpclk = false; | |
1101 | host->double_clk = true; | |
1102 | ||
1103 | switch (ios->timing) { | |
1104 | case MMC_TIMING_UHS_SDR104: | |
1105 | case MMC_TIMING_UHS_SDR50: | |
1106 | host->ssc_depth = RTSX_SSC_DEPTH_2M; | |
1107 | host->vpclk = true; | |
1108 | host->double_clk = false; | |
1109 | break; | |
1a0ae377 | 1110 | case MMC_TIMING_MMC_DDR52: |
ff984e57 WW |
1111 | case MMC_TIMING_UHS_DDR50: |
1112 | case MMC_TIMING_UHS_SDR25: | |
1113 | host->ssc_depth = RTSX_SSC_DEPTH_1M; | |
1114 | break; | |
1115 | default: | |
1116 | host->ssc_depth = RTSX_SSC_DEPTH_500K; | |
1117 | break; | |
1118 | } | |
1119 | ||
1120 | host->initial_mode = (ios->clock <= 1000000) ? true : false; | |
1121 | ||
1122 | host->clock = ios->clock; | |
1123 | rtsx_pci_switch_clock(pcr, ios->clock, host->ssc_depth, | |
1124 | host->initial_mode, host->double_clk, host->vpclk); | |
1125 | ||
1126 | mutex_unlock(&pcr->pcr_mutex); | |
1127 | } | |
1128 | ||
1129 | static int sdmmc_get_ro(struct mmc_host *mmc) | |
1130 | { | |
1131 | struct realtek_pci_sdmmc *host = mmc_priv(mmc); | |
1132 | struct rtsx_pcr *pcr = host->pcr; | |
72085bdc | 1133 | struct device *dev = &host->pdev->dev; |
ff984e57 WW |
1134 | int ro = 0; |
1135 | u32 val; | |
1136 | ||
1137 | if (host->eject) | |
1138 | return -ENOMEDIUM; | |
1139 | ||
1140 | mutex_lock(&pcr->pcr_mutex); | |
1141 | ||
1142 | rtsx_pci_start_run(pcr); | |
1143 | ||
1144 | /* Check SD mechanical write-protect switch */ | |
1145 | val = rtsx_pci_readl(pcr, RTSX_BIPR); | |
1146 | dev_dbg(sdmmc_dev(host), "%s: RTSX_BIPR = 0x%08x\n", __func__, val); | |
1147 | if (val & SD_WRITE_PROTECT) | |
1148 | ro = 1; | |
1149 | ||
1150 | mutex_unlock(&pcr->pcr_mutex); | |
1151 | ||
1152 | return ro; | |
1153 | } | |
1154 | ||
1155 | static int sdmmc_get_cd(struct mmc_host *mmc) | |
1156 | { | |
1157 | struct realtek_pci_sdmmc *host = mmc_priv(mmc); | |
1158 | struct rtsx_pcr *pcr = host->pcr; | |
72085bdc | 1159 | struct device *dev = &host->pdev->dev; |
ff984e57 WW |
1160 | int cd = 0; |
1161 | u32 val; | |
1162 | ||
1163 | if (host->eject) | |
b22217f9 | 1164 | return cd; |
ff984e57 WW |
1165 | |
1166 | mutex_lock(&pcr->pcr_mutex); | |
1167 | ||
1168 | rtsx_pci_start_run(pcr); | |
1169 | ||
1170 | /* Check SD card detect */ | |
1171 | val = rtsx_pci_card_exist(pcr); | |
1172 | dev_dbg(sdmmc_dev(host), "%s: RTSX_BIPR = 0x%08x\n", __func__, val); | |
1173 | if (val & SD_EXIST) | |
1174 | cd = 1; | |
1175 | ||
1176 | mutex_unlock(&pcr->pcr_mutex); | |
1177 | ||
1178 | return cd; | |
1179 | } | |
1180 | ||
1181 | static int sd_wait_voltage_stable_1(struct realtek_pci_sdmmc *host) | |
1182 | { | |
1183 | struct rtsx_pcr *pcr = host->pcr; | |
1184 | int err; | |
1185 | u8 stat; | |
1186 | ||
1187 | /* Reference to Signal Voltage Switch Sequence in SD spec. | |
1188 | * Wait for a period of time so that the card can drive SD_CMD and | |
1189 | * SD_DAT[3:0] to low after sending back CMD11 response. | |
1190 | */ | |
1191 | mdelay(1); | |
1192 | ||
1193 | /* SD_CMD, SD_DAT[3:0] should be driven to low by card; | |
1194 | * If either one of SD_CMD,SD_DAT[3:0] is not low, | |
1195 | * abort the voltage switch sequence; | |
1196 | */ | |
1197 | err = rtsx_pci_read_register(pcr, SD_BUS_STAT, &stat); | |
1198 | if (err < 0) | |
1199 | return err; | |
1200 | ||
1201 | if (stat & (SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS | | |
1202 | SD_DAT1_STATUS | SD_DAT0_STATUS)) | |
1203 | return -EINVAL; | |
1204 | ||
1205 | /* Stop toggle SD clock */ | |
1206 | err = rtsx_pci_write_register(pcr, SD_BUS_STAT, | |
1207 | 0xFF, SD_CLK_FORCE_STOP); | |
1208 | if (err < 0) | |
1209 | return err; | |
1210 | ||
1211 | return 0; | |
1212 | } | |
1213 | ||
1214 | static int sd_wait_voltage_stable_2(struct realtek_pci_sdmmc *host) | |
1215 | { | |
1216 | struct rtsx_pcr *pcr = host->pcr; | |
1217 | int err; | |
1218 | u8 stat, mask, val; | |
1219 | ||
1220 | /* Wait 1.8V output of voltage regulator in card stable */ | |
1221 | msleep(50); | |
1222 | ||
1223 | /* Toggle SD clock again */ | |
1224 | err = rtsx_pci_write_register(pcr, SD_BUS_STAT, 0xFF, SD_CLK_TOGGLE_EN); | |
1225 | if (err < 0) | |
1226 | return err; | |
1227 | ||
1228 | /* Wait for a period of time so that the card can drive | |
1229 | * SD_DAT[3:0] to high at 1.8V | |
1230 | */ | |
1231 | msleep(20); | |
1232 | ||
1233 | /* SD_CMD, SD_DAT[3:0] should be pulled high by host */ | |
1234 | err = rtsx_pci_read_register(pcr, SD_BUS_STAT, &stat); | |
1235 | if (err < 0) | |
1236 | return err; | |
1237 | ||
1238 | mask = SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS | | |
1239 | SD_DAT1_STATUS | SD_DAT0_STATUS; | |
1240 | val = SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS | | |
1241 | SD_DAT1_STATUS | SD_DAT0_STATUS; | |
1242 | if ((stat & mask) != val) { | |
1243 | dev_dbg(sdmmc_dev(host), | |
1244 | "%s: SD_BUS_STAT = 0x%x\n", __func__, stat); | |
1245 | rtsx_pci_write_register(pcr, SD_BUS_STAT, | |
1246 | SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP, 0); | |
1247 | rtsx_pci_write_register(pcr, CARD_CLK_EN, 0xFF, 0); | |
1248 | return -EINVAL; | |
1249 | } | |
1250 | ||
1251 | return 0; | |
1252 | } | |
1253 | ||
ff984e57 WW |
1254 | static int sdmmc_switch_voltage(struct mmc_host *mmc, struct mmc_ios *ios) |
1255 | { | |
1256 | struct realtek_pci_sdmmc *host = mmc_priv(mmc); | |
1257 | struct rtsx_pcr *pcr = host->pcr; | |
72085bdc | 1258 | struct device *dev = &host->pdev->dev; |
ff984e57 WW |
1259 | int err = 0; |
1260 | u8 voltage; | |
1261 | ||
1262 | dev_dbg(sdmmc_dev(host), "%s: signal_voltage = %d\n", | |
1263 | __func__, ios->signal_voltage); | |
1264 | ||
1265 | if (host->eject) | |
1266 | return -ENOMEDIUM; | |
1267 | ||
c3481955 WW |
1268 | err = rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD); |
1269 | if (err) | |
1270 | return err; | |
1271 | ||
ff984e57 WW |
1272 | mutex_lock(&pcr->pcr_mutex); |
1273 | ||
1274 | rtsx_pci_start_run(pcr); | |
1275 | ||
1276 | if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) | |
ef85e736 | 1277 | voltage = OUTPUT_3V3; |
ff984e57 | 1278 | else |
ef85e736 | 1279 | voltage = OUTPUT_1V8; |
ff984e57 | 1280 | |
ef85e736 | 1281 | if (voltage == OUTPUT_1V8) { |
ff984e57 WW |
1282 | err = sd_wait_voltage_stable_1(host); |
1283 | if (err < 0) | |
1284 | goto out; | |
1285 | } | |
1286 | ||
ef85e736 | 1287 | err = rtsx_pci_switch_output_voltage(pcr, voltage); |
ff984e57 WW |
1288 | if (err < 0) |
1289 | goto out; | |
1290 | ||
ef85e736 | 1291 | if (voltage == OUTPUT_1V8) { |
ff984e57 WW |
1292 | err = sd_wait_voltage_stable_2(host); |
1293 | if (err < 0) | |
1294 | goto out; | |
1295 | } | |
1296 | ||
1b8055b4 | 1297 | out: |
ff984e57 WW |
1298 | /* Stop toggle SD clock in idle */ |
1299 | err = rtsx_pci_write_register(pcr, SD_BUS_STAT, | |
1300 | SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP, 0); | |
1301 | ||
ff984e57 WW |
1302 | mutex_unlock(&pcr->pcr_mutex); |
1303 | ||
1304 | return err; | |
1305 | } | |
1306 | ||
1307 | static int sdmmc_execute_tuning(struct mmc_host *mmc, u32 opcode) | |
1308 | { | |
1309 | struct realtek_pci_sdmmc *host = mmc_priv(mmc); | |
1310 | struct rtsx_pcr *pcr = host->pcr; | |
72085bdc | 1311 | struct device *dev = &host->pdev->dev; |
ff984e57 WW |
1312 | int err = 0; |
1313 | ||
1314 | if (host->eject) | |
1315 | return -ENOMEDIUM; | |
1316 | ||
c3481955 WW |
1317 | err = rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD); |
1318 | if (err) | |
1319 | return err; | |
1320 | ||
ff984e57 WW |
1321 | mutex_lock(&pcr->pcr_mutex); |
1322 | ||
1323 | rtsx_pci_start_run(pcr); | |
1324 | ||
84d72f9c WW |
1325 | /* Set initial TX phase */ |
1326 | switch (mmc->ios.timing) { | |
1327 | case MMC_TIMING_UHS_SDR104: | |
1328 | err = sd_change_phase(host, SDR104_TX_PHASE(pcr), false); | |
1329 | break; | |
1330 | ||
1331 | case MMC_TIMING_UHS_SDR50: | |
1332 | err = sd_change_phase(host, SDR50_TX_PHASE(pcr), false); | |
1333 | break; | |
1334 | ||
1335 | case MMC_TIMING_UHS_DDR50: | |
1336 | err = sd_change_phase(host, DDR50_TX_PHASE(pcr), false); | |
1337 | break; | |
1338 | ||
1339 | default: | |
1340 | err = 0; | |
1341 | } | |
ff984e57 | 1342 | |
84d72f9c WW |
1343 | if (err) |
1344 | goto out; | |
1345 | ||
1346 | /* Tuning RX phase */ | |
1347 | if ((mmc->ios.timing == MMC_TIMING_UHS_SDR104) || | |
1348 | (mmc->ios.timing == MMC_TIMING_UHS_SDR50)) | |
1349 | err = sd_tuning_rx(host, opcode); | |
1350 | else if (mmc->ios.timing == MMC_TIMING_UHS_DDR50) | |
1351 | err = sd_change_phase(host, DDR50_RX_PHASE(pcr), true); | |
1352 | ||
1353 | out: | |
ff984e57 WW |
1354 | mutex_unlock(&pcr->pcr_mutex); |
1355 | ||
1356 | return err; | |
1357 | } | |
1358 | ||
9ff43c7b RF |
1359 | static int sdmmc_init_sd_express(struct mmc_host *mmc, struct mmc_ios *ios) |
1360 | { | |
1361 | u32 relink_time; | |
1362 | struct realtek_pci_sdmmc *host = mmc_priv(mmc); | |
1363 | struct rtsx_pcr *pcr = host->pcr; | |
1364 | ||
1365 | /* Set relink_time for changing to PCIe card */ | |
1366 | relink_time = 0x8FFF; | |
1367 | ||
1368 | rtsx_pci_write_register(pcr, 0xFF01, 0xFF, relink_time); | |
1369 | rtsx_pci_write_register(pcr, 0xFF02, 0xFF, relink_time >> 8); | |
1370 | rtsx_pci_write_register(pcr, 0xFF03, 0x01, relink_time >> 16); | |
1371 | ||
1372 | rtsx_pci_write_register(pcr, PETXCFG, 0x80, 0x80); | |
1373 | rtsx_pci_write_register(pcr, LDO_VCC_CFG0, | |
1374 | RTS5261_LDO1_OCP_THD_MASK, | |
1375 | pcr->option.sd_800mA_ocp_thd); | |
1376 | ||
1377 | if (pcr->ops->disable_auto_blink) | |
1378 | pcr->ops->disable_auto_blink(pcr); | |
1379 | ||
1380 | /* For PCIe/NVMe mode can't enter delink issue */ | |
1381 | pcr->hw_param.interrupt_en &= ~(SD_INT_EN); | |
1382 | rtsx_pci_writel(pcr, RTSX_BIER, pcr->hw_param.interrupt_en); | |
1383 | ||
1384 | rtsx_pci_write_register(pcr, RTS5260_AUTOLOAD_CFG4, | |
1385 | RTS5261_AUX_CLK_16M_EN, RTS5261_AUX_CLK_16M_EN); | |
1386 | rtsx_pci_write_register(pcr, RTS5261_FW_CFG0, | |
1387 | RTS5261_FW_ENTER_EXPRESS, RTS5261_FW_ENTER_EXPRESS); | |
6b7b58f4 RF |
1388 | rtsx_pci_write_register(pcr, RTS5261_FW_CFG1, |
1389 | RTS5261_MCU_CLOCK_GATING, RTS5261_MCU_CLOCK_GATING); | |
9ff43c7b RF |
1390 | rtsx_pci_write_register(pcr, RTS5261_FW_CFG1, |
1391 | RTS5261_MCU_BUS_SEL_MASK | RTS5261_MCU_CLOCK_SEL_MASK | |
6b7b58f4 RF |
1392 | | RTS5261_DRIVER_ENABLE_FW, |
1393 | RTS5261_MCU_CLOCK_SEL_16M | RTS5261_DRIVER_ENABLE_FW); | |
9ff43c7b RF |
1394 | host->eject = true; |
1395 | return 0; | |
1396 | } | |
1397 | ||
ff984e57 | 1398 | static const struct mmc_host_ops realtek_pci_sdmmc_ops = { |
6291e715 MC |
1399 | .pre_req = sdmmc_pre_req, |
1400 | .post_req = sdmmc_post_req, | |
ff984e57 WW |
1401 | .request = sdmmc_request, |
1402 | .set_ios = sdmmc_set_ios, | |
1403 | .get_ro = sdmmc_get_ro, | |
1404 | .get_cd = sdmmc_get_cd, | |
1405 | .start_signal_voltage_switch = sdmmc_switch_voltage, | |
1406 | .execute_tuning = sdmmc_execute_tuning, | |
9ff43c7b | 1407 | .init_sd_express = sdmmc_init_sd_express, |
ff984e57 WW |
1408 | }; |
1409 | ||
ff984e57 WW |
1410 | static void init_extra_caps(struct realtek_pci_sdmmc *host) |
1411 | { | |
1412 | struct mmc_host *mmc = host->mmc; | |
1413 | struct rtsx_pcr *pcr = host->pcr; | |
1414 | ||
1415 | dev_dbg(sdmmc_dev(host), "pcr->extra_caps = 0x%x\n", pcr->extra_caps); | |
1416 | ||
1417 | if (pcr->extra_caps & EXTRA_CAPS_SD_SDR50) | |
1418 | mmc->caps |= MMC_CAP_UHS_SDR50; | |
1419 | if (pcr->extra_caps & EXTRA_CAPS_SD_SDR104) | |
1420 | mmc->caps |= MMC_CAP_UHS_SDR104; | |
1421 | if (pcr->extra_caps & EXTRA_CAPS_SD_DDR50) | |
1422 | mmc->caps |= MMC_CAP_UHS_DDR50; | |
1423 | if (pcr->extra_caps & EXTRA_CAPS_MMC_HSDDR) | |
1424 | mmc->caps |= MMC_CAP_1_8V_DDR; | |
1425 | if (pcr->extra_caps & EXTRA_CAPS_MMC_8BIT) | |
1426 | mmc->caps |= MMC_CAP_8_BIT_DATA; | |
849a9366 RW |
1427 | if (pcr->extra_caps & EXTRA_CAPS_NO_MMC) |
1428 | mmc->caps2 |= MMC_CAP2_NO_MMC; | |
9ff43c7b RF |
1429 | if (pcr->extra_caps & EXTRA_CAPS_SD_EXPRESS) |
1430 | mmc->caps2 |= MMC_CAP2_SD_EXP | MMC_CAP2_SD_EXP_1_2V; | |
ff984e57 WW |
1431 | } |
1432 | ||
1433 | static void realtek_init_host(struct realtek_pci_sdmmc *host) | |
1434 | { | |
1435 | struct mmc_host *mmc = host->mmc; | |
5b4258f6 | 1436 | struct rtsx_pcr *pcr = host->pcr; |
ff984e57 WW |
1437 | |
1438 | mmc->f_min = 250000; | |
1439 | mmc->f_max = 208000000; | |
1440 | mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195; | |
1441 | mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SD_HIGHSPEED | | |
1442 | MMC_CAP_MMC_HIGHSPEED | MMC_CAP_BUS_WIDTH_TEST | | |
1be64c79 | 1443 | MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25; |
5b4258f6 RW |
1444 | if (pcr->rtd3_en) |
1445 | mmc->caps = mmc->caps | MMC_CAP_AGGRESSIVE_PM; | |
8b280564 RW |
1446 | mmc->caps2 = MMC_CAP2_NO_PRESCAN_POWERUP | MMC_CAP2_FULL_PWR_CYCLE | |
1447 | MMC_CAP2_NO_SDIO; | |
ff984e57 WW |
1448 | mmc->max_current_330 = 400; |
1449 | mmc->max_current_180 = 800; | |
1450 | mmc->ops = &realtek_pci_sdmmc_ops; | |
1451 | ||
1452 | init_extra_caps(host); | |
1453 | ||
1454 | mmc->max_segs = 256; | |
1455 | mmc->max_seg_size = 65536; | |
1456 | mmc->max_blk_size = 512; | |
1457 | mmc->max_blk_count = 65535; | |
1458 | mmc->max_req_size = 524288; | |
1459 | } | |
1460 | ||
1461 | static void rtsx_pci_sdmmc_card_event(struct platform_device *pdev) | |
1462 | { | |
1463 | struct realtek_pci_sdmmc *host = platform_get_drvdata(pdev); | |
1464 | ||
2057647f | 1465 | host->cookie = -1; |
ff984e57 WW |
1466 | mmc_detect_change(host->mmc, 0); |
1467 | } | |
1468 | ||
1469 | static int rtsx_pci_sdmmc_drv_probe(struct platform_device *pdev) | |
1470 | { | |
1471 | struct mmc_host *mmc; | |
1472 | struct realtek_pci_sdmmc *host; | |
1473 | struct rtsx_pcr *pcr; | |
1474 | struct pcr_handle *handle = pdev->dev.platform_data; | |
1475 | ||
1476 | if (!handle) | |
1477 | return -ENXIO; | |
1478 | ||
1479 | pcr = handle->pcr; | |
1480 | if (!pcr) | |
1481 | return -ENXIO; | |
1482 | ||
1483 | dev_dbg(&(pdev->dev), ": Realtek PCI-E SDMMC controller found\n"); | |
1484 | ||
1485 | mmc = mmc_alloc_host(sizeof(*host), &pdev->dev); | |
1486 | if (!mmc) | |
1487 | return -ENOMEM; | |
1488 | ||
1489 | host = mmc_priv(mmc); | |
1490 | host->pcr = pcr; | |
1491 | host->mmc = mmc; | |
1492 | host->pdev = pdev; | |
2057647f | 1493 | host->cookie = -1; |
d88691be | 1494 | host->power_state = SDMMC_POWER_OFF; |
6291e715 | 1495 | INIT_WORK(&host->work, sd_request); |
ff984e57 WW |
1496 | platform_set_drvdata(pdev, host); |
1497 | pcr->slots[RTSX_SD_CARD].p_dev = pdev; | |
1498 | pcr->slots[RTSX_SD_CARD].card_event = rtsx_pci_sdmmc_card_event; | |
1499 | ||
98fcc576 | 1500 | mutex_init(&host->host_mutex); |
ff984e57 WW |
1501 | |
1502 | realtek_init_host(host); | |
1503 | ||
72085bdc KHF |
1504 | pm_runtime_no_callbacks(&pdev->dev); |
1505 | pm_runtime_set_active(&pdev->dev); | |
1506 | pm_runtime_enable(&pdev->dev); | |
1507 | pm_runtime_set_autosuspend_delay(&pdev->dev, 200); | |
1508 | pm_runtime_mark_last_busy(&pdev->dev); | |
1509 | pm_runtime_use_autosuspend(&pdev->dev); | |
5b4258f6 | 1510 | |
ff984e57 WW |
1511 | mmc_add_host(mmc); |
1512 | ||
1513 | return 0; | |
1514 | } | |
1515 | ||
1516 | static int rtsx_pci_sdmmc_drv_remove(struct platform_device *pdev) | |
1517 | { | |
1518 | struct realtek_pci_sdmmc *host = platform_get_drvdata(pdev); | |
1519 | struct rtsx_pcr *pcr; | |
1520 | struct mmc_host *mmc; | |
1521 | ||
1522 | if (!host) | |
1523 | return 0; | |
1524 | ||
1525 | pcr = host->pcr; | |
1526 | pcr->slots[RTSX_SD_CARD].p_dev = NULL; | |
1527 | pcr->slots[RTSX_SD_CARD].card_event = NULL; | |
1528 | mmc = host->mmc; | |
ff984e57 | 1529 | |
6291e715 MC |
1530 | cancel_work_sync(&host->work); |
1531 | ||
98fcc576 | 1532 | mutex_lock(&host->host_mutex); |
ff984e57 WW |
1533 | if (host->mrq) { |
1534 | dev_dbg(&(pdev->dev), | |
1535 | "%s: Controller removed during transfer\n", | |
1536 | mmc_hostname(mmc)); | |
1537 | ||
98fcc576 | 1538 | rtsx_pci_complete_unfinished_transfer(pcr); |
ff984e57 | 1539 | |
98fcc576 MC |
1540 | host->mrq->cmd->error = -ENOMEDIUM; |
1541 | if (host->mrq->stop) | |
1542 | host->mrq->stop->error = -ENOMEDIUM; | |
1543 | mmc_request_done(mmc, host->mrq); | |
ff984e57 | 1544 | } |
98fcc576 | 1545 | mutex_unlock(&host->host_mutex); |
ff984e57 WW |
1546 | |
1547 | mmc_remove_host(mmc); | |
640e09bc MC |
1548 | host->eject = true; |
1549 | ||
6ea62579 | 1550 | flush_work(&host->work); |
6291e715 | 1551 | |
72085bdc KHF |
1552 | pm_runtime_dont_use_autosuspend(&pdev->dev); |
1553 | pm_runtime_disable(&pdev->dev); | |
1554 | ||
ff984e57 WW |
1555 | mmc_free_host(mmc); |
1556 | ||
ff984e57 WW |
1557 | dev_dbg(&(pdev->dev), |
1558 | ": Realtek PCI-E SDMMC controller has been removed\n"); | |
1559 | ||
1560 | return 0; | |
1561 | } | |
1562 | ||
f2483b0d | 1563 | static const struct platform_device_id rtsx_pci_sdmmc_ids[] = { |
ff984e57 WW |
1564 | { |
1565 | .name = DRV_NAME_RTSX_PCI_SDMMC, | |
1566 | }, { | |
1567 | /* sentinel */ | |
1568 | } | |
1569 | }; | |
1570 | MODULE_DEVICE_TABLE(platform, rtsx_pci_sdmmc_ids); | |
1571 | ||
1572 | static struct platform_driver rtsx_pci_sdmmc_driver = { | |
1573 | .probe = rtsx_pci_sdmmc_drv_probe, | |
1574 | .remove = rtsx_pci_sdmmc_drv_remove, | |
1575 | .id_table = rtsx_pci_sdmmc_ids, | |
ff984e57 | 1576 | .driver = { |
ff984e57 | 1577 | .name = DRV_NAME_RTSX_PCI_SDMMC, |
21b2cec6 | 1578 | .probe_type = PROBE_PREFER_ASYNCHRONOUS, |
ff984e57 WW |
1579 | }, |
1580 | }; | |
1581 | module_platform_driver(rtsx_pci_sdmmc_driver); | |
1582 | ||
1583 | MODULE_LICENSE("GPL"); | |
1584 | MODULE_AUTHOR("Wei WANG <wei_wang@realsil.com.cn>"); | |
1585 | MODULE_DESCRIPTION("Realtek PCI-E SD/MMC Card Host Driver"); |