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mmc: rtsx: add dump_reg_range to simplify dump register
[mirror_ubuntu-artful-kernel.git] / drivers / mmc / host / rtsx_pci_sdmmc.c
CommitLineData
ff984e57
WW		 1/* Realtek PCI-Express SD/MMC Card Interface driver
2 *
62282180 3 * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
ff984e57
WW		 4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2, or (at your option) any
8 * later version.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, see <http://www.gnu.org/licenses/>.
17 *
18 * Author:
19 * Wei WANG <wei_wang@realsil.com.cn>
ff984e57
WW		 20 */
21
22#include <linux/module.h>
433e075c 23#include <linux/slab.h>
ff984e57
WW		 24#include <linux/highmem.h>
25#include <linux/delay.h>
26#include <linux/platform_device.h>
6291e715 27#include <linux/workqueue.h>
ff984e57
WW		 28#include <linux/mmc/host.h>
29#include <linux/mmc/mmc.h>
30#include <linux/mmc/sd.h>
31#include <linux/mmc/card.h>
32#include <linux/mfd/rtsx_pci.h>
33#include <asm/unaligned.h>
34
ff984e57
WW		 35struct realtek_pci_sdmmc {
36 struct platform_device *pdev;
37 struct rtsx_pcr *pcr;
38 struct mmc_host *mmc;
39 struct mmc_request *mrq;
6291e715
MC		 40 struct workqueue_struct *workq;
41#define SDMMC_WORKQ_NAME "rtsx_pci_sdmmc_workq"
98fcc576 42
6291e715 43 struct work_struct work;
98fcc576
MC		 44 struct mutex host_mutex;
45
ff984e57
WW		 46 u8 ssc_depth;
47 unsigned int clock;
48 bool vpclk;
49 bool double_clk;
50 bool eject;
51 bool initial_mode;
d88691be
WW		 52 int power_state;
53#define SDMMC_POWER_ON 1
54#define SDMMC_POWER_OFF 0
6291e715
MC		 55
56 unsigned int sg_count;
57 s32 cookie;
58 unsigned int cookie_sg_count;
59 bool using_cookie;
ff984e57
WW		 60};
61
62static inline struct device *sdmmc_dev(struct realtek_pci_sdmmc *host)
63{
64 return &(host->pdev->dev);
65}
66
67static inline void sd_clear_error(struct realtek_pci_sdmmc *host)
68{
69 rtsx_pci_write_register(host->pcr, CARD_STOP,
70 SD_STOP | SD_CLR_ERR, SD_STOP | SD_CLR_ERR);
71}
72
73#ifdef DEBUG
755987f9 74static void dump_reg_range(struct realtek_pci_sdmmc *host, u16 start, u16 end)
ff984e57 75{
755987f9
MC		 76 u16 len = end - start + 1;
77 int i;
78 u8 data[8];
79
80 for (i = 0; i < len; i += 8) {
81 int j;
82 int n = min(8, len - i);
ff984e57 83
755987f9
MC		 84 memset(&data, 0, sizeof(data));
85 for (j = 0; j < n; j++)
86 rtsx_pci_read_register(host->pcr, start + i + j,
87 data + j);
88 dev_dbg(sdmmc_dev(host), "0x%04X(%d): %8ph\n",
89 start + i, n, data);
90 }
91}
ff984e57 92
755987f9
MC		 93static void sd_print_debug_regs(struct realtek_pci_sdmmc *host)
94{
95 dump_reg_range(host, 0xFDA0, 0xFDB3);
96 dump_reg_range(host, 0xFD52, 0xFD69);
ff984e57
WW		 97}
98#else
99#define sd_print_debug_regs(host)
100#endif /* DEBUG */
101
6291e715
MC		 102/*
103 * sd_pre_dma_transfer - do dma_map_sg() or using cookie
104 *
105 * @pre: if called in pre_req()
106 * return:
107 * 0 - do dma_map_sg()
108 * 1 - using cookie
109 */
110static int sd_pre_dma_transfer(struct realtek_pci_sdmmc *host,
111 struct mmc_data *data, bool pre)
112{
113 struct rtsx_pcr *pcr = host->pcr;
114 int read = data->flags & MMC_DATA_READ;
115 int count = 0;
116 int using_cookie = 0;
117
118 if (!pre && data->host_cookie && data->host_cookie != host->cookie) {
119 dev_err(sdmmc_dev(host),
120 "error: data->host_cookie = %d, host->cookie = %d\n",
121 data->host_cookie, host->cookie);
122 data->host_cookie = 0;
123 }
124
125 if (pre || data->host_cookie != host->cookie) {
126 count = rtsx_pci_dma_map_sg(pcr, data->sg, data->sg_len, read);
127 } else {
128 count = host->cookie_sg_count;
129 using_cookie = 1;
130 }
131
132 if (pre) {
133 host->cookie_sg_count = count;
134 if (++host->cookie < 0)
135 host->cookie = 1;
136 data->host_cookie = host->cookie;
137 } else {
138 host->sg_count = count;
139 }
140
141 return using_cookie;
142}
143
144static void sdmmc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq,
145 bool is_first_req)
146{
147 struct realtek_pci_sdmmc *host = mmc_priv(mmc);
148 struct mmc_data *data = mrq->data;
149
150 if (data->host_cookie) {
151 dev_err(sdmmc_dev(host),
152 "error: reset data->host_cookie = %d\n",
153 data->host_cookie);
154 data->host_cookie = 0;
155 }
156
157 sd_pre_dma_transfer(host, data, true);
158 dev_dbg(sdmmc_dev(host), "pre dma sg: %d\n", host->cookie_sg_count);
159}
160
161static void sdmmc_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
162 int err)
163{
164 struct realtek_pci_sdmmc *host = mmc_priv(mmc);
165 struct rtsx_pcr *pcr = host->pcr;
166 struct mmc_data *data = mrq->data;
167 int read = data->flags & MMC_DATA_READ;
168
169 rtsx_pci_dma_unmap_sg(pcr, data->sg, data->sg_len, read);
170 data->host_cookie = 0;
171}
172
ff984e57
WW		 173static int sd_read_data(struct realtek_pci_sdmmc *host, u8 *cmd, u16 byte_cnt,
174 u8 *buf, int buf_len, int timeout)
175{
176 struct rtsx_pcr *pcr = host->pcr;
177 int err, i;
178 u8 trans_mode;
179
180 dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD%d\n", __func__, cmd[0] - 0x40);
181
182 if (!buf)
183 buf_len = 0;
184
185 if ((cmd[0] & 0x3F) == MMC_SEND_TUNING_BLOCK)
186 trans_mode = SD_TM_AUTO_TUNING;
187 else
188 trans_mode = SD_TM_NORMAL_READ;
189
190 rtsx_pci_init_cmd(pcr);
191
192 for (i = 0; i < 5; i++)
193 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CMD0 + i, 0xFF, cmd[i]);
194
195 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BYTE_CNT_L, 0xFF, (u8)byte_cnt);
196 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BYTE_CNT_H,
197 0xFF, (u8)(byte_cnt >> 8));
198 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BLOCK_CNT_L, 0xFF, 1);
199 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BLOCK_CNT_H, 0xFF, 0);
200
201 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF,
202 SD_CALCULATE_CRC7 | SD_CHECK_CRC16 |
203 SD_NO_WAIT_BUSY_END | SD_CHECK_CRC7 | SD_RSP_LEN_6);
204 if (trans_mode != SD_TM_AUTO_TUNING)
205 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
206 CARD_DATA_SOURCE, 0x01, PINGPONG_BUFFER);
207
208 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER,
209 0xFF, trans_mode | SD_TRANSFER_START);
210 rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER,
211 SD_TRANSFER_END, SD_TRANSFER_END);
212
213 err = rtsx_pci_send_cmd(pcr, timeout);
214 if (err < 0) {
215 sd_print_debug_regs(host);
216 dev_dbg(sdmmc_dev(host),
217 "rtsx_pci_send_cmd fail (err = %d)\n", err);
218 return err;
219 }
220
221 if (buf && buf_len) {
222 err = rtsx_pci_read_ppbuf(pcr, buf, buf_len);
223 if (err < 0) {
224 dev_dbg(sdmmc_dev(host),
225 "rtsx_pci_read_ppbuf fail (err = %d)\n", err);
226 return err;
227 }
228 }
229
230 return 0;
231}
232
233static int sd_write_data(struct realtek_pci_sdmmc *host, u8 *cmd, u16 byte_cnt,
234 u8 *buf, int buf_len, int timeout)
235{
236 struct rtsx_pcr *pcr = host->pcr;
237 int err, i;
238 u8 trans_mode;
239
240 if (!buf)
241 buf_len = 0;
242
243 if (buf && buf_len) {
244 err = rtsx_pci_write_ppbuf(pcr, buf, buf_len);
245 if (err < 0) {
246 dev_dbg(sdmmc_dev(host),
247 "rtsx_pci_write_ppbuf fail (err = %d)\n", err);
248 return err;
249 }
250 }
251
252 trans_mode = cmd ? SD_TM_AUTO_WRITE_2 : SD_TM_AUTO_WRITE_3;
253 rtsx_pci_init_cmd(pcr);
254
255 if (cmd) {
256 dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD %d\n", __func__,
257 cmd[0] - 0x40);
258
259 for (i = 0; i < 5; i++)
260 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
261 SD_CMD0 + i, 0xFF, cmd[i]);
262 }
263
264 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BYTE_CNT_L, 0xFF, (u8)byte_cnt);
265 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BYTE_CNT_H,
266 0xFF, (u8)(byte_cnt >> 8));
267 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BLOCK_CNT_L, 0xFF, 1);
268 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BLOCK_CNT_H, 0xFF, 0);
269
270 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF,
271 SD_CALCULATE_CRC7 | SD_CHECK_CRC16 |
272 SD_NO_WAIT_BUSY_END | SD_CHECK_CRC7 | SD_RSP_LEN_6);
273
274 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER, 0xFF,
275 trans_mode | SD_TRANSFER_START);
276 rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER,
277 SD_TRANSFER_END, SD_TRANSFER_END);
278
279 err = rtsx_pci_send_cmd(pcr, timeout);
280 if (err < 0) {
281 sd_print_debug_regs(host);
282 dev_dbg(sdmmc_dev(host),
283 "rtsx_pci_send_cmd fail (err = %d)\n", err);
284 return err;
285 }
286
287 return 0;
288}
289
98fcc576
MC		 290static void sd_send_cmd_get_rsp(struct realtek_pci_sdmmc *host,
291 struct mmc_command *cmd)
ff984e57
WW		 292{
293 struct rtsx_pcr *pcr = host->pcr;
294 u8 cmd_idx = (u8)cmd->opcode;
295 u32 arg = cmd->arg;
296 int err = 0;
297 int timeout = 100;
298 int i;
98fcc576
MC		 299 u8 *ptr;
300 int stat_idx = 0;
ff984e57
WW		 301 u8 rsp_type;
302 int rsp_len = 5;
98fcc576 303 bool clock_toggled = false;
ff984e57
WW		 304
305 dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD %d, arg = 0x%08x\n",
306 __func__, cmd_idx, arg);
307
308 /* Response type:
309 * R0
310 * R1, R5, R6, R7
311 * R1b
312 * R2
313 * R3, R4
314 */
315 switch (mmc_resp_type(cmd)) {
316 case MMC_RSP_NONE:
317 rsp_type = SD_RSP_TYPE_R0;
318 rsp_len = 0;
319 break;
320 case MMC_RSP_R1:
321 rsp_type = SD_RSP_TYPE_R1;
322 break;
5027251e
MC		 323 case MMC_RSP_R1 & ~MMC_RSP_CRC:
324 rsp_type = SD_RSP_TYPE_R1 | SD_NO_CHECK_CRC7;
325 break;
ff984e57
WW		 326 case MMC_RSP_R1B:
327 rsp_type = SD_RSP_TYPE_R1b;
328 break;
329 case MMC_RSP_R2:
330 rsp_type = SD_RSP_TYPE_R2;
331 rsp_len = 16;
332 break;
333 case MMC_RSP_R3:
334 rsp_type = SD_RSP_TYPE_R3;
335 break;
336 default:
337 dev_dbg(sdmmc_dev(host), "cmd->flag is not valid\n");
338 err = -EINVAL;
339 goto out;
340 }
341
342 if (rsp_type == SD_RSP_TYPE_R1b)
343 timeout = 3000;
344
345 if (cmd->opcode == SD_SWITCH_VOLTAGE) {
346 err = rtsx_pci_write_register(pcr, SD_BUS_STAT,
347 0xFF, SD_CLK_TOGGLE_EN);
348 if (err < 0)
349 goto out;
98fcc576
MC		 350
351 clock_toggled = true;
ff984e57
WW		 352 }
353
354 rtsx_pci_init_cmd(pcr);
355
356 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CMD0, 0xFF, 0x40 | cmd_idx);
357 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CMD1, 0xFF, (u8)(arg >> 24));
358 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CMD2, 0xFF, (u8)(arg >> 16));
359 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CMD3, 0xFF, (u8)(arg >> 8));
360 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CMD4, 0xFF, (u8)arg);
361
362 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF, rsp_type);
363 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_DATA_SOURCE,
364 0x01, PINGPONG_BUFFER);
365 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER,
366 0xFF, SD_TM_CMD_RSP | SD_TRANSFER_START);
367 rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER,
368 SD_TRANSFER_END | SD_STAT_IDLE,
369 SD_TRANSFER_END | SD_STAT_IDLE);
370
371 if (rsp_type == SD_RSP_TYPE_R2) {
372 /* Read data from ping-pong buffer */
373 for (i = PPBUF_BASE2; i < PPBUF_BASE2 + 16; i++)
374 rtsx_pci_add_cmd(pcr, READ_REG_CMD, (u16)i, 0, 0);
98fcc576 375 stat_idx = 16;
ff984e57
WW		 376 } else if (rsp_type != SD_RSP_TYPE_R0) {
377 /* Read data from SD_CMDx registers */
378 for (i = SD_CMD0; i <= SD_CMD4; i++)
379 rtsx_pci_add_cmd(pcr, READ_REG_CMD, (u16)i, 0, 0);
98fcc576 380 stat_idx = 5;
ff984e57
WW		 381 }
382
383 rtsx_pci_add_cmd(pcr, READ_REG_CMD, SD_STAT1, 0, 0);
384
98fcc576
MC		 385 err = rtsx_pci_send_cmd(pcr, timeout);
386 if (err < 0) {
387 sd_print_debug_regs(host);
388 sd_clear_error(host);
389 dev_dbg(sdmmc_dev(host),
390 "rtsx_pci_send_cmd error (err = %d)\n", err);
ff984e57
WW		 391 goto out;
392 }
393
394 if (rsp_type == SD_RSP_TYPE_R0) {
395 err = 0;
396 goto out;
397 }
398
399 /* Eliminate returned value of CHECK_REG_CMD */
400 ptr = rtsx_pci_get_cmd_data(pcr) + 1;
401
402 /* Check (Start,Transmission) bit of Response */
403 if ((ptr[0] & 0xC0) != 0) {
404 err = -EILSEQ;
405 dev_dbg(sdmmc_dev(host), "Invalid response bit\n");
406 goto out;
407 }
408
409 /* Check CRC7 */
410 if (!(rsp_type & SD_NO_CHECK_CRC7)) {
411 if (ptr[stat_idx] & SD_CRC7_ERR) {
412 err = -EILSEQ;
413 dev_dbg(sdmmc_dev(host), "CRC7 error\n");
414 goto out;
415 }
416 }
417
418 if (rsp_type == SD_RSP_TYPE_R2) {
d1419d50
RT		 419 /*
420 * The controller offloads the last byte {CRC-7, end bit 1'b1}
421 * of response type R2. Assign dummy CRC, 0, and end bit to the
422 * byte(ptr[16], goes into the LSB of resp[3] later).
423 */
424 ptr[16] = 1;
425
ff984e57
WW		 426 for (i = 0; i < 4; i++) {
427 cmd->resp[i] = get_unaligned_be32(ptr + 1 + i * 4);
428 dev_dbg(sdmmc_dev(host), "cmd->resp[%d] = 0x%08x\n",
429 i, cmd->resp[i]);
430 }
431 } else {
432 cmd->resp[0] = get_unaligned_be32(ptr + 1);
433 dev_dbg(sdmmc_dev(host), "cmd->resp[0] = 0x%08x\n",
434 cmd->resp[0]);
435 }
436
437out:
438 cmd->error = err;
1b8055b4 439
98fcc576
MC		 440 if (err && clock_toggled)
441 rtsx_pci_write_register(pcr, SD_BUS_STAT,
442 SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP, 0);
ff984e57
WW		 443}
444
98fcc576 445static int sd_rw_multi(struct realtek_pci_sdmmc *host, struct mmc_request *mrq)
ff984e57
WW		 446{
447 struct rtsx_pcr *pcr = host->pcr;
448 struct mmc_host *mmc = host->mmc;
449 struct mmc_card *card = mmc->card;
450 struct mmc_data *data = mrq->data;
71ef1ea4 451 int uhs = mmc_card_uhs(card);
98fcc576 452 int read = (data->flags & MMC_DATA_READ) ? 1 : 0;
ff984e57
WW		 453 u8 cfg2, trans_mode;
454 int err;
455 size_t data_len = data->blksz * data->blocks;
456
457 if (read) {
458 cfg2 = SD_CALCULATE_CRC7 | SD_CHECK_CRC16 |
459 SD_NO_WAIT_BUSY_END | SD_CHECK_CRC7 | SD_RSP_LEN_0;
460 trans_mode = SD_TM_AUTO_READ_3;
461 } else {
462 cfg2 = SD_NO_CALCULATE_CRC7 | SD_CHECK_CRC16 |
463 SD_NO_WAIT_BUSY_END | SD_NO_CHECK_CRC7 | SD_RSP_LEN_0;
464 trans_mode = SD_TM_AUTO_WRITE_3;
465 }
466
467 if (!uhs)
468 cfg2 |= SD_NO_CHECK_WAIT_CRC_TO;
469
470 rtsx_pci_init_cmd(pcr);
471
472 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BYTE_CNT_L, 0xFF, 0x00);
473 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BYTE_CNT_H, 0xFF, 0x02);
474 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BLOCK_CNT_L,
475 0xFF, (u8)data->blocks);
476 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BLOCK_CNT_H,
477 0xFF, (u8)(data->blocks >> 8));
ff984e57
WW		 478
479 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, IRQSTAT0,
480 DMA_DONE_INT, DMA_DONE_INT);
481 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC3,
482 0xFF, (u8)(data_len >> 24));
483 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC2,
484 0xFF, (u8)(data_len >> 16));
485 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC1,
486 0xFF, (u8)(data_len >> 8));
487 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC0, 0xFF, (u8)data_len);
488 if (read) {
489 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMACTL,
490 0x03 | DMA_PACK_SIZE_MASK,
491 DMA_DIR_FROM_CARD | DMA_EN | DMA_512);
492 } else {
493 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMACTL,
494 0x03 | DMA_PACK_SIZE_MASK,
495 DMA_DIR_TO_CARD | DMA_EN | DMA_512);
496 }
497
498 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_DATA_SOURCE,
499 0x01, RING_BUFFER);
500
38d324df 501 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF, cfg2);
ff984e57
WW		 502 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER, 0xFF,
503 trans_mode | SD_TRANSFER_START);
504 rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER,
505 SD_TRANSFER_END, SD_TRANSFER_END);
506
507 rtsx_pci_send_cmd_no_wait(pcr);
508
6291e715 509 err = rtsx_pci_dma_transfer(pcr, data->sg, host->sg_count, read, 10000);
c42deffd 510 if (err < 0) {
98fcc576
MC		 511 sd_clear_error(host);
512 return err;
c42deffd
MC		 513 }
514
98fcc576 515 return 0;
c42deffd
MC		 516}
517
ff984e57
WW		 518static inline void sd_enable_initial_mode(struct realtek_pci_sdmmc *host)
519{
520 rtsx_pci_write_register(host->pcr, SD_CFG1,
521 SD_CLK_DIVIDE_MASK, SD_CLK_DIVIDE_128);
522}
523
524static inline void sd_disable_initial_mode(struct realtek_pci_sdmmc *host)
525{
526 rtsx_pci_write_register(host->pcr, SD_CFG1,
527 SD_CLK_DIVIDE_MASK, SD_CLK_DIVIDE_0);
528}
529
530static void sd_normal_rw(struct realtek_pci_sdmmc *host,
531 struct mmc_request *mrq)
532{
533 struct mmc_command *cmd = mrq->cmd;
534 struct mmc_data *data = mrq->data;
535 u8 _cmd[5], *buf;
536
537 _cmd[0] = 0x40 | (u8)cmd->opcode;
538 put_unaligned_be32(cmd->arg, (u32 *)(&_cmd[1]));
539
540 buf = kzalloc(data->blksz, GFP_NOIO);
541 if (!buf) {
542 cmd->error = -ENOMEM;
543 return;
544 }
545
546 if (data->flags & MMC_DATA_READ) {
547 if (host->initial_mode)
548 sd_disable_initial_mode(host);
549
550 cmd->error = sd_read_data(host, _cmd, (u16)data->blksz, buf,
551 data->blksz, 200);
552
553 if (host->initial_mode)
554 sd_enable_initial_mode(host);
555
556 sg_copy_from_buffer(data->sg, data->sg_len, buf, data->blksz);
557 } else {
558 sg_copy_to_buffer(data->sg, data->sg_len, buf, data->blksz);
559
560 cmd->error = sd_write_data(host, _cmd, (u16)data->blksz, buf,
561 data->blksz, 200);
562 }
563
564 kfree(buf);
565}
566
84d72f9c
WW		 567static int sd_change_phase(struct realtek_pci_sdmmc *host,
568 u8 sample_point, bool rx)
ff984e57
WW		 569{
570 struct rtsx_pcr *pcr = host->pcr;
571 int err;
572
84d72f9c
WW		 573 dev_dbg(sdmmc_dev(host), "%s(%s): sample_point = %d\n",
574 __func__, rx ? "RX" : "TX", sample_point);
ff984e57
WW		 575
576 rtsx_pci_init_cmd(pcr);
577
578 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CHANGE_CLK, CHANGE_CLK);
84d72f9c
WW		 579 if (rx)
580 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
581 SD_VPRX_CTL, 0x1F, sample_point);
582 else
583 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
584 SD_VPTX_CTL, 0x1F, sample_point);
ff984e57
WW		 585 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL, PHASE_NOT_RESET, 0);
586 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL,
587 PHASE_NOT_RESET, PHASE_NOT_RESET);
588 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CHANGE_CLK, 0);
589 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1, SD_ASYNC_FIFO_NOT_RST, 0);
590
591 err = rtsx_pci_send_cmd(pcr, 100);
592 if (err < 0)
593 return err;
594
595 return 0;
596}
597
abcc6b29 598static inline u32 test_phase_bit(u32 phase_map, unsigned int bit)
ff984e57 599{
abcc6b29
MC		 600 bit %= RTSX_PHASE_MAX;
601 return phase_map & (1 << bit);
602}
ff984e57 603
abcc6b29
MC		 604static int sd_get_phase_len(u32 phase_map, unsigned int start_bit)
605{
606 int i;
ff984e57 607
abcc6b29
MC		 608 for (i = 0; i < RTSX_PHASE_MAX; i++) {
609 if (test_phase_bit(phase_map, start_bit + i) == 0)
610 return i;
ff984e57 611 }
abcc6b29
MC		 612 return RTSX_PHASE_MAX;
613}
ff984e57 614
abcc6b29
MC		 615static u8 sd_search_final_phase(struct realtek_pci_sdmmc *host, u32 phase_map)
616{
617 int start = 0, len = 0;
618 int start_final = 0, len_final = 0;
619 u8 final_phase = 0xFF;
620
621 if (phase_map == 0) {
622 dev_err(sdmmc_dev(host), "phase error: [map:%x]\n", phase_map);
623 return final_phase;
ff984e57
WW		 624 }
625
abcc6b29
MC		 626 while (start < RTSX_PHASE_MAX) {
627 len = sd_get_phase_len(phase_map, start);
628 if (len_final < len) {
629 start_final = start;
630 len_final = len;
ff984e57 631 }
abcc6b29 632 start += len ? len : 1;
ff984e57
WW		 633 }
634
abcc6b29
MC		 635 final_phase = (start_final + len_final / 2) % RTSX_PHASE_MAX;
636 dev_dbg(sdmmc_dev(host), "phase: [map:%x] [maxlen:%d] [final:%d]\n",
637 phase_map, len_final, final_phase);
638
ff984e57
WW		 639 return final_phase;
640}
641
642static void sd_wait_data_idle(struct realtek_pci_sdmmc *host)
643{
644 int err, i;
645 u8 val = 0;
646
647 for (i = 0; i < 100; i++) {
648 err = rtsx_pci_read_register(host->pcr, SD_DATA_STATE, &val);
649 if (val & SD_DATA_IDLE)
650 return;
651
652 udelay(100);
653 }
654}
655
656static int sd_tuning_rx_cmd(struct realtek_pci_sdmmc *host,
657 u8 opcode, u8 sample_point)
658{
659 int err;
660 u8 cmd[5] = {0};
661
84d72f9c 662 err = sd_change_phase(host, sample_point, true);
ff984e57
WW		 663 if (err < 0)
664 return err;
665
666 cmd[0] = 0x40 | opcode;
667 err = sd_read_data(host, cmd, 0x40, NULL, 0, 100);
668 if (err < 0) {
669 /* Wait till SD DATA IDLE */
670 sd_wait_data_idle(host);
671 sd_clear_error(host);
672 return err;
673 }
674
675 return 0;
676}
677
678static int sd_tuning_phase(struct realtek_pci_sdmmc *host,
679 u8 opcode, u32 *phase_map)
680{
681 int err, i;
682 u32 raw_phase_map = 0;
683
abcc6b29 684 for (i = 0; i < RTSX_PHASE_MAX; i++) {
ff984e57
WW		 685 err = sd_tuning_rx_cmd(host, opcode, (u8)i);
686 if (err == 0)
687 raw_phase_map |= 1 << i;
688 }
689
690 if (phase_map)
691 *phase_map = raw_phase_map;
692
693 return 0;
694}
695
696static int sd_tuning_rx(struct realtek_pci_sdmmc *host, u8 opcode)
697{
698 int err, i;
699 u32 raw_phase_map[RX_TUNING_CNT] = {0}, phase_map;
700 u8 final_phase;
701
702 for (i = 0; i < RX_TUNING_CNT; i++) {
703 err = sd_tuning_phase(host, opcode, &(raw_phase_map[i]));
704 if (err < 0)
705 return err;
706
707 if (raw_phase_map[i] == 0)
708 break;
709 }
710
711 phase_map = 0xFFFFFFFF;
712 for (i = 0; i < RX_TUNING_CNT; i++) {
713 dev_dbg(sdmmc_dev(host), "RX raw_phase_map[%d] = 0x%08x\n",
714 i, raw_phase_map[i]);
715 phase_map &= raw_phase_map[i];
716 }
717 dev_dbg(sdmmc_dev(host), "RX phase_map = 0x%08x\n", phase_map);
718
719 if (phase_map) {
720 final_phase = sd_search_final_phase(host, phase_map);
721 if (final_phase == 0xFF)
722 return -EINVAL;
723
84d72f9c 724 err = sd_change_phase(host, final_phase, true);
ff984e57
WW		 725 if (err < 0)
726 return err;
727 } else {
728 return -EINVAL;
729 }
730
731 return 0;
732}
733
6291e715 734static inline int sd_rw_cmd(struct mmc_command *cmd)
ff984e57 735{
6291e715
MC		 736 return mmc_op_multi(cmd->opcode) ||
737 (cmd->opcode == MMC_READ_SINGLE_BLOCK) ||
738 (cmd->opcode == MMC_WRITE_BLOCK);
739}
740
741static void sd_request(struct work_struct *work)
742{
743 struct realtek_pci_sdmmc *host = container_of(work,
744 struct realtek_pci_sdmmc, work);
ff984e57 745 struct rtsx_pcr *pcr = host->pcr;
6291e715
MC		 746
747 struct mmc_host *mmc = host->mmc;
748 struct mmc_request *mrq = host->mrq;
ff984e57
WW		 749 struct mmc_command *cmd = mrq->cmd;
750 struct mmc_data *data = mrq->data;
6291e715 751
ff984e57 752 unsigned int data_size = 0;
c3481955 753 int err;
ff984e57
WW		 754
755 if (host->eject) {
756 cmd->error = -ENOMEDIUM;
757 goto finish;
758 }
759
c3481955
WW		 760 err = rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD);
761 if (err) {
762 cmd->error = err;
763 goto finish;
764 }
765
98fcc576
MC		 766 mutex_lock(&pcr->pcr_mutex);
767
ff984e57
WW		 768 rtsx_pci_start_run(pcr);
769
770 rtsx_pci_switch_clock(pcr, host->clock, host->ssc_depth,
771 host->initial_mode, host->double_clk, host->vpclk);
772 rtsx_pci_write_register(pcr, CARD_SELECT, 0x07, SD_MOD_SEL);
773 rtsx_pci_write_register(pcr, CARD_SHARE_MODE,
774 CARD_SHARE_MASK, CARD_SHARE_48_SD);
775
98fcc576
MC		 776 mutex_lock(&host->host_mutex);
777 host->mrq = mrq;
778 mutex_unlock(&host->host_mutex);
779
ff984e57
WW		 780 if (mrq->data)
781 data_size = data->blocks * data->blksz;
782
6291e715 783 if (!data_size || sd_rw_cmd(cmd)) {
98fcc576 784 sd_send_cmd_get_rsp(host, cmd);
ff984e57 785
98fcc576
MC		 786 if (!cmd->error && data_size) {
787 sd_rw_multi(host, mrq);
6291e715
MC		 788 if (!host->using_cookie)
789 sdmmc_post_req(host->mmc, host->mrq, 0);
98fcc576
MC		 790
791 if (mmc_op_multi(cmd->opcode) && mrq->stop)
792 sd_send_cmd_get_rsp(host, mrq->stop);
793 }
ff984e57
WW		 794 } else {
795 sd_normal_rw(host, mrq);
796 }
98fcc576
MC		 797
798 if (mrq->data) {
799 if (cmd->error || data->error)
800 data->bytes_xfered = 0;
801 else
802 data->bytes_xfered = data->blocks * data->blksz;
803 }
804
805 mutex_unlock(&pcr->pcr_mutex);
ff984e57
WW		 806
807finish:
98fcc576
MC		 808 if (cmd->error)
809 dev_dbg(sdmmc_dev(host), "cmd->error = %d\n", cmd->error);
810
811 mutex_lock(&host->host_mutex);
812 host->mrq = NULL;
813 mutex_unlock(&host->host_mutex);
814
815 mmc_request_done(mmc, mrq);
ff984e57
WW		 816}
817
6291e715
MC		 818static void sdmmc_request(struct mmc_host *mmc, struct mmc_request *mrq)
819{
820 struct realtek_pci_sdmmc *host = mmc_priv(mmc);
821 struct mmc_data *data = mrq->data;
822
823 mutex_lock(&host->host_mutex);
824 host->mrq = mrq;
825 mutex_unlock(&host->host_mutex);
826
827 if (sd_rw_cmd(mrq->cmd))
828 host->using_cookie = sd_pre_dma_transfer(host, data, false);
829
830 queue_work(host->workq, &host->work);
831}
832
ff984e57
WW		 833static int sd_set_bus_width(struct realtek_pci_sdmmc *host,
834 unsigned char bus_width)
835{
836 int err = 0;
837 u8 width[] = {
838 [MMC_BUS_WIDTH_1] = SD_BUS_WIDTH_1BIT,
839 [MMC_BUS_WIDTH_4] = SD_BUS_WIDTH_4BIT,
840 [MMC_BUS_WIDTH_8] = SD_BUS_WIDTH_8BIT,
841 };
842
843 if (bus_width <= MMC_BUS_WIDTH_8)
844 err = rtsx_pci_write_register(host->pcr, SD_CFG1,
845 0x03, width[bus_width]);
846
847 return err;
848}
849
850static int sd_power_on(struct realtek_pci_sdmmc *host)
851{
852 struct rtsx_pcr *pcr = host->pcr;
853 int err;
854
d88691be
WW		 855 if (host->power_state == SDMMC_POWER_ON)
856 return 0;
857
ff984e57
WW		 858 rtsx_pci_init_cmd(pcr);
859 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_SELECT, 0x07, SD_MOD_SEL);
860 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_SHARE_MODE,
861 CARD_SHARE_MASK, CARD_SHARE_48_SD);
862 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_EN,
863 SD_CLK_EN, SD_CLK_EN);
864 err = rtsx_pci_send_cmd(pcr, 100);
865 if (err < 0)
866 return err;
867
868 err = rtsx_pci_card_pull_ctl_enable(pcr, RTSX_SD_CARD);
869 if (err < 0)
870 return err;
871
872 err = rtsx_pci_card_power_on(pcr, RTSX_SD_CARD);
873 if (err < 0)
874 return err;
875
876 err = rtsx_pci_write_register(pcr, CARD_OE, SD_OUTPUT_EN, SD_OUTPUT_EN);
877 if (err < 0)
878 return err;
879
d88691be 880 host->power_state = SDMMC_POWER_ON;
ff984e57
WW		 881 return 0;
882}
883
884static int sd_power_off(struct realtek_pci_sdmmc *host)
885{
886 struct rtsx_pcr *pcr = host->pcr;
887 int err;
888
d88691be
WW		 889 host->power_state = SDMMC_POWER_OFF;
890
ff984e57
WW		 891 rtsx_pci_init_cmd(pcr);
892
893 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_EN, SD_CLK_EN, 0);
894 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_OE, SD_OUTPUT_EN, 0);
895
896 err = rtsx_pci_send_cmd(pcr, 100);
897 if (err < 0)
898 return err;
899
900 err = rtsx_pci_card_power_off(pcr, RTSX_SD_CARD);
901 if (err < 0)
902 return err;
903
904 return rtsx_pci_card_pull_ctl_disable(pcr, RTSX_SD_CARD);
905}
906
907static int sd_set_power_mode(struct realtek_pci_sdmmc *host,
908 unsigned char power_mode)
909{
910 int err;
911
912 if (power_mode == MMC_POWER_OFF)
913 err = sd_power_off(host);
914 else
915 err = sd_power_on(host);
916
917 return err;
918}
919
84d72f9c 920static int sd_set_timing(struct realtek_pci_sdmmc *host, unsigned char timing)
ff984e57
WW		 921{
922 struct rtsx_pcr *pcr = host->pcr;
923 int err = 0;
924
ff984e57
WW		 925 rtsx_pci_init_cmd(pcr);
926
927 switch (timing) {
928 case MMC_TIMING_UHS_SDR104:
929 case MMC_TIMING_UHS_SDR50:
930 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1,
931 0x0C | SD_ASYNC_FIFO_NOT_RST,
932 SD_30_MODE | SD_ASYNC_FIFO_NOT_RST);
933 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL,
934 CLK_LOW_FREQ, CLK_LOW_FREQ);
935 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF,
936 CRC_VAR_CLK0 | SD30_FIX_CLK | SAMPLE_VAR_CLK1);
937 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0);
938 break;
939
1a0ae377 940 case MMC_TIMING_MMC_DDR52:
ff984e57 941 case MMC_TIMING_UHS_DDR50:
ff984e57
WW		 942 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1,
943 0x0C | SD_ASYNC_FIFO_NOT_RST,
944 SD_DDR_MODE | SD_ASYNC_FIFO_NOT_RST);
945 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL,
946 CLK_LOW_FREQ, CLK_LOW_FREQ);
947 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF,
948 CRC_VAR_CLK0 | SD30_FIX_CLK | SAMPLE_VAR_CLK1);
949 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0);
950 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_PUSH_POINT_CTL,
951 DDR_VAR_TX_CMD_DAT, DDR_VAR_TX_CMD_DAT);
952 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_SAMPLE_POINT_CTL,
953 DDR_VAR_RX_DAT | DDR_VAR_RX_CMD,
954 DDR_VAR_RX_DAT | DDR_VAR_RX_CMD);
955 break;
956
957 case MMC_TIMING_MMC_HS:
958 case MMC_TIMING_SD_HS:
959 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1,
960 0x0C, SD_20_MODE);
961 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL,
962 CLK_LOW_FREQ, CLK_LOW_FREQ);
963 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF,
964 CRC_FIX_CLK | SD30_VAR_CLK0 | SAMPLE_VAR_CLK1);
965 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0);
966 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_PUSH_POINT_CTL,
967 SD20_TX_SEL_MASK, SD20_TX_14_AHEAD);
968 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_SAMPLE_POINT_CTL,
969 SD20_RX_SEL_MASK, SD20_RX_14_DELAY);
970 break;
971
972 default:
973 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
974 SD_CFG1, 0x0C, SD_20_MODE);
975 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL,
976 CLK_LOW_FREQ, CLK_LOW_FREQ);
977 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF,
978 CRC_FIX_CLK | SD30_VAR_CLK0 | SAMPLE_VAR_CLK1);
979 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0);
980 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
981 SD_PUSH_POINT_CTL, 0xFF, 0);
982 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_SAMPLE_POINT_CTL,
983 SD20_RX_SEL_MASK, SD20_RX_POS_EDGE);
984 break;
985 }
986
987 err = rtsx_pci_send_cmd(pcr, 100);
988
989 return err;
990}
991
992static void sdmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
993{
994 struct realtek_pci_sdmmc *host = mmc_priv(mmc);
995 struct rtsx_pcr *pcr = host->pcr;
996
997 if (host->eject)
998 return;
999
c3481955
WW		 1000 if (rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD))
1001 return;
1002
ff984e57
WW		 1003 mutex_lock(&pcr->pcr_mutex);
1004
1005 rtsx_pci_start_run(pcr);
1006
1007 sd_set_bus_width(host, ios->bus_width);
1008 sd_set_power_mode(host, ios->power_mode);
84d72f9c 1009 sd_set_timing(host, ios->timing);
ff984e57
WW		 1010
1011 host->vpclk = false;
1012 host->double_clk = true;
1013
1014 switch (ios->timing) {
1015 case MMC_TIMING_UHS_SDR104:
1016 case MMC_TIMING_UHS_SDR50:
1017 host->ssc_depth = RTSX_SSC_DEPTH_2M;
1018 host->vpclk = true;
1019 host->double_clk = false;
1020 break;
1a0ae377 1021 case MMC_TIMING_MMC_DDR52:
ff984e57
WW		 1022 case MMC_TIMING_UHS_DDR50:
1023 case MMC_TIMING_UHS_SDR25:
1024 host->ssc_depth = RTSX_SSC_DEPTH_1M;
1025 break;
1026 default:
1027 host->ssc_depth = RTSX_SSC_DEPTH_500K;
1028 break;
1029 }
1030
1031 host->initial_mode = (ios->clock <= 1000000) ? true : false;
1032
1033 host->clock = ios->clock;
1034 rtsx_pci_switch_clock(pcr, ios->clock, host->ssc_depth,
1035 host->initial_mode, host->double_clk, host->vpclk);
1036
1037 mutex_unlock(&pcr->pcr_mutex);
1038}
1039
1040static int sdmmc_get_ro(struct mmc_host *mmc)
1041{
1042 struct realtek_pci_sdmmc *host = mmc_priv(mmc);
1043 struct rtsx_pcr *pcr = host->pcr;
1044 int ro = 0;
1045 u32 val;
1046
1047 if (host->eject)
1048 return -ENOMEDIUM;
1049
1050 mutex_lock(&pcr->pcr_mutex);
1051
1052 rtsx_pci_start_run(pcr);
1053
1054 /* Check SD mechanical write-protect switch */
1055 val = rtsx_pci_readl(pcr, RTSX_BIPR);
1056 dev_dbg(sdmmc_dev(host), "%s: RTSX_BIPR = 0x%08x\n", __func__, val);
1057 if (val & SD_WRITE_PROTECT)
1058 ro = 1;
1059
1060 mutex_unlock(&pcr->pcr_mutex);
1061
1062 return ro;
1063}
1064
1065static int sdmmc_get_cd(struct mmc_host *mmc)
1066{
1067 struct realtek_pci_sdmmc *host = mmc_priv(mmc);
1068 struct rtsx_pcr *pcr = host->pcr;
1069 int cd = 0;
1070 u32 val;
1071
1072 if (host->eject)
1073 return -ENOMEDIUM;
1074
1075 mutex_lock(&pcr->pcr_mutex);
1076
1077 rtsx_pci_start_run(pcr);
1078
1079 /* Check SD card detect */
1080 val = rtsx_pci_card_exist(pcr);
1081 dev_dbg(sdmmc_dev(host), "%s: RTSX_BIPR = 0x%08x\n", __func__, val);
1082 if (val & SD_EXIST)
1083 cd = 1;
1084
1085 mutex_unlock(&pcr->pcr_mutex);
1086
1087 return cd;
1088}
1089
1090static int sd_wait_voltage_stable_1(struct realtek_pci_sdmmc *host)
1091{
1092 struct rtsx_pcr *pcr = host->pcr;
1093 int err;
1094 u8 stat;
1095
1096 /* Reference to Signal Voltage Switch Sequence in SD spec.
1097 * Wait for a period of time so that the card can drive SD_CMD and
1098 * SD_DAT[3:0] to low after sending back CMD11 response.
1099 */
1100 mdelay(1);
1101
1102 /* SD_CMD, SD_DAT[3:0] should be driven to low by card;
1103 * If either one of SD_CMD,SD_DAT[3:0] is not low,
1104 * abort the voltage switch sequence;
1105 */
1106 err = rtsx_pci_read_register(pcr, SD_BUS_STAT, &stat);
1107 if (err < 0)
1108 return err;
1109
1110 if (stat & (SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS |
1111 SD_DAT1_STATUS | SD_DAT0_STATUS))
1112 return -EINVAL;
1113
1114 /* Stop toggle SD clock */
1115 err = rtsx_pci_write_register(pcr, SD_BUS_STAT,
1116 0xFF, SD_CLK_FORCE_STOP);
1117 if (err < 0)
1118 return err;
1119
1120 return 0;
1121}
1122
1123static int sd_wait_voltage_stable_2(struct realtek_pci_sdmmc *host)
1124{
1125 struct rtsx_pcr *pcr = host->pcr;
1126 int err;
1127 u8 stat, mask, val;
1128
1129 /* Wait 1.8V output of voltage regulator in card stable */
1130 msleep(50);
1131
1132 /* Toggle SD clock again */
1133 err = rtsx_pci_write_register(pcr, SD_BUS_STAT, 0xFF, SD_CLK_TOGGLE_EN);
1134 if (err < 0)
1135 return err;
1136
1137 /* Wait for a period of time so that the card can drive
1138 * SD_DAT[3:0] to high at 1.8V
1139 */
1140 msleep(20);
1141
1142 /* SD_CMD, SD_DAT[3:0] should be pulled high by host */
1143 err = rtsx_pci_read_register(pcr, SD_BUS_STAT, &stat);
1144 if (err < 0)
1145 return err;
1146
1147 mask = SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS |
1148 SD_DAT1_STATUS | SD_DAT0_STATUS;
1149 val = SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS |
1150 SD_DAT1_STATUS | SD_DAT0_STATUS;
1151 if ((stat & mask) != val) {
1152 dev_dbg(sdmmc_dev(host),
1153 "%s: SD_BUS_STAT = 0x%x\n", __func__, stat);
1154 rtsx_pci_write_register(pcr, SD_BUS_STAT,
1155 SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP, 0);
1156 rtsx_pci_write_register(pcr, CARD_CLK_EN, 0xFF, 0);
1157 return -EINVAL;
1158 }
1159
1160 return 0;
1161}
1162
ff984e57
WW		 1163static int sdmmc_switch_voltage(struct mmc_host *mmc, struct mmc_ios *ios)
1164{
1165 struct realtek_pci_sdmmc *host = mmc_priv(mmc);
1166 struct rtsx_pcr *pcr = host->pcr;
1167 int err = 0;
1168 u8 voltage;
1169
1170 dev_dbg(sdmmc_dev(host), "%s: signal_voltage = %d\n",
1171 __func__, ios->signal_voltage);
1172
1173 if (host->eject)
1174 return -ENOMEDIUM;
1175
c3481955
WW		 1176 err = rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD);
1177 if (err)
1178 return err;
1179
ff984e57
WW		 1180 mutex_lock(&pcr->pcr_mutex);
1181
1182 rtsx_pci_start_run(pcr);
1183
1184 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330)
ef85e736 1185 voltage = OUTPUT_3V3;
ff984e57 1186 else
ef85e736 1187 voltage = OUTPUT_1V8;
ff984e57 1188
ef85e736 1189 if (voltage == OUTPUT_1V8) {
ff984e57
WW		 1190 err = sd_wait_voltage_stable_1(host);
1191 if (err < 0)
1192 goto out;
1193 }
1194
ef85e736 1195 err = rtsx_pci_switch_output_voltage(pcr, voltage);
ff984e57
WW		 1196 if (err < 0)
1197 goto out;
1198
ef85e736 1199 if (voltage == OUTPUT_1V8) {
ff984e57
WW		 1200 err = sd_wait_voltage_stable_2(host);
1201 if (err < 0)
1202 goto out;
1203 }
1204
1b8055b4 1205out:
ff984e57
WW		 1206 /* Stop toggle SD clock in idle */
1207 err = rtsx_pci_write_register(pcr, SD_BUS_STAT,
1208 SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP, 0);
1209
ff984e57
WW		 1210 mutex_unlock(&pcr->pcr_mutex);
1211
1212 return err;
1213}
1214
1215static int sdmmc_execute_tuning(struct mmc_host *mmc, u32 opcode)
1216{
1217 struct realtek_pci_sdmmc *host = mmc_priv(mmc);
1218 struct rtsx_pcr *pcr = host->pcr;
1219 int err = 0;
1220
1221 if (host->eject)
1222 return -ENOMEDIUM;
1223
c3481955
WW		 1224 err = rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD);
1225 if (err)
1226 return err;
1227
ff984e57
WW		 1228 mutex_lock(&pcr->pcr_mutex);
1229
1230 rtsx_pci_start_run(pcr);
1231
84d72f9c
WW		 1232 /* Set initial TX phase */
1233 switch (mmc->ios.timing) {
1234 case MMC_TIMING_UHS_SDR104:
1235 err = sd_change_phase(host, SDR104_TX_PHASE(pcr), false);
1236 break;
1237
1238 case MMC_TIMING_UHS_SDR50:
1239 err = sd_change_phase(host, SDR50_TX_PHASE(pcr), false);
1240 break;
1241
1242 case MMC_TIMING_UHS_DDR50:
1243 err = sd_change_phase(host, DDR50_TX_PHASE(pcr), false);
1244 break;
1245
1246 default:
1247 err = 0;
1248 }
ff984e57 1249
84d72f9c
WW		 1250 if (err)
1251 goto out;
1252
1253 /* Tuning RX phase */
1254 if ((mmc->ios.timing == MMC_TIMING_UHS_SDR104) ||
1255 (mmc->ios.timing == MMC_TIMING_UHS_SDR50))
1256 err = sd_tuning_rx(host, opcode);
1257 else if (mmc->ios.timing == MMC_TIMING_UHS_DDR50)
1258 err = sd_change_phase(host, DDR50_RX_PHASE(pcr), true);
1259
1260out:
ff984e57
WW		 1261 mutex_unlock(&pcr->pcr_mutex);
1262
1263 return err;
1264}
1265
1266static const struct mmc_host_ops realtek_pci_sdmmc_ops = {
6291e715
MC		 1267 .pre_req = sdmmc_pre_req,
1268 .post_req = sdmmc_post_req,
ff984e57
WW		 1269 .request = sdmmc_request,
1270 .set_ios = sdmmc_set_ios,
1271 .get_ro = sdmmc_get_ro,
1272 .get_cd = sdmmc_get_cd,
1273 .start_signal_voltage_switch = sdmmc_switch_voltage,
1274 .execute_tuning = sdmmc_execute_tuning,
1275};
1276
ff984e57
WW		 1277static void init_extra_caps(struct realtek_pci_sdmmc *host)
1278{
1279 struct mmc_host *mmc = host->mmc;
1280 struct rtsx_pcr *pcr = host->pcr;
1281
1282 dev_dbg(sdmmc_dev(host), "pcr->extra_caps = 0x%x\n", pcr->extra_caps);
1283
1284 if (pcr->extra_caps & EXTRA_CAPS_SD_SDR50)
1285 mmc->caps |= MMC_CAP_UHS_SDR50;
1286 if (pcr->extra_caps & EXTRA_CAPS_SD_SDR104)
1287 mmc->caps |= MMC_CAP_UHS_SDR104;
1288 if (pcr->extra_caps & EXTRA_CAPS_SD_DDR50)
1289 mmc->caps |= MMC_CAP_UHS_DDR50;
1290 if (pcr->extra_caps & EXTRA_CAPS_MMC_HSDDR)
1291 mmc->caps |= MMC_CAP_1_8V_DDR;
1292 if (pcr->extra_caps & EXTRA_CAPS_MMC_8BIT)
1293 mmc->caps |= MMC_CAP_8_BIT_DATA;
1294}
1295
1296static void realtek_init_host(struct realtek_pci_sdmmc *host)
1297{
1298 struct mmc_host *mmc = host->mmc;
1299
1300 mmc->f_min = 250000;
1301 mmc->f_max = 208000000;
1302 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
1303 mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SD_HIGHSPEED |
1304 MMC_CAP_MMC_HIGHSPEED | MMC_CAP_BUS_WIDTH_TEST |
1305 MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;
517bf80f 1306 mmc->caps2 = MMC_CAP2_NO_PRESCAN_POWERUP | MMC_CAP2_FULL_PWR_CYCLE;
ff984e57
WW		 1307 mmc->max_current_330 = 400;
1308 mmc->max_current_180 = 800;
1309 mmc->ops = &realtek_pci_sdmmc_ops;
1310
1311 init_extra_caps(host);
1312
1313 mmc->max_segs = 256;
1314 mmc->max_seg_size = 65536;
1315 mmc->max_blk_size = 512;
1316 mmc->max_blk_count = 65535;
1317 mmc->max_req_size = 524288;
1318}
1319
1320static void rtsx_pci_sdmmc_card_event(struct platform_device *pdev)
1321{
1322 struct realtek_pci_sdmmc *host = platform_get_drvdata(pdev);
1323
1324 mmc_detect_change(host->mmc, 0);
1325}
1326
1327static int rtsx_pci_sdmmc_drv_probe(struct platform_device *pdev)
1328{
1329 struct mmc_host *mmc;
1330 struct realtek_pci_sdmmc *host;
1331 struct rtsx_pcr *pcr;
1332 struct pcr_handle *handle = pdev->dev.platform_data;
1333
1334 if (!handle)
1335 return -ENXIO;
1336
1337 pcr = handle->pcr;
1338 if (!pcr)
1339 return -ENXIO;
1340
1341 dev_dbg(&(pdev->dev), ": Realtek PCI-E SDMMC controller found\n");
1342
1343 mmc = mmc_alloc_host(sizeof(*host), &pdev->dev);
1344 if (!mmc)
1345 return -ENOMEM;
1346
1347 host = mmc_priv(mmc);
6291e715
MC		 1348 host->workq = create_singlethread_workqueue(SDMMC_WORKQ_NAME);
1349 if (!host->workq) {
1350 mmc_free_host(mmc);
1351 return -ENOMEM;
1352 }
ff984e57
WW		 1353 host->pcr = pcr;
1354 host->mmc = mmc;
1355 host->pdev = pdev;
d88691be 1356 host->power_state = SDMMC_POWER_OFF;
6291e715 1357 INIT_WORK(&host->work, sd_request);
ff984e57
WW		 1358 platform_set_drvdata(pdev, host);
1359 pcr->slots[RTSX_SD_CARD].p_dev = pdev;
1360 pcr->slots[RTSX_SD_CARD].card_event = rtsx_pci_sdmmc_card_event;
1361
98fcc576 1362 mutex_init(&host->host_mutex);
ff984e57
WW		 1363
1364 realtek_init_host(host);
1365
1366 mmc_add_host(mmc);
1367
1368 return 0;
1369}
1370
1371static int rtsx_pci_sdmmc_drv_remove(struct platform_device *pdev)
1372{
1373 struct realtek_pci_sdmmc *host = platform_get_drvdata(pdev);
1374 struct rtsx_pcr *pcr;
1375 struct mmc_host *mmc;
1376
1377 if (!host)
1378 return 0;
1379
1380 pcr = host->pcr;
1381 pcr->slots[RTSX_SD_CARD].p_dev = NULL;
1382 pcr->slots[RTSX_SD_CARD].card_event = NULL;
1383 mmc = host->mmc;
ff984e57 1384
6291e715
MC		 1385 cancel_work_sync(&host->work);
1386
98fcc576 1387 mutex_lock(&host->host_mutex);
ff984e57
WW		 1388 if (host->mrq) {
1389 dev_dbg(&(pdev->dev),
1390 "%s: Controller removed during transfer\n",
1391 mmc_hostname(mmc));
1392
98fcc576 1393 rtsx_pci_complete_unfinished_transfer(pcr);
ff984e57 1394
98fcc576
MC		 1395 host->mrq->cmd->error = -ENOMEDIUM;
1396 if (host->mrq->stop)
1397 host->mrq->stop->error = -ENOMEDIUM;
1398 mmc_request_done(mmc, host->mrq);
ff984e57 1399 }
98fcc576 1400 mutex_unlock(&host->host_mutex);
ff984e57
WW		 1401
1402 mmc_remove_host(mmc);
640e09bc
MC		 1403 host->eject = true;
1404
6291e715
MC		 1405 flush_workqueue(host->workq);
1406 destroy_workqueue(host->workq);
1407 host->workq = NULL;
1408
ff984e57
WW		 1409 mmc_free_host(mmc);
1410
ff984e57
WW		 1411 dev_dbg(&(pdev->dev),
1412 ": Realtek PCI-E SDMMC controller has been removed\n");
1413
1414 return 0;
1415}
1416
1417static struct platform_device_id rtsx_pci_sdmmc_ids[] = {
1418 {
1419 .name = DRV_NAME_RTSX_PCI_SDMMC,
1420 }, {
1421 /* sentinel */
1422 }
1423};
1424MODULE_DEVICE_TABLE(platform, rtsx_pci_sdmmc_ids);
1425
1426static struct platform_driver rtsx_pci_sdmmc_driver = {
1427 .probe = rtsx_pci_sdmmc_drv_probe,
1428 .remove = rtsx_pci_sdmmc_drv_remove,
1429 .id_table = rtsx_pci_sdmmc_ids,
ff984e57 1430 .driver = {
ff984e57
WW		 1431 .name = DRV_NAME_RTSX_PCI_SDMMC,
1432 },
1433};
1434module_platform_driver(rtsx_pci_sdmmc_driver);
1435
1436MODULE_LICENSE("GPL");
1437MODULE_AUTHOR("Wei WANG <wei_wang@realsil.com.cn>");
1438MODULE_DESCRIPTION("Realtek PCI-E SD/MMC Card Host Driver");
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