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mfd: mmc: rtsx: Change default tx phase
[mirror_ubuntu-focal-kernel.git] / drivers / mmc / host / rtsx_pci_sdmmc.c
CommitLineData
ff984e57
WW		 1/* Realtek PCI-Express SD/MMC Card Interface driver
2 *
3 * Copyright(c) 2009 Realtek Semiconductor Corp. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2, or (at your option) any
8 * later version.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, see <http://www.gnu.org/licenses/>.
17 *
18 * Author:
19 * Wei WANG <wei_wang@realsil.com.cn>
20 * No. 450, Shenhu Road, Suzhou Industry Park, Suzhou, China
21 */
22
23#include <linux/module.h>
433e075c 24#include <linux/slab.h>
ff984e57
WW		 25#include <linux/highmem.h>
26#include <linux/delay.h>
27#include <linux/platform_device.h>
28#include <linux/mmc/host.h>
29#include <linux/mmc/mmc.h>
30#include <linux/mmc/sd.h>
31#include <linux/mmc/card.h>
32#include <linux/mfd/rtsx_pci.h>
33#include <asm/unaligned.h>
34
35/* SD Tuning Data Structure
36 * Record continuous timing phase path
37 */
38struct timing_phase_path {
39 int start;
40 int end;
41 int mid;
42 int len;
43};
44
45struct realtek_pci_sdmmc {
46 struct platform_device *pdev;
47 struct rtsx_pcr *pcr;
48 struct mmc_host *mmc;
49 struct mmc_request *mrq;
50
51 struct mutex host_mutex;
52
53 u8 ssc_depth;
54 unsigned int clock;
55 bool vpclk;
56 bool double_clk;
57 bool eject;
58 bool initial_mode;
d88691be
WW		 59 int power_state;
60#define SDMMC_POWER_ON 1
61#define SDMMC_POWER_OFF 0
ff984e57
WW		 62};
63
64static inline struct device *sdmmc_dev(struct realtek_pci_sdmmc *host)
65{
66 return &(host->pdev->dev);
67}
68
69static inline void sd_clear_error(struct realtek_pci_sdmmc *host)
70{
71 rtsx_pci_write_register(host->pcr, CARD_STOP,
72 SD_STOP | SD_CLR_ERR, SD_STOP | SD_CLR_ERR);
73}
74
75#ifdef DEBUG
76static void sd_print_debug_regs(struct realtek_pci_sdmmc *host)
77{
78 struct rtsx_pcr *pcr = host->pcr;
79 u16 i;
80 u8 *ptr;
81
82 /* Print SD host internal registers */
83 rtsx_pci_init_cmd(pcr);
84 for (i = 0xFDA0; i <= 0xFDAE; i++)
85 rtsx_pci_add_cmd(pcr, READ_REG_CMD, i, 0, 0);
86 for (i = 0xFD52; i <= 0xFD69; i++)
87 rtsx_pci_add_cmd(pcr, READ_REG_CMD, i, 0, 0);
88 rtsx_pci_send_cmd(pcr, 100);
89
90 ptr = rtsx_pci_get_cmd_data(pcr);
91 for (i = 0xFDA0; i <= 0xFDAE; i++)
92 dev_dbg(sdmmc_dev(host), "0x%04X: 0x%02x\n", i, *(ptr++));
93 for (i = 0xFD52; i <= 0xFD69; i++)
94 dev_dbg(sdmmc_dev(host), "0x%04X: 0x%02x\n", i, *(ptr++));
95}
96#else
97#define sd_print_debug_regs(host)
98#endif /* DEBUG */
99
100static int sd_read_data(struct realtek_pci_sdmmc *host, u8 *cmd, u16 byte_cnt,
101 u8 *buf, int buf_len, int timeout)
102{
103 struct rtsx_pcr *pcr = host->pcr;
104 int err, i;
105 u8 trans_mode;
106
107 dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD%d\n", __func__, cmd[0] - 0x40);
108
109 if (!buf)
110 buf_len = 0;
111
112 if ((cmd[0] & 0x3F) == MMC_SEND_TUNING_BLOCK)
113 trans_mode = SD_TM_AUTO_TUNING;
114 else
115 trans_mode = SD_TM_NORMAL_READ;
116
117 rtsx_pci_init_cmd(pcr);
118
119 for (i = 0; i < 5; i++)
120 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CMD0 + i, 0xFF, cmd[i]);
121
122 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BYTE_CNT_L, 0xFF, (u8)byte_cnt);
123 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BYTE_CNT_H,
124 0xFF, (u8)(byte_cnt >> 8));
125 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BLOCK_CNT_L, 0xFF, 1);
126 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BLOCK_CNT_H, 0xFF, 0);
127
128 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF,
129 SD_CALCULATE_CRC7 | SD_CHECK_CRC16 |
130 SD_NO_WAIT_BUSY_END | SD_CHECK_CRC7 | SD_RSP_LEN_6);
131 if (trans_mode != SD_TM_AUTO_TUNING)
132 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
133 CARD_DATA_SOURCE, 0x01, PINGPONG_BUFFER);
134
135 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER,
136 0xFF, trans_mode | SD_TRANSFER_START);
137 rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER,
138 SD_TRANSFER_END, SD_TRANSFER_END);
139
140 err = rtsx_pci_send_cmd(pcr, timeout);
141 if (err < 0) {
142 sd_print_debug_regs(host);
143 dev_dbg(sdmmc_dev(host),
144 "rtsx_pci_send_cmd fail (err = %d)\n", err);
145 return err;
146 }
147
148 if (buf && buf_len) {
149 err = rtsx_pci_read_ppbuf(pcr, buf, buf_len);
150 if (err < 0) {
151 dev_dbg(sdmmc_dev(host),
152 "rtsx_pci_read_ppbuf fail (err = %d)\n", err);
153 return err;
154 }
155 }
156
157 return 0;
158}
159
160static int sd_write_data(struct realtek_pci_sdmmc *host, u8 *cmd, u16 byte_cnt,
161 u8 *buf, int buf_len, int timeout)
162{
163 struct rtsx_pcr *pcr = host->pcr;
164 int err, i;
165 u8 trans_mode;
166
167 if (!buf)
168 buf_len = 0;
169
170 if (buf && buf_len) {
171 err = rtsx_pci_write_ppbuf(pcr, buf, buf_len);
172 if (err < 0) {
173 dev_dbg(sdmmc_dev(host),
174 "rtsx_pci_write_ppbuf fail (err = %d)\n", err);
175 return err;
176 }
177 }
178
179 trans_mode = cmd ? SD_TM_AUTO_WRITE_2 : SD_TM_AUTO_WRITE_3;
180 rtsx_pci_init_cmd(pcr);
181
182 if (cmd) {
183 dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD %d\n", __func__,
184 cmd[0] - 0x40);
185
186 for (i = 0; i < 5; i++)
187 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
188 SD_CMD0 + i, 0xFF, cmd[i]);
189 }
190
191 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BYTE_CNT_L, 0xFF, (u8)byte_cnt);
192 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BYTE_CNT_H,
193 0xFF, (u8)(byte_cnt >> 8));
194 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BLOCK_CNT_L, 0xFF, 1);
195 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BLOCK_CNT_H, 0xFF, 0);
196
197 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF,
198 SD_CALCULATE_CRC7 | SD_CHECK_CRC16 |
199 SD_NO_WAIT_BUSY_END | SD_CHECK_CRC7 | SD_RSP_LEN_6);
200
201 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER, 0xFF,
202 trans_mode | SD_TRANSFER_START);
203 rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER,
204 SD_TRANSFER_END, SD_TRANSFER_END);
205
206 err = rtsx_pci_send_cmd(pcr, timeout);
207 if (err < 0) {
208 sd_print_debug_regs(host);
209 dev_dbg(sdmmc_dev(host),
210 "rtsx_pci_send_cmd fail (err = %d)\n", err);
211 return err;
212 }
213
214 return 0;
215}
216
217static void sd_send_cmd_get_rsp(struct realtek_pci_sdmmc *host,
218 struct mmc_command *cmd)
219{
220 struct rtsx_pcr *pcr = host->pcr;
221 u8 cmd_idx = (u8)cmd->opcode;
222 u32 arg = cmd->arg;
223 int err = 0;
224 int timeout = 100;
225 int i;
226 u8 *ptr;
227 int stat_idx = 0;
228 u8 rsp_type;
229 int rsp_len = 5;
230
231 dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD %d, arg = 0x%08x\n",
232 __func__, cmd_idx, arg);
233
234 /* Response type:
235 * R0
236 * R1, R5, R6, R7
237 * R1b
238 * R2
239 * R3, R4
240 */
241 switch (mmc_resp_type(cmd)) {
242 case MMC_RSP_NONE:
243 rsp_type = SD_RSP_TYPE_R0;
244 rsp_len = 0;
245 break;
246 case MMC_RSP_R1:
247 rsp_type = SD_RSP_TYPE_R1;
248 break;
249 case MMC_RSP_R1B:
250 rsp_type = SD_RSP_TYPE_R1b;
251 break;
252 case MMC_RSP_R2:
253 rsp_type = SD_RSP_TYPE_R2;
254 rsp_len = 16;
255 break;
256 case MMC_RSP_R3:
257 rsp_type = SD_RSP_TYPE_R3;
258 break;
259 default:
260 dev_dbg(sdmmc_dev(host), "cmd->flag is not valid\n");
261 err = -EINVAL;
262 goto out;
263 }
264
265 if (rsp_type == SD_RSP_TYPE_R1b)
266 timeout = 3000;
267
268 if (cmd->opcode == SD_SWITCH_VOLTAGE) {
269 err = rtsx_pci_write_register(pcr, SD_BUS_STAT,
270 0xFF, SD_CLK_TOGGLE_EN);
271 if (err < 0)
272 goto out;
273 }
274
275 rtsx_pci_init_cmd(pcr);
276
277 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CMD0, 0xFF, 0x40 | cmd_idx);
278 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CMD1, 0xFF, (u8)(arg >> 24));
279 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CMD2, 0xFF, (u8)(arg >> 16));
280 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CMD3, 0xFF, (u8)(arg >> 8));
281 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CMD4, 0xFF, (u8)arg);
282
283 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF, rsp_type);
284 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_DATA_SOURCE,
285 0x01, PINGPONG_BUFFER);
286 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER,
287 0xFF, SD_TM_CMD_RSP | SD_TRANSFER_START);
288 rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER,
289 SD_TRANSFER_END | SD_STAT_IDLE,
290 SD_TRANSFER_END | SD_STAT_IDLE);
291
292 if (rsp_type == SD_RSP_TYPE_R2) {
293 /* Read data from ping-pong buffer */
294 for (i = PPBUF_BASE2; i < PPBUF_BASE2 + 16; i++)
295 rtsx_pci_add_cmd(pcr, READ_REG_CMD, (u16)i, 0, 0);
296 stat_idx = 16;
297 } else if (rsp_type != SD_RSP_TYPE_R0) {
298 /* Read data from SD_CMDx registers */
299 for (i = SD_CMD0; i <= SD_CMD4; i++)
300 rtsx_pci_add_cmd(pcr, READ_REG_CMD, (u16)i, 0, 0);
301 stat_idx = 5;
302 }
303
304 rtsx_pci_add_cmd(pcr, READ_REG_CMD, SD_STAT1, 0, 0);
305
306 err = rtsx_pci_send_cmd(pcr, timeout);
307 if (err < 0) {
308 sd_print_debug_regs(host);
309 sd_clear_error(host);
310 dev_dbg(sdmmc_dev(host),
311 "rtsx_pci_send_cmd error (err = %d)\n", err);
312 goto out;
313 }
314
315 if (rsp_type == SD_RSP_TYPE_R0) {
316 err = 0;
317 goto out;
318 }
319
320 /* Eliminate returned value of CHECK_REG_CMD */
321 ptr = rtsx_pci_get_cmd_data(pcr) + 1;
322
323 /* Check (Start,Transmission) bit of Response */
324 if ((ptr[0] & 0xC0) != 0) {
325 err = -EILSEQ;
326 dev_dbg(sdmmc_dev(host), "Invalid response bit\n");
327 goto out;
328 }
329
330 /* Check CRC7 */
331 if (!(rsp_type & SD_NO_CHECK_CRC7)) {
332 if (ptr[stat_idx] & SD_CRC7_ERR) {
333 err = -EILSEQ;
334 dev_dbg(sdmmc_dev(host), "CRC7 error\n");
335 goto out;
336 }
337 }
338
339 if (rsp_type == SD_RSP_TYPE_R2) {
340 for (i = 0; i < 4; i++) {
341 cmd->resp[i] = get_unaligned_be32(ptr + 1 + i * 4);
342 dev_dbg(sdmmc_dev(host), "cmd->resp[%d] = 0x%08x\n",
343 i, cmd->resp[i]);
344 }
345 } else {
346 cmd->resp[0] = get_unaligned_be32(ptr + 1);
347 dev_dbg(sdmmc_dev(host), "cmd->resp[0] = 0x%08x\n",
348 cmd->resp[0]);
349 }
350
351out:
352 cmd->error = err;
353}
354
355static int sd_rw_multi(struct realtek_pci_sdmmc *host, struct mmc_request *mrq)
356{
357 struct rtsx_pcr *pcr = host->pcr;
358 struct mmc_host *mmc = host->mmc;
359 struct mmc_card *card = mmc->card;
360 struct mmc_data *data = mrq->data;
361 int uhs = mmc_sd_card_uhs(card);
362 int read = (data->flags & MMC_DATA_READ) ? 1 : 0;
363 u8 cfg2, trans_mode;
364 int err;
365 size_t data_len = data->blksz * data->blocks;
366
367 if (read) {
368 cfg2 = SD_CALCULATE_CRC7 | SD_CHECK_CRC16 |
369 SD_NO_WAIT_BUSY_END | SD_CHECK_CRC7 | SD_RSP_LEN_0;
370 trans_mode = SD_TM_AUTO_READ_3;
371 } else {
372 cfg2 = SD_NO_CALCULATE_CRC7 | SD_CHECK_CRC16 |
373 SD_NO_WAIT_BUSY_END | SD_NO_CHECK_CRC7 | SD_RSP_LEN_0;
374 trans_mode = SD_TM_AUTO_WRITE_3;
375 }
376
377 if (!uhs)
378 cfg2 |= SD_NO_CHECK_WAIT_CRC_TO;
379
380 rtsx_pci_init_cmd(pcr);
381
382 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BYTE_CNT_L, 0xFF, 0x00);
383 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BYTE_CNT_H, 0xFF, 0x02);
384 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BLOCK_CNT_L,
385 0xFF, (u8)data->blocks);
386 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BLOCK_CNT_H,
387 0xFF, (u8)(data->blocks >> 8));
ff984e57
WW		 388
389 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, IRQSTAT0,
390 DMA_DONE_INT, DMA_DONE_INT);
391 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC3,
392 0xFF, (u8)(data_len >> 24));
393 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC2,
394 0xFF, (u8)(data_len >> 16));
395 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC1,
396 0xFF, (u8)(data_len >> 8));
397 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC0, 0xFF, (u8)data_len);
398 if (read) {
399 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMACTL,
400 0x03 | DMA_PACK_SIZE_MASK,
401 DMA_DIR_FROM_CARD | DMA_EN | DMA_512);
402 } else {
403 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMACTL,
404 0x03 | DMA_PACK_SIZE_MASK,
405 DMA_DIR_TO_CARD | DMA_EN | DMA_512);
406 }
407
408 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_DATA_SOURCE,
409 0x01, RING_BUFFER);
410
38d324df 411 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF, cfg2);
ff984e57
WW		 412 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER, 0xFF,
413 trans_mode | SD_TRANSFER_START);
414 rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER,
415 SD_TRANSFER_END, SD_TRANSFER_END);
416
417 rtsx_pci_send_cmd_no_wait(pcr);
418
419 err = rtsx_pci_transfer_data(pcr, data->sg, data->sg_len, read, 10000);
420 if (err < 0) {
421 sd_clear_error(host);
422 return err;
423 }
424
425 return 0;
426}
427
428static inline void sd_enable_initial_mode(struct realtek_pci_sdmmc *host)
429{
430 rtsx_pci_write_register(host->pcr, SD_CFG1,
431 SD_CLK_DIVIDE_MASK, SD_CLK_DIVIDE_128);
432}
433
434static inline void sd_disable_initial_mode(struct realtek_pci_sdmmc *host)
435{
436 rtsx_pci_write_register(host->pcr, SD_CFG1,
437 SD_CLK_DIVIDE_MASK, SD_CLK_DIVIDE_0);
438}
439
440static void sd_normal_rw(struct realtek_pci_sdmmc *host,
441 struct mmc_request *mrq)
442{
443 struct mmc_command *cmd = mrq->cmd;
444 struct mmc_data *data = mrq->data;
445 u8 _cmd[5], *buf;
446
447 _cmd[0] = 0x40 | (u8)cmd->opcode;
448 put_unaligned_be32(cmd->arg, (u32 *)(&_cmd[1]));
449
450 buf = kzalloc(data->blksz, GFP_NOIO);
451 if (!buf) {
452 cmd->error = -ENOMEM;
453 return;
454 }
455
456 if (data->flags & MMC_DATA_READ) {
457 if (host->initial_mode)
458 sd_disable_initial_mode(host);
459
460 cmd->error = sd_read_data(host, _cmd, (u16)data->blksz, buf,
461 data->blksz, 200);
462
463 if (host->initial_mode)
464 sd_enable_initial_mode(host);
465
466 sg_copy_from_buffer(data->sg, data->sg_len, buf, data->blksz);
467 } else {
468 sg_copy_to_buffer(data->sg, data->sg_len, buf, data->blksz);
469
470 cmd->error = sd_write_data(host, _cmd, (u16)data->blksz, buf,
471 data->blksz, 200);
472 }
473
474 kfree(buf);
475}
476
84d72f9c
WW		 477static int sd_change_phase(struct realtek_pci_sdmmc *host,
478 u8 sample_point, bool rx)
ff984e57
WW		 479{
480 struct rtsx_pcr *pcr = host->pcr;
481 int err;
482
84d72f9c
WW		 483 dev_dbg(sdmmc_dev(host), "%s(%s): sample_point = %d\n",
484 __func__, rx ? "RX" : "TX", sample_point);
ff984e57
WW		 485
486 rtsx_pci_init_cmd(pcr);
487
488 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CHANGE_CLK, CHANGE_CLK);
84d72f9c
WW		 489 if (rx)
490 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
491 SD_VPRX_CTL, 0x1F, sample_point);
492 else
493 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
494 SD_VPTX_CTL, 0x1F, sample_point);
ff984e57
WW		 495 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL, PHASE_NOT_RESET, 0);
496 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL,
497 PHASE_NOT_RESET, PHASE_NOT_RESET);
498 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CHANGE_CLK, 0);
499 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1, SD_ASYNC_FIFO_NOT_RST, 0);
500
501 err = rtsx_pci_send_cmd(pcr, 100);
502 if (err < 0)
503 return err;
504
505 return 0;
506}
507
508static u8 sd_search_final_phase(struct realtek_pci_sdmmc *host, u32 phase_map)
509{
510 struct timing_phase_path path[MAX_PHASE + 1];
511 int i, j, cont_path_cnt;
512 int new_block, max_len, final_path_idx;
513 u8 final_phase = 0xFF;
514
515 /* Parse phase_map, take it as a bit-ring */
516 cont_path_cnt = 0;
517 new_block = 1;
518 j = 0;
519 for (i = 0; i < MAX_PHASE + 1; i++) {
520 if (phase_map & (1 << i)) {
521 if (new_block) {
522 new_block = 0;
523 j = cont_path_cnt++;
524 path[j].start = i;
525 path[j].end = i;
526 } else {
527 path[j].end = i;
528 }
529 } else {
530 new_block = 1;
531 if (cont_path_cnt) {
532 /* Calculate path length and middle point */
533 int idx = cont_path_cnt - 1;
534 path[idx].len =
535 path[idx].end - path[idx].start + 1;
536 path[idx].mid =
537 path[idx].start + path[idx].len / 2;
538 }
539 }
540 }
541
542 if (cont_path_cnt == 0) {
543 dev_dbg(sdmmc_dev(host), "No continuous phase path\n");
544 goto finish;
545 } else {
546 /* Calculate last continuous path length and middle point */
547 int idx = cont_path_cnt - 1;
548 path[idx].len = path[idx].end - path[idx].start + 1;
549 path[idx].mid = path[idx].start + path[idx].len / 2;
550 }
551
552 /* Connect the first and last continuous paths if they are adjacent */
553 if (!path[0].start && (path[cont_path_cnt - 1].end == MAX_PHASE)) {
554 /* Using negative index */
555 path[0].start = path[cont_path_cnt - 1].start - MAX_PHASE - 1;
556 path[0].len += path[cont_path_cnt - 1].len;
557 path[0].mid = path[0].start + path[0].len / 2;
558 /* Convert negative middle point index to positive one */
559 if (path[0].mid < 0)
560 path[0].mid += MAX_PHASE + 1;
561 cont_path_cnt--;
562 }
563
564 /* Choose the longest continuous phase path */
565 max_len = 0;
566 final_phase = 0;
567 final_path_idx = 0;
568 for (i = 0; i < cont_path_cnt; i++) {
569 if (path[i].len > max_len) {
570 max_len = path[i].len;
571 final_phase = (u8)path[i].mid;
572 final_path_idx = i;
573 }
574
575 dev_dbg(sdmmc_dev(host), "path[%d].start = %d\n",
576 i, path[i].start);
577 dev_dbg(sdmmc_dev(host), "path[%d].end = %d\n",
578 i, path[i].end);
579 dev_dbg(sdmmc_dev(host), "path[%d].len = %d\n",
580 i, path[i].len);
581 dev_dbg(sdmmc_dev(host), "path[%d].mid = %d\n",
582 i, path[i].mid);
583 }
584
585finish:
586 dev_dbg(sdmmc_dev(host), "Final chosen phase: %d\n", final_phase);
587 return final_phase;
588}
589
590static void sd_wait_data_idle(struct realtek_pci_sdmmc *host)
591{
592 int err, i;
593 u8 val = 0;
594
595 for (i = 0; i < 100; i++) {
596 err = rtsx_pci_read_register(host->pcr, SD_DATA_STATE, &val);
597 if (val & SD_DATA_IDLE)
598 return;
599
600 udelay(100);
601 }
602}
603
604static int sd_tuning_rx_cmd(struct realtek_pci_sdmmc *host,
605 u8 opcode, u8 sample_point)
606{
607 int err;
608 u8 cmd[5] = {0};
609
84d72f9c 610 err = sd_change_phase(host, sample_point, true);
ff984e57
WW		 611 if (err < 0)
612 return err;
613
614 cmd[0] = 0x40 | opcode;
615 err = sd_read_data(host, cmd, 0x40, NULL, 0, 100);
616 if (err < 0) {
617 /* Wait till SD DATA IDLE */
618 sd_wait_data_idle(host);
619 sd_clear_error(host);
620 return err;
621 }
622
623 return 0;
624}
625
626static int sd_tuning_phase(struct realtek_pci_sdmmc *host,
627 u8 opcode, u32 *phase_map)
628{
629 int err, i;
630 u32 raw_phase_map = 0;
631
632 for (i = MAX_PHASE; i >= 0; i--) {
633 err = sd_tuning_rx_cmd(host, opcode, (u8)i);
634 if (err == 0)
635 raw_phase_map |= 1 << i;
636 }
637
638 if (phase_map)
639 *phase_map = raw_phase_map;
640
641 return 0;
642}
643
644static int sd_tuning_rx(struct realtek_pci_sdmmc *host, u8 opcode)
645{
646 int err, i;
647 u32 raw_phase_map[RX_TUNING_CNT] = {0}, phase_map;
648 u8 final_phase;
649
650 for (i = 0; i < RX_TUNING_CNT; i++) {
651 err = sd_tuning_phase(host, opcode, &(raw_phase_map[i]));
652 if (err < 0)
653 return err;
654
655 if (raw_phase_map[i] == 0)
656 break;
657 }
658
659 phase_map = 0xFFFFFFFF;
660 for (i = 0; i < RX_TUNING_CNT; i++) {
661 dev_dbg(sdmmc_dev(host), "RX raw_phase_map[%d] = 0x%08x\n",
662 i, raw_phase_map[i]);
663 phase_map &= raw_phase_map[i];
664 }
665 dev_dbg(sdmmc_dev(host), "RX phase_map = 0x%08x\n", phase_map);
666
667 if (phase_map) {
668 final_phase = sd_search_final_phase(host, phase_map);
669 if (final_phase == 0xFF)
670 return -EINVAL;
671
84d72f9c 672 err = sd_change_phase(host, final_phase, true);
ff984e57
WW		 673 if (err < 0)
674 return err;
675 } else {
676 return -EINVAL;
677 }
678
679 return 0;
680}
681
682static void sdmmc_request(struct mmc_host *mmc, struct mmc_request *mrq)
683{
684 struct realtek_pci_sdmmc *host = mmc_priv(mmc);
685 struct rtsx_pcr *pcr = host->pcr;
686 struct mmc_command *cmd = mrq->cmd;
687 struct mmc_data *data = mrq->data;
688 unsigned int data_size = 0;
c3481955 689 int err;
ff984e57
WW		 690
691 if (host->eject) {
692 cmd->error = -ENOMEDIUM;
693 goto finish;
694 }
695
c3481955
WW		 696 err = rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD);
697 if (err) {
698 cmd->error = err;
699 goto finish;
700 }
701
ff984e57
WW		 702 mutex_lock(&pcr->pcr_mutex);
703
704 rtsx_pci_start_run(pcr);
705
706 rtsx_pci_switch_clock(pcr, host->clock, host->ssc_depth,
707 host->initial_mode, host->double_clk, host->vpclk);
708 rtsx_pci_write_register(pcr, CARD_SELECT, 0x07, SD_MOD_SEL);
709 rtsx_pci_write_register(pcr, CARD_SHARE_MODE,
710 CARD_SHARE_MASK, CARD_SHARE_48_SD);
711
712 mutex_lock(&host->host_mutex);
713 host->mrq = mrq;
714 mutex_unlock(&host->host_mutex);
715
716 if (mrq->data)
717 data_size = data->blocks * data->blksz;
718
719 if (!data_size || mmc_op_multi(cmd->opcode) ||
720 (cmd->opcode == MMC_READ_SINGLE_BLOCK) ||
721 (cmd->opcode == MMC_WRITE_BLOCK)) {
722 sd_send_cmd_get_rsp(host, cmd);
723
724 if (!cmd->error && data_size) {
725 sd_rw_multi(host, mrq);
726
727 if (mmc_op_multi(cmd->opcode) && mrq->stop)
728 sd_send_cmd_get_rsp(host, mrq->stop);
729 }
730 } else {
731 sd_normal_rw(host, mrq);
732 }
733
734 if (mrq->data) {
735 if (cmd->error || data->error)
736 data->bytes_xfered = 0;
737 else
738 data->bytes_xfered = data->blocks * data->blksz;
739 }
740
741 mutex_unlock(&pcr->pcr_mutex);
742
743finish:
744 if (cmd->error)
745 dev_dbg(sdmmc_dev(host), "cmd->error = %d\n", cmd->error);
746
747 mutex_lock(&host->host_mutex);
748 host->mrq = NULL;
749 mutex_unlock(&host->host_mutex);
750
751 mmc_request_done(mmc, mrq);
752}
753
754static int sd_set_bus_width(struct realtek_pci_sdmmc *host,
755 unsigned char bus_width)
756{
757 int err = 0;
758 u8 width[] = {
759 [MMC_BUS_WIDTH_1] = SD_BUS_WIDTH_1BIT,
760 [MMC_BUS_WIDTH_4] = SD_BUS_WIDTH_4BIT,
761 [MMC_BUS_WIDTH_8] = SD_BUS_WIDTH_8BIT,
762 };
763
764 if (bus_width <= MMC_BUS_WIDTH_8)
765 err = rtsx_pci_write_register(host->pcr, SD_CFG1,
766 0x03, width[bus_width]);
767
768 return err;
769}
770
771static int sd_power_on(struct realtek_pci_sdmmc *host)
772{
773 struct rtsx_pcr *pcr = host->pcr;
774 int err;
775
d88691be
WW		 776 if (host->power_state == SDMMC_POWER_ON)
777 return 0;
778
ff984e57
WW		 779 rtsx_pci_init_cmd(pcr);
780 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_SELECT, 0x07, SD_MOD_SEL);
781 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_SHARE_MODE,
782 CARD_SHARE_MASK, CARD_SHARE_48_SD);
783 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_EN,
784 SD_CLK_EN, SD_CLK_EN);
785 err = rtsx_pci_send_cmd(pcr, 100);
786 if (err < 0)
787 return err;
788
789 err = rtsx_pci_card_pull_ctl_enable(pcr, RTSX_SD_CARD);
790 if (err < 0)
791 return err;
792
793 err = rtsx_pci_card_power_on(pcr, RTSX_SD_CARD);
794 if (err < 0)
795 return err;
796
797 err = rtsx_pci_write_register(pcr, CARD_OE, SD_OUTPUT_EN, SD_OUTPUT_EN);
798 if (err < 0)
799 return err;
800
d88691be 801 host->power_state = SDMMC_POWER_ON;
ff984e57
WW		 802 return 0;
803}
804
805static int sd_power_off(struct realtek_pci_sdmmc *host)
806{
807 struct rtsx_pcr *pcr = host->pcr;
808 int err;
809
d88691be
WW		 810 host->power_state = SDMMC_POWER_OFF;
811
ff984e57
WW		 812 rtsx_pci_init_cmd(pcr);
813
814 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_EN, SD_CLK_EN, 0);
815 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_OE, SD_OUTPUT_EN, 0);
816
817 err = rtsx_pci_send_cmd(pcr, 100);
818 if (err < 0)
819 return err;
820
821 err = rtsx_pci_card_power_off(pcr, RTSX_SD_CARD);
822 if (err < 0)
823 return err;
824
825 return rtsx_pci_card_pull_ctl_disable(pcr, RTSX_SD_CARD);
826}
827
828static int sd_set_power_mode(struct realtek_pci_sdmmc *host,
829 unsigned char power_mode)
830{
831 int err;
832
833 if (power_mode == MMC_POWER_OFF)
834 err = sd_power_off(host);
835 else
836 err = sd_power_on(host);
837
838 return err;
839}
840
84d72f9c 841static int sd_set_timing(struct realtek_pci_sdmmc *host, unsigned char timing)
ff984e57
WW		 842{
843 struct rtsx_pcr *pcr = host->pcr;
844 int err = 0;
845
ff984e57
WW		 846 rtsx_pci_init_cmd(pcr);
847
848 switch (timing) {
849 case MMC_TIMING_UHS_SDR104:
850 case MMC_TIMING_UHS_SDR50:
851 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1,
852 0x0C | SD_ASYNC_FIFO_NOT_RST,
853 SD_30_MODE | SD_ASYNC_FIFO_NOT_RST);
854 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL,
855 CLK_LOW_FREQ, CLK_LOW_FREQ);
856 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF,
857 CRC_VAR_CLK0 | SD30_FIX_CLK | SAMPLE_VAR_CLK1);
858 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0);
859 break;
860
861 case MMC_TIMING_UHS_DDR50:
ff984e57
WW		 862 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1,
863 0x0C | SD_ASYNC_FIFO_NOT_RST,
864 SD_DDR_MODE | SD_ASYNC_FIFO_NOT_RST);
865 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL,
866 CLK_LOW_FREQ, CLK_LOW_FREQ);
867 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF,
868 CRC_VAR_CLK0 | SD30_FIX_CLK | SAMPLE_VAR_CLK1);
869 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0);
870 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_PUSH_POINT_CTL,
871 DDR_VAR_TX_CMD_DAT, DDR_VAR_TX_CMD_DAT);
872 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_SAMPLE_POINT_CTL,
873 DDR_VAR_RX_DAT | DDR_VAR_RX_CMD,
874 DDR_VAR_RX_DAT | DDR_VAR_RX_CMD);
875 break;
876
877 case MMC_TIMING_MMC_HS:
878 case MMC_TIMING_SD_HS:
879 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1,
880 0x0C, SD_20_MODE);
881 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL,
882 CLK_LOW_FREQ, CLK_LOW_FREQ);
883 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF,
884 CRC_FIX_CLK | SD30_VAR_CLK0 | SAMPLE_VAR_CLK1);
885 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0);
886 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_PUSH_POINT_CTL,
887 SD20_TX_SEL_MASK, SD20_TX_14_AHEAD);
888 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_SAMPLE_POINT_CTL,
889 SD20_RX_SEL_MASK, SD20_RX_14_DELAY);
890 break;
891
892 default:
893 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
894 SD_CFG1, 0x0C, SD_20_MODE);
895 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL,
896 CLK_LOW_FREQ, CLK_LOW_FREQ);
897 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF,
898 CRC_FIX_CLK | SD30_VAR_CLK0 | SAMPLE_VAR_CLK1);
899 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0);
900 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
901 SD_PUSH_POINT_CTL, 0xFF, 0);
902 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_SAMPLE_POINT_CTL,
903 SD20_RX_SEL_MASK, SD20_RX_POS_EDGE);
904 break;
905 }
906
907 err = rtsx_pci_send_cmd(pcr, 100);
908
909 return err;
910}
911
912static void sdmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
913{
914 struct realtek_pci_sdmmc *host = mmc_priv(mmc);
915 struct rtsx_pcr *pcr = host->pcr;
916
917 if (host->eject)
918 return;
919
c3481955
WW		 920 if (rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD))
921 return;
922
ff984e57
WW		 923 mutex_lock(&pcr->pcr_mutex);
924
925 rtsx_pci_start_run(pcr);
926
927 sd_set_bus_width(host, ios->bus_width);
928 sd_set_power_mode(host, ios->power_mode);
84d72f9c 929 sd_set_timing(host, ios->timing);
ff984e57
WW		 930
931 host->vpclk = false;
932 host->double_clk = true;
933
934 switch (ios->timing) {
935 case MMC_TIMING_UHS_SDR104:
936 case MMC_TIMING_UHS_SDR50:
937 host->ssc_depth = RTSX_SSC_DEPTH_2M;
938 host->vpclk = true;
939 host->double_clk = false;
940 break;
941 case MMC_TIMING_UHS_DDR50:
942 case MMC_TIMING_UHS_SDR25:
943 host->ssc_depth = RTSX_SSC_DEPTH_1M;
944 break;
945 default:
946 host->ssc_depth = RTSX_SSC_DEPTH_500K;
947 break;
948 }
949
950 host->initial_mode = (ios->clock <= 1000000) ? true : false;
951
952 host->clock = ios->clock;
953 rtsx_pci_switch_clock(pcr, ios->clock, host->ssc_depth,
954 host->initial_mode, host->double_clk, host->vpclk);
955
956 mutex_unlock(&pcr->pcr_mutex);
957}
958
959static int sdmmc_get_ro(struct mmc_host *mmc)
960{
961 struct realtek_pci_sdmmc *host = mmc_priv(mmc);
962 struct rtsx_pcr *pcr = host->pcr;
963 int ro = 0;
964 u32 val;
965
966 if (host->eject)
967 return -ENOMEDIUM;
968
969 mutex_lock(&pcr->pcr_mutex);
970
971 rtsx_pci_start_run(pcr);
972
973 /* Check SD mechanical write-protect switch */
974 val = rtsx_pci_readl(pcr, RTSX_BIPR);
975 dev_dbg(sdmmc_dev(host), "%s: RTSX_BIPR = 0x%08x\n", __func__, val);
976 if (val & SD_WRITE_PROTECT)
977 ro = 1;
978
979 mutex_unlock(&pcr->pcr_mutex);
980
981 return ro;
982}
983
984static int sdmmc_get_cd(struct mmc_host *mmc)
985{
986 struct realtek_pci_sdmmc *host = mmc_priv(mmc);
987 struct rtsx_pcr *pcr = host->pcr;
988 int cd = 0;
989 u32 val;
990
991 if (host->eject)
992 return -ENOMEDIUM;
993
994 mutex_lock(&pcr->pcr_mutex);
995
996 rtsx_pci_start_run(pcr);
997
998 /* Check SD card detect */
999 val = rtsx_pci_card_exist(pcr);
1000 dev_dbg(sdmmc_dev(host), "%s: RTSX_BIPR = 0x%08x\n", __func__, val);
1001 if (val & SD_EXIST)
1002 cd = 1;
1003
1004 mutex_unlock(&pcr->pcr_mutex);
1005
1006 return cd;
1007}
1008
1009static int sd_wait_voltage_stable_1(struct realtek_pci_sdmmc *host)
1010{
1011 struct rtsx_pcr *pcr = host->pcr;
1012 int err;
1013 u8 stat;
1014
1015 /* Reference to Signal Voltage Switch Sequence in SD spec.
1016 * Wait for a period of time so that the card can drive SD_CMD and
1017 * SD_DAT[3:0] to low after sending back CMD11 response.
1018 */
1019 mdelay(1);
1020
1021 /* SD_CMD, SD_DAT[3:0] should be driven to low by card;
1022 * If either one of SD_CMD,SD_DAT[3:0] is not low,
1023 * abort the voltage switch sequence;
1024 */
1025 err = rtsx_pci_read_register(pcr, SD_BUS_STAT, &stat);
1026 if (err < 0)
1027 return err;
1028
1029 if (stat & (SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS |
1030 SD_DAT1_STATUS | SD_DAT0_STATUS))
1031 return -EINVAL;
1032
1033 /* Stop toggle SD clock */
1034 err = rtsx_pci_write_register(pcr, SD_BUS_STAT,
1035 0xFF, SD_CLK_FORCE_STOP);
1036 if (err < 0)
1037 return err;
1038
1039 return 0;
1040}
1041
1042static int sd_wait_voltage_stable_2(struct realtek_pci_sdmmc *host)
1043{
1044 struct rtsx_pcr *pcr = host->pcr;
1045 int err;
1046 u8 stat, mask, val;
1047
1048 /* Wait 1.8V output of voltage regulator in card stable */
1049 msleep(50);
1050
1051 /* Toggle SD clock again */
1052 err = rtsx_pci_write_register(pcr, SD_BUS_STAT, 0xFF, SD_CLK_TOGGLE_EN);
1053 if (err < 0)
1054 return err;
1055
1056 /* Wait for a period of time so that the card can drive
1057 * SD_DAT[3:0] to high at 1.8V
1058 */
1059 msleep(20);
1060
1061 /* SD_CMD, SD_DAT[3:0] should be pulled high by host */
1062 err = rtsx_pci_read_register(pcr, SD_BUS_STAT, &stat);
1063 if (err < 0)
1064 return err;
1065
1066 mask = SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS |
1067 SD_DAT1_STATUS | SD_DAT0_STATUS;
1068 val = SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS |
1069 SD_DAT1_STATUS | SD_DAT0_STATUS;
1070 if ((stat & mask) != val) {
1071 dev_dbg(sdmmc_dev(host),
1072 "%s: SD_BUS_STAT = 0x%x\n", __func__, stat);
1073 rtsx_pci_write_register(pcr, SD_BUS_STAT,
1074 SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP, 0);
1075 rtsx_pci_write_register(pcr, CARD_CLK_EN, 0xFF, 0);
1076 return -EINVAL;
1077 }
1078
1079 return 0;
1080}
1081
ff984e57
WW		 1082static int sdmmc_switch_voltage(struct mmc_host *mmc, struct mmc_ios *ios)
1083{
1084 struct realtek_pci_sdmmc *host = mmc_priv(mmc);
1085 struct rtsx_pcr *pcr = host->pcr;
1086 int err = 0;
1087 u8 voltage;
1088
1089 dev_dbg(sdmmc_dev(host), "%s: signal_voltage = %d\n",
1090 __func__, ios->signal_voltage);
1091
1092 if (host->eject)
1093 return -ENOMEDIUM;
1094
c3481955
WW		 1095 err = rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD);
1096 if (err)
1097 return err;
1098
ff984e57
WW		 1099 mutex_lock(&pcr->pcr_mutex);
1100
1101 rtsx_pci_start_run(pcr);
1102
1103 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330)
ef85e736 1104 voltage = OUTPUT_3V3;
ff984e57 1105 else
ef85e736 1106 voltage = OUTPUT_1V8;
ff984e57 1107
ef85e736 1108 if (voltage == OUTPUT_1V8) {
ff984e57
WW		 1109 err = sd_wait_voltage_stable_1(host);
1110 if (err < 0)
1111 goto out;
1112 }
1113
ef85e736 1114 err = rtsx_pci_switch_output_voltage(pcr, voltage);
ff984e57
WW		 1115 if (err < 0)
1116 goto out;
1117
ef85e736 1118 if (voltage == OUTPUT_1V8) {
ff984e57
WW		 1119 err = sd_wait_voltage_stable_2(host);
1120 if (err < 0)
1121 goto out;
1122 }
1123
1124 /* Stop toggle SD clock in idle */
1125 err = rtsx_pci_write_register(pcr, SD_BUS_STAT,
1126 SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP, 0);
1127
1128out:
1129 mutex_unlock(&pcr->pcr_mutex);
1130
1131 return err;
1132}
1133
1134static int sdmmc_execute_tuning(struct mmc_host *mmc, u32 opcode)
1135{
1136 struct realtek_pci_sdmmc *host = mmc_priv(mmc);
1137 struct rtsx_pcr *pcr = host->pcr;
1138 int err = 0;
1139
1140 if (host->eject)
1141 return -ENOMEDIUM;
1142
c3481955
WW		 1143 err = rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD);
1144 if (err)
1145 return err;
1146
ff984e57
WW		 1147 mutex_lock(&pcr->pcr_mutex);
1148
1149 rtsx_pci_start_run(pcr);
1150
84d72f9c
WW		 1151 /* Set initial TX phase */
1152 switch (mmc->ios.timing) {
1153 case MMC_TIMING_UHS_SDR104:
1154 err = sd_change_phase(host, SDR104_TX_PHASE(pcr), false);
1155 break;
1156
1157 case MMC_TIMING_UHS_SDR50:
1158 err = sd_change_phase(host, SDR50_TX_PHASE(pcr), false);
1159 break;
1160
1161 case MMC_TIMING_UHS_DDR50:
1162 err = sd_change_phase(host, DDR50_TX_PHASE(pcr), false);
1163 break;
1164
1165 default:
1166 err = 0;
1167 }
ff984e57 1168
84d72f9c
WW		 1169 if (err)
1170 goto out;
1171
1172 /* Tuning RX phase */
1173 if ((mmc->ios.timing == MMC_TIMING_UHS_SDR104) ||
1174 (mmc->ios.timing == MMC_TIMING_UHS_SDR50))
1175 err = sd_tuning_rx(host, opcode);
1176 else if (mmc->ios.timing == MMC_TIMING_UHS_DDR50)
1177 err = sd_change_phase(host, DDR50_RX_PHASE(pcr), true);
1178
1179out:
ff984e57
WW		 1180 mutex_unlock(&pcr->pcr_mutex);
1181
1182 return err;
1183}
1184
1185static const struct mmc_host_ops realtek_pci_sdmmc_ops = {
1186 .request = sdmmc_request,
1187 .set_ios = sdmmc_set_ios,
1188 .get_ro = sdmmc_get_ro,
1189 .get_cd = sdmmc_get_cd,
1190 .start_signal_voltage_switch = sdmmc_switch_voltage,
1191 .execute_tuning = sdmmc_execute_tuning,
1192};
1193
1194#ifdef CONFIG_PM
1195static int rtsx_pci_sdmmc_suspend(struct platform_device *pdev,
1196 pm_message_t state)
1197{
1198 struct realtek_pci_sdmmc *host = platform_get_drvdata(pdev);
1199 struct mmc_host *mmc = host->mmc;
1200 int err;
1201
1202 dev_dbg(sdmmc_dev(host), "--> %s\n", __func__);
1203
1204 err = mmc_suspend_host(mmc);
1205 if (err)
1206 return err;
1207
1208 return 0;
1209}
1210
1211static int rtsx_pci_sdmmc_resume(struct platform_device *pdev)
1212{
1213 struct realtek_pci_sdmmc *host = platform_get_drvdata(pdev);
1214 struct mmc_host *mmc = host->mmc;
1215
1216 dev_dbg(sdmmc_dev(host), "--> %s\n", __func__);
1217
1218 return mmc_resume_host(mmc);
1219}
1220#else /* CONFIG_PM */
1221#define rtsx_pci_sdmmc_suspend NULL
1222#define rtsx_pci_sdmmc_resume NULL
1223#endif /* CONFIG_PM */
1224
1225static void init_extra_caps(struct realtek_pci_sdmmc *host)
1226{
1227 struct mmc_host *mmc = host->mmc;
1228 struct rtsx_pcr *pcr = host->pcr;
1229
1230 dev_dbg(sdmmc_dev(host), "pcr->extra_caps = 0x%x\n", pcr->extra_caps);
1231
1232 if (pcr->extra_caps & EXTRA_CAPS_SD_SDR50)
1233 mmc->caps |= MMC_CAP_UHS_SDR50;
1234 if (pcr->extra_caps & EXTRA_CAPS_SD_SDR104)
1235 mmc->caps |= MMC_CAP_UHS_SDR104;
1236 if (pcr->extra_caps & EXTRA_CAPS_SD_DDR50)
1237 mmc->caps |= MMC_CAP_UHS_DDR50;
1238 if (pcr->extra_caps & EXTRA_CAPS_MMC_HSDDR)
1239 mmc->caps |= MMC_CAP_1_8V_DDR;
1240 if (pcr->extra_caps & EXTRA_CAPS_MMC_8BIT)
1241 mmc->caps |= MMC_CAP_8_BIT_DATA;
1242}
1243
1244static void realtek_init_host(struct realtek_pci_sdmmc *host)
1245{
1246 struct mmc_host *mmc = host->mmc;
1247
1248 mmc->f_min = 250000;
1249 mmc->f_max = 208000000;
1250 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
1251 mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SD_HIGHSPEED |
1252 MMC_CAP_MMC_HIGHSPEED | MMC_CAP_BUS_WIDTH_TEST |
1253 MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;
1254 mmc->max_current_330 = 400;
1255 mmc->max_current_180 = 800;
1256 mmc->ops = &realtek_pci_sdmmc_ops;
1257
1258 init_extra_caps(host);
1259
1260 mmc->max_segs = 256;
1261 mmc->max_seg_size = 65536;
1262 mmc->max_blk_size = 512;
1263 mmc->max_blk_count = 65535;
1264 mmc->max_req_size = 524288;
1265}
1266
1267static void rtsx_pci_sdmmc_card_event(struct platform_device *pdev)
1268{
1269 struct realtek_pci_sdmmc *host = platform_get_drvdata(pdev);
1270
1271 mmc_detect_change(host->mmc, 0);
1272}
1273
1274static int rtsx_pci_sdmmc_drv_probe(struct platform_device *pdev)
1275{
1276 struct mmc_host *mmc;
1277 struct realtek_pci_sdmmc *host;
1278 struct rtsx_pcr *pcr;
1279 struct pcr_handle *handle = pdev->dev.platform_data;
1280
1281 if (!handle)
1282 return -ENXIO;
1283
1284 pcr = handle->pcr;
1285 if (!pcr)
1286 return -ENXIO;
1287
1288 dev_dbg(&(pdev->dev), ": Realtek PCI-E SDMMC controller found\n");
1289
1290 mmc = mmc_alloc_host(sizeof(*host), &pdev->dev);
1291 if (!mmc)
1292 return -ENOMEM;
1293
1294 host = mmc_priv(mmc);
1295 host->pcr = pcr;
1296 host->mmc = mmc;
1297 host->pdev = pdev;
d88691be 1298 host->power_state = SDMMC_POWER_OFF;
ff984e57
WW		 1299 platform_set_drvdata(pdev, host);
1300 pcr->slots[RTSX_SD_CARD].p_dev = pdev;
1301 pcr->slots[RTSX_SD_CARD].card_event = rtsx_pci_sdmmc_card_event;
1302
1303 mutex_init(&host->host_mutex);
1304
1305 realtek_init_host(host);
1306
1307 mmc_add_host(mmc);
1308
1309 return 0;
1310}
1311
1312static int rtsx_pci_sdmmc_drv_remove(struct platform_device *pdev)
1313{
1314 struct realtek_pci_sdmmc *host = platform_get_drvdata(pdev);
1315 struct rtsx_pcr *pcr;
1316 struct mmc_host *mmc;
1317
1318 if (!host)
1319 return 0;
1320
1321 pcr = host->pcr;
1322 pcr->slots[RTSX_SD_CARD].p_dev = NULL;
1323 pcr->slots[RTSX_SD_CARD].card_event = NULL;
1324 mmc = host->mmc;
1325 host->eject = true;
1326
1327 mutex_lock(&host->host_mutex);
1328 if (host->mrq) {
1329 dev_dbg(&(pdev->dev),
1330 "%s: Controller removed during transfer\n",
1331 mmc_hostname(mmc));
1332
1333 rtsx_pci_complete_unfinished_transfer(pcr);
1334
1335 host->mrq->cmd->error = -ENOMEDIUM;
1336 if (host->mrq->stop)
1337 host->mrq->stop->error = -ENOMEDIUM;
1338 mmc_request_done(mmc, host->mrq);
1339 }
1340 mutex_unlock(&host->host_mutex);
1341
1342 mmc_remove_host(mmc);
1343 mmc_free_host(mmc);
1344
ff984e57
WW		 1345 dev_dbg(&(pdev->dev),
1346 ": Realtek PCI-E SDMMC controller has been removed\n");
1347
1348 return 0;
1349}
1350
1351static struct platform_device_id rtsx_pci_sdmmc_ids[] = {
1352 {
1353 .name = DRV_NAME_RTSX_PCI_SDMMC,
1354 }, {
1355 /* sentinel */
1356 }
1357};
1358MODULE_DEVICE_TABLE(platform, rtsx_pci_sdmmc_ids);
1359
1360static struct platform_driver rtsx_pci_sdmmc_driver = {
1361 .probe = rtsx_pci_sdmmc_drv_probe,
1362 .remove = rtsx_pci_sdmmc_drv_remove,
1363 .id_table = rtsx_pci_sdmmc_ids,
1364 .suspend = rtsx_pci_sdmmc_suspend,
1365 .resume = rtsx_pci_sdmmc_resume,
1366 .driver = {
1367 .owner = THIS_MODULE,
1368 .name = DRV_NAME_RTSX_PCI_SDMMC,
1369 },
1370};
1371module_platform_driver(rtsx_pci_sdmmc_driver);
1372
1373MODULE_LICENSE("GPL");
1374MODULE_AUTHOR("Wei WANG <wei_wang@realsil.com.cn>");
1375MODULE_DESCRIPTION("Realtek PCI-E SD/MMC Card Host Driver");
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