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01ebea1b CD |
1 | /* |
2 | * Copyright (C) 2013 Broadcom Corporation | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or | |
5 | * modify it under the terms of the GNU General Public License as | |
6 | * published by the Free Software Foundation version 2. | |
7 | * | |
8 | * This program is distributed "as is" WITHOUT ANY WARRANTY of any | |
9 | * kind, whether express or implied; without even the implied warranty | |
10 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
11 | * GNU General Public License for more details. | |
12 | */ | |
13 | ||
14 | #include <linux/kernel.h> | |
15 | #include <linux/module.h> | |
16 | #include <linux/delay.h> | |
17 | #include <linux/highmem.h> | |
18 | #include <linux/platform_device.h> | |
19 | #include <linux/mmc/host.h> | |
20 | #include <linux/io.h> | |
21 | #include <linux/gpio.h> | |
22 | #include <linux/clk.h> | |
23 | #include <linux/regulator/consumer.h> | |
24 | #include <linux/of.h> | |
25 | #include <linux/of_device.h> | |
26 | #include <linux/of_gpio.h> | |
01ebea1b CD |
27 | #include <linux/mmc/slot-gpio.h> |
28 | ||
29 | #include "sdhci-pltfm.h" | |
30 | #include "sdhci.h" | |
31 | ||
32 | #define SDHCI_SOFT_RESET 0x01000000 | |
33 | #define KONA_SDHOST_CORECTRL 0x8000 | |
34 | #define KONA_SDHOST_CD_PINCTRL 0x00000008 | |
35 | #define KONA_SDHOST_STOP_HCLK 0x00000004 | |
36 | #define KONA_SDHOST_RESET 0x00000002 | |
37 | #define KONA_SDHOST_EN 0x00000001 | |
38 | ||
39 | #define KONA_SDHOST_CORESTAT 0x8004 | |
40 | #define KONA_SDHOST_WP 0x00000002 | |
41 | #define KONA_SDHOST_CD_SW 0x00000001 | |
42 | ||
43 | #define KONA_SDHOST_COREIMR 0x8008 | |
44 | #define KONA_SDHOST_IP 0x00000001 | |
45 | ||
46 | #define KONA_SDHOST_COREISR 0x800C | |
47 | #define KONA_SDHOST_COREIMSR 0x8010 | |
48 | #define KONA_SDHOST_COREDBG1 0x8014 | |
49 | #define KONA_SDHOST_COREGPO_MASK 0x8018 | |
50 | ||
51 | #define SD_DETECT_GPIO_DEBOUNCE_128MS 128 | |
52 | ||
53 | #define KONA_MMC_AUTOSUSPEND_DELAY (50) | |
54 | ||
55 | struct sdhci_bcm_kona_dev { | |
56 | struct mutex write_lock; /* protect back to back writes */ | |
a6492c02 | 57 | struct clk *external_clk; |
01ebea1b CD |
58 | }; |
59 | ||
60 | ||
61 | static int sdhci_bcm_kona_sd_reset(struct sdhci_host *host) | |
62 | { | |
63 | unsigned int val; | |
64 | unsigned long timeout; | |
65 | ||
66 | /* This timeout should be sufficent for core to reset */ | |
67 | timeout = jiffies + msecs_to_jiffies(100); | |
68 | ||
69 | /* reset the host using the top level reset */ | |
70 | val = sdhci_readl(host, KONA_SDHOST_CORECTRL); | |
71 | val |= KONA_SDHOST_RESET; | |
72 | sdhci_writel(host, val, KONA_SDHOST_CORECTRL); | |
73 | ||
74 | while (!(sdhci_readl(host, KONA_SDHOST_CORECTRL) & KONA_SDHOST_RESET)) { | |
75 | if (time_is_before_jiffies(timeout)) { | |
76 | pr_err("Error: sd host is stuck in reset!!!\n"); | |
77 | return -EFAULT; | |
78 | } | |
79 | } | |
80 | ||
81 | /* bring the host out of reset */ | |
82 | val = sdhci_readl(host, KONA_SDHOST_CORECTRL); | |
83 | val &= ~KONA_SDHOST_RESET; | |
84 | ||
85 | /* | |
86 | * Back-to-Back register write needs a delay of 1ms at bootup (min 10uS) | |
87 | * Back-to-Back writes to same register needs delay when SD bus clock | |
88 | * is very low w.r.t AHB clock, mainly during boot-time and during card | |
89 | * insert-removal. | |
90 | */ | |
91 | usleep_range(1000, 5000); | |
92 | sdhci_writel(host, val, KONA_SDHOST_CORECTRL); | |
93 | ||
94 | return 0; | |
95 | } | |
96 | ||
97 | static void sdhci_bcm_kona_sd_init(struct sdhci_host *host) | |
98 | { | |
99 | unsigned int val; | |
100 | ||
101 | /* enable the interrupt from the IP core */ | |
102 | val = sdhci_readl(host, KONA_SDHOST_COREIMR); | |
103 | val |= KONA_SDHOST_IP; | |
104 | sdhci_writel(host, val, KONA_SDHOST_COREIMR); | |
105 | ||
106 | /* Enable the AHB clock gating module to the host */ | |
107 | val = sdhci_readl(host, KONA_SDHOST_CORECTRL); | |
108 | val |= KONA_SDHOST_EN; | |
109 | ||
110 | /* | |
111 | * Back-to-Back register write needs a delay of 1ms at bootup (min 10uS) | |
112 | * Back-to-Back writes to same register needs delay when SD bus clock | |
113 | * is very low w.r.t AHB clock, mainly during boot-time and during card | |
114 | * insert-removal. | |
115 | */ | |
116 | usleep_range(1000, 5000); | |
117 | sdhci_writel(host, val, KONA_SDHOST_CORECTRL); | |
118 | } | |
119 | ||
120 | /* | |
121 | * Software emulation of the SD card insertion/removal. Set insert=1 for insert | |
122 | * and insert=0 for removal. The card detection is done by GPIO. For Broadcom | |
123 | * IP to function properly the bit 0 of CORESTAT register needs to be set/reset | |
124 | * to generate the CD IRQ handled in sdhci.c which schedules card_tasklet. | |
125 | */ | |
126 | static int sdhci_bcm_kona_sd_card_emulate(struct sdhci_host *host, int insert) | |
127 | { | |
128 | struct sdhci_pltfm_host *pltfm_priv = sdhci_priv(host); | |
129 | struct sdhci_bcm_kona_dev *kona_dev = sdhci_pltfm_priv(pltfm_priv); | |
130 | u32 val; | |
131 | ||
132 | /* | |
133 | * Back-to-Back register write needs a delay of min 10uS. | |
134 | * Back-to-Back writes to same register needs delay when SD bus clock | |
135 | * is very low w.r.t AHB clock, mainly during boot-time and during card | |
136 | * insert-removal. | |
137 | * We keep 20uS | |
138 | */ | |
139 | mutex_lock(&kona_dev->write_lock); | |
140 | udelay(20); | |
141 | val = sdhci_readl(host, KONA_SDHOST_CORESTAT); | |
142 | ||
143 | if (insert) { | |
144 | int ret; | |
145 | ||
146 | ret = mmc_gpio_get_ro(host->mmc); | |
147 | if (ret >= 0) | |
148 | val = (val & ~KONA_SDHOST_WP) | | |
149 | ((ret) ? KONA_SDHOST_WP : 0); | |
150 | ||
151 | val |= KONA_SDHOST_CD_SW; | |
152 | sdhci_writel(host, val, KONA_SDHOST_CORESTAT); | |
153 | } else { | |
154 | val &= ~KONA_SDHOST_CD_SW; | |
155 | sdhci_writel(host, val, KONA_SDHOST_CORESTAT); | |
156 | } | |
157 | mutex_unlock(&kona_dev->write_lock); | |
158 | ||
159 | return 0; | |
160 | } | |
161 | ||
162 | /* | |
163 | * SD card interrupt event callback | |
164 | */ | |
ceb2ea19 | 165 | static void sdhci_bcm_kona_card_event(struct sdhci_host *host) |
01ebea1b CD |
166 | { |
167 | if (mmc_gpio_get_cd(host->mmc) > 0) { | |
168 | dev_dbg(mmc_dev(host->mmc), | |
169 | "card inserted\n"); | |
170 | sdhci_bcm_kona_sd_card_emulate(host, 1); | |
171 | } else { | |
172 | dev_dbg(mmc_dev(host->mmc), | |
173 | "card removed\n"); | |
174 | sdhci_bcm_kona_sd_card_emulate(host, 0); | |
175 | } | |
176 | } | |
177 | ||
178 | /* | |
179 | * Get the base clock. Use central clock source for now. Not sure if different | |
180 | * clock speed to each dev is allowed | |
181 | */ | |
182 | static unsigned int sdhci_bcm_kona_get_max_clk(struct sdhci_host *host) | |
183 | { | |
184 | struct sdhci_bcm_kona_dev *kona_dev; | |
185 | struct sdhci_pltfm_host *pltfm_priv = sdhci_priv(host); | |
186 | kona_dev = sdhci_pltfm_priv(pltfm_priv); | |
187 | ||
188 | return host->mmc->f_max; | |
189 | } | |
190 | ||
191 | static unsigned int sdhci_bcm_kona_get_timeout_clock(struct sdhci_host *host) | |
192 | { | |
193 | return sdhci_bcm_kona_get_max_clk(host); | |
194 | } | |
195 | ||
196 | static void sdhci_bcm_kona_init_74_clocks(struct sdhci_host *host, | |
197 | u8 power_mode) | |
198 | { | |
199 | /* | |
200 | * JEDEC and SD spec specify supplying 74 continuous clocks to | |
201 | * device after power up. With minimum bus (100KHz) that | |
202 | * that translates to 740us | |
203 | */ | |
204 | if (power_mode != MMC_POWER_OFF) | |
205 | udelay(740); | |
206 | } | |
207 | ||
208 | static struct sdhci_ops sdhci_bcm_kona_ops = { | |
209 | .get_max_clock = sdhci_bcm_kona_get_max_clk, | |
210 | .get_timeout_clock = sdhci_bcm_kona_get_timeout_clock, | |
211 | .platform_send_init_74_clocks = sdhci_bcm_kona_init_74_clocks, | |
2317f56c | 212 | .set_bus_width = sdhci_set_bus_width, |
01ebea1b CD |
213 | .card_event = sdhci_bcm_kona_card_event, |
214 | }; | |
215 | ||
216 | static struct sdhci_pltfm_data sdhci_pltfm_data_kona = { | |
217 | .ops = &sdhci_bcm_kona_ops, | |
218 | .quirks = SDHCI_QUIRK_NO_CARD_NO_RESET | | |
219 | SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | SDHCI_QUIRK_32BIT_DMA_ADDR | | |
220 | SDHCI_QUIRK_32BIT_DMA_SIZE | SDHCI_QUIRK_32BIT_ADMA_SIZE | | |
221 | SDHCI_QUIRK_FORCE_BLK_SZ_2048 | | |
222 | SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, | |
223 | }; | |
224 | ||
058feb53 | 225 | static struct __initconst of_device_id sdhci_bcm_kona_of_match[] = { |
aea237bf CD |
226 | { .compatible = "brcm,kona-sdhci"}, |
227 | { .compatible = "bcm,kona-sdhci"}, /* deprecated name */ | |
01ebea1b CD |
228 | {} |
229 | }; | |
230 | MODULE_DEVICE_TABLE(of, sdhci_bcm_kona_of_match); | |
231 | ||
058feb53 | 232 | static int sdhci_bcm_kona_probe(struct platform_device *pdev) |
01ebea1b CD |
233 | { |
234 | struct sdhci_bcm_kona_dev *kona_dev = NULL; | |
235 | struct sdhci_pltfm_host *pltfm_priv; | |
236 | struct device *dev = &pdev->dev; | |
237 | struct sdhci_host *host; | |
238 | int ret; | |
239 | ||
240 | ret = 0; | |
241 | ||
242 | host = sdhci_pltfm_init(pdev, &sdhci_pltfm_data_kona, | |
243 | sizeof(*kona_dev)); | |
244 | if (IS_ERR(host)) | |
245 | return PTR_ERR(host); | |
246 | ||
247 | dev_dbg(dev, "%s: inited. IOADDR=%p\n", __func__, host->ioaddr); | |
248 | ||
249 | pltfm_priv = sdhci_priv(host); | |
250 | ||
251 | kona_dev = sdhci_pltfm_priv(pltfm_priv); | |
252 | mutex_init(&kona_dev->write_lock); | |
253 | ||
254 | mmc_of_parse(host->mmc); | |
255 | ||
256 | if (!host->mmc->f_max) { | |
257 | dev_err(&pdev->dev, "Missing max-freq for SDHCI cfg\n"); | |
258 | ret = -ENXIO; | |
259 | goto err_pltfm_free; | |
260 | } | |
261 | ||
a6492c02 TK |
262 | /* Get and enable the external clock */ |
263 | kona_dev->external_clk = devm_clk_get(dev, NULL); | |
264 | if (IS_ERR(kona_dev->external_clk)) { | |
265 | dev_err(dev, "Failed to get external clock\n"); | |
266 | ret = PTR_ERR(kona_dev->external_clk); | |
267 | goto err_pltfm_free; | |
268 | } | |
269 | ||
270 | if (clk_set_rate(kona_dev->external_clk, host->mmc->f_max) != 0) { | |
271 | dev_err(dev, "Failed to set rate external clock\n"); | |
272 | goto err_pltfm_free; | |
273 | } | |
274 | ||
275 | if (clk_prepare_enable(kona_dev->external_clk) != 0) { | |
276 | dev_err(dev, "Failed to enable external clock\n"); | |
277 | goto err_pltfm_free; | |
278 | } | |
279 | ||
01ebea1b CD |
280 | dev_dbg(dev, "non-removable=%c\n", |
281 | (host->mmc->caps & MMC_CAP_NONREMOVABLE) ? 'Y' : 'N'); | |
282 | dev_dbg(dev, "cd_gpio %c, wp_gpio %c\n", | |
283 | (mmc_gpio_get_cd(host->mmc) != -ENOSYS) ? 'Y' : 'N', | |
284 | (mmc_gpio_get_ro(host->mmc) != -ENOSYS) ? 'Y' : 'N'); | |
285 | ||
cf68b629 | 286 | if (host->mmc->caps & MMC_CAP_NONREMOVABLE) |
01ebea1b CD |
287 | host->quirks |= SDHCI_QUIRK_BROKEN_CARD_DETECTION; |
288 | ||
289 | dev_dbg(dev, "is_8bit=%c\n", | |
290 | (host->mmc->caps | MMC_CAP_8_BIT_DATA) ? 'Y' : 'N'); | |
291 | ||
292 | ret = sdhci_bcm_kona_sd_reset(host); | |
293 | if (ret) | |
a6492c02 | 294 | goto err_clk_disable; |
01ebea1b CD |
295 | |
296 | sdhci_bcm_kona_sd_init(host); | |
297 | ||
298 | ret = sdhci_add_host(host); | |
299 | if (ret) { | |
300 | dev_err(dev, "Failed sdhci_add_host\n"); | |
301 | goto err_reset; | |
302 | } | |
303 | ||
304 | /* if device is eMMC, emulate card insert right here */ | |
cf68b629 | 305 | if (host->mmc->caps & MMC_CAP_NONREMOVABLE) { |
01ebea1b CD |
306 | ret = sdhci_bcm_kona_sd_card_emulate(host, 1); |
307 | if (ret) { | |
308 | dev_err(dev, | |
309 | "unable to emulate card insertion\n"); | |
310 | goto err_remove_host; | |
311 | } | |
312 | } | |
313 | /* | |
314 | * Since the card detection GPIO interrupt is configured to be | |
315 | * edge sensitive, check the initial GPIO value here, emulate | |
316 | * only if the card is present | |
317 | */ | |
318 | if (mmc_gpio_get_cd(host->mmc) > 0) | |
319 | sdhci_bcm_kona_sd_card_emulate(host, 1); | |
320 | ||
321 | dev_dbg(dev, "initialized properly\n"); | |
322 | return 0; | |
323 | ||
324 | err_remove_host: | |
325 | sdhci_remove_host(host, 0); | |
326 | ||
327 | err_reset: | |
328 | sdhci_bcm_kona_sd_reset(host); | |
329 | ||
a6492c02 TK |
330 | err_clk_disable: |
331 | clk_disable_unprepare(kona_dev->external_clk); | |
332 | ||
01ebea1b CD |
333 | err_pltfm_free: |
334 | sdhci_pltfm_free(pdev); | |
335 | ||
336 | dev_err(dev, "Probing of sdhci-pltfm failed: %d\n", ret); | |
337 | return ret; | |
338 | } | |
339 | ||
4025ce24 | 340 | static int sdhci_bcm_kona_remove(struct platform_device *pdev) |
01ebea1b | 341 | { |
a6492c02 TK |
342 | struct sdhci_host *host = platform_get_drvdata(pdev); |
343 | struct sdhci_pltfm_host *pltfm_priv = sdhci_priv(host); | |
344 | struct sdhci_bcm_kona_dev *kona_dev = sdhci_pltfm_priv(pltfm_priv); | |
345 | int dead = (readl(host->ioaddr + SDHCI_INT_STATUS) == 0xffffffff); | |
346 | ||
347 | sdhci_remove_host(host, dead); | |
348 | ||
349 | clk_disable_unprepare(kona_dev->external_clk); | |
350 | ||
351 | sdhci_pltfm_free(pdev); | |
352 | ||
353 | return 0; | |
01ebea1b CD |
354 | } |
355 | ||
356 | static struct platform_driver sdhci_bcm_kona_driver = { | |
357 | .driver = { | |
358 | .name = "sdhci-kona", | |
359 | .owner = THIS_MODULE, | |
360 | .pm = SDHCI_PLTFM_PMOPS, | |
058feb53 | 361 | .of_match_table = sdhci_bcm_kona_of_match, |
01ebea1b CD |
362 | }, |
363 | .probe = sdhci_bcm_kona_probe, | |
058feb53 | 364 | .remove = sdhci_bcm_kona_remove, |
01ebea1b CD |
365 | }; |
366 | module_platform_driver(sdhci_bcm_kona_driver); | |
367 | ||
368 | MODULE_DESCRIPTION("SDHCI driver for Broadcom Kona platform"); | |
369 | MODULE_AUTHOR("Broadcom"); | |
370 | MODULE_LICENSE("GPL v2"); |