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95f25efe WS |
1 | /* |
2 | * Freescale eSDHC i.MX controller driver for the platform bus. | |
3 | * | |
4 | * derived from the OF-version. | |
5 | * | |
6 | * Copyright (c) 2010 Pengutronix e.K. | |
7 | * Author: Wolfram Sang <w.sang@pengutronix.de> | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License as published by | |
11 | * the Free Software Foundation; either version 2 of the License. | |
12 | */ | |
13 | ||
14 | #include <linux/io.h> | |
15 | #include <linux/delay.h> | |
16 | #include <linux/err.h> | |
17 | #include <linux/clk.h> | |
0c6d49ce | 18 | #include <linux/gpio.h> |
66506f76 | 19 | #include <linux/module.h> |
e149860d | 20 | #include <linux/slab.h> |
95f25efe | 21 | #include <linux/mmc/host.h> |
58ac8177 RZ |
22 | #include <linux/mmc/mmc.h> |
23 | #include <linux/mmc/sdio.h> | |
fbe5fdd1 | 24 | #include <linux/mmc/slot-gpio.h> |
abfafc2d SG |
25 | #include <linux/of.h> |
26 | #include <linux/of_device.h> | |
27 | #include <linux/of_gpio.h> | |
e62d8b8f | 28 | #include <linux/pinctrl/consumer.h> |
82906b13 | 29 | #include <linux/platform_data/mmc-esdhc-imx.h> |
89d7e5c1 | 30 | #include <linux/pm_runtime.h> |
95f25efe WS |
31 | #include "sdhci-pltfm.h" |
32 | #include "sdhci-esdhc.h" | |
33 | ||
60bf6396 | 34 | #define ESDHC_CTRL_D3CD 0x08 |
58ac8177 | 35 | /* VENDOR SPEC register */ |
60bf6396 SG |
36 | #define ESDHC_VENDOR_SPEC 0xc0 |
37 | #define ESDHC_VENDOR_SPEC_SDIO_QUIRK (1 << 1) | |
0322191e | 38 | #define ESDHC_VENDOR_SPEC_VSELECT (1 << 1) |
fed2f6e2 | 39 | #define ESDHC_VENDOR_SPEC_FRC_SDCLK_ON (1 << 8) |
60bf6396 SG |
40 | #define ESDHC_WTMK_LVL 0x44 |
41 | #define ESDHC_MIX_CTRL 0x48 | |
de5bdbff | 42 | #define ESDHC_MIX_CTRL_DDREN (1 << 3) |
2a15f981 | 43 | #define ESDHC_MIX_CTRL_AC23EN (1 << 7) |
0322191e DA |
44 | #define ESDHC_MIX_CTRL_EXE_TUNE (1 << 22) |
45 | #define ESDHC_MIX_CTRL_SMPCLK_SEL (1 << 23) | |
46 | #define ESDHC_MIX_CTRL_FBCLK_SEL (1 << 25) | |
2a15f981 SG |
47 | /* Bits 3 and 6 are not SDHCI standard definitions */ |
48 | #define ESDHC_MIX_CTRL_SDHCI_MASK 0xb7 | |
d131a71c DA |
49 | /* Tuning bits */ |
50 | #define ESDHC_MIX_CTRL_TUNING_MASK 0x03c00000 | |
58ac8177 | 51 | |
602519b2 DA |
52 | /* dll control register */ |
53 | #define ESDHC_DLL_CTRL 0x60 | |
54 | #define ESDHC_DLL_OVERRIDE_VAL_SHIFT 9 | |
55 | #define ESDHC_DLL_OVERRIDE_EN_SHIFT 8 | |
56 | ||
0322191e DA |
57 | /* tune control register */ |
58 | #define ESDHC_TUNE_CTRL_STATUS 0x68 | |
59 | #define ESDHC_TUNE_CTRL_STEP 1 | |
60 | #define ESDHC_TUNE_CTRL_MIN 0 | |
61 | #define ESDHC_TUNE_CTRL_MAX ((1 << 7) - 1) | |
62 | ||
6e9fd28e DA |
63 | #define ESDHC_TUNING_CTRL 0xcc |
64 | #define ESDHC_STD_TUNING_EN (1 << 24) | |
65 | /* NOTE: the minimum valid tuning start tap for mx6sl is 1 */ | |
66 | #define ESDHC_TUNING_START_TAP 0x1 | |
67 | ||
ad93220d DA |
68 | /* pinctrl state */ |
69 | #define ESDHC_PINCTRL_STATE_100MHZ "state_100mhz" | |
70 | #define ESDHC_PINCTRL_STATE_200MHZ "state_200mhz" | |
71 | ||
af51079e SH |
72 | /* |
73 | * Our interpretation of the SDHCI_HOST_CONTROL register | |
74 | */ | |
75 | #define ESDHC_CTRL_4BITBUS (0x1 << 1) | |
76 | #define ESDHC_CTRL_8BITBUS (0x2 << 1) | |
77 | #define ESDHC_CTRL_BUSWIDTH_MASK (0x3 << 1) | |
78 | ||
97e4ba6a RZ |
79 | /* |
80 | * There is an INT DMA ERR mis-match between eSDHC and STD SDHC SPEC: | |
81 | * Bit25 is used in STD SPEC, and is reserved in fsl eSDHC design, | |
82 | * but bit28 is used as the INT DMA ERR in fsl eSDHC design. | |
83 | * Define this macro DMA error INT for fsl eSDHC | |
84 | */ | |
60bf6396 | 85 | #define ESDHC_INT_VENDOR_SPEC_DMA_ERR (1 << 28) |
97e4ba6a | 86 | |
58ac8177 RZ |
87 | /* |
88 | * The CMDTYPE of the CMD register (offset 0xE) should be set to | |
89 | * "11" when the STOP CMD12 is issued on imx53 to abort one | |
90 | * open ended multi-blk IO. Otherwise the TC INT wouldn't | |
91 | * be generated. | |
92 | * In exact block transfer, the controller doesn't complete the | |
93 | * operations automatically as required at the end of the | |
94 | * transfer and remains on hold if the abort command is not sent. | |
95 | * As a result, the TC flag is not asserted and SW received timeout | |
96 | * exeception. Bit1 of Vendor Spec registor is used to fix it. | |
97 | */ | |
31fbb301 SG |
98 | #define ESDHC_FLAG_MULTIBLK_NO_INT BIT(1) |
99 | /* | |
100 | * The flag enables the workaround for ESDHC errata ENGcm07207 which | |
101 | * affects i.MX25 and i.MX35. | |
102 | */ | |
103 | #define ESDHC_FLAG_ENGCM07207 BIT(2) | |
9d61c009 SG |
104 | /* |
105 | * The flag tells that the ESDHC controller is an USDHC block that is | |
106 | * integrated on the i.MX6 series. | |
107 | */ | |
108 | #define ESDHC_FLAG_USDHC BIT(3) | |
6e9fd28e DA |
109 | /* The IP supports manual tuning process */ |
110 | #define ESDHC_FLAG_MAN_TUNING BIT(4) | |
111 | /* The IP supports standard tuning process */ | |
112 | #define ESDHC_FLAG_STD_TUNING BIT(5) | |
113 | /* The IP has SDHCI_CAPABILITIES_1 register */ | |
114 | #define ESDHC_FLAG_HAVE_CAP1 BIT(6) | |
e149860d | 115 | |
f47c4bbf SG |
116 | struct esdhc_soc_data { |
117 | u32 flags; | |
118 | }; | |
119 | ||
120 | static struct esdhc_soc_data esdhc_imx25_data = { | |
121 | .flags = ESDHC_FLAG_ENGCM07207, | |
122 | }; | |
123 | ||
124 | static struct esdhc_soc_data esdhc_imx35_data = { | |
125 | .flags = ESDHC_FLAG_ENGCM07207, | |
126 | }; | |
127 | ||
128 | static struct esdhc_soc_data esdhc_imx51_data = { | |
129 | .flags = 0, | |
130 | }; | |
131 | ||
132 | static struct esdhc_soc_data esdhc_imx53_data = { | |
133 | .flags = ESDHC_FLAG_MULTIBLK_NO_INT, | |
134 | }; | |
135 | ||
136 | static struct esdhc_soc_data usdhc_imx6q_data = { | |
6e9fd28e DA |
137 | .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_MAN_TUNING, |
138 | }; | |
139 | ||
140 | static struct esdhc_soc_data usdhc_imx6sl_data = { | |
141 | .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING | |
142 | | ESDHC_FLAG_HAVE_CAP1, | |
57ed3314 SG |
143 | }; |
144 | ||
e149860d | 145 | struct pltfm_imx_data { |
e149860d | 146 | u32 scratchpad; |
e62d8b8f | 147 | struct pinctrl *pinctrl; |
ad93220d DA |
148 | struct pinctrl_state *pins_default; |
149 | struct pinctrl_state *pins_100mhz; | |
150 | struct pinctrl_state *pins_200mhz; | |
f47c4bbf | 151 | const struct esdhc_soc_data *socdata; |
842afc02 | 152 | struct esdhc_platform_data boarddata; |
52dac615 SH |
153 | struct clk *clk_ipg; |
154 | struct clk *clk_ahb; | |
155 | struct clk *clk_per; | |
361b8482 LS |
156 | enum { |
157 | NO_CMD_PENDING, /* no multiblock command pending*/ | |
158 | MULTIBLK_IN_PROCESS, /* exact multiblock cmd in process */ | |
159 | WAIT_FOR_INT, /* sent CMD12, waiting for response INT */ | |
160 | } multiblock_status; | |
de5bdbff | 161 | u32 is_ddr; |
e149860d RZ |
162 | }; |
163 | ||
57ed3314 SG |
164 | static struct platform_device_id imx_esdhc_devtype[] = { |
165 | { | |
166 | .name = "sdhci-esdhc-imx25", | |
f47c4bbf | 167 | .driver_data = (kernel_ulong_t) &esdhc_imx25_data, |
57ed3314 SG |
168 | }, { |
169 | .name = "sdhci-esdhc-imx35", | |
f47c4bbf | 170 | .driver_data = (kernel_ulong_t) &esdhc_imx35_data, |
57ed3314 SG |
171 | }, { |
172 | .name = "sdhci-esdhc-imx51", | |
f47c4bbf | 173 | .driver_data = (kernel_ulong_t) &esdhc_imx51_data, |
57ed3314 SG |
174 | }, { |
175 | /* sentinel */ | |
176 | } | |
177 | }; | |
178 | MODULE_DEVICE_TABLE(platform, imx_esdhc_devtype); | |
179 | ||
abfafc2d | 180 | static const struct of_device_id imx_esdhc_dt_ids[] = { |
f47c4bbf SG |
181 | { .compatible = "fsl,imx25-esdhc", .data = &esdhc_imx25_data, }, |
182 | { .compatible = "fsl,imx35-esdhc", .data = &esdhc_imx35_data, }, | |
183 | { .compatible = "fsl,imx51-esdhc", .data = &esdhc_imx51_data, }, | |
184 | { .compatible = "fsl,imx53-esdhc", .data = &esdhc_imx53_data, }, | |
6e9fd28e | 185 | { .compatible = "fsl,imx6sl-usdhc", .data = &usdhc_imx6sl_data, }, |
f47c4bbf | 186 | { .compatible = "fsl,imx6q-usdhc", .data = &usdhc_imx6q_data, }, |
abfafc2d SG |
187 | { /* sentinel */ } |
188 | }; | |
189 | MODULE_DEVICE_TABLE(of, imx_esdhc_dt_ids); | |
190 | ||
57ed3314 SG |
191 | static inline int is_imx25_esdhc(struct pltfm_imx_data *data) |
192 | { | |
f47c4bbf | 193 | return data->socdata == &esdhc_imx25_data; |
57ed3314 SG |
194 | } |
195 | ||
196 | static inline int is_imx53_esdhc(struct pltfm_imx_data *data) | |
197 | { | |
f47c4bbf | 198 | return data->socdata == &esdhc_imx53_data; |
57ed3314 SG |
199 | } |
200 | ||
95a2482a SG |
201 | static inline int is_imx6q_usdhc(struct pltfm_imx_data *data) |
202 | { | |
f47c4bbf | 203 | return data->socdata == &usdhc_imx6q_data; |
95a2482a SG |
204 | } |
205 | ||
9d61c009 SG |
206 | static inline int esdhc_is_usdhc(struct pltfm_imx_data *data) |
207 | { | |
f47c4bbf | 208 | return !!(data->socdata->flags & ESDHC_FLAG_USDHC); |
9d61c009 SG |
209 | } |
210 | ||
95f25efe WS |
211 | static inline void esdhc_clrset_le(struct sdhci_host *host, u32 mask, u32 val, int reg) |
212 | { | |
213 | void __iomem *base = host->ioaddr + (reg & ~0x3); | |
214 | u32 shift = (reg & 0x3) * 8; | |
215 | ||
216 | writel(((readl(base) & ~(mask << shift)) | (val << shift)), base); | |
217 | } | |
218 | ||
7e29c306 WS |
219 | static u32 esdhc_readl_le(struct sdhci_host *host, int reg) |
220 | { | |
361b8482 LS |
221 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
222 | struct pltfm_imx_data *imx_data = pltfm_host->priv; | |
7e29c306 WS |
223 | u32 val = readl(host->ioaddr + reg); |
224 | ||
0322191e DA |
225 | if (unlikely(reg == SDHCI_PRESENT_STATE)) { |
226 | u32 fsl_prss = val; | |
227 | /* save the least 20 bits */ | |
228 | val = fsl_prss & 0x000FFFFF; | |
229 | /* move dat[0-3] bits */ | |
230 | val |= (fsl_prss & 0x0F000000) >> 4; | |
231 | /* move cmd line bit */ | |
232 | val |= (fsl_prss & 0x00800000) << 1; | |
233 | } | |
234 | ||
97e4ba6a | 235 | if (unlikely(reg == SDHCI_CAPABILITIES)) { |
6b4fb671 DA |
236 | /* ignore bit[0-15] as it stores cap_1 register val for mx6sl */ |
237 | if (imx_data->socdata->flags & ESDHC_FLAG_HAVE_CAP1) | |
238 | val &= 0xffff0000; | |
239 | ||
97e4ba6a RZ |
240 | /* In FSL esdhc IC module, only bit20 is used to indicate the |
241 | * ADMA2 capability of esdhc, but this bit is messed up on | |
242 | * some SOCs (e.g. on MX25, MX35 this bit is set, but they | |
243 | * don't actually support ADMA2). So set the BROKEN_ADMA | |
244 | * uirk on MX25/35 platforms. | |
245 | */ | |
246 | ||
247 | if (val & SDHCI_CAN_DO_ADMA1) { | |
248 | val &= ~SDHCI_CAN_DO_ADMA1; | |
249 | val |= SDHCI_CAN_DO_ADMA2; | |
250 | } | |
251 | } | |
252 | ||
6e9fd28e DA |
253 | if (unlikely(reg == SDHCI_CAPABILITIES_1)) { |
254 | if (esdhc_is_usdhc(imx_data)) { | |
255 | if (imx_data->socdata->flags & ESDHC_FLAG_HAVE_CAP1) | |
256 | val = readl(host->ioaddr + SDHCI_CAPABILITIES) & 0xFFFF; | |
257 | else | |
258 | /* imx6q/dl does not have cap_1 register, fake one */ | |
259 | val = SDHCI_SUPPORT_DDR50 | SDHCI_SUPPORT_SDR104 | |
888824bb DA |
260 | | SDHCI_SUPPORT_SDR50 |
261 | | SDHCI_USE_SDR50_TUNING; | |
6e9fd28e DA |
262 | } |
263 | } | |
0322191e | 264 | |
9d61c009 | 265 | if (unlikely(reg == SDHCI_MAX_CURRENT) && esdhc_is_usdhc(imx_data)) { |
0322191e DA |
266 | val = 0; |
267 | val |= 0xFF << SDHCI_MAX_CURRENT_330_SHIFT; | |
268 | val |= 0xFF << SDHCI_MAX_CURRENT_300_SHIFT; | |
269 | val |= 0xFF << SDHCI_MAX_CURRENT_180_SHIFT; | |
270 | } | |
271 | ||
97e4ba6a | 272 | if (unlikely(reg == SDHCI_INT_STATUS)) { |
60bf6396 SG |
273 | if (val & ESDHC_INT_VENDOR_SPEC_DMA_ERR) { |
274 | val &= ~ESDHC_INT_VENDOR_SPEC_DMA_ERR; | |
97e4ba6a RZ |
275 | val |= SDHCI_INT_ADMA_ERROR; |
276 | } | |
361b8482 LS |
277 | |
278 | /* | |
279 | * mask off the interrupt we get in response to the manually | |
280 | * sent CMD12 | |
281 | */ | |
282 | if ((imx_data->multiblock_status == WAIT_FOR_INT) && | |
283 | ((val & SDHCI_INT_RESPONSE) == SDHCI_INT_RESPONSE)) { | |
284 | val &= ~SDHCI_INT_RESPONSE; | |
285 | writel(SDHCI_INT_RESPONSE, host->ioaddr + | |
286 | SDHCI_INT_STATUS); | |
287 | imx_data->multiblock_status = NO_CMD_PENDING; | |
288 | } | |
97e4ba6a RZ |
289 | } |
290 | ||
7e29c306 WS |
291 | return val; |
292 | } | |
293 | ||
294 | static void esdhc_writel_le(struct sdhci_host *host, u32 val, int reg) | |
295 | { | |
e149860d RZ |
296 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
297 | struct pltfm_imx_data *imx_data = pltfm_host->priv; | |
0d58864b TL |
298 | u32 data; |
299 | ||
300 | if (unlikely(reg == SDHCI_INT_ENABLE || reg == SDHCI_SIGNAL_ENABLE)) { | |
0d58864b TL |
301 | if (val & SDHCI_INT_CARD_INT) { |
302 | /* | |
303 | * Clear and then set D3CD bit to avoid missing the | |
304 | * card interrupt. This is a eSDHC controller problem | |
305 | * so we need to apply the following workaround: clear | |
306 | * and set D3CD bit will make eSDHC re-sample the card | |
307 | * interrupt. In case a card interrupt was lost, | |
308 | * re-sample it by the following steps. | |
309 | */ | |
310 | data = readl(host->ioaddr + SDHCI_HOST_CONTROL); | |
60bf6396 | 311 | data &= ~ESDHC_CTRL_D3CD; |
0d58864b | 312 | writel(data, host->ioaddr + SDHCI_HOST_CONTROL); |
60bf6396 | 313 | data |= ESDHC_CTRL_D3CD; |
0d58864b TL |
314 | writel(data, host->ioaddr + SDHCI_HOST_CONTROL); |
315 | } | |
316 | } | |
7e29c306 | 317 | |
f47c4bbf | 318 | if (unlikely((imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT) |
58ac8177 RZ |
319 | && (reg == SDHCI_INT_STATUS) |
320 | && (val & SDHCI_INT_DATA_END))) { | |
321 | u32 v; | |
60bf6396 SG |
322 | v = readl(host->ioaddr + ESDHC_VENDOR_SPEC); |
323 | v &= ~ESDHC_VENDOR_SPEC_SDIO_QUIRK; | |
324 | writel(v, host->ioaddr + ESDHC_VENDOR_SPEC); | |
361b8482 LS |
325 | |
326 | if (imx_data->multiblock_status == MULTIBLK_IN_PROCESS) | |
327 | { | |
328 | /* send a manual CMD12 with RESPTYP=none */ | |
329 | data = MMC_STOP_TRANSMISSION << 24 | | |
330 | SDHCI_CMD_ABORTCMD << 16; | |
331 | writel(data, host->ioaddr + SDHCI_TRANSFER_MODE); | |
332 | imx_data->multiblock_status = WAIT_FOR_INT; | |
333 | } | |
58ac8177 RZ |
334 | } |
335 | ||
97e4ba6a RZ |
336 | if (unlikely(reg == SDHCI_INT_ENABLE || reg == SDHCI_SIGNAL_ENABLE)) { |
337 | if (val & SDHCI_INT_ADMA_ERROR) { | |
338 | val &= ~SDHCI_INT_ADMA_ERROR; | |
60bf6396 | 339 | val |= ESDHC_INT_VENDOR_SPEC_DMA_ERR; |
97e4ba6a RZ |
340 | } |
341 | } | |
342 | ||
7e29c306 WS |
343 | writel(val, host->ioaddr + reg); |
344 | } | |
345 | ||
95f25efe WS |
346 | static u16 esdhc_readw_le(struct sdhci_host *host, int reg) |
347 | { | |
ef4d0888 SG |
348 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
349 | struct pltfm_imx_data *imx_data = pltfm_host->priv; | |
0322191e DA |
350 | u16 ret = 0; |
351 | u32 val; | |
ef4d0888 | 352 | |
95a2482a | 353 | if (unlikely(reg == SDHCI_HOST_VERSION)) { |
ef4d0888 | 354 | reg ^= 2; |
9d61c009 | 355 | if (esdhc_is_usdhc(imx_data)) { |
ef4d0888 SG |
356 | /* |
357 | * The usdhc register returns a wrong host version. | |
358 | * Correct it here. | |
359 | */ | |
360 | return SDHCI_SPEC_300; | |
361 | } | |
95a2482a | 362 | } |
95f25efe | 363 | |
0322191e DA |
364 | if (unlikely(reg == SDHCI_HOST_CONTROL2)) { |
365 | val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); | |
366 | if (val & ESDHC_VENDOR_SPEC_VSELECT) | |
367 | ret |= SDHCI_CTRL_VDD_180; | |
368 | ||
9d61c009 | 369 | if (esdhc_is_usdhc(imx_data)) { |
6e9fd28e DA |
370 | if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) |
371 | val = readl(host->ioaddr + ESDHC_MIX_CTRL); | |
372 | else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) | |
373 | /* the std tuning bits is in ACMD12_ERR for imx6sl */ | |
374 | val = readl(host->ioaddr + SDHCI_ACMD12_ERR); | |
0322191e DA |
375 | } |
376 | ||
6e9fd28e DA |
377 | if (val & ESDHC_MIX_CTRL_EXE_TUNE) |
378 | ret |= SDHCI_CTRL_EXEC_TUNING; | |
379 | if (val & ESDHC_MIX_CTRL_SMPCLK_SEL) | |
380 | ret |= SDHCI_CTRL_TUNED_CLK; | |
381 | ||
0322191e DA |
382 | ret &= ~SDHCI_CTRL_PRESET_VAL_ENABLE; |
383 | ||
384 | return ret; | |
385 | } | |
386 | ||
7dd109ef DA |
387 | if (unlikely(reg == SDHCI_TRANSFER_MODE)) { |
388 | if (esdhc_is_usdhc(imx_data)) { | |
389 | u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL); | |
390 | ret = m & ESDHC_MIX_CTRL_SDHCI_MASK; | |
391 | /* Swap AC23 bit */ | |
392 | if (m & ESDHC_MIX_CTRL_AC23EN) { | |
393 | ret &= ~ESDHC_MIX_CTRL_AC23EN; | |
394 | ret |= SDHCI_TRNS_AUTO_CMD23; | |
395 | } | |
396 | } else { | |
397 | ret = readw(host->ioaddr + SDHCI_TRANSFER_MODE); | |
398 | } | |
399 | ||
400 | return ret; | |
401 | } | |
402 | ||
95f25efe WS |
403 | return readw(host->ioaddr + reg); |
404 | } | |
405 | ||
406 | static void esdhc_writew_le(struct sdhci_host *host, u16 val, int reg) | |
407 | { | |
408 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
e149860d | 409 | struct pltfm_imx_data *imx_data = pltfm_host->priv; |
0322191e | 410 | u32 new_val = 0; |
95f25efe WS |
411 | |
412 | switch (reg) { | |
0322191e DA |
413 | case SDHCI_CLOCK_CONTROL: |
414 | new_val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); | |
415 | if (val & SDHCI_CLOCK_CARD_EN) | |
416 | new_val |= ESDHC_VENDOR_SPEC_FRC_SDCLK_ON; | |
417 | else | |
418 | new_val &= ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON; | |
eeed7026 | 419 | writel(new_val, host->ioaddr + ESDHC_VENDOR_SPEC); |
0322191e DA |
420 | return; |
421 | case SDHCI_HOST_CONTROL2: | |
422 | new_val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); | |
423 | if (val & SDHCI_CTRL_VDD_180) | |
424 | new_val |= ESDHC_VENDOR_SPEC_VSELECT; | |
425 | else | |
426 | new_val &= ~ESDHC_VENDOR_SPEC_VSELECT; | |
427 | writel(new_val, host->ioaddr + ESDHC_VENDOR_SPEC); | |
6e9fd28e DA |
428 | if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) { |
429 | new_val = readl(host->ioaddr + ESDHC_MIX_CTRL); | |
430 | if (val & SDHCI_CTRL_TUNED_CLK) | |
431 | new_val |= ESDHC_MIX_CTRL_SMPCLK_SEL; | |
432 | else | |
433 | new_val &= ~ESDHC_MIX_CTRL_SMPCLK_SEL; | |
434 | writel(new_val , host->ioaddr + ESDHC_MIX_CTRL); | |
435 | } else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) { | |
436 | u32 v = readl(host->ioaddr + SDHCI_ACMD12_ERR); | |
437 | u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL); | |
8b2bb0ad DA |
438 | if (val & SDHCI_CTRL_TUNED_CLK) { |
439 | v |= ESDHC_MIX_CTRL_SMPCLK_SEL; | |
440 | } else { | |
441 | v &= ~ESDHC_MIX_CTRL_SMPCLK_SEL; | |
442 | m &= ~ESDHC_MIX_CTRL_FBCLK_SEL; | |
443 | } | |
444 | ||
6e9fd28e | 445 | if (val & SDHCI_CTRL_EXEC_TUNING) { |
6e9fd28e DA |
446 | v |= ESDHC_MIX_CTRL_EXE_TUNE; |
447 | m |= ESDHC_MIX_CTRL_FBCLK_SEL; | |
448 | } else { | |
6e9fd28e | 449 | v &= ~ESDHC_MIX_CTRL_EXE_TUNE; |
6e9fd28e DA |
450 | } |
451 | ||
6e9fd28e DA |
452 | writel(v, host->ioaddr + SDHCI_ACMD12_ERR); |
453 | writel(m, host->ioaddr + ESDHC_MIX_CTRL); | |
454 | } | |
0322191e | 455 | return; |
95f25efe | 456 | case SDHCI_TRANSFER_MODE: |
f47c4bbf | 457 | if ((imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT) |
58ac8177 RZ |
458 | && (host->cmd->opcode == SD_IO_RW_EXTENDED) |
459 | && (host->cmd->data->blocks > 1) | |
460 | && (host->cmd->data->flags & MMC_DATA_READ)) { | |
461 | u32 v; | |
60bf6396 SG |
462 | v = readl(host->ioaddr + ESDHC_VENDOR_SPEC); |
463 | v |= ESDHC_VENDOR_SPEC_SDIO_QUIRK; | |
464 | writel(v, host->ioaddr + ESDHC_VENDOR_SPEC); | |
58ac8177 | 465 | } |
69f54698 | 466 | |
9d61c009 | 467 | if (esdhc_is_usdhc(imx_data)) { |
69f54698 | 468 | u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL); |
2a15f981 SG |
469 | /* Swap AC23 bit */ |
470 | if (val & SDHCI_TRNS_AUTO_CMD23) { | |
471 | val &= ~SDHCI_TRNS_AUTO_CMD23; | |
472 | val |= ESDHC_MIX_CTRL_AC23EN; | |
473 | } | |
474 | m = val | (m & ~ESDHC_MIX_CTRL_SDHCI_MASK); | |
69f54698 SG |
475 | writel(m, host->ioaddr + ESDHC_MIX_CTRL); |
476 | } else { | |
477 | /* | |
478 | * Postpone this write, we must do it together with a | |
479 | * command write that is down below. | |
480 | */ | |
481 | imx_data->scratchpad = val; | |
482 | } | |
95f25efe WS |
483 | return; |
484 | case SDHCI_COMMAND: | |
361b8482 | 485 | if (host->cmd->opcode == MMC_STOP_TRANSMISSION) |
58ac8177 | 486 | val |= SDHCI_CMD_ABORTCMD; |
95a2482a | 487 | |
361b8482 | 488 | if ((host->cmd->opcode == MMC_SET_BLOCK_COUNT) && |
f47c4bbf | 489 | (imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT)) |
361b8482 LS |
490 | imx_data->multiblock_status = MULTIBLK_IN_PROCESS; |
491 | ||
9d61c009 | 492 | if (esdhc_is_usdhc(imx_data)) |
95a2482a SG |
493 | writel(val << 16, |
494 | host->ioaddr + SDHCI_TRANSFER_MODE); | |
69f54698 | 495 | else |
95a2482a SG |
496 | writel(val << 16 | imx_data->scratchpad, |
497 | host->ioaddr + SDHCI_TRANSFER_MODE); | |
95f25efe WS |
498 | return; |
499 | case SDHCI_BLOCK_SIZE: | |
500 | val &= ~SDHCI_MAKE_BLKSZ(0x7, 0); | |
501 | break; | |
502 | } | |
503 | esdhc_clrset_le(host, 0xffff, val, reg); | |
504 | } | |
505 | ||
506 | static void esdhc_writeb_le(struct sdhci_host *host, u8 val, int reg) | |
507 | { | |
9a0985b7 WC |
508 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
509 | struct pltfm_imx_data *imx_data = pltfm_host->priv; | |
95f25efe | 510 | u32 new_val; |
af51079e | 511 | u32 mask; |
95f25efe WS |
512 | |
513 | switch (reg) { | |
514 | case SDHCI_POWER_CONTROL: | |
515 | /* | |
516 | * FSL put some DMA bits here | |
517 | * If your board has a regulator, code should be here | |
518 | */ | |
519 | return; | |
520 | case SDHCI_HOST_CONTROL: | |
6b40d182 | 521 | /* FSL messed up here, so we need to manually compose it. */ |
af51079e | 522 | new_val = val & SDHCI_CTRL_LED; |
7122bbb0 | 523 | /* ensure the endianness */ |
95f25efe | 524 | new_val |= ESDHC_HOST_CONTROL_LE; |
9a0985b7 WC |
525 | /* bits 8&9 are reserved on mx25 */ |
526 | if (!is_imx25_esdhc(imx_data)) { | |
527 | /* DMA mode bits are shifted */ | |
528 | new_val |= (val & SDHCI_CTRL_DMA_MASK) << 5; | |
529 | } | |
95f25efe | 530 | |
af51079e SH |
531 | /* |
532 | * Do not touch buswidth bits here. This is done in | |
533 | * esdhc_pltfm_bus_width. | |
f6825748 MF |
534 | * Do not touch the D3CD bit either which is used for the |
535 | * SDIO interrupt errata workaround. | |
af51079e | 536 | */ |
f6825748 | 537 | mask = 0xffff & ~(ESDHC_CTRL_BUSWIDTH_MASK | ESDHC_CTRL_D3CD); |
af51079e SH |
538 | |
539 | esdhc_clrset_le(host, mask, new_val, reg); | |
95f25efe WS |
540 | return; |
541 | } | |
542 | esdhc_clrset_le(host, 0xff, val, reg); | |
913413c3 SG |
543 | |
544 | /* | |
545 | * The esdhc has a design violation to SDHC spec which tells | |
546 | * that software reset should not affect card detection circuit. | |
547 | * But esdhc clears its SYSCTL register bits [0..2] during the | |
548 | * software reset. This will stop those clocks that card detection | |
549 | * circuit relies on. To work around it, we turn the clocks on back | |
550 | * to keep card detection circuit functional. | |
551 | */ | |
58c8c4fb | 552 | if ((reg == SDHCI_SOFTWARE_RESET) && (val & 1)) { |
913413c3 | 553 | esdhc_clrset_le(host, 0x7, 0x7, ESDHC_SYSTEM_CONTROL); |
58c8c4fb SG |
554 | /* |
555 | * The reset on usdhc fails to clear MIX_CTRL register. | |
556 | * Do it manually here. | |
557 | */ | |
de5bdbff | 558 | if (esdhc_is_usdhc(imx_data)) { |
d131a71c DA |
559 | /* the tuning bits should be kept during reset */ |
560 | new_val = readl(host->ioaddr + ESDHC_MIX_CTRL); | |
561 | writel(new_val & ESDHC_MIX_CTRL_TUNING_MASK, | |
562 | host->ioaddr + ESDHC_MIX_CTRL); | |
de5bdbff DA |
563 | imx_data->is_ddr = 0; |
564 | } | |
58c8c4fb | 565 | } |
95f25efe WS |
566 | } |
567 | ||
0ddf03c9 LS |
568 | static unsigned int esdhc_pltfm_get_max_clock(struct sdhci_host *host) |
569 | { | |
570 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
571 | struct pltfm_imx_data *imx_data = pltfm_host->priv; | |
572 | struct esdhc_platform_data *boarddata = &imx_data->boarddata; | |
573 | ||
a974862f | 574 | if (boarddata->f_max && (boarddata->f_max < pltfm_host->clock)) |
0ddf03c9 LS |
575 | return boarddata->f_max; |
576 | else | |
a974862f | 577 | return pltfm_host->clock; |
0ddf03c9 LS |
578 | } |
579 | ||
95f25efe WS |
580 | static unsigned int esdhc_pltfm_get_min_clock(struct sdhci_host *host) |
581 | { | |
582 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
583 | ||
a974862f | 584 | return pltfm_host->clock / 256 / 16; |
95f25efe WS |
585 | } |
586 | ||
8ba9580a LS |
587 | static inline void esdhc_pltfm_set_clock(struct sdhci_host *host, |
588 | unsigned int clock) | |
589 | { | |
590 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
fed2f6e2 | 591 | struct pltfm_imx_data *imx_data = pltfm_host->priv; |
a974862f | 592 | unsigned int host_clock = pltfm_host->clock; |
d31fc00a DA |
593 | int pre_div = 2; |
594 | int div = 1; | |
fed2f6e2 | 595 | u32 temp, val; |
d31fc00a | 596 | |
fed2f6e2 | 597 | if (clock == 0) { |
1650d0c7 RK |
598 | host->mmc->actual_clock = 0; |
599 | ||
9d61c009 | 600 | if (esdhc_is_usdhc(imx_data)) { |
fed2f6e2 DA |
601 | val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); |
602 | writel(val & ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON, | |
603 | host->ioaddr + ESDHC_VENDOR_SPEC); | |
604 | } | |
373073ef | 605 | return; |
fed2f6e2 | 606 | } |
d31fc00a | 607 | |
de5bdbff | 608 | if (esdhc_is_usdhc(imx_data) && !imx_data->is_ddr) |
5f7886c5 DA |
609 | pre_div = 1; |
610 | ||
d31fc00a DA |
611 | temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL); |
612 | temp &= ~(ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN | |
613 | | ESDHC_CLOCK_MASK); | |
614 | sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL); | |
615 | ||
616 | while (host_clock / pre_div / 16 > clock && pre_div < 256) | |
617 | pre_div *= 2; | |
618 | ||
619 | while (host_clock / pre_div / div > clock && div < 16) | |
620 | div++; | |
621 | ||
e76b8559 | 622 | host->mmc->actual_clock = host_clock / pre_div / div; |
d31fc00a | 623 | dev_dbg(mmc_dev(host->mmc), "desired SD clock: %d, actual: %d\n", |
e76b8559 | 624 | clock, host->mmc->actual_clock); |
d31fc00a | 625 | |
de5bdbff DA |
626 | if (imx_data->is_ddr) |
627 | pre_div >>= 2; | |
628 | else | |
629 | pre_div >>= 1; | |
d31fc00a DA |
630 | div--; |
631 | ||
632 | temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL); | |
633 | temp |= (ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN | |
634 | | (div << ESDHC_DIVIDER_SHIFT) | |
635 | | (pre_div << ESDHC_PREDIV_SHIFT)); | |
636 | sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL); | |
fed2f6e2 | 637 | |
9d61c009 | 638 | if (esdhc_is_usdhc(imx_data)) { |
fed2f6e2 DA |
639 | val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); |
640 | writel(val | ESDHC_VENDOR_SPEC_FRC_SDCLK_ON, | |
641 | host->ioaddr + ESDHC_VENDOR_SPEC); | |
642 | } | |
643 | ||
d31fc00a | 644 | mdelay(1); |
8ba9580a LS |
645 | } |
646 | ||
913413c3 SG |
647 | static unsigned int esdhc_pltfm_get_ro(struct sdhci_host *host) |
648 | { | |
842afc02 SG |
649 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
650 | struct pltfm_imx_data *imx_data = pltfm_host->priv; | |
651 | struct esdhc_platform_data *boarddata = &imx_data->boarddata; | |
913413c3 SG |
652 | |
653 | switch (boarddata->wp_type) { | |
654 | case ESDHC_WP_GPIO: | |
fbe5fdd1 | 655 | return mmc_gpio_get_ro(host->mmc); |
913413c3 SG |
656 | case ESDHC_WP_CONTROLLER: |
657 | return !(readl(host->ioaddr + SDHCI_PRESENT_STATE) & | |
658 | SDHCI_WRITE_PROTECT); | |
659 | case ESDHC_WP_NONE: | |
660 | break; | |
661 | } | |
662 | ||
663 | return -ENOSYS; | |
664 | } | |
665 | ||
2317f56c | 666 | static void esdhc_pltfm_set_bus_width(struct sdhci_host *host, int width) |
af51079e SH |
667 | { |
668 | u32 ctrl; | |
669 | ||
670 | switch (width) { | |
671 | case MMC_BUS_WIDTH_8: | |
672 | ctrl = ESDHC_CTRL_8BITBUS; | |
673 | break; | |
674 | case MMC_BUS_WIDTH_4: | |
675 | ctrl = ESDHC_CTRL_4BITBUS; | |
676 | break; | |
677 | default: | |
678 | ctrl = 0; | |
679 | break; | |
680 | } | |
681 | ||
682 | esdhc_clrset_le(host, ESDHC_CTRL_BUSWIDTH_MASK, ctrl, | |
683 | SDHCI_HOST_CONTROL); | |
af51079e SH |
684 | } |
685 | ||
0322191e DA |
686 | static void esdhc_prepare_tuning(struct sdhci_host *host, u32 val) |
687 | { | |
688 | u32 reg; | |
689 | ||
690 | /* FIXME: delay a bit for card to be ready for next tuning due to errors */ | |
691 | mdelay(1); | |
692 | ||
693 | reg = readl(host->ioaddr + ESDHC_MIX_CTRL); | |
694 | reg |= ESDHC_MIX_CTRL_EXE_TUNE | ESDHC_MIX_CTRL_SMPCLK_SEL | | |
695 | ESDHC_MIX_CTRL_FBCLK_SEL; | |
696 | writel(reg, host->ioaddr + ESDHC_MIX_CTRL); | |
697 | writel(val << 8, host->ioaddr + ESDHC_TUNE_CTRL_STATUS); | |
698 | dev_dbg(mmc_dev(host->mmc), | |
699 | "tunning with delay 0x%x ESDHC_TUNE_CTRL_STATUS 0x%x\n", | |
700 | val, readl(host->ioaddr + ESDHC_TUNE_CTRL_STATUS)); | |
701 | } | |
702 | ||
0322191e DA |
703 | static void esdhc_post_tuning(struct sdhci_host *host) |
704 | { | |
705 | u32 reg; | |
706 | ||
707 | reg = readl(host->ioaddr + ESDHC_MIX_CTRL); | |
708 | reg &= ~ESDHC_MIX_CTRL_EXE_TUNE; | |
709 | writel(reg, host->ioaddr + ESDHC_MIX_CTRL); | |
710 | } | |
711 | ||
712 | static int esdhc_executing_tuning(struct sdhci_host *host, u32 opcode) | |
713 | { | |
714 | int min, max, avg, ret; | |
715 | ||
716 | /* find the mininum delay first which can pass tuning */ | |
717 | min = ESDHC_TUNE_CTRL_MIN; | |
718 | while (min < ESDHC_TUNE_CTRL_MAX) { | |
719 | esdhc_prepare_tuning(host, min); | |
d1785326 | 720 | if (!mmc_send_tuning(host->mmc)) |
0322191e DA |
721 | break; |
722 | min += ESDHC_TUNE_CTRL_STEP; | |
723 | } | |
724 | ||
725 | /* find the maxinum delay which can not pass tuning */ | |
726 | max = min + ESDHC_TUNE_CTRL_STEP; | |
727 | while (max < ESDHC_TUNE_CTRL_MAX) { | |
728 | esdhc_prepare_tuning(host, max); | |
d1785326 | 729 | if (mmc_send_tuning(host->mmc)) { |
0322191e DA |
730 | max -= ESDHC_TUNE_CTRL_STEP; |
731 | break; | |
732 | } | |
733 | max += ESDHC_TUNE_CTRL_STEP; | |
734 | } | |
735 | ||
736 | /* use average delay to get the best timing */ | |
737 | avg = (min + max) / 2; | |
738 | esdhc_prepare_tuning(host, avg); | |
d1785326 | 739 | ret = mmc_send_tuning(host->mmc); |
0322191e DA |
740 | esdhc_post_tuning(host); |
741 | ||
742 | dev_dbg(mmc_dev(host->mmc), "tunning %s at 0x%x ret %d\n", | |
743 | ret ? "failed" : "passed", avg, ret); | |
744 | ||
745 | return ret; | |
746 | } | |
747 | ||
ad93220d DA |
748 | static int esdhc_change_pinstate(struct sdhci_host *host, |
749 | unsigned int uhs) | |
750 | { | |
751 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
752 | struct pltfm_imx_data *imx_data = pltfm_host->priv; | |
753 | struct pinctrl_state *pinctrl; | |
754 | ||
755 | dev_dbg(mmc_dev(host->mmc), "change pinctrl state for uhs %d\n", uhs); | |
756 | ||
757 | if (IS_ERR(imx_data->pinctrl) || | |
758 | IS_ERR(imx_data->pins_default) || | |
759 | IS_ERR(imx_data->pins_100mhz) || | |
760 | IS_ERR(imx_data->pins_200mhz)) | |
761 | return -EINVAL; | |
762 | ||
763 | switch (uhs) { | |
764 | case MMC_TIMING_UHS_SDR50: | |
765 | pinctrl = imx_data->pins_100mhz; | |
766 | break; | |
767 | case MMC_TIMING_UHS_SDR104: | |
429a5b45 | 768 | case MMC_TIMING_MMC_HS200: |
ad93220d DA |
769 | pinctrl = imx_data->pins_200mhz; |
770 | break; | |
771 | default: | |
772 | /* back to default state for other legacy timing */ | |
773 | pinctrl = imx_data->pins_default; | |
774 | } | |
775 | ||
776 | return pinctrl_select_state(imx_data->pinctrl, pinctrl); | |
777 | } | |
778 | ||
850a29b8 | 779 | static void esdhc_set_uhs_signaling(struct sdhci_host *host, unsigned timing) |
ad93220d DA |
780 | { |
781 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
782 | struct pltfm_imx_data *imx_data = pltfm_host->priv; | |
602519b2 | 783 | struct esdhc_platform_data *boarddata = &imx_data->boarddata; |
ad93220d | 784 | |
850a29b8 | 785 | switch (timing) { |
ad93220d | 786 | case MMC_TIMING_UHS_SDR12: |
ad93220d | 787 | case MMC_TIMING_UHS_SDR25: |
ad93220d | 788 | case MMC_TIMING_UHS_SDR50: |
ad93220d | 789 | case MMC_TIMING_UHS_SDR104: |
429a5b45 | 790 | case MMC_TIMING_MMC_HS200: |
ad93220d DA |
791 | break; |
792 | case MMC_TIMING_UHS_DDR50: | |
69f5bf38 | 793 | case MMC_TIMING_MMC_DDR52: |
de5bdbff DA |
794 | writel(readl(host->ioaddr + ESDHC_MIX_CTRL) | |
795 | ESDHC_MIX_CTRL_DDREN, | |
796 | host->ioaddr + ESDHC_MIX_CTRL); | |
797 | imx_data->is_ddr = 1; | |
602519b2 DA |
798 | if (boarddata->delay_line) { |
799 | u32 v; | |
800 | v = boarddata->delay_line << | |
801 | ESDHC_DLL_OVERRIDE_VAL_SHIFT | | |
802 | (1 << ESDHC_DLL_OVERRIDE_EN_SHIFT); | |
803 | if (is_imx53_esdhc(imx_data)) | |
804 | v <<= 1; | |
805 | writel(v, host->ioaddr + ESDHC_DLL_CTRL); | |
806 | } | |
ad93220d DA |
807 | break; |
808 | } | |
809 | ||
850a29b8 | 810 | esdhc_change_pinstate(host, timing); |
ad93220d DA |
811 | } |
812 | ||
0718e59a RK |
813 | static void esdhc_reset(struct sdhci_host *host, u8 mask) |
814 | { | |
815 | sdhci_reset(host, mask); | |
816 | ||
817 | sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); | |
818 | sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); | |
819 | } | |
820 | ||
10fd0ad9 AD |
821 | static unsigned int esdhc_get_max_timeout_count(struct sdhci_host *host) |
822 | { | |
823 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
824 | struct pltfm_imx_data *imx_data = pltfm_host->priv; | |
825 | ||
826 | return esdhc_is_usdhc(imx_data) ? 1 << 28 : 1 << 27; | |
827 | } | |
828 | ||
e33eb8e2 AD |
829 | static void esdhc_set_timeout(struct sdhci_host *host, struct mmc_command *cmd) |
830 | { | |
831 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
832 | struct pltfm_imx_data *imx_data = pltfm_host->priv; | |
833 | ||
834 | /* use maximum timeout counter */ | |
835 | sdhci_writeb(host, esdhc_is_usdhc(imx_data) ? 0xF : 0xE, | |
836 | SDHCI_TIMEOUT_CONTROL); | |
837 | } | |
838 | ||
6e9fd28e | 839 | static struct sdhci_ops sdhci_esdhc_ops = { |
e149860d | 840 | .read_l = esdhc_readl_le, |
0c6d49ce | 841 | .read_w = esdhc_readw_le, |
e149860d | 842 | .write_l = esdhc_writel_le, |
0c6d49ce WS |
843 | .write_w = esdhc_writew_le, |
844 | .write_b = esdhc_writeb_le, | |
8ba9580a | 845 | .set_clock = esdhc_pltfm_set_clock, |
0ddf03c9 | 846 | .get_max_clock = esdhc_pltfm_get_max_clock, |
0c6d49ce | 847 | .get_min_clock = esdhc_pltfm_get_min_clock, |
10fd0ad9 | 848 | .get_max_timeout_count = esdhc_get_max_timeout_count, |
913413c3 | 849 | .get_ro = esdhc_pltfm_get_ro, |
e33eb8e2 | 850 | .set_timeout = esdhc_set_timeout, |
2317f56c | 851 | .set_bus_width = esdhc_pltfm_set_bus_width, |
ad93220d | 852 | .set_uhs_signaling = esdhc_set_uhs_signaling, |
0718e59a | 853 | .reset = esdhc_reset, |
0c6d49ce WS |
854 | }; |
855 | ||
1db5eebf | 856 | static const struct sdhci_pltfm_data sdhci_esdhc_imx_pdata = { |
97e4ba6a RZ |
857 | .quirks = ESDHC_DEFAULT_QUIRKS | SDHCI_QUIRK_NO_HISPD_BIT |
858 | | SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC | |
859 | | SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | |
85d6509d | 860 | | SDHCI_QUIRK_BROKEN_CARD_DETECTION, |
85d6509d SG |
861 | .ops = &sdhci_esdhc_ops, |
862 | }; | |
863 | ||
abfafc2d | 864 | #ifdef CONFIG_OF |
c3be1efd | 865 | static int |
abfafc2d | 866 | sdhci_esdhc_imx_probe_dt(struct platform_device *pdev, |
07bf2b54 | 867 | struct sdhci_host *host, |
abfafc2d SG |
868 | struct esdhc_platform_data *boarddata) |
869 | { | |
870 | struct device_node *np = pdev->dev.of_node; | |
871 | ||
872 | if (!np) | |
873 | return -ENODEV; | |
874 | ||
7f217794 | 875 | if (of_get_property(np, "non-removable", NULL)) |
abfafc2d SG |
876 | boarddata->cd_type = ESDHC_CD_PERMANENT; |
877 | ||
878 | if (of_get_property(np, "fsl,cd-controller", NULL)) | |
879 | boarddata->cd_type = ESDHC_CD_CONTROLLER; | |
880 | ||
881 | if (of_get_property(np, "fsl,wp-controller", NULL)) | |
882 | boarddata->wp_type = ESDHC_WP_CONTROLLER; | |
883 | ||
884 | boarddata->cd_gpio = of_get_named_gpio(np, "cd-gpios", 0); | |
885 | if (gpio_is_valid(boarddata->cd_gpio)) | |
886 | boarddata->cd_type = ESDHC_CD_GPIO; | |
887 | ||
888 | boarddata->wp_gpio = of_get_named_gpio(np, "wp-gpios", 0); | |
889 | if (gpio_is_valid(boarddata->wp_gpio)) | |
890 | boarddata->wp_type = ESDHC_WP_GPIO; | |
891 | ||
af51079e SH |
892 | of_property_read_u32(np, "bus-width", &boarddata->max_bus_width); |
893 | ||
0ddf03c9 LS |
894 | of_property_read_u32(np, "max-frequency", &boarddata->f_max); |
895 | ||
ad93220d DA |
896 | if (of_find_property(np, "no-1-8-v", NULL)) |
897 | boarddata->support_vsel = false; | |
898 | else | |
899 | boarddata->support_vsel = true; | |
900 | ||
602519b2 DA |
901 | if (of_property_read_u32(np, "fsl,delay-line", &boarddata->delay_line)) |
902 | boarddata->delay_line = 0; | |
903 | ||
07bf2b54 SH |
904 | mmc_of_parse_voltage(np, &host->ocr_mask); |
905 | ||
abfafc2d SG |
906 | return 0; |
907 | } | |
908 | #else | |
909 | static inline int | |
910 | sdhci_esdhc_imx_probe_dt(struct platform_device *pdev, | |
07bf2b54 | 911 | struct sdhci_host *host, |
abfafc2d SG |
912 | struct esdhc_platform_data *boarddata) |
913 | { | |
914 | return -ENODEV; | |
915 | } | |
916 | #endif | |
917 | ||
c3be1efd | 918 | static int sdhci_esdhc_imx_probe(struct platform_device *pdev) |
95f25efe | 919 | { |
abfafc2d SG |
920 | const struct of_device_id *of_id = |
921 | of_match_device(imx_esdhc_dt_ids, &pdev->dev); | |
85d6509d SG |
922 | struct sdhci_pltfm_host *pltfm_host; |
923 | struct sdhci_host *host; | |
924 | struct esdhc_platform_data *boarddata; | |
0c6d49ce | 925 | int err; |
e149860d | 926 | struct pltfm_imx_data *imx_data; |
95f25efe | 927 | |
0e748234 | 928 | host = sdhci_pltfm_init(pdev, &sdhci_esdhc_imx_pdata, 0); |
85d6509d SG |
929 | if (IS_ERR(host)) |
930 | return PTR_ERR(host); | |
931 | ||
932 | pltfm_host = sdhci_priv(host); | |
933 | ||
e3af31c6 | 934 | imx_data = devm_kzalloc(&pdev->dev, sizeof(*imx_data), GFP_KERNEL); |
abfafc2d SG |
935 | if (!imx_data) { |
936 | err = -ENOMEM; | |
e3af31c6 | 937 | goto free_sdhci; |
abfafc2d | 938 | } |
57ed3314 | 939 | |
f47c4bbf SG |
940 | imx_data->socdata = of_id ? of_id->data : (struct esdhc_soc_data *) |
941 | pdev->id_entry->driver_data; | |
85d6509d SG |
942 | pltfm_host->priv = imx_data; |
943 | ||
52dac615 SH |
944 | imx_data->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); |
945 | if (IS_ERR(imx_data->clk_ipg)) { | |
946 | err = PTR_ERR(imx_data->clk_ipg); | |
e3af31c6 | 947 | goto free_sdhci; |
95f25efe | 948 | } |
52dac615 SH |
949 | |
950 | imx_data->clk_ahb = devm_clk_get(&pdev->dev, "ahb"); | |
951 | if (IS_ERR(imx_data->clk_ahb)) { | |
952 | err = PTR_ERR(imx_data->clk_ahb); | |
e3af31c6 | 953 | goto free_sdhci; |
52dac615 SH |
954 | } |
955 | ||
956 | imx_data->clk_per = devm_clk_get(&pdev->dev, "per"); | |
957 | if (IS_ERR(imx_data->clk_per)) { | |
958 | err = PTR_ERR(imx_data->clk_per); | |
e3af31c6 | 959 | goto free_sdhci; |
52dac615 SH |
960 | } |
961 | ||
962 | pltfm_host->clk = imx_data->clk_per; | |
a974862f | 963 | pltfm_host->clock = clk_get_rate(pltfm_host->clk); |
52dac615 SH |
964 | clk_prepare_enable(imx_data->clk_per); |
965 | clk_prepare_enable(imx_data->clk_ipg); | |
966 | clk_prepare_enable(imx_data->clk_ahb); | |
95f25efe | 967 | |
ad93220d | 968 | imx_data->pinctrl = devm_pinctrl_get(&pdev->dev); |
e62d8b8f DA |
969 | if (IS_ERR(imx_data->pinctrl)) { |
970 | err = PTR_ERR(imx_data->pinctrl); | |
e3af31c6 | 971 | goto disable_clk; |
e62d8b8f DA |
972 | } |
973 | ||
ad93220d DA |
974 | imx_data->pins_default = pinctrl_lookup_state(imx_data->pinctrl, |
975 | PINCTRL_STATE_DEFAULT); | |
cd529af7 DB |
976 | if (IS_ERR(imx_data->pins_default)) |
977 | dev_warn(mmc_dev(host->mmc), "could not get default state\n"); | |
ad93220d | 978 | |
b8915282 | 979 | host->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL; |
37865fe9 | 980 | |
f47c4bbf | 981 | if (imx_data->socdata->flags & ESDHC_FLAG_ENGCM07207) |
0c6d49ce | 982 | /* Fix errata ENGcm07207 present on i.MX25 and i.MX35 */ |
97e4ba6a RZ |
983 | host->quirks |= SDHCI_QUIRK_NO_MULTIBLOCK |
984 | | SDHCI_QUIRK_BROKEN_ADMA; | |
0c6d49ce | 985 | |
f750ba9b SG |
986 | /* |
987 | * The imx6q ROM code will change the default watermark level setting | |
988 | * to something insane. Change it back here. | |
989 | */ | |
69ed60e0 | 990 | if (esdhc_is_usdhc(imx_data)) { |
60bf6396 | 991 | writel(0x08100810, host->ioaddr + ESDHC_WTMK_LVL); |
69ed60e0 | 992 | host->quirks2 |= SDHCI_QUIRK2_PRESET_VALUE_BROKEN; |
e2997c94 | 993 | host->mmc->caps |= MMC_CAP_1_8V_DDR; |
69ed60e0 | 994 | } |
f750ba9b | 995 | |
6e9fd28e DA |
996 | if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) |
997 | sdhci_esdhc_ops.platform_execute_tuning = | |
998 | esdhc_executing_tuning; | |
8b2bb0ad DA |
999 | |
1000 | if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) | |
1001 | writel(readl(host->ioaddr + ESDHC_TUNING_CTRL) | | |
1002 | ESDHC_STD_TUNING_EN | ESDHC_TUNING_START_TAP, | |
1003 | host->ioaddr + ESDHC_TUNING_CTRL); | |
1004 | ||
842afc02 | 1005 | boarddata = &imx_data->boarddata; |
07bf2b54 | 1006 | if (sdhci_esdhc_imx_probe_dt(pdev, host, boarddata) < 0) { |
abfafc2d SG |
1007 | if (!host->mmc->parent->platform_data) { |
1008 | dev_err(mmc_dev(host->mmc), "no board data!\n"); | |
1009 | err = -EINVAL; | |
e3af31c6 | 1010 | goto disable_clk; |
abfafc2d SG |
1011 | } |
1012 | imx_data->boarddata = *((struct esdhc_platform_data *) | |
1013 | host->mmc->parent->platform_data); | |
1014 | } | |
913413c3 | 1015 | |
913413c3 | 1016 | /* card_detect */ |
8d86e4fc | 1017 | if (boarddata->cd_type == ESDHC_CD_CONTROLLER) |
7e29c306 | 1018 | host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION; |
16a790bc | 1019 | |
af51079e SH |
1020 | switch (boarddata->max_bus_width) { |
1021 | case 8: | |
1022 | host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_4_BIT_DATA; | |
1023 | break; | |
1024 | case 4: | |
1025 | host->mmc->caps |= MMC_CAP_4_BIT_DATA; | |
1026 | break; | |
1027 | case 1: | |
1028 | default: | |
1029 | host->quirks |= SDHCI_QUIRK_FORCE_1_BIT_DATA; | |
1030 | break; | |
1031 | } | |
1032 | ||
ad93220d | 1033 | /* sdr50 and sdr104 needs work on 1.8v signal voltage */ |
cd529af7 DB |
1034 | if ((boarddata->support_vsel) && esdhc_is_usdhc(imx_data) && |
1035 | !IS_ERR(imx_data->pins_default)) { | |
ad93220d DA |
1036 | imx_data->pins_100mhz = pinctrl_lookup_state(imx_data->pinctrl, |
1037 | ESDHC_PINCTRL_STATE_100MHZ); | |
1038 | imx_data->pins_200mhz = pinctrl_lookup_state(imx_data->pinctrl, | |
1039 | ESDHC_PINCTRL_STATE_200MHZ); | |
1040 | if (IS_ERR(imx_data->pins_100mhz) || | |
1041 | IS_ERR(imx_data->pins_200mhz)) { | |
1042 | dev_warn(mmc_dev(host->mmc), | |
1043 | "could not get ultra high speed state, work on normal mode\n"); | |
1044 | /* fall back to not support uhs by specify no 1.8v quirk */ | |
1045 | host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V; | |
1046 | } | |
1047 | } else { | |
1048 | host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V; | |
1049 | } | |
1050 | ||
8d86e4fc FE |
1051 | /* call to generic mmc_of_parse to support additional capabilities */ |
1052 | err = mmc_of_parse(host->mmc); | |
1053 | if (err) | |
1054 | goto disable_clk; | |
1055 | ||
85d6509d SG |
1056 | err = sdhci_add_host(host); |
1057 | if (err) | |
e3af31c6 | 1058 | goto disable_clk; |
85d6509d | 1059 | |
89d7e5c1 | 1060 | pm_runtime_set_active(&pdev->dev); |
89d7e5c1 DA |
1061 | pm_runtime_set_autosuspend_delay(&pdev->dev, 50); |
1062 | pm_runtime_use_autosuspend(&pdev->dev); | |
1063 | pm_suspend_ignore_children(&pdev->dev, 1); | |
77903c01 | 1064 | pm_runtime_enable(&pdev->dev); |
89d7e5c1 | 1065 | |
95f25efe | 1066 | return 0; |
7e29c306 | 1067 | |
e3af31c6 | 1068 | disable_clk: |
52dac615 SH |
1069 | clk_disable_unprepare(imx_data->clk_per); |
1070 | clk_disable_unprepare(imx_data->clk_ipg); | |
1071 | clk_disable_unprepare(imx_data->clk_ahb); | |
e3af31c6 | 1072 | free_sdhci: |
85d6509d SG |
1073 | sdhci_pltfm_free(pdev); |
1074 | return err; | |
95f25efe WS |
1075 | } |
1076 | ||
6e0ee714 | 1077 | static int sdhci_esdhc_imx_remove(struct platform_device *pdev) |
95f25efe | 1078 | { |
85d6509d | 1079 | struct sdhci_host *host = platform_get_drvdata(pdev); |
95f25efe | 1080 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
e149860d | 1081 | struct pltfm_imx_data *imx_data = pltfm_host->priv; |
85d6509d SG |
1082 | int dead = (readl(host->ioaddr + SDHCI_INT_STATUS) == 0xffffffff); |
1083 | ||
0b414368 | 1084 | pm_runtime_get_sync(&pdev->dev); |
89d7e5c1 | 1085 | pm_runtime_disable(&pdev->dev); |
0b414368 | 1086 | pm_runtime_put_noidle(&pdev->dev); |
89d7e5c1 | 1087 | |
0b414368 UH |
1088 | sdhci_remove_host(host, dead); |
1089 | ||
1090 | clk_disable_unprepare(imx_data->clk_per); | |
1091 | clk_disable_unprepare(imx_data->clk_ipg); | |
1092 | clk_disable_unprepare(imx_data->clk_ahb); | |
52dac615 | 1093 | |
85d6509d SG |
1094 | sdhci_pltfm_free(pdev); |
1095 | ||
1096 | return 0; | |
95f25efe WS |
1097 | } |
1098 | ||
162d6f98 | 1099 | #ifdef CONFIG_PM |
89d7e5c1 DA |
1100 | static int sdhci_esdhc_runtime_suspend(struct device *dev) |
1101 | { | |
1102 | struct sdhci_host *host = dev_get_drvdata(dev); | |
1103 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
1104 | struct pltfm_imx_data *imx_data = pltfm_host->priv; | |
1105 | int ret; | |
1106 | ||
1107 | ret = sdhci_runtime_suspend_host(host); | |
1108 | ||
be138554 RK |
1109 | if (!sdhci_sdio_irq_enabled(host)) { |
1110 | clk_disable_unprepare(imx_data->clk_per); | |
1111 | clk_disable_unprepare(imx_data->clk_ipg); | |
1112 | } | |
89d7e5c1 DA |
1113 | clk_disable_unprepare(imx_data->clk_ahb); |
1114 | ||
1115 | return ret; | |
1116 | } | |
1117 | ||
1118 | static int sdhci_esdhc_runtime_resume(struct device *dev) | |
1119 | { | |
1120 | struct sdhci_host *host = dev_get_drvdata(dev); | |
1121 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
1122 | struct pltfm_imx_data *imx_data = pltfm_host->priv; | |
1123 | ||
be138554 RK |
1124 | if (!sdhci_sdio_irq_enabled(host)) { |
1125 | clk_prepare_enable(imx_data->clk_per); | |
1126 | clk_prepare_enable(imx_data->clk_ipg); | |
1127 | } | |
89d7e5c1 DA |
1128 | clk_prepare_enable(imx_data->clk_ahb); |
1129 | ||
1130 | return sdhci_runtime_resume_host(host); | |
1131 | } | |
1132 | #endif | |
1133 | ||
1134 | static const struct dev_pm_ops sdhci_esdhc_pmops = { | |
1135 | SET_SYSTEM_SLEEP_PM_OPS(sdhci_pltfm_suspend, sdhci_pltfm_resume) | |
1136 | SET_RUNTIME_PM_OPS(sdhci_esdhc_runtime_suspend, | |
1137 | sdhci_esdhc_runtime_resume, NULL) | |
1138 | }; | |
1139 | ||
85d6509d SG |
1140 | static struct platform_driver sdhci_esdhc_imx_driver = { |
1141 | .driver = { | |
1142 | .name = "sdhci-esdhc-imx", | |
abfafc2d | 1143 | .of_match_table = imx_esdhc_dt_ids, |
89d7e5c1 | 1144 | .pm = &sdhci_esdhc_pmops, |
85d6509d | 1145 | }, |
57ed3314 | 1146 | .id_table = imx_esdhc_devtype, |
85d6509d | 1147 | .probe = sdhci_esdhc_imx_probe, |
0433c143 | 1148 | .remove = sdhci_esdhc_imx_remove, |
95f25efe | 1149 | }; |
85d6509d | 1150 | |
d1f81a64 | 1151 | module_platform_driver(sdhci_esdhc_imx_driver); |
85d6509d SG |
1152 | |
1153 | MODULE_DESCRIPTION("SDHCI driver for Freescale i.MX eSDHC"); | |
1154 | MODULE_AUTHOR("Wolfram Sang <w.sang@pengutronix.de>"); | |
1155 | MODULE_LICENSE("GPL v2"); |