projects / mirror_ubuntu-eoan-kernel.git / blame
| Commit | Line | Data |
|---|---|---|
| 80872e21 WS |
1 | /* |
| 2 | * Freescale eSDHC controller driver generics for OF and pltfm. | |
| 3 | * | |
| 4 | * Copyright (c) 2007 Freescale Semiconductor, Inc. | |
| 5 | * Copyright (c) 2009 MontaVista Software, Inc. | |
| 6 | * Copyright (c) 2010 Pengutronix e.K. | |
| 7 | * Author: Wolfram Sang <w.sang@pengutronix.de> | |
| 8 | * | |
| 9 | * This program is free software; you can redistribute it and/or modify | |
| 10 | * it under the terms of the GNU General Public License as published by | |
| 11 | * the Free Software Foundation; either version 2 of the License. | |
| 12 | */ | |
| 13 | ||
| 14 | #ifndef _DRIVERS_MMC_SDHCI_ESDHC_H | |
| 15 | #define _DRIVERS_MMC_SDHCI_ESDHC_H | |
| 16 | ||
| 17 | /* | |
| 18 | * Ops and quirks for the Freescale eSDHC controller. | |
| 19 | */ | |
| 20 | ||
| 21 | #define ESDHC_DEFAULT_QUIRKS (SDHCI_QUIRK_FORCE_BLK_SZ_2048 | \ | |
| cbb45093 | 22 | SDHCI_QUIRK_32BIT_DMA_ADDR | \ |
| 80872e21 | 23 | SDHCI_QUIRK_NO_BUSY_IRQ | \ |
| 80872e21 | 24 | SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | \ |
| 67b589a2 YL |
25 | SDHCI_QUIRK_PIO_NEEDS_DELAY | \ |
| 26 | SDHCI_QUIRK_NO_HISPD_BIT) | |
| 80872e21 | 27 | |
| 80872e21 WS |
28 | /* pltfm-specific */ |
| 29 | #define ESDHC_HOST_CONTROL_LE 0x20 | |
| 30 | ||
| 66b50a00 | 31 | /* |
| a6b44888 | 32 | * eSDHC register definition |
| 66b50a00 | 33 | */ |
| 80872e21 | 34 | |
| e87d2db2 | 35 | /* Present State Register */ |
| 36 | #define ESDHC_PRSSTAT 0x24 | |
| 37 | #define ESDHC_CLOCK_STABLE 0x00000008 | |
| 38 | ||
| a6b44888 | 39 | /* Protocol Control Register */ |
| 40 | #define ESDHC_PROCTL 0x28 | |
| ea35645a | 41 | #define ESDHC_VOLT_SEL 0x00000400 |
| a6b44888 | 42 | #define ESDHC_CTRL_4BITBUS (0x1 << 1) |
| 43 | #define ESDHC_CTRL_8BITBUS (0x2 << 1) | |
| 44 | #define ESDHC_CTRL_BUSWIDTH_MASK (0x3 << 1) | |
| 45 | #define ESDHC_HOST_CONTROL_RES 0x01 | |
| 46 | ||
| 47 | /* System Control Register */ | |
| 48 | #define ESDHC_SYSTEM_CONTROL 0x2c | |
| 49 | #define ESDHC_CLOCK_MASK 0x0000fff0 | |
| 50 | #define ESDHC_PREDIV_SHIFT 8 | |
| 51 | #define ESDHC_DIVIDER_SHIFT 4 | |
| e87d2db2 | 52 | #define ESDHC_CLOCK_SDCLKEN 0x00000008 |
| a6b44888 | 53 | #define ESDHC_CLOCK_PEREN 0x00000004 |
| 54 | #define ESDHC_CLOCK_HCKEN 0x00000002 | |
| 55 | #define ESDHC_CLOCK_IPGEN 0x00000001 | |
| 56 | ||
| 2f3110cc | 57 | /* Host Controller Capabilities Register 2 */ |
| 58 | #define ESDHC_CAPABILITIES_1 0x114 | |
| 59 | ||
| ba49cbd0 | 60 | /* Tuning Block Control Register */ |
| 61 | #define ESDHC_TBCTL 0x120 | |
| 54e08d9a YL |
62 | #define ESDHC_HS400_WNDW_ADJUST 0x00000040 |
| 63 | #define ESDHC_HS400_MODE 0x00000010 | |
| ba49cbd0 | 64 | #define ESDHC_TB_EN 0x00000004 |
| b1f378ab | 65 | #define ESDHC_TBPTR 0x128 |
| ba49cbd0 | 66 | |
| 54e08d9a YL |
67 | /* SD Clock Control Register */ |
| 68 | #define ESDHC_SDCLKCTL 0x144 | |
| 69 | #define ESDHC_LPBK_CLK_SEL 0x80000000 | |
| 70 | #define ESDHC_CMD_CLK_CTL 0x00008000 | |
| 71 | ||
| 72 | /* SD Timing Control Register */ | |
| 73 | #define ESDHC_SDTIMNGCTL 0x148 | |
| 74 | #define ESDHC_FLW_CTL_BG 0x00008000 | |
| 75 | ||
| 76 | /* DLL Config 0 Register */ | |
| 77 | #define ESDHC_DLLCFG0 0x160 | |
| 78 | #define ESDHC_DLL_ENABLE 0x80000000 | |
| 79 | #define ESDHC_DLL_FREQ_SEL 0x08000000 | |
| 80 | ||
| 48e304cc YL |
81 | /* DLL Config 1 Register */ |
| 82 | #define ESDHC_DLLCFG1 0x164 | |
| 83 | #define ESDHC_DLL_PD_PULSE_STRETCH_SEL 0x80000000 | |
| 84 | ||
| 54e08d9a YL |
85 | /* DLL Status 0 Register */ |
| 86 | #define ESDHC_DLLSTAT0 0x170 | |
| 87 | #define ESDHC_DLL_STS_SLV_LOCK 0x08000000 | |
| 88 | ||
| a6b44888 | 89 | /* Control Register for DMA transfer */ |
| 90 | #define ESDHC_DMA_SYSCTL 0x40c | |
| 19c3a0ef | 91 | #define ESDHC_PERIPHERAL_CLK_SEL 0x00080000 |
| ba49cbd0 | 92 | #define ESDHC_FLUSH_ASYNC_FIFO 0x00040000 |
| a6b44888 | 93 | #define ESDHC_DMA_SNOOP 0x00000040 |
| 80872e21 | 94 | |
| 80872e21 | 95 | #endif /* _DRIVERS_MMC_SDHCI_ESDHC_H */ |