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97fb5e8d | 1 | // SPDX-License-Identifier: GPL-2.0-only |
0eb0d9f4 GD |
2 | /* |
3 | * drivers/mmc/host/sdhci-msm.c - Qualcomm SDHCI Platform driver | |
4 | * | |
5 | * Copyright (c) 2013-2014, The Linux Foundation. All rights reserved. | |
0eb0d9f4 GD |
6 | */ |
7 | ||
8 | #include <linux/module.h> | |
9 | #include <linux/of_device.h> | |
0eb0d9f4 | 10 | #include <linux/delay.h> |
415b5a75 | 11 | #include <linux/mmc/mmc.h> |
67e6db11 | 12 | #include <linux/pm_runtime.h> |
415b5a75 | 13 | #include <linux/slab.h> |
cc392c58 | 14 | #include <linux/iopoll.h> |
ac06fba1 | 15 | #include <linux/regulator/consumer.h> |
0eb0d9f4 GD |
16 | |
17 | #include "sdhci-pltfm.h" | |
87a8df0d | 18 | #include "cqhci.h" |
0eb0d9f4 | 19 | |
3a3ad3e9 GD |
20 | #define CORE_MCI_VERSION 0x50 |
21 | #define CORE_VERSION_MAJOR_SHIFT 28 | |
22 | #define CORE_VERSION_MAJOR_MASK (0xf << CORE_VERSION_MAJOR_SHIFT) | |
23 | #define CORE_VERSION_MINOR_MASK 0xff | |
24 | ||
52884f8f BA |
25 | #define CORE_MCI_GENERICS 0x70 |
26 | #define SWITCHABLE_SIGNALING_VOLTAGE BIT(29) | |
27 | ||
0eb0d9f4 GD |
28 | #define HC_MODE_EN 0x1 |
29 | #define CORE_POWER 0x0 | |
30 | #define CORE_SW_RST BIT(7) | |
ff06ce41 | 31 | #define FF_CLK_SW_RST_DIS BIT(13) |
0eb0d9f4 | 32 | |
ad81d387 GD |
33 | #define CORE_PWRCTL_BUS_OFF BIT(0) |
34 | #define CORE_PWRCTL_BUS_ON BIT(1) | |
35 | #define CORE_PWRCTL_IO_LOW BIT(2) | |
36 | #define CORE_PWRCTL_IO_HIGH BIT(3) | |
37 | #define CORE_PWRCTL_BUS_SUCCESS BIT(0) | |
38 | #define CORE_PWRCTL_IO_SUCCESS BIT(2) | |
39 | #define REQ_BUS_OFF BIT(0) | |
40 | #define REQ_BUS_ON BIT(1) | |
41 | #define REQ_IO_LOW BIT(2) | |
42 | #define REQ_IO_HIGH BIT(3) | |
43 | #define INT_MASK 0xf | |
415b5a75 GD |
44 | #define MAX_PHASES 16 |
45 | #define CORE_DLL_LOCK BIT(7) | |
02e4293d | 46 | #define CORE_DDR_DLL_LOCK BIT(11) |
415b5a75 GD |
47 | #define CORE_DLL_EN BIT(16) |
48 | #define CORE_CDR_EN BIT(17) | |
49 | #define CORE_CK_OUT_EN BIT(18) | |
50 | #define CORE_CDR_EXT_EN BIT(19) | |
51 | #define CORE_DLL_PDN BIT(29) | |
52 | #define CORE_DLL_RST BIT(30) | |
cc392c58 | 53 | #define CORE_CMD_DAT_TRACK_SEL BIT(0) |
415b5a75 | 54 | |
02e4293d | 55 | #define CORE_DDR_CAL_EN BIT(0) |
83736352 VG |
56 | #define CORE_FLL_CYCLE_CNT BIT(18) |
57 | #define CORE_DLL_CLOCK_DISABLE BIT(21) | |
58 | ||
bc99266b | 59 | #define CORE_VENDOR_SPEC_POR_VAL 0xa1c |
415b5a75 | 60 | #define CORE_CLK_PWRSAVE BIT(1) |
ff06ce41 VG |
61 | #define CORE_HC_MCLK_SEL_DFLT (2 << 8) |
62 | #define CORE_HC_MCLK_SEL_HS400 (3 << 8) | |
63 | #define CORE_HC_MCLK_SEL_MASK (3 << 8) | |
5c132323 VV |
64 | #define CORE_IO_PAD_PWR_SWITCH_EN (1 << 15) |
65 | #define CORE_IO_PAD_PWR_SWITCH (1 << 16) | |
ff06ce41 VG |
66 | #define CORE_HC_SELECT_IN_EN BIT(18) |
67 | #define CORE_HC_SELECT_IN_HS400 (6 << 19) | |
68 | #define CORE_HC_SELECT_IN_MASK (7 << 19) | |
415b5a75 | 69 | |
ac06fba1 VV |
70 | #define CORE_3_0V_SUPPORT (1 << 25) |
71 | #define CORE_1_8V_SUPPORT (1 << 26) | |
5c132323 | 72 | #define CORE_VOLT_SUPPORT (CORE_3_0V_SUPPORT | CORE_1_8V_SUPPORT) |
ac06fba1 | 73 | |
cc392c58 RH |
74 | #define CORE_CSR_CDC_CTLR_CFG0 0x130 |
75 | #define CORE_SW_TRIG_FULL_CALIB BIT(16) | |
76 | #define CORE_HW_AUTOCAL_ENA BIT(17) | |
77 | ||
78 | #define CORE_CSR_CDC_CTLR_CFG1 0x134 | |
79 | #define CORE_CSR_CDC_CAL_TIMER_CFG0 0x138 | |
80 | #define CORE_TIMER_ENA BIT(16) | |
81 | ||
82 | #define CORE_CSR_CDC_CAL_TIMER_CFG1 0x13C | |
83 | #define CORE_CSR_CDC_REFCOUNT_CFG 0x140 | |
84 | #define CORE_CSR_CDC_COARSE_CAL_CFG 0x144 | |
85 | #define CORE_CDC_OFFSET_CFG 0x14C | |
86 | #define CORE_CSR_CDC_DELAY_CFG 0x150 | |
87 | #define CORE_CDC_SLAVE_DDA_CFG 0x160 | |
88 | #define CORE_CSR_CDC_STATUS0 0x164 | |
89 | #define CORE_CALIBRATION_DONE BIT(0) | |
90 | ||
91 | #define CORE_CDC_ERROR_CODE_MASK 0x7000000 | |
92 | ||
93 | #define CORE_CSR_CDC_GEN_CFG 0x178 | |
94 | #define CORE_CDC_SWITCH_BYPASS_OFF BIT(0) | |
95 | #define CORE_CDC_SWITCH_RC_EN BIT(1) | |
96 | ||
cc392c58 | 97 | #define CORE_CDC_T4_DLY_SEL BIT(0) |
44bf2312 | 98 | #define CORE_CMDIN_RCLK_EN BIT(1) |
cc392c58 | 99 | #define CORE_START_CDC_TRAFFIC BIT(6) |
bc99266b | 100 | |
02e4293d RH |
101 | #define CORE_PWRSAVE_DLL BIT(3) |
102 | ||
fa56ac97 | 103 | #define DDR_CONFIG_POR_VAL 0x80040873 |
cc392c58 | 104 | |
3a3ad3e9 | 105 | |
abf270e5 | 106 | #define INVALID_TUNING_PHASE -1 |
80031bde | 107 | #define SDHCI_MSM_MIN_CLOCK 400000 |
ff06ce41 | 108 | #define CORE_FREQ_100MHZ (100 * 1000 * 1000) |
80031bde | 109 | |
415b5a75 GD |
110 | #define CDR_SELEXT_SHIFT 20 |
111 | #define CDR_SELEXT_MASK (0xf << CDR_SELEXT_SHIFT) | |
112 | #define CMUX_SHIFT_PHASE_SHIFT 24 | |
113 | #define CMUX_SHIFT_PHASE_MASK (7 << CMUX_SHIFT_PHASE_SHIFT) | |
114 | ||
67e6db11 | 115 | #define MSM_MMC_AUTOSUSPEND_DELAY_MS 50 |
c0309b38 VV |
116 | |
117 | /* Timeout value to avoid infinite waiting for pwr_irq */ | |
118 | #define MSM_PWR_IRQ_TIMEOUT_MS 5000 | |
119 | ||
bc99266b SL |
120 | #define msm_host_readl(msm_host, host, offset) \ |
121 | msm_host->var_ops->msm_readl_relaxed(host, offset) | |
122 | ||
123 | #define msm_host_writel(msm_host, val, host, offset) \ | |
124 | msm_host->var_ops->msm_writel_relaxed(val, host, offset) | |
125 | ||
87a8df0d RH |
126 | /* CQHCI vendor specific registers */ |
127 | #define CQHCI_VENDOR_CFG1 0xA00 | |
128 | #define CQHCI_VENDOR_DIS_RST_ON_CQ_EN (0x3 << 13) | |
129 | ||
f1535888 SL |
130 | struct sdhci_msm_offset { |
131 | u32 core_hc_mode; | |
132 | u32 core_mci_data_cnt; | |
133 | u32 core_mci_status; | |
134 | u32 core_mci_fifo_cnt; | |
135 | u32 core_mci_version; | |
136 | u32 core_generics; | |
137 | u32 core_testbus_config; | |
138 | u32 core_testbus_sel2_bit; | |
139 | u32 core_testbus_ena; | |
140 | u32 core_testbus_sel2; | |
141 | u32 core_pwrctl_status; | |
142 | u32 core_pwrctl_mask; | |
143 | u32 core_pwrctl_clear; | |
144 | u32 core_pwrctl_ctl; | |
145 | u32 core_sdcc_debug_reg; | |
146 | u32 core_dll_config; | |
147 | u32 core_dll_status; | |
148 | u32 core_vendor_spec; | |
149 | u32 core_vendor_spec_adma_err_addr0; | |
150 | u32 core_vendor_spec_adma_err_addr1; | |
151 | u32 core_vendor_spec_func2; | |
152 | u32 core_vendor_spec_capabilities0; | |
153 | u32 core_ddr_200_cfg; | |
154 | u32 core_vendor_spec3; | |
155 | u32 core_dll_config_2; | |
fa56ac97 VB |
156 | u32 core_dll_config_3; |
157 | u32 core_ddr_config_old; /* Applicable to sdcc minor ver < 0x49 */ | |
f1535888 | 158 | u32 core_ddr_config; |
f1535888 SL |
159 | }; |
160 | ||
161 | static const struct sdhci_msm_offset sdhci_msm_v5_offset = { | |
162 | .core_mci_data_cnt = 0x35c, | |
163 | .core_mci_status = 0x324, | |
164 | .core_mci_fifo_cnt = 0x308, | |
165 | .core_mci_version = 0x318, | |
166 | .core_generics = 0x320, | |
167 | .core_testbus_config = 0x32c, | |
168 | .core_testbus_sel2_bit = 3, | |
169 | .core_testbus_ena = (1 << 31), | |
170 | .core_testbus_sel2 = (1 << 3), | |
171 | .core_pwrctl_status = 0x240, | |
172 | .core_pwrctl_mask = 0x244, | |
173 | .core_pwrctl_clear = 0x248, | |
174 | .core_pwrctl_ctl = 0x24c, | |
175 | .core_sdcc_debug_reg = 0x358, | |
176 | .core_dll_config = 0x200, | |
177 | .core_dll_status = 0x208, | |
178 | .core_vendor_spec = 0x20c, | |
179 | .core_vendor_spec_adma_err_addr0 = 0x214, | |
180 | .core_vendor_spec_adma_err_addr1 = 0x218, | |
181 | .core_vendor_spec_func2 = 0x210, | |
182 | .core_vendor_spec_capabilities0 = 0x21c, | |
183 | .core_ddr_200_cfg = 0x224, | |
184 | .core_vendor_spec3 = 0x250, | |
185 | .core_dll_config_2 = 0x254, | |
fa56ac97 VB |
186 | .core_dll_config_3 = 0x258, |
187 | .core_ddr_config = 0x25c, | |
f1535888 SL |
188 | }; |
189 | ||
190 | static const struct sdhci_msm_offset sdhci_msm_mci_offset = { | |
191 | .core_hc_mode = 0x78, | |
192 | .core_mci_data_cnt = 0x30, | |
193 | .core_mci_status = 0x34, | |
194 | .core_mci_fifo_cnt = 0x44, | |
195 | .core_mci_version = 0x050, | |
196 | .core_generics = 0x70, | |
197 | .core_testbus_config = 0x0cc, | |
198 | .core_testbus_sel2_bit = 4, | |
199 | .core_testbus_ena = (1 << 3), | |
200 | .core_testbus_sel2 = (1 << 4), | |
201 | .core_pwrctl_status = 0xdc, | |
202 | .core_pwrctl_mask = 0xe0, | |
203 | .core_pwrctl_clear = 0xe4, | |
204 | .core_pwrctl_ctl = 0xe8, | |
205 | .core_sdcc_debug_reg = 0x124, | |
206 | .core_dll_config = 0x100, | |
207 | .core_dll_status = 0x108, | |
208 | .core_vendor_spec = 0x10c, | |
209 | .core_vendor_spec_adma_err_addr0 = 0x114, | |
210 | .core_vendor_spec_adma_err_addr1 = 0x118, | |
211 | .core_vendor_spec_func2 = 0x110, | |
212 | .core_vendor_spec_capabilities0 = 0x11c, | |
213 | .core_ddr_200_cfg = 0x184, | |
214 | .core_vendor_spec3 = 0x1b0, | |
215 | .core_dll_config_2 = 0x1b4, | |
fa56ac97 VB |
216 | .core_ddr_config_old = 0x1b8, |
217 | .core_ddr_config = 0x1bc, | |
f1535888 SL |
218 | }; |
219 | ||
6ed4bb43 VV |
220 | struct sdhci_msm_variant_ops { |
221 | u32 (*msm_readl_relaxed)(struct sdhci_host *host, u32 offset); | |
222 | void (*msm_writel_relaxed)(u32 val, struct sdhci_host *host, | |
223 | u32 offset); | |
224 | }; | |
225 | ||
226 | /* | |
227 | * From V5, register spaces have changed. Wrap this info in a structure | |
228 | * and choose the data_structure based on version info mentioned in DT. | |
229 | */ | |
230 | struct sdhci_msm_variant_info { | |
231 | bool mci_removed; | |
21f1e2d4 | 232 | bool restore_dll_config; |
6ed4bb43 VV |
233 | const struct sdhci_msm_variant_ops *var_ops; |
234 | const struct sdhci_msm_offset *offset; | |
235 | }; | |
236 | ||
0eb0d9f4 GD |
237 | struct sdhci_msm_host { |
238 | struct platform_device *pdev; | |
239 | void __iomem *core_mem; /* MSM SDCC mapped address */ | |
ad81d387 | 240 | int pwr_irq; /* power irq */ |
0eb0d9f4 | 241 | struct clk *bus_clk; /* SDHC bus voter clock */ |
83736352 | 242 | struct clk *xo_clk; /* TCXO clk needed for FLL feature of cm_dll*/ |
4946b3af | 243 | struct clk_bulk_data bulk_clks[4]; /* core, iface, cal, sleep clocks */ |
edc609fd | 244 | unsigned long clk_rate; |
0eb0d9f4 | 245 | struct mmc_host *mmc; |
83736352 | 246 | bool use_14lpp_dll_reset; |
ff06ce41 VG |
247 | bool tuning_done; |
248 | bool calibration_done; | |
abf270e5 | 249 | u8 saved_tuning_phase; |
02e4293d | 250 | bool use_cdclp533; |
c0309b38 VV |
251 | u32 curr_pwr_state; |
252 | u32 curr_io_level; | |
253 | wait_queue_head_t pwr_irq_wait; | |
254 | bool pwr_irq_flag; | |
ac06fba1 | 255 | u32 caps_0; |
6ed4bb43 | 256 | bool mci_removed; |
21f1e2d4 | 257 | bool restore_dll_config; |
6ed4bb43 VV |
258 | const struct sdhci_msm_variant_ops *var_ops; |
259 | const struct sdhci_msm_offset *offset; | |
a89e7bcb LP |
260 | bool use_cdr; |
261 | u32 transfer_mode; | |
fa56ac97 | 262 | bool updated_ddr_cfg; |
0eb0d9f4 GD |
263 | }; |
264 | ||
bc99266b SL |
265 | static const struct sdhci_msm_offset *sdhci_priv_msm_offset(struct sdhci_host *host) |
266 | { | |
267 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
268 | struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host); | |
269 | ||
270 | return msm_host->offset; | |
271 | } | |
272 | ||
6ed4bb43 VV |
273 | /* |
274 | * APIs to read/write to vendor specific registers which were there in the | |
275 | * core_mem region before MCI was removed. | |
276 | */ | |
277 | static u32 sdhci_msm_mci_variant_readl_relaxed(struct sdhci_host *host, | |
278 | u32 offset) | |
279 | { | |
280 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
281 | struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host); | |
282 | ||
283 | return readl_relaxed(msm_host->core_mem + offset); | |
284 | } | |
285 | ||
286 | static u32 sdhci_msm_v5_variant_readl_relaxed(struct sdhci_host *host, | |
287 | u32 offset) | |
288 | { | |
289 | return readl_relaxed(host->ioaddr + offset); | |
290 | } | |
291 | ||
292 | static void sdhci_msm_mci_variant_writel_relaxed(u32 val, | |
293 | struct sdhci_host *host, u32 offset) | |
294 | { | |
295 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
296 | struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host); | |
297 | ||
298 | writel_relaxed(val, msm_host->core_mem + offset); | |
299 | } | |
300 | ||
301 | static void sdhci_msm_v5_variant_writel_relaxed(u32 val, | |
302 | struct sdhci_host *host, u32 offset) | |
303 | { | |
304 | writel_relaxed(val, host->ioaddr + offset); | |
305 | } | |
306 | ||
0fb8a3d4 RH |
307 | static unsigned int msm_get_clock_rate_for_bus_mode(struct sdhci_host *host, |
308 | unsigned int clock) | |
309 | { | |
310 | struct mmc_ios ios = host->mmc->ios; | |
311 | /* | |
312 | * The SDHC requires internal clock frequency to be double the | |
313 | * actual clock that will be set for DDR mode. The controller | |
314 | * uses the faster clock(100/400MHz) for some of its parts and | |
315 | * send the actual required clock (50/200MHz) to the card. | |
316 | */ | |
317 | if (ios.timing == MMC_TIMING_UHS_DDR50 || | |
318 | ios.timing == MMC_TIMING_MMC_DDR52 || | |
d7507aa1 RH |
319 | ios.timing == MMC_TIMING_MMC_HS400 || |
320 | host->flags & SDHCI_HS400_TUNING) | |
0fb8a3d4 RH |
321 | clock *= 2; |
322 | return clock; | |
323 | } | |
324 | ||
325 | static void msm_set_clock_rate_for_bus_mode(struct sdhci_host *host, | |
326 | unsigned int clock) | |
327 | { | |
328 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
329 | struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host); | |
330 | struct mmc_ios curr_ios = host->mmc->ios; | |
e4bf91f6 | 331 | struct clk *core_clk = msm_host->bulk_clks[0].clk; |
0fb8a3d4 RH |
332 | int rc; |
333 | ||
334 | clock = msm_get_clock_rate_for_bus_mode(host, clock); | |
e4bf91f6 | 335 | rc = clk_set_rate(core_clk, clock); |
0fb8a3d4 RH |
336 | if (rc) { |
337 | pr_err("%s: Failed to set clock at rate %u at timing %d\n", | |
338 | mmc_hostname(host->mmc), clock, | |
339 | curr_ios.timing); | |
340 | return; | |
341 | } | |
342 | msm_host->clk_rate = clock; | |
343 | pr_debug("%s: Setting clock at rate %lu at timing %d\n", | |
e4bf91f6 | 344 | mmc_hostname(host->mmc), clk_get_rate(core_clk), |
0fb8a3d4 RH |
345 | curr_ios.timing); |
346 | } | |
347 | ||
0eb0d9f4 | 348 | /* Platform specific tuning */ |
415b5a75 GD |
349 | static inline int msm_dll_poll_ck_out_en(struct sdhci_host *host, u8 poll) |
350 | { | |
351 | u32 wait_cnt = 50; | |
352 | u8 ck_out_en; | |
353 | struct mmc_host *mmc = host->mmc; | |
bc99266b SL |
354 | const struct sdhci_msm_offset *msm_offset = |
355 | sdhci_priv_msm_offset(host); | |
415b5a75 GD |
356 | |
357 | /* Poll for CK_OUT_EN bit. max. poll time = 50us */ | |
bc99266b SL |
358 | ck_out_en = !!(readl_relaxed(host->ioaddr + |
359 | msm_offset->core_dll_config) & CORE_CK_OUT_EN); | |
415b5a75 GD |
360 | |
361 | while (ck_out_en != poll) { | |
362 | if (--wait_cnt == 0) { | |
363 | dev_err(mmc_dev(mmc), "%s: CK_OUT_EN bit is not %d\n", | |
364 | mmc_hostname(mmc), poll); | |
365 | return -ETIMEDOUT; | |
366 | } | |
367 | udelay(1); | |
368 | ||
bc99266b SL |
369 | ck_out_en = !!(readl_relaxed(host->ioaddr + |
370 | msm_offset->core_dll_config) & CORE_CK_OUT_EN); | |
415b5a75 GD |
371 | } |
372 | ||
373 | return 0; | |
374 | } | |
375 | ||
376 | static int msm_config_cm_dll_phase(struct sdhci_host *host, u8 phase) | |
377 | { | |
378 | int rc; | |
379 | static const u8 grey_coded_phase_table[] = { | |
380 | 0x0, 0x1, 0x3, 0x2, 0x6, 0x7, 0x5, 0x4, | |
381 | 0xc, 0xd, 0xf, 0xe, 0xa, 0xb, 0x9, 0x8 | |
382 | }; | |
383 | unsigned long flags; | |
384 | u32 config; | |
385 | struct mmc_host *mmc = host->mmc; | |
bc99266b SL |
386 | const struct sdhci_msm_offset *msm_offset = |
387 | sdhci_priv_msm_offset(host); | |
415b5a75 | 388 | |
abf270e5 RH |
389 | if (phase > 0xf) |
390 | return -EINVAL; | |
391 | ||
415b5a75 GD |
392 | spin_lock_irqsave(&host->lock, flags); |
393 | ||
bc99266b | 394 | config = readl_relaxed(host->ioaddr + msm_offset->core_dll_config); |
415b5a75 GD |
395 | config &= ~(CORE_CDR_EN | CORE_CK_OUT_EN); |
396 | config |= (CORE_CDR_EXT_EN | CORE_DLL_EN); | |
bc99266b | 397 | writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config); |
415b5a75 GD |
398 | |
399 | /* Wait until CK_OUT_EN bit of DLL_CONFIG register becomes '0' */ | |
400 | rc = msm_dll_poll_ck_out_en(host, 0); | |
401 | if (rc) | |
402 | goto err_out; | |
403 | ||
404 | /* | |
405 | * Write the selected DLL clock output phase (0 ... 15) | |
406 | * to CDR_SELEXT bit field of DLL_CONFIG register. | |
407 | */ | |
bc99266b | 408 | config = readl_relaxed(host->ioaddr + msm_offset->core_dll_config); |
415b5a75 GD |
409 | config &= ~CDR_SELEXT_MASK; |
410 | config |= grey_coded_phase_table[phase] << CDR_SELEXT_SHIFT; | |
bc99266b | 411 | writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config); |
415b5a75 | 412 | |
bc99266b | 413 | config = readl_relaxed(host->ioaddr + msm_offset->core_dll_config); |
29301f40 | 414 | config |= CORE_CK_OUT_EN; |
bc99266b | 415 | writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config); |
415b5a75 GD |
416 | |
417 | /* Wait until CK_OUT_EN bit of DLL_CONFIG register becomes '1' */ | |
418 | rc = msm_dll_poll_ck_out_en(host, 1); | |
419 | if (rc) | |
420 | goto err_out; | |
421 | ||
bc99266b | 422 | config = readl_relaxed(host->ioaddr + msm_offset->core_dll_config); |
415b5a75 GD |
423 | config |= CORE_CDR_EN; |
424 | config &= ~CORE_CDR_EXT_EN; | |
bc99266b | 425 | writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config); |
415b5a75 GD |
426 | goto out; |
427 | ||
428 | err_out: | |
429 | dev_err(mmc_dev(mmc), "%s: Failed to set DLL phase: %d\n", | |
430 | mmc_hostname(mmc), phase); | |
431 | out: | |
432 | spin_unlock_irqrestore(&host->lock, flags); | |
433 | return rc; | |
434 | } | |
435 | ||
436 | /* | |
437 | * Find out the greatest range of consecuitive selected | |
438 | * DLL clock output phases that can be used as sampling | |
439 | * setting for SD3.0 UHS-I card read operation (in SDR104 | |
ff06ce41 VG |
440 | * timing mode) or for eMMC4.5 card read operation (in |
441 | * HS400/HS200 timing mode). | |
415b5a75 GD |
442 | * Select the 3/4 of the range and configure the DLL with the |
443 | * selected DLL clock output phase. | |
444 | */ | |
445 | ||
446 | static int msm_find_most_appropriate_phase(struct sdhci_host *host, | |
447 | u8 *phase_table, u8 total_phases) | |
448 | { | |
449 | int ret; | |
450 | u8 ranges[MAX_PHASES][MAX_PHASES] = { {0}, {0} }; | |
451 | u8 phases_per_row[MAX_PHASES] = { 0 }; | |
452 | int row_index = 0, col_index = 0, selected_row_index = 0, curr_max = 0; | |
453 | int i, cnt, phase_0_raw_index = 0, phase_15_raw_index = 0; | |
454 | bool phase_0_found = false, phase_15_found = false; | |
455 | struct mmc_host *mmc = host->mmc; | |
456 | ||
457 | if (!total_phases || (total_phases > MAX_PHASES)) { | |
458 | dev_err(mmc_dev(mmc), "%s: Invalid argument: total_phases=%d\n", | |
459 | mmc_hostname(mmc), total_phases); | |
460 | return -EINVAL; | |
461 | } | |
462 | ||
463 | for (cnt = 0; cnt < total_phases; cnt++) { | |
464 | ranges[row_index][col_index] = phase_table[cnt]; | |
465 | phases_per_row[row_index] += 1; | |
466 | col_index++; | |
467 | ||
468 | if ((cnt + 1) == total_phases) { | |
469 | continue; | |
470 | /* check if next phase in phase_table is consecutive or not */ | |
471 | } else if ((phase_table[cnt] + 1) != phase_table[cnt + 1]) { | |
472 | row_index++; | |
473 | col_index = 0; | |
474 | } | |
475 | } | |
476 | ||
477 | if (row_index >= MAX_PHASES) | |
478 | return -EINVAL; | |
479 | ||
480 | /* Check if phase-0 is present in first valid window? */ | |
481 | if (!ranges[0][0]) { | |
482 | phase_0_found = true; | |
483 | phase_0_raw_index = 0; | |
484 | /* Check if cycle exist between 2 valid windows */ | |
485 | for (cnt = 1; cnt <= row_index; cnt++) { | |
486 | if (phases_per_row[cnt]) { | |
487 | for (i = 0; i < phases_per_row[cnt]; i++) { | |
488 | if (ranges[cnt][i] == 15) { | |
489 | phase_15_found = true; | |
490 | phase_15_raw_index = cnt; | |
491 | break; | |
492 | } | |
493 | } | |
494 | } | |
495 | } | |
496 | } | |
497 | ||
498 | /* If 2 valid windows form cycle then merge them as single window */ | |
499 | if (phase_0_found && phase_15_found) { | |
500 | /* number of phases in raw where phase 0 is present */ | |
501 | u8 phases_0 = phases_per_row[phase_0_raw_index]; | |
502 | /* number of phases in raw where phase 15 is present */ | |
503 | u8 phases_15 = phases_per_row[phase_15_raw_index]; | |
504 | ||
505 | if (phases_0 + phases_15 >= MAX_PHASES) | |
506 | /* | |
507 | * If there are more than 1 phase windows then total | |
508 | * number of phases in both the windows should not be | |
509 | * more than or equal to MAX_PHASES. | |
510 | */ | |
511 | return -EINVAL; | |
512 | ||
513 | /* Merge 2 cyclic windows */ | |
514 | i = phases_15; | |
515 | for (cnt = 0; cnt < phases_0; cnt++) { | |
516 | ranges[phase_15_raw_index][i] = | |
517 | ranges[phase_0_raw_index][cnt]; | |
518 | if (++i >= MAX_PHASES) | |
519 | break; | |
520 | } | |
521 | ||
522 | phases_per_row[phase_0_raw_index] = 0; | |
523 | phases_per_row[phase_15_raw_index] = phases_15 + phases_0; | |
524 | } | |
525 | ||
526 | for (cnt = 0; cnt <= row_index; cnt++) { | |
527 | if (phases_per_row[cnt] > curr_max) { | |
528 | curr_max = phases_per_row[cnt]; | |
529 | selected_row_index = cnt; | |
530 | } | |
531 | } | |
532 | ||
533 | i = (curr_max * 3) / 4; | |
534 | if (i) | |
535 | i--; | |
536 | ||
537 | ret = ranges[selected_row_index][i]; | |
538 | ||
539 | if (ret >= MAX_PHASES) { | |
540 | ret = -EINVAL; | |
541 | dev_err(mmc_dev(mmc), "%s: Invalid phase selected=%d\n", | |
542 | mmc_hostname(mmc), ret); | |
543 | } | |
544 | ||
545 | return ret; | |
546 | } | |
547 | ||
548 | static inline void msm_cm_dll_set_freq(struct sdhci_host *host) | |
0eb0d9f4 | 549 | { |
415b5a75 | 550 | u32 mclk_freq = 0, config; |
bc99266b SL |
551 | const struct sdhci_msm_offset *msm_offset = |
552 | sdhci_priv_msm_offset(host); | |
415b5a75 GD |
553 | |
554 | /* Program the MCLK value to MCLK_FREQ bit field */ | |
555 | if (host->clock <= 112000000) | |
556 | mclk_freq = 0; | |
557 | else if (host->clock <= 125000000) | |
558 | mclk_freq = 1; | |
559 | else if (host->clock <= 137000000) | |
560 | mclk_freq = 2; | |
561 | else if (host->clock <= 150000000) | |
562 | mclk_freq = 3; | |
563 | else if (host->clock <= 162000000) | |
564 | mclk_freq = 4; | |
565 | else if (host->clock <= 175000000) | |
566 | mclk_freq = 5; | |
567 | else if (host->clock <= 187000000) | |
568 | mclk_freq = 6; | |
569 | else if (host->clock <= 200000000) | |
570 | mclk_freq = 7; | |
571 | ||
bc99266b | 572 | config = readl_relaxed(host->ioaddr + msm_offset->core_dll_config); |
415b5a75 GD |
573 | config &= ~CMUX_SHIFT_PHASE_MASK; |
574 | config |= mclk_freq << CMUX_SHIFT_PHASE_SHIFT; | |
bc99266b | 575 | writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config); |
415b5a75 GD |
576 | } |
577 | ||
578 | /* Initialize the DLL (Programmable Delay Line) */ | |
579 | static int msm_init_cm_dll(struct sdhci_host *host) | |
580 | { | |
581 | struct mmc_host *mmc = host->mmc; | |
83736352 VG |
582 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
583 | struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host); | |
415b5a75 | 584 | int wait_cnt = 50; |
5e6b6651 | 585 | unsigned long flags, xo_clk = 0; |
29301f40 | 586 | u32 config; |
bc99266b SL |
587 | const struct sdhci_msm_offset *msm_offset = |
588 | msm_host->offset; | |
415b5a75 | 589 | |
5e6b6651 JRO |
590 | if (msm_host->use_14lpp_dll_reset && !IS_ERR_OR_NULL(msm_host->xo_clk)) |
591 | xo_clk = clk_get_rate(msm_host->xo_clk); | |
592 | ||
415b5a75 GD |
593 | spin_lock_irqsave(&host->lock, flags); |
594 | ||
0eb0d9f4 | 595 | /* |
415b5a75 GD |
596 | * Make sure that clock is always enabled when DLL |
597 | * tuning is in progress. Keeping PWRSAVE ON may | |
598 | * turn off the clock. | |
0eb0d9f4 | 599 | */ |
bc99266b | 600 | config = readl_relaxed(host->ioaddr + msm_offset->core_vendor_spec); |
29301f40 | 601 | config &= ~CORE_CLK_PWRSAVE; |
bc99266b | 602 | writel_relaxed(config, host->ioaddr + msm_offset->core_vendor_spec); |
415b5a75 | 603 | |
83736352 | 604 | if (msm_host->use_14lpp_dll_reset) { |
bc99266b SL |
605 | config = readl_relaxed(host->ioaddr + |
606 | msm_offset->core_dll_config); | |
83736352 | 607 | config &= ~CORE_CK_OUT_EN; |
bc99266b SL |
608 | writel_relaxed(config, host->ioaddr + |
609 | msm_offset->core_dll_config); | |
83736352 | 610 | |
bc99266b SL |
611 | config = readl_relaxed(host->ioaddr + |
612 | msm_offset->core_dll_config_2); | |
83736352 | 613 | config |= CORE_DLL_CLOCK_DISABLE; |
bc99266b SL |
614 | writel_relaxed(config, host->ioaddr + |
615 | msm_offset->core_dll_config_2); | |
83736352 VG |
616 | } |
617 | ||
bc99266b SL |
618 | config = readl_relaxed(host->ioaddr + |
619 | msm_offset->core_dll_config); | |
29301f40 | 620 | config |= CORE_DLL_RST; |
bc99266b SL |
621 | writel_relaxed(config, host->ioaddr + |
622 | msm_offset->core_dll_config); | |
415b5a75 | 623 | |
bc99266b SL |
624 | config = readl_relaxed(host->ioaddr + |
625 | msm_offset->core_dll_config); | |
29301f40 | 626 | config |= CORE_DLL_PDN; |
bc99266b SL |
627 | writel_relaxed(config, host->ioaddr + |
628 | msm_offset->core_dll_config); | |
415b5a75 GD |
629 | msm_cm_dll_set_freq(host); |
630 | ||
83736352 VG |
631 | if (msm_host->use_14lpp_dll_reset && |
632 | !IS_ERR_OR_NULL(msm_host->xo_clk)) { | |
633 | u32 mclk_freq = 0; | |
634 | ||
bc99266b SL |
635 | config = readl_relaxed(host->ioaddr + |
636 | msm_offset->core_dll_config_2); | |
83736352 VG |
637 | config &= CORE_FLL_CYCLE_CNT; |
638 | if (config) | |
639 | mclk_freq = DIV_ROUND_CLOSEST_ULL((host->clock * 8), | |
5e6b6651 | 640 | xo_clk); |
83736352 VG |
641 | else |
642 | mclk_freq = DIV_ROUND_CLOSEST_ULL((host->clock * 4), | |
5e6b6651 | 643 | xo_clk); |
83736352 | 644 | |
bc99266b SL |
645 | config = readl_relaxed(host->ioaddr + |
646 | msm_offset->core_dll_config_2); | |
83736352 VG |
647 | config &= ~(0xFF << 10); |
648 | config |= mclk_freq << 10; | |
649 | ||
bc99266b SL |
650 | writel_relaxed(config, host->ioaddr + |
651 | msm_offset->core_dll_config_2); | |
83736352 VG |
652 | /* wait for 5us before enabling DLL clock */ |
653 | udelay(5); | |
654 | } | |
655 | ||
bc99266b SL |
656 | config = readl_relaxed(host->ioaddr + |
657 | msm_offset->core_dll_config); | |
29301f40 | 658 | config &= ~CORE_DLL_RST; |
bc99266b SL |
659 | writel_relaxed(config, host->ioaddr + |
660 | msm_offset->core_dll_config); | |
415b5a75 | 661 | |
bc99266b SL |
662 | config = readl_relaxed(host->ioaddr + |
663 | msm_offset->core_dll_config); | |
29301f40 | 664 | config &= ~CORE_DLL_PDN; |
bc99266b SL |
665 | writel_relaxed(config, host->ioaddr + |
666 | msm_offset->core_dll_config); | |
415b5a75 | 667 | |
83736352 VG |
668 | if (msm_host->use_14lpp_dll_reset) { |
669 | msm_cm_dll_set_freq(host); | |
bc99266b SL |
670 | config = readl_relaxed(host->ioaddr + |
671 | msm_offset->core_dll_config_2); | |
83736352 | 672 | config &= ~CORE_DLL_CLOCK_DISABLE; |
bc99266b SL |
673 | writel_relaxed(config, host->ioaddr + |
674 | msm_offset->core_dll_config_2); | |
83736352 VG |
675 | } |
676 | ||
bc99266b SL |
677 | config = readl_relaxed(host->ioaddr + |
678 | msm_offset->core_dll_config); | |
29301f40 | 679 | config |= CORE_DLL_EN; |
bc99266b SL |
680 | writel_relaxed(config, host->ioaddr + |
681 | msm_offset->core_dll_config); | |
415b5a75 | 682 | |
bc99266b SL |
683 | config = readl_relaxed(host->ioaddr + |
684 | msm_offset->core_dll_config); | |
29301f40 | 685 | config |= CORE_CK_OUT_EN; |
bc99266b SL |
686 | writel_relaxed(config, host->ioaddr + |
687 | msm_offset->core_dll_config); | |
415b5a75 GD |
688 | |
689 | /* Wait until DLL_LOCK bit of DLL_STATUS register becomes '1' */ | |
bc99266b | 690 | while (!(readl_relaxed(host->ioaddr + msm_offset->core_dll_status) & |
415b5a75 GD |
691 | CORE_DLL_LOCK)) { |
692 | /* max. wait for 50us sec for LOCK bit to be set */ | |
693 | if (--wait_cnt == 0) { | |
694 | dev_err(mmc_dev(mmc), "%s: DLL failed to LOCK\n", | |
695 | mmc_hostname(mmc)); | |
696 | spin_unlock_irqrestore(&host->lock, flags); | |
697 | return -ETIMEDOUT; | |
698 | } | |
699 | udelay(1); | |
700 | } | |
701 | ||
702 | spin_unlock_irqrestore(&host->lock, flags); | |
0eb0d9f4 GD |
703 | return 0; |
704 | } | |
705 | ||
b54aaa8a RH |
706 | static void msm_hc_select_default(struct sdhci_host *host) |
707 | { | |
708 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
709 | struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host); | |
710 | u32 config; | |
bc99266b SL |
711 | const struct sdhci_msm_offset *msm_offset = |
712 | msm_host->offset; | |
b54aaa8a RH |
713 | |
714 | if (!msm_host->use_cdclp533) { | |
715 | config = readl_relaxed(host->ioaddr + | |
bc99266b | 716 | msm_offset->core_vendor_spec3); |
b54aaa8a RH |
717 | config &= ~CORE_PWRSAVE_DLL; |
718 | writel_relaxed(config, host->ioaddr + | |
bc99266b | 719 | msm_offset->core_vendor_spec3); |
b54aaa8a RH |
720 | } |
721 | ||
bc99266b | 722 | config = readl_relaxed(host->ioaddr + msm_offset->core_vendor_spec); |
b54aaa8a RH |
723 | config &= ~CORE_HC_MCLK_SEL_MASK; |
724 | config |= CORE_HC_MCLK_SEL_DFLT; | |
bc99266b | 725 | writel_relaxed(config, host->ioaddr + msm_offset->core_vendor_spec); |
b54aaa8a RH |
726 | |
727 | /* | |
728 | * Disable HC_SELECT_IN to be able to use the UHS mode select | |
729 | * configuration from Host Control2 register for all other | |
730 | * modes. | |
731 | * Write 0 to HC_SELECT_IN and HC_SELECT_IN_EN field | |
732 | * in VENDOR_SPEC_FUNC | |
733 | */ | |
bc99266b | 734 | config = readl_relaxed(host->ioaddr + msm_offset->core_vendor_spec); |
b54aaa8a RH |
735 | config &= ~CORE_HC_SELECT_IN_EN; |
736 | config &= ~CORE_HC_SELECT_IN_MASK; | |
bc99266b | 737 | writel_relaxed(config, host->ioaddr + msm_offset->core_vendor_spec); |
b54aaa8a RH |
738 | |
739 | /* | |
740 | * Make sure above writes impacting free running MCLK are completed | |
741 | * before changing the clk_rate at GCC. | |
742 | */ | |
743 | wmb(); | |
744 | } | |
745 | ||
746 | static void msm_hc_select_hs400(struct sdhci_host *host) | |
747 | { | |
748 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
749 | struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host); | |
44bf2312 | 750 | struct mmc_ios ios = host->mmc->ios; |
b54aaa8a RH |
751 | u32 config, dll_lock; |
752 | int rc; | |
bc99266b SL |
753 | const struct sdhci_msm_offset *msm_offset = |
754 | msm_host->offset; | |
b54aaa8a RH |
755 | |
756 | /* Select the divided clock (free running MCLK/2) */ | |
bc99266b | 757 | config = readl_relaxed(host->ioaddr + msm_offset->core_vendor_spec); |
b54aaa8a RH |
758 | config &= ~CORE_HC_MCLK_SEL_MASK; |
759 | config |= CORE_HC_MCLK_SEL_HS400; | |
760 | ||
bc99266b | 761 | writel_relaxed(config, host->ioaddr + msm_offset->core_vendor_spec); |
b54aaa8a RH |
762 | /* |
763 | * Select HS400 mode using the HC_SELECT_IN from VENDOR SPEC | |
764 | * register | |
765 | */ | |
44bf2312 RH |
766 | if ((msm_host->tuning_done || ios.enhanced_strobe) && |
767 | !msm_host->calibration_done) { | |
bc99266b SL |
768 | config = readl_relaxed(host->ioaddr + |
769 | msm_offset->core_vendor_spec); | |
b54aaa8a RH |
770 | config |= CORE_HC_SELECT_IN_HS400; |
771 | config |= CORE_HC_SELECT_IN_EN; | |
bc99266b SL |
772 | writel_relaxed(config, host->ioaddr + |
773 | msm_offset->core_vendor_spec); | |
b54aaa8a RH |
774 | } |
775 | if (!msm_host->clk_rate && !msm_host->use_cdclp533) { | |
776 | /* | |
777 | * Poll on DLL_LOCK or DDR_DLL_LOCK bits in | |
bc99266b | 778 | * core_dll_status to be set. This should get set |
b54aaa8a RH |
779 | * within 15 us at 200 MHz. |
780 | */ | |
781 | rc = readl_relaxed_poll_timeout(host->ioaddr + | |
bc99266b | 782 | msm_offset->core_dll_status, |
b54aaa8a RH |
783 | dll_lock, |
784 | (dll_lock & | |
785 | (CORE_DLL_LOCK | | |
786 | CORE_DDR_DLL_LOCK)), 10, | |
787 | 1000); | |
788 | if (rc == -ETIMEDOUT) | |
789 | pr_err("%s: Unable to get DLL_LOCK/DDR_DLL_LOCK, dll_status: 0x%08x\n", | |
790 | mmc_hostname(host->mmc), dll_lock); | |
791 | } | |
792 | /* | |
793 | * Make sure above writes impacting free running MCLK are completed | |
794 | * before changing the clk_rate at GCC. | |
795 | */ | |
796 | wmb(); | |
797 | } | |
798 | ||
799 | /* | |
800 | * sdhci_msm_hc_select_mode :- In general all timing modes are | |
801 | * controlled via UHS mode select in Host Control2 register. | |
802 | * eMMC specific HS200/HS400 doesn't have their respective modes | |
803 | * defined here, hence we use these values. | |
804 | * | |
805 | * HS200 - SDR104 (Since they both are equivalent in functionality) | |
806 | * HS400 - This involves multiple configurations | |
807 | * Initially SDR104 - when tuning is required as HS200 | |
808 | * Then when switching to DDR @ 400MHz (HS400) we use | |
809 | * the vendor specific HC_SELECT_IN to control the mode. | |
810 | * | |
811 | * In addition to controlling the modes we also need to select the | |
812 | * correct input clock for DLL depending on the mode. | |
813 | * | |
814 | * HS400 - divided clock (free running MCLK/2) | |
815 | * All other modes - default (free running MCLK) | |
816 | */ | |
30de038d | 817 | static void sdhci_msm_hc_select_mode(struct sdhci_host *host) |
b54aaa8a RH |
818 | { |
819 | struct mmc_ios ios = host->mmc->ios; | |
820 | ||
d7507aa1 RH |
821 | if (ios.timing == MMC_TIMING_MMC_HS400 || |
822 | host->flags & SDHCI_HS400_TUNING) | |
b54aaa8a RH |
823 | msm_hc_select_hs400(host); |
824 | else | |
825 | msm_hc_select_default(host); | |
826 | } | |
827 | ||
cc392c58 RH |
828 | static int sdhci_msm_cdclp533_calibration(struct sdhci_host *host) |
829 | { | |
830 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
831 | struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host); | |
832 | u32 config, calib_done; | |
833 | int ret; | |
bc99266b SL |
834 | const struct sdhci_msm_offset *msm_offset = |
835 | msm_host->offset; | |
cc392c58 RH |
836 | |
837 | pr_debug("%s: %s: Enter\n", mmc_hostname(host->mmc), __func__); | |
838 | ||
839 | /* | |
840 | * Retuning in HS400 (DDR mode) will fail, just reset the | |
841 | * tuning block and restore the saved tuning phase. | |
842 | */ | |
843 | ret = msm_init_cm_dll(host); | |
844 | if (ret) | |
845 | goto out; | |
846 | ||
847 | /* Set the selected phase in delay line hw block */ | |
848 | ret = msm_config_cm_dll_phase(host, msm_host->saved_tuning_phase); | |
849 | if (ret) | |
850 | goto out; | |
851 | ||
bc99266b | 852 | config = readl_relaxed(host->ioaddr + msm_offset->core_dll_config); |
cc392c58 | 853 | config |= CORE_CMD_DAT_TRACK_SEL; |
bc99266b | 854 | writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config); |
cc392c58 | 855 | |
bc99266b | 856 | config = readl_relaxed(host->ioaddr + msm_offset->core_ddr_200_cfg); |
cc392c58 | 857 | config &= ~CORE_CDC_T4_DLY_SEL; |
bc99266b | 858 | writel_relaxed(config, host->ioaddr + msm_offset->core_ddr_200_cfg); |
cc392c58 RH |
859 | |
860 | config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_GEN_CFG); | |
861 | config &= ~CORE_CDC_SWITCH_BYPASS_OFF; | |
862 | writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_GEN_CFG); | |
863 | ||
864 | config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_GEN_CFG); | |
865 | config |= CORE_CDC_SWITCH_RC_EN; | |
866 | writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_GEN_CFG); | |
867 | ||
bc99266b | 868 | config = readl_relaxed(host->ioaddr + msm_offset->core_ddr_200_cfg); |
cc392c58 | 869 | config &= ~CORE_START_CDC_TRAFFIC; |
bc99266b | 870 | writel_relaxed(config, host->ioaddr + msm_offset->core_ddr_200_cfg); |
cc392c58 | 871 | |
543c576d | 872 | /* Perform CDC Register Initialization Sequence */ |
cc392c58 RH |
873 | |
874 | writel_relaxed(0x11800EC, host->ioaddr + CORE_CSR_CDC_CTLR_CFG0); | |
875 | writel_relaxed(0x3011111, host->ioaddr + CORE_CSR_CDC_CTLR_CFG1); | |
876 | writel_relaxed(0x1201000, host->ioaddr + CORE_CSR_CDC_CAL_TIMER_CFG0); | |
877 | writel_relaxed(0x4, host->ioaddr + CORE_CSR_CDC_CAL_TIMER_CFG1); | |
878 | writel_relaxed(0xCB732020, host->ioaddr + CORE_CSR_CDC_REFCOUNT_CFG); | |
879 | writel_relaxed(0xB19, host->ioaddr + CORE_CSR_CDC_COARSE_CAL_CFG); | |
083c9aa0 | 880 | writel_relaxed(0x4E2, host->ioaddr + CORE_CSR_CDC_DELAY_CFG); |
cc392c58 RH |
881 | writel_relaxed(0x0, host->ioaddr + CORE_CDC_OFFSET_CFG); |
882 | writel_relaxed(0x16334, host->ioaddr + CORE_CDC_SLAVE_DDA_CFG); | |
883 | ||
884 | /* CDC HW Calibration */ | |
885 | ||
886 | config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_CTLR_CFG0); | |
887 | config |= CORE_SW_TRIG_FULL_CALIB; | |
888 | writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_CTLR_CFG0); | |
889 | ||
890 | config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_CTLR_CFG0); | |
891 | config &= ~CORE_SW_TRIG_FULL_CALIB; | |
892 | writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_CTLR_CFG0); | |
893 | ||
894 | config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_CTLR_CFG0); | |
895 | config |= CORE_HW_AUTOCAL_ENA; | |
896 | writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_CTLR_CFG0); | |
897 | ||
898 | config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_CAL_TIMER_CFG0); | |
899 | config |= CORE_TIMER_ENA; | |
900 | writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_CAL_TIMER_CFG0); | |
901 | ||
902 | ret = readl_relaxed_poll_timeout(host->ioaddr + CORE_CSR_CDC_STATUS0, | |
903 | calib_done, | |
904 | (calib_done & CORE_CALIBRATION_DONE), | |
905 | 1, 50); | |
906 | ||
907 | if (ret == -ETIMEDOUT) { | |
908 | pr_err("%s: %s: CDC calibration was not completed\n", | |
909 | mmc_hostname(host->mmc), __func__); | |
910 | goto out; | |
911 | } | |
912 | ||
913 | ret = readl_relaxed(host->ioaddr + CORE_CSR_CDC_STATUS0) | |
914 | & CORE_CDC_ERROR_CODE_MASK; | |
915 | if (ret) { | |
916 | pr_err("%s: %s: CDC error code %d\n", | |
917 | mmc_hostname(host->mmc), __func__, ret); | |
918 | ret = -EINVAL; | |
919 | goto out; | |
920 | } | |
921 | ||
bc99266b | 922 | config = readl_relaxed(host->ioaddr + msm_offset->core_ddr_200_cfg); |
cc392c58 | 923 | config |= CORE_START_CDC_TRAFFIC; |
bc99266b | 924 | writel_relaxed(config, host->ioaddr + msm_offset->core_ddr_200_cfg); |
cc392c58 RH |
925 | out: |
926 | pr_debug("%s: %s: Exit, ret %d\n", mmc_hostname(host->mmc), | |
927 | __func__, ret); | |
928 | return ret; | |
929 | } | |
930 | ||
02e4293d RH |
931 | static int sdhci_msm_cm_dll_sdc4_calibration(struct sdhci_host *host) |
932 | { | |
44bf2312 | 933 | struct mmc_host *mmc = host->mmc; |
fa56ac97 | 934 | u32 dll_status, config, ddr_cfg_offset; |
02e4293d | 935 | int ret; |
fa56ac97 VB |
936 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
937 | struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host); | |
bc99266b SL |
938 | const struct sdhci_msm_offset *msm_offset = |
939 | sdhci_priv_msm_offset(host); | |
02e4293d RH |
940 | |
941 | pr_debug("%s: %s: Enter\n", mmc_hostname(host->mmc), __func__); | |
942 | ||
943 | /* | |
bc99266b | 944 | * Currently the core_ddr_config register defaults to desired |
02e4293d RH |
945 | * configuration on reset. Currently reprogramming the power on |
946 | * reset (POR) value in case it might have been modified by | |
947 | * bootloaders. In the future, if this changes, then the desired | |
948 | * values will need to be programmed appropriately. | |
949 | */ | |
fa56ac97 VB |
950 | if (msm_host->updated_ddr_cfg) |
951 | ddr_cfg_offset = msm_offset->core_ddr_config; | |
952 | else | |
953 | ddr_cfg_offset = msm_offset->core_ddr_config_old; | |
954 | writel_relaxed(DDR_CONFIG_POR_VAL, host->ioaddr + ddr_cfg_offset); | |
02e4293d | 955 | |
44bf2312 | 956 | if (mmc->ios.enhanced_strobe) { |
bc99266b SL |
957 | config = readl_relaxed(host->ioaddr + |
958 | msm_offset->core_ddr_200_cfg); | |
44bf2312 | 959 | config |= CORE_CMDIN_RCLK_EN; |
bc99266b SL |
960 | writel_relaxed(config, host->ioaddr + |
961 | msm_offset->core_ddr_200_cfg); | |
44bf2312 RH |
962 | } |
963 | ||
bc99266b | 964 | config = readl_relaxed(host->ioaddr + msm_offset->core_dll_config_2); |
02e4293d | 965 | config |= CORE_DDR_CAL_EN; |
bc99266b | 966 | writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config_2); |
02e4293d | 967 | |
bc99266b SL |
968 | ret = readl_relaxed_poll_timeout(host->ioaddr + |
969 | msm_offset->core_dll_status, | |
970 | dll_status, | |
971 | (dll_status & CORE_DDR_DLL_LOCK), | |
972 | 10, 1000); | |
02e4293d RH |
973 | |
974 | if (ret == -ETIMEDOUT) { | |
975 | pr_err("%s: %s: CM_DLL_SDC4 calibration was not completed\n", | |
976 | mmc_hostname(host->mmc), __func__); | |
977 | goto out; | |
978 | } | |
979 | ||
bc99266b | 980 | config = readl_relaxed(host->ioaddr + msm_offset->core_vendor_spec3); |
02e4293d | 981 | config |= CORE_PWRSAVE_DLL; |
bc99266b | 982 | writel_relaxed(config, host->ioaddr + msm_offset->core_vendor_spec3); |
02e4293d RH |
983 | |
984 | /* | |
985 | * Drain writebuffer to ensure above DLL calibration | |
986 | * and PWRSAVE DLL is enabled. | |
987 | */ | |
988 | wmb(); | |
989 | out: | |
990 | pr_debug("%s: %s: Exit, ret %d\n", mmc_hostname(host->mmc), | |
991 | __func__, ret); | |
992 | return ret; | |
993 | } | |
994 | ||
995 | static int sdhci_msm_hs400_dll_calibration(struct sdhci_host *host) | |
996 | { | |
997 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
998 | struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host); | |
44bf2312 | 999 | struct mmc_host *mmc = host->mmc; |
02e4293d RH |
1000 | int ret; |
1001 | u32 config; | |
bc99266b SL |
1002 | const struct sdhci_msm_offset *msm_offset = |
1003 | msm_host->offset; | |
02e4293d RH |
1004 | |
1005 | pr_debug("%s: %s: Enter\n", mmc_hostname(host->mmc), __func__); | |
1006 | ||
1007 | /* | |
1008 | * Retuning in HS400 (DDR mode) will fail, just reset the | |
1009 | * tuning block and restore the saved tuning phase. | |
1010 | */ | |
1011 | ret = msm_init_cm_dll(host); | |
1012 | if (ret) | |
1013 | goto out; | |
1014 | ||
44bf2312 RH |
1015 | if (!mmc->ios.enhanced_strobe) { |
1016 | /* Set the selected phase in delay line hw block */ | |
1017 | ret = msm_config_cm_dll_phase(host, | |
1018 | msm_host->saved_tuning_phase); | |
1019 | if (ret) | |
1020 | goto out; | |
bc99266b SL |
1021 | config = readl_relaxed(host->ioaddr + |
1022 | msm_offset->core_dll_config); | |
44bf2312 | 1023 | config |= CORE_CMD_DAT_TRACK_SEL; |
bc99266b SL |
1024 | writel_relaxed(config, host->ioaddr + |
1025 | msm_offset->core_dll_config); | |
44bf2312 | 1026 | } |
02e4293d | 1027 | |
02e4293d RH |
1028 | if (msm_host->use_cdclp533) |
1029 | ret = sdhci_msm_cdclp533_calibration(host); | |
1030 | else | |
1031 | ret = sdhci_msm_cm_dll_sdc4_calibration(host); | |
1032 | out: | |
1033 | pr_debug("%s: %s: Exit, ret %d\n", mmc_hostname(host->mmc), | |
1034 | __func__, ret); | |
1035 | return ret; | |
1036 | } | |
1037 | ||
21f1e2d4 VB |
1038 | static bool sdhci_msm_is_tuning_needed(struct sdhci_host *host) |
1039 | { | |
1040 | struct mmc_ios *ios = &host->mmc->ios; | |
1041 | ||
1042 | /* | |
1043 | * Tuning is required for SDR104, HS200 and HS400 cards and | |
1044 | * if clock frequency is greater than 100MHz in these modes. | |
1045 | */ | |
1046 | if (host->clock <= CORE_FREQ_100MHZ || | |
1047 | !(ios->timing == MMC_TIMING_MMC_HS400 || | |
1048 | ios->timing == MMC_TIMING_MMC_HS200 || | |
1049 | ios->timing == MMC_TIMING_UHS_SDR104) || | |
1050 | ios->enhanced_strobe) | |
1051 | return false; | |
1052 | ||
1053 | return true; | |
1054 | } | |
1055 | ||
1056 | static int sdhci_msm_restore_sdr_dll_config(struct sdhci_host *host) | |
1057 | { | |
1058 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
1059 | struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host); | |
1060 | int ret; | |
1061 | ||
1062 | /* | |
1063 | * SDR DLL comes into picture only for timing modes which needs | |
1064 | * tuning. | |
1065 | */ | |
1066 | if (!sdhci_msm_is_tuning_needed(host)) | |
1067 | return 0; | |
1068 | ||
1069 | /* Reset the tuning block */ | |
1070 | ret = msm_init_cm_dll(host); | |
1071 | if (ret) | |
1072 | return ret; | |
1073 | ||
1074 | /* Restore the tuning block */ | |
1075 | ret = msm_config_cm_dll_phase(host, msm_host->saved_tuning_phase); | |
1076 | ||
1077 | return ret; | |
1078 | } | |
1079 | ||
a89e7bcb LP |
1080 | static void sdhci_msm_set_cdr(struct sdhci_host *host, bool enable) |
1081 | { | |
1082 | const struct sdhci_msm_offset *msm_offset = sdhci_priv_msm_offset(host); | |
1083 | u32 config, oldconfig = readl_relaxed(host->ioaddr + | |
1084 | msm_offset->core_dll_config); | |
1085 | ||
1086 | config = oldconfig; | |
1087 | if (enable) { | |
1088 | config |= CORE_CDR_EN; | |
1089 | config &= ~CORE_CDR_EXT_EN; | |
1090 | } else { | |
1091 | config &= ~CORE_CDR_EN; | |
1092 | config |= CORE_CDR_EXT_EN; | |
1093 | } | |
1094 | ||
1095 | if (config != oldconfig) { | |
1096 | writel_relaxed(config, host->ioaddr + | |
1097 | msm_offset->core_dll_config); | |
1098 | } | |
1099 | } | |
1100 | ||
4436c535 | 1101 | static int sdhci_msm_execute_tuning(struct mmc_host *mmc, u32 opcode) |
415b5a75 | 1102 | { |
4436c535 | 1103 | struct sdhci_host *host = mmc_priv(mmc); |
415b5a75 | 1104 | int tuning_seq_cnt = 3; |
33d73935 | 1105 | u8 phase, tuned_phases[16], tuned_phase_cnt = 0; |
415b5a75 | 1106 | int rc; |
415b5a75 | 1107 | struct mmc_ios ios = host->mmc->ios; |
abf270e5 RH |
1108 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
1109 | struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host); | |
415b5a75 | 1110 | |
a89e7bcb LP |
1111 | if (!sdhci_msm_is_tuning_needed(host)) { |
1112 | msm_host->use_cdr = false; | |
1113 | sdhci_msm_set_cdr(host, false); | |
415b5a75 | 1114 | return 0; |
a89e7bcb LP |
1115 | } |
1116 | ||
1117 | /* Clock-Data-Recovery used to dynamically adjust RX sampling point */ | |
1118 | msm_host->use_cdr = true; | |
415b5a75 | 1119 | |
d7507aa1 RH |
1120 | /* |
1121 | * For HS400 tuning in HS200 timing requires: | |
1122 | * - select MCLK/2 in VENDOR_SPEC | |
1123 | * - program MCLK to 400MHz (or nearest supported) in GCC | |
1124 | */ | |
1125 | if (host->flags & SDHCI_HS400_TUNING) { | |
1126 | sdhci_msm_hc_select_mode(host); | |
1127 | msm_set_clock_rate_for_bus_mode(host, ios.clock); | |
4436c535 | 1128 | host->flags &= ~SDHCI_HS400_TUNING; |
d7507aa1 RH |
1129 | } |
1130 | ||
415b5a75 GD |
1131 | retry: |
1132 | /* First of all reset the tuning block */ | |
1133 | rc = msm_init_cm_dll(host); | |
1134 | if (rc) | |
33d73935 | 1135 | return rc; |
415b5a75 GD |
1136 | |
1137 | phase = 0; | |
1138 | do { | |
415b5a75 GD |
1139 | /* Set the phase in delay line hw block */ |
1140 | rc = msm_config_cm_dll_phase(host, phase); | |
1141 | if (rc) | |
33d73935 | 1142 | return rc; |
415b5a75 | 1143 | |
9979dbe5 | 1144 | rc = mmc_send_tuning(mmc, opcode, NULL); |
33d73935 | 1145 | if (!rc) { |
415b5a75 GD |
1146 | /* Tuning is successful at this tuning point */ |
1147 | tuned_phases[tuned_phase_cnt++] = phase; | |
1148 | dev_dbg(mmc_dev(mmc), "%s: Found good phase = %d\n", | |
1149 | mmc_hostname(mmc), phase); | |
1150 | } | |
1151 | } while (++phase < ARRAY_SIZE(tuned_phases)); | |
1152 | ||
1153 | if (tuned_phase_cnt) { | |
1154 | rc = msm_find_most_appropriate_phase(host, tuned_phases, | |
1155 | tuned_phase_cnt); | |
1156 | if (rc < 0) | |
33d73935 | 1157 | return rc; |
415b5a75 GD |
1158 | else |
1159 | phase = rc; | |
1160 | ||
1161 | /* | |
1162 | * Finally set the selected phase in delay | |
1163 | * line hw block. | |
1164 | */ | |
1165 | rc = msm_config_cm_dll_phase(host, phase); | |
1166 | if (rc) | |
33d73935 | 1167 | return rc; |
21f1e2d4 | 1168 | msm_host->saved_tuning_phase = phase; |
415b5a75 GD |
1169 | dev_dbg(mmc_dev(mmc), "%s: Setting the tuning phase to %d\n", |
1170 | mmc_hostname(mmc), phase); | |
1171 | } else { | |
1172 | if (--tuning_seq_cnt) | |
1173 | goto retry; | |
1174 | /* Tuning failed */ | |
1175 | dev_dbg(mmc_dev(mmc), "%s: No tuning point found\n", | |
1176 | mmc_hostname(mmc)); | |
1177 | rc = -EIO; | |
1178 | } | |
1179 | ||
ff06ce41 VG |
1180 | if (!rc) |
1181 | msm_host->tuning_done = true; | |
415b5a75 GD |
1182 | return rc; |
1183 | } | |
1184 | ||
db9bd163 RH |
1185 | /* |
1186 | * sdhci_msm_hs400 - Calibrate the DLL for HS400 bus speed mode operation. | |
44bf2312 | 1187 | * This needs to be done for both tuning and enhanced_strobe mode. |
db9bd163 RH |
1188 | * DLL operation is only needed for clock > 100MHz. For clock <= 100MHz |
1189 | * fixed feedback clock is used. | |
1190 | */ | |
1191 | static void sdhci_msm_hs400(struct sdhci_host *host, struct mmc_ios *ios) | |
1192 | { | |
1193 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
1194 | struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host); | |
1195 | int ret; | |
1196 | ||
1197 | if (host->clock > CORE_FREQ_100MHZ && | |
44bf2312 RH |
1198 | (msm_host->tuning_done || ios->enhanced_strobe) && |
1199 | !msm_host->calibration_done) { | |
db9bd163 RH |
1200 | ret = sdhci_msm_hs400_dll_calibration(host); |
1201 | if (!ret) | |
1202 | msm_host->calibration_done = true; | |
1203 | else | |
1204 | pr_err("%s: Failed to calibrate DLL for hs400 mode (%d)\n", | |
1205 | mmc_hostname(host->mmc), ret); | |
1206 | } | |
1207 | } | |
1208 | ||
ee320674 RH |
1209 | static void sdhci_msm_set_uhs_signaling(struct sdhci_host *host, |
1210 | unsigned int uhs) | |
1211 | { | |
1212 | struct mmc_host *mmc = host->mmc; | |
ff06ce41 VG |
1213 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
1214 | struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host); | |
ee320674 | 1215 | u16 ctrl_2; |
ff06ce41 | 1216 | u32 config; |
bc99266b SL |
1217 | const struct sdhci_msm_offset *msm_offset = |
1218 | msm_host->offset; | |
ee320674 RH |
1219 | |
1220 | ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); | |
1221 | /* Select Bus Speed Mode for host */ | |
1222 | ctrl_2 &= ~SDHCI_CTRL_UHS_MASK; | |
1223 | switch (uhs) { | |
1224 | case MMC_TIMING_UHS_SDR12: | |
1225 | ctrl_2 |= SDHCI_CTRL_UHS_SDR12; | |
1226 | break; | |
1227 | case MMC_TIMING_UHS_SDR25: | |
1228 | ctrl_2 |= SDHCI_CTRL_UHS_SDR25; | |
1229 | break; | |
1230 | case MMC_TIMING_UHS_SDR50: | |
1231 | ctrl_2 |= SDHCI_CTRL_UHS_SDR50; | |
1232 | break; | |
ff06ce41 | 1233 | case MMC_TIMING_MMC_HS400: |
ee320674 RH |
1234 | case MMC_TIMING_MMC_HS200: |
1235 | case MMC_TIMING_UHS_SDR104: | |
1236 | ctrl_2 |= SDHCI_CTRL_UHS_SDR104; | |
1237 | break; | |
1238 | case MMC_TIMING_UHS_DDR50: | |
1239 | case MMC_TIMING_MMC_DDR52: | |
1240 | ctrl_2 |= SDHCI_CTRL_UHS_DDR50; | |
1241 | break; | |
1242 | } | |
1243 | ||
1244 | /* | |
1245 | * When clock frequency is less than 100MHz, the feedback clock must be | |
1246 | * provided and DLL must not be used so that tuning can be skipped. To | |
1247 | * provide feedback clock, the mode selection can be any value less | |
1248 | * than 3'b011 in bits [2:0] of HOST CONTROL2 register. | |
1249 | */ | |
ff06ce41 VG |
1250 | if (host->clock <= CORE_FREQ_100MHZ) { |
1251 | if (uhs == MMC_TIMING_MMC_HS400 || | |
1252 | uhs == MMC_TIMING_MMC_HS200 || | |
1253 | uhs == MMC_TIMING_UHS_SDR104) | |
1254 | ctrl_2 &= ~SDHCI_CTRL_UHS_MASK; | |
1255 | /* | |
1256 | * DLL is not required for clock <= 100MHz | |
1257 | * Thus, make sure DLL it is disabled when not required | |
1258 | */ | |
bc99266b SL |
1259 | config = readl_relaxed(host->ioaddr + |
1260 | msm_offset->core_dll_config); | |
ff06ce41 | 1261 | config |= CORE_DLL_RST; |
bc99266b SL |
1262 | writel_relaxed(config, host->ioaddr + |
1263 | msm_offset->core_dll_config); | |
ff06ce41 | 1264 | |
bc99266b SL |
1265 | config = readl_relaxed(host->ioaddr + |
1266 | msm_offset->core_dll_config); | |
ff06ce41 | 1267 | config |= CORE_DLL_PDN; |
bc99266b SL |
1268 | writel_relaxed(config, host->ioaddr + |
1269 | msm_offset->core_dll_config); | |
ff06ce41 VG |
1270 | |
1271 | /* | |
1272 | * The DLL needs to be restored and CDCLP533 recalibrated | |
1273 | * when the clock frequency is set back to 400MHz. | |
1274 | */ | |
1275 | msm_host->calibration_done = false; | |
1276 | } | |
ee320674 RH |
1277 | |
1278 | dev_dbg(mmc_dev(mmc), "%s: clock=%u uhs=%u ctrl_2=0x%x\n", | |
1279 | mmc_hostname(host->mmc), host->clock, uhs, ctrl_2); | |
1280 | sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); | |
cc392c58 | 1281 | |
db9bd163 RH |
1282 | if (mmc->ios.timing == MMC_TIMING_MMC_HS400) |
1283 | sdhci_msm_hs400(host, &mmc->ios); | |
ee320674 RH |
1284 | } |
1285 | ||
c0309b38 VV |
1286 | static inline void sdhci_msm_init_pwr_irq_wait(struct sdhci_msm_host *msm_host) |
1287 | { | |
1288 | init_waitqueue_head(&msm_host->pwr_irq_wait); | |
1289 | } | |
1290 | ||
1291 | static inline void sdhci_msm_complete_pwr_irq_wait( | |
1292 | struct sdhci_msm_host *msm_host) | |
1293 | { | |
1294 | wake_up(&msm_host->pwr_irq_wait); | |
1295 | } | |
1296 | ||
1297 | /* | |
1298 | * sdhci_msm_check_power_status API should be called when registers writes | |
1299 | * which can toggle sdhci IO bus ON/OFF or change IO lines HIGH/LOW happens. | |
1300 | * To what state the register writes will change the IO lines should be passed | |
1301 | * as the argument req_type. This API will check whether the IO line's state | |
1302 | * is already the expected state and will wait for power irq only if | |
1303 | * power irq is expected to be trigerred based on the current IO line state | |
1304 | * and expected IO line state. | |
1305 | */ | |
1306 | static void sdhci_msm_check_power_status(struct sdhci_host *host, u32 req_type) | |
1307 | { | |
1308 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
1309 | struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host); | |
1310 | bool done = false; | |
bc99266b SL |
1311 | u32 val = SWITCHABLE_SIGNALING_VOLTAGE; |
1312 | const struct sdhci_msm_offset *msm_offset = | |
1313 | msm_host->offset; | |
c0309b38 VV |
1314 | |
1315 | pr_debug("%s: %s: request %d curr_pwr_state %x curr_io_level %x\n", | |
1316 | mmc_hostname(host->mmc), __func__, req_type, | |
1317 | msm_host->curr_pwr_state, msm_host->curr_io_level); | |
1318 | ||
52884f8f BA |
1319 | /* |
1320 | * The power interrupt will not be generated for signal voltage | |
1321 | * switches if SWITCHABLE_SIGNALING_VOLTAGE in MCI_GENERICS is not set. | |
bc99266b SL |
1322 | * Since sdhci-msm-v5, this bit has been removed and SW must consider |
1323 | * it as always set. | |
52884f8f | 1324 | */ |
bc99266b SL |
1325 | if (!msm_host->mci_removed) |
1326 | val = msm_host_readl(msm_host, host, | |
1327 | msm_offset->core_generics); | |
52884f8f BA |
1328 | if ((req_type & REQ_IO_HIGH || req_type & REQ_IO_LOW) && |
1329 | !(val & SWITCHABLE_SIGNALING_VOLTAGE)) { | |
1330 | return; | |
1331 | } | |
1332 | ||
c0309b38 VV |
1333 | /* |
1334 | * The IRQ for request type IO High/LOW will be generated when - | |
1335 | * there is a state change in 1.8V enable bit (bit 3) of | |
1336 | * SDHCI_HOST_CONTROL2 register. The reset state of that bit is 0 | |
1337 | * which indicates 3.3V IO voltage. So, when MMC core layer tries | |
1338 | * to set it to 3.3V before card detection happens, the | |
1339 | * IRQ doesn't get triggered as there is no state change in this bit. | |
1340 | * The driver already handles this case by changing the IO voltage | |
1341 | * level to high as part of controller power up sequence. Hence, check | |
1342 | * for host->pwr to handle a case where IO voltage high request is | |
1343 | * issued even before controller power up. | |
1344 | */ | |
1345 | if ((req_type & REQ_IO_HIGH) && !host->pwr) { | |
1346 | pr_debug("%s: do not wait for power IRQ that never comes, req_type: %d\n", | |
1347 | mmc_hostname(host->mmc), req_type); | |
1348 | return; | |
1349 | } | |
1350 | if ((req_type & msm_host->curr_pwr_state) || | |
1351 | (req_type & msm_host->curr_io_level)) | |
1352 | done = true; | |
1353 | /* | |
1354 | * This is needed here to handle cases where register writes will | |
1355 | * not change the current bus state or io level of the controller. | |
1356 | * In this case, no power irq will be triggerred and we should | |
1357 | * not wait. | |
1358 | */ | |
1359 | if (!done) { | |
1360 | if (!wait_event_timeout(msm_host->pwr_irq_wait, | |
1361 | msm_host->pwr_irq_flag, | |
1362 | msecs_to_jiffies(MSM_PWR_IRQ_TIMEOUT_MS))) | |
9ccfa817 AB |
1363 | dev_warn(&msm_host->pdev->dev, |
1364 | "%s: pwr_irq for req: (%d) timed out\n", | |
1365 | mmc_hostname(host->mmc), req_type); | |
c0309b38 VV |
1366 | } |
1367 | pr_debug("%s: %s: request %d done\n", mmc_hostname(host->mmc), | |
1368 | __func__, req_type); | |
1369 | } | |
1370 | ||
401b2d06 ST |
1371 | static void sdhci_msm_dump_pwr_ctrl_regs(struct sdhci_host *host) |
1372 | { | |
1373 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
1374 | struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host); | |
bc99266b SL |
1375 | const struct sdhci_msm_offset *msm_offset = |
1376 | msm_host->offset; | |
401b2d06 ST |
1377 | |
1378 | pr_err("%s: PWRCTL_STATUS: 0x%08x | PWRCTL_MASK: 0x%08x | PWRCTL_CTL: 0x%08x\n", | |
bc99266b SL |
1379 | mmc_hostname(host->mmc), |
1380 | msm_host_readl(msm_host, host, msm_offset->core_pwrctl_status), | |
1381 | msm_host_readl(msm_host, host, msm_offset->core_pwrctl_mask), | |
1382 | msm_host_readl(msm_host, host, msm_offset->core_pwrctl_ctl)); | |
401b2d06 ST |
1383 | } |
1384 | ||
1385 | static void sdhci_msm_handle_pwr_irq(struct sdhci_host *host, int irq) | |
ad81d387 GD |
1386 | { |
1387 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
1388 | struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host); | |
1389 | u32 irq_status, irq_ack = 0; | |
401b2d06 | 1390 | int retry = 10; |
ac06fba1 | 1391 | u32 pwr_state = 0, io_level = 0; |
5c132323 | 1392 | u32 config; |
bc99266b | 1393 | const struct sdhci_msm_offset *msm_offset = msm_host->offset; |
ad81d387 | 1394 | |
bc99266b SL |
1395 | irq_status = msm_host_readl(msm_host, host, |
1396 | msm_offset->core_pwrctl_status); | |
ad81d387 GD |
1397 | irq_status &= INT_MASK; |
1398 | ||
bc99266b SL |
1399 | msm_host_writel(msm_host, irq_status, host, |
1400 | msm_offset->core_pwrctl_clear); | |
ad81d387 | 1401 | |
401b2d06 ST |
1402 | /* |
1403 | * There is a rare HW scenario where the first clear pulse could be | |
1404 | * lost when actual reset and clear/read of status register is | |
1405 | * happening at a time. Hence, retry for at least 10 times to make | |
1406 | * sure status register is cleared. Otherwise, this will result in | |
1407 | * a spurious power IRQ resulting in system instability. | |
1408 | */ | |
bc99266b SL |
1409 | while (irq_status & msm_host_readl(msm_host, host, |
1410 | msm_offset->core_pwrctl_status)) { | |
401b2d06 ST |
1411 | if (retry == 0) { |
1412 | pr_err("%s: Timedout clearing (0x%x) pwrctl status register\n", | |
1413 | mmc_hostname(host->mmc), irq_status); | |
1414 | sdhci_msm_dump_pwr_ctrl_regs(host); | |
1415 | WARN_ON(1); | |
1416 | break; | |
1417 | } | |
bc99266b SL |
1418 | msm_host_writel(msm_host, irq_status, host, |
1419 | msm_offset->core_pwrctl_clear); | |
401b2d06 ST |
1420 | retry--; |
1421 | udelay(10); | |
1422 | } | |
1423 | ||
c0309b38 VV |
1424 | /* Handle BUS ON/OFF*/ |
1425 | if (irq_status & CORE_PWRCTL_BUS_ON) { | |
1426 | pwr_state = REQ_BUS_ON; | |
1427 | io_level = REQ_IO_HIGH; | |
1428 | irq_ack |= CORE_PWRCTL_BUS_SUCCESS; | |
1429 | } | |
1430 | if (irq_status & CORE_PWRCTL_BUS_OFF) { | |
1431 | pwr_state = REQ_BUS_OFF; | |
1432 | io_level = REQ_IO_LOW; | |
ad81d387 | 1433 | irq_ack |= CORE_PWRCTL_BUS_SUCCESS; |
c0309b38 VV |
1434 | } |
1435 | /* Handle IO LOW/HIGH */ | |
1436 | if (irq_status & CORE_PWRCTL_IO_LOW) { | |
1437 | io_level = REQ_IO_LOW; | |
ad81d387 | 1438 | irq_ack |= CORE_PWRCTL_IO_SUCCESS; |
c0309b38 VV |
1439 | } |
1440 | if (irq_status & CORE_PWRCTL_IO_HIGH) { | |
1441 | io_level = REQ_IO_HIGH; | |
1442 | irq_ack |= CORE_PWRCTL_IO_SUCCESS; | |
1443 | } | |
ad81d387 GD |
1444 | |
1445 | /* | |
1446 | * The driver has to acknowledge the interrupt, switch voltages and | |
1447 | * report back if it succeded or not to this register. The voltage | |
1448 | * switches are handled by the sdhci core, so just report success. | |
1449 | */ | |
bc99266b SL |
1450 | msm_host_writel(msm_host, irq_ack, host, |
1451 | msm_offset->core_pwrctl_ctl); | |
401b2d06 | 1452 | |
5c132323 VV |
1453 | /* |
1454 | * If we don't have info regarding the voltage levels supported by | |
1455 | * regulators, don't change the IO PAD PWR SWITCH. | |
1456 | */ | |
1457 | if (msm_host->caps_0 & CORE_VOLT_SUPPORT) { | |
1458 | u32 new_config; | |
1459 | /* | |
1460 | * We should unset IO PAD PWR switch only if the register write | |
1461 | * can set IO lines high and the regulator also switches to 3 V. | |
1462 | * Else, we should keep the IO PAD PWR switch set. | |
1463 | * This is applicable to certain targets where eMMC vccq supply | |
1464 | * is only 1.8V. In such targets, even during REQ_IO_HIGH, the | |
1465 | * IO PAD PWR switch must be kept set to reflect actual | |
1466 | * regulator voltage. This way, during initialization of | |
1467 | * controllers with only 1.8V, we will set the IO PAD bit | |
1468 | * without waiting for a REQ_IO_LOW. | |
1469 | */ | |
bc99266b SL |
1470 | config = readl_relaxed(host->ioaddr + |
1471 | msm_offset->core_vendor_spec); | |
5c132323 VV |
1472 | new_config = config; |
1473 | ||
1474 | if ((io_level & REQ_IO_HIGH) && | |
1475 | (msm_host->caps_0 & CORE_3_0V_SUPPORT)) | |
1476 | new_config &= ~CORE_IO_PAD_PWR_SWITCH; | |
1477 | else if ((io_level & REQ_IO_LOW) || | |
1478 | (msm_host->caps_0 & CORE_1_8V_SUPPORT)) | |
1479 | new_config |= CORE_IO_PAD_PWR_SWITCH; | |
1480 | ||
1481 | if (config ^ new_config) | |
bc99266b SL |
1482 | writel_relaxed(new_config, host->ioaddr + |
1483 | msm_offset->core_vendor_spec); | |
5c132323 VV |
1484 | } |
1485 | ||
c0309b38 VV |
1486 | if (pwr_state) |
1487 | msm_host->curr_pwr_state = pwr_state; | |
1488 | if (io_level) | |
1489 | msm_host->curr_io_level = io_level; | |
1490 | ||
401b2d06 ST |
1491 | pr_debug("%s: %s: Handled IRQ(%d), irq_status=0x%x, ack=0x%x\n", |
1492 | mmc_hostname(msm_host->mmc), __func__, irq, irq_status, | |
1493 | irq_ack); | |
ad81d387 GD |
1494 | } |
1495 | ||
1496 | static irqreturn_t sdhci_msm_pwr_irq(int irq, void *data) | |
1497 | { | |
1498 | struct sdhci_host *host = (struct sdhci_host *)data; | |
c0309b38 VV |
1499 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
1500 | struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host); | |
ad81d387 | 1501 | |
401b2d06 | 1502 | sdhci_msm_handle_pwr_irq(host, irq); |
c0309b38 VV |
1503 | msm_host->pwr_irq_flag = 1; |
1504 | sdhci_msm_complete_pwr_irq_wait(msm_host); | |
1505 | ||
ad81d387 GD |
1506 | |
1507 | return IRQ_HANDLED; | |
1508 | } | |
1509 | ||
80031bde RH |
1510 | static unsigned int sdhci_msm_get_max_clock(struct sdhci_host *host) |
1511 | { | |
1512 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
1513 | struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host); | |
e4bf91f6 | 1514 | struct clk *core_clk = msm_host->bulk_clks[0].clk; |
80031bde | 1515 | |
e4bf91f6 | 1516 | return clk_round_rate(core_clk, ULONG_MAX); |
80031bde RH |
1517 | } |
1518 | ||
1519 | static unsigned int sdhci_msm_get_min_clock(struct sdhci_host *host) | |
1520 | { | |
1521 | return SDHCI_MSM_MIN_CLOCK; | |
1522 | } | |
1523 | ||
edc609fd RH |
1524 | /** |
1525 | * __sdhci_msm_set_clock - sdhci_msm clock control. | |
1526 | * | |
1527 | * Description: | |
1528 | * MSM controller does not use internal divider and | |
1529 | * instead directly control the GCC clock as per | |
1530 | * HW recommendation. | |
1531 | **/ | |
30de038d | 1532 | static void __sdhci_msm_set_clock(struct sdhci_host *host, unsigned int clock) |
edc609fd RH |
1533 | { |
1534 | u16 clk; | |
1535 | /* | |
1536 | * Keep actual_clock as zero - | |
1537 | * - since there is no divider used so no need of having actual_clock. | |
1538 | * - MSM controller uses SDCLK for data timeout calculation. If | |
1539 | * actual_clock is zero, host->clock is taken for calculation. | |
1540 | */ | |
1541 | host->mmc->actual_clock = 0; | |
1542 | ||
1543 | sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL); | |
1544 | ||
1545 | if (clock == 0) | |
1546 | return; | |
1547 | ||
1548 | /* | |
1549 | * MSM controller do not use clock divider. | |
1550 | * Thus read SDHCI_CLOCK_CONTROL and only enable | |
1551 | * clock with no divider value programmed. | |
1552 | */ | |
1553 | clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); | |
1554 | sdhci_enable_clk(host, clk); | |
1555 | } | |
1556 | ||
1557 | /* sdhci_msm_set_clock - Called with (host->lock) spinlock held. */ | |
1558 | static void sdhci_msm_set_clock(struct sdhci_host *host, unsigned int clock) | |
1559 | { | |
1560 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
1561 | struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host); | |
edc609fd RH |
1562 | |
1563 | if (!clock) { | |
1564 | msm_host->clk_rate = clock; | |
1565 | goto out; | |
1566 | } | |
1567 | ||
b54aaa8a | 1568 | sdhci_msm_hc_select_mode(host); |
edc609fd | 1569 | |
0fb8a3d4 | 1570 | msm_set_clock_rate_for_bus_mode(host, clock); |
edc609fd RH |
1571 | out: |
1572 | __sdhci_msm_set_clock(host, clock); | |
1573 | } | |
1574 | ||
87a8df0d RH |
1575 | /*****************************************************************************\ |
1576 | * * | |
1577 | * MSM Command Queue Engine (CQE) * | |
1578 | * * | |
1579 | \*****************************************************************************/ | |
1580 | ||
1581 | static u32 sdhci_msm_cqe_irq(struct sdhci_host *host, u32 intmask) | |
1582 | { | |
1583 | int cmd_error = 0; | |
1584 | int data_error = 0; | |
1585 | ||
1586 | if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error)) | |
1587 | return intmask; | |
1588 | ||
1589 | cqhci_irq(host->mmc, intmask, cmd_error, data_error); | |
1590 | return 0; | |
1591 | } | |
1592 | ||
9051db38 | 1593 | static void sdhci_msm_cqe_disable(struct mmc_host *mmc, bool recovery) |
87a8df0d RH |
1594 | { |
1595 | struct sdhci_host *host = mmc_priv(mmc); | |
1596 | unsigned long flags; | |
1597 | u32 ctrl; | |
1598 | ||
1599 | /* | |
1600 | * When CQE is halted, the legacy SDHCI path operates only | |
1601 | * on 16-byte descriptors in 64bit mode. | |
1602 | */ | |
1603 | if (host->flags & SDHCI_USE_64_BIT_DMA) | |
1604 | host->desc_sz = 16; | |
1605 | ||
1606 | spin_lock_irqsave(&host->lock, flags); | |
1607 | ||
1608 | /* | |
1609 | * During CQE command transfers, command complete bit gets latched. | |
1610 | * So s/w should clear command complete interrupt status when CQE is | |
1611 | * either halted or disabled. Otherwise unexpected SDCHI legacy | |
1612 | * interrupt gets triggered when CQE is halted/disabled. | |
1613 | */ | |
1614 | ctrl = sdhci_readl(host, SDHCI_INT_ENABLE); | |
1615 | ctrl |= SDHCI_INT_RESPONSE; | |
1616 | sdhci_writel(host, ctrl, SDHCI_INT_ENABLE); | |
1617 | sdhci_writel(host, SDHCI_INT_RESPONSE, SDHCI_INT_STATUS); | |
1618 | ||
1619 | spin_unlock_irqrestore(&host->lock, flags); | |
1620 | ||
1621 | sdhci_cqe_disable(mmc, recovery); | |
1622 | } | |
1623 | ||
1624 | static const struct cqhci_host_ops sdhci_msm_cqhci_ops = { | |
1625 | .enable = sdhci_cqe_enable, | |
1626 | .disable = sdhci_msm_cqe_disable, | |
1627 | }; | |
1628 | ||
1629 | static int sdhci_msm_cqe_add_host(struct sdhci_host *host, | |
1630 | struct platform_device *pdev) | |
1631 | { | |
1632 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
1633 | struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host); | |
1634 | struct cqhci_host *cq_host; | |
1635 | bool dma64; | |
1636 | u32 cqcfg; | |
1637 | int ret; | |
1638 | ||
1639 | /* | |
1640 | * When CQE is halted, SDHC operates only on 16byte ADMA descriptors. | |
1641 | * So ensure ADMA table is allocated for 16byte descriptors. | |
1642 | */ | |
1643 | if (host->caps & SDHCI_CAN_64BIT) | |
1644 | host->alloc_desc_sz = 16; | |
1645 | ||
1646 | ret = sdhci_setup_host(host); | |
1647 | if (ret) | |
1648 | return ret; | |
1649 | ||
1650 | cq_host = cqhci_pltfm_init(pdev); | |
1651 | if (IS_ERR(cq_host)) { | |
1652 | ret = PTR_ERR(cq_host); | |
1653 | dev_err(&pdev->dev, "cqhci-pltfm init: failed: %d\n", ret); | |
1654 | goto cleanup; | |
1655 | } | |
1656 | ||
1657 | msm_host->mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD; | |
1658 | cq_host->ops = &sdhci_msm_cqhci_ops; | |
1659 | ||
1660 | dma64 = host->flags & SDHCI_USE_64_BIT_DMA; | |
1661 | ||
1662 | ret = cqhci_init(cq_host, host->mmc, dma64); | |
1663 | if (ret) { | |
1664 | dev_err(&pdev->dev, "%s: CQE init: failed (%d)\n", | |
1665 | mmc_hostname(host->mmc), ret); | |
1666 | goto cleanup; | |
1667 | } | |
1668 | ||
1669 | /* Disable cqe reset due to cqe enable signal */ | |
1670 | cqcfg = cqhci_readl(cq_host, CQHCI_VENDOR_CFG1); | |
1671 | cqcfg |= CQHCI_VENDOR_DIS_RST_ON_CQ_EN; | |
1672 | cqhci_writel(cq_host, cqcfg, CQHCI_VENDOR_CFG1); | |
1673 | ||
1674 | /* | |
1675 | * SDHC expects 12byte ADMA descriptors till CQE is enabled. | |
1676 | * So limit desc_sz to 12 so that the data commands that are sent | |
1677 | * during card initialization (before CQE gets enabled) would | |
1678 | * get executed without any issues. | |
1679 | */ | |
1680 | if (host->flags & SDHCI_USE_64_BIT_DMA) | |
1681 | host->desc_sz = 12; | |
1682 | ||
1683 | ret = __sdhci_add_host(host); | |
1684 | if (ret) | |
1685 | goto cleanup; | |
1686 | ||
1687 | dev_info(&pdev->dev, "%s: CQE init: success\n", | |
1688 | mmc_hostname(host->mmc)); | |
1689 | return ret; | |
1690 | ||
1691 | cleanup: | |
1692 | sdhci_cleanup_host(host); | |
1693 | return ret; | |
1694 | } | |
1695 | ||
c0309b38 VV |
1696 | /* |
1697 | * Platform specific register write functions. This is so that, if any | |
1698 | * register write needs to be followed up by platform specific actions, | |
1699 | * they can be added here. These functions can go to sleep when writes | |
1700 | * to certain registers are done. | |
1701 | * These functions are relying on sdhci_set_ios not using spinlock. | |
1702 | */ | |
1703 | static int __sdhci_msm_check_write(struct sdhci_host *host, u16 val, int reg) | |
1704 | { | |
1705 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
1706 | struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host); | |
1707 | u32 req_type = 0; | |
1708 | ||
1709 | switch (reg) { | |
1710 | case SDHCI_HOST_CONTROL2: | |
1711 | req_type = (val & SDHCI_CTRL_VDD_180) ? REQ_IO_LOW : | |
1712 | REQ_IO_HIGH; | |
1713 | break; | |
1714 | case SDHCI_SOFTWARE_RESET: | |
1715 | if (host->pwr && (val & SDHCI_RESET_ALL)) | |
1716 | req_type = REQ_BUS_OFF; | |
1717 | break; | |
1718 | case SDHCI_POWER_CONTROL: | |
1719 | req_type = !val ? REQ_BUS_OFF : REQ_BUS_ON; | |
1720 | break; | |
a89e7bcb LP |
1721 | case SDHCI_TRANSFER_MODE: |
1722 | msm_host->transfer_mode = val; | |
1723 | break; | |
1724 | case SDHCI_COMMAND: | |
1725 | if (!msm_host->use_cdr) | |
1726 | break; | |
1727 | if ((msm_host->transfer_mode & SDHCI_TRNS_READ) && | |
1728 | SDHCI_GET_CMD(val) != MMC_SEND_TUNING_BLOCK_HS200 && | |
1729 | SDHCI_GET_CMD(val) != MMC_SEND_TUNING_BLOCK) | |
1730 | sdhci_msm_set_cdr(host, true); | |
1731 | else | |
1732 | sdhci_msm_set_cdr(host, false); | |
1733 | break; | |
c0309b38 VV |
1734 | } |
1735 | ||
1736 | if (req_type) { | |
1737 | msm_host->pwr_irq_flag = 0; | |
1738 | /* | |
1739 | * Since this register write may trigger a power irq, ensure | |
1740 | * all previous register writes are complete by this point. | |
1741 | */ | |
1742 | mb(); | |
1743 | } | |
1744 | return req_type; | |
1745 | } | |
1746 | ||
1747 | /* This function may sleep*/ | |
1748 | static void sdhci_msm_writew(struct sdhci_host *host, u16 val, int reg) | |
1749 | { | |
1750 | u32 req_type = 0; | |
1751 | ||
1752 | req_type = __sdhci_msm_check_write(host, val, reg); | |
1753 | writew_relaxed(val, host->ioaddr + reg); | |
1754 | ||
1755 | if (req_type) | |
1756 | sdhci_msm_check_power_status(host, req_type); | |
1757 | } | |
1758 | ||
1759 | /* This function may sleep*/ | |
1760 | static void sdhci_msm_writeb(struct sdhci_host *host, u8 val, int reg) | |
1761 | { | |
1762 | u32 req_type = 0; | |
1763 | ||
1764 | req_type = __sdhci_msm_check_write(host, val, reg); | |
1765 | ||
1766 | writeb_relaxed(val, host->ioaddr + reg); | |
1767 | ||
1768 | if (req_type) | |
1769 | sdhci_msm_check_power_status(host, req_type); | |
1770 | } | |
1771 | ||
ac06fba1 VV |
1772 | static void sdhci_msm_set_regulator_caps(struct sdhci_msm_host *msm_host) |
1773 | { | |
1774 | struct mmc_host *mmc = msm_host->mmc; | |
1775 | struct regulator *supply = mmc->supply.vqmmc; | |
5c132323 VV |
1776 | u32 caps = 0, config; |
1777 | struct sdhci_host *host = mmc_priv(mmc); | |
bc99266b | 1778 | const struct sdhci_msm_offset *msm_offset = msm_host->offset; |
ac06fba1 VV |
1779 | |
1780 | if (!IS_ERR(mmc->supply.vqmmc)) { | |
1781 | if (regulator_is_supported_voltage(supply, 1700000, 1950000)) | |
1782 | caps |= CORE_1_8V_SUPPORT; | |
1783 | if (regulator_is_supported_voltage(supply, 2700000, 3600000)) | |
1784 | caps |= CORE_3_0V_SUPPORT; | |
1785 | ||
1786 | if (!caps) | |
1787 | pr_warn("%s: 1.8/3V not supported for vqmmc\n", | |
1788 | mmc_hostname(mmc)); | |
1789 | } | |
1790 | ||
5c132323 VV |
1791 | if (caps) { |
1792 | /* | |
1793 | * Set the PAD_PWR_SWITCH_EN bit so that the PAD_PWR_SWITCH | |
1794 | * bit can be used as required later on. | |
1795 | */ | |
1796 | u32 io_level = msm_host->curr_io_level; | |
1797 | ||
bc99266b SL |
1798 | config = readl_relaxed(host->ioaddr + |
1799 | msm_offset->core_vendor_spec); | |
5c132323 VV |
1800 | config |= CORE_IO_PAD_PWR_SWITCH_EN; |
1801 | ||
1802 | if ((io_level & REQ_IO_HIGH) && (caps & CORE_3_0V_SUPPORT)) | |
1803 | config &= ~CORE_IO_PAD_PWR_SWITCH; | |
1804 | else if ((io_level & REQ_IO_LOW) || (caps & CORE_1_8V_SUPPORT)) | |
1805 | config |= CORE_IO_PAD_PWR_SWITCH; | |
1806 | ||
bc99266b SL |
1807 | writel_relaxed(config, |
1808 | host->ioaddr + msm_offset->core_vendor_spec); | |
5c132323 | 1809 | } |
ac06fba1 VV |
1810 | msm_host->caps_0 |= caps; |
1811 | pr_debug("%s: supported caps: 0x%08x\n", mmc_hostname(mmc), caps); | |
1812 | } | |
1813 | ||
6ed4bb43 VV |
1814 | static const struct sdhci_msm_variant_ops mci_var_ops = { |
1815 | .msm_readl_relaxed = sdhci_msm_mci_variant_readl_relaxed, | |
1816 | .msm_writel_relaxed = sdhci_msm_mci_variant_writel_relaxed, | |
1817 | }; | |
1818 | ||
1819 | static const struct sdhci_msm_variant_ops v5_var_ops = { | |
1820 | .msm_readl_relaxed = sdhci_msm_v5_variant_readl_relaxed, | |
1821 | .msm_writel_relaxed = sdhci_msm_v5_variant_writel_relaxed, | |
1822 | }; | |
1823 | ||
1824 | static const struct sdhci_msm_variant_info sdhci_msm_mci_var = { | |
6ed4bb43 VV |
1825 | .var_ops = &mci_var_ops, |
1826 | .offset = &sdhci_msm_mci_offset, | |
1827 | }; | |
1828 | ||
1829 | static const struct sdhci_msm_variant_info sdhci_msm_v5_var = { | |
1830 | .mci_removed = true, | |
1831 | .var_ops = &v5_var_ops, | |
1832 | .offset = &sdhci_msm_v5_offset, | |
1833 | }; | |
1834 | ||
21f1e2d4 VB |
1835 | static const struct sdhci_msm_variant_info sdm845_sdhci_var = { |
1836 | .mci_removed = true, | |
1837 | .restore_dll_config = true, | |
1838 | .var_ops = &v5_var_ops, | |
1839 | .offset = &sdhci_msm_v5_offset, | |
1840 | }; | |
1841 | ||
0eb0d9f4 | 1842 | static const struct of_device_id sdhci_msm_dt_match[] = { |
bc99266b SL |
1843 | {.compatible = "qcom,sdhci-msm-v4", .data = &sdhci_msm_mci_var}, |
1844 | {.compatible = "qcom,sdhci-msm-v5", .data = &sdhci_msm_v5_var}, | |
21f1e2d4 | 1845 | {.compatible = "qcom,sdm845-sdhci", .data = &sdm845_sdhci_var}, |
0eb0d9f4 GD |
1846 | {}, |
1847 | }; | |
1848 | ||
1849 | MODULE_DEVICE_TABLE(of, sdhci_msm_dt_match); | |
1850 | ||
a50396a4 | 1851 | static const struct sdhci_ops sdhci_msm_ops = { |
ed1761d7 | 1852 | .reset = sdhci_reset, |
edc609fd | 1853 | .set_clock = sdhci_msm_set_clock, |
80031bde RH |
1854 | .get_min_clock = sdhci_msm_get_min_clock, |
1855 | .get_max_clock = sdhci_msm_get_max_clock, | |
ed1761d7 | 1856 | .set_bus_width = sdhci_set_bus_width, |
ee320674 | 1857 | .set_uhs_signaling = sdhci_msm_set_uhs_signaling, |
c0309b38 VV |
1858 | .write_w = sdhci_msm_writew, |
1859 | .write_b = sdhci_msm_writeb, | |
87a8df0d | 1860 | .irq = sdhci_msm_cqe_irq, |
0eb0d9f4 GD |
1861 | }; |
1862 | ||
a50396a4 JZ |
1863 | static const struct sdhci_pltfm_data sdhci_msm_pdata = { |
1864 | .quirks = SDHCI_QUIRK_BROKEN_CARD_DETECTION | | |
a0e31428 RH |
1865 | SDHCI_QUIRK_SINGLE_POWER_WRITE | |
1866 | SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, | |
1867 | .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, | |
a50396a4 JZ |
1868 | .ops = &sdhci_msm_ops, |
1869 | }; | |
1870 | ||
0eb0d9f4 GD |
1871 | static int sdhci_msm_probe(struct platform_device *pdev) |
1872 | { | |
1873 | struct sdhci_host *host; | |
1874 | struct sdhci_pltfm_host *pltfm_host; | |
1875 | struct sdhci_msm_host *msm_host; | |
e4bf91f6 | 1876 | struct clk *clk; |
0eb0d9f4 | 1877 | int ret; |
3a3ad3e9 | 1878 | u16 host_version, core_minor; |
29301f40 | 1879 | u32 core_version, config; |
3a3ad3e9 | 1880 | u8 core_major; |
bc99266b SL |
1881 | const struct sdhci_msm_offset *msm_offset; |
1882 | const struct sdhci_msm_variant_info *var_info; | |
87a8df0d | 1883 | struct device_node *node = pdev->dev.of_node; |
0eb0d9f4 | 1884 | |
6f699531 | 1885 | host = sdhci_pltfm_init(pdev, &sdhci_msm_pdata, sizeof(*msm_host)); |
0eb0d9f4 GD |
1886 | if (IS_ERR(host)) |
1887 | return PTR_ERR(host); | |
1888 | ||
2a641e53 | 1889 | host->sdma_boundary = 0; |
0eb0d9f4 | 1890 | pltfm_host = sdhci_priv(host); |
6f699531 | 1891 | msm_host = sdhci_pltfm_priv(pltfm_host); |
0eb0d9f4 GD |
1892 | msm_host->mmc = host->mmc; |
1893 | msm_host->pdev = pdev; | |
1894 | ||
1895 | ret = mmc_of_parse(host->mmc); | |
1896 | if (ret) | |
1897 | goto pltfm_free; | |
1898 | ||
bc99266b SL |
1899 | /* |
1900 | * Based on the compatible string, load the required msm host info from | |
1901 | * the data associated with the version info. | |
1902 | */ | |
1903 | var_info = of_device_get_match_data(&pdev->dev); | |
1904 | ||
1905 | msm_host->mci_removed = var_info->mci_removed; | |
21f1e2d4 | 1906 | msm_host->restore_dll_config = var_info->restore_dll_config; |
bc99266b SL |
1907 | msm_host->var_ops = var_info->var_ops; |
1908 | msm_host->offset = var_info->offset; | |
1909 | ||
1910 | msm_offset = msm_host->offset; | |
1911 | ||
0eb0d9f4 GD |
1912 | sdhci_get_of_property(pdev); |
1913 | ||
abf270e5 RH |
1914 | msm_host->saved_tuning_phase = INVALID_TUNING_PHASE; |
1915 | ||
0eb0d9f4 GD |
1916 | /* Setup SDCC bus voter clock. */ |
1917 | msm_host->bus_clk = devm_clk_get(&pdev->dev, "bus"); | |
1918 | if (!IS_ERR(msm_host->bus_clk)) { | |
1919 | /* Vote for max. clk rate for max. performance */ | |
1920 | ret = clk_set_rate(msm_host->bus_clk, INT_MAX); | |
1921 | if (ret) | |
1922 | goto pltfm_free; | |
1923 | ret = clk_prepare_enable(msm_host->bus_clk); | |
1924 | if (ret) | |
1925 | goto pltfm_free; | |
1926 | } | |
1927 | ||
1928 | /* Setup main peripheral bus clock */ | |
e4bf91f6 BA |
1929 | clk = devm_clk_get(&pdev->dev, "iface"); |
1930 | if (IS_ERR(clk)) { | |
1931 | ret = PTR_ERR(clk); | |
2801b95e | 1932 | dev_err(&pdev->dev, "Peripheral clk setup failed (%d)\n", ret); |
0eb0d9f4 GD |
1933 | goto bus_clk_disable; |
1934 | } | |
e4bf91f6 | 1935 | msm_host->bulk_clks[1].clk = clk; |
0eb0d9f4 GD |
1936 | |
1937 | /* Setup SDC MMC clock */ | |
e4bf91f6 BA |
1938 | clk = devm_clk_get(&pdev->dev, "core"); |
1939 | if (IS_ERR(clk)) { | |
1940 | ret = PTR_ERR(clk); | |
0eb0d9f4 | 1941 | dev_err(&pdev->dev, "SDC MMC clk setup failed (%d)\n", ret); |
e4bf91f6 | 1942 | goto bus_clk_disable; |
0eb0d9f4 | 1943 | } |
e4bf91f6 BA |
1944 | msm_host->bulk_clks[0].clk = clk; |
1945 | ||
1946 | /* Vote for maximum clock rate for maximum performance */ | |
1947 | ret = clk_set_rate(clk, INT_MAX); | |
1948 | if (ret) | |
1949 | dev_warn(&pdev->dev, "core clock boost failed\n"); | |
1950 | ||
4946b3af BA |
1951 | clk = devm_clk_get(&pdev->dev, "cal"); |
1952 | if (IS_ERR(clk)) | |
1953 | clk = NULL; | |
1954 | msm_host->bulk_clks[2].clk = clk; | |
1955 | ||
1956 | clk = devm_clk_get(&pdev->dev, "sleep"); | |
1957 | if (IS_ERR(clk)) | |
1958 | clk = NULL; | |
1959 | msm_host->bulk_clks[3].clk = clk; | |
1960 | ||
e4bf91f6 BA |
1961 | ret = clk_bulk_prepare_enable(ARRAY_SIZE(msm_host->bulk_clks), |
1962 | msm_host->bulk_clks); | |
1963 | if (ret) | |
1964 | goto bus_clk_disable; | |
0eb0d9f4 | 1965 | |
83736352 VG |
1966 | /* |
1967 | * xo clock is needed for FLL feature of cm_dll. | |
1968 | * In case if xo clock is not mentioned in DT, warn and proceed. | |
1969 | */ | |
1970 | msm_host->xo_clk = devm_clk_get(&pdev->dev, "xo"); | |
1971 | if (IS_ERR(msm_host->xo_clk)) { | |
1972 | ret = PTR_ERR(msm_host->xo_clk); | |
1973 | dev_warn(&pdev->dev, "TCXO clk not present (%d)\n", ret); | |
1974 | } | |
1975 | ||
bc99266b | 1976 | if (!msm_host->mci_removed) { |
cb064b50 | 1977 | msm_host->core_mem = devm_platform_ioremap_resource(pdev, 1); |
bc99266b | 1978 | if (IS_ERR(msm_host->core_mem)) { |
bc99266b SL |
1979 | ret = PTR_ERR(msm_host->core_mem); |
1980 | goto clk_disable; | |
1981 | } | |
0eb0d9f4 GD |
1982 | } |
1983 | ||
5574ddcc VG |
1984 | /* Reset the vendor spec register to power on reset state */ |
1985 | writel_relaxed(CORE_VENDOR_SPEC_POR_VAL, | |
bc99266b SL |
1986 | host->ioaddr + msm_offset->core_vendor_spec); |
1987 | ||
1988 | if (!msm_host->mci_removed) { | |
1989 | /* Set HC_MODE_EN bit in HC_MODE register */ | |
1990 | msm_host_writel(msm_host, HC_MODE_EN, host, | |
1991 | msm_offset->core_hc_mode); | |
1992 | config = msm_host_readl(msm_host, host, | |
1993 | msm_offset->core_hc_mode); | |
1994 | config |= FF_CLK_SW_RST_DIS; | |
1995 | msm_host_writel(msm_host, config, host, | |
1996 | msm_offset->core_hc_mode); | |
1997 | } | |
ff06ce41 | 1998 | |
0eb0d9f4 GD |
1999 | host_version = readw_relaxed((host->ioaddr + SDHCI_HOST_VERSION)); |
2000 | dev_dbg(&pdev->dev, "Host Version: 0x%x Vendor Version 0x%x\n", | |
2001 | host_version, ((host_version & SDHCI_VENDOR_VER_MASK) >> | |
2002 | SDHCI_VENDOR_VER_SHIFT)); | |
2003 | ||
bc99266b SL |
2004 | core_version = msm_host_readl(msm_host, host, |
2005 | msm_offset->core_mci_version); | |
3a3ad3e9 GD |
2006 | core_major = (core_version & CORE_VERSION_MAJOR_MASK) >> |
2007 | CORE_VERSION_MAJOR_SHIFT; | |
2008 | core_minor = core_version & CORE_VERSION_MINOR_MASK; | |
2009 | dev_dbg(&pdev->dev, "MCI Version: 0x%08x, major: 0x%04x, minor: 0x%02x\n", | |
2010 | core_version, core_major, core_minor); | |
2011 | ||
83736352 VG |
2012 | if (core_major == 1 && core_minor >= 0x42) |
2013 | msm_host->use_14lpp_dll_reset = true; | |
2014 | ||
02e4293d RH |
2015 | /* |
2016 | * SDCC 5 controller with major version 1, minor version 0x34 and later | |
2017 | * with HS 400 mode support will use CM DLL instead of CDC LP 533 DLL. | |
2018 | */ | |
2019 | if (core_major == 1 && core_minor < 0x34) | |
2020 | msm_host->use_cdclp533 = true; | |
2021 | ||
3a3ad3e9 GD |
2022 | /* |
2023 | * Support for some capabilities is not advertised by newer | |
2024 | * controller versions and must be explicitly enabled. | |
2025 | */ | |
2026 | if (core_major >= 1 && core_minor != 0x11 && core_minor != 0x12) { | |
29301f40 RH |
2027 | config = readl_relaxed(host->ioaddr + SDHCI_CAPABILITIES); |
2028 | config |= SDHCI_CAN_VDD_300 | SDHCI_CAN_DO_8BIT; | |
2029 | writel_relaxed(config, host->ioaddr + | |
bc99266b | 2030 | msm_offset->core_vendor_spec_capabilities0); |
3a3ad3e9 GD |
2031 | } |
2032 | ||
fa56ac97 VB |
2033 | if (core_major == 1 && core_minor >= 0x49) |
2034 | msm_host->updated_ddr_cfg = true; | |
2035 | ||
c7ccee22 SJ |
2036 | /* |
2037 | * Power on reset state may trigger power irq if previous status of | |
2038 | * PWRCTL was either BUS_ON or IO_HIGH_V. So before enabling pwr irq | |
2039 | * interrupt in GIC, any pending power irq interrupt should be | |
2040 | * acknowledged. Otherwise power irq interrupt handler would be | |
2041 | * fired prematurely. | |
2042 | */ | |
401b2d06 | 2043 | sdhci_msm_handle_pwr_irq(host, 0); |
c7ccee22 SJ |
2044 | |
2045 | /* | |
2046 | * Ensure that above writes are propogated before interrupt enablement | |
2047 | * in GIC. | |
2048 | */ | |
2049 | mb(); | |
2050 | ||
ad81d387 GD |
2051 | /* Setup IRQ for handling power/voltage tasks with PMIC */ |
2052 | msm_host->pwr_irq = platform_get_irq_byname(pdev, "pwr_irq"); | |
2053 | if (msm_host->pwr_irq < 0) { | |
d1f63f0c | 2054 | ret = msm_host->pwr_irq; |
ad81d387 GD |
2055 | goto clk_disable; |
2056 | } | |
2057 | ||
c0309b38 | 2058 | sdhci_msm_init_pwr_irq_wait(msm_host); |
c7ccee22 | 2059 | /* Enable pwr irq interrupts */ |
bc99266b SL |
2060 | msm_host_writel(msm_host, INT_MASK, host, |
2061 | msm_offset->core_pwrctl_mask); | |
c7ccee22 | 2062 | |
ad81d387 GD |
2063 | ret = devm_request_threaded_irq(&pdev->dev, msm_host->pwr_irq, NULL, |
2064 | sdhci_msm_pwr_irq, IRQF_ONESHOT, | |
2065 | dev_name(&pdev->dev), host); | |
2066 | if (ret) { | |
2067 | dev_err(&pdev->dev, "Request IRQ failed (%d)\n", ret); | |
2068 | goto clk_disable; | |
2069 | } | |
2070 | ||
67e6db11 PG |
2071 | pm_runtime_get_noresume(&pdev->dev); |
2072 | pm_runtime_set_active(&pdev->dev); | |
2073 | pm_runtime_enable(&pdev->dev); | |
2074 | pm_runtime_set_autosuspend_delay(&pdev->dev, | |
2075 | MSM_MMC_AUTOSUSPEND_DELAY_MS); | |
2076 | pm_runtime_use_autosuspend(&pdev->dev); | |
2077 | ||
4436c535 | 2078 | host->mmc_host_ops.execute_tuning = sdhci_msm_execute_tuning; |
87a8df0d RH |
2079 | if (of_property_read_bool(node, "supports-cqe")) |
2080 | ret = sdhci_msm_cqe_add_host(host, pdev); | |
2081 | else | |
2082 | ret = sdhci_add_host(host); | |
0eb0d9f4 | 2083 | if (ret) |
67e6db11 | 2084 | goto pm_runtime_disable; |
ac06fba1 | 2085 | sdhci_msm_set_regulator_caps(msm_host); |
67e6db11 PG |
2086 | |
2087 | pm_runtime_mark_last_busy(&pdev->dev); | |
2088 | pm_runtime_put_autosuspend(&pdev->dev); | |
0eb0d9f4 GD |
2089 | |
2090 | return 0; | |
2091 | ||
67e6db11 PG |
2092 | pm_runtime_disable: |
2093 | pm_runtime_disable(&pdev->dev); | |
2094 | pm_runtime_set_suspended(&pdev->dev); | |
2095 | pm_runtime_put_noidle(&pdev->dev); | |
0eb0d9f4 | 2096 | clk_disable: |
e4bf91f6 BA |
2097 | clk_bulk_disable_unprepare(ARRAY_SIZE(msm_host->bulk_clks), |
2098 | msm_host->bulk_clks); | |
0eb0d9f4 GD |
2099 | bus_clk_disable: |
2100 | if (!IS_ERR(msm_host->bus_clk)) | |
2101 | clk_disable_unprepare(msm_host->bus_clk); | |
2102 | pltfm_free: | |
2103 | sdhci_pltfm_free(pdev); | |
2104 | return ret; | |
2105 | } | |
2106 | ||
2107 | static int sdhci_msm_remove(struct platform_device *pdev) | |
2108 | { | |
2109 | struct sdhci_host *host = platform_get_drvdata(pdev); | |
2110 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
6f699531 | 2111 | struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host); |
0eb0d9f4 GD |
2112 | int dead = (readl_relaxed(host->ioaddr + SDHCI_INT_STATUS) == |
2113 | 0xffffffff); | |
2114 | ||
2115 | sdhci_remove_host(host, dead); | |
67e6db11 PG |
2116 | |
2117 | pm_runtime_get_sync(&pdev->dev); | |
2118 | pm_runtime_disable(&pdev->dev); | |
2119 | pm_runtime_put_noidle(&pdev->dev); | |
2120 | ||
e4bf91f6 BA |
2121 | clk_bulk_disable_unprepare(ARRAY_SIZE(msm_host->bulk_clks), |
2122 | msm_host->bulk_clks); | |
0eb0d9f4 GD |
2123 | if (!IS_ERR(msm_host->bus_clk)) |
2124 | clk_disable_unprepare(msm_host->bus_clk); | |
6f699531 | 2125 | sdhci_pltfm_free(pdev); |
0eb0d9f4 GD |
2126 | return 0; |
2127 | } | |
2128 | ||
6809a5f7 | 2129 | static __maybe_unused int sdhci_msm_runtime_suspend(struct device *dev) |
67e6db11 PG |
2130 | { |
2131 | struct sdhci_host *host = dev_get_drvdata(dev); | |
2132 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
2133 | struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host); | |
2134 | ||
e4bf91f6 BA |
2135 | clk_bulk_disable_unprepare(ARRAY_SIZE(msm_host->bulk_clks), |
2136 | msm_host->bulk_clks); | |
67e6db11 PG |
2137 | |
2138 | return 0; | |
2139 | } | |
2140 | ||
6809a5f7 | 2141 | static __maybe_unused int sdhci_msm_runtime_resume(struct device *dev) |
67e6db11 PG |
2142 | { |
2143 | struct sdhci_host *host = dev_get_drvdata(dev); | |
2144 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
2145 | struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host); | |
21f1e2d4 | 2146 | int ret; |
67e6db11 | 2147 | |
21f1e2d4 | 2148 | ret = clk_bulk_prepare_enable(ARRAY_SIZE(msm_host->bulk_clks), |
e4bf91f6 | 2149 | msm_host->bulk_clks); |
21f1e2d4 VB |
2150 | if (ret) |
2151 | return ret; | |
2152 | /* | |
2153 | * Whenever core-clock is gated dynamically, it's needed to | |
2154 | * restore the SDR DLL settings when the clock is ungated. | |
2155 | */ | |
2156 | if (msm_host->restore_dll_config && msm_host->clk_rate) | |
2157 | return sdhci_msm_restore_sdr_dll_config(host); | |
2158 | ||
2159 | return 0; | |
67e6db11 | 2160 | } |
67e6db11 PG |
2161 | |
2162 | static const struct dev_pm_ops sdhci_msm_pm_ops = { | |
2163 | SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, | |
2164 | pm_runtime_force_resume) | |
2165 | SET_RUNTIME_PM_OPS(sdhci_msm_runtime_suspend, | |
2166 | sdhci_msm_runtime_resume, | |
2167 | NULL) | |
2168 | }; | |
2169 | ||
0eb0d9f4 GD |
2170 | static struct platform_driver sdhci_msm_driver = { |
2171 | .probe = sdhci_msm_probe, | |
2172 | .remove = sdhci_msm_remove, | |
2173 | .driver = { | |
2174 | .name = "sdhci_msm", | |
0eb0d9f4 | 2175 | .of_match_table = sdhci_msm_dt_match, |
67e6db11 | 2176 | .pm = &sdhci_msm_pm_ops, |
0eb0d9f4 GD |
2177 | }, |
2178 | }; | |
2179 | ||
2180 | module_platform_driver(sdhci_msm_driver); | |
2181 | ||
2182 | MODULE_DESCRIPTION("Qualcomm Secure Digital Host Controller Interface driver"); | |
2183 | MODULE_LICENSE("GPL v2"); |