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0eb0d9f4 GD |
1 | /* |
2 | * drivers/mmc/host/sdhci-msm.c - Qualcomm SDHCI Platform driver | |
3 | * | |
4 | * Copyright (c) 2013-2014, The Linux Foundation. All rights reserved. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 and | |
8 | * only version 2 as published by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | */ | |
16 | ||
17 | #include <linux/module.h> | |
18 | #include <linux/of_device.h> | |
0eb0d9f4 | 19 | #include <linux/delay.h> |
415b5a75 | 20 | #include <linux/mmc/mmc.h> |
67e6db11 | 21 | #include <linux/pm_runtime.h> |
415b5a75 | 22 | #include <linux/slab.h> |
cc392c58 | 23 | #include <linux/iopoll.h> |
0eb0d9f4 GD |
24 | |
25 | #include "sdhci-pltfm.h" | |
26 | ||
3a3ad3e9 GD |
27 | #define CORE_MCI_VERSION 0x50 |
28 | #define CORE_VERSION_MAJOR_SHIFT 28 | |
29 | #define CORE_VERSION_MAJOR_MASK (0xf << CORE_VERSION_MAJOR_SHIFT) | |
30 | #define CORE_VERSION_MINOR_MASK 0xff | |
31 | ||
0eb0d9f4 GD |
32 | #define CORE_HC_MODE 0x78 |
33 | #define HC_MODE_EN 0x1 | |
34 | #define CORE_POWER 0x0 | |
35 | #define CORE_SW_RST BIT(7) | |
ff06ce41 | 36 | #define FF_CLK_SW_RST_DIS BIT(13) |
0eb0d9f4 | 37 | |
ad81d387 GD |
38 | #define CORE_PWRCTL_STATUS 0xdc |
39 | #define CORE_PWRCTL_MASK 0xe0 | |
40 | #define CORE_PWRCTL_CLEAR 0xe4 | |
41 | #define CORE_PWRCTL_CTL 0xe8 | |
42 | #define CORE_PWRCTL_BUS_OFF BIT(0) | |
43 | #define CORE_PWRCTL_BUS_ON BIT(1) | |
44 | #define CORE_PWRCTL_IO_LOW BIT(2) | |
45 | #define CORE_PWRCTL_IO_HIGH BIT(3) | |
46 | #define CORE_PWRCTL_BUS_SUCCESS BIT(0) | |
47 | #define CORE_PWRCTL_IO_SUCCESS BIT(2) | |
48 | #define REQ_BUS_OFF BIT(0) | |
49 | #define REQ_BUS_ON BIT(1) | |
50 | #define REQ_IO_LOW BIT(2) | |
51 | #define REQ_IO_HIGH BIT(3) | |
52 | #define INT_MASK 0xf | |
415b5a75 GD |
53 | #define MAX_PHASES 16 |
54 | #define CORE_DLL_LOCK BIT(7) | |
02e4293d | 55 | #define CORE_DDR_DLL_LOCK BIT(11) |
415b5a75 GD |
56 | #define CORE_DLL_EN BIT(16) |
57 | #define CORE_CDR_EN BIT(17) | |
58 | #define CORE_CK_OUT_EN BIT(18) | |
59 | #define CORE_CDR_EXT_EN BIT(19) | |
60 | #define CORE_DLL_PDN BIT(29) | |
61 | #define CORE_DLL_RST BIT(30) | |
62 | #define CORE_DLL_CONFIG 0x100 | |
cc392c58 | 63 | #define CORE_CMD_DAT_TRACK_SEL BIT(0) |
415b5a75 GD |
64 | #define CORE_DLL_STATUS 0x108 |
65 | ||
83736352 | 66 | #define CORE_DLL_CONFIG_2 0x1b4 |
02e4293d | 67 | #define CORE_DDR_CAL_EN BIT(0) |
83736352 VG |
68 | #define CORE_FLL_CYCLE_CNT BIT(18) |
69 | #define CORE_DLL_CLOCK_DISABLE BIT(21) | |
70 | ||
415b5a75 | 71 | #define CORE_VENDOR_SPEC 0x10c |
5574ddcc | 72 | #define CORE_VENDOR_SPEC_POR_VAL 0xa1c |
415b5a75 | 73 | #define CORE_CLK_PWRSAVE BIT(1) |
ff06ce41 VG |
74 | #define CORE_HC_MCLK_SEL_DFLT (2 << 8) |
75 | #define CORE_HC_MCLK_SEL_HS400 (3 << 8) | |
76 | #define CORE_HC_MCLK_SEL_MASK (3 << 8) | |
77 | #define CORE_HC_SELECT_IN_EN BIT(18) | |
78 | #define CORE_HC_SELECT_IN_HS400 (6 << 19) | |
79 | #define CORE_HC_SELECT_IN_MASK (7 << 19) | |
415b5a75 | 80 | |
cc392c58 RH |
81 | #define CORE_CSR_CDC_CTLR_CFG0 0x130 |
82 | #define CORE_SW_TRIG_FULL_CALIB BIT(16) | |
83 | #define CORE_HW_AUTOCAL_ENA BIT(17) | |
84 | ||
85 | #define CORE_CSR_CDC_CTLR_CFG1 0x134 | |
86 | #define CORE_CSR_CDC_CAL_TIMER_CFG0 0x138 | |
87 | #define CORE_TIMER_ENA BIT(16) | |
88 | ||
89 | #define CORE_CSR_CDC_CAL_TIMER_CFG1 0x13C | |
90 | #define CORE_CSR_CDC_REFCOUNT_CFG 0x140 | |
91 | #define CORE_CSR_CDC_COARSE_CAL_CFG 0x144 | |
92 | #define CORE_CDC_OFFSET_CFG 0x14C | |
93 | #define CORE_CSR_CDC_DELAY_CFG 0x150 | |
94 | #define CORE_CDC_SLAVE_DDA_CFG 0x160 | |
95 | #define CORE_CSR_CDC_STATUS0 0x164 | |
96 | #define CORE_CALIBRATION_DONE BIT(0) | |
97 | ||
98 | #define CORE_CDC_ERROR_CODE_MASK 0x7000000 | |
99 | ||
100 | #define CORE_CSR_CDC_GEN_CFG 0x178 | |
101 | #define CORE_CDC_SWITCH_BYPASS_OFF BIT(0) | |
102 | #define CORE_CDC_SWITCH_RC_EN BIT(1) | |
103 | ||
104 | #define CORE_DDR_200_CFG 0x184 | |
105 | #define CORE_CDC_T4_DLY_SEL BIT(0) | |
106 | #define CORE_START_CDC_TRAFFIC BIT(6) | |
02e4293d RH |
107 | #define CORE_VENDOR_SPEC3 0x1b0 |
108 | #define CORE_PWRSAVE_DLL BIT(3) | |
109 | ||
110 | #define CORE_DDR_CONFIG 0x1b8 | |
111 | #define DDR_CONFIG_POR_VAL 0x80040853 | |
cc392c58 | 112 | |
3a3ad3e9 GD |
113 | #define CORE_VENDOR_SPEC_CAPABILITIES0 0x11c |
114 | ||
abf270e5 | 115 | #define INVALID_TUNING_PHASE -1 |
80031bde | 116 | #define SDHCI_MSM_MIN_CLOCK 400000 |
ff06ce41 | 117 | #define CORE_FREQ_100MHZ (100 * 1000 * 1000) |
80031bde | 118 | |
415b5a75 GD |
119 | #define CDR_SELEXT_SHIFT 20 |
120 | #define CDR_SELEXT_MASK (0xf << CDR_SELEXT_SHIFT) | |
121 | #define CMUX_SHIFT_PHASE_SHIFT 24 | |
122 | #define CMUX_SHIFT_PHASE_MASK (7 << CMUX_SHIFT_PHASE_SHIFT) | |
123 | ||
67e6db11 | 124 | #define MSM_MMC_AUTOSUSPEND_DELAY_MS 50 |
0eb0d9f4 GD |
125 | struct sdhci_msm_host { |
126 | struct platform_device *pdev; | |
127 | void __iomem *core_mem; /* MSM SDCC mapped address */ | |
ad81d387 | 128 | int pwr_irq; /* power irq */ |
0eb0d9f4 GD |
129 | struct clk *clk; /* main SD/MMC bus clock */ |
130 | struct clk *pclk; /* SDHC peripheral bus clock */ | |
131 | struct clk *bus_clk; /* SDHC bus voter clock */ | |
83736352 | 132 | struct clk *xo_clk; /* TCXO clk needed for FLL feature of cm_dll*/ |
edc609fd | 133 | unsigned long clk_rate; |
0eb0d9f4 | 134 | struct mmc_host *mmc; |
83736352 | 135 | bool use_14lpp_dll_reset; |
ff06ce41 VG |
136 | bool tuning_done; |
137 | bool calibration_done; | |
abf270e5 | 138 | u8 saved_tuning_phase; |
02e4293d | 139 | bool use_cdclp533; |
0eb0d9f4 GD |
140 | }; |
141 | ||
0fb8a3d4 RH |
142 | static unsigned int msm_get_clock_rate_for_bus_mode(struct sdhci_host *host, |
143 | unsigned int clock) | |
144 | { | |
145 | struct mmc_ios ios = host->mmc->ios; | |
146 | /* | |
147 | * The SDHC requires internal clock frequency to be double the | |
148 | * actual clock that will be set for DDR mode. The controller | |
149 | * uses the faster clock(100/400MHz) for some of its parts and | |
150 | * send the actual required clock (50/200MHz) to the card. | |
151 | */ | |
152 | if (ios.timing == MMC_TIMING_UHS_DDR50 || | |
153 | ios.timing == MMC_TIMING_MMC_DDR52 || | |
154 | ios.timing == MMC_TIMING_MMC_HS400) | |
155 | clock *= 2; | |
156 | return clock; | |
157 | } | |
158 | ||
159 | static void msm_set_clock_rate_for_bus_mode(struct sdhci_host *host, | |
160 | unsigned int clock) | |
161 | { | |
162 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
163 | struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host); | |
164 | struct mmc_ios curr_ios = host->mmc->ios; | |
165 | int rc; | |
166 | ||
167 | clock = msm_get_clock_rate_for_bus_mode(host, clock); | |
168 | rc = clk_set_rate(msm_host->clk, clock); | |
169 | if (rc) { | |
170 | pr_err("%s: Failed to set clock at rate %u at timing %d\n", | |
171 | mmc_hostname(host->mmc), clock, | |
172 | curr_ios.timing); | |
173 | return; | |
174 | } | |
175 | msm_host->clk_rate = clock; | |
176 | pr_debug("%s: Setting clock at rate %lu at timing %d\n", | |
177 | mmc_hostname(host->mmc), clk_get_rate(msm_host->clk), | |
178 | curr_ios.timing); | |
179 | } | |
180 | ||
0eb0d9f4 | 181 | /* Platform specific tuning */ |
415b5a75 GD |
182 | static inline int msm_dll_poll_ck_out_en(struct sdhci_host *host, u8 poll) |
183 | { | |
184 | u32 wait_cnt = 50; | |
185 | u8 ck_out_en; | |
186 | struct mmc_host *mmc = host->mmc; | |
187 | ||
188 | /* Poll for CK_OUT_EN bit. max. poll time = 50us */ | |
189 | ck_out_en = !!(readl_relaxed(host->ioaddr + CORE_DLL_CONFIG) & | |
190 | CORE_CK_OUT_EN); | |
191 | ||
192 | while (ck_out_en != poll) { | |
193 | if (--wait_cnt == 0) { | |
194 | dev_err(mmc_dev(mmc), "%s: CK_OUT_EN bit is not %d\n", | |
195 | mmc_hostname(mmc), poll); | |
196 | return -ETIMEDOUT; | |
197 | } | |
198 | udelay(1); | |
199 | ||
200 | ck_out_en = !!(readl_relaxed(host->ioaddr + CORE_DLL_CONFIG) & | |
201 | CORE_CK_OUT_EN); | |
202 | } | |
203 | ||
204 | return 0; | |
205 | } | |
206 | ||
207 | static int msm_config_cm_dll_phase(struct sdhci_host *host, u8 phase) | |
208 | { | |
209 | int rc; | |
210 | static const u8 grey_coded_phase_table[] = { | |
211 | 0x0, 0x1, 0x3, 0x2, 0x6, 0x7, 0x5, 0x4, | |
212 | 0xc, 0xd, 0xf, 0xe, 0xa, 0xb, 0x9, 0x8 | |
213 | }; | |
214 | unsigned long flags; | |
215 | u32 config; | |
216 | struct mmc_host *mmc = host->mmc; | |
217 | ||
abf270e5 RH |
218 | if (phase > 0xf) |
219 | return -EINVAL; | |
220 | ||
415b5a75 GD |
221 | spin_lock_irqsave(&host->lock, flags); |
222 | ||
223 | config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG); | |
224 | config &= ~(CORE_CDR_EN | CORE_CK_OUT_EN); | |
225 | config |= (CORE_CDR_EXT_EN | CORE_DLL_EN); | |
226 | writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG); | |
227 | ||
228 | /* Wait until CK_OUT_EN bit of DLL_CONFIG register becomes '0' */ | |
229 | rc = msm_dll_poll_ck_out_en(host, 0); | |
230 | if (rc) | |
231 | goto err_out; | |
232 | ||
233 | /* | |
234 | * Write the selected DLL clock output phase (0 ... 15) | |
235 | * to CDR_SELEXT bit field of DLL_CONFIG register. | |
236 | */ | |
237 | config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG); | |
238 | config &= ~CDR_SELEXT_MASK; | |
239 | config |= grey_coded_phase_table[phase] << CDR_SELEXT_SHIFT; | |
240 | writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG); | |
241 | ||
29301f40 RH |
242 | config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG); |
243 | config |= CORE_CK_OUT_EN; | |
244 | writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG); | |
415b5a75 GD |
245 | |
246 | /* Wait until CK_OUT_EN bit of DLL_CONFIG register becomes '1' */ | |
247 | rc = msm_dll_poll_ck_out_en(host, 1); | |
248 | if (rc) | |
249 | goto err_out; | |
250 | ||
251 | config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG); | |
252 | config |= CORE_CDR_EN; | |
253 | config &= ~CORE_CDR_EXT_EN; | |
254 | writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG); | |
255 | goto out; | |
256 | ||
257 | err_out: | |
258 | dev_err(mmc_dev(mmc), "%s: Failed to set DLL phase: %d\n", | |
259 | mmc_hostname(mmc), phase); | |
260 | out: | |
261 | spin_unlock_irqrestore(&host->lock, flags); | |
262 | return rc; | |
263 | } | |
264 | ||
265 | /* | |
266 | * Find out the greatest range of consecuitive selected | |
267 | * DLL clock output phases that can be used as sampling | |
268 | * setting for SD3.0 UHS-I card read operation (in SDR104 | |
ff06ce41 VG |
269 | * timing mode) or for eMMC4.5 card read operation (in |
270 | * HS400/HS200 timing mode). | |
415b5a75 GD |
271 | * Select the 3/4 of the range and configure the DLL with the |
272 | * selected DLL clock output phase. | |
273 | */ | |
274 | ||
275 | static int msm_find_most_appropriate_phase(struct sdhci_host *host, | |
276 | u8 *phase_table, u8 total_phases) | |
277 | { | |
278 | int ret; | |
279 | u8 ranges[MAX_PHASES][MAX_PHASES] = { {0}, {0} }; | |
280 | u8 phases_per_row[MAX_PHASES] = { 0 }; | |
281 | int row_index = 0, col_index = 0, selected_row_index = 0, curr_max = 0; | |
282 | int i, cnt, phase_0_raw_index = 0, phase_15_raw_index = 0; | |
283 | bool phase_0_found = false, phase_15_found = false; | |
284 | struct mmc_host *mmc = host->mmc; | |
285 | ||
286 | if (!total_phases || (total_phases > MAX_PHASES)) { | |
287 | dev_err(mmc_dev(mmc), "%s: Invalid argument: total_phases=%d\n", | |
288 | mmc_hostname(mmc), total_phases); | |
289 | return -EINVAL; | |
290 | } | |
291 | ||
292 | for (cnt = 0; cnt < total_phases; cnt++) { | |
293 | ranges[row_index][col_index] = phase_table[cnt]; | |
294 | phases_per_row[row_index] += 1; | |
295 | col_index++; | |
296 | ||
297 | if ((cnt + 1) == total_phases) { | |
298 | continue; | |
299 | /* check if next phase in phase_table is consecutive or not */ | |
300 | } else if ((phase_table[cnt] + 1) != phase_table[cnt + 1]) { | |
301 | row_index++; | |
302 | col_index = 0; | |
303 | } | |
304 | } | |
305 | ||
306 | if (row_index >= MAX_PHASES) | |
307 | return -EINVAL; | |
308 | ||
309 | /* Check if phase-0 is present in first valid window? */ | |
310 | if (!ranges[0][0]) { | |
311 | phase_0_found = true; | |
312 | phase_0_raw_index = 0; | |
313 | /* Check if cycle exist between 2 valid windows */ | |
314 | for (cnt = 1; cnt <= row_index; cnt++) { | |
315 | if (phases_per_row[cnt]) { | |
316 | for (i = 0; i < phases_per_row[cnt]; i++) { | |
317 | if (ranges[cnt][i] == 15) { | |
318 | phase_15_found = true; | |
319 | phase_15_raw_index = cnt; | |
320 | break; | |
321 | } | |
322 | } | |
323 | } | |
324 | } | |
325 | } | |
326 | ||
327 | /* If 2 valid windows form cycle then merge them as single window */ | |
328 | if (phase_0_found && phase_15_found) { | |
329 | /* number of phases in raw where phase 0 is present */ | |
330 | u8 phases_0 = phases_per_row[phase_0_raw_index]; | |
331 | /* number of phases in raw where phase 15 is present */ | |
332 | u8 phases_15 = phases_per_row[phase_15_raw_index]; | |
333 | ||
334 | if (phases_0 + phases_15 >= MAX_PHASES) | |
335 | /* | |
336 | * If there are more than 1 phase windows then total | |
337 | * number of phases in both the windows should not be | |
338 | * more than or equal to MAX_PHASES. | |
339 | */ | |
340 | return -EINVAL; | |
341 | ||
342 | /* Merge 2 cyclic windows */ | |
343 | i = phases_15; | |
344 | for (cnt = 0; cnt < phases_0; cnt++) { | |
345 | ranges[phase_15_raw_index][i] = | |
346 | ranges[phase_0_raw_index][cnt]; | |
347 | if (++i >= MAX_PHASES) | |
348 | break; | |
349 | } | |
350 | ||
351 | phases_per_row[phase_0_raw_index] = 0; | |
352 | phases_per_row[phase_15_raw_index] = phases_15 + phases_0; | |
353 | } | |
354 | ||
355 | for (cnt = 0; cnt <= row_index; cnt++) { | |
356 | if (phases_per_row[cnt] > curr_max) { | |
357 | curr_max = phases_per_row[cnt]; | |
358 | selected_row_index = cnt; | |
359 | } | |
360 | } | |
361 | ||
362 | i = (curr_max * 3) / 4; | |
363 | if (i) | |
364 | i--; | |
365 | ||
366 | ret = ranges[selected_row_index][i]; | |
367 | ||
368 | if (ret >= MAX_PHASES) { | |
369 | ret = -EINVAL; | |
370 | dev_err(mmc_dev(mmc), "%s: Invalid phase selected=%d\n", | |
371 | mmc_hostname(mmc), ret); | |
372 | } | |
373 | ||
374 | return ret; | |
375 | } | |
376 | ||
377 | static inline void msm_cm_dll_set_freq(struct sdhci_host *host) | |
0eb0d9f4 | 378 | { |
415b5a75 GD |
379 | u32 mclk_freq = 0, config; |
380 | ||
381 | /* Program the MCLK value to MCLK_FREQ bit field */ | |
382 | if (host->clock <= 112000000) | |
383 | mclk_freq = 0; | |
384 | else if (host->clock <= 125000000) | |
385 | mclk_freq = 1; | |
386 | else if (host->clock <= 137000000) | |
387 | mclk_freq = 2; | |
388 | else if (host->clock <= 150000000) | |
389 | mclk_freq = 3; | |
390 | else if (host->clock <= 162000000) | |
391 | mclk_freq = 4; | |
392 | else if (host->clock <= 175000000) | |
393 | mclk_freq = 5; | |
394 | else if (host->clock <= 187000000) | |
395 | mclk_freq = 6; | |
396 | else if (host->clock <= 200000000) | |
397 | mclk_freq = 7; | |
398 | ||
399 | config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG); | |
400 | config &= ~CMUX_SHIFT_PHASE_MASK; | |
401 | config |= mclk_freq << CMUX_SHIFT_PHASE_SHIFT; | |
402 | writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG); | |
403 | } | |
404 | ||
405 | /* Initialize the DLL (Programmable Delay Line) */ | |
406 | static int msm_init_cm_dll(struct sdhci_host *host) | |
407 | { | |
408 | struct mmc_host *mmc = host->mmc; | |
83736352 VG |
409 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
410 | struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host); | |
415b5a75 GD |
411 | int wait_cnt = 50; |
412 | unsigned long flags; | |
29301f40 | 413 | u32 config; |
415b5a75 GD |
414 | |
415 | spin_lock_irqsave(&host->lock, flags); | |
416 | ||
0eb0d9f4 | 417 | /* |
415b5a75 GD |
418 | * Make sure that clock is always enabled when DLL |
419 | * tuning is in progress. Keeping PWRSAVE ON may | |
420 | * turn off the clock. | |
0eb0d9f4 | 421 | */ |
29301f40 RH |
422 | config = readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC); |
423 | config &= ~CORE_CLK_PWRSAVE; | |
424 | writel_relaxed(config, host->ioaddr + CORE_VENDOR_SPEC); | |
415b5a75 | 425 | |
83736352 VG |
426 | if (msm_host->use_14lpp_dll_reset) { |
427 | config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG); | |
428 | config &= ~CORE_CK_OUT_EN; | |
429 | writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG); | |
430 | ||
431 | config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG_2); | |
432 | config |= CORE_DLL_CLOCK_DISABLE; | |
433 | writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG_2); | |
434 | } | |
435 | ||
29301f40 RH |
436 | config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG); |
437 | config |= CORE_DLL_RST; | |
438 | writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG); | |
415b5a75 | 439 | |
29301f40 RH |
440 | config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG); |
441 | config |= CORE_DLL_PDN; | |
442 | writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG); | |
415b5a75 GD |
443 | msm_cm_dll_set_freq(host); |
444 | ||
83736352 VG |
445 | if (msm_host->use_14lpp_dll_reset && |
446 | !IS_ERR_OR_NULL(msm_host->xo_clk)) { | |
447 | u32 mclk_freq = 0; | |
448 | ||
449 | config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG_2); | |
450 | config &= CORE_FLL_CYCLE_CNT; | |
451 | if (config) | |
452 | mclk_freq = DIV_ROUND_CLOSEST_ULL((host->clock * 8), | |
453 | clk_get_rate(msm_host->xo_clk)); | |
454 | else | |
455 | mclk_freq = DIV_ROUND_CLOSEST_ULL((host->clock * 4), | |
456 | clk_get_rate(msm_host->xo_clk)); | |
457 | ||
458 | config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG_2); | |
459 | config &= ~(0xFF << 10); | |
460 | config |= mclk_freq << 10; | |
461 | ||
462 | writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG_2); | |
463 | /* wait for 5us before enabling DLL clock */ | |
464 | udelay(5); | |
465 | } | |
466 | ||
29301f40 RH |
467 | config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG); |
468 | config &= ~CORE_DLL_RST; | |
469 | writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG); | |
415b5a75 | 470 | |
29301f40 RH |
471 | config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG); |
472 | config &= ~CORE_DLL_PDN; | |
473 | writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG); | |
415b5a75 | 474 | |
83736352 VG |
475 | if (msm_host->use_14lpp_dll_reset) { |
476 | msm_cm_dll_set_freq(host); | |
477 | config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG_2); | |
478 | config &= ~CORE_DLL_CLOCK_DISABLE; | |
479 | writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG_2); | |
480 | } | |
481 | ||
29301f40 RH |
482 | config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG); |
483 | config |= CORE_DLL_EN; | |
484 | writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG); | |
415b5a75 | 485 | |
29301f40 RH |
486 | config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG); |
487 | config |= CORE_CK_OUT_EN; | |
488 | writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG); | |
415b5a75 GD |
489 | |
490 | /* Wait until DLL_LOCK bit of DLL_STATUS register becomes '1' */ | |
491 | while (!(readl_relaxed(host->ioaddr + CORE_DLL_STATUS) & | |
492 | CORE_DLL_LOCK)) { | |
493 | /* max. wait for 50us sec for LOCK bit to be set */ | |
494 | if (--wait_cnt == 0) { | |
495 | dev_err(mmc_dev(mmc), "%s: DLL failed to LOCK\n", | |
496 | mmc_hostname(mmc)); | |
497 | spin_unlock_irqrestore(&host->lock, flags); | |
498 | return -ETIMEDOUT; | |
499 | } | |
500 | udelay(1); | |
501 | } | |
502 | ||
503 | spin_unlock_irqrestore(&host->lock, flags); | |
0eb0d9f4 GD |
504 | return 0; |
505 | } | |
506 | ||
b54aaa8a RH |
507 | static void msm_hc_select_default(struct sdhci_host *host) |
508 | { | |
509 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
510 | struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host); | |
511 | u32 config; | |
512 | ||
513 | if (!msm_host->use_cdclp533) { | |
514 | config = readl_relaxed(host->ioaddr + | |
515 | CORE_VENDOR_SPEC3); | |
516 | config &= ~CORE_PWRSAVE_DLL; | |
517 | writel_relaxed(config, host->ioaddr + | |
518 | CORE_VENDOR_SPEC3); | |
519 | } | |
520 | ||
521 | config = readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC); | |
522 | config &= ~CORE_HC_MCLK_SEL_MASK; | |
523 | config |= CORE_HC_MCLK_SEL_DFLT; | |
524 | writel_relaxed(config, host->ioaddr + CORE_VENDOR_SPEC); | |
525 | ||
526 | /* | |
527 | * Disable HC_SELECT_IN to be able to use the UHS mode select | |
528 | * configuration from Host Control2 register for all other | |
529 | * modes. | |
530 | * Write 0 to HC_SELECT_IN and HC_SELECT_IN_EN field | |
531 | * in VENDOR_SPEC_FUNC | |
532 | */ | |
533 | config = readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC); | |
534 | config &= ~CORE_HC_SELECT_IN_EN; | |
535 | config &= ~CORE_HC_SELECT_IN_MASK; | |
536 | writel_relaxed(config, host->ioaddr + CORE_VENDOR_SPEC); | |
537 | ||
538 | /* | |
539 | * Make sure above writes impacting free running MCLK are completed | |
540 | * before changing the clk_rate at GCC. | |
541 | */ | |
542 | wmb(); | |
543 | } | |
544 | ||
545 | static void msm_hc_select_hs400(struct sdhci_host *host) | |
546 | { | |
547 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
548 | struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host); | |
549 | u32 config, dll_lock; | |
550 | int rc; | |
551 | ||
552 | /* Select the divided clock (free running MCLK/2) */ | |
553 | config = readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC); | |
554 | config &= ~CORE_HC_MCLK_SEL_MASK; | |
555 | config |= CORE_HC_MCLK_SEL_HS400; | |
556 | ||
557 | writel_relaxed(config, host->ioaddr + CORE_VENDOR_SPEC); | |
558 | /* | |
559 | * Select HS400 mode using the HC_SELECT_IN from VENDOR SPEC | |
560 | * register | |
561 | */ | |
562 | if (msm_host->tuning_done && !msm_host->calibration_done) { | |
563 | config = readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC); | |
564 | config |= CORE_HC_SELECT_IN_HS400; | |
565 | config |= CORE_HC_SELECT_IN_EN; | |
566 | writel_relaxed(config, host->ioaddr + CORE_VENDOR_SPEC); | |
567 | } | |
568 | if (!msm_host->clk_rate && !msm_host->use_cdclp533) { | |
569 | /* | |
570 | * Poll on DLL_LOCK or DDR_DLL_LOCK bits in | |
571 | * CORE_DLL_STATUS to be set. This should get set | |
572 | * within 15 us at 200 MHz. | |
573 | */ | |
574 | rc = readl_relaxed_poll_timeout(host->ioaddr + | |
575 | CORE_DLL_STATUS, | |
576 | dll_lock, | |
577 | (dll_lock & | |
578 | (CORE_DLL_LOCK | | |
579 | CORE_DDR_DLL_LOCK)), 10, | |
580 | 1000); | |
581 | if (rc == -ETIMEDOUT) | |
582 | pr_err("%s: Unable to get DLL_LOCK/DDR_DLL_LOCK, dll_status: 0x%08x\n", | |
583 | mmc_hostname(host->mmc), dll_lock); | |
584 | } | |
585 | /* | |
586 | * Make sure above writes impacting free running MCLK are completed | |
587 | * before changing the clk_rate at GCC. | |
588 | */ | |
589 | wmb(); | |
590 | } | |
591 | ||
592 | /* | |
593 | * sdhci_msm_hc_select_mode :- In general all timing modes are | |
594 | * controlled via UHS mode select in Host Control2 register. | |
595 | * eMMC specific HS200/HS400 doesn't have their respective modes | |
596 | * defined here, hence we use these values. | |
597 | * | |
598 | * HS200 - SDR104 (Since they both are equivalent in functionality) | |
599 | * HS400 - This involves multiple configurations | |
600 | * Initially SDR104 - when tuning is required as HS200 | |
601 | * Then when switching to DDR @ 400MHz (HS400) we use | |
602 | * the vendor specific HC_SELECT_IN to control the mode. | |
603 | * | |
604 | * In addition to controlling the modes we also need to select the | |
605 | * correct input clock for DLL depending on the mode. | |
606 | * | |
607 | * HS400 - divided clock (free running MCLK/2) | |
608 | * All other modes - default (free running MCLK) | |
609 | */ | |
610 | void sdhci_msm_hc_select_mode(struct sdhci_host *host) | |
611 | { | |
612 | struct mmc_ios ios = host->mmc->ios; | |
613 | ||
614 | if (ios.timing == MMC_TIMING_MMC_HS400) | |
615 | msm_hc_select_hs400(host); | |
616 | else | |
617 | msm_hc_select_default(host); | |
618 | } | |
619 | ||
cc392c58 RH |
620 | static int sdhci_msm_cdclp533_calibration(struct sdhci_host *host) |
621 | { | |
622 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
623 | struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host); | |
624 | u32 config, calib_done; | |
625 | int ret; | |
626 | ||
627 | pr_debug("%s: %s: Enter\n", mmc_hostname(host->mmc), __func__); | |
628 | ||
629 | /* | |
630 | * Retuning in HS400 (DDR mode) will fail, just reset the | |
631 | * tuning block and restore the saved tuning phase. | |
632 | */ | |
633 | ret = msm_init_cm_dll(host); | |
634 | if (ret) | |
635 | goto out; | |
636 | ||
637 | /* Set the selected phase in delay line hw block */ | |
638 | ret = msm_config_cm_dll_phase(host, msm_host->saved_tuning_phase); | |
639 | if (ret) | |
640 | goto out; | |
641 | ||
642 | config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG); | |
643 | config |= CORE_CMD_DAT_TRACK_SEL; | |
644 | writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG); | |
645 | ||
646 | config = readl_relaxed(host->ioaddr + CORE_DDR_200_CFG); | |
647 | config &= ~CORE_CDC_T4_DLY_SEL; | |
648 | writel_relaxed(config, host->ioaddr + CORE_DDR_200_CFG); | |
649 | ||
650 | config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_GEN_CFG); | |
651 | config &= ~CORE_CDC_SWITCH_BYPASS_OFF; | |
652 | writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_GEN_CFG); | |
653 | ||
654 | config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_GEN_CFG); | |
655 | config |= CORE_CDC_SWITCH_RC_EN; | |
656 | writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_GEN_CFG); | |
657 | ||
658 | config = readl_relaxed(host->ioaddr + CORE_DDR_200_CFG); | |
659 | config &= ~CORE_START_CDC_TRAFFIC; | |
660 | writel_relaxed(config, host->ioaddr + CORE_DDR_200_CFG); | |
661 | ||
662 | /* | |
663 | * Perform CDC Register Initialization Sequence | |
664 | * | |
665 | * CORE_CSR_CDC_CTLR_CFG0 0x11800EC | |
666 | * CORE_CSR_CDC_CTLR_CFG1 0x3011111 | |
667 | * CORE_CSR_CDC_CAL_TIMER_CFG0 0x1201000 | |
668 | * CORE_CSR_CDC_CAL_TIMER_CFG1 0x4 | |
669 | * CORE_CSR_CDC_REFCOUNT_CFG 0xCB732020 | |
670 | * CORE_CSR_CDC_COARSE_CAL_CFG 0xB19 | |
671 | * CORE_CSR_CDC_DELAY_CFG 0x3AC | |
672 | * CORE_CDC_OFFSET_CFG 0x0 | |
673 | * CORE_CDC_SLAVE_DDA_CFG 0x16334 | |
674 | */ | |
675 | ||
676 | writel_relaxed(0x11800EC, host->ioaddr + CORE_CSR_CDC_CTLR_CFG0); | |
677 | writel_relaxed(0x3011111, host->ioaddr + CORE_CSR_CDC_CTLR_CFG1); | |
678 | writel_relaxed(0x1201000, host->ioaddr + CORE_CSR_CDC_CAL_TIMER_CFG0); | |
679 | writel_relaxed(0x4, host->ioaddr + CORE_CSR_CDC_CAL_TIMER_CFG1); | |
680 | writel_relaxed(0xCB732020, host->ioaddr + CORE_CSR_CDC_REFCOUNT_CFG); | |
681 | writel_relaxed(0xB19, host->ioaddr + CORE_CSR_CDC_COARSE_CAL_CFG); | |
083c9aa0 | 682 | writel_relaxed(0x4E2, host->ioaddr + CORE_CSR_CDC_DELAY_CFG); |
cc392c58 RH |
683 | writel_relaxed(0x0, host->ioaddr + CORE_CDC_OFFSET_CFG); |
684 | writel_relaxed(0x16334, host->ioaddr + CORE_CDC_SLAVE_DDA_CFG); | |
685 | ||
686 | /* CDC HW Calibration */ | |
687 | ||
688 | config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_CTLR_CFG0); | |
689 | config |= CORE_SW_TRIG_FULL_CALIB; | |
690 | writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_CTLR_CFG0); | |
691 | ||
692 | config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_CTLR_CFG0); | |
693 | config &= ~CORE_SW_TRIG_FULL_CALIB; | |
694 | writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_CTLR_CFG0); | |
695 | ||
696 | config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_CTLR_CFG0); | |
697 | config |= CORE_HW_AUTOCAL_ENA; | |
698 | writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_CTLR_CFG0); | |
699 | ||
700 | config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_CAL_TIMER_CFG0); | |
701 | config |= CORE_TIMER_ENA; | |
702 | writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_CAL_TIMER_CFG0); | |
703 | ||
704 | ret = readl_relaxed_poll_timeout(host->ioaddr + CORE_CSR_CDC_STATUS0, | |
705 | calib_done, | |
706 | (calib_done & CORE_CALIBRATION_DONE), | |
707 | 1, 50); | |
708 | ||
709 | if (ret == -ETIMEDOUT) { | |
710 | pr_err("%s: %s: CDC calibration was not completed\n", | |
711 | mmc_hostname(host->mmc), __func__); | |
712 | goto out; | |
713 | } | |
714 | ||
715 | ret = readl_relaxed(host->ioaddr + CORE_CSR_CDC_STATUS0) | |
716 | & CORE_CDC_ERROR_CODE_MASK; | |
717 | if (ret) { | |
718 | pr_err("%s: %s: CDC error code %d\n", | |
719 | mmc_hostname(host->mmc), __func__, ret); | |
720 | ret = -EINVAL; | |
721 | goto out; | |
722 | } | |
723 | ||
724 | config = readl_relaxed(host->ioaddr + CORE_DDR_200_CFG); | |
725 | config |= CORE_START_CDC_TRAFFIC; | |
726 | writel_relaxed(config, host->ioaddr + CORE_DDR_200_CFG); | |
727 | out: | |
728 | pr_debug("%s: %s: Exit, ret %d\n", mmc_hostname(host->mmc), | |
729 | __func__, ret); | |
730 | return ret; | |
731 | } | |
732 | ||
02e4293d RH |
733 | static int sdhci_msm_cm_dll_sdc4_calibration(struct sdhci_host *host) |
734 | { | |
735 | u32 dll_status, config; | |
736 | int ret; | |
737 | ||
738 | pr_debug("%s: %s: Enter\n", mmc_hostname(host->mmc), __func__); | |
739 | ||
740 | /* | |
741 | * Currently the CORE_DDR_CONFIG register defaults to desired | |
742 | * configuration on reset. Currently reprogramming the power on | |
743 | * reset (POR) value in case it might have been modified by | |
744 | * bootloaders. In the future, if this changes, then the desired | |
745 | * values will need to be programmed appropriately. | |
746 | */ | |
747 | writel_relaxed(DDR_CONFIG_POR_VAL, host->ioaddr + CORE_DDR_CONFIG); | |
748 | ||
749 | config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG_2); | |
750 | config |= CORE_DDR_CAL_EN; | |
751 | writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG_2); | |
752 | ||
753 | ret = readl_relaxed_poll_timeout(host->ioaddr + CORE_DLL_STATUS, | |
754 | dll_status, | |
755 | (dll_status & CORE_DDR_DLL_LOCK), | |
756 | 10, 1000); | |
757 | ||
758 | if (ret == -ETIMEDOUT) { | |
759 | pr_err("%s: %s: CM_DLL_SDC4 calibration was not completed\n", | |
760 | mmc_hostname(host->mmc), __func__); | |
761 | goto out; | |
762 | } | |
763 | ||
764 | config = readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC3); | |
765 | config |= CORE_PWRSAVE_DLL; | |
766 | writel_relaxed(config, host->ioaddr + CORE_VENDOR_SPEC3); | |
767 | ||
768 | /* | |
769 | * Drain writebuffer to ensure above DLL calibration | |
770 | * and PWRSAVE DLL is enabled. | |
771 | */ | |
772 | wmb(); | |
773 | out: | |
774 | pr_debug("%s: %s: Exit, ret %d\n", mmc_hostname(host->mmc), | |
775 | __func__, ret); | |
776 | return ret; | |
777 | } | |
778 | ||
779 | static int sdhci_msm_hs400_dll_calibration(struct sdhci_host *host) | |
780 | { | |
781 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
782 | struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host); | |
783 | int ret; | |
784 | u32 config; | |
785 | ||
786 | pr_debug("%s: %s: Enter\n", mmc_hostname(host->mmc), __func__); | |
787 | ||
788 | /* | |
789 | * Retuning in HS400 (DDR mode) will fail, just reset the | |
790 | * tuning block and restore the saved tuning phase. | |
791 | */ | |
792 | ret = msm_init_cm_dll(host); | |
793 | if (ret) | |
794 | goto out; | |
795 | ||
796 | /* Set the selected phase in delay line hw block */ | |
797 | ret = msm_config_cm_dll_phase(host, msm_host->saved_tuning_phase); | |
798 | if (ret) | |
799 | goto out; | |
800 | ||
801 | config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG); | |
802 | config |= CORE_CMD_DAT_TRACK_SEL; | |
803 | writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG); | |
804 | if (msm_host->use_cdclp533) | |
805 | ret = sdhci_msm_cdclp533_calibration(host); | |
806 | else | |
807 | ret = sdhci_msm_cm_dll_sdc4_calibration(host); | |
808 | out: | |
809 | pr_debug("%s: %s: Exit, ret %d\n", mmc_hostname(host->mmc), | |
810 | __func__, ret); | |
811 | return ret; | |
812 | } | |
813 | ||
415b5a75 GD |
814 | static int sdhci_msm_execute_tuning(struct sdhci_host *host, u32 opcode) |
815 | { | |
816 | int tuning_seq_cnt = 3; | |
33d73935 | 817 | u8 phase, tuned_phases[16], tuned_phase_cnt = 0; |
415b5a75 GD |
818 | int rc; |
819 | struct mmc_host *mmc = host->mmc; | |
820 | struct mmc_ios ios = host->mmc->ios; | |
abf270e5 RH |
821 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
822 | struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host); | |
415b5a75 GD |
823 | |
824 | /* | |
825 | * Tuning is required for SDR104, HS200 and HS400 cards and | |
826 | * if clock frequency is greater than 100MHz in these modes. | |
827 | */ | |
ff06ce41 VG |
828 | if (host->clock <= CORE_FREQ_100MHZ || |
829 | !(ios.timing == MMC_TIMING_MMC_HS400 || | |
830 | ios.timing == MMC_TIMING_MMC_HS200 || | |
831 | ios.timing == MMC_TIMING_UHS_SDR104)) | |
415b5a75 GD |
832 | return 0; |
833 | ||
415b5a75 GD |
834 | retry: |
835 | /* First of all reset the tuning block */ | |
836 | rc = msm_init_cm_dll(host); | |
837 | if (rc) | |
33d73935 | 838 | return rc; |
415b5a75 GD |
839 | |
840 | phase = 0; | |
841 | do { | |
415b5a75 GD |
842 | /* Set the phase in delay line hw block */ |
843 | rc = msm_config_cm_dll_phase(host, phase); | |
844 | if (rc) | |
33d73935 | 845 | return rc; |
415b5a75 | 846 | |
abf270e5 | 847 | msm_host->saved_tuning_phase = phase; |
9979dbe5 | 848 | rc = mmc_send_tuning(mmc, opcode, NULL); |
33d73935 | 849 | if (!rc) { |
415b5a75 GD |
850 | /* Tuning is successful at this tuning point */ |
851 | tuned_phases[tuned_phase_cnt++] = phase; | |
852 | dev_dbg(mmc_dev(mmc), "%s: Found good phase = %d\n", | |
853 | mmc_hostname(mmc), phase); | |
854 | } | |
855 | } while (++phase < ARRAY_SIZE(tuned_phases)); | |
856 | ||
857 | if (tuned_phase_cnt) { | |
858 | rc = msm_find_most_appropriate_phase(host, tuned_phases, | |
859 | tuned_phase_cnt); | |
860 | if (rc < 0) | |
33d73935 | 861 | return rc; |
415b5a75 GD |
862 | else |
863 | phase = rc; | |
864 | ||
865 | /* | |
866 | * Finally set the selected phase in delay | |
867 | * line hw block. | |
868 | */ | |
869 | rc = msm_config_cm_dll_phase(host, phase); | |
870 | if (rc) | |
33d73935 | 871 | return rc; |
415b5a75 GD |
872 | dev_dbg(mmc_dev(mmc), "%s: Setting the tuning phase to %d\n", |
873 | mmc_hostname(mmc), phase); | |
874 | } else { | |
875 | if (--tuning_seq_cnt) | |
876 | goto retry; | |
877 | /* Tuning failed */ | |
878 | dev_dbg(mmc_dev(mmc), "%s: No tuning point found\n", | |
879 | mmc_hostname(mmc)); | |
880 | rc = -EIO; | |
881 | } | |
882 | ||
ff06ce41 VG |
883 | if (!rc) |
884 | msm_host->tuning_done = true; | |
415b5a75 GD |
885 | return rc; |
886 | } | |
887 | ||
db9bd163 RH |
888 | /* |
889 | * sdhci_msm_hs400 - Calibrate the DLL for HS400 bus speed mode operation. | |
890 | * DLL operation is only needed for clock > 100MHz. For clock <= 100MHz | |
891 | * fixed feedback clock is used. | |
892 | */ | |
893 | static void sdhci_msm_hs400(struct sdhci_host *host, struct mmc_ios *ios) | |
894 | { | |
895 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
896 | struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host); | |
897 | int ret; | |
898 | ||
899 | if (host->clock > CORE_FREQ_100MHZ && | |
900 | msm_host->tuning_done && !msm_host->calibration_done) { | |
901 | ret = sdhci_msm_hs400_dll_calibration(host); | |
902 | if (!ret) | |
903 | msm_host->calibration_done = true; | |
904 | else | |
905 | pr_err("%s: Failed to calibrate DLL for hs400 mode (%d)\n", | |
906 | mmc_hostname(host->mmc), ret); | |
907 | } | |
908 | } | |
909 | ||
ee320674 RH |
910 | static void sdhci_msm_set_uhs_signaling(struct sdhci_host *host, |
911 | unsigned int uhs) | |
912 | { | |
913 | struct mmc_host *mmc = host->mmc; | |
ff06ce41 VG |
914 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
915 | struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host); | |
ee320674 | 916 | u16 ctrl_2; |
ff06ce41 | 917 | u32 config; |
ee320674 RH |
918 | |
919 | ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); | |
920 | /* Select Bus Speed Mode for host */ | |
921 | ctrl_2 &= ~SDHCI_CTRL_UHS_MASK; | |
922 | switch (uhs) { | |
923 | case MMC_TIMING_UHS_SDR12: | |
924 | ctrl_2 |= SDHCI_CTRL_UHS_SDR12; | |
925 | break; | |
926 | case MMC_TIMING_UHS_SDR25: | |
927 | ctrl_2 |= SDHCI_CTRL_UHS_SDR25; | |
928 | break; | |
929 | case MMC_TIMING_UHS_SDR50: | |
930 | ctrl_2 |= SDHCI_CTRL_UHS_SDR50; | |
931 | break; | |
ff06ce41 | 932 | case MMC_TIMING_MMC_HS400: |
ee320674 RH |
933 | case MMC_TIMING_MMC_HS200: |
934 | case MMC_TIMING_UHS_SDR104: | |
935 | ctrl_2 |= SDHCI_CTRL_UHS_SDR104; | |
936 | break; | |
937 | case MMC_TIMING_UHS_DDR50: | |
938 | case MMC_TIMING_MMC_DDR52: | |
939 | ctrl_2 |= SDHCI_CTRL_UHS_DDR50; | |
940 | break; | |
941 | } | |
942 | ||
943 | /* | |
944 | * When clock frequency is less than 100MHz, the feedback clock must be | |
945 | * provided and DLL must not be used so that tuning can be skipped. To | |
946 | * provide feedback clock, the mode selection can be any value less | |
947 | * than 3'b011 in bits [2:0] of HOST CONTROL2 register. | |
948 | */ | |
ff06ce41 VG |
949 | if (host->clock <= CORE_FREQ_100MHZ) { |
950 | if (uhs == MMC_TIMING_MMC_HS400 || | |
951 | uhs == MMC_TIMING_MMC_HS200 || | |
952 | uhs == MMC_TIMING_UHS_SDR104) | |
953 | ctrl_2 &= ~SDHCI_CTRL_UHS_MASK; | |
954 | /* | |
955 | * DLL is not required for clock <= 100MHz | |
956 | * Thus, make sure DLL it is disabled when not required | |
957 | */ | |
958 | config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG); | |
959 | config |= CORE_DLL_RST; | |
960 | writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG); | |
961 | ||
962 | config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG); | |
963 | config |= CORE_DLL_PDN; | |
964 | writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG); | |
965 | ||
966 | /* | |
967 | * The DLL needs to be restored and CDCLP533 recalibrated | |
968 | * when the clock frequency is set back to 400MHz. | |
969 | */ | |
970 | msm_host->calibration_done = false; | |
971 | } | |
ee320674 RH |
972 | |
973 | dev_dbg(mmc_dev(mmc), "%s: clock=%u uhs=%u ctrl_2=0x%x\n", | |
974 | mmc_hostname(host->mmc), host->clock, uhs, ctrl_2); | |
975 | sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); | |
cc392c58 RH |
976 | |
977 | spin_unlock_irq(&host->lock); | |
db9bd163 RH |
978 | |
979 | if (mmc->ios.timing == MMC_TIMING_MMC_HS400) | |
980 | sdhci_msm_hs400(host, &mmc->ios); | |
981 | ||
cc392c58 | 982 | spin_lock_irq(&host->lock); |
ee320674 RH |
983 | } |
984 | ||
ad81d387 GD |
985 | static void sdhci_msm_voltage_switch(struct sdhci_host *host) |
986 | { | |
987 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
988 | struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host); | |
989 | u32 irq_status, irq_ack = 0; | |
990 | ||
991 | irq_status = readl_relaxed(msm_host->core_mem + CORE_PWRCTL_STATUS); | |
992 | irq_status &= INT_MASK; | |
993 | ||
994 | writel_relaxed(irq_status, msm_host->core_mem + CORE_PWRCTL_CLEAR); | |
995 | ||
996 | if (irq_status & (CORE_PWRCTL_BUS_ON | CORE_PWRCTL_BUS_OFF)) | |
997 | irq_ack |= CORE_PWRCTL_BUS_SUCCESS; | |
998 | if (irq_status & (CORE_PWRCTL_IO_LOW | CORE_PWRCTL_IO_HIGH)) | |
999 | irq_ack |= CORE_PWRCTL_IO_SUCCESS; | |
1000 | ||
1001 | /* | |
1002 | * The driver has to acknowledge the interrupt, switch voltages and | |
1003 | * report back if it succeded or not to this register. The voltage | |
1004 | * switches are handled by the sdhci core, so just report success. | |
1005 | */ | |
1006 | writel_relaxed(irq_ack, msm_host->core_mem + CORE_PWRCTL_CTL); | |
1007 | } | |
1008 | ||
1009 | static irqreturn_t sdhci_msm_pwr_irq(int irq, void *data) | |
1010 | { | |
1011 | struct sdhci_host *host = (struct sdhci_host *)data; | |
1012 | ||
1013 | sdhci_msm_voltage_switch(host); | |
1014 | ||
1015 | return IRQ_HANDLED; | |
1016 | } | |
1017 | ||
80031bde RH |
1018 | static unsigned int sdhci_msm_get_max_clock(struct sdhci_host *host) |
1019 | { | |
1020 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
1021 | struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host); | |
1022 | ||
1023 | return clk_round_rate(msm_host->clk, ULONG_MAX); | |
1024 | } | |
1025 | ||
1026 | static unsigned int sdhci_msm_get_min_clock(struct sdhci_host *host) | |
1027 | { | |
1028 | return SDHCI_MSM_MIN_CLOCK; | |
1029 | } | |
1030 | ||
edc609fd RH |
1031 | /** |
1032 | * __sdhci_msm_set_clock - sdhci_msm clock control. | |
1033 | * | |
1034 | * Description: | |
1035 | * MSM controller does not use internal divider and | |
1036 | * instead directly control the GCC clock as per | |
1037 | * HW recommendation. | |
1038 | **/ | |
1039 | void __sdhci_msm_set_clock(struct sdhci_host *host, unsigned int clock) | |
1040 | { | |
1041 | u16 clk; | |
1042 | /* | |
1043 | * Keep actual_clock as zero - | |
1044 | * - since there is no divider used so no need of having actual_clock. | |
1045 | * - MSM controller uses SDCLK for data timeout calculation. If | |
1046 | * actual_clock is zero, host->clock is taken for calculation. | |
1047 | */ | |
1048 | host->mmc->actual_clock = 0; | |
1049 | ||
1050 | sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL); | |
1051 | ||
1052 | if (clock == 0) | |
1053 | return; | |
1054 | ||
1055 | /* | |
1056 | * MSM controller do not use clock divider. | |
1057 | * Thus read SDHCI_CLOCK_CONTROL and only enable | |
1058 | * clock with no divider value programmed. | |
1059 | */ | |
1060 | clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); | |
1061 | sdhci_enable_clk(host, clk); | |
1062 | } | |
1063 | ||
1064 | /* sdhci_msm_set_clock - Called with (host->lock) spinlock held. */ | |
1065 | static void sdhci_msm_set_clock(struct sdhci_host *host, unsigned int clock) | |
1066 | { | |
1067 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
1068 | struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host); | |
edc609fd RH |
1069 | |
1070 | if (!clock) { | |
1071 | msm_host->clk_rate = clock; | |
1072 | goto out; | |
1073 | } | |
1074 | ||
1075 | spin_unlock_irq(&host->lock); | |
ff06ce41 | 1076 | |
b54aaa8a | 1077 | sdhci_msm_hc_select_mode(host); |
edc609fd | 1078 | |
0fb8a3d4 | 1079 | msm_set_clock_rate_for_bus_mode(host, clock); |
edc609fd | 1080 | |
edc609fd RH |
1081 | spin_lock_irq(&host->lock); |
1082 | out: | |
1083 | __sdhci_msm_set_clock(host, clock); | |
1084 | } | |
1085 | ||
0eb0d9f4 GD |
1086 | static const struct of_device_id sdhci_msm_dt_match[] = { |
1087 | { .compatible = "qcom,sdhci-msm-v4" }, | |
1088 | {}, | |
1089 | }; | |
1090 | ||
1091 | MODULE_DEVICE_TABLE(of, sdhci_msm_dt_match); | |
1092 | ||
a50396a4 | 1093 | static const struct sdhci_ops sdhci_msm_ops = { |
0eb0d9f4 | 1094 | .platform_execute_tuning = sdhci_msm_execute_tuning, |
ed1761d7 | 1095 | .reset = sdhci_reset, |
edc609fd | 1096 | .set_clock = sdhci_msm_set_clock, |
80031bde RH |
1097 | .get_min_clock = sdhci_msm_get_min_clock, |
1098 | .get_max_clock = sdhci_msm_get_max_clock, | |
ed1761d7 | 1099 | .set_bus_width = sdhci_set_bus_width, |
ee320674 | 1100 | .set_uhs_signaling = sdhci_msm_set_uhs_signaling, |
ad81d387 | 1101 | .voltage_switch = sdhci_msm_voltage_switch, |
0eb0d9f4 GD |
1102 | }; |
1103 | ||
a50396a4 JZ |
1104 | static const struct sdhci_pltfm_data sdhci_msm_pdata = { |
1105 | .quirks = SDHCI_QUIRK_BROKEN_CARD_DETECTION | | |
9718f84b | 1106 | SDHCI_QUIRK_NO_CARD_NO_RESET | |
a0e31428 RH |
1107 | SDHCI_QUIRK_SINGLE_POWER_WRITE | |
1108 | SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, | |
1109 | .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, | |
a50396a4 JZ |
1110 | .ops = &sdhci_msm_ops, |
1111 | }; | |
1112 | ||
0eb0d9f4 GD |
1113 | static int sdhci_msm_probe(struct platform_device *pdev) |
1114 | { | |
1115 | struct sdhci_host *host; | |
1116 | struct sdhci_pltfm_host *pltfm_host; | |
1117 | struct sdhci_msm_host *msm_host; | |
1118 | struct resource *core_memres; | |
1119 | int ret; | |
3a3ad3e9 | 1120 | u16 host_version, core_minor; |
29301f40 | 1121 | u32 core_version, config; |
3a3ad3e9 | 1122 | u8 core_major; |
0eb0d9f4 | 1123 | |
6f699531 | 1124 | host = sdhci_pltfm_init(pdev, &sdhci_msm_pdata, sizeof(*msm_host)); |
0eb0d9f4 GD |
1125 | if (IS_ERR(host)) |
1126 | return PTR_ERR(host); | |
1127 | ||
1128 | pltfm_host = sdhci_priv(host); | |
6f699531 | 1129 | msm_host = sdhci_pltfm_priv(pltfm_host); |
0eb0d9f4 GD |
1130 | msm_host->mmc = host->mmc; |
1131 | msm_host->pdev = pdev; | |
1132 | ||
1133 | ret = mmc_of_parse(host->mmc); | |
1134 | if (ret) | |
1135 | goto pltfm_free; | |
1136 | ||
1137 | sdhci_get_of_property(pdev); | |
1138 | ||
abf270e5 RH |
1139 | msm_host->saved_tuning_phase = INVALID_TUNING_PHASE; |
1140 | ||
0eb0d9f4 GD |
1141 | /* Setup SDCC bus voter clock. */ |
1142 | msm_host->bus_clk = devm_clk_get(&pdev->dev, "bus"); | |
1143 | if (!IS_ERR(msm_host->bus_clk)) { | |
1144 | /* Vote for max. clk rate for max. performance */ | |
1145 | ret = clk_set_rate(msm_host->bus_clk, INT_MAX); | |
1146 | if (ret) | |
1147 | goto pltfm_free; | |
1148 | ret = clk_prepare_enable(msm_host->bus_clk); | |
1149 | if (ret) | |
1150 | goto pltfm_free; | |
1151 | } | |
1152 | ||
1153 | /* Setup main peripheral bus clock */ | |
1154 | msm_host->pclk = devm_clk_get(&pdev->dev, "iface"); | |
1155 | if (IS_ERR(msm_host->pclk)) { | |
1156 | ret = PTR_ERR(msm_host->pclk); | |
2801b95e | 1157 | dev_err(&pdev->dev, "Peripheral clk setup failed (%d)\n", ret); |
0eb0d9f4 GD |
1158 | goto bus_clk_disable; |
1159 | } | |
1160 | ||
1161 | ret = clk_prepare_enable(msm_host->pclk); | |
1162 | if (ret) | |
1163 | goto bus_clk_disable; | |
1164 | ||
1165 | /* Setup SDC MMC clock */ | |
1166 | msm_host->clk = devm_clk_get(&pdev->dev, "core"); | |
1167 | if (IS_ERR(msm_host->clk)) { | |
1168 | ret = PTR_ERR(msm_host->clk); | |
1169 | dev_err(&pdev->dev, "SDC MMC clk setup failed (%d)\n", ret); | |
1170 | goto pclk_disable; | |
1171 | } | |
1172 | ||
83736352 VG |
1173 | /* |
1174 | * xo clock is needed for FLL feature of cm_dll. | |
1175 | * In case if xo clock is not mentioned in DT, warn and proceed. | |
1176 | */ | |
1177 | msm_host->xo_clk = devm_clk_get(&pdev->dev, "xo"); | |
1178 | if (IS_ERR(msm_host->xo_clk)) { | |
1179 | ret = PTR_ERR(msm_host->xo_clk); | |
1180 | dev_warn(&pdev->dev, "TCXO clk not present (%d)\n", ret); | |
1181 | } | |
1182 | ||
951b8c87 II |
1183 | /* Vote for maximum clock rate for maximum performance */ |
1184 | ret = clk_set_rate(msm_host->clk, INT_MAX); | |
1185 | if (ret) | |
1186 | dev_warn(&pdev->dev, "core clock boost failed\n"); | |
1187 | ||
0eb0d9f4 GD |
1188 | ret = clk_prepare_enable(msm_host->clk); |
1189 | if (ret) | |
1190 | goto pclk_disable; | |
1191 | ||
1192 | core_memres = platform_get_resource(pdev, IORESOURCE_MEM, 1); | |
1193 | msm_host->core_mem = devm_ioremap_resource(&pdev->dev, core_memres); | |
1194 | ||
1195 | if (IS_ERR(msm_host->core_mem)) { | |
1196 | dev_err(&pdev->dev, "Failed to remap registers\n"); | |
1197 | ret = PTR_ERR(msm_host->core_mem); | |
1198 | goto clk_disable; | |
1199 | } | |
1200 | ||
5574ddcc VG |
1201 | /* Reset the vendor spec register to power on reset state */ |
1202 | writel_relaxed(CORE_VENDOR_SPEC_POR_VAL, | |
1203 | host->ioaddr + CORE_VENDOR_SPEC); | |
0eb0d9f4 GD |
1204 | |
1205 | /* Set HC_MODE_EN bit in HC_MODE register */ | |
1206 | writel_relaxed(HC_MODE_EN, (msm_host->core_mem + CORE_HC_MODE)); | |
1207 | ||
ff06ce41 VG |
1208 | config = readl_relaxed(msm_host->core_mem + CORE_HC_MODE); |
1209 | config |= FF_CLK_SW_RST_DIS; | |
1210 | writel_relaxed(config, msm_host->core_mem + CORE_HC_MODE); | |
1211 | ||
0eb0d9f4 GD |
1212 | host_version = readw_relaxed((host->ioaddr + SDHCI_HOST_VERSION)); |
1213 | dev_dbg(&pdev->dev, "Host Version: 0x%x Vendor Version 0x%x\n", | |
1214 | host_version, ((host_version & SDHCI_VENDOR_VER_MASK) >> | |
1215 | SDHCI_VENDOR_VER_SHIFT)); | |
1216 | ||
3a3ad3e9 GD |
1217 | core_version = readl_relaxed(msm_host->core_mem + CORE_MCI_VERSION); |
1218 | core_major = (core_version & CORE_VERSION_MAJOR_MASK) >> | |
1219 | CORE_VERSION_MAJOR_SHIFT; | |
1220 | core_minor = core_version & CORE_VERSION_MINOR_MASK; | |
1221 | dev_dbg(&pdev->dev, "MCI Version: 0x%08x, major: 0x%04x, minor: 0x%02x\n", | |
1222 | core_version, core_major, core_minor); | |
1223 | ||
83736352 VG |
1224 | if (core_major == 1 && core_minor >= 0x42) |
1225 | msm_host->use_14lpp_dll_reset = true; | |
1226 | ||
02e4293d RH |
1227 | /* |
1228 | * SDCC 5 controller with major version 1, minor version 0x34 and later | |
1229 | * with HS 400 mode support will use CM DLL instead of CDC LP 533 DLL. | |
1230 | */ | |
1231 | if (core_major == 1 && core_minor < 0x34) | |
1232 | msm_host->use_cdclp533 = true; | |
1233 | ||
3a3ad3e9 GD |
1234 | /* |
1235 | * Support for some capabilities is not advertised by newer | |
1236 | * controller versions and must be explicitly enabled. | |
1237 | */ | |
1238 | if (core_major >= 1 && core_minor != 0x11 && core_minor != 0x12) { | |
29301f40 RH |
1239 | config = readl_relaxed(host->ioaddr + SDHCI_CAPABILITIES); |
1240 | config |= SDHCI_CAN_VDD_300 | SDHCI_CAN_DO_8BIT; | |
1241 | writel_relaxed(config, host->ioaddr + | |
3a3ad3e9 GD |
1242 | CORE_VENDOR_SPEC_CAPABILITIES0); |
1243 | } | |
1244 | ||
ad81d387 GD |
1245 | /* Setup IRQ for handling power/voltage tasks with PMIC */ |
1246 | msm_host->pwr_irq = platform_get_irq_byname(pdev, "pwr_irq"); | |
1247 | if (msm_host->pwr_irq < 0) { | |
1248 | dev_err(&pdev->dev, "Get pwr_irq failed (%d)\n", | |
1249 | msm_host->pwr_irq); | |
d1f63f0c | 1250 | ret = msm_host->pwr_irq; |
ad81d387 GD |
1251 | goto clk_disable; |
1252 | } | |
1253 | ||
1254 | ret = devm_request_threaded_irq(&pdev->dev, msm_host->pwr_irq, NULL, | |
1255 | sdhci_msm_pwr_irq, IRQF_ONESHOT, | |
1256 | dev_name(&pdev->dev), host); | |
1257 | if (ret) { | |
1258 | dev_err(&pdev->dev, "Request IRQ failed (%d)\n", ret); | |
1259 | goto clk_disable; | |
1260 | } | |
1261 | ||
67e6db11 PG |
1262 | pm_runtime_get_noresume(&pdev->dev); |
1263 | pm_runtime_set_active(&pdev->dev); | |
1264 | pm_runtime_enable(&pdev->dev); | |
1265 | pm_runtime_set_autosuspend_delay(&pdev->dev, | |
1266 | MSM_MMC_AUTOSUSPEND_DELAY_MS); | |
1267 | pm_runtime_use_autosuspend(&pdev->dev); | |
1268 | ||
0eb0d9f4 GD |
1269 | ret = sdhci_add_host(host); |
1270 | if (ret) | |
67e6db11 PG |
1271 | goto pm_runtime_disable; |
1272 | ||
1273 | pm_runtime_mark_last_busy(&pdev->dev); | |
1274 | pm_runtime_put_autosuspend(&pdev->dev); | |
0eb0d9f4 GD |
1275 | |
1276 | return 0; | |
1277 | ||
67e6db11 PG |
1278 | pm_runtime_disable: |
1279 | pm_runtime_disable(&pdev->dev); | |
1280 | pm_runtime_set_suspended(&pdev->dev); | |
1281 | pm_runtime_put_noidle(&pdev->dev); | |
0eb0d9f4 GD |
1282 | clk_disable: |
1283 | clk_disable_unprepare(msm_host->clk); | |
1284 | pclk_disable: | |
1285 | clk_disable_unprepare(msm_host->pclk); | |
1286 | bus_clk_disable: | |
1287 | if (!IS_ERR(msm_host->bus_clk)) | |
1288 | clk_disable_unprepare(msm_host->bus_clk); | |
1289 | pltfm_free: | |
1290 | sdhci_pltfm_free(pdev); | |
1291 | return ret; | |
1292 | } | |
1293 | ||
1294 | static int sdhci_msm_remove(struct platform_device *pdev) | |
1295 | { | |
1296 | struct sdhci_host *host = platform_get_drvdata(pdev); | |
1297 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
6f699531 | 1298 | struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host); |
0eb0d9f4 GD |
1299 | int dead = (readl_relaxed(host->ioaddr + SDHCI_INT_STATUS) == |
1300 | 0xffffffff); | |
1301 | ||
1302 | sdhci_remove_host(host, dead); | |
67e6db11 PG |
1303 | |
1304 | pm_runtime_get_sync(&pdev->dev); | |
1305 | pm_runtime_disable(&pdev->dev); | |
1306 | pm_runtime_put_noidle(&pdev->dev); | |
1307 | ||
0eb0d9f4 GD |
1308 | clk_disable_unprepare(msm_host->clk); |
1309 | clk_disable_unprepare(msm_host->pclk); | |
1310 | if (!IS_ERR(msm_host->bus_clk)) | |
1311 | clk_disable_unprepare(msm_host->bus_clk); | |
6f699531 | 1312 | sdhci_pltfm_free(pdev); |
0eb0d9f4 GD |
1313 | return 0; |
1314 | } | |
1315 | ||
67e6db11 PG |
1316 | #ifdef CONFIG_PM |
1317 | static int sdhci_msm_runtime_suspend(struct device *dev) | |
1318 | { | |
1319 | struct sdhci_host *host = dev_get_drvdata(dev); | |
1320 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
1321 | struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host); | |
1322 | ||
1323 | clk_disable_unprepare(msm_host->clk); | |
1324 | clk_disable_unprepare(msm_host->pclk); | |
1325 | ||
1326 | return 0; | |
1327 | } | |
1328 | ||
1329 | static int sdhci_msm_runtime_resume(struct device *dev) | |
1330 | { | |
1331 | struct sdhci_host *host = dev_get_drvdata(dev); | |
1332 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
1333 | struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host); | |
1334 | int ret; | |
1335 | ||
1336 | ret = clk_prepare_enable(msm_host->clk); | |
1337 | if (ret) { | |
1338 | dev_err(dev, "clk_enable failed for core_clk: %d\n", ret); | |
1339 | return ret; | |
1340 | } | |
1341 | ret = clk_prepare_enable(msm_host->pclk); | |
1342 | if (ret) { | |
1343 | dev_err(dev, "clk_enable failed for iface_clk: %d\n", ret); | |
1344 | clk_disable_unprepare(msm_host->clk); | |
1345 | return ret; | |
1346 | } | |
1347 | ||
1348 | return 0; | |
1349 | } | |
1350 | #endif | |
1351 | ||
1352 | static const struct dev_pm_ops sdhci_msm_pm_ops = { | |
1353 | SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, | |
1354 | pm_runtime_force_resume) | |
1355 | SET_RUNTIME_PM_OPS(sdhci_msm_runtime_suspend, | |
1356 | sdhci_msm_runtime_resume, | |
1357 | NULL) | |
1358 | }; | |
1359 | ||
0eb0d9f4 GD |
1360 | static struct platform_driver sdhci_msm_driver = { |
1361 | .probe = sdhci_msm_probe, | |
1362 | .remove = sdhci_msm_remove, | |
1363 | .driver = { | |
1364 | .name = "sdhci_msm", | |
0eb0d9f4 | 1365 | .of_match_table = sdhci_msm_dt_match, |
67e6db11 | 1366 | .pm = &sdhci_msm_pm_ops, |
0eb0d9f4 GD |
1367 | }, |
1368 | }; | |
1369 | ||
1370 | module_platform_driver(sdhci_msm_driver); | |
1371 | ||
1372 | MODULE_DESCRIPTION("Qualcomm Secure Digital Host Controller Interface driver"); | |
1373 | MODULE_LICENSE("GPL v2"); |