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mmc: sdhci-msm: Add calibration tuning for CDCLP533 circuit
[mirror_ubuntu-artful-kernel.git] / drivers / mmc / host / sdhci-msm.c
CommitLineData
0eb0d9f4
GD		 1/*
2 * drivers/mmc/host/sdhci-msm.c - Qualcomm SDHCI Platform driver
3 *
4 * Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 and
8 * only version 2 as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 */
16
17#include <linux/module.h>
18#include <linux/of_device.h>
0eb0d9f4 19#include <linux/delay.h>
415b5a75 20#include <linux/mmc/mmc.h>
67e6db11 21#include <linux/pm_runtime.h>
415b5a75 22#include <linux/slab.h>
cc392c58 23#include <linux/iopoll.h>
0eb0d9f4
GD		 24
25#include "sdhci-pltfm.h"
26
3a3ad3e9
GD		 27#define CORE_MCI_VERSION 0x50
28#define CORE_VERSION_MAJOR_SHIFT 28
29#define CORE_VERSION_MAJOR_MASK (0xf << CORE_VERSION_MAJOR_SHIFT)
30#define CORE_VERSION_MINOR_MASK 0xff
31
0eb0d9f4
GD		 32#define CORE_HC_MODE 0x78
33#define HC_MODE_EN 0x1
34#define CORE_POWER 0x0
35#define CORE_SW_RST BIT(7)
ff06ce41 36#define FF_CLK_SW_RST_DIS BIT(13)
0eb0d9f4 37
ad81d387
GD		 38#define CORE_PWRCTL_STATUS 0xdc
39#define CORE_PWRCTL_MASK 0xe0
40#define CORE_PWRCTL_CLEAR 0xe4
41#define CORE_PWRCTL_CTL 0xe8
42#define CORE_PWRCTL_BUS_OFF BIT(0)
43#define CORE_PWRCTL_BUS_ON BIT(1)
44#define CORE_PWRCTL_IO_LOW BIT(2)
45#define CORE_PWRCTL_IO_HIGH BIT(3)
46#define CORE_PWRCTL_BUS_SUCCESS BIT(0)
47#define CORE_PWRCTL_IO_SUCCESS BIT(2)
48#define REQ_BUS_OFF BIT(0)
49#define REQ_BUS_ON BIT(1)
50#define REQ_IO_LOW BIT(2)
51#define REQ_IO_HIGH BIT(3)
52#define INT_MASK 0xf
415b5a75
GD		 53#define MAX_PHASES 16
54#define CORE_DLL_LOCK BIT(7)
55#define CORE_DLL_EN BIT(16)
56#define CORE_CDR_EN BIT(17)
57#define CORE_CK_OUT_EN BIT(18)
58#define CORE_CDR_EXT_EN BIT(19)
59#define CORE_DLL_PDN BIT(29)
60#define CORE_DLL_RST BIT(30)
61#define CORE_DLL_CONFIG 0x100
cc392c58 62#define CORE_CMD_DAT_TRACK_SEL BIT(0)
415b5a75
GD		 63#define CORE_DLL_STATUS 0x108
64
83736352
VG		 65#define CORE_DLL_CONFIG_2 0x1b4
66#define CORE_FLL_CYCLE_CNT BIT(18)
67#define CORE_DLL_CLOCK_DISABLE BIT(21)
68
415b5a75
GD		 69#define CORE_VENDOR_SPEC 0x10c
70#define CORE_CLK_PWRSAVE BIT(1)
ff06ce41
VG		 71#define CORE_HC_MCLK_SEL_DFLT (2 << 8)
72#define CORE_HC_MCLK_SEL_HS400 (3 << 8)
73#define CORE_HC_MCLK_SEL_MASK (3 << 8)
74#define CORE_HC_SELECT_IN_EN BIT(18)
75#define CORE_HC_SELECT_IN_HS400 (6 << 19)
76#define CORE_HC_SELECT_IN_MASK (7 << 19)
415b5a75 77
cc392c58
RH		 78#define CORE_CSR_CDC_CTLR_CFG0 0x130
79#define CORE_SW_TRIG_FULL_CALIB BIT(16)
80#define CORE_HW_AUTOCAL_ENA BIT(17)
81
82#define CORE_CSR_CDC_CTLR_CFG1 0x134
83#define CORE_CSR_CDC_CAL_TIMER_CFG0 0x138
84#define CORE_TIMER_ENA BIT(16)
85
86#define CORE_CSR_CDC_CAL_TIMER_CFG1 0x13C
87#define CORE_CSR_CDC_REFCOUNT_CFG 0x140
88#define CORE_CSR_CDC_COARSE_CAL_CFG 0x144
89#define CORE_CDC_OFFSET_CFG 0x14C
90#define CORE_CSR_CDC_DELAY_CFG 0x150
91#define CORE_CDC_SLAVE_DDA_CFG 0x160
92#define CORE_CSR_CDC_STATUS0 0x164
93#define CORE_CALIBRATION_DONE BIT(0)
94
95#define CORE_CDC_ERROR_CODE_MASK 0x7000000
96
97#define CORE_CSR_CDC_GEN_CFG 0x178
98#define CORE_CDC_SWITCH_BYPASS_OFF BIT(0)
99#define CORE_CDC_SWITCH_RC_EN BIT(1)
100
101#define CORE_DDR_200_CFG 0x184
102#define CORE_CDC_T4_DLY_SEL BIT(0)
103#define CORE_START_CDC_TRAFFIC BIT(6)
104
3a3ad3e9
GD		 105#define CORE_VENDOR_SPEC_CAPABILITIES0 0x11c
106
abf270e5 107#define INVALID_TUNING_PHASE -1
80031bde 108#define SDHCI_MSM_MIN_CLOCK 400000
ff06ce41 109#define CORE_FREQ_100MHZ (100 * 1000 * 1000)
80031bde 110
415b5a75
GD		 111#define CDR_SELEXT_SHIFT 20
112#define CDR_SELEXT_MASK (0xf << CDR_SELEXT_SHIFT)
113#define CMUX_SHIFT_PHASE_SHIFT 24
114#define CMUX_SHIFT_PHASE_MASK (7 << CMUX_SHIFT_PHASE_SHIFT)
115
67e6db11 116#define MSM_MMC_AUTOSUSPEND_DELAY_MS 50
0eb0d9f4
GD		 117struct sdhci_msm_host {
118 struct platform_device *pdev;
119 void __iomem *core_mem; /* MSM SDCC mapped address */
ad81d387 120 int pwr_irq; /* power irq */
0eb0d9f4
GD		 121 struct clk *clk; /* main SD/MMC bus clock */
122 struct clk *pclk; /* SDHC peripheral bus clock */
123 struct clk *bus_clk; /* SDHC bus voter clock */
83736352 124 struct clk *xo_clk; /* TCXO clk needed for FLL feature of cm_dll*/
edc609fd 125 unsigned long clk_rate;
0eb0d9f4 126 struct mmc_host *mmc;
83736352 127 bool use_14lpp_dll_reset;
ff06ce41
VG		 128 bool tuning_done;
129 bool calibration_done;
abf270e5 130 u8 saved_tuning_phase;
0eb0d9f4
GD		 131};
132
133/* Platform specific tuning */
415b5a75
GD		 134static inline int msm_dll_poll_ck_out_en(struct sdhci_host *host, u8 poll)
135{
136 u32 wait_cnt = 50;
137 u8 ck_out_en;
138 struct mmc_host *mmc = host->mmc;
139
140 /* Poll for CK_OUT_EN bit. max. poll time = 50us */
141 ck_out_en = !!(readl_relaxed(host->ioaddr + CORE_DLL_CONFIG) &
142 CORE_CK_OUT_EN);
143
144 while (ck_out_en != poll) {
145 if (--wait_cnt == 0) {
146 dev_err(mmc_dev(mmc), "%s: CK_OUT_EN bit is not %d\n",
147 mmc_hostname(mmc), poll);
148 return -ETIMEDOUT;
149 }
150 udelay(1);
151
152 ck_out_en = !!(readl_relaxed(host->ioaddr + CORE_DLL_CONFIG) &
153 CORE_CK_OUT_EN);
154 }
155
156 return 0;
157}
158
159static int msm_config_cm_dll_phase(struct sdhci_host *host, u8 phase)
160{
161 int rc;
162 static const u8 grey_coded_phase_table[] = {
163 0x0, 0x1, 0x3, 0x2, 0x6, 0x7, 0x5, 0x4,
164 0xc, 0xd, 0xf, 0xe, 0xa, 0xb, 0x9, 0x8
165 };
166 unsigned long flags;
167 u32 config;
168 struct mmc_host *mmc = host->mmc;
169
abf270e5
RH		 170 if (phase > 0xf)
171 return -EINVAL;
172
415b5a75
GD		 173 spin_lock_irqsave(&host->lock, flags);
174
175 config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
176 config &= ~(CORE_CDR_EN | CORE_CK_OUT_EN);
177 config |= (CORE_CDR_EXT_EN | CORE_DLL_EN);
178 writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
179
180 /* Wait until CK_OUT_EN bit of DLL_CONFIG register becomes '0' */
181 rc = msm_dll_poll_ck_out_en(host, 0);
182 if (rc)
183 goto err_out;
184
185 /*
186 * Write the selected DLL clock output phase (0 ... 15)
187 * to CDR_SELEXT bit field of DLL_CONFIG register.
188 */
189 config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
190 config &= ~CDR_SELEXT_MASK;
191 config |= grey_coded_phase_table[phase] << CDR_SELEXT_SHIFT;
192 writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
193
29301f40
RH		 194 config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
195 config |= CORE_CK_OUT_EN;
196 writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
415b5a75
GD		 197
198 /* Wait until CK_OUT_EN bit of DLL_CONFIG register becomes '1' */
199 rc = msm_dll_poll_ck_out_en(host, 1);
200 if (rc)
201 goto err_out;
202
203 config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
204 config |= CORE_CDR_EN;
205 config &= ~CORE_CDR_EXT_EN;
206 writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
207 goto out;
208
209err_out:
210 dev_err(mmc_dev(mmc), "%s: Failed to set DLL phase: %d\n",
211 mmc_hostname(mmc), phase);
212out:
213 spin_unlock_irqrestore(&host->lock, flags);
214 return rc;
215}
216
217/*
218 * Find out the greatest range of consecuitive selected
219 * DLL clock output phases that can be used as sampling
220 * setting for SD3.0 UHS-I card read operation (in SDR104
ff06ce41
VG		 221 * timing mode) or for eMMC4.5 card read operation (in
222 * HS400/HS200 timing mode).
415b5a75
GD		 223 * Select the 3/4 of the range and configure the DLL with the
224 * selected DLL clock output phase.
225 */
226
227static int msm_find_most_appropriate_phase(struct sdhci_host *host,
228 u8 *phase_table, u8 total_phases)
229{
230 int ret;
231 u8 ranges[MAX_PHASES][MAX_PHASES] = { {0}, {0} };
232 u8 phases_per_row[MAX_PHASES] = { 0 };
233 int row_index = 0, col_index = 0, selected_row_index = 0, curr_max = 0;
234 int i, cnt, phase_0_raw_index = 0, phase_15_raw_index = 0;
235 bool phase_0_found = false, phase_15_found = false;
236 struct mmc_host *mmc = host->mmc;
237
238 if (!total_phases || (total_phases > MAX_PHASES)) {
239 dev_err(mmc_dev(mmc), "%s: Invalid argument: total_phases=%d\n",
240 mmc_hostname(mmc), total_phases);
241 return -EINVAL;
242 }
243
244 for (cnt = 0; cnt < total_phases; cnt++) {
245 ranges[row_index][col_index] = phase_table[cnt];
246 phases_per_row[row_index] += 1;
247 col_index++;
248
249 if ((cnt + 1) == total_phases) {
250 continue;
251 /* check if next phase in phase_table is consecutive or not */
252 } else if ((phase_table[cnt] + 1) != phase_table[cnt + 1]) {
253 row_index++;
254 col_index = 0;
255 }
256 }
257
258 if (row_index >= MAX_PHASES)
259 return -EINVAL;
260
261 /* Check if phase-0 is present in first valid window? */
262 if (!ranges[0][0]) {
263 phase_0_found = true;
264 phase_0_raw_index = 0;
265 /* Check if cycle exist between 2 valid windows */
266 for (cnt = 1; cnt <= row_index; cnt++) {
267 if (phases_per_row[cnt]) {
268 for (i = 0; i < phases_per_row[cnt]; i++) {
269 if (ranges[cnt][i] == 15) {
270 phase_15_found = true;
271 phase_15_raw_index = cnt;
272 break;
273 }
274 }
275 }
276 }
277 }
278
279 /* If 2 valid windows form cycle then merge them as single window */
280 if (phase_0_found && phase_15_found) {
281 /* number of phases in raw where phase 0 is present */
282 u8 phases_0 = phases_per_row[phase_0_raw_index];
283 /* number of phases in raw where phase 15 is present */
284 u8 phases_15 = phases_per_row[phase_15_raw_index];
285
286 if (phases_0 + phases_15 >= MAX_PHASES)
287 /*
288 * If there are more than 1 phase windows then total
289 * number of phases in both the windows should not be
290 * more than or equal to MAX_PHASES.
291 */
292 return -EINVAL;
293
294 /* Merge 2 cyclic windows */
295 i = phases_15;
296 for (cnt = 0; cnt < phases_0; cnt++) {
297 ranges[phase_15_raw_index][i] =
298 ranges[phase_0_raw_index][cnt];
299 if (++i >= MAX_PHASES)
300 break;
301 }
302
303 phases_per_row[phase_0_raw_index] = 0;
304 phases_per_row[phase_15_raw_index] = phases_15 + phases_0;
305 }
306
307 for (cnt = 0; cnt <= row_index; cnt++) {
308 if (phases_per_row[cnt] > curr_max) {
309 curr_max = phases_per_row[cnt];
310 selected_row_index = cnt;
311 }
312 }
313
314 i = (curr_max * 3) / 4;
315 if (i)
316 i--;
317
318 ret = ranges[selected_row_index][i];
319
320 if (ret >= MAX_PHASES) {
321 ret = -EINVAL;
322 dev_err(mmc_dev(mmc), "%s: Invalid phase selected=%d\n",
323 mmc_hostname(mmc), ret);
324 }
325
326 return ret;
327}
328
329static inline void msm_cm_dll_set_freq(struct sdhci_host *host)
0eb0d9f4 330{
415b5a75
GD		 331 u32 mclk_freq = 0, config;
332
333 /* Program the MCLK value to MCLK_FREQ bit field */
334 if (host->clock <= 112000000)
335 mclk_freq = 0;
336 else if (host->clock <= 125000000)
337 mclk_freq = 1;
338 else if (host->clock <= 137000000)
339 mclk_freq = 2;
340 else if (host->clock <= 150000000)
341 mclk_freq = 3;
342 else if (host->clock <= 162000000)
343 mclk_freq = 4;
344 else if (host->clock <= 175000000)
345 mclk_freq = 5;
346 else if (host->clock <= 187000000)
347 mclk_freq = 6;
348 else if (host->clock <= 200000000)
349 mclk_freq = 7;
350
351 config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
352 config &= ~CMUX_SHIFT_PHASE_MASK;
353 config |= mclk_freq << CMUX_SHIFT_PHASE_SHIFT;
354 writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
355}
356
357/* Initialize the DLL (Programmable Delay Line) */
358static int msm_init_cm_dll(struct sdhci_host *host)
359{
360 struct mmc_host *mmc = host->mmc;
83736352
VG		 361 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
362 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
415b5a75
GD		 363 int wait_cnt = 50;
364 unsigned long flags;
29301f40 365 u32 config;
415b5a75
GD		 366
367 spin_lock_irqsave(&host->lock, flags);
368
0eb0d9f4 369 /*
415b5a75
GD		 370 * Make sure that clock is always enabled when DLL
371 * tuning is in progress. Keeping PWRSAVE ON may
372 * turn off the clock.
0eb0d9f4 373 */
29301f40
RH		 374 config = readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC);
375 config &= ~CORE_CLK_PWRSAVE;
376 writel_relaxed(config, host->ioaddr + CORE_VENDOR_SPEC);
415b5a75 377
83736352
VG		 378 if (msm_host->use_14lpp_dll_reset) {
379 config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
380 config &= ~CORE_CK_OUT_EN;
381 writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
382
383 config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG_2);
384 config |= CORE_DLL_CLOCK_DISABLE;
385 writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG_2);
386 }
387
29301f40
RH		 388 config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
389 config |= CORE_DLL_RST;
390 writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
415b5a75 391
29301f40
RH		 392 config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
393 config |= CORE_DLL_PDN;
394 writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
415b5a75
GD		 395 msm_cm_dll_set_freq(host);
396
83736352
VG		 397 if (msm_host->use_14lpp_dll_reset &&
398 !IS_ERR_OR_NULL(msm_host->xo_clk)) {
399 u32 mclk_freq = 0;
400
401 config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG_2);
402 config &= CORE_FLL_CYCLE_CNT;
403 if (config)
404 mclk_freq = DIV_ROUND_CLOSEST_ULL((host->clock * 8),
405 clk_get_rate(msm_host->xo_clk));
406 else
407 mclk_freq = DIV_ROUND_CLOSEST_ULL((host->clock * 4),
408 clk_get_rate(msm_host->xo_clk));
409
410 config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG_2);
411 config &= ~(0xFF << 10);
412 config |= mclk_freq << 10;
413
414 writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG_2);
415 /* wait for 5us before enabling DLL clock */
416 udelay(5);
417 }
418
29301f40
RH		 419 config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
420 config &= ~CORE_DLL_RST;
421 writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
415b5a75 422
29301f40
RH		 423 config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
424 config &= ~CORE_DLL_PDN;
425 writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
415b5a75 426
83736352
VG		 427 if (msm_host->use_14lpp_dll_reset) {
428 msm_cm_dll_set_freq(host);
429 config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG_2);
430 config &= ~CORE_DLL_CLOCK_DISABLE;
431 writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG_2);
432 }
433
29301f40
RH		 434 config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
435 config |= CORE_DLL_EN;
436 writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
415b5a75 437
29301f40
RH		 438 config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
439 config |= CORE_CK_OUT_EN;
440 writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
415b5a75
GD		 441
442 /* Wait until DLL_LOCK bit of DLL_STATUS register becomes '1' */
443 while (!(readl_relaxed(host->ioaddr + CORE_DLL_STATUS) &
444 CORE_DLL_LOCK)) {
445 /* max. wait for 50us sec for LOCK bit to be set */
446 if (--wait_cnt == 0) {
447 dev_err(mmc_dev(mmc), "%s: DLL failed to LOCK\n",
448 mmc_hostname(mmc));
449 spin_unlock_irqrestore(&host->lock, flags);
450 return -ETIMEDOUT;
451 }
452 udelay(1);
453 }
454
455 spin_unlock_irqrestore(&host->lock, flags);
0eb0d9f4
GD		 456 return 0;
457}
458
cc392c58
RH		 459static int sdhci_msm_cdclp533_calibration(struct sdhci_host *host)
460{
461 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
462 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
463 u32 config, calib_done;
464 int ret;
465
466 pr_debug("%s: %s: Enter\n", mmc_hostname(host->mmc), __func__);
467
468 /*
469 * Retuning in HS400 (DDR mode) will fail, just reset the
470 * tuning block and restore the saved tuning phase.
471 */
472 ret = msm_init_cm_dll(host);
473 if (ret)
474 goto out;
475
476 /* Set the selected phase in delay line hw block */
477 ret = msm_config_cm_dll_phase(host, msm_host->saved_tuning_phase);
478 if (ret)
479 goto out;
480
481 config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
482 config |= CORE_CMD_DAT_TRACK_SEL;
483 writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
484
485 config = readl_relaxed(host->ioaddr + CORE_DDR_200_CFG);
486 config &= ~CORE_CDC_T4_DLY_SEL;
487 writel_relaxed(config, host->ioaddr + CORE_DDR_200_CFG);
488
489 config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_GEN_CFG);
490 config &= ~CORE_CDC_SWITCH_BYPASS_OFF;
491 writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_GEN_CFG);
492
493 config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_GEN_CFG);
494 config |= CORE_CDC_SWITCH_RC_EN;
495 writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_GEN_CFG);
496
497 config = readl_relaxed(host->ioaddr + CORE_DDR_200_CFG);
498 config &= ~CORE_START_CDC_TRAFFIC;
499 writel_relaxed(config, host->ioaddr + CORE_DDR_200_CFG);
500
501 /*
502 * Perform CDC Register Initialization Sequence
503 *
504 * CORE_CSR_CDC_CTLR_CFG0 0x11800EC
505 * CORE_CSR_CDC_CTLR_CFG1 0x3011111
506 * CORE_CSR_CDC_CAL_TIMER_CFG0 0x1201000
507 * CORE_CSR_CDC_CAL_TIMER_CFG1 0x4
508 * CORE_CSR_CDC_REFCOUNT_CFG 0xCB732020
509 * CORE_CSR_CDC_COARSE_CAL_CFG 0xB19
510 * CORE_CSR_CDC_DELAY_CFG 0x3AC
511 * CORE_CDC_OFFSET_CFG 0x0
512 * CORE_CDC_SLAVE_DDA_CFG 0x16334
513 */
514
515 writel_relaxed(0x11800EC, host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
516 writel_relaxed(0x3011111, host->ioaddr + CORE_CSR_CDC_CTLR_CFG1);
517 writel_relaxed(0x1201000, host->ioaddr + CORE_CSR_CDC_CAL_TIMER_CFG0);
518 writel_relaxed(0x4, host->ioaddr + CORE_CSR_CDC_CAL_TIMER_CFG1);
519 writel_relaxed(0xCB732020, host->ioaddr + CORE_CSR_CDC_REFCOUNT_CFG);
520 writel_relaxed(0xB19, host->ioaddr + CORE_CSR_CDC_COARSE_CAL_CFG);
521 writel_relaxed(0x3AC, host->ioaddr + CORE_CSR_CDC_DELAY_CFG);
522 writel_relaxed(0x0, host->ioaddr + CORE_CDC_OFFSET_CFG);
523 writel_relaxed(0x16334, host->ioaddr + CORE_CDC_SLAVE_DDA_CFG);
524
525 /* CDC HW Calibration */
526
527 config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
528 config |= CORE_SW_TRIG_FULL_CALIB;
529 writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
530
531 config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
532 config &= ~CORE_SW_TRIG_FULL_CALIB;
533 writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
534
535 config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
536 config |= CORE_HW_AUTOCAL_ENA;
537 writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
538
539 config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_CAL_TIMER_CFG0);
540 config |= CORE_TIMER_ENA;
541 writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_CAL_TIMER_CFG0);
542
543 ret = readl_relaxed_poll_timeout(host->ioaddr + CORE_CSR_CDC_STATUS0,
544 calib_done,
545 (calib_done & CORE_CALIBRATION_DONE),
546 1, 50);
547
548 if (ret == -ETIMEDOUT) {
549 pr_err("%s: %s: CDC calibration was not completed\n",
550 mmc_hostname(host->mmc), __func__);
551 goto out;
552 }
553
554 ret = readl_relaxed(host->ioaddr + CORE_CSR_CDC_STATUS0)
555 & CORE_CDC_ERROR_CODE_MASK;
556 if (ret) {
557 pr_err("%s: %s: CDC error code %d\n",
558 mmc_hostname(host->mmc), __func__, ret);
559 ret = -EINVAL;
560 goto out;
561 }
562
563 config = readl_relaxed(host->ioaddr + CORE_DDR_200_CFG);
564 config |= CORE_START_CDC_TRAFFIC;
565 writel_relaxed(config, host->ioaddr + CORE_DDR_200_CFG);
566out:
567 pr_debug("%s: %s: Exit, ret %d\n", mmc_hostname(host->mmc),
568 __func__, ret);
569 return ret;
570}
571
415b5a75
GD		 572static int sdhci_msm_execute_tuning(struct sdhci_host *host, u32 opcode)
573{
574 int tuning_seq_cnt = 3;
33d73935 575 u8 phase, tuned_phases[16], tuned_phase_cnt = 0;
415b5a75
GD		 576 int rc;
577 struct mmc_host *mmc = host->mmc;
578 struct mmc_ios ios = host->mmc->ios;
abf270e5
RH		 579 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
580 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
415b5a75
GD		 581
582 /*
583 * Tuning is required for SDR104, HS200 and HS400 cards and
584 * if clock frequency is greater than 100MHz in these modes.
585 */
ff06ce41
VG		 586 if (host->clock <= CORE_FREQ_100MHZ ||
587 !(ios.timing == MMC_TIMING_MMC_HS400 ||
588 ios.timing == MMC_TIMING_MMC_HS200 ||
589 ios.timing == MMC_TIMING_UHS_SDR104))
415b5a75
GD		 590 return 0;
591
415b5a75
GD		 592retry:
593 /* First of all reset the tuning block */
594 rc = msm_init_cm_dll(host);
595 if (rc)
33d73935 596 return rc;
415b5a75
GD		 597
598 phase = 0;
599 do {
415b5a75
GD		 600 /* Set the phase in delay line hw block */
601 rc = msm_config_cm_dll_phase(host, phase);
602 if (rc)
33d73935 603 return rc;
415b5a75 604
abf270e5 605 msm_host->saved_tuning_phase = phase;
9979dbe5 606 rc = mmc_send_tuning(mmc, opcode, NULL);
33d73935 607 if (!rc) {
415b5a75
GD		 608 /* Tuning is successful at this tuning point */
609 tuned_phases[tuned_phase_cnt++] = phase;
610 dev_dbg(mmc_dev(mmc), "%s: Found good phase = %d\n",
611 mmc_hostname(mmc), phase);
612 }
613 } while (++phase < ARRAY_SIZE(tuned_phases));
614
615 if (tuned_phase_cnt) {
616 rc = msm_find_most_appropriate_phase(host, tuned_phases,
617 tuned_phase_cnt);
618 if (rc < 0)
33d73935 619 return rc;
415b5a75
GD		 620 else
621 phase = rc;
622
623 /*
624 * Finally set the selected phase in delay
625 * line hw block.
626 */
627 rc = msm_config_cm_dll_phase(host, phase);
628 if (rc)
33d73935 629 return rc;
415b5a75
GD		 630 dev_dbg(mmc_dev(mmc), "%s: Setting the tuning phase to %d\n",
631 mmc_hostname(mmc), phase);
632 } else {
633 if (--tuning_seq_cnt)
634 goto retry;
635 /* Tuning failed */
636 dev_dbg(mmc_dev(mmc), "%s: No tuning point found\n",
637 mmc_hostname(mmc));
638 rc = -EIO;
639 }
640
ff06ce41
VG		 641 if (!rc)
642 msm_host->tuning_done = true;
415b5a75
GD		 643 return rc;
644}
645
ee320674
RH		 646static void sdhci_msm_set_uhs_signaling(struct sdhci_host *host,
647 unsigned int uhs)
648{
649 struct mmc_host *mmc = host->mmc;
ff06ce41
VG		 650 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
651 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
ee320674 652 u16 ctrl_2;
ff06ce41 653 u32 config;
ee320674
RH		 654
655 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
656 /* Select Bus Speed Mode for host */
657 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
658 switch (uhs) {
659 case MMC_TIMING_UHS_SDR12:
660 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
661 break;
662 case MMC_TIMING_UHS_SDR25:
663 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
664 break;
665 case MMC_TIMING_UHS_SDR50:
666 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
667 break;
ff06ce41 668 case MMC_TIMING_MMC_HS400:
ee320674
RH		 669 case MMC_TIMING_MMC_HS200:
670 case MMC_TIMING_UHS_SDR104:
671 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
672 break;
673 case MMC_TIMING_UHS_DDR50:
674 case MMC_TIMING_MMC_DDR52:
675 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
676 break;
677 }
678
679 /*
680 * When clock frequency is less than 100MHz, the feedback clock must be
681 * provided and DLL must not be used so that tuning can be skipped. To
682 * provide feedback clock, the mode selection can be any value less
683 * than 3'b011 in bits [2:0] of HOST CONTROL2 register.
684 */
ff06ce41
VG		 685 if (host->clock <= CORE_FREQ_100MHZ) {
686 if (uhs == MMC_TIMING_MMC_HS400 ||
687 uhs == MMC_TIMING_MMC_HS200 ||
688 uhs == MMC_TIMING_UHS_SDR104)
689 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
690 /*
691 * DLL is not required for clock <= 100MHz
692 * Thus, make sure DLL it is disabled when not required
693 */
694 config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
695 config |= CORE_DLL_RST;
696 writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
697
698 config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
699 config |= CORE_DLL_PDN;
700 writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
701
702 /*
703 * The DLL needs to be restored and CDCLP533 recalibrated
704 * when the clock frequency is set back to 400MHz.
705 */
706 msm_host->calibration_done = false;
707 }
ee320674
RH		 708
709 dev_dbg(mmc_dev(mmc), "%s: clock=%u uhs=%u ctrl_2=0x%x\n",
710 mmc_hostname(host->mmc), host->clock, uhs, ctrl_2);
711 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
cc392c58
RH		 712
713 spin_unlock_irq(&host->lock);
714 /* CDCLP533 HW calibration is only required for HS400 mode*/
715 if (host->clock > CORE_FREQ_100MHZ &&
716 msm_host->tuning_done && !msm_host->calibration_done &&
717 mmc->ios.timing == MMC_TIMING_MMC_HS400)
718 if (!sdhci_msm_cdclp533_calibration(host))
719 msm_host->calibration_done = true;
720 spin_lock_irq(&host->lock);
ee320674
RH		 721}
722
ad81d387
GD		 723static void sdhci_msm_voltage_switch(struct sdhci_host *host)
724{
725 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
726 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
727 u32 irq_status, irq_ack = 0;
728
729 irq_status = readl_relaxed(msm_host->core_mem + CORE_PWRCTL_STATUS);
730 irq_status &= INT_MASK;
731
732 writel_relaxed(irq_status, msm_host->core_mem + CORE_PWRCTL_CLEAR);
733
734 if (irq_status & (CORE_PWRCTL_BUS_ON | CORE_PWRCTL_BUS_OFF))
735 irq_ack |= CORE_PWRCTL_BUS_SUCCESS;
736 if (irq_status & (CORE_PWRCTL_IO_LOW | CORE_PWRCTL_IO_HIGH))
737 irq_ack |= CORE_PWRCTL_IO_SUCCESS;
738
739 /*
740 * The driver has to acknowledge the interrupt, switch voltages and
741 * report back if it succeded or not to this register. The voltage
742 * switches are handled by the sdhci core, so just report success.
743 */
744 writel_relaxed(irq_ack, msm_host->core_mem + CORE_PWRCTL_CTL);
745}
746
747static irqreturn_t sdhci_msm_pwr_irq(int irq, void *data)
748{
749 struct sdhci_host *host = (struct sdhci_host *)data;
750
751 sdhci_msm_voltage_switch(host);
752
753 return IRQ_HANDLED;
754}
755
80031bde
RH		 756static unsigned int sdhci_msm_get_max_clock(struct sdhci_host *host)
757{
758 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
759 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
760
761 return clk_round_rate(msm_host->clk, ULONG_MAX);
762}
763
764static unsigned int sdhci_msm_get_min_clock(struct sdhci_host *host)
765{
766 return SDHCI_MSM_MIN_CLOCK;
767}
768
edc609fd
RH		 769/**
770 * __sdhci_msm_set_clock - sdhci_msm clock control.
771 *
772 * Description:
773 * MSM controller does not use internal divider and
774 * instead directly control the GCC clock as per
775 * HW recommendation.
776 **/
777void __sdhci_msm_set_clock(struct sdhci_host *host, unsigned int clock)
778{
779 u16 clk;
780 /*
781 * Keep actual_clock as zero -
782 * - since there is no divider used so no need of having actual_clock.
783 * - MSM controller uses SDCLK for data timeout calculation. If
784 * actual_clock is zero, host->clock is taken for calculation.
785 */
786 host->mmc->actual_clock = 0;
787
788 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
789
790 if (clock == 0)
791 return;
792
793 /*
794 * MSM controller do not use clock divider.
795 * Thus read SDHCI_CLOCK_CONTROL and only enable
796 * clock with no divider value programmed.
797 */
798 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
799 sdhci_enable_clk(host, clk);
800}
801
802/* sdhci_msm_set_clock - Called with (host->lock) spinlock held. */
803static void sdhci_msm_set_clock(struct sdhci_host *host, unsigned int clock)
804{
805 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
806 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
b12d44db 807 struct mmc_ios curr_ios = host->mmc->ios;
ff06ce41 808 u32 config;
edc609fd
RH		 809 int rc;
810
811 if (!clock) {
812 msm_host->clk_rate = clock;
813 goto out;
814 }
815
816 spin_unlock_irq(&host->lock);
b12d44db
RH		 817 /*
818 * The SDHC requires internal clock frequency to be double the
819 * actual clock that will be set for DDR mode. The controller
820 * uses the faster clock(100/400MHz) for some of its parts and
821 * send the actual required clock (50/200MHz) to the card.
822 */
823 if (curr_ios.timing == MMC_TIMING_UHS_DDR50 ||
824 curr_ios.timing == MMC_TIMING_MMC_DDR52 ||
825 curr_ios.timing == MMC_TIMING_MMC_HS400)
826 clock *= 2;
ff06ce41
VG		 827 /*
828 * In general all timing modes are controlled via UHS mode select in
829 * Host Control2 register. eMMC specific HS200/HS400 doesn't have
830 * their respective modes defined here, hence we use these values.
831 *
832 * HS200 - SDR104 (Since they both are equivalent in functionality)
833 * HS400 - This involves multiple configurations
834 * Initially SDR104 - when tuning is required as HS200
835 * Then when switching to DDR @ 400MHz (HS400) we use
836 * the vendor specific HC_SELECT_IN to control the mode.
837 *
838 * In addition to controlling the modes we also need to select the
839 * correct input clock for DLL depending on the mode.
840 *
841 * HS400 - divided clock (free running MCLK/2)
842 * All other modes - default (free running MCLK)
843 */
844 if (curr_ios.timing == MMC_TIMING_MMC_HS400) {
845 /* Select the divided clock (free running MCLK/2) */
846 config = readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC);
847 config &= ~CORE_HC_MCLK_SEL_MASK;
848 config |= CORE_HC_MCLK_SEL_HS400;
849
850 writel_relaxed(config, host->ioaddr + CORE_VENDOR_SPEC);
851 /*
852 * Select HS400 mode using the HC_SELECT_IN from VENDOR SPEC
853 * register
854 */
855 if (msm_host->tuning_done && !msm_host->calibration_done) {
856 /*
857 * Write 0x6 to HC_SELECT_IN and 1 to HC_SELECT_IN_EN
858 * field in VENDOR_SPEC_FUNC
859 */
860 config = readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC);
861 config |= CORE_HC_SELECT_IN_HS400;
862 config |= CORE_HC_SELECT_IN_EN;
863 writel_relaxed(config, host->ioaddr + CORE_VENDOR_SPEC);
864 }
865 } else {
866 config = readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC);
867 config &= ~CORE_HC_MCLK_SEL_MASK;
868 config |= CORE_HC_MCLK_SEL_DFLT;
869 writel_relaxed(config, host->ioaddr + CORE_VENDOR_SPEC);
870
871 /*
872 * Disable HC_SELECT_IN to be able to use the UHS mode select
873 * configuration from Host Control2 register for all other
874 * modes.
875 * Write 0 to HC_SELECT_IN and HC_SELECT_IN_EN field
876 * in VENDOR_SPEC_FUNC
877 */
878 config = readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC);
879 config &= ~CORE_HC_SELECT_IN_EN;
880 config &= ~CORE_HC_SELECT_IN_MASK;
881 writel_relaxed(config, host->ioaddr + CORE_VENDOR_SPEC);
882 }
883
884 /*
885 * Make sure above writes impacting free running MCLK are completed
886 * before changing the clk_rate at GCC.
887 */
888 wmb();
edc609fd
RH		 889
890 rc = clk_set_rate(msm_host->clk, clock);
891 if (rc) {
b12d44db
RH		 892 pr_err("%s: Failed to set clock at rate %u at timing %d\n",
893 mmc_hostname(host->mmc), clock,
894 curr_ios.timing);
edc609fd
RH		 895 goto out_lock;
896 }
897 msm_host->clk_rate = clock;
b12d44db
RH		 898 pr_debug("%s: Setting clock at rate %lu at timing %d\n",
899 mmc_hostname(host->mmc), clk_get_rate(msm_host->clk),
900 curr_ios.timing);
edc609fd
RH		 901
902out_lock:
903 spin_lock_irq(&host->lock);
904out:
905 __sdhci_msm_set_clock(host, clock);
906}
907
0eb0d9f4
GD		 908static const struct of_device_id sdhci_msm_dt_match[] = {
909 { .compatible = "qcom,sdhci-msm-v4" },
910 {},
911};
912
913MODULE_DEVICE_TABLE(of, sdhci_msm_dt_match);
914
a50396a4 915static const struct sdhci_ops sdhci_msm_ops = {
0eb0d9f4 916 .platform_execute_tuning = sdhci_msm_execute_tuning,
ed1761d7 917 .reset = sdhci_reset,
edc609fd 918 .set_clock = sdhci_msm_set_clock,
80031bde
RH		 919 .get_min_clock = sdhci_msm_get_min_clock,
920 .get_max_clock = sdhci_msm_get_max_clock,
ed1761d7 921 .set_bus_width = sdhci_set_bus_width,
ee320674 922 .set_uhs_signaling = sdhci_msm_set_uhs_signaling,
ad81d387 923 .voltage_switch = sdhci_msm_voltage_switch,
0eb0d9f4
GD		 924};
925
a50396a4
JZ		 926static const struct sdhci_pltfm_data sdhci_msm_pdata = {
927 .quirks = SDHCI_QUIRK_BROKEN_CARD_DETECTION |
9718f84b 928 SDHCI_QUIRK_NO_CARD_NO_RESET |
a0e31428
RH		 929 SDHCI_QUIRK_SINGLE_POWER_WRITE |
930 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
931 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
a50396a4
JZ		 932 .ops = &sdhci_msm_ops,
933};
934
0eb0d9f4
GD		 935static int sdhci_msm_probe(struct platform_device *pdev)
936{
937 struct sdhci_host *host;
938 struct sdhci_pltfm_host *pltfm_host;
939 struct sdhci_msm_host *msm_host;
940 struct resource *core_memres;
941 int ret;
3a3ad3e9 942 u16 host_version, core_minor;
29301f40 943 u32 core_version, config;
3a3ad3e9 944 u8 core_major;
0eb0d9f4 945
6f699531 946 host = sdhci_pltfm_init(pdev, &sdhci_msm_pdata, sizeof(*msm_host));
0eb0d9f4
GD		 947 if (IS_ERR(host))
948 return PTR_ERR(host);
949
950 pltfm_host = sdhci_priv(host);
6f699531 951 msm_host = sdhci_pltfm_priv(pltfm_host);
0eb0d9f4
GD		 952 msm_host->mmc = host->mmc;
953 msm_host->pdev = pdev;
954
955 ret = mmc_of_parse(host->mmc);
956 if (ret)
957 goto pltfm_free;
958
959 sdhci_get_of_property(pdev);
960
abf270e5
RH		 961 msm_host->saved_tuning_phase = INVALID_TUNING_PHASE;
962
0eb0d9f4
GD		 963 /* Setup SDCC bus voter clock. */
964 msm_host->bus_clk = devm_clk_get(&pdev->dev, "bus");
965 if (!IS_ERR(msm_host->bus_clk)) {
966 /* Vote for max. clk rate for max. performance */
967 ret = clk_set_rate(msm_host->bus_clk, INT_MAX);
968 if (ret)
969 goto pltfm_free;
970 ret = clk_prepare_enable(msm_host->bus_clk);
971 if (ret)
972 goto pltfm_free;
973 }
974
975 /* Setup main peripheral bus clock */
976 msm_host->pclk = devm_clk_get(&pdev->dev, "iface");
977 if (IS_ERR(msm_host->pclk)) {
978 ret = PTR_ERR(msm_host->pclk);
2801b95e 979 dev_err(&pdev->dev, "Peripheral clk setup failed (%d)\n", ret);
0eb0d9f4
GD		 980 goto bus_clk_disable;
981 }
982
983 ret = clk_prepare_enable(msm_host->pclk);
984 if (ret)
985 goto bus_clk_disable;
986
987 /* Setup SDC MMC clock */
988 msm_host->clk = devm_clk_get(&pdev->dev, "core");
989 if (IS_ERR(msm_host->clk)) {
990 ret = PTR_ERR(msm_host->clk);
991 dev_err(&pdev->dev, "SDC MMC clk setup failed (%d)\n", ret);
992 goto pclk_disable;
993 }
994
83736352
VG		 995 /*
996 * xo clock is needed for FLL feature of cm_dll.
997 * In case if xo clock is not mentioned in DT, warn and proceed.
998 */
999 msm_host->xo_clk = devm_clk_get(&pdev->dev, "xo");
1000 if (IS_ERR(msm_host->xo_clk)) {
1001 ret = PTR_ERR(msm_host->xo_clk);
1002 dev_warn(&pdev->dev, "TCXO clk not present (%d)\n", ret);
1003 }
1004
951b8c87
II		 1005 /* Vote for maximum clock rate for maximum performance */
1006 ret = clk_set_rate(msm_host->clk, INT_MAX);
1007 if (ret)
1008 dev_warn(&pdev->dev, "core clock boost failed\n");
1009
0eb0d9f4
GD		 1010 ret = clk_prepare_enable(msm_host->clk);
1011 if (ret)
1012 goto pclk_disable;
1013
1014 core_memres = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1015 msm_host->core_mem = devm_ioremap_resource(&pdev->dev, core_memres);
1016
1017 if (IS_ERR(msm_host->core_mem)) {
1018 dev_err(&pdev->dev, "Failed to remap registers\n");
1019 ret = PTR_ERR(msm_host->core_mem);
1020 goto clk_disable;
1021 }
1022
29301f40
RH		 1023 config = readl_relaxed(msm_host->core_mem + CORE_POWER);
1024 config |= CORE_SW_RST;
1025 writel_relaxed(config, msm_host->core_mem + CORE_POWER);
0eb0d9f4
GD		 1026
1027 /* SW reset can take upto 10HCLK + 15MCLK cycles. (min 40us) */
1028 usleep_range(1000, 5000);
1029 if (readl(msm_host->core_mem + CORE_POWER) & CORE_SW_RST) {
1030 dev_err(&pdev->dev, "Stuck in reset\n");
1031 ret = -ETIMEDOUT;
1032 goto clk_disable;
1033 }
1034
1035 /* Set HC_MODE_EN bit in HC_MODE register */
1036 writel_relaxed(HC_MODE_EN, (msm_host->core_mem + CORE_HC_MODE));
1037
ff06ce41
VG		 1038 config = readl_relaxed(msm_host->core_mem + CORE_HC_MODE);
1039 config |= FF_CLK_SW_RST_DIS;
1040 writel_relaxed(config, msm_host->core_mem + CORE_HC_MODE);
1041
0eb0d9f4
GD		 1042 host_version = readw_relaxed((host->ioaddr + SDHCI_HOST_VERSION));
1043 dev_dbg(&pdev->dev, "Host Version: 0x%x Vendor Version 0x%x\n",
1044 host_version, ((host_version & SDHCI_VENDOR_VER_MASK) >>
1045 SDHCI_VENDOR_VER_SHIFT));
1046
3a3ad3e9
GD		 1047 core_version = readl_relaxed(msm_host->core_mem + CORE_MCI_VERSION);
1048 core_major = (core_version & CORE_VERSION_MAJOR_MASK) >>
1049 CORE_VERSION_MAJOR_SHIFT;
1050 core_minor = core_version & CORE_VERSION_MINOR_MASK;
1051 dev_dbg(&pdev->dev, "MCI Version: 0x%08x, major: 0x%04x, minor: 0x%02x\n",
1052 core_version, core_major, core_minor);
1053
83736352
VG		 1054 if (core_major == 1 && core_minor >= 0x42)
1055 msm_host->use_14lpp_dll_reset = true;
1056
3a3ad3e9
GD		 1057 /*
1058 * Support for some capabilities is not advertised by newer
1059 * controller versions and must be explicitly enabled.
1060 */
1061 if (core_major >= 1 && core_minor != 0x11 && core_minor != 0x12) {
29301f40
RH		 1062 config = readl_relaxed(host->ioaddr + SDHCI_CAPABILITIES);
1063 config |= SDHCI_CAN_VDD_300 | SDHCI_CAN_DO_8BIT;
1064 writel_relaxed(config, host->ioaddr +
3a3ad3e9
GD		 1065 CORE_VENDOR_SPEC_CAPABILITIES0);
1066 }
1067
ad81d387
GD		 1068 /* Setup IRQ for handling power/voltage tasks with PMIC */
1069 msm_host->pwr_irq = platform_get_irq_byname(pdev, "pwr_irq");
1070 if (msm_host->pwr_irq < 0) {
1071 dev_err(&pdev->dev, "Get pwr_irq failed (%d)\n",
1072 msm_host->pwr_irq);
d1f63f0c 1073 ret = msm_host->pwr_irq;
ad81d387
GD		 1074 goto clk_disable;
1075 }
1076
1077 ret = devm_request_threaded_irq(&pdev->dev, msm_host->pwr_irq, NULL,
1078 sdhci_msm_pwr_irq, IRQF_ONESHOT,
1079 dev_name(&pdev->dev), host);
1080 if (ret) {
1081 dev_err(&pdev->dev, "Request IRQ failed (%d)\n", ret);
1082 goto clk_disable;
1083 }
1084
67e6db11
PG		 1085 pm_runtime_get_noresume(&pdev->dev);
1086 pm_runtime_set_active(&pdev->dev);
1087 pm_runtime_enable(&pdev->dev);
1088 pm_runtime_set_autosuspend_delay(&pdev->dev,
1089 MSM_MMC_AUTOSUSPEND_DELAY_MS);
1090 pm_runtime_use_autosuspend(&pdev->dev);
1091
0eb0d9f4
GD		 1092 ret = sdhci_add_host(host);
1093 if (ret)
67e6db11
PG		 1094 goto pm_runtime_disable;
1095
1096 pm_runtime_mark_last_busy(&pdev->dev);
1097 pm_runtime_put_autosuspend(&pdev->dev);
0eb0d9f4
GD		 1098
1099 return 0;
1100
67e6db11
PG		 1101pm_runtime_disable:
1102 pm_runtime_disable(&pdev->dev);
1103 pm_runtime_set_suspended(&pdev->dev);
1104 pm_runtime_put_noidle(&pdev->dev);
0eb0d9f4
GD		 1105clk_disable:
1106 clk_disable_unprepare(msm_host->clk);
1107pclk_disable:
1108 clk_disable_unprepare(msm_host->pclk);
1109bus_clk_disable:
1110 if (!IS_ERR(msm_host->bus_clk))
1111 clk_disable_unprepare(msm_host->bus_clk);
1112pltfm_free:
1113 sdhci_pltfm_free(pdev);
1114 return ret;
1115}
1116
1117static int sdhci_msm_remove(struct platform_device *pdev)
1118{
1119 struct sdhci_host *host = platform_get_drvdata(pdev);
1120 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
6f699531 1121 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
0eb0d9f4
GD		 1122 int dead = (readl_relaxed(host->ioaddr + SDHCI_INT_STATUS) ==
1123 0xffffffff);
1124
1125 sdhci_remove_host(host, dead);
67e6db11
PG		 1126
1127 pm_runtime_get_sync(&pdev->dev);
1128 pm_runtime_disable(&pdev->dev);
1129 pm_runtime_put_noidle(&pdev->dev);
1130
0eb0d9f4
GD		 1131 clk_disable_unprepare(msm_host->clk);
1132 clk_disable_unprepare(msm_host->pclk);
1133 if (!IS_ERR(msm_host->bus_clk))
1134 clk_disable_unprepare(msm_host->bus_clk);
6f699531 1135 sdhci_pltfm_free(pdev);
0eb0d9f4
GD		 1136 return 0;
1137}
1138
67e6db11
PG		 1139#ifdef CONFIG_PM
1140static int sdhci_msm_runtime_suspend(struct device *dev)
1141{
1142 struct sdhci_host *host = dev_get_drvdata(dev);
1143 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1144 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1145
1146 clk_disable_unprepare(msm_host->clk);
1147 clk_disable_unprepare(msm_host->pclk);
1148
1149 return 0;
1150}
1151
1152static int sdhci_msm_runtime_resume(struct device *dev)
1153{
1154 struct sdhci_host *host = dev_get_drvdata(dev);
1155 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1156 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1157 int ret;
1158
1159 ret = clk_prepare_enable(msm_host->clk);
1160 if (ret) {
1161 dev_err(dev, "clk_enable failed for core_clk: %d\n", ret);
1162 return ret;
1163 }
1164 ret = clk_prepare_enable(msm_host->pclk);
1165 if (ret) {
1166 dev_err(dev, "clk_enable failed for iface_clk: %d\n", ret);
1167 clk_disable_unprepare(msm_host->clk);
1168 return ret;
1169 }
1170
1171 return 0;
1172}
1173#endif
1174
1175static const struct dev_pm_ops sdhci_msm_pm_ops = {
1176 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
1177 pm_runtime_force_resume)
1178 SET_RUNTIME_PM_OPS(sdhci_msm_runtime_suspend,
1179 sdhci_msm_runtime_resume,
1180 NULL)
1181};
1182
0eb0d9f4
GD		 1183static struct platform_driver sdhci_msm_driver = {
1184 .probe = sdhci_msm_probe,
1185 .remove = sdhci_msm_remove,
1186 .driver = {
1187 .name = "sdhci_msm",
0eb0d9f4 1188 .of_match_table = sdhci_msm_dt_match,
67e6db11 1189 .pm = &sdhci_msm_pm_ops,
0eb0d9f4
GD		 1190 },
1191};
1192
1193module_platform_driver(sdhci_msm_driver);
1194
1195MODULE_DESCRIPTION("Qualcomm Secure Digital Host Controller Interface driver");
1196MODULE_LICENSE("GPL v2");
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