[mirror_ubuntu-artful-kernel.git] / drivers / mmc / host / sdhci-msm.c

/*
 * drivers/mmc/host/sdhci-msm.c - Qualcomm SDHCI Platform driver
 *
 * Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 and
 * only version 2 as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 */

#include <linux/module.h>
#include <linux/of_device.h>
#include <linux/delay.h>
#include <linux/mmc/mmc.h>
#include <linux/slab.h>

#include "sdhci-pltfm.h"

#define CORE_MCI_VERSION		0x50
#define CORE_VERSION_MAJOR_SHIFT	28
#define CORE_VERSION_MAJOR_MASK		(0xf << CORE_VERSION_MAJOR_SHIFT)
#define CORE_VERSION_MINOR_MASK		0xff

#define CORE_HC_MODE		0x78
#define HC_MODE_EN		0x1
#define CORE_POWER		0x0
#define CORE_SW_RST		BIT(7)

#define MAX_PHASES		16
#define CORE_DLL_LOCK		BIT(7)
#define CORE_DLL_EN		BIT(16)
#define CORE_CDR_EN		BIT(17)
#define CORE_CK_OUT_EN		BIT(18)
#define CORE_CDR_EXT_EN		BIT(19)
#define CORE_DLL_PDN		BIT(29)
#define CORE_DLL_RST		BIT(30)
#define CORE_DLL_CONFIG		0x100
#define CORE_DLL_STATUS		0x108

#define CORE_VENDOR_SPEC	0x10c
#define CORE_CLK_PWRSAVE	BIT(1)

#define CORE_VENDOR_SPEC_CAPABILITIES0	0x11c

#define CDR_SELEXT_SHIFT	20
#define CDR_SELEXT_MASK		(0xf << CDR_SELEXT_SHIFT)
#define CMUX_SHIFT_PHASE_SHIFT	24
#define CMUX_SHIFT_PHASE_MASK	(7 << CMUX_SHIFT_PHASE_SHIFT)

struct sdhci_msm_host {
	struct platform_device *pdev;
	void __iomem *core_mem;	/* MSM SDCC mapped address */
	struct clk *clk;	/* main SD/MMC bus clock */
	struct clk *pclk;	/* SDHC peripheral bus clock */
	struct clk *bus_clk;	/* SDHC bus voter clock */
	struct mmc_host *mmc;
};

/* Platform specific tuning */
static inline int msm_dll_poll_ck_out_en(struct sdhci_host *host, u8 poll)
{
	u32 wait_cnt = 50;
	u8 ck_out_en;
	struct mmc_host *mmc = host->mmc;

	/* Poll for CK_OUT_EN bit.  max. poll time = 50us */
	ck_out_en = !!(readl_relaxed(host->ioaddr + CORE_DLL_CONFIG) &
			CORE_CK_OUT_EN);

	while (ck_out_en != poll) {
		if (--wait_cnt == 0) {
			dev_err(mmc_dev(mmc), "%s: CK_OUT_EN bit is not %d\n",
			       mmc_hostname(mmc), poll);
			return -ETIMEDOUT;
		}
		udelay(1);

		ck_out_en = !!(readl_relaxed(host->ioaddr + CORE_DLL_CONFIG) &
				CORE_CK_OUT_EN);
	}

	return 0;
}

static int msm_config_cm_dll_phase(struct sdhci_host *host, u8 phase)
{
	int rc;
	static const u8 grey_coded_phase_table[] = {
		0x0, 0x1, 0x3, 0x2, 0x6, 0x7, 0x5, 0x4,
		0xc, 0xd, 0xf, 0xe, 0xa, 0xb, 0x9, 0x8
	};
	unsigned long flags;
	u32 config;
	struct mmc_host *mmc = host->mmc;

	spin_lock_irqsave(&host->lock, flags);

	config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
	config &= ~(CORE_CDR_EN | CORE_CK_OUT_EN);
	config |= (CORE_CDR_EXT_EN | CORE_DLL_EN);
	writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);

	/* Wait until CK_OUT_EN bit of DLL_CONFIG register becomes '0' */
	rc = msm_dll_poll_ck_out_en(host, 0);
	if (rc)
		goto err_out;

	/*
	 * Write the selected DLL clock output phase (0 ... 15)
	 * to CDR_SELEXT bit field of DLL_CONFIG register.
	 */
	config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
	config &= ~CDR_SELEXT_MASK;
	config |= grey_coded_phase_table[phase] << CDR_SELEXT_SHIFT;
	writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);

	/* Set CK_OUT_EN bit of DLL_CONFIG register to 1. */
	writel_relaxed((readl_relaxed(host->ioaddr + CORE_DLL_CONFIG)
			| CORE_CK_OUT_EN), host->ioaddr + CORE_DLL_CONFIG);

	/* Wait until CK_OUT_EN bit of DLL_CONFIG register becomes '1' */
	rc = msm_dll_poll_ck_out_en(host, 1);
	if (rc)
		goto err_out;

	config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
	config |= CORE_CDR_EN;
	config &= ~CORE_CDR_EXT_EN;
	writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
	goto out;

err_out:
	dev_err(mmc_dev(mmc), "%s: Failed to set DLL phase: %d\n",
	       mmc_hostname(mmc), phase);
out:
	spin_unlock_irqrestore(&host->lock, flags);
	return rc;
}

/*
 * Find out the greatest range of consecuitive selected
 * DLL clock output phases that can be used as sampling
 * setting for SD3.0 UHS-I card read operation (in SDR104
 * timing mode) or for eMMC4.5 card read operation (in HS200
 * timing mode).
 * Select the 3/4 of the range and configure the DLL with the
 * selected DLL clock output phase.
 */

static int msm_find_most_appropriate_phase(struct sdhci_host *host,
					   u8 *phase_table, u8 total_phases)
{
	int ret;
	u8 ranges[MAX_PHASES][MAX_PHASES] = { {0}, {0} };
	u8 phases_per_row[MAX_PHASES] = { 0 };
	int row_index = 0, col_index = 0, selected_row_index = 0, curr_max = 0;
	int i, cnt, phase_0_raw_index = 0, phase_15_raw_index = 0;
	bool phase_0_found = false, phase_15_found = false;
	struct mmc_host *mmc = host->mmc;

	if (!total_phases || (total_phases > MAX_PHASES)) {
		dev_err(mmc_dev(mmc), "%s: Invalid argument: total_phases=%d\n",
		       mmc_hostname(mmc), total_phases);
		return -EINVAL;
	}

	for (cnt = 0; cnt < total_phases; cnt++) {
		ranges[row_index][col_index] = phase_table[cnt];
		phases_per_row[row_index] += 1;
		col_index++;

		if ((cnt + 1) == total_phases) {
			continue;
		/* check if next phase in phase_table is consecutive or not */
		} else if ((phase_table[cnt] + 1) != phase_table[cnt + 1]) {
			row_index++;
			col_index = 0;
		}
	}

	if (row_index >= MAX_PHASES)
		return -EINVAL;

	/* Check if phase-0 is present in first valid window? */
	if (!ranges[0][0]) {
		phase_0_found = true;
		phase_0_raw_index = 0;
		/* Check if cycle exist between 2 valid windows */
		for (cnt = 1; cnt <= row_index; cnt++) {
			if (phases_per_row[cnt]) {
				for (i = 0; i < phases_per_row[cnt]; i++) {
					if (ranges[cnt][i] == 15) {
						phase_15_found = true;
						phase_15_raw_index = cnt;
						break;
					}
				}
			}
		}
	}

	/* If 2 valid windows form cycle then merge them as single window */
	if (phase_0_found && phase_15_found) {
		/* number of phases in raw where phase 0 is present */
		u8 phases_0 = phases_per_row[phase_0_raw_index];
		/* number of phases in raw where phase 15 is present */
		u8 phases_15 = phases_per_row[phase_15_raw_index];

		if (phases_0 + phases_15 >= MAX_PHASES)
			/*
			 * If there are more than 1 phase windows then total
			 * number of phases in both the windows should not be
			 * more than or equal to MAX_PHASES.
			 */
			return -EINVAL;

		/* Merge 2 cyclic windows */
		i = phases_15;
		for (cnt = 0; cnt < phases_0; cnt++) {
			ranges[phase_15_raw_index][i] =
			    ranges[phase_0_raw_index][cnt];
			if (++i >= MAX_PHASES)
				break;
		}

		phases_per_row[phase_0_raw_index] = 0;
		phases_per_row[phase_15_raw_index] = phases_15 + phases_0;
	}

	for (cnt = 0; cnt <= row_index; cnt++) {
		if (phases_per_row[cnt] > curr_max) {
			curr_max = phases_per_row[cnt];
			selected_row_index = cnt;
		}
	}

	i = (curr_max * 3) / 4;
	if (i)
		i--;

	ret = ranges[selected_row_index][i];

	if (ret >= MAX_PHASES) {
		ret = -EINVAL;
		dev_err(mmc_dev(mmc), "%s: Invalid phase selected=%d\n",
		       mmc_hostname(mmc), ret);
	}

	return ret;
}

static inline void msm_cm_dll_set_freq(struct sdhci_host *host)
{
	u32 mclk_freq = 0, config;

	/* Program the MCLK value to MCLK_FREQ bit field */
	if (host->clock <= 112000000)
		mclk_freq = 0;
	else if (host->clock <= 125000000)
		mclk_freq = 1;
	else if (host->clock <= 137000000)
		mclk_freq = 2;
	else if (host->clock <= 150000000)
		mclk_freq = 3;
	else if (host->clock <= 162000000)
		mclk_freq = 4;
	else if (host->clock <= 175000000)
		mclk_freq = 5;
	else if (host->clock <= 187000000)
		mclk_freq = 6;
	else if (host->clock <= 200000000)
		mclk_freq = 7;

	config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
	config &= ~CMUX_SHIFT_PHASE_MASK;
	config |= mclk_freq << CMUX_SHIFT_PHASE_SHIFT;
	writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
}

/* Initialize the DLL (Programmable Delay Line) */
static int msm_init_cm_dll(struct sdhci_host *host)
{
	struct mmc_host *mmc = host->mmc;
	int wait_cnt = 50;
	unsigned long flags;

	spin_lock_irqsave(&host->lock, flags);

	/*
	 * Make sure that clock is always enabled when DLL
	 * tuning is in progress. Keeping PWRSAVE ON may
	 * turn off the clock.
	 */
	writel_relaxed((readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC)
			& ~CORE_CLK_PWRSAVE), host->ioaddr + CORE_VENDOR_SPEC);

	/* Write 1 to DLL_RST bit of DLL_CONFIG register */
	writel_relaxed((readl_relaxed(host->ioaddr + CORE_DLL_CONFIG)
			| CORE_DLL_RST), host->ioaddr + CORE_DLL_CONFIG);

	/* Write 1 to DLL_PDN bit of DLL_CONFIG register */
	writel_relaxed((readl_relaxed(host->ioaddr + CORE_DLL_CONFIG)
			| CORE_DLL_PDN), host->ioaddr + CORE_DLL_CONFIG);
	msm_cm_dll_set_freq(host);

	/* Write 0 to DLL_RST bit of DLL_CONFIG register */
	writel_relaxed((readl_relaxed(host->ioaddr + CORE_DLL_CONFIG)
			& ~CORE_DLL_RST), host->ioaddr + CORE_DLL_CONFIG);

	/* Write 0 to DLL_PDN bit of DLL_CONFIG register */
	writel_relaxed((readl_relaxed(host->ioaddr + CORE_DLL_CONFIG)
			& ~CORE_DLL_PDN), host->ioaddr + CORE_DLL_CONFIG);

	/* Set DLL_EN bit to 1. */
	writel_relaxed((readl_relaxed(host->ioaddr + CORE_DLL_CONFIG)
			| CORE_DLL_EN), host->ioaddr + CORE_DLL_CONFIG);

	/* Set CK_OUT_EN bit to 1. */
	writel_relaxed((readl_relaxed(host->ioaddr + CORE_DLL_CONFIG)
			| CORE_CK_OUT_EN), host->ioaddr + CORE_DLL_CONFIG);

	/* Wait until DLL_LOCK bit of DLL_STATUS register becomes '1' */
	while (!(readl_relaxed(host->ioaddr + CORE_DLL_STATUS) &
		 CORE_DLL_LOCK)) {
		/* max. wait for 50us sec for LOCK bit to be set */
		if (--wait_cnt == 0) {
			dev_err(mmc_dev(mmc), "%s: DLL failed to LOCK\n",
			       mmc_hostname(mmc));
			spin_unlock_irqrestore(&host->lock, flags);
			return -ETIMEDOUT;
		}
		udelay(1);
	}

	spin_unlock_irqrestore(&host->lock, flags);
	return 0;
}

static int sdhci_msm_execute_tuning(struct sdhci_host *host, u32 opcode)
{
	int tuning_seq_cnt = 3;
	u8 phase, tuned_phases[16], tuned_phase_cnt = 0;
	int rc;
	struct mmc_host *mmc = host->mmc;
	struct mmc_ios ios = host->mmc->ios;

	/*
	 * Tuning is required for SDR104, HS200 and HS400 cards and
	 * if clock frequency is greater than 100MHz in these modes.
	 */
	if (host->clock <= 100 * 1000 * 1000 ||
	    !((ios.timing == MMC_TIMING_MMC_HS200) ||
	      (ios.timing == MMC_TIMING_UHS_SDR104)))
		return 0;

retry:
	/* First of all reset the tuning block */
	rc = msm_init_cm_dll(host);
	if (rc)
		return rc;

	phase = 0;
	do {
		/* Set the phase in delay line hw block */
		rc = msm_config_cm_dll_phase(host, phase);
		if (rc)
			return rc;

		rc = mmc_send_tuning(mmc, opcode, NULL);
		if (!rc) {
			/* Tuning is successful at this tuning point */
			tuned_phases[tuned_phase_cnt++] = phase;
			dev_dbg(mmc_dev(mmc), "%s: Found good phase = %d\n",
				 mmc_hostname(mmc), phase);
		}
	} while (++phase < ARRAY_SIZE(tuned_phases));

	if (tuned_phase_cnt) {
		rc = msm_find_most_appropriate_phase(host, tuned_phases,
						     tuned_phase_cnt);
		if (rc < 0)
			return rc;
		else
			phase = rc;

		/*
		 * Finally set the selected phase in delay
		 * line hw block.
		 */
		rc = msm_config_cm_dll_phase(host, phase);
		if (rc)
			return rc;
		dev_dbg(mmc_dev(mmc), "%s: Setting the tuning phase to %d\n",
			 mmc_hostname(mmc), phase);
	} else {
		if (--tuning_seq_cnt)
			goto retry;
		/* Tuning failed */
		dev_dbg(mmc_dev(mmc), "%s: No tuning point found\n",
		       mmc_hostname(mmc));
		rc = -EIO;
	}

	return rc;
}

static void sdhci_msm_set_uhs_signaling(struct sdhci_host *host,
					unsigned int uhs)
{
	struct mmc_host *mmc = host->mmc;
	u16 ctrl_2;

	ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
	/* Select Bus Speed Mode for host */
	ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
	switch (uhs) {
	case MMC_TIMING_UHS_SDR12:
		ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
		break;
	case MMC_TIMING_UHS_SDR25:
		ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
		break;
	case MMC_TIMING_UHS_SDR50:
		ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
		break;
	case MMC_TIMING_MMC_HS200:
	case MMC_TIMING_UHS_SDR104:
		ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
		break;
	case MMC_TIMING_UHS_DDR50:
	case MMC_TIMING_MMC_DDR52:
		ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
		break;
	}

	/*
	 * When clock frequency is less than 100MHz, the feedback clock must be
	 * provided and DLL must not be used so that tuning can be skipped. To
	 * provide feedback clock, the mode selection can be any value less
	 * than 3'b011 in bits [2:0] of HOST CONTROL2 register.
	 */
	if (host->clock <= 100000000 &&
	    (uhs == MMC_TIMING_MMC_HS400 ||
	     uhs == MMC_TIMING_MMC_HS200 ||
	     uhs == MMC_TIMING_UHS_SDR104))
		ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;

	dev_dbg(mmc_dev(mmc), "%s: clock=%u uhs=%u ctrl_2=0x%x\n",
		mmc_hostname(host->mmc), host->clock, uhs, ctrl_2);
	sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
}

static const struct of_device_id sdhci_msm_dt_match[] = {
	{ .compatible = "qcom,sdhci-msm-v4" },
	{},
};

MODULE_DEVICE_TABLE(of, sdhci_msm_dt_match);

static const struct sdhci_ops sdhci_msm_ops = {
	.platform_execute_tuning = sdhci_msm_execute_tuning,
	.reset = sdhci_reset,
	.set_clock = sdhci_set_clock,
	.set_bus_width = sdhci_set_bus_width,
	.set_uhs_signaling = sdhci_msm_set_uhs_signaling,
};

static const struct sdhci_pltfm_data sdhci_msm_pdata = {
	.quirks = SDHCI_QUIRK_BROKEN_CARD_DETECTION |
		  SDHCI_QUIRK_NO_CARD_NO_RESET |
		  SDHCI_QUIRK_SINGLE_POWER_WRITE,
	.ops = &sdhci_msm_ops,
};

static int sdhci_msm_probe(struct platform_device *pdev)
{
	struct sdhci_host *host;
	struct sdhci_pltfm_host *pltfm_host;
	struct sdhci_msm_host *msm_host;
	struct resource *core_memres;
	int ret;
	u16 host_version, core_minor;
	u32 core_version, caps;
	u8 core_major;

	host = sdhci_pltfm_init(pdev, &sdhci_msm_pdata, sizeof(*msm_host));
	if (IS_ERR(host))
		return PTR_ERR(host);

	pltfm_host = sdhci_priv(host);
	msm_host = sdhci_pltfm_priv(pltfm_host);
	msm_host->mmc = host->mmc;
	msm_host->pdev = pdev;

	ret = mmc_of_parse(host->mmc);
	if (ret)
		goto pltfm_free;

	sdhci_get_of_property(pdev);

	/* Setup SDCC bus voter clock. */
	msm_host->bus_clk = devm_clk_get(&pdev->dev, "bus");
	if (!IS_ERR(msm_host->bus_clk)) {
		/* Vote for max. clk rate for max. performance */
		ret = clk_set_rate(msm_host->bus_clk, INT_MAX);
		if (ret)
			goto pltfm_free;
		ret = clk_prepare_enable(msm_host->bus_clk);
		if (ret)
			goto pltfm_free;
	}

	/* Setup main peripheral bus clock */
	msm_host->pclk = devm_clk_get(&pdev->dev, "iface");
	if (IS_ERR(msm_host->pclk)) {
		ret = PTR_ERR(msm_host->pclk);
		dev_err(&pdev->dev, "Peripheral clk setup failed (%d)\n", ret);
		goto bus_clk_disable;
	}

	ret = clk_prepare_enable(msm_host->pclk);
	if (ret)
		goto bus_clk_disable;

	/* Setup SDC MMC clock */
	msm_host->clk = devm_clk_get(&pdev->dev, "core");
	if (IS_ERR(msm_host->clk)) {
		ret = PTR_ERR(msm_host->clk);
		dev_err(&pdev->dev, "SDC MMC clk setup failed (%d)\n", ret);
		goto pclk_disable;
	}

	/* Vote for maximum clock rate for maximum performance */
	ret = clk_set_rate(msm_host->clk, INT_MAX);
	if (ret)
		dev_warn(&pdev->dev, "core clock boost failed\n");

	ret = clk_prepare_enable(msm_host->clk);
	if (ret)
		goto pclk_disable;

	core_memres = platform_get_resource(pdev, IORESOURCE_MEM, 1);
	msm_host->core_mem = devm_ioremap_resource(&pdev->dev, core_memres);

	if (IS_ERR(msm_host->core_mem)) {
		dev_err(&pdev->dev, "Failed to remap registers\n");
		ret = PTR_ERR(msm_host->core_mem);
		goto clk_disable;
	}

	/* Reset the core and Enable SDHC mode */
	writel_relaxed(readl_relaxed(msm_host->core_mem + CORE_POWER) |
		       CORE_SW_RST, msm_host->core_mem + CORE_POWER);

	/* SW reset can take upto 10HCLK + 15MCLK cycles. (min 40us) */
	usleep_range(1000, 5000);
	if (readl(msm_host->core_mem + CORE_POWER) & CORE_SW_RST) {
		dev_err(&pdev->dev, "Stuck in reset\n");
		ret = -ETIMEDOUT;
		goto clk_disable;
	}

	/* Set HC_MODE_EN bit in HC_MODE register */
	writel_relaxed(HC_MODE_EN, (msm_host->core_mem + CORE_HC_MODE));

	host_version = readw_relaxed((host->ioaddr + SDHCI_HOST_VERSION));
	dev_dbg(&pdev->dev, "Host Version: 0x%x Vendor Version 0x%x\n",
		host_version, ((host_version & SDHCI_VENDOR_VER_MASK) >>
			       SDHCI_VENDOR_VER_SHIFT));

	core_version = readl_relaxed(msm_host->core_mem + CORE_MCI_VERSION);
	core_major = (core_version & CORE_VERSION_MAJOR_MASK) >>
		      CORE_VERSION_MAJOR_SHIFT;
	core_minor = core_version & CORE_VERSION_MINOR_MASK;
	dev_dbg(&pdev->dev, "MCI Version: 0x%08x, major: 0x%04x, minor: 0x%02x\n",
		core_version, core_major, core_minor);

	/*
	 * Support for some capabilities is not advertised by newer
	 * controller versions and must be explicitly enabled.
	 */
	if (core_major >= 1 && core_minor != 0x11 && core_minor != 0x12) {
		caps = readl_relaxed(host->ioaddr + SDHCI_CAPABILITIES);
		caps |= SDHCI_CAN_VDD_300 | SDHCI_CAN_DO_8BIT;
		writel_relaxed(caps, host->ioaddr +
			       CORE_VENDOR_SPEC_CAPABILITIES0);
	}

	ret = sdhci_add_host(host);
	if (ret)
		goto clk_disable;

	return 0;

clk_disable:
	clk_disable_unprepare(msm_host->clk);
pclk_disable:
	clk_disable_unprepare(msm_host->pclk);
bus_clk_disable:
	if (!IS_ERR(msm_host->bus_clk))
		clk_disable_unprepare(msm_host->bus_clk);
pltfm_free:
	sdhci_pltfm_free(pdev);
	return ret;
}

static int sdhci_msm_remove(struct platform_device *pdev)
{
	struct sdhci_host *host = platform_get_drvdata(pdev);
	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
	struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
	int dead = (readl_relaxed(host->ioaddr + SDHCI_INT_STATUS) ==
		    0xffffffff);

	sdhci_remove_host(host, dead);
	clk_disable_unprepare(msm_host->clk);
	clk_disable_unprepare(msm_host->pclk);
	if (!IS_ERR(msm_host->bus_clk))
		clk_disable_unprepare(msm_host->bus_clk);
	sdhci_pltfm_free(pdev);
	return 0;
}

static struct platform_driver sdhci_msm_driver = {
	.probe = sdhci_msm_probe,
	.remove = sdhci_msm_remove,
	.driver = {
		   .name = "sdhci_msm",
		   .of_match_table = sdhci_msm_dt_match,
	},
};

module_platform_driver(sdhci_msm_driver);

MODULE_DESCRIPTION("Qualcomm Secure Digital Host Controller Interface driver");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
0eb0d9f4 GD	1	/*
	2	* drivers/mmc/host/sdhci-msm.c - Qualcomm SDHCI Platform driver
	3	*
	4	* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License version 2 and
	8	* only version 2 as published by the Free Software Foundation.
	9	*
	10	* This program is distributed in the hope that it will be useful,
	11	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	* GNU General Public License for more details.
	14	*
	15	*/
	16
	17	#include <linux/module.h>
	18	#include <linux/of_device.h>
0eb0d9f4	19	#include <linux/delay.h>
415b5a75 GD	20	#include <linux/mmc/mmc.h>
415b5a75 GD	21	#include <linux/slab.h>
0eb0d9f4 GD	22
	23	#include "sdhci-pltfm.h"
	24
3a3ad3e9 GD	25	#define CORE_MCI_VERSION 0x50
	26	#define CORE_VERSION_MAJOR_SHIFT 28
	27	#define CORE_VERSION_MAJOR_MASK (0xf << CORE_VERSION_MAJOR_SHIFT)
	28	#define CORE_VERSION_MINOR_MASK 0xff
	29
0eb0d9f4 GD	30	#define CORE_HC_MODE 0x78
	31	#define HC_MODE_EN 0x1
	32	#define CORE_POWER 0x0
	33	#define CORE_SW_RST BIT(7)
	34
415b5a75 GD	35	#define MAX_PHASES 16
	36	#define CORE_DLL_LOCK BIT(7)
	37	#define CORE_DLL_EN BIT(16)
	38	#define CORE_CDR_EN BIT(17)
	39	#define CORE_CK_OUT_EN BIT(18)
	40	#define CORE_CDR_EXT_EN BIT(19)
	41	#define CORE_DLL_PDN BIT(29)
	42	#define CORE_DLL_RST BIT(30)
	43	#define CORE_DLL_CONFIG 0x100
	44	#define CORE_DLL_STATUS 0x108
	45
	46	#define CORE_VENDOR_SPEC 0x10c
	47	#define CORE_CLK_PWRSAVE BIT(1)
	48
3a3ad3e9 GD	49	#define CORE_VENDOR_SPEC_CAPABILITIES0 0x11c
3a3ad3e9 GD	50
415b5a75 GD	51	#define CDR_SELEXT_SHIFT 20
	52	#define CDR_SELEXT_MASK (0xf << CDR_SELEXT_SHIFT)
	53	#define CMUX_SHIFT_PHASE_SHIFT 24
	54	#define CMUX_SHIFT_PHASE_MASK (7 << CMUX_SHIFT_PHASE_SHIFT)
	55
0eb0d9f4 GD	56	struct sdhci_msm_host {
	57	struct platform_device *pdev;
	58	void __iomem core_mem; / MSM SDCC mapped address */
	59	struct clk clk; / main SD/MMC bus clock */
	60	struct clk pclk; / SDHC peripheral bus clock */
	61	struct clk bus_clk; / SDHC bus voter clock */
	62	struct mmc_host *mmc;
0eb0d9f4 GD	63	};
	64
	65	/* Platform specific tuning */
415b5a75 GD	66	static inline int msm_dll_poll_ck_out_en(struct sdhci_host *host, u8 poll)
	67	{
	68	u32 wait_cnt = 50;
	69	u8 ck_out_en;
	70	struct mmc_host *mmc = host->mmc;
	71
	72	/* Poll for CK_OUT_EN bit. max. poll time = 50us */
	73	ck_out_en = !!(readl_relaxed(host->ioaddr + CORE_DLL_CONFIG) &
	74	CORE_CK_OUT_EN);
	75
	76	while (ck_out_en != poll) {
	77	if (--wait_cnt == 0) {
	78	dev_err(mmc_dev(mmc), "%s: CK_OUT_EN bit is not %d\n",
	79	mmc_hostname(mmc), poll);
	80	return -ETIMEDOUT;
	81	}
	82	udelay(1);
	83
	84	ck_out_en = !!(readl_relaxed(host->ioaddr + CORE_DLL_CONFIG) &
	85	CORE_CK_OUT_EN);
	86	}
	87
	88	return 0;
	89	}
	90
	91	static int msm_config_cm_dll_phase(struct sdhci_host *host, u8 phase)
	92	{
	93	int rc;
	94	static const u8 grey_coded_phase_table[] = {
	95	0x0, 0x1, 0x3, 0x2, 0x6, 0x7, 0x5, 0x4,
	96	0xc, 0xd, 0xf, 0xe, 0xa, 0xb, 0x9, 0x8
	97	};
	98	unsigned long flags;
	99	u32 config;
	100	struct mmc_host *mmc = host->mmc;
	101
	102	spin_lock_irqsave(&host->lock, flags);
	103
	104	config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
	105	config &= ~(CORE_CDR_EN \| CORE_CK_OUT_EN);
	106	config \|= (CORE_CDR_EXT_EN \| CORE_DLL_EN);
	107	writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
	108
	109	/* Wait until CK_OUT_EN bit of DLL_CONFIG register becomes '0' */
	110	rc = msm_dll_poll_ck_out_en(host, 0);
	111	if (rc)
	112	goto err_out;
	113
	114	/*
	115	* Write the selected DLL clock output phase (0 ... 15)
	116	* to CDR_SELEXT bit field of DLL_CONFIG register.
	117	*/
	118	config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
	119	config &= ~CDR_SELEXT_MASK;
	120	config \|= grey_coded_phase_table[phase] << CDR_SELEXT_SHIFT;
	121	writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
	122
	123	/* Set CK_OUT_EN bit of DLL_CONFIG register to 1. */
	124	writel_relaxed((readl_relaxed(host->ioaddr + CORE_DLL_CONFIG)
	125	\| CORE_CK_OUT_EN), host->ioaddr + CORE_DLL_CONFIG);
	126
	127	/* Wait until CK_OUT_EN bit of DLL_CONFIG register becomes '1' */
	128	rc = msm_dll_poll_ck_out_en(host, 1);
	129	if (rc)
130	goto err_out;
131
132	config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
133	config \|= CORE_CDR_EN;
134	config &= ~CORE_CDR_EXT_EN;
135	writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
136	goto out;
137
138	err_out:
139	dev_err(mmc_dev(mmc), "%s: Failed to set DLL phase: %d\n",
140	mmc_hostname(mmc), phase);
141	out:
142	spin_unlock_irqrestore(&host->lock, flags);
143	return rc;
144	}
145
146	/*
147	* Find out the greatest range of consecuitive selected
148	* DLL clock output phases that can be used as sampling
149	* setting for SD3.0 UHS-I card read operation (in SDR104
150	* timing mode) or for eMMC4.5 card read operation (in HS200
151	* timing mode).
152	* Select the 3/4 of the range and configure the DLL with the
153	* selected DLL clock output phase.
154	*/
155
156	static int msm_find_most_appropriate_phase(struct sdhci_host *host,
157	u8 *phase_table, u8 total_phases)
158	{
159	int ret;
160	u8 ranges[MAX_PHASES][MAX_PHASES] = { {0}, {0} };
161	u8 phases_per_row[MAX_PHASES] = { 0 };
162	int row_index = 0, col_index = 0, selected_row_index = 0, curr_max = 0;
163	int i, cnt, phase_0_raw_index = 0, phase_15_raw_index = 0;
164	bool phase_0_found = false, phase_15_found = false;
165	struct mmc_host *mmc = host->mmc;
166
167	if (!total_phases \|\| (total_phases > MAX_PHASES)) {
168	dev_err(mmc_dev(mmc), "%s: Invalid argument: total_phases=%d\n",
169	mmc_hostname(mmc), total_phases);
170	return -EINVAL;
171	}
172
173	for (cnt = 0; cnt < total_phases; cnt++) {
174	ranges[row_index][col_index] = phase_table[cnt];
175	phases_per_row[row_index] += 1;
176	col_index++;
177
178	if ((cnt + 1) == total_phases) {
179	continue;
180	/* check if next phase in phase_table is consecutive or not */
181	} else if ((phase_table[cnt] + 1) != phase_table[cnt + 1]) {
182	row_index++;
183	col_index = 0;
184	}
185	}
186
187	if (row_index >= MAX_PHASES)
188	return -EINVAL;
189
190	/* Check if phase-0 is present in first valid window? */
191	if (!ranges[0][0]) {
192	phase_0_found = true;
193	phase_0_raw_index = 0;
194	/* Check if cycle exist between 2 valid windows */
195	for (cnt = 1; cnt <= row_index; cnt++) {
196	if (phases_per_row[cnt]) {
197	for (i = 0; i < phases_per_row[cnt]; i++) {
198	if (ranges[cnt][i] == 15) {
199	phase_15_found = true;
200	phase_15_raw_index = cnt;
201	break;
202	}
203	}
204	}
205	}
206	}
207
208	/* If 2 valid windows form cycle then merge them as single window */
209	if (phase_0_found && phase_15_found) {
210	/* number of phases in raw where phase 0 is present */
211	u8 phases_0 = phases_per_row[phase_0_raw_index];
212	/* number of phases in raw where phase 15 is present */
213	u8 phases_15 = phases_per_row[phase_15_raw_index];
214
215	if (phases_0 + phases_15 >= MAX_PHASES)
216	/*
217	* If there are more than 1 phase windows then total
218	* number of phases in both the windows should not be
219	* more than or equal to MAX_PHASES.
220	*/
221	return -EINVAL;
222
223	/* Merge 2 cyclic windows */
224	i = phases_15;
225	for (cnt = 0; cnt < phases_0; cnt++) {
226	ranges[phase_15_raw_index][i] =
227	ranges[phase_0_raw_index][cnt];
228	if (++i >= MAX_PHASES)
229	break;
230	}
231
232	phases_per_row[phase_0_raw_index] = 0;
233	phases_per_row[phase_15_raw_index] = phases_15 + phases_0;
234	}
235
236	for (cnt = 0; cnt <= row_index; cnt++) {
237	if (phases_per_row[cnt] > curr_max) {
238	curr_max = phases_per_row[cnt];
239	selected_row_index = cnt;
240	}
241	}
242
243	i = (curr_max * 3) / 4;
244	if (i)
245	i--;
246
247	ret = ranges[selected_row_index][i];
248
249	if (ret >= MAX_PHASES) {
250	ret = -EINVAL;
251	dev_err(mmc_dev(mmc), "%s: Invalid phase selected=%d\n",
252	mmc_hostname(mmc), ret);
253	}
254
255	return ret;
256	}
257
258	static inline void msm_cm_dll_set_freq(struct sdhci_host *host)
0eb0d9f4	259	{
415b5a75 GD	260	u32 mclk_freq = 0, config;
	261
	262	/* Program the MCLK value to MCLK_FREQ bit field */
	263	if (host->clock <= 112000000)
	264	mclk_freq = 0;
	265	else if (host->clock <= 125000000)
	266	mclk_freq = 1;
	267	else if (host->clock <= 137000000)
	268	mclk_freq = 2;
	269	else if (host->clock <= 150000000)
	270	mclk_freq = 3;
	271	else if (host->clock <= 162000000)
	272	mclk_freq = 4;
	273	else if (host->clock <= 175000000)
	274	mclk_freq = 5;
	275	else if (host->clock <= 187000000)
	276	mclk_freq = 6;
	277	else if (host->clock <= 200000000)
	278	mclk_freq = 7;
	279
	280	config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
	281	config &= ~CMUX_SHIFT_PHASE_MASK;
	282	config \|= mclk_freq << CMUX_SHIFT_PHASE_SHIFT;
	283	writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
	284	}
	285
	286	/* Initialize the DLL (Programmable Delay Line) */
	287	static int msm_init_cm_dll(struct sdhci_host *host)
	288	{
	289	struct mmc_host *mmc = host->mmc;
	290	int wait_cnt = 50;
	291	unsigned long flags;
	292
	293	spin_lock_irqsave(&host->lock, flags);
	294
0eb0d9f4	295	/*
415b5a75 GD	296	* Make sure that clock is always enabled when DLL
	297	* tuning is in progress. Keeping PWRSAVE ON may
	298	* turn off the clock.
0eb0d9f4	299	*/
415b5a75 GD	300	writel_relaxed((readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC)
	301	& ~CORE_CLK_PWRSAVE), host->ioaddr + CORE_VENDOR_SPEC);
	302
	303	/* Write 1 to DLL_RST bit of DLL_CONFIG register */
	304	writel_relaxed((readl_relaxed(host->ioaddr + CORE_DLL_CONFIG)
	305	\| CORE_DLL_RST), host->ioaddr + CORE_DLL_CONFIG);
	306
	307	/* Write 1 to DLL_PDN bit of DLL_CONFIG register */
	308	writel_relaxed((readl_relaxed(host->ioaddr + CORE_DLL_CONFIG)
	309	\| CORE_DLL_PDN), host->ioaddr + CORE_DLL_CONFIG);
	310	msm_cm_dll_set_freq(host);
	311
	312	/* Write 0 to DLL_RST bit of DLL_CONFIG register */
	313	writel_relaxed((readl_relaxed(host->ioaddr + CORE_DLL_CONFIG)
	314	& ~CORE_DLL_RST), host->ioaddr + CORE_DLL_CONFIG);
	315
	316	/* Write 0 to DLL_PDN bit of DLL_CONFIG register */
	317	writel_relaxed((readl_relaxed(host->ioaddr + CORE_DLL_CONFIG)
	318	& ~CORE_DLL_PDN), host->ioaddr + CORE_DLL_CONFIG);
	319
	320	/* Set DLL_EN bit to 1. */
	321	writel_relaxed((readl_relaxed(host->ioaddr + CORE_DLL_CONFIG)
	322	\| CORE_DLL_EN), host->ioaddr + CORE_DLL_CONFIG);
	323
	324	/* Set CK_OUT_EN bit to 1. */
	325	writel_relaxed((readl_relaxed(host->ioaddr + CORE_DLL_CONFIG)
	326	\| CORE_CK_OUT_EN), host->ioaddr + CORE_DLL_CONFIG);
	327
	328	/* Wait until DLL_LOCK bit of DLL_STATUS register becomes '1' */
	329	while (!(readl_relaxed(host->ioaddr + CORE_DLL_STATUS) &
	330	CORE_DLL_LOCK)) {
	331	/* max. wait for 50us sec for LOCK bit to be set */
	332	if (--wait_cnt == 0) {
	333	dev_err(mmc_dev(mmc), "%s: DLL failed to LOCK\n",
	334	mmc_hostname(mmc));
	335	spin_unlock_irqrestore(&host->lock, flags);
	336	return -ETIMEDOUT;
	337	}
	338	udelay(1);
	339	}
	340
	341	spin_unlock_irqrestore(&host->lock, flags);
0eb0d9f4 GD	342	return 0;
	343	}
	344
415b5a75 GD	345	static int sdhci_msm_execute_tuning(struct sdhci_host *host, u32 opcode)
	346	{
	347	int tuning_seq_cnt = 3;
33d73935	348	u8 phase, tuned_phases[16], tuned_phase_cnt = 0;
415b5a75 GD	349	int rc;
	350	struct mmc_host *mmc = host->mmc;
	351	struct mmc_ios ios = host->mmc->ios;
	352
	353	/*
	354	* Tuning is required for SDR104, HS200 and HS400 cards and
	355	* if clock frequency is greater than 100MHz in these modes.
	356	*/
	357	if (host->clock <= 100 * 1000 * 1000 \|\|
	358	!((ios.timing == MMC_TIMING_MMC_HS200) \|\|
	359	(ios.timing == MMC_TIMING_UHS_SDR104)))
	360	return 0;
	361
415b5a75 GD	362	retry:
	363	/* First of all reset the tuning block */
	364	rc = msm_init_cm_dll(host);
	365	if (rc)
33d73935	366	return rc;
415b5a75 GD	367
	368	phase = 0;
	369	do {
415b5a75 GD	370	/* Set the phase in delay line hw block */
	371	rc = msm_config_cm_dll_phase(host, phase);
	372	if (rc)
33d73935	373	return rc;
415b5a75	374
9979dbe5	375	rc = mmc_send_tuning(mmc, opcode, NULL);
33d73935	376	if (!rc) {
415b5a75 GD	377	/* Tuning is successful at this tuning point */
	378	tuned_phases[tuned_phase_cnt++] = phase;
	379	dev_dbg(mmc_dev(mmc), "%s: Found good phase = %d\n",
	380	mmc_hostname(mmc), phase);
	381	}
	382	} while (++phase < ARRAY_SIZE(tuned_phases));
	383
	384	if (tuned_phase_cnt) {
	385	rc = msm_find_most_appropriate_phase(host, tuned_phases,
	386	tuned_phase_cnt);
	387	if (rc < 0)
33d73935	388	return rc;
415b5a75 GD	389	else
	390	phase = rc;
	391
	392	/*
	393	* Finally set the selected phase in delay
	394	* line hw block.
	395	*/
	396	rc = msm_config_cm_dll_phase(host, phase);
	397	if (rc)
33d73935	398	return rc;
415b5a75 GD	399	dev_dbg(mmc_dev(mmc), "%s: Setting the tuning phase to %d\n",
	400	mmc_hostname(mmc), phase);
	401	} else {
	402	if (--tuning_seq_cnt)
	403	goto retry;
	404	/* Tuning failed */
	405	dev_dbg(mmc_dev(mmc), "%s: No tuning point found\n",
	406	mmc_hostname(mmc));
	407	rc = -EIO;
	408	}
	409
415b5a75 GD	410	return rc;
	411	}
	412
ee320674 RH	413	static void sdhci_msm_set_uhs_signaling(struct sdhci_host *host,
	414	unsigned int uhs)
	415	{
	416	struct mmc_host *mmc = host->mmc;
	417	u16 ctrl_2;
	418
	419	ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
	420	/* Select Bus Speed Mode for host */
	421	ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
	422	switch (uhs) {
	423	case MMC_TIMING_UHS_SDR12:
	424	ctrl_2 \|= SDHCI_CTRL_UHS_SDR12;
	425	break;
	426	case MMC_TIMING_UHS_SDR25:
	427	ctrl_2 \|= SDHCI_CTRL_UHS_SDR25;
	428	break;
	429	case MMC_TIMING_UHS_SDR50:
	430	ctrl_2 \|= SDHCI_CTRL_UHS_SDR50;
	431	break;
	432	case MMC_TIMING_MMC_HS200:
	433	case MMC_TIMING_UHS_SDR104:
	434	ctrl_2 \|= SDHCI_CTRL_UHS_SDR104;
	435	break;
	436	case MMC_TIMING_UHS_DDR50:
	437	case MMC_TIMING_MMC_DDR52:
	438	ctrl_2 \|= SDHCI_CTRL_UHS_DDR50;
	439	break;
	440	}
	441
	442	/*
	443	* When clock frequency is less than 100MHz, the feedback clock must be
	444	* provided and DLL must not be used so that tuning can be skipped. To
	445	* provide feedback clock, the mode selection can be any value less
	446	* than 3'b011 in bits [2:0] of HOST CONTROL2 register.
	447	*/
	448	if (host->clock <= 100000000 &&
	449	(uhs == MMC_TIMING_MMC_HS400 \|\|
	450	uhs == MMC_TIMING_MMC_HS200 \|\|
	451	uhs == MMC_TIMING_UHS_SDR104))
	452	ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
	453
	454	dev_dbg(mmc_dev(mmc), "%s: clock=%u uhs=%u ctrl_2=0x%x\n",
	455	mmc_hostname(host->mmc), host->clock, uhs, ctrl_2);
	456	sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
	457	}
	458
0eb0d9f4 GD	459	static const struct of_device_id sdhci_msm_dt_match[] = {
	460	{ .compatible = "qcom,sdhci-msm-v4" },
	461	{},
	462	};
	463
	464	MODULE_DEVICE_TABLE(of, sdhci_msm_dt_match);
	465
a50396a4	466	static const struct sdhci_ops sdhci_msm_ops = {
0eb0d9f4	467	.platform_execute_tuning = sdhci_msm_execute_tuning,
ed1761d7 SB	468	.reset = sdhci_reset,
	469	.set_clock = sdhci_set_clock,
	470	.set_bus_width = sdhci_set_bus_width,
ee320674	471	.set_uhs_signaling = sdhci_msm_set_uhs_signaling,
0eb0d9f4 GD	472	};
0eb0d9f4 GD	473
a50396a4 JZ	474	static const struct sdhci_pltfm_data sdhci_msm_pdata = {
a50396a4 JZ	475	.quirks = SDHCI_QUIRK_BROKEN_CARD_DETECTION \|
9718f84b	476	SDHCI_QUIRK_NO_CARD_NO_RESET \|
a50396a4 JZ	477	SDHCI_QUIRK_SINGLE_POWER_WRITE,
	478	.ops = &sdhci_msm_ops,
	479	};
	480
0eb0d9f4 GD	481	static int sdhci_msm_probe(struct platform_device *pdev)
	482	{
	483	struct sdhci_host *host;
	484	struct sdhci_pltfm_host *pltfm_host;
	485	struct sdhci_msm_host *msm_host;
	486	struct resource *core_memres;
	487	int ret;
3a3ad3e9 GD	488	u16 host_version, core_minor;
	489	u32 core_version, caps;
	490	u8 core_major;
0eb0d9f4	491
6f699531	492	host = sdhci_pltfm_init(pdev, &sdhci_msm_pdata, sizeof(*msm_host));
0eb0d9f4 GD	493	if (IS_ERR(host))
	494	return PTR_ERR(host);
	495
	496	pltfm_host = sdhci_priv(host);
6f699531	497	msm_host = sdhci_pltfm_priv(pltfm_host);
0eb0d9f4 GD	498	msm_host->mmc = host->mmc;
	499	msm_host->pdev = pdev;
	500
	501	ret = mmc_of_parse(host->mmc);
	502	if (ret)
	503	goto pltfm_free;
	504
	505	sdhci_get_of_property(pdev);
	506
	507	/* Setup SDCC bus voter clock. */
	508	msm_host->bus_clk = devm_clk_get(&pdev->dev, "bus");
	509	if (!IS_ERR(msm_host->bus_clk)) {
	510	/* Vote for max. clk rate for max. performance */
	511	ret = clk_set_rate(msm_host->bus_clk, INT_MAX);
	512	if (ret)
	513	goto pltfm_free;
	514	ret = clk_prepare_enable(msm_host->bus_clk);
	515	if (ret)
	516	goto pltfm_free;
	517	}
	518
	519	/* Setup main peripheral bus clock */
	520	msm_host->pclk = devm_clk_get(&pdev->dev, "iface");
	521	if (IS_ERR(msm_host->pclk)) {
	522	ret = PTR_ERR(msm_host->pclk);
2801b95e	523	dev_err(&pdev->dev, "Peripheral clk setup failed (%d)\n", ret);
0eb0d9f4 GD	524	goto bus_clk_disable;
	525	}
	526
	527	ret = clk_prepare_enable(msm_host->pclk);
	528	if (ret)
	529	goto bus_clk_disable;
	530
	531	/* Setup SDC MMC clock */
	532	msm_host->clk = devm_clk_get(&pdev->dev, "core");
	533	if (IS_ERR(msm_host->clk)) {
	534	ret = PTR_ERR(msm_host->clk);
	535	dev_err(&pdev->dev, "SDC MMC clk setup failed (%d)\n", ret);
	536	goto pclk_disable;
	537	}
	538
951b8c87 II	539	/* Vote for maximum clock rate for maximum performance */
	540	ret = clk_set_rate(msm_host->clk, INT_MAX);
	541	if (ret)
	542	dev_warn(&pdev->dev, "core clock boost failed\n");
	543
0eb0d9f4 GD	544	ret = clk_prepare_enable(msm_host->clk);
	545	if (ret)
	546	goto pclk_disable;
	547
	548	core_memres = platform_get_resource(pdev, IORESOURCE_MEM, 1);
	549	msm_host->core_mem = devm_ioremap_resource(&pdev->dev, core_memres);
	550
	551	if (IS_ERR(msm_host->core_mem)) {
	552	dev_err(&pdev->dev, "Failed to remap registers\n");
	553	ret = PTR_ERR(msm_host->core_mem);
	554	goto clk_disable;
	555	}
	556
	557	/* Reset the core and Enable SDHC mode */
	558	writel_relaxed(readl_relaxed(msm_host->core_mem + CORE_POWER) \|
	559	CORE_SW_RST, msm_host->core_mem + CORE_POWER);
	560
	561	/* SW reset can take upto 10HCLK + 15MCLK cycles. (min 40us) */
	562	usleep_range(1000, 5000);
	563	if (readl(msm_host->core_mem + CORE_POWER) & CORE_SW_RST) {
	564	dev_err(&pdev->dev, "Stuck in reset\n");
	565	ret = -ETIMEDOUT;
	566	goto clk_disable;
	567	}
	568
	569	/* Set HC_MODE_EN bit in HC_MODE register */
	570	writel_relaxed(HC_MODE_EN, (msm_host->core_mem + CORE_HC_MODE));
	571
0eb0d9f4 GD	572	host_version = readw_relaxed((host->ioaddr + SDHCI_HOST_VERSION));
	573	dev_dbg(&pdev->dev, "Host Version: 0x%x Vendor Version 0x%x\n",
	574	host_version, ((host_version & SDHCI_VENDOR_VER_MASK) >>
	575	SDHCI_VENDOR_VER_SHIFT));
	576
3a3ad3e9 GD	577	core_version = readl_relaxed(msm_host->core_mem + CORE_MCI_VERSION);
	578	core_major = (core_version & CORE_VERSION_MAJOR_MASK) >>
	579	CORE_VERSION_MAJOR_SHIFT;
	580	core_minor = core_version & CORE_VERSION_MINOR_MASK;
	581	dev_dbg(&pdev->dev, "MCI Version: 0x%08x, major: 0x%04x, minor: 0x%02x\n",
	582	core_version, core_major, core_minor);
	583
	584	/*
	585	* Support for some capabilities is not advertised by newer
	586	* controller versions and must be explicitly enabled.
	587	*/
	588	if (core_major >= 1 && core_minor != 0x11 && core_minor != 0x12) {
	589	caps = readl_relaxed(host->ioaddr + SDHCI_CAPABILITIES);
	590	caps \|= SDHCI_CAN_VDD_300 \| SDHCI_CAN_DO_8BIT;
	591	writel_relaxed(caps, host->ioaddr +
	592	CORE_VENDOR_SPEC_CAPABILITIES0);
	593	}
	594
0eb0d9f4 GD	595	ret = sdhci_add_host(host);
	596	if (ret)
	597	goto clk_disable;
	598
	599	return 0;
	600
	601	clk_disable:
	602	clk_disable_unprepare(msm_host->clk);
	603	pclk_disable:
	604	clk_disable_unprepare(msm_host->pclk);
	605	bus_clk_disable:
	606	if (!IS_ERR(msm_host->bus_clk))
	607	clk_disable_unprepare(msm_host->bus_clk);
	608	pltfm_free:
	609	sdhci_pltfm_free(pdev);
	610	return ret;
	611	}
	612
	613	static int sdhci_msm_remove(struct platform_device *pdev)
	614	{
	615	struct sdhci_host *host = platform_get_drvdata(pdev);
	616	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
6f699531	617	struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
0eb0d9f4 GD	618	int dead = (readl_relaxed(host->ioaddr + SDHCI_INT_STATUS) ==
	619	0xffffffff);
	620
	621	sdhci_remove_host(host, dead);
0eb0d9f4 GD	622	clk_disable_unprepare(msm_host->clk);
	623	clk_disable_unprepare(msm_host->pclk);
	624	if (!IS_ERR(msm_host->bus_clk))
	625	clk_disable_unprepare(msm_host->bus_clk);
6f699531	626	sdhci_pltfm_free(pdev);
0eb0d9f4 GD	627	return 0;
	628	}
	629
	630	static struct platform_driver sdhci_msm_driver = {
	631	.probe = sdhci_msm_probe,
	632	.remove = sdhci_msm_remove,
	633	.driver = {
	634	.name = "sdhci_msm",
0eb0d9f4 GD	635	.of_match_table = sdhci_msm_dt_match,
	636	},
	637	};
	638
	639	module_platform_driver(sdhci_msm_driver);
	640
	641	MODULE_DESCRIPTION("Qualcomm Secure Digital Host Controller Interface driver");
	642	MODULE_LICENSE("GPL v2");