[mirror_ubuntu-eoan-kernel.git] / drivers / mmc / host / sdhci-of-arasan.c

/*
 * Arasan Secure Digital Host Controller Interface.
 * Copyright (C) 2011 - 2012 Michal Simek <monstr@monstr.eu>
 * Copyright (c) 2012 Wind River Systems, Inc.
 * Copyright (C) 2013 Pengutronix e.K.
 * Copyright (C) 2013 Xilinx Inc.
 *
 * Based on sdhci-of-esdhc.c
 *
 * Copyright (c) 2007 Freescale Semiconductor, Inc.
 * Copyright (c) 2009 MontaVista Software, Inc.
 *
 * Authors: Xiaobo Xie <X.Xie@freescale.com>
 *	    Anton Vorontsov <avorontsov@ru.mvista.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or (at
 * your option) any later version.
 */

#include <linux/module.h>
#include <linux/of_device.h>
#include "sdhci-pltfm.h"

#define SDHCI_ARASAN_CLK_CTRL_OFFSET	0x2c

#define CLK_CTRL_TIMEOUT_SHIFT		16
#define CLK_CTRL_TIMEOUT_MASK		(0xf << CLK_CTRL_TIMEOUT_SHIFT)
#define CLK_CTRL_TIMEOUT_MIN_EXP	13

/**
 * struct sdhci_arasan_data
 * @clk_ahb:	Pointer to the AHB clock
 */
struct sdhci_arasan_data {
	struct clk	*clk_ahb;
};

static unsigned int sdhci_arasan_get_timeout_clock(struct sdhci_host *host)
{
	u32 div;
	unsigned long freq;
	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);

	div = readl(host->ioaddr + SDHCI_ARASAN_CLK_CTRL_OFFSET);
	div = (div & CLK_CTRL_TIMEOUT_MASK) >> CLK_CTRL_TIMEOUT_SHIFT;

	freq = clk_get_rate(pltfm_host->clk);
	freq /= 1 << (CLK_CTRL_TIMEOUT_MIN_EXP + div);

	return freq;
}

static struct sdhci_ops sdhci_arasan_ops = {
	.set_clock = sdhci_set_clock,
	.get_max_clock = sdhci_pltfm_clk_get_max_clock,
	.get_timeout_clock = sdhci_arasan_get_timeout_clock,
	.set_bus_width = sdhci_set_bus_width,
	.reset = sdhci_reset,
	.set_uhs_signaling = sdhci_set_uhs_signaling,
};

static struct sdhci_pltfm_data sdhci_arasan_pdata = {
	.ops = &sdhci_arasan_ops,
	.quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
	.quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
			SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN,
};

#ifdef CONFIG_PM_SLEEP
/**
 * sdhci_arasan_suspend - Suspend method for the driver
 * @dev:	Address of the device structure
 * Returns 0 on success and error value on error
 *
 * Put the device in a low power state.
 */
static int sdhci_arasan_suspend(struct device *dev)
{
	struct platform_device *pdev = to_platform_device(dev);
	struct sdhci_host *host = platform_get_drvdata(pdev);
	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
	struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
	int ret;

	ret = sdhci_suspend_host(host);
	if (ret)
		return ret;

	clk_disable(pltfm_host->clk);
	clk_disable(sdhci_arasan->clk_ahb);

	return 0;
}

/**
 * sdhci_arasan_resume - Resume method for the driver
 * @dev:	Address of the device structure
 * Returns 0 on success and error value on error
 *
 * Resume operation after suspend
 */
static int sdhci_arasan_resume(struct device *dev)
{
	struct platform_device *pdev = to_platform_device(dev);
	struct sdhci_host *host = platform_get_drvdata(pdev);
	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
	struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
	int ret;

	ret = clk_enable(sdhci_arasan->clk_ahb);
	if (ret) {
		dev_err(dev, "Cannot enable AHB clock.\n");
		return ret;
	}

	ret = clk_enable(pltfm_host->clk);
	if (ret) {
		dev_err(dev, "Cannot enable SD clock.\n");
		return ret;
	}

	return sdhci_resume_host(host);
}
#endif /* ! CONFIG_PM_SLEEP */

static SIMPLE_DEV_PM_OPS(sdhci_arasan_dev_pm_ops, sdhci_arasan_suspend,
			 sdhci_arasan_resume);

static int sdhci_arasan_probe(struct platform_device *pdev)
{
	int ret;
	struct clk *clk_xin;
	struct sdhci_host *host;
	struct sdhci_pltfm_host *pltfm_host;
	struct sdhci_arasan_data *sdhci_arasan;

	host = sdhci_pltfm_init(pdev, &sdhci_arasan_pdata,
				sizeof(*sdhci_arasan));
	if (IS_ERR(host))
		return PTR_ERR(host);

	pltfm_host = sdhci_priv(host);
	sdhci_arasan = sdhci_pltfm_priv(pltfm_host);

	sdhci_arasan->clk_ahb = devm_clk_get(&pdev->dev, "clk_ahb");
	if (IS_ERR(sdhci_arasan->clk_ahb)) {
		dev_err(&pdev->dev, "clk_ahb clock not found.\n");
		return PTR_ERR(sdhci_arasan->clk_ahb);
	}

	clk_xin = devm_clk_get(&pdev->dev, "clk_xin");
	if (IS_ERR(clk_xin)) {
		dev_err(&pdev->dev, "clk_xin clock not found.\n");
		return PTR_ERR(clk_xin);
	}

	ret = clk_prepare_enable(sdhci_arasan->clk_ahb);
	if (ret) {
		dev_err(&pdev->dev, "Unable to enable AHB clock.\n");
		return ret;
	}

	ret = clk_prepare_enable(clk_xin);
	if (ret) {
		dev_err(&pdev->dev, "Unable to enable SD clock.\n");
		goto clk_dis_ahb;
	}

	sdhci_get_of_property(pdev);
	pltfm_host->clk = clk_xin;

	ret = mmc_of_parse(host->mmc);
	if (ret) {
		dev_err(&pdev->dev, "parsing dt failed (%u)\n", ret);
		goto clk_disable_all;
	}

	ret = sdhci_add_host(host);
	if (ret)
		goto err_pltfm_free;

	return 0;

err_pltfm_free:
	sdhci_pltfm_free(pdev);
clk_disable_all:
	clk_disable_unprepare(clk_xin);
clk_dis_ahb:
	clk_disable_unprepare(sdhci_arasan->clk_ahb);

	return ret;
}

static int sdhci_arasan_remove(struct platform_device *pdev)
{
	int ret;
	struct sdhci_host *host = platform_get_drvdata(pdev);
	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
	struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
	struct clk *clk_ahb = sdhci_arasan->clk_ahb;

	ret = sdhci_pltfm_unregister(pdev);

	clk_disable_unprepare(clk_ahb);

	return ret;
}

static const struct of_device_id sdhci_arasan_of_match[] = {
	{ .compatible = "arasan,sdhci-8.9a" },
	{ .compatible = "arasan,sdhci-5.1" },
	{ .compatible = "arasan,sdhci-4.9a" },
	{ }
};
MODULE_DEVICE_TABLE(of, sdhci_arasan_of_match);

static struct platform_driver sdhci_arasan_driver = {
	.driver = {
		.name = "sdhci-arasan",
		.of_match_table = sdhci_arasan_of_match,
		.pm = &sdhci_arasan_dev_pm_ops,
	},
	.probe = sdhci_arasan_probe,
	.remove = sdhci_arasan_remove,
};

module_platform_driver(sdhci_arasan_driver);

MODULE_DESCRIPTION("Driver for the Arasan SDHCI Controller");
MODULE_AUTHOR("Soeren Brinkmann <soren.brinkmann@xilinx.com>");
MODULE_LICENSE("GPL");
Commit	Line	Data
e3ec3a3d SB	1	/*
	2	* Arasan Secure Digital Host Controller Interface.
	3	* Copyright (C) 2011 - 2012 Michal Simek <monstr@monstr.eu>
	4	* Copyright (c) 2012 Wind River Systems, Inc.
	5	* Copyright (C) 2013 Pengutronix e.K.
	6	* Copyright (C) 2013 Xilinx Inc.
	7	*
	8	* Based on sdhci-of-esdhc.c
	9	*
	10	* Copyright (c) 2007 Freescale Semiconductor, Inc.
	11	* Copyright (c) 2009 MontaVista Software, Inc.
	12	*
	13	* Authors: Xiaobo Xie <X.Xie@freescale.com>
	14	* Anton Vorontsov <avorontsov@ru.mvista.com>
	15	*
	16	* This program is free software; you can redistribute it and/or modify
	17	* it under the terms of the GNU General Public License as published by
	18	* the Free Software Foundation; either version 2 of the License, or (at
	19	* your option) any later version.
	20	*/
	21
	22	#include <linux/module.h>
308f3f8d	23	#include <linux/of_device.h>
e3ec3a3d SB	24	#include "sdhci-pltfm.h"
	25
	26	#define SDHCI_ARASAN_CLK_CTRL_OFFSET 0x2c
	27
	28	#define CLK_CTRL_TIMEOUT_SHIFT 16
	29	#define CLK_CTRL_TIMEOUT_MASK (0xf << CLK_CTRL_TIMEOUT_SHIFT)
	30	#define CLK_CTRL_TIMEOUT_MIN_EXP 13
	31
	32	/**
	33	* struct sdhci_arasan_data
	34	* @clk_ahb: Pointer to the AHB clock
	35	*/
	36	struct sdhci_arasan_data {
	37	struct clk *clk_ahb;
	38	};
	39
	40	static unsigned int sdhci_arasan_get_timeout_clock(struct sdhci_host *host)
	41	{
	42	u32 div;
	43	unsigned long freq;
	44	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
	45
	46	div = readl(host->ioaddr + SDHCI_ARASAN_CLK_CTRL_OFFSET);
	47	div = (div & CLK_CTRL_TIMEOUT_MASK) >> CLK_CTRL_TIMEOUT_SHIFT;
	48
	49	freq = clk_get_rate(pltfm_host->clk);
	50	freq /= 1 << (CLK_CTRL_TIMEOUT_MIN_EXP + div);
	51
	52	return freq;
	53	}
	54
	55	static struct sdhci_ops sdhci_arasan_ops = {
1771059c	56	.set_clock = sdhci_set_clock,
e3ec3a3d SB	57	.get_max_clock = sdhci_pltfm_clk_get_max_clock,
e3ec3a3d SB	58	.get_timeout_clock = sdhci_arasan_get_timeout_clock,
2317f56c	59	.set_bus_width = sdhci_set_bus_width,
03231f9b	60	.reset = sdhci_reset,
96d7b78c	61	.set_uhs_signaling = sdhci_set_uhs_signaling,
e3ec3a3d SB	62	};
	63
	64	static struct sdhci_pltfm_data sdhci_arasan_pdata = {
	65	.ops = &sdhci_arasan_ops,
2d532d45 SG	66	.quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
	67	.quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN \|
	68	SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN,
e3ec3a3d SB	69	};
	70
	71	#ifdef CONFIG_PM_SLEEP
	72	/**
	73	* sdhci_arasan_suspend - Suspend method for the driver
	74	* @dev: Address of the device structure
	75	* Returns 0 on success and error value on error
	76	*
	77	* Put the device in a low power state.
	78	*/
	79	static int sdhci_arasan_suspend(struct device *dev)
	80	{
	81	struct platform_device *pdev = to_platform_device(dev);
	82	struct sdhci_host *host = platform_get_drvdata(pdev);
	83	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
89211418	84	struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
e3ec3a3d SB	85	int ret;
	86
	87	ret = sdhci_suspend_host(host);
	88	if (ret)
	89	return ret;
	90
	91	clk_disable(pltfm_host->clk);
	92	clk_disable(sdhci_arasan->clk_ahb);
	93
	94	return 0;
	95	}
	96
	97	/**
	98	* sdhci_arasan_resume - Resume method for the driver
	99	* @dev: Address of the device structure
	100	* Returns 0 on success and error value on error
	101	*
	102	* Resume operation after suspend
	103	*/
	104	static int sdhci_arasan_resume(struct device *dev)
	105	{
	106	struct platform_device *pdev = to_platform_device(dev);
	107	struct sdhci_host *host = platform_get_drvdata(pdev);
	108	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
89211418	109	struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
e3ec3a3d SB	110	int ret;
	111
	112	ret = clk_enable(sdhci_arasan->clk_ahb);
	113	if (ret) {
	114	dev_err(dev, "Cannot enable AHB clock.\n");
	115	return ret;
	116	}
	117
	118	ret = clk_enable(pltfm_host->clk);
	119	if (ret) {
	120	dev_err(dev, "Cannot enable SD clock.\n");
e3ec3a3d SB	121	return ret;
	122	}
	123
	124	return sdhci_resume_host(host);
	125	}
	126	#endif /* ! CONFIG_PM_SLEEP */
	127
	128	static SIMPLE_DEV_PM_OPS(sdhci_arasan_dev_pm_ops, sdhci_arasan_suspend,
	129	sdhci_arasan_resume);
	130
	131	static int sdhci_arasan_probe(struct platform_device *pdev)
	132	{
	133	int ret;
	134	struct clk *clk_xin;
	135	struct sdhci_host *host;
	136	struct sdhci_pltfm_host *pltfm_host;
	137	struct sdhci_arasan_data *sdhci_arasan;
	138
89211418 JZ	139	host = sdhci_pltfm_init(pdev, &sdhci_arasan_pdata,
	140	sizeof(*sdhci_arasan));
	141	if (IS_ERR(host))
	142	return PTR_ERR(host);
	143
	144	pltfm_host = sdhci_priv(host);
	145	sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
e3ec3a3d SB	146
	147	sdhci_arasan->clk_ahb = devm_clk_get(&pdev->dev, "clk_ahb");
	148	if (IS_ERR(sdhci_arasan->clk_ahb)) {
	149	dev_err(&pdev->dev, "clk_ahb clock not found.\n");
	150	return PTR_ERR(sdhci_arasan->clk_ahb);
	151	}
	152
	153	clk_xin = devm_clk_get(&pdev->dev, "clk_xin");
	154	if (IS_ERR(clk_xin)) {
	155	dev_err(&pdev->dev, "clk_xin clock not found.\n");
	156	return PTR_ERR(clk_xin);
	157	}
	158
	159	ret = clk_prepare_enable(sdhci_arasan->clk_ahb);
	160	if (ret) {
	161	dev_err(&pdev->dev, "Unable to enable AHB clock.\n");
	162	return ret;
	163	}
	164
	165	ret = clk_prepare_enable(clk_xin);
	166	if (ret) {
	167	dev_err(&pdev->dev, "Unable to enable SD clock.\n");
	168	goto clk_dis_ahb;
	169	}
	170
e3ec3a3d	171	sdhci_get_of_property(pdev);
e3ec3a3d SB	172	pltfm_host->clk = clk_xin;
e3ec3a3d SB	173
16b23787 MS	174	ret = mmc_of_parse(host->mmc);
	175	if (ret) {
	176	dev_err(&pdev->dev, "parsing dt failed (%u)\n", ret);
	177	goto clk_disable_all;
	178	}
	179
e3ec3a3d	180	ret = sdhci_add_host(host);
b1df9de7	181	if (ret)
e3ec3a3d	182	goto err_pltfm_free;
e3ec3a3d SB	183
	184	return 0;
	185
	186	err_pltfm_free:
	187	sdhci_pltfm_free(pdev);
	188	clk_disable_all:
	189	clk_disable_unprepare(clk_xin);
	190	clk_dis_ahb:
	191	clk_disable_unprepare(sdhci_arasan->clk_ahb);
	192
	193	return ret;
	194	}
	195
	196	static int sdhci_arasan_remove(struct platform_device *pdev)
	197	{
0c7fe32e	198	int ret;
e3ec3a3d SB	199	struct sdhci_host *host = platform_get_drvdata(pdev);
e3ec3a3d SB	200	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
89211418 JZ	201	struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
89211418 JZ	202	struct clk *clk_ahb = sdhci_arasan->clk_ahb;
e3ec3a3d	203
0c7fe32e JZ	204	ret = sdhci_pltfm_unregister(pdev);
0c7fe32e JZ	205
89211418	206	clk_disable_unprepare(clk_ahb);
e3ec3a3d	207
0c7fe32e	208	return ret;
e3ec3a3d SB	209	}
	210
	211	static const struct of_device_id sdhci_arasan_of_match[] = {
	212	{ .compatible = "arasan,sdhci-8.9a" },
da795ec2	213	{ .compatible = "arasan,sdhci-5.1" },
308f3f8d	214	{ .compatible = "arasan,sdhci-4.9a" },
e3ec3a3d SB	215	{ }
	216	};
	217	MODULE_DEVICE_TABLE(of, sdhci_arasan_of_match);
	218
	219	static struct platform_driver sdhci_arasan_driver = {
	220	.driver = {
	221	.name = "sdhci-arasan",
e3ec3a3d SB	222	.of_match_table = sdhci_arasan_of_match,
	223	.pm = &sdhci_arasan_dev_pm_ops,
	224	},
	225	.probe = sdhci_arasan_probe,
	226	.remove = sdhci_arasan_remove,
	227	};
	228
	229	module_platform_driver(sdhci_arasan_driver);
	230
	231	MODULE_DESCRIPTION("Driver for the Arasan SDHCI Controller");
	232	MODULE_AUTHOR("Soeren Brinkmann <soren.brinkmann@xilinx.com>");
	233	MODULE_LICENSE("GPL");