[mirror_ubuntu-bionic-kernel.git] / drivers / mmc / host / sdhci-of-at91.c

/*
 * Atmel SDMMC controller driver.
 *
 * Copyright (C) 2015 Atmel,
 *		 2015 Ludovic Desroches <ludovic.desroches@atmel.com>
 *
 * This software is licensed under the terms of the GNU General Public
 * License version 2, as published by the Free Software Foundation, and
 * may be copied, distributed, and modified under those terms.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/mmc/host.h>
#include <linux/mmc/slot-gpio.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/pm.h>
#include <linux/pm_runtime.h>

#include "sdhci-pltfm.h"

#define SDMMC_MC1R	0x204
#define		SDMMC_MC1R_DDR		BIT(3)
#define SDMMC_CACR	0x230
#define		SDMMC_CACR_CAPWREN	BIT(0)
#define		SDMMC_CACR_KEY		(0x46 << 8)

#define SDHCI_AT91_PRESET_COMMON_CONF	0x400 /* drv type B, programmable clock mode */

struct sdhci_at91_priv {
	struct clk *hclock;
	struct clk *gck;
	struct clk *mainck;
};

static void sdhci_at91_set_clock(struct sdhci_host *host, unsigned int clock)
{
	u16 clk;
	unsigned long timeout;

	host->mmc->actual_clock = 0;

	/*
	 * There is no requirement to disable the internal clock before
	 * changing the SD clock configuration. Moreover, disabling the
	 * internal clock, changing the configuration and re-enabling the
	 * internal clock causes some bugs. It can prevent to get the internal
	 * clock stable flag ready and an unexpected switch to the base clock
	 * when using presets.
	 */
	clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
	clk &= SDHCI_CLOCK_INT_EN;
	sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);

	if (clock == 0)
		return;

	clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock);

	clk |= SDHCI_CLOCK_INT_EN;
	sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);

	/* Wait max 20 ms */
	timeout = 20;
	while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
		& SDHCI_CLOCK_INT_STABLE)) {
		if (timeout == 0) {
			pr_err("%s: Internal clock never stabilised.\n",
			       mmc_hostname(host->mmc));
			return;
		}
		timeout--;
		mdelay(1);
	}

	clk |= SDHCI_CLOCK_CARD_EN;
	sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
}

/*
 * In this specific implementation of the SDHCI controller, the power register
 * needs to have a valid voltage set even when the power supply is managed by
 * an external regulator.
 */
static void sdhci_at91_set_power(struct sdhci_host *host, unsigned char mode,
		     unsigned short vdd)
{
	if (!IS_ERR(host->mmc->supply.vmmc)) {
		struct mmc_host *mmc = host->mmc;

		spin_unlock_irq(&host->lock);
		mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd);
		spin_lock_irq(&host->lock);
	}
	sdhci_set_power_noreg(host, mode, vdd);
}

void sdhci_at91_set_uhs_signaling(struct sdhci_host *host, unsigned int timing)
{
	if (timing == MMC_TIMING_MMC_DDR52)
		sdhci_writeb(host, SDMMC_MC1R_DDR, SDMMC_MC1R);
	sdhci_set_uhs_signaling(host, timing);
}

static const struct sdhci_ops sdhci_at91_sama5d2_ops = {
	.set_clock		= sdhci_at91_set_clock,
	.set_bus_width		= sdhci_set_bus_width,
	.reset			= sdhci_reset,
	.set_uhs_signaling	= sdhci_at91_set_uhs_signaling,
	.set_power		= sdhci_at91_set_power,
};

static const struct sdhci_pltfm_data soc_data_sama5d2 = {
	.ops = &sdhci_at91_sama5d2_ops,
};

static const struct of_device_id sdhci_at91_dt_match[] = {
	{ .compatible = "atmel,sama5d2-sdhci", .data = &soc_data_sama5d2 },
	{}
};
MODULE_DEVICE_TABLE(of, sdhci_at91_dt_match);

#ifdef CONFIG_PM
static int sdhci_at91_runtime_suspend(struct device *dev)
{
	struct sdhci_host *host = dev_get_drvdata(dev);
	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
	struct sdhci_at91_priv *priv = sdhci_pltfm_priv(pltfm_host);
	int ret;

	ret = sdhci_runtime_suspend_host(host);

	clk_disable_unprepare(priv->gck);
	clk_disable_unprepare(priv->hclock);
	clk_disable_unprepare(priv->mainck);

	return ret;
}

static int sdhci_at91_runtime_resume(struct device *dev)
{
	struct sdhci_host *host = dev_get_drvdata(dev);
	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
	struct sdhci_at91_priv *priv = sdhci_pltfm_priv(pltfm_host);
	int ret;

	ret = clk_prepare_enable(priv->mainck);
	if (ret) {
		dev_err(dev, "can't enable mainck\n");
		return ret;
	}

	ret = clk_prepare_enable(priv->hclock);
	if (ret) {
		dev_err(dev, "can't enable hclock\n");
		return ret;
	}

	ret = clk_prepare_enable(priv->gck);
	if (ret) {
		dev_err(dev, "can't enable gck\n");
		return ret;
	}

	return sdhci_runtime_resume_host(host);
}
#endif /* CONFIG_PM */

static const struct dev_pm_ops sdhci_at91_dev_pm_ops = {
	SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
				pm_runtime_force_resume)
	SET_RUNTIME_PM_OPS(sdhci_at91_runtime_suspend,
			   sdhci_at91_runtime_resume,
			   NULL)
};

static int sdhci_at91_probe(struct platform_device *pdev)
{
	const struct of_device_id	*match;
	const struct sdhci_pltfm_data	*soc_data;
	struct sdhci_host		*host;
	struct sdhci_pltfm_host		*pltfm_host;
	struct sdhci_at91_priv		*priv;
	unsigned int			caps0, caps1;
	unsigned int			clk_base, clk_mul;
	unsigned int			gck_rate, real_gck_rate;
	int				ret;
	unsigned int			preset_div;

	match = of_match_device(sdhci_at91_dt_match, &pdev->dev);
	if (!match)
		return -EINVAL;
	soc_data = match->data;

	host = sdhci_pltfm_init(pdev, soc_data, sizeof(*priv));
	if (IS_ERR(host))
		return PTR_ERR(host);

	pltfm_host = sdhci_priv(host);
	priv = sdhci_pltfm_priv(pltfm_host);

	priv->mainck = devm_clk_get(&pdev->dev, "baseclk");
	if (IS_ERR(priv->mainck)) {
		dev_err(&pdev->dev, "failed to get baseclk\n");
		return PTR_ERR(priv->mainck);
	}

	priv->hclock = devm_clk_get(&pdev->dev, "hclock");
	if (IS_ERR(priv->hclock)) {
		dev_err(&pdev->dev, "failed to get hclock\n");
		return PTR_ERR(priv->hclock);
	}

	priv->gck = devm_clk_get(&pdev->dev, "multclk");
	if (IS_ERR(priv->gck)) {
		dev_err(&pdev->dev, "failed to get multclk\n");
		return PTR_ERR(priv->gck);
	}

	/*
	 * The mult clock is provided by as a generated clock by the PMC
	 * controller. In order to set the rate of gck, we have to get the
	 * base clock rate and the clock mult from capabilities.
	 */
	clk_prepare_enable(priv->hclock);
	caps0 = readl(host->ioaddr + SDHCI_CAPABILITIES);
	caps1 = readl(host->ioaddr + SDHCI_CAPABILITIES_1);
	clk_base = (caps0 & SDHCI_CLOCK_V3_BASE_MASK) >> SDHCI_CLOCK_BASE_SHIFT;
	clk_mul = (caps1 & SDHCI_CLOCK_MUL_MASK) >> SDHCI_CLOCK_MUL_SHIFT;
	gck_rate = clk_base * 1000000 * (clk_mul + 1);
	ret = clk_set_rate(priv->gck, gck_rate);
	if (ret < 0) {
		dev_err(&pdev->dev, "failed to set gck");
		goto hclock_disable_unprepare;
	}
	/*
	 * We need to check if we have the requested rate for gck because in
	 * some cases this rate could be not supported. If it happens, the rate
	 * is the closest one gck can provide. We have to update the value
	 * of clk mul.
	 */
	real_gck_rate = clk_get_rate(priv->gck);
	if (real_gck_rate != gck_rate) {
		clk_mul = real_gck_rate / (clk_base * 1000000) - 1;
		caps1 &= (~SDHCI_CLOCK_MUL_MASK);
		caps1 |= ((clk_mul << SDHCI_CLOCK_MUL_SHIFT) & SDHCI_CLOCK_MUL_MASK);
		/* Set capabilities in r/w mode. */
		writel(SDMMC_CACR_KEY | SDMMC_CACR_CAPWREN, host->ioaddr + SDMMC_CACR);
		writel(caps1, host->ioaddr + SDHCI_CAPABILITIES_1);
		/* Set capabilities in ro mode. */
		writel(0, host->ioaddr + SDMMC_CACR);
		dev_info(&pdev->dev, "update clk mul to %u as gck rate is %u Hz\n",
			 clk_mul, real_gck_rate);
	}

	/*
	 * We have to set preset values because it depends on the clk_mul
	 * value. Moreover, SDR104 is supported in a degraded mode since the
	 * maximum sd clock value is 120 MHz instead of 208 MHz. For that
	 * reason, we need to use presets to support SDR104.
	 */
	preset_div = DIV_ROUND_UP(real_gck_rate, 24000000) - 1;
	writew(SDHCI_AT91_PRESET_COMMON_CONF | preset_div,
	       host->ioaddr + SDHCI_PRESET_FOR_SDR12);
	preset_div = DIV_ROUND_UP(real_gck_rate, 50000000) - 1;
	writew(SDHCI_AT91_PRESET_COMMON_CONF | preset_div,
	       host->ioaddr + SDHCI_PRESET_FOR_SDR25);
	preset_div = DIV_ROUND_UP(real_gck_rate, 100000000) - 1;
	writew(SDHCI_AT91_PRESET_COMMON_CONF | preset_div,
	       host->ioaddr + SDHCI_PRESET_FOR_SDR50);
	preset_div = DIV_ROUND_UP(real_gck_rate, 120000000) - 1;
	writew(SDHCI_AT91_PRESET_COMMON_CONF | preset_div,
	       host->ioaddr + SDHCI_PRESET_FOR_SDR104);
	preset_div = DIV_ROUND_UP(real_gck_rate, 50000000) - 1;
	writew(SDHCI_AT91_PRESET_COMMON_CONF | preset_div,
	       host->ioaddr + SDHCI_PRESET_FOR_DDR50);

	clk_prepare_enable(priv->mainck);
	clk_prepare_enable(priv->gck);

	ret = mmc_of_parse(host->mmc);
	if (ret)
		goto clocks_disable_unprepare;

	sdhci_get_of_property(pdev);

	pm_runtime_get_noresume(&pdev->dev);
	pm_runtime_set_active(&pdev->dev);
	pm_runtime_enable(&pdev->dev);
	pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
	pm_runtime_use_autosuspend(&pdev->dev);

	ret = sdhci_add_host(host);
	if (ret)
		goto pm_runtime_disable;

	/*
	 * When calling sdhci_runtime_suspend_host(), the sdhci layer makes
	 * the assumption that all the clocks of the controller are disabled.
	 * It means we can't get irq from it when it is runtime suspended.
	 * For that reason, it is not planned to wake-up on a card detect irq
	 * from the controller.
	 * If we want to use runtime PM and to be able to wake-up on card
	 * insertion, we have to use a GPIO for the card detection or we can
	 * use polling. Be aware that using polling will resume/suspend the
	 * controller between each attempt.
	 * Disable SDHCI_QUIRK_BROKEN_CARD_DETECTION to be sure nobody tries
	 * to enable polling via device tree with broken-cd property.
	 */
	if (mmc_card_is_removable(host->mmc) &&
	    mmc_gpio_get_cd(host->mmc) < 0) {
		host->mmc->caps |= MMC_CAP_NEEDS_POLL;
		host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION;
	}

	pm_runtime_put_autosuspend(&pdev->dev);

	return 0;

pm_runtime_disable:
	pm_runtime_disable(&pdev->dev);
	pm_runtime_set_suspended(&pdev->dev);
	pm_runtime_put_noidle(&pdev->dev);
clocks_disable_unprepare:
	clk_disable_unprepare(priv->gck);
	clk_disable_unprepare(priv->mainck);
hclock_disable_unprepare:
	clk_disable_unprepare(priv->hclock);
	sdhci_pltfm_free(pdev);
	return ret;
}

static int sdhci_at91_remove(struct platform_device *pdev)
{
	struct sdhci_host	*host = platform_get_drvdata(pdev);
	struct sdhci_pltfm_host	*pltfm_host = sdhci_priv(host);
	struct sdhci_at91_priv	*priv = sdhci_pltfm_priv(pltfm_host);
	struct clk *gck = priv->gck;
	struct clk *hclock = priv->hclock;
	struct clk *mainck = priv->mainck;

	pm_runtime_get_sync(&pdev->dev);
	pm_runtime_disable(&pdev->dev);
	pm_runtime_put_noidle(&pdev->dev);

	sdhci_pltfm_unregister(pdev);

	clk_disable_unprepare(gck);
	clk_disable_unprepare(hclock);
	clk_disable_unprepare(mainck);

	return 0;
}

static struct platform_driver sdhci_at91_driver = {
	.driver		= {
		.name	= "sdhci-at91",
		.of_match_table = sdhci_at91_dt_match,
		.pm	= &sdhci_at91_dev_pm_ops,
	},
	.probe		= sdhci_at91_probe,
	.remove		= sdhci_at91_remove,
};

module_platform_driver(sdhci_at91_driver);

MODULE_DESCRIPTION("SDHCI driver for at91");
MODULE_AUTHOR("Ludovic Desroches <ludovic.desroches@atmel.com>");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
bb5f8ea4	1	/*
	2	* Atmel SDMMC controller driver.
	3	*
	4	* Copyright (C) 2015 Atmel,
	5	* 2015 Ludovic Desroches <ludovic.desroches@atmel.com>
	6	*
	7	* This software is licensed under the terms of the GNU General Public
	8	* License version 2, as published by the Free Software Foundation, and
	9	* may be copied, distributed, and modified under those terms.
	10	*
	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	* GNU General Public License for more details.
	15	*/
	16
	17	#include <linux/clk.h>
4e289a7d	18	#include <linux/delay.h>
bb5f8ea4	19	#include <linux/err.h>
bb5f8ea4	20	#include <linux/io.h>
4406433d	21	#include <linux/kernel.h>
bb5f8ea4	22	#include <linux/mmc/host.h>
64e5cd72	23	#include <linux/mmc/slot-gpio.h>
bb5f8ea4	24	#include <linux/module.h>
	25	#include <linux/of.h>
	26	#include <linux/of_device.h>
f5f17813	27	#include <linux/pm.h>
f5f17813	28	#include <linux/pm_runtime.h>
bb5f8ea4	29
	30	#include "sdhci-pltfm.h"
	31
d0918764 LD	32	#define SDMMC_MC1R 0x204
d0918764 LD	33	#define SDMMC_MC1R_DDR BIT(3)
bb5f8ea4	34	#define SDMMC_CACR 0x230
	35	#define SDMMC_CACR_CAPWREN BIT(0)
	36	#define SDMMC_CACR_KEY (0x46 << 8)
	37
4406433d LD	38	#define SDHCI_AT91_PRESET_COMMON_CONF 0x400 /* drv type B, programmable clock mode */
4406433d LD	39
bb5f8ea4	40	struct sdhci_at91_priv {
	41	struct clk *hclock;
	42	struct clk *gck;
	43	struct clk *mainck;
	44	};
	45
4e289a7d LD	46	static void sdhci_at91_set_clock(struct sdhci_host *host, unsigned int clock)
	47	{
	48	u16 clk;
	49	unsigned long timeout;
	50
	51	host->mmc->actual_clock = 0;
	52
	53	/*
	54	* There is no requirement to disable the internal clock before
	55	* changing the SD clock configuration. Moreover, disabling the
	56	* internal clock, changing the configuration and re-enabling the
	57	* internal clock causes some bugs. It can prevent to get the internal
	58	* clock stable flag ready and an unexpected switch to the base clock
	59	* when using presets.
	60	*/
	61	clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
	62	clk &= SDHCI_CLOCK_INT_EN;
	63	sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
	64
	65	if (clock == 0)
	66	return;
	67
	68	clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock);
	69
	70	clk \|= SDHCI_CLOCK_INT_EN;
	71	sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
	72
	73	/* Wait max 20 ms */
	74	timeout = 20;
	75	while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
	76	& SDHCI_CLOCK_INT_STABLE)) {
	77	if (timeout == 0) {
	78	pr_err("%s: Internal clock never stabilised.\n",
	79	mmc_hostname(host->mmc));
	80	return;
	81	}
	82	timeout--;
	83	mdelay(1);
	84	}
	85
	86	clk \|= SDHCI_CLOCK_CARD_EN;
	87	sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
	88	}
	89
2ce0c7b6 RI	90	/*
	91	* In this specific implementation of the SDHCI controller, the power register
	92	* needs to have a valid voltage set even when the power supply is managed by
	93	* an external regulator.
	94	*/
	95	static void sdhci_at91_set_power(struct sdhci_host *host, unsigned char mode,
	96	unsigned short vdd)
	97	{
	98	if (!IS_ERR(host->mmc->supply.vmmc)) {
	99	struct mmc_host *mmc = host->mmc;
	100
	101	spin_unlock_irq(&host->lock);
	102	mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd);
	103	spin_lock_irq(&host->lock);
	104	}
	105	sdhci_set_power_noreg(host, mode, vdd);
	106	}
	107
d0918764 LD	108	void sdhci_at91_set_uhs_signaling(struct sdhci_host *host, unsigned int timing)
	109	{
	110	if (timing == MMC_TIMING_MMC_DDR52)
	111	sdhci_writeb(host, SDMMC_MC1R_DDR, SDMMC_MC1R);
	112	sdhci_set_uhs_signaling(host, timing);
	113	}
	114
bb5f8ea4	115	static const struct sdhci_ops sdhci_at91_sama5d2_ops = {
4e289a7d	116	.set_clock = sdhci_at91_set_clock,
bb5f8ea4	117	.set_bus_width = sdhci_set_bus_width,
bb5f8ea4	118	.reset = sdhci_reset,
d0918764	119	.set_uhs_signaling = sdhci_at91_set_uhs_signaling,
2ce0c7b6	120	.set_power = sdhci_at91_set_power,
bb5f8ea4	121	};
	122
	123	static const struct sdhci_pltfm_data soc_data_sama5d2 = {
	124	.ops = &sdhci_at91_sama5d2_ops,
	125	};
	126
	127	static const struct of_device_id sdhci_at91_dt_match[] = {
	128	{ .compatible = "atmel,sama5d2-sdhci", .data = &soc_data_sama5d2 },
	129	{}
	130	};
d9943c68	131	MODULE_DEVICE_TABLE(of, sdhci_at91_dt_match);
bb5f8ea4	132
f5f17813	133	#ifdef CONFIG_PM
	134	static int sdhci_at91_runtime_suspend(struct device *dev)
	135	{
	136	struct sdhci_host *host = dev_get_drvdata(dev);
	137	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
10f1c135	138	struct sdhci_at91_priv *priv = sdhci_pltfm_priv(pltfm_host);
f5f17813	139	int ret;
	140
	141	ret = sdhci_runtime_suspend_host(host);
	142
	143	clk_disable_unprepare(priv->gck);
	144	clk_disable_unprepare(priv->hclock);
	145	clk_disable_unprepare(priv->mainck);
	146
	147	return ret;
	148	}
	149
	150	static int sdhci_at91_runtime_resume(struct device *dev)
	151	{
	152	struct sdhci_host *host = dev_get_drvdata(dev);
	153	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
10f1c135	154	struct sdhci_at91_priv *priv = sdhci_pltfm_priv(pltfm_host);
f5f17813	155	int ret;
	156
	157	ret = clk_prepare_enable(priv->mainck);
	158	if (ret) {
	159	dev_err(dev, "can't enable mainck\n");
	160	return ret;
	161	}
	162
	163	ret = clk_prepare_enable(priv->hclock);
	164	if (ret) {
	165	dev_err(dev, "can't enable hclock\n");
	166	return ret;
	167	}
	168
	169	ret = clk_prepare_enable(priv->gck);
	170	if (ret) {
	171	dev_err(dev, "can't enable gck\n");
	172	return ret;
	173	}
	174
	175	return sdhci_runtime_resume_host(host);
	176	}
	177	#endif /* CONFIG_PM */
	178
	179	static const struct dev_pm_ops sdhci_at91_dev_pm_ops = {
	180	SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
	181	pm_runtime_force_resume)
	182	SET_RUNTIME_PM_OPS(sdhci_at91_runtime_suspend,
	183	sdhci_at91_runtime_resume,
	184	NULL)
	185	};
	186
bb5f8ea4	187	static int sdhci_at91_probe(struct platform_device *pdev)
	188	{
	189	const struct of_device_id *match;
	190	const struct sdhci_pltfm_data *soc_data;
	191	struct sdhci_host *host;
	192	struct sdhci_pltfm_host *pltfm_host;
	193	struct sdhci_at91_priv *priv;
	194	unsigned int caps0, caps1;
	195	unsigned int clk_base, clk_mul;
	196	unsigned int gck_rate, real_gck_rate;
	197	int ret;
4406433d	198	unsigned int preset_div;
bb5f8ea4	199
	200	match = of_match_device(sdhci_at91_dt_match, &pdev->dev);
	201	if (!match)
	202	return -EINVAL;
	203	soc_data = match->data;
	204
10f1c135 JZ	205	host = sdhci_pltfm_init(pdev, soc_data, sizeof(*priv));
	206	if (IS_ERR(host))
	207	return PTR_ERR(host);
	208
	209	pltfm_host = sdhci_priv(host);
	210	priv = sdhci_pltfm_priv(pltfm_host);
bb5f8ea4	211
	212	priv->mainck = devm_clk_get(&pdev->dev, "baseclk");
	213	if (IS_ERR(priv->mainck)) {
	214	dev_err(&pdev->dev, "failed to get baseclk\n");
	215	return PTR_ERR(priv->mainck);
	216	}
	217
	218	priv->hclock = devm_clk_get(&pdev->dev, "hclock");
	219	if (IS_ERR(priv->hclock)) {
	220	dev_err(&pdev->dev, "failed to get hclock\n");
	221	return PTR_ERR(priv->hclock);
	222	}
	223
	224	priv->gck = devm_clk_get(&pdev->dev, "multclk");
	225	if (IS_ERR(priv->gck)) {
	226	dev_err(&pdev->dev, "failed to get multclk\n");
	227	return PTR_ERR(priv->gck);
	228	}
	229
bb5f8ea4	230	/*
	231	* The mult clock is provided by as a generated clock by the PMC
	232	* controller. In order to set the rate of gck, we have to get the
	233	* base clock rate and the clock mult from capabilities.
	234	*/
	235	clk_prepare_enable(priv->hclock);
	236	caps0 = readl(host->ioaddr + SDHCI_CAPABILITIES);
	237	caps1 = readl(host->ioaddr + SDHCI_CAPABILITIES_1);
	238	clk_base = (caps0 & SDHCI_CLOCK_V3_BASE_MASK) >> SDHCI_CLOCK_BASE_SHIFT;
	239	clk_mul = (caps1 & SDHCI_CLOCK_MUL_MASK) >> SDHCI_CLOCK_MUL_SHIFT;
	240	gck_rate = clk_base * 1000000 * (clk_mul + 1);
	241	ret = clk_set_rate(priv->gck, gck_rate);
	242	if (ret < 0) {
	243	dev_err(&pdev->dev, "failed to set gck");
	244	goto hclock_disable_unprepare;
bb5f8ea4	245	}
	246	/*
	247	* We need to check if we have the requested rate for gck because in
	248	* some cases this rate could be not supported. If it happens, the rate
	249	* is the closest one gck can provide. We have to update the value
	250	* of clk mul.
	251	*/
	252	real_gck_rate = clk_get_rate(priv->gck);
	253	if (real_gck_rate != gck_rate) {
	254	clk_mul = real_gck_rate / (clk_base * 1000000) - 1;
	255	caps1 &= (~SDHCI_CLOCK_MUL_MASK);
	256	caps1 \|= ((clk_mul << SDHCI_CLOCK_MUL_SHIFT) & SDHCI_CLOCK_MUL_MASK);
	257	/* Set capabilities in r/w mode. */
	258	writel(SDMMC_CACR_KEY \| SDMMC_CACR_CAPWREN, host->ioaddr + SDMMC_CACR);
	259	writel(caps1, host->ioaddr + SDHCI_CAPABILITIES_1);
	260	/* Set capabilities in ro mode. */
	261	writel(0, host->ioaddr + SDMMC_CACR);
	262	dev_info(&pdev->dev, "update clk mul to %u as gck rate is %u Hz\n",
	263	clk_mul, real_gck_rate);
	264	}
	265
4406433d LD	266	/*
	267	* We have to set preset values because it depends on the clk_mul
	268	* value. Moreover, SDR104 is supported in a degraded mode since the
	269	* maximum sd clock value is 120 MHz instead of 208 MHz. For that
	270	* reason, we need to use presets to support SDR104.
	271	*/
	272	preset_div = DIV_ROUND_UP(real_gck_rate, 24000000) - 1;
	273	writew(SDHCI_AT91_PRESET_COMMON_CONF \| preset_div,
	274	host->ioaddr + SDHCI_PRESET_FOR_SDR12);
	275	preset_div = DIV_ROUND_UP(real_gck_rate, 50000000) - 1;
	276	writew(SDHCI_AT91_PRESET_COMMON_CONF \| preset_div,
	277	host->ioaddr + SDHCI_PRESET_FOR_SDR25);
	278	preset_div = DIV_ROUND_UP(real_gck_rate, 100000000) - 1;
	279	writew(SDHCI_AT91_PRESET_COMMON_CONF \| preset_div,
	280	host->ioaddr + SDHCI_PRESET_FOR_SDR50);
	281	preset_div = DIV_ROUND_UP(real_gck_rate, 120000000) - 1;
	282	writew(SDHCI_AT91_PRESET_COMMON_CONF \| preset_div,
	283	host->ioaddr + SDHCI_PRESET_FOR_SDR104);
	284	preset_div = DIV_ROUND_UP(real_gck_rate, 50000000) - 1;
	285	writew(SDHCI_AT91_PRESET_COMMON_CONF \| preset_div,
	286	host->ioaddr + SDHCI_PRESET_FOR_DDR50);
	287
bb5f8ea4	288	clk_prepare_enable(priv->mainck);
	289	clk_prepare_enable(priv->gck);
	290
bb5f8ea4	291	ret = mmc_of_parse(host->mmc);
	292	if (ret)
	293	goto clocks_disable_unprepare;
	294
	295	sdhci_get_of_property(pdev);
	296
f5f17813	297	pm_runtime_get_noresume(&pdev->dev);
	298	pm_runtime_set_active(&pdev->dev);
	299	pm_runtime_enable(&pdev->dev);
	300	pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
	301	pm_runtime_use_autosuspend(&pdev->dev);
	302
bb5f8ea4	303	ret = sdhci_add_host(host);
bb5f8ea4	304	if (ret)
f5f17813	305	goto pm_runtime_disable;
f5f17813	306
64e5cd72	307	/*
	308	* When calling sdhci_runtime_suspend_host(), the sdhci layer makes
	309	* the assumption that all the clocks of the controller are disabled.
	310	* It means we can't get irq from it when it is runtime suspended.
	311	* For that reason, it is not planned to wake-up on a card detect irq
	312	* from the controller.
	313	* If we want to use runtime PM and to be able to wake-up on card
	314	* insertion, we have to use a GPIO for the card detection or we can
	315	* use polling. Be aware that using polling will resume/suspend the
	316	* controller between each attempt.
	317	* Disable SDHCI_QUIRK_BROKEN_CARD_DETECTION to be sure nobody tries
	318	* to enable polling via device tree with broken-cd property.
	319	*/
860951c5	320	if (mmc_card_is_removable(host->mmc) &&
287980e4	321	mmc_gpio_get_cd(host->mmc) < 0) {
64e5cd72	322	host->mmc->caps \|= MMC_CAP_NEEDS_POLL;
	323	host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION;
	324	}
	325
f5f17813	326	pm_runtime_put_autosuspend(&pdev->dev);
bb5f8ea4	327
	328	return 0;
	329
f5f17813	330	pm_runtime_disable:
	331	pm_runtime_disable(&pdev->dev);
	332	pm_runtime_set_suspended(&pdev->dev);
2df9d58f	333	pm_runtime_put_noidle(&pdev->dev);
bb5f8ea4	334	clocks_disable_unprepare:
	335	clk_disable_unprepare(priv->gck);
	336	clk_disable_unprepare(priv->mainck);
	337	hclock_disable_unprepare:
	338	clk_disable_unprepare(priv->hclock);
	339	sdhci_pltfm_free(pdev);
	340	return ret;
	341	}
	342
	343	static int sdhci_at91_remove(struct platform_device *pdev)
	344	{
	345	struct sdhci_host *host = platform_get_drvdata(pdev);
	346	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
10f1c135 JZ	347	struct sdhci_at91_priv *priv = sdhci_pltfm_priv(pltfm_host);
	348	struct clk *gck = priv->gck;
	349	struct clk *hclock = priv->hclock;
	350	struct clk *mainck = priv->mainck;
bb5f8ea4	351
f5f17813	352	pm_runtime_get_sync(&pdev->dev);
	353	pm_runtime_disable(&pdev->dev);
	354	pm_runtime_put_noidle(&pdev->dev);
	355
bb5f8ea4	356	sdhci_pltfm_unregister(pdev);
bb5f8ea4	357
10f1c135 JZ	358	clk_disable_unprepare(gck);
	359	clk_disable_unprepare(hclock);
	360	clk_disable_unprepare(mainck);
bb5f8ea4	361
	362	return 0;
	363	}
	364
	365	static struct platform_driver sdhci_at91_driver = {
	366	.driver = {
	367	.name = "sdhci-at91",
bb5f8ea4	368	.of_match_table = sdhci_at91_dt_match,
f5f17813	369	.pm = &sdhci_at91_dev_pm_ops,
bb5f8ea4	370	},
	371	.probe = sdhci_at91_probe,
	372	.remove = sdhci_at91_remove,
	373	};
	374
	375	module_platform_driver(sdhci_at91_driver);
	376
	377	MODULE_DESCRIPTION("SDHCI driver for at91");
	378	MODULE_AUTHOR("Ludovic Desroches <ludovic.desroches@atmel.com>");
	379	MODULE_LICENSE("GPL v2");