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bb5f8ea4 | 1 | /* |
2 | * Atmel SDMMC controller driver. | |
3 | * | |
4 | * Copyright (C) 2015 Atmel, | |
5 | * 2015 Ludovic Desroches <ludovic.desroches@atmel.com> | |
6 | * | |
7 | * This software is licensed under the terms of the GNU General Public | |
8 | * License version 2, as published by the Free Software Foundation, and | |
9 | * may be copied, distributed, and modified under those terms. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | */ | |
16 | ||
17 | #include <linux/clk.h> | |
4e289a7d | 18 | #include <linux/delay.h> |
bb5f8ea4 | 19 | #include <linux/err.h> |
20 | #include <linux/io.h> | |
4406433d | 21 | #include <linux/kernel.h> |
bb5f8ea4 | 22 | #include <linux/mmc/host.h> |
64e5cd72 | 23 | #include <linux/mmc/slot-gpio.h> |
bb5f8ea4 | 24 | #include <linux/module.h> |
25 | #include <linux/of.h> | |
26 | #include <linux/of_device.h> | |
f5f17813 | 27 | #include <linux/pm.h> |
28 | #include <linux/pm_runtime.h> | |
bb5f8ea4 | 29 | |
30 | #include "sdhci-pltfm.h" | |
31 | ||
d0918764 LD |
32 | #define SDMMC_MC1R 0x204 |
33 | #define SDMMC_MC1R_DDR BIT(3) | |
7a1e3f14 | 34 | #define SDMMC_MC1R_FCD BIT(7) |
bb5f8ea4 | 35 | #define SDMMC_CACR 0x230 |
36 | #define SDMMC_CACR_CAPWREN BIT(0) | |
37 | #define SDMMC_CACR_KEY (0x46 << 8) | |
38 | ||
4406433d LD |
39 | #define SDHCI_AT91_PRESET_COMMON_CONF 0x400 /* drv type B, programmable clock mode */ |
40 | ||
bb5f8ea4 | 41 | struct sdhci_at91_priv { |
42 | struct clk *hclock; | |
43 | struct clk *gck; | |
44 | struct clk *mainck; | |
45 | }; | |
46 | ||
7a1e3f14 LD |
47 | static void sdhci_at91_set_force_card_detect(struct sdhci_host *host) |
48 | { | |
49 | u8 mc1r; | |
50 | ||
51 | mc1r = readb(host->ioaddr + SDMMC_MC1R); | |
52 | mc1r |= SDMMC_MC1R_FCD; | |
53 | writeb(mc1r, host->ioaddr + SDMMC_MC1R); | |
54 | } | |
55 | ||
4e289a7d LD |
56 | static void sdhci_at91_set_clock(struct sdhci_host *host, unsigned int clock) |
57 | { | |
58 | u16 clk; | |
59 | unsigned long timeout; | |
60 | ||
61 | host->mmc->actual_clock = 0; | |
62 | ||
63 | /* | |
64 | * There is no requirement to disable the internal clock before | |
65 | * changing the SD clock configuration. Moreover, disabling the | |
66 | * internal clock, changing the configuration and re-enabling the | |
67 | * internal clock causes some bugs. It can prevent to get the internal | |
68 | * clock stable flag ready and an unexpected switch to the base clock | |
69 | * when using presets. | |
70 | */ | |
71 | clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); | |
72 | clk &= SDHCI_CLOCK_INT_EN; | |
73 | sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); | |
74 | ||
75 | if (clock == 0) | |
76 | return; | |
77 | ||
78 | clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock); | |
79 | ||
80 | clk |= SDHCI_CLOCK_INT_EN; | |
81 | sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); | |
82 | ||
83 | /* Wait max 20 ms */ | |
84 | timeout = 20; | |
85 | while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL)) | |
86 | & SDHCI_CLOCK_INT_STABLE)) { | |
87 | if (timeout == 0) { | |
88 | pr_err("%s: Internal clock never stabilised.\n", | |
89 | mmc_hostname(host->mmc)); | |
90 | return; | |
91 | } | |
92 | timeout--; | |
93 | mdelay(1); | |
94 | } | |
95 | ||
96 | clk |= SDHCI_CLOCK_CARD_EN; | |
97 | sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); | |
98 | } | |
99 | ||
2ce0c7b6 RI |
100 | /* |
101 | * In this specific implementation of the SDHCI controller, the power register | |
102 | * needs to have a valid voltage set even when the power supply is managed by | |
103 | * an external regulator. | |
104 | */ | |
105 | static void sdhci_at91_set_power(struct sdhci_host *host, unsigned char mode, | |
106 | unsigned short vdd) | |
107 | { | |
108 | if (!IS_ERR(host->mmc->supply.vmmc)) { | |
109 | struct mmc_host *mmc = host->mmc; | |
110 | ||
2ce0c7b6 | 111 | mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd); |
2ce0c7b6 RI |
112 | } |
113 | sdhci_set_power_noreg(host, mode, vdd); | |
114 | } | |
115 | ||
d0918764 LD |
116 | void sdhci_at91_set_uhs_signaling(struct sdhci_host *host, unsigned int timing) |
117 | { | |
118 | if (timing == MMC_TIMING_MMC_DDR52) | |
119 | sdhci_writeb(host, SDMMC_MC1R_DDR, SDMMC_MC1R); | |
120 | sdhci_set_uhs_signaling(host, timing); | |
121 | } | |
122 | ||
7a1e3f14 LD |
123 | static void sdhci_at91_reset(struct sdhci_host *host, u8 mask) |
124 | { | |
125 | sdhci_reset(host, mask); | |
126 | ||
127 | if (host->mmc->caps & MMC_CAP_NONREMOVABLE) | |
128 | sdhci_at91_set_force_card_detect(host); | |
129 | } | |
130 | ||
bb5f8ea4 | 131 | static const struct sdhci_ops sdhci_at91_sama5d2_ops = { |
4e289a7d | 132 | .set_clock = sdhci_at91_set_clock, |
bb5f8ea4 | 133 | .set_bus_width = sdhci_set_bus_width, |
7a1e3f14 | 134 | .reset = sdhci_at91_reset, |
d0918764 | 135 | .set_uhs_signaling = sdhci_at91_set_uhs_signaling, |
2ce0c7b6 | 136 | .set_power = sdhci_at91_set_power, |
bb5f8ea4 | 137 | }; |
138 | ||
139 | static const struct sdhci_pltfm_data soc_data_sama5d2 = { | |
140 | .ops = &sdhci_at91_sama5d2_ops, | |
141 | }; | |
142 | ||
143 | static const struct of_device_id sdhci_at91_dt_match[] = { | |
144 | { .compatible = "atmel,sama5d2-sdhci", .data = &soc_data_sama5d2 }, | |
145 | {} | |
146 | }; | |
d9943c68 | 147 | MODULE_DEVICE_TABLE(of, sdhci_at91_dt_match); |
bb5f8ea4 | 148 | |
f5f17813 | 149 | #ifdef CONFIG_PM |
150 | static int sdhci_at91_runtime_suspend(struct device *dev) | |
151 | { | |
152 | struct sdhci_host *host = dev_get_drvdata(dev); | |
153 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
10f1c135 | 154 | struct sdhci_at91_priv *priv = sdhci_pltfm_priv(pltfm_host); |
f5f17813 | 155 | int ret; |
156 | ||
157 | ret = sdhci_runtime_suspend_host(host); | |
158 | ||
d38dcad4 AH |
159 | if (host->tuning_mode != SDHCI_TUNING_MODE_3) |
160 | mmc_retune_needed(host->mmc); | |
161 | ||
f5f17813 | 162 | clk_disable_unprepare(priv->gck); |
163 | clk_disable_unprepare(priv->hclock); | |
164 | clk_disable_unprepare(priv->mainck); | |
165 | ||
166 | return ret; | |
167 | } | |
168 | ||
169 | static int sdhci_at91_runtime_resume(struct device *dev) | |
170 | { | |
171 | struct sdhci_host *host = dev_get_drvdata(dev); | |
172 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
10f1c135 | 173 | struct sdhci_at91_priv *priv = sdhci_pltfm_priv(pltfm_host); |
f5f17813 | 174 | int ret; |
175 | ||
176 | ret = clk_prepare_enable(priv->mainck); | |
177 | if (ret) { | |
178 | dev_err(dev, "can't enable mainck\n"); | |
179 | return ret; | |
180 | } | |
181 | ||
182 | ret = clk_prepare_enable(priv->hclock); | |
183 | if (ret) { | |
184 | dev_err(dev, "can't enable hclock\n"); | |
185 | return ret; | |
186 | } | |
187 | ||
188 | ret = clk_prepare_enable(priv->gck); | |
189 | if (ret) { | |
190 | dev_err(dev, "can't enable gck\n"); | |
191 | return ret; | |
192 | } | |
193 | ||
194 | return sdhci_runtime_resume_host(host); | |
195 | } | |
196 | #endif /* CONFIG_PM */ | |
197 | ||
198 | static const struct dev_pm_ops sdhci_at91_dev_pm_ops = { | |
199 | SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, | |
200 | pm_runtime_force_resume) | |
201 | SET_RUNTIME_PM_OPS(sdhci_at91_runtime_suspend, | |
202 | sdhci_at91_runtime_resume, | |
203 | NULL) | |
204 | }; | |
205 | ||
bb5f8ea4 | 206 | static int sdhci_at91_probe(struct platform_device *pdev) |
207 | { | |
208 | const struct of_device_id *match; | |
209 | const struct sdhci_pltfm_data *soc_data; | |
210 | struct sdhci_host *host; | |
211 | struct sdhci_pltfm_host *pltfm_host; | |
212 | struct sdhci_at91_priv *priv; | |
213 | unsigned int caps0, caps1; | |
214 | unsigned int clk_base, clk_mul; | |
215 | unsigned int gck_rate, real_gck_rate; | |
216 | int ret; | |
4406433d | 217 | unsigned int preset_div; |
bb5f8ea4 | 218 | |
219 | match = of_match_device(sdhci_at91_dt_match, &pdev->dev); | |
220 | if (!match) | |
221 | return -EINVAL; | |
222 | soc_data = match->data; | |
223 | ||
10f1c135 JZ |
224 | host = sdhci_pltfm_init(pdev, soc_data, sizeof(*priv)); |
225 | if (IS_ERR(host)) | |
226 | return PTR_ERR(host); | |
227 | ||
228 | pltfm_host = sdhci_priv(host); | |
229 | priv = sdhci_pltfm_priv(pltfm_host); | |
bb5f8ea4 | 230 | |
231 | priv->mainck = devm_clk_get(&pdev->dev, "baseclk"); | |
232 | if (IS_ERR(priv->mainck)) { | |
233 | dev_err(&pdev->dev, "failed to get baseclk\n"); | |
234 | return PTR_ERR(priv->mainck); | |
235 | } | |
236 | ||
237 | priv->hclock = devm_clk_get(&pdev->dev, "hclock"); | |
238 | if (IS_ERR(priv->hclock)) { | |
239 | dev_err(&pdev->dev, "failed to get hclock\n"); | |
240 | return PTR_ERR(priv->hclock); | |
241 | } | |
242 | ||
243 | priv->gck = devm_clk_get(&pdev->dev, "multclk"); | |
244 | if (IS_ERR(priv->gck)) { | |
245 | dev_err(&pdev->dev, "failed to get multclk\n"); | |
246 | return PTR_ERR(priv->gck); | |
247 | } | |
248 | ||
bb5f8ea4 | 249 | /* |
250 | * The mult clock is provided by as a generated clock by the PMC | |
251 | * controller. In order to set the rate of gck, we have to get the | |
252 | * base clock rate and the clock mult from capabilities. | |
253 | */ | |
254 | clk_prepare_enable(priv->hclock); | |
255 | caps0 = readl(host->ioaddr + SDHCI_CAPABILITIES); | |
256 | caps1 = readl(host->ioaddr + SDHCI_CAPABILITIES_1); | |
257 | clk_base = (caps0 & SDHCI_CLOCK_V3_BASE_MASK) >> SDHCI_CLOCK_BASE_SHIFT; | |
258 | clk_mul = (caps1 & SDHCI_CLOCK_MUL_MASK) >> SDHCI_CLOCK_MUL_SHIFT; | |
259 | gck_rate = clk_base * 1000000 * (clk_mul + 1); | |
260 | ret = clk_set_rate(priv->gck, gck_rate); | |
261 | if (ret < 0) { | |
262 | dev_err(&pdev->dev, "failed to set gck"); | |
263 | goto hclock_disable_unprepare; | |
bb5f8ea4 | 264 | } |
265 | /* | |
266 | * We need to check if we have the requested rate for gck because in | |
267 | * some cases this rate could be not supported. If it happens, the rate | |
268 | * is the closest one gck can provide. We have to update the value | |
269 | * of clk mul. | |
270 | */ | |
271 | real_gck_rate = clk_get_rate(priv->gck); | |
272 | if (real_gck_rate != gck_rate) { | |
273 | clk_mul = real_gck_rate / (clk_base * 1000000) - 1; | |
274 | caps1 &= (~SDHCI_CLOCK_MUL_MASK); | |
275 | caps1 |= ((clk_mul << SDHCI_CLOCK_MUL_SHIFT) & SDHCI_CLOCK_MUL_MASK); | |
276 | /* Set capabilities in r/w mode. */ | |
277 | writel(SDMMC_CACR_KEY | SDMMC_CACR_CAPWREN, host->ioaddr + SDMMC_CACR); | |
278 | writel(caps1, host->ioaddr + SDHCI_CAPABILITIES_1); | |
279 | /* Set capabilities in ro mode. */ | |
280 | writel(0, host->ioaddr + SDMMC_CACR); | |
281 | dev_info(&pdev->dev, "update clk mul to %u as gck rate is %u Hz\n", | |
282 | clk_mul, real_gck_rate); | |
283 | } | |
284 | ||
4406433d LD |
285 | /* |
286 | * We have to set preset values because it depends on the clk_mul | |
287 | * value. Moreover, SDR104 is supported in a degraded mode since the | |
288 | * maximum sd clock value is 120 MHz instead of 208 MHz. For that | |
289 | * reason, we need to use presets to support SDR104. | |
290 | */ | |
291 | preset_div = DIV_ROUND_UP(real_gck_rate, 24000000) - 1; | |
292 | writew(SDHCI_AT91_PRESET_COMMON_CONF | preset_div, | |
293 | host->ioaddr + SDHCI_PRESET_FOR_SDR12); | |
294 | preset_div = DIV_ROUND_UP(real_gck_rate, 50000000) - 1; | |
295 | writew(SDHCI_AT91_PRESET_COMMON_CONF | preset_div, | |
296 | host->ioaddr + SDHCI_PRESET_FOR_SDR25); | |
297 | preset_div = DIV_ROUND_UP(real_gck_rate, 100000000) - 1; | |
298 | writew(SDHCI_AT91_PRESET_COMMON_CONF | preset_div, | |
299 | host->ioaddr + SDHCI_PRESET_FOR_SDR50); | |
300 | preset_div = DIV_ROUND_UP(real_gck_rate, 120000000) - 1; | |
301 | writew(SDHCI_AT91_PRESET_COMMON_CONF | preset_div, | |
302 | host->ioaddr + SDHCI_PRESET_FOR_SDR104); | |
303 | preset_div = DIV_ROUND_UP(real_gck_rate, 50000000) - 1; | |
304 | writew(SDHCI_AT91_PRESET_COMMON_CONF | preset_div, | |
305 | host->ioaddr + SDHCI_PRESET_FOR_DDR50); | |
306 | ||
bb5f8ea4 | 307 | clk_prepare_enable(priv->mainck); |
308 | clk_prepare_enable(priv->gck); | |
309 | ||
bb5f8ea4 | 310 | ret = mmc_of_parse(host->mmc); |
311 | if (ret) | |
312 | goto clocks_disable_unprepare; | |
313 | ||
314 | sdhci_get_of_property(pdev); | |
315 | ||
f5f17813 | 316 | pm_runtime_get_noresume(&pdev->dev); |
317 | pm_runtime_set_active(&pdev->dev); | |
318 | pm_runtime_enable(&pdev->dev); | |
319 | pm_runtime_set_autosuspend_delay(&pdev->dev, 50); | |
320 | pm_runtime_use_autosuspend(&pdev->dev); | |
321 | ||
bb5f8ea4 | 322 | ret = sdhci_add_host(host); |
323 | if (ret) | |
f5f17813 | 324 | goto pm_runtime_disable; |
325 | ||
64e5cd72 | 326 | /* |
327 | * When calling sdhci_runtime_suspend_host(), the sdhci layer makes | |
328 | * the assumption that all the clocks of the controller are disabled. | |
329 | * It means we can't get irq from it when it is runtime suspended. | |
330 | * For that reason, it is not planned to wake-up on a card detect irq | |
331 | * from the controller. | |
332 | * If we want to use runtime PM and to be able to wake-up on card | |
333 | * insertion, we have to use a GPIO for the card detection or we can | |
334 | * use polling. Be aware that using polling will resume/suspend the | |
335 | * controller between each attempt. | |
336 | * Disable SDHCI_QUIRK_BROKEN_CARD_DETECTION to be sure nobody tries | |
337 | * to enable polling via device tree with broken-cd property. | |
338 | */ | |
860951c5 | 339 | if (mmc_card_is_removable(host->mmc) && |
287980e4 | 340 | mmc_gpio_get_cd(host->mmc) < 0) { |
64e5cd72 | 341 | host->mmc->caps |= MMC_CAP_NEEDS_POLL; |
342 | host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION; | |
343 | } | |
344 | ||
7a1e3f14 LD |
345 | /* |
346 | * If the device attached to the MMC bus is not removable, it is safer | |
347 | * to set the Force Card Detect bit. People often don't connect the | |
348 | * card detect signal and use this pin for another purpose. If the card | |
349 | * detect pin is not muxed to SDHCI controller, a default value is | |
350 | * used. This value can be different from a SoC revision to another | |
351 | * one. Problems come when this default value is not card present. To | |
352 | * avoid this case, if the device is non removable then the card | |
353 | * detection procedure using the SDMCC_CD signal is bypassed. | |
354 | * This bit is reset when a software reset for all command is performed | |
355 | * so we need to implement our own reset function to set back this bit. | |
356 | */ | |
357 | if (host->mmc->caps & MMC_CAP_NONREMOVABLE) | |
358 | sdhci_at91_set_force_card_detect(host); | |
359 | ||
f5f17813 | 360 | pm_runtime_put_autosuspend(&pdev->dev); |
bb5f8ea4 | 361 | |
362 | return 0; | |
363 | ||
f5f17813 | 364 | pm_runtime_disable: |
365 | pm_runtime_disable(&pdev->dev); | |
366 | pm_runtime_set_suspended(&pdev->dev); | |
2df9d58f | 367 | pm_runtime_put_noidle(&pdev->dev); |
bb5f8ea4 | 368 | clocks_disable_unprepare: |
369 | clk_disable_unprepare(priv->gck); | |
370 | clk_disable_unprepare(priv->mainck); | |
371 | hclock_disable_unprepare: | |
372 | clk_disable_unprepare(priv->hclock); | |
373 | sdhci_pltfm_free(pdev); | |
374 | return ret; | |
375 | } | |
376 | ||
377 | static int sdhci_at91_remove(struct platform_device *pdev) | |
378 | { | |
379 | struct sdhci_host *host = platform_get_drvdata(pdev); | |
380 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
10f1c135 JZ |
381 | struct sdhci_at91_priv *priv = sdhci_pltfm_priv(pltfm_host); |
382 | struct clk *gck = priv->gck; | |
383 | struct clk *hclock = priv->hclock; | |
384 | struct clk *mainck = priv->mainck; | |
bb5f8ea4 | 385 | |
f5f17813 | 386 | pm_runtime_get_sync(&pdev->dev); |
387 | pm_runtime_disable(&pdev->dev); | |
388 | pm_runtime_put_noidle(&pdev->dev); | |
389 | ||
bb5f8ea4 | 390 | sdhci_pltfm_unregister(pdev); |
391 | ||
10f1c135 JZ |
392 | clk_disable_unprepare(gck); |
393 | clk_disable_unprepare(hclock); | |
394 | clk_disable_unprepare(mainck); | |
bb5f8ea4 | 395 | |
396 | return 0; | |
397 | } | |
398 | ||
399 | static struct platform_driver sdhci_at91_driver = { | |
400 | .driver = { | |
401 | .name = "sdhci-at91", | |
bb5f8ea4 | 402 | .of_match_table = sdhci_at91_dt_match, |
f5f17813 | 403 | .pm = &sdhci_at91_dev_pm_ops, |
bb5f8ea4 | 404 | }, |
405 | .probe = sdhci_at91_probe, | |
406 | .remove = sdhci_at91_remove, | |
407 | }; | |
408 | ||
409 | module_platform_driver(sdhci_at91_driver); | |
410 | ||
411 | MODULE_DESCRIPTION("SDHCI driver for at91"); | |
412 | MODULE_AUTHOR("Ludovic Desroches <ludovic.desroches@atmel.com>"); | |
413 | MODULE_LICENSE("GPL v2"); |