[mirror_ubuntu-eoan-kernel.git] / drivers / mmc / host / sdhci-of-at91.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Atmel SDMMC controller driver.
 *
 * Copyright (C) 2015 Atmel,
 *		 2015 Ludovic Desroches <ludovic.desroches@atmel.com>
 */

#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/mmc/host.h>
#include <linux/mmc/slot-gpio.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/pm.h>
#include <linux/pm_runtime.h>

#include "sdhci-pltfm.h"

#define SDMMC_MC1R	0x204
#define		SDMMC_MC1R_DDR		BIT(3)
#define		SDMMC_MC1R_FCD		BIT(7)
#define SDMMC_CACR	0x230
#define		SDMMC_CACR_CAPWREN	BIT(0)
#define		SDMMC_CACR_KEY		(0x46 << 8)

#define SDHCI_AT91_PRESET_COMMON_CONF	0x400 /* drv type B, programmable clock mode */

struct sdhci_at91_priv {
	struct clk *hclock;
	struct clk *gck;
	struct clk *mainck;
	bool restore_needed;
};

static void sdhci_at91_set_force_card_detect(struct sdhci_host *host)
{
	u8 mc1r;

	mc1r = readb(host->ioaddr + SDMMC_MC1R);
	mc1r |= SDMMC_MC1R_FCD;
	writeb(mc1r, host->ioaddr + SDMMC_MC1R);
}

static void sdhci_at91_set_clock(struct sdhci_host *host, unsigned int clock)
{
	u16 clk;
	unsigned long timeout;

	host->mmc->actual_clock = 0;

	/*
	 * There is no requirement to disable the internal clock before
	 * changing the SD clock configuration. Moreover, disabling the
	 * internal clock, changing the configuration and re-enabling the
	 * internal clock causes some bugs. It can prevent to get the internal
	 * clock stable flag ready and an unexpected switch to the base clock
	 * when using presets.
	 */
	clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
	clk &= SDHCI_CLOCK_INT_EN;
	sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);

	if (clock == 0)
		return;

	clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock);

	clk |= SDHCI_CLOCK_INT_EN;
	sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);

	/* Wait max 20 ms */
	timeout = 20;
	while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
		& SDHCI_CLOCK_INT_STABLE)) {
		if (timeout == 0) {
			pr_err("%s: Internal clock never stabilised.\n",
			       mmc_hostname(host->mmc));
			return;
		}
		timeout--;
		mdelay(1);
	}

	clk |= SDHCI_CLOCK_CARD_EN;
	sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
}

/*
 * In this specific implementation of the SDHCI controller, the power register
 * needs to have a valid voltage set even when the power supply is managed by
 * an external regulator.
 */
static void sdhci_at91_set_power(struct sdhci_host *host, unsigned char mode,
		     unsigned short vdd)
{
	if (!IS_ERR(host->mmc->supply.vmmc)) {
		struct mmc_host *mmc = host->mmc;

		mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd);
	}
	sdhci_set_power_noreg(host, mode, vdd);
}

static void sdhci_at91_set_uhs_signaling(struct sdhci_host *host,
					 unsigned int timing)
{
	if (timing == MMC_TIMING_MMC_DDR52)
		sdhci_writeb(host, SDMMC_MC1R_DDR, SDMMC_MC1R);
	sdhci_set_uhs_signaling(host, timing);
}

static void sdhci_at91_reset(struct sdhci_host *host, u8 mask)
{
	sdhci_reset(host, mask);

	if (host->mmc->caps & MMC_CAP_NONREMOVABLE)
		sdhci_at91_set_force_card_detect(host);
}

static const struct sdhci_ops sdhci_at91_sama5d2_ops = {
	.set_clock		= sdhci_at91_set_clock,
	.set_bus_width		= sdhci_set_bus_width,
	.reset			= sdhci_at91_reset,
	.set_uhs_signaling	= sdhci_at91_set_uhs_signaling,
	.set_power		= sdhci_at91_set_power,
};

static const struct sdhci_pltfm_data soc_data_sama5d2 = {
	.ops = &sdhci_at91_sama5d2_ops,
};

static const struct of_device_id sdhci_at91_dt_match[] = {
	{ .compatible = "atmel,sama5d2-sdhci", .data = &soc_data_sama5d2 },
	{}
};
MODULE_DEVICE_TABLE(of, sdhci_at91_dt_match);

static int sdhci_at91_set_clks_presets(struct device *dev)
{
	struct sdhci_host *host = dev_get_drvdata(dev);
	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
	struct sdhci_at91_priv *priv = sdhci_pltfm_priv(pltfm_host);
	int ret;
	unsigned int			caps0, caps1;
	unsigned int			clk_base, clk_mul;
	unsigned int			gck_rate, real_gck_rate;
	unsigned int			preset_div;

	/*
	 * The mult clock is provided by as a generated clock by the PMC
	 * controller. In order to set the rate of gck, we have to get the
	 * base clock rate and the clock mult from capabilities.
	 */
	clk_prepare_enable(priv->hclock);
	caps0 = readl(host->ioaddr + SDHCI_CAPABILITIES);
	caps1 = readl(host->ioaddr + SDHCI_CAPABILITIES_1);
	clk_base = (caps0 & SDHCI_CLOCK_V3_BASE_MASK) >> SDHCI_CLOCK_BASE_SHIFT;
	clk_mul = (caps1 & SDHCI_CLOCK_MUL_MASK) >> SDHCI_CLOCK_MUL_SHIFT;
	gck_rate = clk_base * 1000000 * (clk_mul + 1);
	ret = clk_set_rate(priv->gck, gck_rate);
	if (ret < 0) {
		dev_err(dev, "failed to set gck");
		clk_disable_unprepare(priv->hclock);
		return ret;
	}
	/*
	 * We need to check if we have the requested rate for gck because in
	 * some cases this rate could be not supported. If it happens, the rate
	 * is the closest one gck can provide. We have to update the value
	 * of clk mul.
	 */
	real_gck_rate = clk_get_rate(priv->gck);
	if (real_gck_rate != gck_rate) {
		clk_mul = real_gck_rate / (clk_base * 1000000) - 1;
		caps1 &= (~SDHCI_CLOCK_MUL_MASK);
		caps1 |= ((clk_mul << SDHCI_CLOCK_MUL_SHIFT) &
			  SDHCI_CLOCK_MUL_MASK);
		/* Set capabilities in r/w mode. */
		writel(SDMMC_CACR_KEY | SDMMC_CACR_CAPWREN,
		       host->ioaddr + SDMMC_CACR);
		writel(caps1, host->ioaddr + SDHCI_CAPABILITIES_1);
		/* Set capabilities in ro mode. */
		writel(0, host->ioaddr + SDMMC_CACR);
		dev_info(dev, "update clk mul to %u as gck rate is %u Hz\n",
			 clk_mul, real_gck_rate);
	}

	/*
	 * We have to set preset values because it depends on the clk_mul
	 * value. Moreover, SDR104 is supported in a degraded mode since the
	 * maximum sd clock value is 120 MHz instead of 208 MHz. For that
	 * reason, we need to use presets to support SDR104.
	 */
	preset_div = DIV_ROUND_UP(real_gck_rate, 24000000) - 1;
	writew(SDHCI_AT91_PRESET_COMMON_CONF | preset_div,
	       host->ioaddr + SDHCI_PRESET_FOR_SDR12);
	preset_div = DIV_ROUND_UP(real_gck_rate, 50000000) - 1;
	writew(SDHCI_AT91_PRESET_COMMON_CONF | preset_div,
	       host->ioaddr + SDHCI_PRESET_FOR_SDR25);
	preset_div = DIV_ROUND_UP(real_gck_rate, 100000000) - 1;
	writew(SDHCI_AT91_PRESET_COMMON_CONF | preset_div,
	       host->ioaddr + SDHCI_PRESET_FOR_SDR50);
	preset_div = DIV_ROUND_UP(real_gck_rate, 120000000) - 1;
	writew(SDHCI_AT91_PRESET_COMMON_CONF | preset_div,
	       host->ioaddr + SDHCI_PRESET_FOR_SDR104);
	preset_div = DIV_ROUND_UP(real_gck_rate, 50000000) - 1;
	writew(SDHCI_AT91_PRESET_COMMON_CONF | preset_div,
	       host->ioaddr + SDHCI_PRESET_FOR_DDR50);

	clk_prepare_enable(priv->mainck);
	clk_prepare_enable(priv->gck);

	return 0;
}

#ifdef CONFIG_PM_SLEEP
static int sdhci_at91_suspend(struct device *dev)
{
	struct sdhci_host *host = dev_get_drvdata(dev);
	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
	struct sdhci_at91_priv *priv = sdhci_pltfm_priv(pltfm_host);
	int ret;

	ret = pm_runtime_force_suspend(dev);

	priv->restore_needed = true;

	return ret;
}
#endif /* CONFIG_PM_SLEEP */

#ifdef CONFIG_PM
static int sdhci_at91_runtime_suspend(struct device *dev)
{
	struct sdhci_host *host = dev_get_drvdata(dev);
	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
	struct sdhci_at91_priv *priv = sdhci_pltfm_priv(pltfm_host);
	int ret;

	ret = sdhci_runtime_suspend_host(host);

	if (host->tuning_mode != SDHCI_TUNING_MODE_3)
		mmc_retune_needed(host->mmc);

	clk_disable_unprepare(priv->gck);
	clk_disable_unprepare(priv->hclock);
	clk_disable_unprepare(priv->mainck);

	return ret;
}

static int sdhci_at91_runtime_resume(struct device *dev)
{
	struct sdhci_host *host = dev_get_drvdata(dev);
	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
	struct sdhci_at91_priv *priv = sdhci_pltfm_priv(pltfm_host);
	int ret;

	if (priv->restore_needed) {
		ret = sdhci_at91_set_clks_presets(dev);
		if (ret)
			return ret;

		priv->restore_needed = false;
		goto out;
	}

	ret = clk_prepare_enable(priv->mainck);
	if (ret) {
		dev_err(dev, "can't enable mainck\n");
		return ret;
	}

	ret = clk_prepare_enable(priv->hclock);
	if (ret) {
		dev_err(dev, "can't enable hclock\n");
		return ret;
	}

	ret = clk_prepare_enable(priv->gck);
	if (ret) {
		dev_err(dev, "can't enable gck\n");
		return ret;
	}

out:
	return sdhci_runtime_resume_host(host, 0);
}
#endif /* CONFIG_PM */

static const struct dev_pm_ops sdhci_at91_dev_pm_ops = {
	SET_SYSTEM_SLEEP_PM_OPS(sdhci_at91_suspend, pm_runtime_force_resume)
	SET_RUNTIME_PM_OPS(sdhci_at91_runtime_suspend,
			   sdhci_at91_runtime_resume,
			   NULL)
};

static int sdhci_at91_probe(struct platform_device *pdev)
{
	const struct of_device_id	*match;
	const struct sdhci_pltfm_data	*soc_data;
	struct sdhci_host		*host;
	struct sdhci_pltfm_host		*pltfm_host;
	struct sdhci_at91_priv		*priv;
	int				ret;

	match = of_match_device(sdhci_at91_dt_match, &pdev->dev);
	if (!match)
		return -EINVAL;
	soc_data = match->data;

	host = sdhci_pltfm_init(pdev, soc_data, sizeof(*priv));
	if (IS_ERR(host))
		return PTR_ERR(host);

	pltfm_host = sdhci_priv(host);
	priv = sdhci_pltfm_priv(pltfm_host);

	priv->mainck = devm_clk_get(&pdev->dev, "baseclk");
	if (IS_ERR(priv->mainck)) {
		dev_err(&pdev->dev, "failed to get baseclk\n");
		return PTR_ERR(priv->mainck);
	}

	priv->hclock = devm_clk_get(&pdev->dev, "hclock");
	if (IS_ERR(priv->hclock)) {
		dev_err(&pdev->dev, "failed to get hclock\n");
		return PTR_ERR(priv->hclock);
	}

	priv->gck = devm_clk_get(&pdev->dev, "multclk");
	if (IS_ERR(priv->gck)) {
		dev_err(&pdev->dev, "failed to get multclk\n");
		return PTR_ERR(priv->gck);
	}

	ret = sdhci_at91_set_clks_presets(&pdev->dev);
	if (ret)
		goto sdhci_pltfm_free;

	priv->restore_needed = false;

	ret = mmc_of_parse(host->mmc);
	if (ret)
		goto clocks_disable_unprepare;

	sdhci_get_of_property(pdev);

	pm_runtime_get_noresume(&pdev->dev);
	pm_runtime_set_active(&pdev->dev);
	pm_runtime_enable(&pdev->dev);
	pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
	pm_runtime_use_autosuspend(&pdev->dev);

	/* HS200 is broken at this moment */
	host->quirks2 |= SDHCI_QUIRK2_BROKEN_HS200;

	ret = sdhci_add_host(host);
	if (ret)
		goto pm_runtime_disable;

	/*
	 * When calling sdhci_runtime_suspend_host(), the sdhci layer makes
	 * the assumption that all the clocks of the controller are disabled.
	 * It means we can't get irq from it when it is runtime suspended.
	 * For that reason, it is not planned to wake-up on a card detect irq
	 * from the controller.
	 * If we want to use runtime PM and to be able to wake-up on card
	 * insertion, we have to use a GPIO for the card detection or we can
	 * use polling. Be aware that using polling will resume/suspend the
	 * controller between each attempt.
	 * Disable SDHCI_QUIRK_BROKEN_CARD_DETECTION to be sure nobody tries
	 * to enable polling via device tree with broken-cd property.
	 */
	if (mmc_card_is_removable(host->mmc) &&
	    mmc_gpio_get_cd(host->mmc) < 0) {
		host->mmc->caps |= MMC_CAP_NEEDS_POLL;
		host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION;
	}

	/*
	 * If the device attached to the MMC bus is not removable, it is safer
	 * to set the Force Card Detect bit. People often don't connect the
	 * card detect signal and use this pin for another purpose. If the card
	 * detect pin is not muxed to SDHCI controller, a default value is
	 * used. This value can be different from a SoC revision to another
	 * one. Problems come when this default value is not card present. To
	 * avoid this case, if the device is non removable then the card
	 * detection procedure using the SDMCC_CD signal is bypassed.
	 * This bit is reset when a software reset for all command is performed
	 * so we need to implement our own reset function to set back this bit.
	 */
	if (host->mmc->caps & MMC_CAP_NONREMOVABLE)
		sdhci_at91_set_force_card_detect(host);

	pm_runtime_put_autosuspend(&pdev->dev);

	return 0;

pm_runtime_disable:
	pm_runtime_disable(&pdev->dev);
	pm_runtime_set_suspended(&pdev->dev);
	pm_runtime_put_noidle(&pdev->dev);
clocks_disable_unprepare:
	clk_disable_unprepare(priv->gck);
	clk_disable_unprepare(priv->mainck);
	clk_disable_unprepare(priv->hclock);
sdhci_pltfm_free:
	sdhci_pltfm_free(pdev);
	return ret;
}

static int sdhci_at91_remove(struct platform_device *pdev)
{
	struct sdhci_host	*host = platform_get_drvdata(pdev);
	struct sdhci_pltfm_host	*pltfm_host = sdhci_priv(host);
	struct sdhci_at91_priv	*priv = sdhci_pltfm_priv(pltfm_host);
	struct clk *gck = priv->gck;
	struct clk *hclock = priv->hclock;
	struct clk *mainck = priv->mainck;

	pm_runtime_get_sync(&pdev->dev);
	pm_runtime_disable(&pdev->dev);
	pm_runtime_put_noidle(&pdev->dev);

	sdhci_pltfm_unregister(pdev);

	clk_disable_unprepare(gck);
	clk_disable_unprepare(hclock);
	clk_disable_unprepare(mainck);

	return 0;
}

static struct platform_driver sdhci_at91_driver = {
	.driver		= {
		.name	= "sdhci-at91",
		.of_match_table = sdhci_at91_dt_match,
		.pm	= &sdhci_at91_dev_pm_ops,
	},
	.probe		= sdhci_at91_probe,
	.remove		= sdhci_at91_remove,
};

module_platform_driver(sdhci_at91_driver);

MODULE_DESCRIPTION("SDHCI driver for at91");
MODULE_AUTHOR("Ludovic Desroches <ludovic.desroches@atmel.com>");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
9c92ab61	1	// SPDX-License-Identifier: GPL-2.0-only
bb5f8ea4	2	/*
	3	* Atmel SDMMC controller driver.
	4	*
	5	* Copyright (C) 2015 Atmel,
	6	* 2015 Ludovic Desroches <ludovic.desroches@atmel.com>
bb5f8ea4	7	*/
	8
	9	#include <linux/clk.h>
4e289a7d	10	#include <linux/delay.h>
bb5f8ea4	11	#include <linux/err.h>
bb5f8ea4	12	#include <linux/io.h>
4406433d	13	#include <linux/kernel.h>
bb5f8ea4	14	#include <linux/mmc/host.h>
64e5cd72	15	#include <linux/mmc/slot-gpio.h>
bb5f8ea4	16	#include <linux/module.h>
	17	#include <linux/of.h>
	18	#include <linux/of_device.h>
f5f17813	19	#include <linux/pm.h>
f5f17813	20	#include <linux/pm_runtime.h>
bb5f8ea4	21
	22	#include "sdhci-pltfm.h"
	23
d0918764 LD	24	#define SDMMC_MC1R 0x204
d0918764 LD	25	#define SDMMC_MC1R_DDR BIT(3)
7a1e3f14	26	#define SDMMC_MC1R_FCD BIT(7)
bb5f8ea4	27	#define SDMMC_CACR 0x230
	28	#define SDMMC_CACR_CAPWREN BIT(0)
	29	#define SDMMC_CACR_KEY (0x46 << 8)
	30
4406433d LD	31	#define SDHCI_AT91_PRESET_COMMON_CONF 0x400 /* drv type B, programmable clock mode */
4406433d LD	32
bb5f8ea4	33	struct sdhci_at91_priv {
	34	struct clk *hclock;
	35	struct clk *gck;
	36	struct clk *mainck;
e2b372eb	37	bool restore_needed;
bb5f8ea4	38	};
bb5f8ea4	39
7a1e3f14 LD	40	static void sdhci_at91_set_force_card_detect(struct sdhci_host *host)
	41	{
	42	u8 mc1r;
	43
	44	mc1r = readb(host->ioaddr + SDMMC_MC1R);
	45	mc1r \|= SDMMC_MC1R_FCD;
	46	writeb(mc1r, host->ioaddr + SDMMC_MC1R);
	47	}
	48
4e289a7d LD	49	static void sdhci_at91_set_clock(struct sdhci_host *host, unsigned int clock)
	50	{
	51	u16 clk;
	52	unsigned long timeout;
	53
	54	host->mmc->actual_clock = 0;
	55
	56	/*
	57	* There is no requirement to disable the internal clock before
	58	* changing the SD clock configuration. Moreover, disabling the
	59	* internal clock, changing the configuration and re-enabling the
	60	* internal clock causes some bugs. It can prevent to get the internal
	61	* clock stable flag ready and an unexpected switch to the base clock
	62	* when using presets.
	63	*/
	64	clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
	65	clk &= SDHCI_CLOCK_INT_EN;
	66	sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
	67
	68	if (clock == 0)
	69	return;
	70
	71	clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock);
	72
	73	clk \|= SDHCI_CLOCK_INT_EN;
	74	sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
	75
	76	/* Wait max 20 ms */
	77	timeout = 20;
	78	while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
	79	& SDHCI_CLOCK_INT_STABLE)) {
	80	if (timeout == 0) {
	81	pr_err("%s: Internal clock never stabilised.\n",
	82	mmc_hostname(host->mmc));
	83	return;
	84	}
	85	timeout--;
	86	mdelay(1);
	87	}
	88
	89	clk \|= SDHCI_CLOCK_CARD_EN;
	90	sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
	91	}
	92
2ce0c7b6 RI	93	/*
	94	* In this specific implementation of the SDHCI controller, the power register
	95	* needs to have a valid voltage set even when the power supply is managed by
	96	* an external regulator.
	97	*/
	98	static void sdhci_at91_set_power(struct sdhci_host *host, unsigned char mode,
	99	unsigned short vdd)
	100	{
	101	if (!IS_ERR(host->mmc->supply.vmmc)) {
	102	struct mmc_host *mmc = host->mmc;
	103
2ce0c7b6	104	mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd);
2ce0c7b6 RI	105	}
	106	sdhci_set_power_noreg(host, mode, vdd);
	107	}
	108
519c51af CIK	109	static void sdhci_at91_set_uhs_signaling(struct sdhci_host *host,
519c51af CIK	110	unsigned int timing)
d0918764 LD	111	{
	112	if (timing == MMC_TIMING_MMC_DDR52)
	113	sdhci_writeb(host, SDMMC_MC1R_DDR, SDMMC_MC1R);
	114	sdhci_set_uhs_signaling(host, timing);
	115	}
	116
7a1e3f14 LD	117	static void sdhci_at91_reset(struct sdhci_host *host, u8 mask)
	118	{
	119	sdhci_reset(host, mask);
	120
	121	if (host->mmc->caps & MMC_CAP_NONREMOVABLE)
	122	sdhci_at91_set_force_card_detect(host);
	123	}
	124
bb5f8ea4	125	static const struct sdhci_ops sdhci_at91_sama5d2_ops = {
4e289a7d	126	.set_clock = sdhci_at91_set_clock,
bb5f8ea4	127	.set_bus_width = sdhci_set_bus_width,
7a1e3f14	128	.reset = sdhci_at91_reset,
d0918764	129	.set_uhs_signaling = sdhci_at91_set_uhs_signaling,
2ce0c7b6	130	.set_power = sdhci_at91_set_power,
bb5f8ea4	131	};
	132
	133	static const struct sdhci_pltfm_data soc_data_sama5d2 = {
	134	.ops = &sdhci_at91_sama5d2_ops,
	135	};
	136
	137	static const struct of_device_id sdhci_at91_dt_match[] = {
	138	{ .compatible = "atmel,sama5d2-sdhci", .data = &soc_data_sama5d2 },
	139	{}
	140	};
d9943c68	141	MODULE_DEVICE_TABLE(of, sdhci_at91_dt_match);
bb5f8ea4	142
c8a019e7 QS	143	static int sdhci_at91_set_clks_presets(struct device *dev)
	144	{
	145	struct sdhci_host *host = dev_get_drvdata(dev);
	146	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
	147	struct sdhci_at91_priv *priv = sdhci_pltfm_priv(pltfm_host);
	148	int ret;
	149	unsigned int caps0, caps1;
	150	unsigned int clk_base, clk_mul;
	151	unsigned int gck_rate, real_gck_rate;
	152	unsigned int preset_div;
	153
	154	/*
	155	* The mult clock is provided by as a generated clock by the PMC
	156	* controller. In order to set the rate of gck, we have to get the
	157	* base clock rate and the clock mult from capabilities.
	158	*/
	159	clk_prepare_enable(priv->hclock);
	160	caps0 = readl(host->ioaddr + SDHCI_CAPABILITIES);
	161	caps1 = readl(host->ioaddr + SDHCI_CAPABILITIES_1);
	162	clk_base = (caps0 & SDHCI_CLOCK_V3_BASE_MASK) >> SDHCI_CLOCK_BASE_SHIFT;
	163	clk_mul = (caps1 & SDHCI_CLOCK_MUL_MASK) >> SDHCI_CLOCK_MUL_SHIFT;
	164	gck_rate = clk_base * 1000000 * (clk_mul + 1);
	165	ret = clk_set_rate(priv->gck, gck_rate);
	166	if (ret < 0) {
	167	dev_err(dev, "failed to set gck");
	168	clk_disable_unprepare(priv->hclock);
	169	return ret;
	170	}
	171	/*
	172	* We need to check if we have the requested rate for gck because in
	173	* some cases this rate could be not supported. If it happens, the rate
	174	* is the closest one gck can provide. We have to update the value
	175	* of clk mul.
	176	*/
	177	real_gck_rate = clk_get_rate(priv->gck);
	178	if (real_gck_rate != gck_rate) {
	179	clk_mul = real_gck_rate / (clk_base * 1000000) - 1;
	180	caps1 &= (~SDHCI_CLOCK_MUL_MASK);
	181	caps1 \|= ((clk_mul << SDHCI_CLOCK_MUL_SHIFT) &
	182	SDHCI_CLOCK_MUL_MASK);
	183	/* Set capabilities in r/w mode. */
	184	writel(SDMMC_CACR_KEY \| SDMMC_CACR_CAPWREN,
	185	host->ioaddr + SDMMC_CACR);
	186	writel(caps1, host->ioaddr + SDHCI_CAPABILITIES_1);
	187	/* Set capabilities in ro mode. */
	188	writel(0, host->ioaddr + SDMMC_CACR);
	189	dev_info(dev, "update clk mul to %u as gck rate is %u Hz\n",
	190	clk_mul, real_gck_rate);
	191	}
	192
	193	/*
	194	* We have to set preset values because it depends on the clk_mul
	195	* value. Moreover, SDR104 is supported in a degraded mode since the
	196	* maximum sd clock value is 120 MHz instead of 208 MHz. For that
	197	* reason, we need to use presets to support SDR104.
	198	*/
	199	preset_div = DIV_ROUND_UP(real_gck_rate, 24000000) - 1;
	200	writew(SDHCI_AT91_PRESET_COMMON_CONF \| preset_div,
	201	host->ioaddr + SDHCI_PRESET_FOR_SDR12);
	202	preset_div = DIV_ROUND_UP(real_gck_rate, 50000000) - 1;
	203	writew(SDHCI_AT91_PRESET_COMMON_CONF \| preset_div,
	204	host->ioaddr + SDHCI_PRESET_FOR_SDR25);
	205	preset_div = DIV_ROUND_UP(real_gck_rate, 100000000) - 1;
	206	writew(SDHCI_AT91_PRESET_COMMON_CONF \| preset_div,
207	host->ioaddr + SDHCI_PRESET_FOR_SDR50);
208	preset_div = DIV_ROUND_UP(real_gck_rate, 120000000) - 1;
209	writew(SDHCI_AT91_PRESET_COMMON_CONF \| preset_div,
210	host->ioaddr + SDHCI_PRESET_FOR_SDR104);
211	preset_div = DIV_ROUND_UP(real_gck_rate, 50000000) - 1;
212	writew(SDHCI_AT91_PRESET_COMMON_CONF \| preset_div,
213	host->ioaddr + SDHCI_PRESET_FOR_DDR50);
214
215	clk_prepare_enable(priv->mainck);
216	clk_prepare_enable(priv->gck);
217
218	return 0;
219	}
220
e2b372eb QS	221	#ifdef CONFIG_PM_SLEEP
	222	static int sdhci_at91_suspend(struct device *dev)
	223	{
	224	struct sdhci_host *host = dev_get_drvdata(dev);
	225	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
	226	struct sdhci_at91_priv *priv = sdhci_pltfm_priv(pltfm_host);
	227	int ret;
	228
	229	ret = pm_runtime_force_suspend(dev);
	230
	231	priv->restore_needed = true;
	232
	233	return ret;
	234	}
	235	#endif /* CONFIG_PM_SLEEP */
	236
f5f17813	237	#ifdef CONFIG_PM
	238	static int sdhci_at91_runtime_suspend(struct device *dev)
	239	{
	240	struct sdhci_host *host = dev_get_drvdata(dev);
	241	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
10f1c135	242	struct sdhci_at91_priv *priv = sdhci_pltfm_priv(pltfm_host);
f5f17813	243	int ret;
	244
	245	ret = sdhci_runtime_suspend_host(host);
	246
d38dcad4 AH	247	if (host->tuning_mode != SDHCI_TUNING_MODE_3)
	248	mmc_retune_needed(host->mmc);
	249
f5f17813	250	clk_disable_unprepare(priv->gck);
	251	clk_disable_unprepare(priv->hclock);
	252	clk_disable_unprepare(priv->mainck);
	253
	254	return ret;
	255	}
	256
	257	static int sdhci_at91_runtime_resume(struct device *dev)
	258	{
	259	struct sdhci_host *host = dev_get_drvdata(dev);
	260	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
10f1c135	261	struct sdhci_at91_priv *priv = sdhci_pltfm_priv(pltfm_host);
f5f17813	262	int ret;
f5f17813	263
e2b372eb QS	264	if (priv->restore_needed) {
	265	ret = sdhci_at91_set_clks_presets(dev);
	266	if (ret)
	267	return ret;
	268
	269	priv->restore_needed = false;
	270	goto out;
	271	}
	272
f5f17813	273	ret = clk_prepare_enable(priv->mainck);
	274	if (ret) {
	275	dev_err(dev, "can't enable mainck\n");
	276	return ret;
	277	}
	278
	279	ret = clk_prepare_enable(priv->hclock);
	280	if (ret) {
	281	dev_err(dev, "can't enable hclock\n");
	282	return ret;
	283	}
	284
	285	ret = clk_prepare_enable(priv->gck);
	286	if (ret) {
	287	dev_err(dev, "can't enable gck\n");
	288	return ret;
	289	}
	290
e2b372eb	291	out:
c6303c5d	292	return sdhci_runtime_resume_host(host, 0);
f5f17813	293	}
	294	#endif /* CONFIG_PM */
	295
	296	static const struct dev_pm_ops sdhci_at91_dev_pm_ops = {
e2b372eb	297	SET_SYSTEM_SLEEP_PM_OPS(sdhci_at91_suspend, pm_runtime_force_resume)
f5f17813	298	SET_RUNTIME_PM_OPS(sdhci_at91_runtime_suspend,
	299	sdhci_at91_runtime_resume,
	300	NULL)
	301	};
	302
bb5f8ea4	303	static int sdhci_at91_probe(struct platform_device *pdev)
	304	{
	305	const struct of_device_id *match;
	306	const struct sdhci_pltfm_data *soc_data;
	307	struct sdhci_host *host;
	308	struct sdhci_pltfm_host *pltfm_host;
	309	struct sdhci_at91_priv *priv;
bb5f8ea4	310	int ret;
	311
	312	match = of_match_device(sdhci_at91_dt_match, &pdev->dev);
	313	if (!match)
	314	return -EINVAL;
	315	soc_data = match->data;
	316
10f1c135 JZ	317	host = sdhci_pltfm_init(pdev, soc_data, sizeof(*priv));
	318	if (IS_ERR(host))
	319	return PTR_ERR(host);
	320
	321	pltfm_host = sdhci_priv(host);
	322	priv = sdhci_pltfm_priv(pltfm_host);
bb5f8ea4	323
	324	priv->mainck = devm_clk_get(&pdev->dev, "baseclk");
	325	if (IS_ERR(priv->mainck)) {
	326	dev_err(&pdev->dev, "failed to get baseclk\n");
	327	return PTR_ERR(priv->mainck);
	328	}
	329
	330	priv->hclock = devm_clk_get(&pdev->dev, "hclock");
	331	if (IS_ERR(priv->hclock)) {
	332	dev_err(&pdev->dev, "failed to get hclock\n");
	333	return PTR_ERR(priv->hclock);
	334	}
	335
	336	priv->gck = devm_clk_get(&pdev->dev, "multclk");
	337	if (IS_ERR(priv->gck)) {
	338	dev_err(&pdev->dev, "failed to get multclk\n");
	339	return PTR_ERR(priv->gck);
	340	}
	341
c8a019e7 QS	342	ret = sdhci_at91_set_clks_presets(&pdev->dev);
	343	if (ret)
	344	goto sdhci_pltfm_free;
bb5f8ea4	345
e2b372eb QS	346	priv->restore_needed = false;
e2b372eb QS	347
bb5f8ea4	348	ret = mmc_of_parse(host->mmc);
	349	if (ret)
	350	goto clocks_disable_unprepare;
	351
	352	sdhci_get_of_property(pdev);
	353
f5f17813	354	pm_runtime_get_noresume(&pdev->dev);
	355	pm_runtime_set_active(&pdev->dev);
	356	pm_runtime_enable(&pdev->dev);
	357	pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
	358	pm_runtime_use_autosuspend(&pdev->dev);
	359
7871aa60	360	/* HS200 is broken at this moment */
d9dab053	361	host->quirks2 \|= SDHCI_QUIRK2_BROKEN_HS200;
7871aa60	362
bb5f8ea4	363	ret = sdhci_add_host(host);
bb5f8ea4	364	if (ret)
f5f17813	365	goto pm_runtime_disable;
f5f17813	366
64e5cd72	367	/*
	368	* When calling sdhci_runtime_suspend_host(), the sdhci layer makes
	369	* the assumption that all the clocks of the controller are disabled.
	370	* It means we can't get irq from it when it is runtime suspended.
	371	* For that reason, it is not planned to wake-up on a card detect irq
	372	* from the controller.
	373	* If we want to use runtime PM and to be able to wake-up on card
	374	* insertion, we have to use a GPIO for the card detection or we can
	375	* use polling. Be aware that using polling will resume/suspend the
	376	* controller between each attempt.
	377	* Disable SDHCI_QUIRK_BROKEN_CARD_DETECTION to be sure nobody tries
	378	* to enable polling via device tree with broken-cd property.
	379	*/
860951c5	380	if (mmc_card_is_removable(host->mmc) &&
287980e4	381	mmc_gpio_get_cd(host->mmc) < 0) {
64e5cd72	382	host->mmc->caps \|= MMC_CAP_NEEDS_POLL;
	383	host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION;
	384	}
	385
7a1e3f14 LD	386	/*
	387	* If the device attached to the MMC bus is not removable, it is safer
	388	* to set the Force Card Detect bit. People often don't connect the
	389	* card detect signal and use this pin for another purpose. If the card
	390	* detect pin is not muxed to SDHCI controller, a default value is
	391	* used. This value can be different from a SoC revision to another
	392	* one. Problems come when this default value is not card present. To
	393	* avoid this case, if the device is non removable then the card
	394	* detection procedure using the SDMCC_CD signal is bypassed.
	395	* This bit is reset when a software reset for all command is performed
	396	* so we need to implement our own reset function to set back this bit.
	397	*/
	398	if (host->mmc->caps & MMC_CAP_NONREMOVABLE)
	399	sdhci_at91_set_force_card_detect(host);
	400
f5f17813	401	pm_runtime_put_autosuspend(&pdev->dev);
bb5f8ea4	402
	403	return 0;
	404
f5f17813	405	pm_runtime_disable:
	406	pm_runtime_disable(&pdev->dev);
	407	pm_runtime_set_suspended(&pdev->dev);
2df9d58f	408	pm_runtime_put_noidle(&pdev->dev);
bb5f8ea4	409	clocks_disable_unprepare:
	410	clk_disable_unprepare(priv->gck);
	411	clk_disable_unprepare(priv->mainck);
bb5f8ea4	412	clk_disable_unprepare(priv->hclock);
c8a019e7	413	sdhci_pltfm_free:
bb5f8ea4	414	sdhci_pltfm_free(pdev);
	415	return ret;
	416	}
	417
	418	static int sdhci_at91_remove(struct platform_device *pdev)
	419	{
	420	struct sdhci_host *host = platform_get_drvdata(pdev);
	421	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
10f1c135 JZ	422	struct sdhci_at91_priv *priv = sdhci_pltfm_priv(pltfm_host);
	423	struct clk *gck = priv->gck;
	424	struct clk *hclock = priv->hclock;
	425	struct clk *mainck = priv->mainck;
bb5f8ea4	426
f5f17813	427	pm_runtime_get_sync(&pdev->dev);
	428	pm_runtime_disable(&pdev->dev);
	429	pm_runtime_put_noidle(&pdev->dev);
	430
bb5f8ea4	431	sdhci_pltfm_unregister(pdev);
bb5f8ea4	432
10f1c135 JZ	433	clk_disable_unprepare(gck);
	434	clk_disable_unprepare(hclock);
	435	clk_disable_unprepare(mainck);
bb5f8ea4	436
	437	return 0;
	438	}
	439
	440	static struct platform_driver sdhci_at91_driver = {
	441	.driver = {
	442	.name = "sdhci-at91",
bb5f8ea4	443	.of_match_table = sdhci_at91_dt_match,
f5f17813	444	.pm = &sdhci_at91_dev_pm_ops,
bb5f8ea4	445	},
	446	.probe = sdhci_at91_probe,
	447	.remove = sdhci_at91_remove,
	448	};
	449
	450	module_platform_driver(sdhci_at91_driver);
	451
	452	MODULE_DESCRIPTION("SDHCI driver for at91");
	453	MODULE_AUTHOR("Ludovic Desroches <ludovic.desroches@atmel.com>");
	454	MODULE_LICENSE("GPL v2");