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b8c86fc5 PO |
1 | /* linux/drivers/mmc/host/sdhci-pci.c - SDHCI on PCI bus interface |
2 | * | |
3 | * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved. | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License as published by | |
7 | * the Free Software Foundation; either version 2 of the License, or (at | |
8 | * your option) any later version. | |
9 | * | |
10 | * Thanks to the following companies for their support: | |
11 | * | |
12 | * - JMicron (hardware and technical support) | |
13 | */ | |
14 | ||
a72016a4 | 15 | #include <linux/string.h> |
b8c86fc5 PO |
16 | #include <linux/delay.h> |
17 | #include <linux/highmem.h> | |
88b47679 | 18 | #include <linux/module.h> |
b8c86fc5 PO |
19 | #include <linux/pci.h> |
20 | #include <linux/dma-mapping.h> | |
5a0e3ad6 | 21 | #include <linux/slab.h> |
ccc92c23 | 22 | #include <linux/device.h> |
b8c86fc5 | 23 | #include <linux/mmc/host.h> |
e1bfad6d | 24 | #include <linux/mmc/mmc.h> |
b177bc91 AP |
25 | #include <linux/scatterlist.h> |
26 | #include <linux/io.h> | |
0f201655 | 27 | #include <linux/gpio.h> |
66fd8ad5 | 28 | #include <linux/pm_runtime.h> |
ff59c520 | 29 | #include <linux/mmc/slot-gpio.h> |
52c506f0 | 30 | #include <linux/mmc/sdhci-pci-data.h> |
3f23df72 | 31 | #include <linux/acpi.h> |
b8c86fc5 PO |
32 | |
33 | #include "sdhci.h" | |
522624f9 | 34 | #include "sdhci-pci.h" |
01acf691 | 35 | #include "sdhci-pci-o2micro.h" |
22606405 | 36 | |
fee686b7 AH |
37 | static int sdhci_pci_enable_dma(struct sdhci_host *host); |
38 | static void sdhci_pci_set_bus_width(struct sdhci_host *host, int width); | |
39 | static void sdhci_pci_hw_reset(struct sdhci_host *host); | |
fee686b7 | 40 | |
30cf2803 AH |
41 | #ifdef CONFIG_PM_SLEEP |
42 | static int __sdhci_pci_suspend_host(struct sdhci_pci_chip *chip) | |
43 | { | |
44 | int i, ret; | |
45 | ||
46 | for (i = 0; i < chip->num_slots; i++) { | |
47 | struct sdhci_pci_slot *slot = chip->slots[i]; | |
48 | struct sdhci_host *host; | |
49 | ||
50 | if (!slot) | |
51 | continue; | |
52 | ||
53 | host = slot->host; | |
54 | ||
55 | if (chip->pm_retune && host->tuning_mode != SDHCI_TUNING_MODE_3) | |
56 | mmc_retune_needed(host->mmc); | |
57 | ||
58 | ret = sdhci_suspend_host(host); | |
59 | if (ret) | |
60 | goto err_pci_suspend; | |
61 | ||
62 | if (host->mmc->pm_flags & MMC_PM_WAKE_SDIO_IRQ) | |
63 | sdhci_enable_irq_wakeups(host); | |
64 | } | |
65 | ||
66 | return 0; | |
67 | ||
68 | err_pci_suspend: | |
69 | while (--i >= 0) | |
70 | sdhci_resume_host(chip->slots[i]->host); | |
71 | return ret; | |
72 | } | |
73 | ||
74 | static int sdhci_pci_init_wakeup(struct sdhci_pci_chip *chip) | |
75 | { | |
76 | mmc_pm_flag_t pm_flags = 0; | |
77 | int i; | |
78 | ||
79 | for (i = 0; i < chip->num_slots; i++) { | |
80 | struct sdhci_pci_slot *slot = chip->slots[i]; | |
81 | ||
82 | if (slot) | |
83 | pm_flags |= slot->host->mmc->pm_flags; | |
84 | } | |
85 | ||
86 | return device_init_wakeup(&chip->pdev->dev, | |
87 | (pm_flags & MMC_PM_KEEP_POWER) && | |
88 | (pm_flags & MMC_PM_WAKE_SDIO_IRQ)); | |
89 | } | |
90 | ||
91 | static int sdhci_pci_suspend_host(struct sdhci_pci_chip *chip) | |
92 | { | |
93 | int ret; | |
94 | ||
95 | ret = __sdhci_pci_suspend_host(chip); | |
96 | if (ret) | |
97 | return ret; | |
98 | ||
99 | sdhci_pci_init_wakeup(chip); | |
100 | ||
101 | return 0; | |
102 | } | |
103 | ||
104 | int sdhci_pci_resume_host(struct sdhci_pci_chip *chip) | |
105 | { | |
106 | struct sdhci_pci_slot *slot; | |
107 | int i, ret; | |
108 | ||
109 | for (i = 0; i < chip->num_slots; i++) { | |
110 | slot = chip->slots[i]; | |
111 | if (!slot) | |
112 | continue; | |
113 | ||
114 | ret = sdhci_resume_host(slot->host); | |
115 | if (ret) | |
116 | return ret; | |
117 | } | |
118 | ||
119 | return 0; | |
120 | } | |
121 | #endif | |
122 | ||
966d696a AH |
123 | #ifdef CONFIG_PM |
124 | static int sdhci_pci_runtime_suspend_host(struct sdhci_pci_chip *chip) | |
125 | { | |
126 | struct sdhci_pci_slot *slot; | |
127 | struct sdhci_host *host; | |
128 | int i, ret; | |
129 | ||
130 | for (i = 0; i < chip->num_slots; i++) { | |
131 | slot = chip->slots[i]; | |
132 | if (!slot) | |
133 | continue; | |
134 | ||
135 | host = slot->host; | |
136 | ||
137 | ret = sdhci_runtime_suspend_host(host); | |
138 | if (ret) | |
139 | goto err_pci_runtime_suspend; | |
140 | ||
141 | if (chip->rpm_retune && | |
142 | host->tuning_mode != SDHCI_TUNING_MODE_3) | |
143 | mmc_retune_needed(host->mmc); | |
144 | } | |
145 | ||
146 | return 0; | |
147 | ||
148 | err_pci_runtime_suspend: | |
149 | while (--i >= 0) | |
150 | sdhci_runtime_resume_host(chip->slots[i]->host); | |
151 | return ret; | |
152 | } | |
153 | ||
154 | static int sdhci_pci_runtime_resume_host(struct sdhci_pci_chip *chip) | |
155 | { | |
156 | struct sdhci_pci_slot *slot; | |
157 | int i, ret; | |
158 | ||
159 | for (i = 0; i < chip->num_slots; i++) { | |
160 | slot = chip->slots[i]; | |
161 | if (!slot) | |
162 | continue; | |
163 | ||
164 | ret = sdhci_runtime_resume_host(slot->host); | |
165 | if (ret) | |
166 | return ret; | |
167 | } | |
168 | ||
169 | return 0; | |
170 | } | |
171 | #endif | |
172 | ||
22606405 PO |
173 | /*****************************************************************************\ |
174 | * * | |
175 | * Hardware specific quirk handling * | |
176 | * * | |
177 | \*****************************************************************************/ | |
178 | ||
179 | static int ricoh_probe(struct sdhci_pci_chip *chip) | |
180 | { | |
c99436fb CB |
181 | if (chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG || |
182 | chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SONY) | |
22606405 | 183 | chip->quirks |= SDHCI_QUIRK_NO_CARD_NO_RESET; |
ccc92c23 ML |
184 | return 0; |
185 | } | |
186 | ||
187 | static int ricoh_mmc_probe_slot(struct sdhci_pci_slot *slot) | |
188 | { | |
189 | slot->host->caps = | |
190 | ((0x21 << SDHCI_TIMEOUT_CLK_SHIFT) | |
191 | & SDHCI_TIMEOUT_CLK_MASK) | | |
22606405 | 192 | |
ccc92c23 ML |
193 | ((0x21 << SDHCI_CLOCK_BASE_SHIFT) |
194 | & SDHCI_CLOCK_BASE_MASK) | | |
195 | ||
196 | SDHCI_TIMEOUT_CLK_UNIT | | |
197 | SDHCI_CAN_VDD_330 | | |
1a1f1f04 | 198 | SDHCI_CAN_DO_HISPD | |
ccc92c23 ML |
199 | SDHCI_CAN_DO_SDMA; |
200 | return 0; | |
201 | } | |
202 | ||
b7813f0f | 203 | #ifdef CONFIG_PM_SLEEP |
ccc92c23 ML |
204 | static int ricoh_mmc_resume(struct sdhci_pci_chip *chip) |
205 | { | |
206 | /* Apply a delay to allow controller to settle */ | |
207 | /* Otherwise it becomes confused if card state changed | |
208 | during suspend */ | |
209 | msleep(500); | |
30cf2803 | 210 | return sdhci_pci_resume_host(chip); |
22606405 | 211 | } |
b7813f0f | 212 | #endif |
22606405 PO |
213 | |
214 | static const struct sdhci_pci_fixes sdhci_ricoh = { | |
215 | .probe = ricoh_probe, | |
84938294 VK |
216 | .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR | |
217 | SDHCI_QUIRK_FORCE_DMA | | |
218 | SDHCI_QUIRK_CLOCK_BEFORE_RESET, | |
22606405 PO |
219 | }; |
220 | ||
ccc92c23 ML |
221 | static const struct sdhci_pci_fixes sdhci_ricoh_mmc = { |
222 | .probe_slot = ricoh_mmc_probe_slot, | |
b7813f0f | 223 | #ifdef CONFIG_PM_SLEEP |
ccc92c23 | 224 | .resume = ricoh_mmc_resume, |
b7813f0f | 225 | #endif |
ccc92c23 ML |
226 | .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR | |
227 | SDHCI_QUIRK_CLOCK_BEFORE_RESET | | |
228 | SDHCI_QUIRK_NO_CARD_NO_RESET | | |
229 | SDHCI_QUIRK_MISSING_CAPS | |
230 | }; | |
231 | ||
22606405 PO |
232 | static const struct sdhci_pci_fixes sdhci_ene_712 = { |
233 | .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE | | |
234 | SDHCI_QUIRK_BROKEN_DMA, | |
235 | }; | |
236 | ||
237 | static const struct sdhci_pci_fixes sdhci_ene_714 = { | |
238 | .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE | | |
239 | SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS | | |
240 | SDHCI_QUIRK_BROKEN_DMA, | |
241 | }; | |
242 | ||
243 | static const struct sdhci_pci_fixes sdhci_cafe = { | |
244 | .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER | | |
a0874897 | 245 | SDHCI_QUIRK_NO_BUSY_IRQ | |
55fc05b7 | 246 | SDHCI_QUIRK_BROKEN_CARD_DETECTION | |
ee53ab5d | 247 | SDHCI_QUIRK_BROKEN_TIMEOUT_VAL, |
22606405 PO |
248 | }; |
249 | ||
43e968ce DB |
250 | static const struct sdhci_pci_fixes sdhci_intel_qrk = { |
251 | .quirks = SDHCI_QUIRK_NO_HISPD_BIT, | |
252 | }; | |
253 | ||
68077b02 ML |
254 | static int mrst_hc_probe_slot(struct sdhci_pci_slot *slot) |
255 | { | |
256 | slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA; | |
257 | return 0; | |
258 | } | |
259 | ||
f9ee3eab AC |
260 | /* |
261 | * ADMA operation is disabled for Moorestown platform due to | |
262 | * hardware bugs. | |
263 | */ | |
35ac6f08 | 264 | static int mrst_hc_probe(struct sdhci_pci_chip *chip) |
f9ee3eab AC |
265 | { |
266 | /* | |
35ac6f08 JP |
267 | * slots number is fixed here for MRST as SDIO3/5 are never used and |
268 | * have hardware bugs. | |
f9ee3eab AC |
269 | */ |
270 | chip->num_slots = 1; | |
271 | return 0; | |
272 | } | |
273 | ||
296e0b03 AS |
274 | static int pch_hc_probe_slot(struct sdhci_pci_slot *slot) |
275 | { | |
276 | slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA; | |
277 | return 0; | |
278 | } | |
279 | ||
162d6f98 | 280 | #ifdef CONFIG_PM |
66fd8ad5 | 281 | |
c5e027a4 | 282 | static irqreturn_t sdhci_pci_sd_cd(int irq, void *dev_id) |
66fd8ad5 AH |
283 | { |
284 | struct sdhci_pci_slot *slot = dev_id; | |
285 | struct sdhci_host *host = slot->host; | |
286 | ||
287 | mmc_detect_change(host->mmc, msecs_to_jiffies(200)); | |
288 | return IRQ_HANDLED; | |
289 | } | |
290 | ||
c5e027a4 | 291 | static void sdhci_pci_add_own_cd(struct sdhci_pci_slot *slot) |
66fd8ad5 | 292 | { |
c5e027a4 | 293 | int err, irq, gpio = slot->cd_gpio; |
66fd8ad5 AH |
294 | |
295 | slot->cd_gpio = -EINVAL; | |
296 | slot->cd_irq = -EINVAL; | |
297 | ||
c5e027a4 AH |
298 | if (!gpio_is_valid(gpio)) |
299 | return; | |
300 | ||
c10bc372 | 301 | err = devm_gpio_request(&slot->chip->pdev->dev, gpio, "sd_cd"); |
66fd8ad5 AH |
302 | if (err < 0) |
303 | goto out; | |
304 | ||
305 | err = gpio_direction_input(gpio); | |
306 | if (err < 0) | |
307 | goto out_free; | |
308 | ||
309 | irq = gpio_to_irq(gpio); | |
310 | if (irq < 0) | |
311 | goto out_free; | |
312 | ||
c5e027a4 | 313 | err = request_irq(irq, sdhci_pci_sd_cd, IRQF_TRIGGER_RISING | |
66fd8ad5 AH |
314 | IRQF_TRIGGER_FALLING, "sd_cd", slot); |
315 | if (err) | |
316 | goto out_free; | |
317 | ||
318 | slot->cd_gpio = gpio; | |
319 | slot->cd_irq = irq; | |
66fd8ad5 | 320 | |
c5e027a4 | 321 | return; |
66fd8ad5 AH |
322 | |
323 | out_free: | |
c10bc372 | 324 | devm_gpio_free(&slot->chip->pdev->dev, gpio); |
66fd8ad5 AH |
325 | out: |
326 | dev_warn(&slot->chip->pdev->dev, "failed to setup card detect wake up\n"); | |
66fd8ad5 AH |
327 | } |
328 | ||
c5e027a4 | 329 | static void sdhci_pci_remove_own_cd(struct sdhci_pci_slot *slot) |
66fd8ad5 AH |
330 | { |
331 | if (slot->cd_irq >= 0) | |
332 | free_irq(slot->cd_irq, slot); | |
66fd8ad5 AH |
333 | } |
334 | ||
335 | #else | |
336 | ||
c5e027a4 AH |
337 | static inline void sdhci_pci_add_own_cd(struct sdhci_pci_slot *slot) |
338 | { | |
339 | } | |
340 | ||
341 | static inline void sdhci_pci_remove_own_cd(struct sdhci_pci_slot *slot) | |
342 | { | |
343 | } | |
66fd8ad5 AH |
344 | |
345 | #endif | |
346 | ||
0d013bcf AH |
347 | static int mfd_emmc_probe_slot(struct sdhci_pci_slot *slot) |
348 | { | |
66fd8ad5 | 349 | slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE; |
d2a47176 | 350 | slot->host->mmc->caps2 |= MMC_CAP2_BOOTPART_NOACC; |
0d013bcf AH |
351 | return 0; |
352 | } | |
353 | ||
93933508 AH |
354 | static int mfd_sdio_probe_slot(struct sdhci_pci_slot *slot) |
355 | { | |
012e4671 | 356 | slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE; |
93933508 AH |
357 | return 0; |
358 | } | |
359 | ||
f9ee3eab AC |
360 | static const struct sdhci_pci_fixes sdhci_intel_mrst_hc0 = { |
361 | .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT, | |
68077b02 | 362 | .probe_slot = mrst_hc_probe_slot, |
f9ee3eab AC |
363 | }; |
364 | ||
35ac6f08 | 365 | static const struct sdhci_pci_fixes sdhci_intel_mrst_hc1_hc2 = { |
f9ee3eab | 366 | .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT, |
35ac6f08 | 367 | .probe = mrst_hc_probe, |
f9ee3eab AC |
368 | }; |
369 | ||
29229052 XS |
370 | static const struct sdhci_pci_fixes sdhci_intel_mfd_sd = { |
371 | .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, | |
c43fd774 | 372 | .allow_runtime_pm = true, |
77a0122e | 373 | .own_cd_for_runtime_pm = true, |
29229052 XS |
374 | }; |
375 | ||
0d013bcf AH |
376 | static const struct sdhci_pci_fixes sdhci_intel_mfd_sdio = { |
377 | .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, | |
f3c55a7b | 378 | .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON, |
c43fd774 | 379 | .allow_runtime_pm = true, |
93933508 | 380 | .probe_slot = mfd_sdio_probe_slot, |
0d013bcf AH |
381 | }; |
382 | ||
383 | static const struct sdhci_pci_fixes sdhci_intel_mfd_emmc = { | |
29229052 | 384 | .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, |
c43fd774 | 385 | .allow_runtime_pm = true, |
0d013bcf | 386 | .probe_slot = mfd_emmc_probe_slot, |
29229052 XS |
387 | }; |
388 | ||
296e0b03 AS |
389 | static const struct sdhci_pci_fixes sdhci_intel_pch_sdio = { |
390 | .quirks = SDHCI_QUIRK_BROKEN_ADMA, | |
391 | .probe_slot = pch_hc_probe_slot, | |
392 | }; | |
393 | ||
c959a6b0 AH |
394 | enum { |
395 | INTEL_DSM_FNS = 0, | |
51ced59c | 396 | INTEL_DSM_DRV_STRENGTH = 9, |
c959a6b0 AH |
397 | INTEL_DSM_D3_RETUNE = 10, |
398 | }; | |
399 | ||
400 | struct intel_host { | |
401 | u32 dsm_fns; | |
51ced59c | 402 | int drv_strength; |
c959a6b0 AH |
403 | bool d3_retune; |
404 | }; | |
405 | ||
406 | const u8 intel_dsm_uuid[] = { | |
407 | 0xA5, 0x3E, 0xC1, 0xF6, 0xCD, 0x65, 0x1F, 0x46, | |
408 | 0xAB, 0x7A, 0x29, 0xF7, 0xE8, 0xD5, 0xBD, 0x61, | |
409 | }; | |
410 | ||
411 | static int __intel_dsm(struct intel_host *intel_host, struct device *dev, | |
412 | unsigned int fn, u32 *result) | |
413 | { | |
414 | union acpi_object *obj; | |
415 | int err = 0; | |
a72016a4 | 416 | size_t len; |
c959a6b0 AH |
417 | |
418 | obj = acpi_evaluate_dsm(ACPI_HANDLE(dev), intel_dsm_uuid, 0, fn, NULL); | |
419 | if (!obj) | |
420 | return -EOPNOTSUPP; | |
421 | ||
422 | if (obj->type != ACPI_TYPE_BUFFER || obj->buffer.length < 1) { | |
423 | err = -EINVAL; | |
424 | goto out; | |
425 | } | |
426 | ||
a72016a4 AH |
427 | len = min_t(size_t, obj->buffer.length, 4); |
428 | ||
429 | *result = 0; | |
430 | memcpy(result, obj->buffer.pointer, len); | |
c959a6b0 AH |
431 | out: |
432 | ACPI_FREE(obj); | |
433 | ||
434 | return err; | |
435 | } | |
436 | ||
437 | static int intel_dsm(struct intel_host *intel_host, struct device *dev, | |
438 | unsigned int fn, u32 *result) | |
439 | { | |
440 | if (fn > 31 || !(intel_host->dsm_fns & (1 << fn))) | |
441 | return -EOPNOTSUPP; | |
442 | ||
443 | return __intel_dsm(intel_host, dev, fn, result); | |
444 | } | |
445 | ||
446 | static void intel_dsm_init(struct intel_host *intel_host, struct device *dev, | |
447 | struct mmc_host *mmc) | |
448 | { | |
449 | int err; | |
450 | u32 val; | |
451 | ||
452 | err = __intel_dsm(intel_host, dev, INTEL_DSM_FNS, &intel_host->dsm_fns); | |
453 | if (err) { | |
454 | pr_debug("%s: DSM not supported, error %d\n", | |
455 | mmc_hostname(mmc), err); | |
456 | return; | |
457 | } | |
458 | ||
459 | pr_debug("%s: DSM function mask %#x\n", | |
460 | mmc_hostname(mmc), intel_host->dsm_fns); | |
461 | ||
51ced59c AH |
462 | err = intel_dsm(intel_host, dev, INTEL_DSM_DRV_STRENGTH, &val); |
463 | intel_host->drv_strength = err ? 0 : val; | |
464 | ||
c959a6b0 AH |
465 | err = intel_dsm(intel_host, dev, INTEL_DSM_D3_RETUNE, &val); |
466 | intel_host->d3_retune = err ? true : !!val; | |
467 | } | |
468 | ||
c9faff6c AH |
469 | static void sdhci_pci_int_hw_reset(struct sdhci_host *host) |
470 | { | |
471 | u8 reg; | |
472 | ||
473 | reg = sdhci_readb(host, SDHCI_POWER_CONTROL); | |
474 | reg |= 0x10; | |
475 | sdhci_writeb(host, reg, SDHCI_POWER_CONTROL); | |
476 | /* For eMMC, minimum is 1us but give it 9us for good measure */ | |
477 | udelay(9); | |
478 | reg &= ~0x10; | |
479 | sdhci_writeb(host, reg, SDHCI_POWER_CONTROL); | |
480 | /* For eMMC, minimum is 200us but give it 300us for good measure */ | |
481 | usleep_range(300, 1000); | |
482 | } | |
483 | ||
51ced59c AH |
484 | static int intel_select_drive_strength(struct mmc_card *card, |
485 | unsigned int max_dtr, int host_drv, | |
486 | int card_drv, int *drv_type) | |
e1bfad6d | 487 | { |
51ced59c AH |
488 | struct sdhci_host *host = mmc_priv(card->host); |
489 | struct sdhci_pci_slot *slot = sdhci_priv(host); | |
490 | struct intel_host *intel_host = sdhci_pci_priv(slot); | |
e1bfad6d | 491 | |
51ced59c | 492 | return intel_host->drv_strength; |
e1bfad6d AH |
493 | } |
494 | ||
163cbe31 AH |
495 | static int bxt_get_cd(struct mmc_host *mmc) |
496 | { | |
497 | int gpio_cd = mmc_gpio_get_cd(mmc); | |
498 | struct sdhci_host *host = mmc_priv(mmc); | |
499 | unsigned long flags; | |
500 | int ret = 0; | |
501 | ||
502 | if (!gpio_cd) | |
503 | return 0; | |
504 | ||
163cbe31 AH |
505 | spin_lock_irqsave(&host->lock, flags); |
506 | ||
507 | if (host->flags & SDHCI_DEVICE_DEAD) | |
508 | goto out; | |
509 | ||
510 | ret = !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT); | |
511 | out: | |
512 | spin_unlock_irqrestore(&host->lock, flags); | |
513 | ||
163cbe31 AH |
514 | return ret; |
515 | } | |
516 | ||
48d685a2 AH |
517 | #define SDHCI_INTEL_PWR_TIMEOUT_CNT 20 |
518 | #define SDHCI_INTEL_PWR_TIMEOUT_UDELAY 100 | |
519 | ||
520 | static void sdhci_intel_set_power(struct sdhci_host *host, unsigned char mode, | |
521 | unsigned short vdd) | |
522 | { | |
523 | int cntr; | |
524 | u8 reg; | |
525 | ||
526 | sdhci_set_power(host, mode, vdd); | |
527 | ||
528 | if (mode == MMC_POWER_OFF) | |
529 | return; | |
530 | ||
531 | /* | |
532 | * Bus power might not enable after D3 -> D0 transition due to the | |
533 | * present state not yet having propagated. Retry for up to 2ms. | |
534 | */ | |
535 | for (cntr = 0; cntr < SDHCI_INTEL_PWR_TIMEOUT_CNT; cntr++) { | |
536 | reg = sdhci_readb(host, SDHCI_POWER_CONTROL); | |
537 | if (reg & SDHCI_POWER_ON) | |
538 | break; | |
539 | udelay(SDHCI_INTEL_PWR_TIMEOUT_UDELAY); | |
540 | reg |= SDHCI_POWER_ON; | |
541 | sdhci_writeb(host, reg, SDHCI_POWER_CONTROL); | |
542 | } | |
543 | } | |
544 | ||
bc55dcd8 AH |
545 | #define INTEL_HS400_ES_REG 0x78 |
546 | #define INTEL_HS400_ES_BIT BIT(0) | |
547 | ||
548 | static void intel_hs400_enhanced_strobe(struct mmc_host *mmc, | |
549 | struct mmc_ios *ios) | |
550 | { | |
551 | struct sdhci_host *host = mmc_priv(mmc); | |
552 | u32 val; | |
553 | ||
554 | val = sdhci_readl(host, INTEL_HS400_ES_REG); | |
555 | if (ios->enhanced_strobe) | |
556 | val |= INTEL_HS400_ES_BIT; | |
557 | else | |
558 | val &= ~INTEL_HS400_ES_BIT; | |
559 | sdhci_writel(host, val, INTEL_HS400_ES_REG); | |
560 | } | |
561 | ||
48d685a2 AH |
562 | static const struct sdhci_ops sdhci_intel_byt_ops = { |
563 | .set_clock = sdhci_set_clock, | |
564 | .set_power = sdhci_intel_set_power, | |
565 | .enable_dma = sdhci_pci_enable_dma, | |
566 | .set_bus_width = sdhci_pci_set_bus_width, | |
567 | .reset = sdhci_reset, | |
568 | .set_uhs_signaling = sdhci_set_uhs_signaling, | |
569 | .hw_reset = sdhci_pci_hw_reset, | |
570 | }; | |
571 | ||
c959a6b0 AH |
572 | static void byt_read_dsm(struct sdhci_pci_slot *slot) |
573 | { | |
574 | struct intel_host *intel_host = sdhci_pci_priv(slot); | |
575 | struct device *dev = &slot->chip->pdev->dev; | |
576 | struct mmc_host *mmc = slot->host->mmc; | |
577 | ||
578 | intel_dsm_init(intel_host, dev, mmc); | |
579 | slot->chip->rpm_retune = intel_host->d3_retune; | |
580 | } | |
581 | ||
728ef3d1 AH |
582 | static int byt_emmc_probe_slot(struct sdhci_pci_slot *slot) |
583 | { | |
c959a6b0 | 584 | byt_read_dsm(slot); |
c9faff6c | 585 | slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE | |
6aab23a8 | 586 | MMC_CAP_HW_RESET | MMC_CAP_1_8V_DDR | |
32828857 | 587 | MMC_CAP_CMD_DURING_TFR | |
6aab23a8 | 588 | MMC_CAP_WAIT_WHILE_BUSY; |
c9faff6c | 589 | slot->hw_reset = sdhci_pci_int_hw_reset; |
a06586b6 AH |
590 | if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BSW_EMMC) |
591 | slot->host->timeout_clk = 1000; /* 1000 kHz i.e. 1 MHz */ | |
51ced59c AH |
592 | slot->host->mmc_host_ops.select_drive_strength = |
593 | intel_select_drive_strength; | |
728ef3d1 AH |
594 | return 0; |
595 | } | |
596 | ||
bc55dcd8 AH |
597 | static int glk_emmc_probe_slot(struct sdhci_pci_slot *slot) |
598 | { | |
599 | int ret = byt_emmc_probe_slot(slot); | |
600 | ||
601 | if (slot->chip->pdev->device != PCI_DEVICE_ID_INTEL_GLK_EMMC) { | |
602 | slot->host->mmc->caps2 |= MMC_CAP2_HS400_ES, | |
603 | slot->host->mmc_host_ops.hs400_enhanced_strobe = | |
604 | intel_hs400_enhanced_strobe; | |
605 | } | |
606 | ||
607 | return ret; | |
608 | } | |
609 | ||
3f23df72 ZB |
610 | #ifdef CONFIG_ACPI |
611 | static int ni_set_max_freq(struct sdhci_pci_slot *slot) | |
612 | { | |
613 | acpi_status status; | |
614 | unsigned long long max_freq; | |
615 | ||
616 | status = acpi_evaluate_integer(ACPI_HANDLE(&slot->chip->pdev->dev), | |
617 | "MXFQ", NULL, &max_freq); | |
618 | if (ACPI_FAILURE(status)) { | |
619 | dev_err(&slot->chip->pdev->dev, | |
620 | "MXFQ not found in acpi table\n"); | |
621 | return -EINVAL; | |
622 | } | |
623 | ||
624 | slot->host->mmc->f_max = max_freq * 1000000; | |
625 | ||
626 | return 0; | |
627 | } | |
628 | #else | |
629 | static inline int ni_set_max_freq(struct sdhci_pci_slot *slot) | |
630 | { | |
631 | return 0; | |
632 | } | |
633 | #endif | |
634 | ||
42b06496 ZB |
635 | static int ni_byt_sdio_probe_slot(struct sdhci_pci_slot *slot) |
636 | { | |
3f23df72 ZB |
637 | int err; |
638 | ||
c959a6b0 AH |
639 | byt_read_dsm(slot); |
640 | ||
3f23df72 ZB |
641 | err = ni_set_max_freq(slot); |
642 | if (err) | |
643 | return err; | |
644 | ||
42b06496 ZB |
645 | slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE | |
646 | MMC_CAP_WAIT_WHILE_BUSY; | |
647 | return 0; | |
648 | } | |
649 | ||
728ef3d1 AH |
650 | static int byt_sdio_probe_slot(struct sdhci_pci_slot *slot) |
651 | { | |
c959a6b0 | 652 | byt_read_dsm(slot); |
6aab23a8 | 653 | slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE | |
6aab23a8 | 654 | MMC_CAP_WAIT_WHILE_BUSY; |
728ef3d1 AH |
655 | return 0; |
656 | } | |
657 | ||
ff59c520 AH |
658 | static int byt_sd_probe_slot(struct sdhci_pci_slot *slot) |
659 | { | |
c959a6b0 | 660 | byt_read_dsm(slot); |
c2c49a2e AS |
661 | slot->host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY | |
662 | MMC_CAP_AGGRESSIVE_PM; | |
ff59c520 AH |
663 | slot->cd_idx = 0; |
664 | slot->cd_override_level = true; | |
163cbe31 | 665 | if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BXT_SD || |
01d6b2a4 | 666 | slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BXTM_SD || |
2d1956d0 | 667 | slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_APL_SD || |
c2c49a2e | 668 | slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_GLK_SD) |
163cbe31 AH |
669 | slot->host->mmc_host_ops.get_cd = bxt_get_cd; |
670 | ||
ff59c520 AH |
671 | return 0; |
672 | } | |
673 | ||
728ef3d1 AH |
674 | static const struct sdhci_pci_fixes sdhci_intel_byt_emmc = { |
675 | .allow_runtime_pm = true, | |
676 | .probe_slot = byt_emmc_probe_slot, | |
db6e8cdf | 677 | .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, |
e58e4a0d | 678 | .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | |
b69587e2 | 679 | SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 | |
e58e4a0d | 680 | SDHCI_QUIRK2_STOP_WITH_TC, |
fee686b7 | 681 | .ops = &sdhci_intel_byt_ops, |
c959a6b0 | 682 | .priv_size = sizeof(struct intel_host), |
728ef3d1 AH |
683 | }; |
684 | ||
bc55dcd8 AH |
685 | static const struct sdhci_pci_fixes sdhci_intel_glk_emmc = { |
686 | .allow_runtime_pm = true, | |
687 | .probe_slot = glk_emmc_probe_slot, | |
688 | .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, | |
689 | .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | | |
690 | SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 | | |
691 | SDHCI_QUIRK2_STOP_WITH_TC, | |
692 | .ops = &sdhci_intel_byt_ops, | |
693 | .priv_size = sizeof(struct intel_host), | |
694 | }; | |
695 | ||
42b06496 ZB |
696 | static const struct sdhci_pci_fixes sdhci_ni_byt_sdio = { |
697 | .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, | |
698 | .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON | | |
699 | SDHCI_QUIRK2_PRESET_VALUE_BROKEN, | |
700 | .allow_runtime_pm = true, | |
701 | .probe_slot = ni_byt_sdio_probe_slot, | |
702 | .ops = &sdhci_intel_byt_ops, | |
c959a6b0 | 703 | .priv_size = sizeof(struct intel_host), |
42b06496 ZB |
704 | }; |
705 | ||
728ef3d1 | 706 | static const struct sdhci_pci_fixes sdhci_intel_byt_sdio = { |
db6e8cdf | 707 | .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, |
b7574bad GY |
708 | .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON | |
709 | SDHCI_QUIRK2_PRESET_VALUE_BROKEN, | |
728ef3d1 AH |
710 | .allow_runtime_pm = true, |
711 | .probe_slot = byt_sdio_probe_slot, | |
fee686b7 | 712 | .ops = &sdhci_intel_byt_ops, |
c959a6b0 | 713 | .priv_size = sizeof(struct intel_host), |
728ef3d1 AH |
714 | }; |
715 | ||
716 | static const struct sdhci_pci_fixes sdhci_intel_byt_sd = { | |
db6e8cdf | 717 | .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, |
b7574bad | 718 | .quirks2 = SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON | |
e58e4a0d AH |
719 | SDHCI_QUIRK2_PRESET_VALUE_BROKEN | |
720 | SDHCI_QUIRK2_STOP_WITH_TC, | |
7396e318 | 721 | .allow_runtime_pm = true, |
77a0122e | 722 | .own_cd_for_runtime_pm = true, |
ff59c520 | 723 | .probe_slot = byt_sd_probe_slot, |
fee686b7 | 724 | .ops = &sdhci_intel_byt_ops, |
c959a6b0 | 725 | .priv_size = sizeof(struct intel_host), |
728ef3d1 AH |
726 | }; |
727 | ||
8776a165 | 728 | /* Define Host controllers for Intel Merrifield platform */ |
1f64cec2 AS |
729 | #define INTEL_MRFLD_EMMC_0 0 |
730 | #define INTEL_MRFLD_EMMC_1 1 | |
4674b6c8 | 731 | #define INTEL_MRFLD_SD 2 |
d5565577 | 732 | #define INTEL_MRFLD_SDIO 3 |
8776a165 | 733 | |
1f64cec2 | 734 | static int intel_mrfld_mmc_probe_slot(struct sdhci_pci_slot *slot) |
8776a165 | 735 | { |
2e57bbe2 AS |
736 | unsigned int func = PCI_FUNC(slot->chip->pdev->devfn); |
737 | ||
738 | switch (func) { | |
739 | case INTEL_MRFLD_EMMC_0: | |
740 | case INTEL_MRFLD_EMMC_1: | |
741 | slot->host->mmc->caps |= MMC_CAP_NONREMOVABLE | | |
742 | MMC_CAP_8_BIT_DATA | | |
743 | MMC_CAP_1_8V_DDR; | |
744 | break; | |
4674b6c8 AS |
745 | case INTEL_MRFLD_SD: |
746 | slot->host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V; | |
747 | break; | |
d5565577 AS |
748 | case INTEL_MRFLD_SDIO: |
749 | slot->host->mmc->caps |= MMC_CAP_NONREMOVABLE | | |
750 | MMC_CAP_POWER_OFF_CARD; | |
751 | break; | |
2e57bbe2 | 752 | default: |
8776a165 | 753 | return -ENODEV; |
2e57bbe2 | 754 | } |
8776a165 DC |
755 | return 0; |
756 | } | |
757 | ||
1f64cec2 | 758 | static const struct sdhci_pci_fixes sdhci_intel_mrfld_mmc = { |
8776a165 | 759 | .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, |
b7574bad GY |
760 | .quirks2 = SDHCI_QUIRK2_BROKEN_HS200 | |
761 | SDHCI_QUIRK2_PRESET_VALUE_BROKEN, | |
f1b55a55 | 762 | .allow_runtime_pm = true, |
1f64cec2 | 763 | .probe_slot = intel_mrfld_mmc_probe_slot, |
8776a165 DC |
764 | }; |
765 | ||
26daa1ed JL |
766 | /* O2Micro extra registers */ |
767 | #define O2_SD_LOCK_WP 0xD3 | |
768 | #define O2_SD_MULTI_VCC3V 0xEE | |
769 | #define O2_SD_CLKREQ 0xEC | |
770 | #define O2_SD_CAPS 0xE0 | |
771 | #define O2_SD_ADMA1 0xE2 | |
772 | #define O2_SD_ADMA2 0xE7 | |
773 | #define O2_SD_INF_MOD 0xF1 | |
774 | ||
45211e21 PO |
775 | static int jmicron_pmos(struct sdhci_pci_chip *chip, int on) |
776 | { | |
777 | u8 scratch; | |
778 | int ret; | |
779 | ||
780 | ret = pci_read_config_byte(chip->pdev, 0xAE, &scratch); | |
781 | if (ret) | |
782 | return ret; | |
783 | ||
784 | /* | |
785 | * Turn PMOS on [bit 0], set over current detection to 2.4 V | |
786 | * [bit 1:2] and enable over current debouncing [bit 6]. | |
787 | */ | |
788 | if (on) | |
789 | scratch |= 0x47; | |
790 | else | |
791 | scratch &= ~0x47; | |
792 | ||
7582041f | 793 | return pci_write_config_byte(chip->pdev, 0xAE, scratch); |
45211e21 PO |
794 | } |
795 | ||
796 | static int jmicron_probe(struct sdhci_pci_chip *chip) | |
797 | { | |
798 | int ret; | |
8f230f45 | 799 | u16 mmcdev = 0; |
45211e21 | 800 | |
93fc48c7 PO |
801 | if (chip->pdev->revision == 0) { |
802 | chip->quirks |= SDHCI_QUIRK_32BIT_DMA_ADDR | | |
803 | SDHCI_QUIRK_32BIT_DMA_SIZE | | |
2134a922 | 804 | SDHCI_QUIRK_32BIT_ADMA_SIZE | |
4a3cba32 | 805 | SDHCI_QUIRK_RESET_AFTER_REQUEST | |
86a6a874 | 806 | SDHCI_QUIRK_BROKEN_SMALL_PIO; |
93fc48c7 PO |
807 | } |
808 | ||
4489428a PO |
809 | /* |
810 | * JMicron chips can have two interfaces to the same hardware | |
811 | * in order to work around limitations in Microsoft's driver. | |
812 | * We need to make sure we only bind to one of them. | |
813 | * | |
814 | * This code assumes two things: | |
815 | * | |
816 | * 1. The PCI code adds subfunctions in order. | |
817 | * | |
818 | * 2. The MMC interface has a lower subfunction number | |
819 | * than the SD interface. | |
820 | */ | |
8f230f45 TI |
821 | if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_SD) |
822 | mmcdev = PCI_DEVICE_ID_JMICRON_JMB38X_MMC; | |
823 | else if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD) | |
824 | mmcdev = PCI_DEVICE_ID_JMICRON_JMB388_ESD; | |
825 | ||
826 | if (mmcdev) { | |
4489428a PO |
827 | struct pci_dev *sd_dev; |
828 | ||
829 | sd_dev = NULL; | |
830 | while ((sd_dev = pci_get_device(PCI_VENDOR_ID_JMICRON, | |
8f230f45 | 831 | mmcdev, sd_dev)) != NULL) { |
4489428a PO |
832 | if ((PCI_SLOT(chip->pdev->devfn) == |
833 | PCI_SLOT(sd_dev->devfn)) && | |
834 | (chip->pdev->bus == sd_dev->bus)) | |
835 | break; | |
836 | } | |
837 | ||
838 | if (sd_dev) { | |
839 | pci_dev_put(sd_dev); | |
840 | dev_info(&chip->pdev->dev, "Refusing to bind to " | |
841 | "secondary interface.\n"); | |
842 | return -ENODEV; | |
843 | } | |
844 | } | |
845 | ||
45211e21 PO |
846 | /* |
847 | * JMicron chips need a bit of a nudge to enable the power | |
848 | * output pins. | |
849 | */ | |
850 | ret = jmicron_pmos(chip, 1); | |
851 | if (ret) { | |
852 | dev_err(&chip->pdev->dev, "Failure enabling card power\n"); | |
853 | return ret; | |
854 | } | |
855 | ||
82b0e23a TI |
856 | /* quirk for unsable RO-detection on JM388 chips */ |
857 | if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD || | |
858 | chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) | |
859 | chip->quirks |= SDHCI_QUIRK_UNSTABLE_RO_DETECT; | |
860 | ||
45211e21 PO |
861 | return 0; |
862 | } | |
863 | ||
4489428a PO |
864 | static void jmicron_enable_mmc(struct sdhci_host *host, int on) |
865 | { | |
866 | u8 scratch; | |
867 | ||
868 | scratch = readb(host->ioaddr + 0xC0); | |
869 | ||
870 | if (on) | |
871 | scratch |= 0x01; | |
872 | else | |
873 | scratch &= ~0x01; | |
874 | ||
875 | writeb(scratch, host->ioaddr + 0xC0); | |
876 | } | |
877 | ||
878 | static int jmicron_probe_slot(struct sdhci_pci_slot *slot) | |
879 | { | |
2134a922 PO |
880 | if (slot->chip->pdev->revision == 0) { |
881 | u16 version; | |
882 | ||
883 | version = readl(slot->host->ioaddr + SDHCI_HOST_VERSION); | |
884 | version = (version & SDHCI_VENDOR_VER_MASK) >> | |
885 | SDHCI_VENDOR_VER_SHIFT; | |
886 | ||
887 | /* | |
888 | * Older versions of the chip have lots of nasty glitches | |
889 | * in the ADMA engine. It's best just to avoid it | |
890 | * completely. | |
891 | */ | |
892 | if (version < 0xAC) | |
893 | slot->host->quirks |= SDHCI_QUIRK_BROKEN_ADMA; | |
894 | } | |
895 | ||
8f230f45 TI |
896 | /* JM388 MMC doesn't support 1.8V while SD supports it */ |
897 | if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) { | |
898 | slot->host->ocr_avail_sd = MMC_VDD_32_33 | MMC_VDD_33_34 | | |
899 | MMC_VDD_29_30 | MMC_VDD_30_31 | | |
900 | MMC_VDD_165_195; /* allow 1.8V */ | |
901 | slot->host->ocr_avail_mmc = MMC_VDD_32_33 | MMC_VDD_33_34 | | |
902 | MMC_VDD_29_30 | MMC_VDD_30_31; /* no 1.8V for MMC */ | |
903 | } | |
904 | ||
4489428a PO |
905 | /* |
906 | * The secondary interface requires a bit set to get the | |
907 | * interrupts. | |
908 | */ | |
8f230f45 TI |
909 | if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || |
910 | slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) | |
4489428a PO |
911 | jmicron_enable_mmc(slot->host, 1); |
912 | ||
d75c1084 TI |
913 | slot->host->mmc->caps |= MMC_CAP_BUS_WIDTH_TEST; |
914 | ||
4489428a PO |
915 | return 0; |
916 | } | |
917 | ||
1e72859e | 918 | static void jmicron_remove_slot(struct sdhci_pci_slot *slot, int dead) |
4489428a | 919 | { |
1e72859e PO |
920 | if (dead) |
921 | return; | |
922 | ||
8f230f45 TI |
923 | if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || |
924 | slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) | |
4489428a PO |
925 | jmicron_enable_mmc(slot->host, 0); |
926 | } | |
927 | ||
b7813f0f | 928 | #ifdef CONFIG_PM_SLEEP |
29495aa0 | 929 | static int jmicron_suspend(struct sdhci_pci_chip *chip) |
4489428a | 930 | { |
30cf2803 AH |
931 | int i, ret; |
932 | ||
933 | ret = __sdhci_pci_suspend_host(chip); | |
934 | if (ret) | |
935 | return ret; | |
4489428a | 936 | |
8f230f45 TI |
937 | if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || |
938 | chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) { | |
b177bc91 | 939 | for (i = 0; i < chip->num_slots; i++) |
4489428a PO |
940 | jmicron_enable_mmc(chip->slots[i]->host, 0); |
941 | } | |
942 | ||
30cf2803 AH |
943 | sdhci_pci_init_wakeup(chip); |
944 | ||
4489428a PO |
945 | return 0; |
946 | } | |
947 | ||
45211e21 PO |
948 | static int jmicron_resume(struct sdhci_pci_chip *chip) |
949 | { | |
4489428a PO |
950 | int ret, i; |
951 | ||
8f230f45 TI |
952 | if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || |
953 | chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) { | |
b177bc91 | 954 | for (i = 0; i < chip->num_slots; i++) |
4489428a PO |
955 | jmicron_enable_mmc(chip->slots[i]->host, 1); |
956 | } | |
45211e21 PO |
957 | |
958 | ret = jmicron_pmos(chip, 1); | |
959 | if (ret) { | |
960 | dev_err(&chip->pdev->dev, "Failure enabling card power\n"); | |
961 | return ret; | |
962 | } | |
963 | ||
30cf2803 | 964 | return sdhci_pci_resume_host(chip); |
45211e21 | 965 | } |
b7813f0f | 966 | #endif |
45211e21 | 967 | |
26daa1ed | 968 | static const struct sdhci_pci_fixes sdhci_o2 = { |
01acf691 AL |
969 | .probe = sdhci_pci_o2_probe, |
970 | .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, | |
143b648d | 971 | .quirks2 = SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD, |
01acf691 | 972 | .probe_slot = sdhci_pci_o2_probe_slot, |
b7813f0f | 973 | #ifdef CONFIG_PM_SLEEP |
01acf691 | 974 | .resume = sdhci_pci_o2_resume, |
b7813f0f | 975 | #endif |
26daa1ed JL |
976 | }; |
977 | ||
22606405 | 978 | static const struct sdhci_pci_fixes sdhci_jmicron = { |
45211e21 PO |
979 | .probe = jmicron_probe, |
980 | ||
4489428a PO |
981 | .probe_slot = jmicron_probe_slot, |
982 | .remove_slot = jmicron_remove_slot, | |
983 | ||
b7813f0f | 984 | #ifdef CONFIG_PM_SLEEP |
4489428a | 985 | .suspend = jmicron_suspend, |
45211e21 | 986 | .resume = jmicron_resume, |
b7813f0f | 987 | #endif |
22606405 PO |
988 | }; |
989 | ||
a7a6186c NP |
990 | /* SysKonnect CardBus2SDIO extra registers */ |
991 | #define SYSKT_CTRL 0x200 | |
992 | #define SYSKT_RDFIFO_STAT 0x204 | |
993 | #define SYSKT_WRFIFO_STAT 0x208 | |
994 | #define SYSKT_POWER_DATA 0x20c | |
995 | #define SYSKT_POWER_330 0xef | |
996 | #define SYSKT_POWER_300 0xf8 | |
997 | #define SYSKT_POWER_184 0xcc | |
998 | #define SYSKT_POWER_CMD 0x20d | |
999 | #define SYSKT_POWER_START (1 << 7) | |
1000 | #define SYSKT_POWER_STATUS 0x20e | |
1001 | #define SYSKT_POWER_STATUS_OK (1 << 0) | |
1002 | #define SYSKT_BOARD_REV 0x210 | |
1003 | #define SYSKT_CHIP_REV 0x211 | |
1004 | #define SYSKT_CONF_DATA 0x212 | |
1005 | #define SYSKT_CONF_DATA_1V8 (1 << 2) | |
1006 | #define SYSKT_CONF_DATA_2V5 (1 << 1) | |
1007 | #define SYSKT_CONF_DATA_3V3 (1 << 0) | |
1008 | ||
1009 | static int syskt_probe(struct sdhci_pci_chip *chip) | |
1010 | { | |
1011 | if ((chip->pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) { | |
1012 | chip->pdev->class &= ~0x0000FF; | |
1013 | chip->pdev->class |= PCI_SDHCI_IFDMA; | |
1014 | } | |
1015 | return 0; | |
1016 | } | |
1017 | ||
1018 | static int syskt_probe_slot(struct sdhci_pci_slot *slot) | |
1019 | { | |
1020 | int tm, ps; | |
1021 | ||
1022 | u8 board_rev = readb(slot->host->ioaddr + SYSKT_BOARD_REV); | |
1023 | u8 chip_rev = readb(slot->host->ioaddr + SYSKT_CHIP_REV); | |
1024 | dev_info(&slot->chip->pdev->dev, "SysKonnect CardBus2SDIO, " | |
1025 | "board rev %d.%d, chip rev %d.%d\n", | |
1026 | board_rev >> 4, board_rev & 0xf, | |
1027 | chip_rev >> 4, chip_rev & 0xf); | |
1028 | if (chip_rev >= 0x20) | |
1029 | slot->host->quirks |= SDHCI_QUIRK_FORCE_DMA; | |
1030 | ||
1031 | writeb(SYSKT_POWER_330, slot->host->ioaddr + SYSKT_POWER_DATA); | |
1032 | writeb(SYSKT_POWER_START, slot->host->ioaddr + SYSKT_POWER_CMD); | |
1033 | udelay(50); | |
1034 | tm = 10; /* Wait max 1 ms */ | |
1035 | do { | |
1036 | ps = readw(slot->host->ioaddr + SYSKT_POWER_STATUS); | |
1037 | if (ps & SYSKT_POWER_STATUS_OK) | |
1038 | break; | |
1039 | udelay(100); | |
1040 | } while (--tm); | |
1041 | if (!tm) { | |
1042 | dev_err(&slot->chip->pdev->dev, | |
1043 | "power regulator never stabilized"); | |
1044 | writeb(0, slot->host->ioaddr + SYSKT_POWER_CMD); | |
1045 | return -ENODEV; | |
1046 | } | |
1047 | ||
1048 | return 0; | |
1049 | } | |
1050 | ||
1051 | static const struct sdhci_pci_fixes sdhci_syskt = { | |
1052 | .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER, | |
1053 | .probe = syskt_probe, | |
1054 | .probe_slot = syskt_probe_slot, | |
1055 | }; | |
1056 | ||
557b0697 HW |
1057 | static int via_probe(struct sdhci_pci_chip *chip) |
1058 | { | |
1059 | if (chip->pdev->revision == 0x10) | |
1060 | chip->quirks |= SDHCI_QUIRK_DELAY_AFTER_POWER; | |
1061 | ||
1062 | return 0; | |
1063 | } | |
1064 | ||
1065 | static const struct sdhci_pci_fixes sdhci_via = { | |
1066 | .probe = via_probe, | |
1067 | }; | |
1068 | ||
9107ebbf MC |
1069 | static int rtsx_probe_slot(struct sdhci_pci_slot *slot) |
1070 | { | |
1071 | slot->host->mmc->caps2 |= MMC_CAP2_HS200; | |
1072 | return 0; | |
1073 | } | |
1074 | ||
1075 | static const struct sdhci_pci_fixes sdhci_rtsx = { | |
1076 | .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | | |
e30b978f | 1077 | SDHCI_QUIRK2_BROKEN_64_BIT_DMA | |
9107ebbf MC |
1078 | SDHCI_QUIRK2_BROKEN_DDR50, |
1079 | .probe_slot = rtsx_probe_slot, | |
1080 | }; | |
1081 | ||
b5e97d6e VW |
1082 | /*AMD chipset generation*/ |
1083 | enum amd_chipset_gen { | |
1084 | AMD_CHIPSET_BEFORE_ML, | |
1085 | AMD_CHIPSET_CZ, | |
1086 | AMD_CHIPSET_NL, | |
1087 | AMD_CHIPSET_UNKNOWN, | |
1088 | }; | |
1089 | ||
c31165d7 SS |
1090 | /* AMD registers */ |
1091 | #define AMD_SD_AUTO_PATTERN 0xB8 | |
1092 | #define AMD_MSLEEP_DURATION 4 | |
1093 | #define AMD_SD_MISC_CONTROL 0xD0 | |
1094 | #define AMD_MAX_TUNE_VALUE 0x0B | |
1095 | #define AMD_AUTO_TUNE_SEL 0x10800 | |
1096 | #define AMD_FIFO_PTR 0x30 | |
1097 | #define AMD_BIT_MASK 0x1F | |
1098 | ||
1099 | static void amd_tuning_reset(struct sdhci_host *host) | |
1100 | { | |
1101 | unsigned int val; | |
1102 | ||
1103 | val = sdhci_readw(host, SDHCI_HOST_CONTROL2); | |
1104 | val |= SDHCI_CTRL_PRESET_VAL_ENABLE | SDHCI_CTRL_EXEC_TUNING; | |
1105 | sdhci_writew(host, val, SDHCI_HOST_CONTROL2); | |
1106 | ||
1107 | val = sdhci_readw(host, SDHCI_HOST_CONTROL2); | |
1108 | val &= ~SDHCI_CTRL_EXEC_TUNING; | |
1109 | sdhci_writew(host, val, SDHCI_HOST_CONTROL2); | |
1110 | } | |
1111 | ||
1112 | static void amd_config_tuning_phase(struct pci_dev *pdev, u8 phase) | |
1113 | { | |
1114 | unsigned int val; | |
1115 | ||
1116 | pci_read_config_dword(pdev, AMD_SD_AUTO_PATTERN, &val); | |
1117 | val &= ~AMD_BIT_MASK; | |
1118 | val |= (AMD_AUTO_TUNE_SEL | (phase << 1)); | |
1119 | pci_write_config_dword(pdev, AMD_SD_AUTO_PATTERN, val); | |
1120 | } | |
1121 | ||
1122 | static void amd_enable_manual_tuning(struct pci_dev *pdev) | |
1123 | { | |
1124 | unsigned int val; | |
1125 | ||
1126 | pci_read_config_dword(pdev, AMD_SD_MISC_CONTROL, &val); | |
1127 | val |= AMD_FIFO_PTR; | |
1128 | pci_write_config_dword(pdev, AMD_SD_MISC_CONTROL, val); | |
1129 | } | |
1130 | ||
1131 | static int amd_execute_tuning(struct sdhci_host *host, u32 opcode) | |
1132 | { | |
1133 | struct sdhci_pci_slot *slot = sdhci_priv(host); | |
1134 | struct pci_dev *pdev = slot->chip->pdev; | |
1135 | u8 valid_win = 0; | |
1136 | u8 valid_win_max = 0; | |
1137 | u8 valid_win_end = 0; | |
1138 | u8 ctrl, tune_around; | |
1139 | ||
1140 | amd_tuning_reset(host); | |
1141 | ||
1142 | for (tune_around = 0; tune_around < 12; tune_around++) { | |
1143 | amd_config_tuning_phase(pdev, tune_around); | |
1144 | ||
1145 | if (mmc_send_tuning(host->mmc, opcode, NULL)) { | |
1146 | valid_win = 0; | |
1147 | msleep(AMD_MSLEEP_DURATION); | |
1148 | ctrl = SDHCI_RESET_CMD | SDHCI_RESET_DATA; | |
1149 | sdhci_writeb(host, ctrl, SDHCI_SOFTWARE_RESET); | |
1150 | } else if (++valid_win > valid_win_max) { | |
1151 | valid_win_max = valid_win; | |
1152 | valid_win_end = tune_around; | |
1153 | } | |
1154 | } | |
1155 | ||
1156 | if (!valid_win_max) { | |
1157 | dev_err(&pdev->dev, "no tuning point found\n"); | |
1158 | return -EIO; | |
1159 | } | |
1160 | ||
1161 | amd_config_tuning_phase(pdev, valid_win_end - valid_win_max / 2); | |
1162 | ||
1163 | amd_enable_manual_tuning(pdev); | |
1164 | ||
1165 | host->mmc->retune_period = 0; | |
1166 | ||
1167 | return 0; | |
1168 | } | |
1169 | ||
d44f88da VW |
1170 | static int amd_probe(struct sdhci_pci_chip *chip) |
1171 | { | |
1172 | struct pci_dev *smbus_dev; | |
b5e97d6e | 1173 | enum amd_chipset_gen gen; |
d44f88da VW |
1174 | |
1175 | smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD, | |
1176 | PCI_DEVICE_ID_AMD_HUDSON2_SMBUS, NULL); | |
b5e97d6e VW |
1177 | if (smbus_dev) { |
1178 | gen = AMD_CHIPSET_BEFORE_ML; | |
1179 | } else { | |
1180 | smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD, | |
1181 | PCI_DEVICE_ID_AMD_KERNCZ_SMBUS, NULL); | |
1182 | if (smbus_dev) { | |
1183 | if (smbus_dev->revision < 0x51) | |
1184 | gen = AMD_CHIPSET_CZ; | |
1185 | else | |
1186 | gen = AMD_CHIPSET_NL; | |
1187 | } else { | |
1188 | gen = AMD_CHIPSET_UNKNOWN; | |
1189 | } | |
1190 | } | |
d44f88da | 1191 | |
c31165d7 | 1192 | if (gen == AMD_CHIPSET_BEFORE_ML || gen == AMD_CHIPSET_CZ) |
d44f88da VW |
1193 | chip->quirks2 |= SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD; |
1194 | ||
1195 | return 0; | |
1196 | } | |
1197 | ||
c31165d7 SS |
1198 | static const struct sdhci_ops amd_sdhci_pci_ops = { |
1199 | .set_clock = sdhci_set_clock, | |
1200 | .enable_dma = sdhci_pci_enable_dma, | |
1201 | .set_bus_width = sdhci_pci_set_bus_width, | |
1202 | .reset = sdhci_reset, | |
1203 | .set_uhs_signaling = sdhci_set_uhs_signaling, | |
1204 | .platform_execute_tuning = amd_execute_tuning, | |
1205 | }; | |
1206 | ||
d44f88da VW |
1207 | static const struct sdhci_pci_fixes sdhci_amd = { |
1208 | .probe = amd_probe, | |
c31165d7 | 1209 | .ops = &amd_sdhci_pci_ops, |
d44f88da VW |
1210 | }; |
1211 | ||
9647f84d | 1212 | static const struct pci_device_id pci_ids[] = { |
c949c907 MK |
1213 | SDHCI_PCI_DEVICE(RICOH, R5C822, ricoh), |
1214 | SDHCI_PCI_DEVICE(RICOH, R5C843, ricoh_mmc), | |
1215 | SDHCI_PCI_DEVICE(RICOH, R5CE822, ricoh_mmc), | |
1216 | SDHCI_PCI_DEVICE(RICOH, R5CE823, ricoh_mmc), | |
1217 | SDHCI_PCI_DEVICE(ENE, CB712_SD, ene_712), | |
1218 | SDHCI_PCI_DEVICE(ENE, CB712_SD_2, ene_712), | |
1219 | SDHCI_PCI_DEVICE(ENE, CB714_SD, ene_714), | |
1220 | SDHCI_PCI_DEVICE(ENE, CB714_SD_2, ene_714), | |
1221 | SDHCI_PCI_DEVICE(MARVELL, 88ALP01_SD, cafe), | |
1222 | SDHCI_PCI_DEVICE(JMICRON, JMB38X_SD, jmicron), | |
1223 | SDHCI_PCI_DEVICE(JMICRON, JMB38X_MMC, jmicron), | |
1224 | SDHCI_PCI_DEVICE(JMICRON, JMB388_SD, jmicron), | |
1225 | SDHCI_PCI_DEVICE(JMICRON, JMB388_ESD, jmicron), | |
1226 | SDHCI_PCI_DEVICE(SYSKONNECT, 8000, syskt), | |
1227 | SDHCI_PCI_DEVICE(VIA, 95D0, via), | |
1228 | SDHCI_PCI_DEVICE(REALTEK, 5250, rtsx), | |
1229 | SDHCI_PCI_DEVICE(INTEL, QRK_SD, intel_qrk), | |
1230 | SDHCI_PCI_DEVICE(INTEL, MRST_SD0, intel_mrst_hc0), | |
1231 | SDHCI_PCI_DEVICE(INTEL, MRST_SD1, intel_mrst_hc1_hc2), | |
1232 | SDHCI_PCI_DEVICE(INTEL, MRST_SD2, intel_mrst_hc1_hc2), | |
1233 | SDHCI_PCI_DEVICE(INTEL, MFD_SD, intel_mfd_sd), | |
1234 | SDHCI_PCI_DEVICE(INTEL, MFD_SDIO1, intel_mfd_sdio), | |
1235 | SDHCI_PCI_DEVICE(INTEL, MFD_SDIO2, intel_mfd_sdio), | |
1236 | SDHCI_PCI_DEVICE(INTEL, MFD_EMMC0, intel_mfd_emmc), | |
1237 | SDHCI_PCI_DEVICE(INTEL, MFD_EMMC1, intel_mfd_emmc), | |
1238 | SDHCI_PCI_DEVICE(INTEL, PCH_SDIO0, intel_pch_sdio), | |
1239 | SDHCI_PCI_DEVICE(INTEL, PCH_SDIO1, intel_pch_sdio), | |
1240 | SDHCI_PCI_DEVICE(INTEL, BYT_EMMC, intel_byt_emmc), | |
1241 | SDHCI_PCI_SUBDEVICE(INTEL, BYT_SDIO, NI, 7884, ni_byt_sdio), | |
1242 | SDHCI_PCI_DEVICE(INTEL, BYT_SDIO, intel_byt_sdio), | |
1243 | SDHCI_PCI_DEVICE(INTEL, BYT_SD, intel_byt_sd), | |
1244 | SDHCI_PCI_DEVICE(INTEL, BYT_EMMC2, intel_byt_emmc), | |
1245 | SDHCI_PCI_DEVICE(INTEL, BSW_EMMC, intel_byt_emmc), | |
1246 | SDHCI_PCI_DEVICE(INTEL, BSW_SDIO, intel_byt_sdio), | |
1247 | SDHCI_PCI_DEVICE(INTEL, BSW_SD, intel_byt_sd), | |
1248 | SDHCI_PCI_DEVICE(INTEL, CLV_SDIO0, intel_mfd_sd), | |
1249 | SDHCI_PCI_DEVICE(INTEL, CLV_SDIO1, intel_mfd_sdio), | |
1250 | SDHCI_PCI_DEVICE(INTEL, CLV_SDIO2, intel_mfd_sdio), | |
1251 | SDHCI_PCI_DEVICE(INTEL, CLV_EMMC0, intel_mfd_emmc), | |
1252 | SDHCI_PCI_DEVICE(INTEL, CLV_EMMC1, intel_mfd_emmc), | |
1253 | SDHCI_PCI_DEVICE(INTEL, MRFLD_MMC, intel_mrfld_mmc), | |
1254 | SDHCI_PCI_DEVICE(INTEL, SPT_EMMC, intel_byt_emmc), | |
1255 | SDHCI_PCI_DEVICE(INTEL, SPT_SDIO, intel_byt_sdio), | |
1256 | SDHCI_PCI_DEVICE(INTEL, SPT_SD, intel_byt_sd), | |
1257 | SDHCI_PCI_DEVICE(INTEL, DNV_EMMC, intel_byt_emmc), | |
1258 | SDHCI_PCI_DEVICE(INTEL, BXT_EMMC, intel_byt_emmc), | |
1259 | SDHCI_PCI_DEVICE(INTEL, BXT_SDIO, intel_byt_sdio), | |
1260 | SDHCI_PCI_DEVICE(INTEL, BXT_SD, intel_byt_sd), | |
1261 | SDHCI_PCI_DEVICE(INTEL, BXTM_EMMC, intel_byt_emmc), | |
1262 | SDHCI_PCI_DEVICE(INTEL, BXTM_SDIO, intel_byt_sdio), | |
1263 | SDHCI_PCI_DEVICE(INTEL, BXTM_SD, intel_byt_sd), | |
1264 | SDHCI_PCI_DEVICE(INTEL, APL_EMMC, intel_byt_emmc), | |
1265 | SDHCI_PCI_DEVICE(INTEL, APL_SDIO, intel_byt_sdio), | |
1266 | SDHCI_PCI_DEVICE(INTEL, APL_SD, intel_byt_sd), | |
bc55dcd8 | 1267 | SDHCI_PCI_DEVICE(INTEL, GLK_EMMC, intel_glk_emmc), |
c949c907 MK |
1268 | SDHCI_PCI_DEVICE(INTEL, GLK_SDIO, intel_byt_sdio), |
1269 | SDHCI_PCI_DEVICE(INTEL, GLK_SD, intel_byt_sd), | |
bc55dcd8 AH |
1270 | SDHCI_PCI_DEVICE(INTEL, CNP_EMMC, intel_glk_emmc), |
1271 | SDHCI_PCI_DEVICE(INTEL, CNP_SD, intel_byt_sd), | |
1272 | SDHCI_PCI_DEVICE(INTEL, CNPH_SD, intel_byt_sd), | |
c949c907 MK |
1273 | SDHCI_PCI_DEVICE(O2, 8120, o2), |
1274 | SDHCI_PCI_DEVICE(O2, 8220, o2), | |
1275 | SDHCI_PCI_DEVICE(O2, 8221, o2), | |
1276 | SDHCI_PCI_DEVICE(O2, 8320, o2), | |
1277 | SDHCI_PCI_DEVICE(O2, 8321, o2), | |
1278 | SDHCI_PCI_DEVICE(O2, FUJIN2, o2), | |
1279 | SDHCI_PCI_DEVICE(O2, SDS0, o2), | |
1280 | SDHCI_PCI_DEVICE(O2, SDS1, o2), | |
1281 | SDHCI_PCI_DEVICE(O2, SEABIRD0, o2), | |
1282 | SDHCI_PCI_DEVICE(O2, SEABIRD1, o2), | |
1283 | SDHCI_PCI_DEVICE_CLASS(AMD, SYSTEM_SDHCI, PCI_CLASS_MASK, amd), | |
1284 | /* Generic SD host controller */ | |
1285 | {PCI_DEVICE_CLASS(SYSTEM_SDHCI, PCI_CLASS_MASK)}, | |
b8c86fc5 PO |
1286 | { /* end: all zeroes */ }, |
1287 | }; | |
1288 | ||
1289 | MODULE_DEVICE_TABLE(pci, pci_ids); | |
1290 | ||
b8c86fc5 PO |
1291 | /*****************************************************************************\ |
1292 | * * | |
1293 | * SDHCI core callbacks * | |
1294 | * * | |
1295 | \*****************************************************************************/ | |
1296 | ||
1297 | static int sdhci_pci_enable_dma(struct sdhci_host *host) | |
1298 | { | |
1299 | struct sdhci_pci_slot *slot; | |
1300 | struct pci_dev *pdev; | |
b8c86fc5 PO |
1301 | |
1302 | slot = sdhci_priv(host); | |
1303 | pdev = slot->chip->pdev; | |
1304 | ||
1305 | if (((pdev->class & 0xFFFF00) == (PCI_CLASS_SYSTEM_SDHCI << 8)) && | |
1306 | ((pdev->class & 0x0000FF) != PCI_SDHCI_IFDMA) && | |
a13abc7b | 1307 | (host->flags & SDHCI_USE_SDMA)) { |
b8c86fc5 PO |
1308 | dev_warn(&pdev->dev, "Will use DMA mode even though HW " |
1309 | "doesn't fully claim to support it.\n"); | |
1310 | } | |
1311 | ||
b8c86fc5 PO |
1312 | pci_set_master(pdev); |
1313 | ||
1314 | return 0; | |
1315 | } | |
1316 | ||
2317f56c | 1317 | static void sdhci_pci_set_bus_width(struct sdhci_host *host, int width) |
68077b02 ML |
1318 | { |
1319 | u8 ctrl; | |
1320 | ||
1321 | ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); | |
1322 | ||
1323 | switch (width) { | |
1324 | case MMC_BUS_WIDTH_8: | |
1325 | ctrl |= SDHCI_CTRL_8BITBUS; | |
1326 | ctrl &= ~SDHCI_CTRL_4BITBUS; | |
1327 | break; | |
1328 | case MMC_BUS_WIDTH_4: | |
1329 | ctrl |= SDHCI_CTRL_4BITBUS; | |
1330 | ctrl &= ~SDHCI_CTRL_8BITBUS; | |
1331 | break; | |
1332 | default: | |
1333 | ctrl &= ~(SDHCI_CTRL_8BITBUS | SDHCI_CTRL_4BITBUS); | |
1334 | break; | |
1335 | } | |
1336 | ||
1337 | sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); | |
68077b02 ML |
1338 | } |
1339 | ||
c9faff6c | 1340 | static void sdhci_pci_gpio_hw_reset(struct sdhci_host *host) |
0f201655 AH |
1341 | { |
1342 | struct sdhci_pci_slot *slot = sdhci_priv(host); | |
1343 | int rst_n_gpio = slot->rst_n_gpio; | |
1344 | ||
1345 | if (!gpio_is_valid(rst_n_gpio)) | |
1346 | return; | |
1347 | gpio_set_value_cansleep(rst_n_gpio, 0); | |
1348 | /* For eMMC, minimum is 1us but give it 10us for good measure */ | |
1349 | udelay(10); | |
1350 | gpio_set_value_cansleep(rst_n_gpio, 1); | |
1351 | /* For eMMC, minimum is 200us but give it 300us for good measure */ | |
1352 | usleep_range(300, 1000); | |
1353 | } | |
1354 | ||
c9faff6c AH |
1355 | static void sdhci_pci_hw_reset(struct sdhci_host *host) |
1356 | { | |
1357 | struct sdhci_pci_slot *slot = sdhci_priv(host); | |
1358 | ||
1359 | if (slot->hw_reset) | |
1360 | slot->hw_reset(host); | |
1361 | } | |
1362 | ||
c915568d | 1363 | static const struct sdhci_ops sdhci_pci_ops = { |
1771059c | 1364 | .set_clock = sdhci_set_clock, |
b8c86fc5 | 1365 | .enable_dma = sdhci_pci_enable_dma, |
2317f56c | 1366 | .set_bus_width = sdhci_pci_set_bus_width, |
03231f9b | 1367 | .reset = sdhci_reset, |
96d7b78c | 1368 | .set_uhs_signaling = sdhci_set_uhs_signaling, |
0f201655 | 1369 | .hw_reset = sdhci_pci_hw_reset, |
b8c86fc5 PO |
1370 | }; |
1371 | ||
1372 | /*****************************************************************************\ | |
1373 | * * | |
1374 | * Suspend/resume * | |
1375 | * * | |
1376 | \*****************************************************************************/ | |
1377 | ||
f9900f15 | 1378 | #ifdef CONFIG_PM_SLEEP |
29495aa0 | 1379 | static int sdhci_pci_suspend(struct device *dev) |
b8c86fc5 | 1380 | { |
29495aa0 | 1381 | struct pci_dev *pdev = to_pci_dev(dev); |
30cf2803 | 1382 | struct sdhci_pci_chip *chip = pci_get_drvdata(pdev); |
b8c86fc5 | 1383 | |
b8c86fc5 PO |
1384 | if (!chip) |
1385 | return 0; | |
1386 | ||
30cf2803 AH |
1387 | if (chip->fixes && chip->fixes->suspend) |
1388 | return chip->fixes->suspend(chip); | |
b8c86fc5 | 1389 | |
30cf2803 | 1390 | return sdhci_pci_suspend_host(chip); |
b8c86fc5 PO |
1391 | } |
1392 | ||
29495aa0 | 1393 | static int sdhci_pci_resume(struct device *dev) |
b8c86fc5 | 1394 | { |
29495aa0 | 1395 | struct pci_dev *pdev = to_pci_dev(dev); |
30cf2803 | 1396 | struct sdhci_pci_chip *chip = pci_get_drvdata(pdev); |
b8c86fc5 | 1397 | |
b8c86fc5 PO |
1398 | if (!chip) |
1399 | return 0; | |
1400 | ||
30cf2803 AH |
1401 | if (chip->fixes && chip->fixes->resume) |
1402 | return chip->fixes->resume(chip); | |
b8c86fc5 | 1403 | |
30cf2803 | 1404 | return sdhci_pci_resume_host(chip); |
b8c86fc5 | 1405 | } |
f9900f15 | 1406 | #endif |
b8c86fc5 | 1407 | |
f9900f15 | 1408 | #ifdef CONFIG_PM |
66fd8ad5 AH |
1409 | static int sdhci_pci_runtime_suspend(struct device *dev) |
1410 | { | |
923a231c | 1411 | struct pci_dev *pdev = to_pci_dev(dev); |
966d696a | 1412 | struct sdhci_pci_chip *chip = pci_get_drvdata(pdev); |
66fd8ad5 | 1413 | |
66fd8ad5 AH |
1414 | if (!chip) |
1415 | return 0; | |
1416 | ||
966d696a AH |
1417 | if (chip->fixes && chip->fixes->runtime_suspend) |
1418 | return chip->fixes->runtime_suspend(chip); | |
66fd8ad5 | 1419 | |
966d696a | 1420 | return sdhci_pci_runtime_suspend_host(chip); |
66fd8ad5 AH |
1421 | } |
1422 | ||
1423 | static int sdhci_pci_runtime_resume(struct device *dev) | |
1424 | { | |
923a231c | 1425 | struct pci_dev *pdev = to_pci_dev(dev); |
966d696a | 1426 | struct sdhci_pci_chip *chip = pci_get_drvdata(pdev); |
66fd8ad5 | 1427 | |
66fd8ad5 AH |
1428 | if (!chip) |
1429 | return 0; | |
1430 | ||
966d696a AH |
1431 | if (chip->fixes && chip->fixes->runtime_resume) |
1432 | return chip->fixes->runtime_resume(chip); | |
66fd8ad5 | 1433 | |
966d696a | 1434 | return sdhci_pci_runtime_resume_host(chip); |
66fd8ad5 | 1435 | } |
f9900f15 | 1436 | #endif |
66fd8ad5 AH |
1437 | |
1438 | static const struct dev_pm_ops sdhci_pci_pm_ops = { | |
f9900f15 | 1439 | SET_SYSTEM_SLEEP_PM_OPS(sdhci_pci_suspend, sdhci_pci_resume) |
f3a92b1a | 1440 | SET_RUNTIME_PM_OPS(sdhci_pci_runtime_suspend, |
106276bb | 1441 | sdhci_pci_runtime_resume, NULL) |
66fd8ad5 AH |
1442 | }; |
1443 | ||
b8c86fc5 PO |
1444 | /*****************************************************************************\ |
1445 | * * | |
1446 | * Device probing/removal * | |
1447 | * * | |
1448 | \*****************************************************************************/ | |
1449 | ||
c3be1efd | 1450 | static struct sdhci_pci_slot *sdhci_pci_probe_slot( |
52c506f0 AH |
1451 | struct pci_dev *pdev, struct sdhci_pci_chip *chip, int first_bar, |
1452 | int slotno) | |
b8c86fc5 PO |
1453 | { |
1454 | struct sdhci_pci_slot *slot; | |
1455 | struct sdhci_host *host; | |
52c506f0 | 1456 | int ret, bar = first_bar + slotno; |
ac9f67b5 | 1457 | size_t priv_size = chip->fixes ? chip->fixes->priv_size : 0; |
b8c86fc5 PO |
1458 | |
1459 | if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) { | |
1460 | dev_err(&pdev->dev, "BAR %d is not iomem. Aborting.\n", bar); | |
1461 | return ERR_PTR(-ENODEV); | |
1462 | } | |
1463 | ||
90b3e6c5 | 1464 | if (pci_resource_len(pdev, bar) < 0x100) { |
b8c86fc5 PO |
1465 | dev_err(&pdev->dev, "Invalid iomem size. You may " |
1466 | "experience problems.\n"); | |
1467 | } | |
1468 | ||
1469 | if ((pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) { | |
1470 | dev_err(&pdev->dev, "Vendor specific interface. Aborting.\n"); | |
1471 | return ERR_PTR(-ENODEV); | |
1472 | } | |
1473 | ||
1474 | if ((pdev->class & 0x0000FF) > PCI_SDHCI_IFVENDOR) { | |
1475 | dev_err(&pdev->dev, "Unknown interface. Aborting.\n"); | |
1476 | return ERR_PTR(-ENODEV); | |
1477 | } | |
1478 | ||
ac9f67b5 | 1479 | host = sdhci_alloc_host(&pdev->dev, sizeof(*slot) + priv_size); |
b8c86fc5 | 1480 | if (IS_ERR(host)) { |
c60a32cd | 1481 | dev_err(&pdev->dev, "cannot allocate host\n"); |
dc0fd7b5 | 1482 | return ERR_CAST(host); |
b8c86fc5 PO |
1483 | } |
1484 | ||
1485 | slot = sdhci_priv(host); | |
1486 | ||
1487 | slot->chip = chip; | |
1488 | slot->host = host; | |
0f201655 | 1489 | slot->rst_n_gpio = -EINVAL; |
c5e027a4 | 1490 | slot->cd_gpio = -EINVAL; |
ff59c520 | 1491 | slot->cd_idx = -1; |
b8c86fc5 | 1492 | |
52c506f0 AH |
1493 | /* Retrieve platform data if there is any */ |
1494 | if (*sdhci_pci_get_data) | |
1495 | slot->data = sdhci_pci_get_data(pdev, slotno); | |
1496 | ||
1497 | if (slot->data) { | |
1498 | if (slot->data->setup) { | |
1499 | ret = slot->data->setup(slot->data); | |
1500 | if (ret) { | |
1501 | dev_err(&pdev->dev, "platform setup failed\n"); | |
1502 | goto free; | |
1503 | } | |
1504 | } | |
c5e027a4 AH |
1505 | slot->rst_n_gpio = slot->data->rst_n_gpio; |
1506 | slot->cd_gpio = slot->data->cd_gpio; | |
52c506f0 AH |
1507 | } |
1508 | ||
b8c86fc5 | 1509 | host->hw_name = "PCI"; |
6bc09063 AH |
1510 | host->ops = chip->fixes && chip->fixes->ops ? |
1511 | chip->fixes->ops : | |
1512 | &sdhci_pci_ops; | |
b8c86fc5 | 1513 | host->quirks = chip->quirks; |
f3c55a7b | 1514 | host->quirks2 = chip->quirks2; |
b8c86fc5 PO |
1515 | |
1516 | host->irq = pdev->irq; | |
1517 | ||
c10bc372 | 1518 | ret = pcim_iomap_regions(pdev, BIT(bar), mmc_hostname(host->mmc)); |
b8c86fc5 PO |
1519 | if (ret) { |
1520 | dev_err(&pdev->dev, "cannot request region\n"); | |
52c506f0 | 1521 | goto cleanup; |
b8c86fc5 PO |
1522 | } |
1523 | ||
c10bc372 | 1524 | host->ioaddr = pcim_iomap_table(pdev)[bar]; |
b8c86fc5 | 1525 | |
4489428a PO |
1526 | if (chip->fixes && chip->fixes->probe_slot) { |
1527 | ret = chip->fixes->probe_slot(slot); | |
1528 | if (ret) | |
c10bc372 | 1529 | goto cleanup; |
4489428a PO |
1530 | } |
1531 | ||
c5e027a4 | 1532 | if (gpio_is_valid(slot->rst_n_gpio)) { |
c10bc372 | 1533 | if (!devm_gpio_request(&pdev->dev, slot->rst_n_gpio, "eMMC_reset")) { |
c5e027a4 AH |
1534 | gpio_direction_output(slot->rst_n_gpio, 1); |
1535 | slot->host->mmc->caps |= MMC_CAP_HW_RESET; | |
c9faff6c | 1536 | slot->hw_reset = sdhci_pci_gpio_hw_reset; |
c5e027a4 AH |
1537 | } else { |
1538 | dev_warn(&pdev->dev, "failed to request rst_n_gpio\n"); | |
1539 | slot->rst_n_gpio = -EINVAL; | |
1540 | } | |
1541 | } | |
1542 | ||
2f4cbb3d | 1543 | host->mmc->pm_caps = MMC_PM_KEEP_POWER | MMC_PM_WAKE_SDIO_IRQ; |
eed222ac | 1544 | host->mmc->slotno = slotno; |
a08b17be | 1545 | host->mmc->caps2 |= MMC_CAP2_NO_PRESCAN_POWERUP; |
2f4cbb3d | 1546 | |
8f743d03 | 1547 | if (slot->cd_idx >= 0) { |
6ac9b837 | 1548 | ret = mmc_gpiod_request_cd(host->mmc, NULL, slot->cd_idx, |
8f743d03 DB |
1549 | slot->cd_override_level, 0, NULL); |
1550 | if (ret == -EPROBE_DEFER) | |
1551 | goto remove; | |
1552 | ||
1553 | if (ret) { | |
1554 | dev_warn(&pdev->dev, "failed to setup card detect gpio\n"); | |
1555 | slot->cd_idx = -1; | |
1556 | } | |
ff59c520 AH |
1557 | } |
1558 | ||
61c951de AH |
1559 | if (chip->fixes && chip->fixes->add_host) |
1560 | ret = chip->fixes->add_host(slot); | |
1561 | else | |
1562 | ret = sdhci_add_host(host); | |
b8c86fc5 | 1563 | if (ret) |
4489428a | 1564 | goto remove; |
b8c86fc5 | 1565 | |
c5e027a4 AH |
1566 | sdhci_pci_add_own_cd(slot); |
1567 | ||
77a0122e AH |
1568 | /* |
1569 | * Check if the chip needs a separate GPIO for card detect to wake up | |
1570 | * from runtime suspend. If it is not there, don't allow runtime PM. | |
1571 | * Note sdhci_pci_add_own_cd() sets slot->cd_gpio to -EINVAL on failure. | |
1572 | */ | |
945be38c | 1573 | if (chip->fixes && chip->fixes->own_cd_for_runtime_pm && |
ff59c520 | 1574 | !gpio_is_valid(slot->cd_gpio) && slot->cd_idx < 0) |
77a0122e AH |
1575 | chip->allow_runtime_pm = false; |
1576 | ||
b8c86fc5 PO |
1577 | return slot; |
1578 | ||
4489428a PO |
1579 | remove: |
1580 | if (chip->fixes && chip->fixes->remove_slot) | |
1e72859e | 1581 | chip->fixes->remove_slot(slot, 0); |
4489428a | 1582 | |
52c506f0 AH |
1583 | cleanup: |
1584 | if (slot->data && slot->data->cleanup) | |
1585 | slot->data->cleanup(slot->data); | |
1586 | ||
c60a32cd | 1587 | free: |
b8c86fc5 PO |
1588 | sdhci_free_host(host); |
1589 | ||
1590 | return ERR_PTR(ret); | |
1591 | } | |
1592 | ||
1593 | static void sdhci_pci_remove_slot(struct sdhci_pci_slot *slot) | |
1594 | { | |
1e72859e PO |
1595 | int dead; |
1596 | u32 scratch; | |
1597 | ||
c5e027a4 AH |
1598 | sdhci_pci_remove_own_cd(slot); |
1599 | ||
1e72859e PO |
1600 | dead = 0; |
1601 | scratch = readl(slot->host->ioaddr + SDHCI_INT_STATUS); | |
1602 | if (scratch == (u32)-1) | |
1603 | dead = 1; | |
1604 | ||
1605 | sdhci_remove_host(slot->host, dead); | |
4489428a PO |
1606 | |
1607 | if (slot->chip->fixes && slot->chip->fixes->remove_slot) | |
1e72859e | 1608 | slot->chip->fixes->remove_slot(slot, dead); |
4489428a | 1609 | |
52c506f0 AH |
1610 | if (slot->data && slot->data->cleanup) |
1611 | slot->data->cleanup(slot->data); | |
1612 | ||
b8c86fc5 PO |
1613 | sdhci_free_host(slot->host); |
1614 | } | |
1615 | ||
c3be1efd | 1616 | static void sdhci_pci_runtime_pm_allow(struct device *dev) |
66fd8ad5 | 1617 | { |
00884b61 | 1618 | pm_suspend_ignore_children(dev, 1); |
66fd8ad5 AH |
1619 | pm_runtime_set_autosuspend_delay(dev, 50); |
1620 | pm_runtime_use_autosuspend(dev); | |
00884b61 AH |
1621 | pm_runtime_allow(dev); |
1622 | /* Stay active until mmc core scans for a card */ | |
1623 | pm_runtime_put_noidle(dev); | |
66fd8ad5 AH |
1624 | } |
1625 | ||
6e0ee714 | 1626 | static void sdhci_pci_runtime_pm_forbid(struct device *dev) |
66fd8ad5 AH |
1627 | { |
1628 | pm_runtime_forbid(dev); | |
1629 | pm_runtime_get_noresume(dev); | |
1630 | } | |
1631 | ||
c3be1efd | 1632 | static int sdhci_pci_probe(struct pci_dev *pdev, |
b8c86fc5 PO |
1633 | const struct pci_device_id *ent) |
1634 | { | |
1635 | struct sdhci_pci_chip *chip; | |
1636 | struct sdhci_pci_slot *slot; | |
1637 | ||
cf5e23e1 | 1638 | u8 slots, first_bar; |
b8c86fc5 PO |
1639 | int ret, i; |
1640 | ||
1641 | BUG_ON(pdev == NULL); | |
1642 | BUG_ON(ent == NULL); | |
1643 | ||
b8c86fc5 | 1644 | dev_info(&pdev->dev, "SDHCI controller found [%04x:%04x] (rev %x)\n", |
cf5e23e1 | 1645 | (int)pdev->vendor, (int)pdev->device, (int)pdev->revision); |
b8c86fc5 PO |
1646 | |
1647 | ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &slots); | |
1648 | if (ret) | |
1649 | return ret; | |
1650 | ||
1651 | slots = PCI_SLOT_INFO_SLOTS(slots) + 1; | |
1652 | dev_dbg(&pdev->dev, "found %d slot(s)\n", slots); | |
1653 | if (slots == 0) | |
1654 | return -ENODEV; | |
1655 | ||
1656 | BUG_ON(slots > MAX_SLOTS); | |
1657 | ||
1658 | ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &first_bar); | |
1659 | if (ret) | |
1660 | return ret; | |
1661 | ||
1662 | first_bar &= PCI_SLOT_INFO_FIRST_BAR_MASK; | |
1663 | ||
1664 | if (first_bar > 5) { | |
1665 | dev_err(&pdev->dev, "Invalid first BAR. Aborting.\n"); | |
1666 | return -ENODEV; | |
1667 | } | |
1668 | ||
52ac7acf | 1669 | ret = pcim_enable_device(pdev); |
b8c86fc5 PO |
1670 | if (ret) |
1671 | return ret; | |
1672 | ||
52ac7acf AS |
1673 | chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL); |
1674 | if (!chip) | |
1675 | return -ENOMEM; | |
b8c86fc5 PO |
1676 | |
1677 | chip->pdev = pdev; | |
b177bc91 | 1678 | chip->fixes = (const struct sdhci_pci_fixes *)ent->driver_data; |
c43fd774 | 1679 | if (chip->fixes) { |
22606405 | 1680 | chip->quirks = chip->fixes->quirks; |
f3c55a7b | 1681 | chip->quirks2 = chip->fixes->quirks2; |
c43fd774 AH |
1682 | chip->allow_runtime_pm = chip->fixes->allow_runtime_pm; |
1683 | } | |
b8c86fc5 | 1684 | chip->num_slots = slots; |
d38dcad4 AH |
1685 | chip->pm_retune = true; |
1686 | chip->rpm_retune = true; | |
b8c86fc5 PO |
1687 | |
1688 | pci_set_drvdata(pdev, chip); | |
1689 | ||
22606405 PO |
1690 | if (chip->fixes && chip->fixes->probe) { |
1691 | ret = chip->fixes->probe(chip); | |
1692 | if (ret) | |
52ac7acf | 1693 | return ret; |
22606405 PO |
1694 | } |
1695 | ||
225d85fe AC |
1696 | slots = chip->num_slots; /* Quirk may have changed this */ |
1697 | ||
b177bc91 | 1698 | for (i = 0; i < slots; i++) { |
52c506f0 | 1699 | slot = sdhci_pci_probe_slot(pdev, chip, first_bar, i); |
b8c86fc5 | 1700 | if (IS_ERR(slot)) { |
b177bc91 | 1701 | for (i--; i >= 0; i--) |
b8c86fc5 | 1702 | sdhci_pci_remove_slot(chip->slots[i]); |
52ac7acf | 1703 | return PTR_ERR(slot); |
b8c86fc5 PO |
1704 | } |
1705 | ||
1706 | chip->slots[i] = slot; | |
1707 | } | |
1708 | ||
c43fd774 AH |
1709 | if (chip->allow_runtime_pm) |
1710 | sdhci_pci_runtime_pm_allow(&pdev->dev); | |
66fd8ad5 | 1711 | |
b8c86fc5 | 1712 | return 0; |
b8c86fc5 PO |
1713 | } |
1714 | ||
6e0ee714 | 1715 | static void sdhci_pci_remove(struct pci_dev *pdev) |
b8c86fc5 PO |
1716 | { |
1717 | int i; | |
52ac7acf | 1718 | struct sdhci_pci_chip *chip = pci_get_drvdata(pdev); |
c43fd774 | 1719 | |
52ac7acf AS |
1720 | if (chip->allow_runtime_pm) |
1721 | sdhci_pci_runtime_pm_forbid(&pdev->dev); | |
b8c86fc5 | 1722 | |
52ac7acf AS |
1723 | for (i = 0; i < chip->num_slots; i++) |
1724 | sdhci_pci_remove_slot(chip->slots[i]); | |
b8c86fc5 PO |
1725 | } |
1726 | ||
1727 | static struct pci_driver sdhci_driver = { | |
b177bc91 | 1728 | .name = "sdhci-pci", |
b8c86fc5 | 1729 | .id_table = pci_ids, |
b177bc91 | 1730 | .probe = sdhci_pci_probe, |
0433c143 | 1731 | .remove = sdhci_pci_remove, |
66fd8ad5 AH |
1732 | .driver = { |
1733 | .pm = &sdhci_pci_pm_ops | |
1734 | }, | |
b8c86fc5 PO |
1735 | }; |
1736 | ||
acc69646 | 1737 | module_pci_driver(sdhci_driver); |
b8c86fc5 | 1738 | |
32710e8f | 1739 | MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>"); |
b8c86fc5 PO |
1740 | MODULE_DESCRIPTION("Secure Digital Host Controller Interface PCI driver"); |
1741 | MODULE_LICENSE("GPL"); |