]> git.proxmox.com Git - mirror_ubuntu-eoan-kernel.git/blame - drivers/mmc/host/sdhci-pci-core.c
projects / mirror_ubuntu-eoan-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
mmc: sdhci: Support cap_cmd_during_tfr requests
[mirror_ubuntu-eoan-kernel.git] / drivers / mmc / host / sdhci-pci-core.c
CommitLineData
b8c86fc5
PO		 1/* linux/drivers/mmc/host/sdhci-pci.c - SDHCI on PCI bus interface
2 *
3 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or (at
8 * your option) any later version.
9 *
10 * Thanks to the following companies for their support:
11 *
12 * - JMicron (hardware and technical support)
13 */
14
15#include <linux/delay.h>
16#include <linux/highmem.h>
88b47679 17#include <linux/module.h>
b8c86fc5
PO		 18#include <linux/pci.h>
19#include <linux/dma-mapping.h>
5a0e3ad6 20#include <linux/slab.h>
ccc92c23 21#include <linux/device.h>
b8c86fc5 22#include <linux/mmc/host.h>
e1bfad6d 23#include <linux/mmc/mmc.h>
b177bc91
AP		 24#include <linux/scatterlist.h>
25#include <linux/io.h>
0f201655 26#include <linux/gpio.h>
66fd8ad5 27#include <linux/pm_runtime.h>
ff59c520 28#include <linux/mmc/slot-gpio.h>
52c506f0 29#include <linux/mmc/sdhci-pci-data.h>
b8c86fc5
PO		 30
31#include "sdhci.h"
522624f9 32#include "sdhci-pci.h"
01acf691 33#include "sdhci-pci-o2micro.h"
22606405
PO		 34
35/*****************************************************************************\
36 * *
37 * Hardware specific quirk handling *
38 * *
39\*****************************************************************************/
40
41static int ricoh_probe(struct sdhci_pci_chip *chip)
42{
c99436fb
CB		 43 if (chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG ||
44 chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SONY)
22606405 45 chip->quirks |= SDHCI_QUIRK_NO_CARD_NO_RESET;
ccc92c23
ML		 46 return 0;
47}
48
49static int ricoh_mmc_probe_slot(struct sdhci_pci_slot *slot)
50{
51 slot->host->caps =
52 ((0x21 << SDHCI_TIMEOUT_CLK_SHIFT)
53 & SDHCI_TIMEOUT_CLK_MASK) |
22606405 54
ccc92c23
ML		 55 ((0x21 << SDHCI_CLOCK_BASE_SHIFT)
56 & SDHCI_CLOCK_BASE_MASK) |
57
58 SDHCI_TIMEOUT_CLK_UNIT |
59 SDHCI_CAN_VDD_330 |
1a1f1f04 60 SDHCI_CAN_DO_HISPD |
ccc92c23
ML		 61 SDHCI_CAN_DO_SDMA;
62 return 0;
63}
64
65static int ricoh_mmc_resume(struct sdhci_pci_chip *chip)
66{
67 /* Apply a delay to allow controller to settle */
68 /* Otherwise it becomes confused if card state changed
69 during suspend */
70 msleep(500);
22606405
PO		 71 return 0;
72}
73
74static const struct sdhci_pci_fixes sdhci_ricoh = {
75 .probe = ricoh_probe,
84938294
VK		 76 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR |
77 SDHCI_QUIRK_FORCE_DMA |
78 SDHCI_QUIRK_CLOCK_BEFORE_RESET,
22606405
PO		 79};
80
ccc92c23
ML		 81static const struct sdhci_pci_fixes sdhci_ricoh_mmc = {
82 .probe_slot = ricoh_mmc_probe_slot,
83 .resume = ricoh_mmc_resume,
84 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR |
85 SDHCI_QUIRK_CLOCK_BEFORE_RESET |
86 SDHCI_QUIRK_NO_CARD_NO_RESET |
87 SDHCI_QUIRK_MISSING_CAPS
88};
89
22606405
PO		 90static const struct sdhci_pci_fixes sdhci_ene_712 = {
91 .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE |
92 SDHCI_QUIRK_BROKEN_DMA,
93};
94
95static const struct sdhci_pci_fixes sdhci_ene_714 = {
96 .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE |
97 SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS |
98 SDHCI_QUIRK_BROKEN_DMA,
99};
100
101static const struct sdhci_pci_fixes sdhci_cafe = {
102 .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER |
a0874897 103 SDHCI_QUIRK_NO_BUSY_IRQ |
55fc05b7 104 SDHCI_QUIRK_BROKEN_CARD_DETECTION |
ee53ab5d 105 SDHCI_QUIRK_BROKEN_TIMEOUT_VAL,
22606405
PO		 106};
107
43e968ce
DB		 108static const struct sdhci_pci_fixes sdhci_intel_qrk = {
109 .quirks = SDHCI_QUIRK_NO_HISPD_BIT,
110};
111
68077b02
ML		 112static int mrst_hc_probe_slot(struct sdhci_pci_slot *slot)
113{
114 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA;
115 return 0;
116}
117
f9ee3eab
AC		 118/*
119 * ADMA operation is disabled for Moorestown platform due to
120 * hardware bugs.
121 */
35ac6f08 122static int mrst_hc_probe(struct sdhci_pci_chip *chip)
f9ee3eab
AC		 123{
124 /*
35ac6f08
JP		 125 * slots number is fixed here for MRST as SDIO3/5 are never used and
126 * have hardware bugs.
f9ee3eab
AC		 127 */
128 chip->num_slots = 1;
129 return 0;
130}
131
296e0b03
AS		 132static int pch_hc_probe_slot(struct sdhci_pci_slot *slot)
133{
134 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA;
135 return 0;
136}
137
162d6f98 138#ifdef CONFIG_PM
66fd8ad5 139
c5e027a4 140static irqreturn_t sdhci_pci_sd_cd(int irq, void *dev_id)
66fd8ad5
AH		 141{
142 struct sdhci_pci_slot *slot = dev_id;
143 struct sdhci_host *host = slot->host;
144
145 mmc_detect_change(host->mmc, msecs_to_jiffies(200));
146 return IRQ_HANDLED;
147}
148
c5e027a4 149static void sdhci_pci_add_own_cd(struct sdhci_pci_slot *slot)
66fd8ad5 150{
c5e027a4 151 int err, irq, gpio = slot->cd_gpio;
66fd8ad5
AH		 152
153 slot->cd_gpio = -EINVAL;
154 slot->cd_irq = -EINVAL;
155
c5e027a4
AH		 156 if (!gpio_is_valid(gpio))
157 return;
158
c10bc372 159 err = devm_gpio_request(&slot->chip->pdev->dev, gpio, "sd_cd");
66fd8ad5
AH		 160 if (err < 0)
161 goto out;
162
163 err = gpio_direction_input(gpio);
164 if (err < 0)
165 goto out_free;
166
167 irq = gpio_to_irq(gpio);
168 if (irq < 0)
169 goto out_free;
170
c5e027a4 171 err = request_irq(irq, sdhci_pci_sd_cd, IRQF_TRIGGER_RISING |
66fd8ad5
AH		 172 IRQF_TRIGGER_FALLING, "sd_cd", slot);
173 if (err)
174 goto out_free;
175
176 slot->cd_gpio = gpio;
177 slot->cd_irq = irq;
66fd8ad5 178
c5e027a4 179 return;
66fd8ad5
AH		 180
181out_free:
c10bc372 182 devm_gpio_free(&slot->chip->pdev->dev, gpio);
66fd8ad5
AH		 183out:
184 dev_warn(&slot->chip->pdev->dev, "failed to setup card detect wake up\n");
66fd8ad5
AH		 185}
186
c5e027a4 187static void sdhci_pci_remove_own_cd(struct sdhci_pci_slot *slot)
66fd8ad5
AH		 188{
189 if (slot->cd_irq >= 0)
190 free_irq(slot->cd_irq, slot);
66fd8ad5
AH		 191}
192
193#else
194
c5e027a4
AH		 195static inline void sdhci_pci_add_own_cd(struct sdhci_pci_slot *slot)
196{
197}
198
199static inline void sdhci_pci_remove_own_cd(struct sdhci_pci_slot *slot)
200{
201}
66fd8ad5
AH		 202
203#endif
204
0d013bcf
AH		 205static int mfd_emmc_probe_slot(struct sdhci_pci_slot *slot)
206{
66fd8ad5 207 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE;
da721cf7
AH		 208 slot->host->mmc->caps2 |= MMC_CAP2_BOOTPART_NOACC |
209 MMC_CAP2_HC_ERASE_SZ;
0d013bcf
AH		 210 return 0;
211}
212
93933508
AH		 213static int mfd_sdio_probe_slot(struct sdhci_pci_slot *slot)
214{
012e4671 215 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE;
93933508
AH		 216 return 0;
217}
218
f9ee3eab
AC		 219static const struct sdhci_pci_fixes sdhci_intel_mrst_hc0 = {
220 .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT,
68077b02 221 .probe_slot = mrst_hc_probe_slot,
f9ee3eab
AC		 222};
223
35ac6f08 224static const struct sdhci_pci_fixes sdhci_intel_mrst_hc1_hc2 = {
f9ee3eab 225 .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT,
35ac6f08 226 .probe = mrst_hc_probe,
f9ee3eab
AC		 227};
228
29229052
XS		 229static const struct sdhci_pci_fixes sdhci_intel_mfd_sd = {
230 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
c43fd774 231 .allow_runtime_pm = true,
77a0122e 232 .own_cd_for_runtime_pm = true,
29229052
XS		 233};
234
0d013bcf
AH		 235static const struct sdhci_pci_fixes sdhci_intel_mfd_sdio = {
236 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
f3c55a7b 237 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON,
c43fd774 238 .allow_runtime_pm = true,
93933508 239 .probe_slot = mfd_sdio_probe_slot,
0d013bcf
AH		 240};
241
242static const struct sdhci_pci_fixes sdhci_intel_mfd_emmc = {
29229052 243 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
c43fd774 244 .allow_runtime_pm = true,
0d013bcf 245 .probe_slot = mfd_emmc_probe_slot,
29229052
XS		 246};
247
296e0b03
AS		 248static const struct sdhci_pci_fixes sdhci_intel_pch_sdio = {
249 .quirks = SDHCI_QUIRK_BROKEN_ADMA,
250 .probe_slot = pch_hc_probe_slot,
251};
252
c9faff6c
AH		 253static void sdhci_pci_int_hw_reset(struct sdhci_host *host)
254{
255 u8 reg;
256
257 reg = sdhci_readb(host, SDHCI_POWER_CONTROL);
258 reg |= 0x10;
259 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL);
260 /* For eMMC, minimum is 1us but give it 9us for good measure */
261 udelay(9);
262 reg &= ~0x10;
263 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL);
264 /* For eMMC, minimum is 200us but give it 300us for good measure */
265 usleep_range(300, 1000);
266}
267
e1bfad6d
AH		 268static int spt_select_drive_strength(struct sdhci_host *host,
269 struct mmc_card *card,
270 unsigned int max_dtr,
271 int host_drv, int card_drv, int *drv_type)
272{
273 int drive_strength;
274
275 if (sdhci_pci_spt_drive_strength > 0)
276 drive_strength = sdhci_pci_spt_drive_strength & 0xf;
277 else
1ca89685 278 drive_strength = 0; /* Default 50-ohm */
e1bfad6d
AH		 279
280 if ((mmc_driver_type_mask(drive_strength) & card_drv) == 0)
281 drive_strength = 0; /* Default 50-ohm */
282
283 return drive_strength;
284}
285
286/* Try to read the drive strength from the card */
287static void spt_read_drive_strength(struct sdhci_host *host)
288{
289 u32 val, i, t;
290 u16 m;
291
292 if (sdhci_pci_spt_drive_strength)
293 return;
294
295 sdhci_pci_spt_drive_strength = -1;
296
297 m = sdhci_readw(host, SDHCI_HOST_CONTROL2) & 0x7;
298 if (m != 3 && m != 5)
299 return;
300 val = sdhci_readl(host, SDHCI_PRESENT_STATE);
301 if (val & 0x3)
302 return;
303 sdhci_writel(host, 0x007f0023, SDHCI_INT_ENABLE);
304 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
305 sdhci_writew(host, 0x10, SDHCI_TRANSFER_MODE);
306 sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL);
307 sdhci_writew(host, 512, SDHCI_BLOCK_SIZE);
308 sdhci_writew(host, 1, SDHCI_BLOCK_COUNT);
309 sdhci_writel(host, 0, SDHCI_ARGUMENT);
310 sdhci_writew(host, 0x83b, SDHCI_COMMAND);
311 for (i = 0; i < 1000; i++) {
312 val = sdhci_readl(host, SDHCI_INT_STATUS);
313 if (val & 0xffff8000)
314 return;
315 if (val & 0x20)
316 break;
317 udelay(1);
318 }
319 val = sdhci_readl(host, SDHCI_PRESENT_STATE);
320 if (!(val & 0x800))
321 return;
322 for (i = 0; i < 47; i++)
323 val = sdhci_readl(host, SDHCI_BUFFER);
324 t = val & 0xf00;
325 if (t != 0x200 && t != 0x300)
326 return;
327
328 sdhci_pci_spt_drive_strength = 0x10 | ((val >> 12) & 0xf);
329}
330
163cbe31
AH		 331static int bxt_get_cd(struct mmc_host *mmc)
332{
333 int gpio_cd = mmc_gpio_get_cd(mmc);
334 struct sdhci_host *host = mmc_priv(mmc);
335 unsigned long flags;
336 int ret = 0;
337
338 if (!gpio_cd)
339 return 0;
340
163cbe31
AH		 341 spin_lock_irqsave(&host->lock, flags);
342
343 if (host->flags & SDHCI_DEVICE_DEAD)
344 goto out;
345
346 ret = !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
347out:
348 spin_unlock_irqrestore(&host->lock, flags);
349
163cbe31
AH		 350 return ret;
351}
352
728ef3d1
AH		 353static int byt_emmc_probe_slot(struct sdhci_pci_slot *slot)
354{
c9faff6c 355 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE |
6aab23a8 356 MMC_CAP_HW_RESET | MMC_CAP_1_8V_DDR |
6aab23a8 357 MMC_CAP_WAIT_WHILE_BUSY;
728ef3d1 358 slot->host->mmc->caps2 |= MMC_CAP2_HC_ERASE_SZ;
c9faff6c 359 slot->hw_reset = sdhci_pci_int_hw_reset;
a06586b6
AH		 360 if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BSW_EMMC)
361 slot->host->timeout_clk = 1000; /* 1000 kHz i.e. 1 MHz */
e1bfad6d
AH		 362 if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_SPT_EMMC) {
363 spt_read_drive_strength(slot->host);
364 slot->select_drive_strength = spt_select_drive_strength;
365 }
728ef3d1
AH		 366 return 0;
367}
368
369static int byt_sdio_probe_slot(struct sdhci_pci_slot *slot)
370{
6aab23a8 371 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE |
6aab23a8 372 MMC_CAP_WAIT_WHILE_BUSY;
728ef3d1
AH		 373 return 0;
374}
375
ff59c520
AH		 376static int byt_sd_probe_slot(struct sdhci_pci_slot *slot)
377{
82296936 378 slot->host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY;
ff59c520
AH		 379 slot->cd_con_id = NULL;
380 slot->cd_idx = 0;
381 slot->cd_override_level = true;
163cbe31 382 if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BXT_SD ||
01d6b2a4 383 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BXTM_SD ||
e8ef5176 384 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_APL_SD) {
163cbe31 385 slot->host->mmc_host_ops.get_cd = bxt_get_cd;
e8ef5176
AH		 386 slot->host->mmc->caps |= MMC_CAP_AGGRESSIVE_PM;
387 }
163cbe31 388
ff59c520
AH		 389 return 0;
390}
391
728ef3d1
AH		 392static const struct sdhci_pci_fixes sdhci_intel_byt_emmc = {
393 .allow_runtime_pm = true,
394 .probe_slot = byt_emmc_probe_slot,
db6e8cdf 395 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
e58e4a0d 396 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
b69587e2 397 SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 |
e58e4a0d 398 SDHCI_QUIRK2_STOP_WITH_TC,
728ef3d1
AH		 399};
400
401static const struct sdhci_pci_fixes sdhci_intel_byt_sdio = {
db6e8cdf 402 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
b7574bad
GY		 403 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON |
404 SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
728ef3d1
AH		 405 .allow_runtime_pm = true,
406 .probe_slot = byt_sdio_probe_slot,
407};
408
409static const struct sdhci_pci_fixes sdhci_intel_byt_sd = {
db6e8cdf 410 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
b7574bad 411 .quirks2 = SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON |
e58e4a0d
AH		 412 SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
413 SDHCI_QUIRK2_STOP_WITH_TC,
7396e318 414 .allow_runtime_pm = true,
77a0122e 415 .own_cd_for_runtime_pm = true,
ff59c520 416 .probe_slot = byt_sd_probe_slot,
728ef3d1
AH		 417};
418
8776a165 419/* Define Host controllers for Intel Merrifield platform */
1f64cec2
AS		 420#define INTEL_MRFLD_EMMC_0 0
421#define INTEL_MRFLD_EMMC_1 1
4674b6c8 422#define INTEL_MRFLD_SD 2
d5565577 423#define INTEL_MRFLD_SDIO 3
8776a165 424
1f64cec2 425static int intel_mrfld_mmc_probe_slot(struct sdhci_pci_slot *slot)
8776a165 426{
2e57bbe2
AS		 427 unsigned int func = PCI_FUNC(slot->chip->pdev->devfn);
428
429 switch (func) {
430 case INTEL_MRFLD_EMMC_0:
431 case INTEL_MRFLD_EMMC_1:
432 slot->host->mmc->caps |= MMC_CAP_NONREMOVABLE |
433 MMC_CAP_8_BIT_DATA |
434 MMC_CAP_1_8V_DDR;
435 break;
4674b6c8
AS		 436 case INTEL_MRFLD_SD:
437 slot->host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V;
438 break;
d5565577
AS		 439 case INTEL_MRFLD_SDIO:
440 slot->host->mmc->caps |= MMC_CAP_NONREMOVABLE |
441 MMC_CAP_POWER_OFF_CARD;
442 break;
2e57bbe2 443 default:
8776a165 444 return -ENODEV;
2e57bbe2 445 }
8776a165
DC		 446 return 0;
447}
448
1f64cec2 449static const struct sdhci_pci_fixes sdhci_intel_mrfld_mmc = {
8776a165 450 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
b7574bad
GY		 451 .quirks2 = SDHCI_QUIRK2_BROKEN_HS200 |
452 SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
f1b55a55 453 .allow_runtime_pm = true,
1f64cec2 454 .probe_slot = intel_mrfld_mmc_probe_slot,
8776a165
DC		 455};
456
26daa1ed
JL		 457/* O2Micro extra registers */
458#define O2_SD_LOCK_WP 0xD3
459#define O2_SD_MULTI_VCC3V 0xEE
460#define O2_SD_CLKREQ 0xEC
461#define O2_SD_CAPS 0xE0
462#define O2_SD_ADMA1 0xE2
463#define O2_SD_ADMA2 0xE7
464#define O2_SD_INF_MOD 0xF1
465
45211e21
PO		 466static int jmicron_pmos(struct sdhci_pci_chip *chip, int on)
467{
468 u8 scratch;
469 int ret;
470
471 ret = pci_read_config_byte(chip->pdev, 0xAE, &scratch);
472 if (ret)
473 return ret;
474
475 /*
476 * Turn PMOS on [bit 0], set over current detection to 2.4 V
477 * [bit 1:2] and enable over current debouncing [bit 6].
478 */
479 if (on)
480 scratch |= 0x47;
481 else
482 scratch &= ~0x47;
483
7582041f 484 return pci_write_config_byte(chip->pdev, 0xAE, scratch);
45211e21
PO		 485}
486
487static int jmicron_probe(struct sdhci_pci_chip *chip)
488{
489 int ret;
8f230f45 490 u16 mmcdev = 0;
45211e21 491
93fc48c7
PO		 492 if (chip->pdev->revision == 0) {
493 chip->quirks |= SDHCI_QUIRK_32BIT_DMA_ADDR |
494 SDHCI_QUIRK_32BIT_DMA_SIZE |
2134a922 495 SDHCI_QUIRK_32BIT_ADMA_SIZE |
4a3cba32 496 SDHCI_QUIRK_RESET_AFTER_REQUEST |
86a6a874 497 SDHCI_QUIRK_BROKEN_SMALL_PIO;
93fc48c7
PO		 498 }
499
4489428a
PO		 500 /*
501 * JMicron chips can have two interfaces to the same hardware
502 * in order to work around limitations in Microsoft's driver.
503 * We need to make sure we only bind to one of them.
504 *
505 * This code assumes two things:
506 *
507 * 1. The PCI code adds subfunctions in order.
508 *
509 * 2. The MMC interface has a lower subfunction number
510 * than the SD interface.
511 */
8f230f45
TI		 512 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_SD)
513 mmcdev = PCI_DEVICE_ID_JMICRON_JMB38X_MMC;
514 else if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD)
515 mmcdev = PCI_DEVICE_ID_JMICRON_JMB388_ESD;
516
517 if (mmcdev) {
4489428a
PO		 518 struct pci_dev *sd_dev;
519
520 sd_dev = NULL;
521 while ((sd_dev = pci_get_device(PCI_VENDOR_ID_JMICRON,
8f230f45 522 mmcdev, sd_dev)) != NULL) {
4489428a
PO		 523 if ((PCI_SLOT(chip->pdev->devfn) ==
524 PCI_SLOT(sd_dev->devfn)) &&
525 (chip->pdev->bus == sd_dev->bus))
526 break;
527 }
528
529 if (sd_dev) {
530 pci_dev_put(sd_dev);
531 dev_info(&chip->pdev->dev, "Refusing to bind to "
532 "secondary interface.\n");
533 return -ENODEV;
534 }
535 }
536
45211e21
PO		 537 /*
538 * JMicron chips need a bit of a nudge to enable the power
539 * output pins.
540 */
541 ret = jmicron_pmos(chip, 1);
542 if (ret) {
543 dev_err(&chip->pdev->dev, "Failure enabling card power\n");
544 return ret;
545 }
546
82b0e23a
TI		 547 /* quirk for unsable RO-detection on JM388 chips */
548 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD ||
549 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD)
550 chip->quirks |= SDHCI_QUIRK_UNSTABLE_RO_DETECT;
551
45211e21
PO		 552 return 0;
553}
554
4489428a
PO		 555static void jmicron_enable_mmc(struct sdhci_host *host, int on)
556{
557 u8 scratch;
558
559 scratch = readb(host->ioaddr + 0xC0);
560
561 if (on)
562 scratch |= 0x01;
563 else
564 scratch &= ~0x01;
565
566 writeb(scratch, host->ioaddr + 0xC0);
567}
568
569static int jmicron_probe_slot(struct sdhci_pci_slot *slot)
570{
2134a922
PO		 571 if (slot->chip->pdev->revision == 0) {
572 u16 version;
573
574 version = readl(slot->host->ioaddr + SDHCI_HOST_VERSION);
575 version = (version & SDHCI_VENDOR_VER_MASK) >>
576 SDHCI_VENDOR_VER_SHIFT;
577
578 /*
579 * Older versions of the chip have lots of nasty glitches
580 * in the ADMA engine. It's best just to avoid it
581 * completely.
582 */
583 if (version < 0xAC)
584 slot->host->quirks |= SDHCI_QUIRK_BROKEN_ADMA;
585 }
586
8f230f45
TI		 587 /* JM388 MMC doesn't support 1.8V while SD supports it */
588 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) {
589 slot->host->ocr_avail_sd = MMC_VDD_32_33 | MMC_VDD_33_34 |
590 MMC_VDD_29_30 | MMC_VDD_30_31 |
591 MMC_VDD_165_195; /* allow 1.8V */
592 slot->host->ocr_avail_mmc = MMC_VDD_32_33 | MMC_VDD_33_34 |
593 MMC_VDD_29_30 | MMC_VDD_30_31; /* no 1.8V for MMC */
594 }
595
4489428a
PO		 596 /*
597 * The secondary interface requires a bit set to get the
598 * interrupts.
599 */
8f230f45
TI		 600 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
601 slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD)
4489428a
PO		 602 jmicron_enable_mmc(slot->host, 1);
603
d75c1084
TI		 604 slot->host->mmc->caps |= MMC_CAP_BUS_WIDTH_TEST;
605
4489428a
PO		 606 return 0;
607}
608
1e72859e 609static void jmicron_remove_slot(struct sdhci_pci_slot *slot, int dead)
4489428a 610{
1e72859e
PO		 611 if (dead)
612 return;
613
8f230f45
TI		 614 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
615 slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD)
4489428a
PO		 616 jmicron_enable_mmc(slot->host, 0);
617}
618
29495aa0 619static int jmicron_suspend(struct sdhci_pci_chip *chip)
4489428a
PO		 620{
621 int i;
622
8f230f45
TI		 623 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
624 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) {
b177bc91 625 for (i = 0; i < chip->num_slots; i++)
4489428a
PO		 626 jmicron_enable_mmc(chip->slots[i]->host, 0);
627 }
628
629 return 0;
630}
631
45211e21
PO		 632static int jmicron_resume(struct sdhci_pci_chip *chip)
633{
4489428a
PO		 634 int ret, i;
635
8f230f45
TI		 636 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
637 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) {
b177bc91 638 for (i = 0; i < chip->num_slots; i++)
4489428a
PO		 639 jmicron_enable_mmc(chip->slots[i]->host, 1);
640 }
45211e21
PO		 641
642 ret = jmicron_pmos(chip, 1);
643 if (ret) {
644 dev_err(&chip->pdev->dev, "Failure enabling card power\n");
645 return ret;
646 }
647
648 return 0;
649}
650
26daa1ed 651static const struct sdhci_pci_fixes sdhci_o2 = {
01acf691
AL		 652 .probe = sdhci_pci_o2_probe,
653 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
143b648d 654 .quirks2 = SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD,
01acf691
AL		 655 .probe_slot = sdhci_pci_o2_probe_slot,
656 .resume = sdhci_pci_o2_resume,
26daa1ed
JL		 657};
658
22606405 659static const struct sdhci_pci_fixes sdhci_jmicron = {
45211e21
PO		 660 .probe = jmicron_probe,
661
4489428a
PO		 662 .probe_slot = jmicron_probe_slot,
663 .remove_slot = jmicron_remove_slot,
664
665 .suspend = jmicron_suspend,
45211e21 666 .resume = jmicron_resume,
22606405
PO		 667};
668
a7a6186c
NP		 669/* SysKonnect CardBus2SDIO extra registers */
670#define SYSKT_CTRL 0x200
671#define SYSKT_RDFIFO_STAT 0x204
672#define SYSKT_WRFIFO_STAT 0x208
673#define SYSKT_POWER_DATA 0x20c
674#define SYSKT_POWER_330 0xef
675#define SYSKT_POWER_300 0xf8
676#define SYSKT_POWER_184 0xcc
677#define SYSKT_POWER_CMD 0x20d
678#define SYSKT_POWER_START (1 << 7)
679#define SYSKT_POWER_STATUS 0x20e
680#define SYSKT_POWER_STATUS_OK (1 << 0)
681#define SYSKT_BOARD_REV 0x210
682#define SYSKT_CHIP_REV 0x211
683#define SYSKT_CONF_DATA 0x212
684#define SYSKT_CONF_DATA_1V8 (1 << 2)
685#define SYSKT_CONF_DATA_2V5 (1 << 1)
686#define SYSKT_CONF_DATA_3V3 (1 << 0)
687
688static int syskt_probe(struct sdhci_pci_chip *chip)
689{
690 if ((chip->pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) {
691 chip->pdev->class &= ~0x0000FF;
692 chip->pdev->class |= PCI_SDHCI_IFDMA;
693 }
694 return 0;
695}
696
697static int syskt_probe_slot(struct sdhci_pci_slot *slot)
698{
699 int tm, ps;
700
701 u8 board_rev = readb(slot->host->ioaddr + SYSKT_BOARD_REV);
702 u8 chip_rev = readb(slot->host->ioaddr + SYSKT_CHIP_REV);
703 dev_info(&slot->chip->pdev->dev, "SysKonnect CardBus2SDIO, "
704 "board rev %d.%d, chip rev %d.%d\n",
705 board_rev >> 4, board_rev & 0xf,
706 chip_rev >> 4, chip_rev & 0xf);
707 if (chip_rev >= 0x20)
708 slot->host->quirks |= SDHCI_QUIRK_FORCE_DMA;
709
710 writeb(SYSKT_POWER_330, slot->host->ioaddr + SYSKT_POWER_DATA);
711 writeb(SYSKT_POWER_START, slot->host->ioaddr + SYSKT_POWER_CMD);
712 udelay(50);
713 tm = 10; /* Wait max 1 ms */
714 do {
715 ps = readw(slot->host->ioaddr + SYSKT_POWER_STATUS);
716 if (ps & SYSKT_POWER_STATUS_OK)
717 break;
718 udelay(100);
719 } while (--tm);
720 if (!tm) {
721 dev_err(&slot->chip->pdev->dev,
722 "power regulator never stabilized");
723 writeb(0, slot->host->ioaddr + SYSKT_POWER_CMD);
724 return -ENODEV;
725 }
726
727 return 0;
728}
729
730static const struct sdhci_pci_fixes sdhci_syskt = {
731 .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER,
732 .probe = syskt_probe,
733 .probe_slot = syskt_probe_slot,
734};
735
557b0697
HW		 736static int via_probe(struct sdhci_pci_chip *chip)
737{
738 if (chip->pdev->revision == 0x10)
739 chip->quirks |= SDHCI_QUIRK_DELAY_AFTER_POWER;
740
741 return 0;
742}
743
744static const struct sdhci_pci_fixes sdhci_via = {
745 .probe = via_probe,
746};
747
9107ebbf
MC		 748static int rtsx_probe_slot(struct sdhci_pci_slot *slot)
749{
750 slot->host->mmc->caps2 |= MMC_CAP2_HS200;
751 return 0;
752}
753
754static const struct sdhci_pci_fixes sdhci_rtsx = {
755 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
e30b978f 756 SDHCI_QUIRK2_BROKEN_64_BIT_DMA |
9107ebbf
MC		 757 SDHCI_QUIRK2_BROKEN_DDR50,
758 .probe_slot = rtsx_probe_slot,
759};
760
b5e97d6e
VW		 761/*AMD chipset generation*/
762enum amd_chipset_gen {
763 AMD_CHIPSET_BEFORE_ML,
764 AMD_CHIPSET_CZ,
765 AMD_CHIPSET_NL,
766 AMD_CHIPSET_UNKNOWN,
767};
768
d44f88da
VW		 769static int amd_probe(struct sdhci_pci_chip *chip)
770{
771 struct pci_dev *smbus_dev;
b5e97d6e 772 enum amd_chipset_gen gen;
d44f88da
VW		 773
774 smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD,
775 PCI_DEVICE_ID_AMD_HUDSON2_SMBUS, NULL);
b5e97d6e
VW		 776 if (smbus_dev) {
777 gen = AMD_CHIPSET_BEFORE_ML;
778 } else {
779 smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD,
780 PCI_DEVICE_ID_AMD_KERNCZ_SMBUS, NULL);
781 if (smbus_dev) {
782 if (smbus_dev->revision < 0x51)
783 gen = AMD_CHIPSET_CZ;
784 else
785 gen = AMD_CHIPSET_NL;
786 } else {
787 gen = AMD_CHIPSET_UNKNOWN;
788 }
789 }
d44f88da 790
b5e97d6e 791 if ((gen == AMD_CHIPSET_BEFORE_ML) || (gen == AMD_CHIPSET_CZ)) {
d44f88da 792 chip->quirks2 |= SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD;
e765bfa2
VW		 793 chip->quirks2 |= SDHCI_QUIRK2_BROKEN_HS200;
794 }
d44f88da
VW		 795
796 return 0;
797}
798
799static const struct sdhci_pci_fixes sdhci_amd = {
800 .probe = amd_probe,
801};
802
9647f84d 803static const struct pci_device_id pci_ids[] = {
b8c86fc5
PO		 804 {
805 .vendor = PCI_VENDOR_ID_RICOH,
806 .device = PCI_DEVICE_ID_RICOH_R5C822,
22606405 807 .subvendor = PCI_ANY_ID,
b8c86fc5 808 .subdevice = PCI_ANY_ID,
22606405 809 .driver_data = (kernel_ulong_t)&sdhci_ricoh,
b8c86fc5
PO		 810 },
811
ccc92c23
ML		 812 {
813 .vendor = PCI_VENDOR_ID_RICOH,
814 .device = 0x843,
815 .subvendor = PCI_ANY_ID,
816 .subdevice = PCI_ANY_ID,
817 .driver_data = (kernel_ulong_t)&sdhci_ricoh_mmc,
818 },
819
568133eb
PC		 820 {
821 .vendor = PCI_VENDOR_ID_RICOH,
822 .device = 0xe822,
823 .subvendor = PCI_ANY_ID,
824 .subdevice = PCI_ANY_ID,
825 .driver_data = (kernel_ulong_t)&sdhci_ricoh_mmc,
826 },
827
5fd11c07
MI		 828 {
829 .vendor = PCI_VENDOR_ID_RICOH,
830 .device = 0xe823,
831 .subvendor = PCI_ANY_ID,
832 .subdevice = PCI_ANY_ID,
833 .driver_data = (kernel_ulong_t)&sdhci_ricoh_mmc,
834 },
835
b8c86fc5
PO		 836 {
837 .vendor = PCI_VENDOR_ID_ENE,
838 .device = PCI_DEVICE_ID_ENE_CB712_SD,
839 .subvendor = PCI_ANY_ID,
840 .subdevice = PCI_ANY_ID,
22606405 841 .driver_data = (kernel_ulong_t)&sdhci_ene_712,
b8c86fc5
PO		 842 },
843
844 {
845 .vendor = PCI_VENDOR_ID_ENE,
846 .device = PCI_DEVICE_ID_ENE_CB712_SD_2,
847 .subvendor = PCI_ANY_ID,
848 .subdevice = PCI_ANY_ID,
22606405 849 .driver_data = (kernel_ulong_t)&sdhci_ene_712,
b8c86fc5
PO		 850 },
851
852 {
853 .vendor = PCI_VENDOR_ID_ENE,
854 .device = PCI_DEVICE_ID_ENE_CB714_SD,
855 .subvendor = PCI_ANY_ID,
856 .subdevice = PCI_ANY_ID,
22606405 857 .driver_data = (kernel_ulong_t)&sdhci_ene_714,
b8c86fc5
PO		 858 },
859
860 {
861 .vendor = PCI_VENDOR_ID_ENE,
862 .device = PCI_DEVICE_ID_ENE_CB714_SD_2,
863 .subvendor = PCI_ANY_ID,
864 .subdevice = PCI_ANY_ID,
22606405 865 .driver_data = (kernel_ulong_t)&sdhci_ene_714,
b8c86fc5
PO		 866 },
867
868 {
869 .vendor = PCI_VENDOR_ID_MARVELL,
8c5eb880 870 .device = PCI_DEVICE_ID_MARVELL_88ALP01_SD,
b8c86fc5
PO		 871 .subvendor = PCI_ANY_ID,
872 .subdevice = PCI_ANY_ID,
22606405 873 .driver_data = (kernel_ulong_t)&sdhci_cafe,
b8c86fc5
PO		 874 },
875
876 {
877 .vendor = PCI_VENDOR_ID_JMICRON,
878 .device = PCI_DEVICE_ID_JMICRON_JMB38X_SD,
879 .subvendor = PCI_ANY_ID,
880 .subdevice = PCI_ANY_ID,
22606405 881 .driver_data = (kernel_ulong_t)&sdhci_jmicron,
b8c86fc5
PO		 882 },
883
4489428a
PO		 884 {
885 .vendor = PCI_VENDOR_ID_JMICRON,
886 .device = PCI_DEVICE_ID_JMICRON_JMB38X_MMC,
887 .subvendor = PCI_ANY_ID,
888 .subdevice = PCI_ANY_ID,
889 .driver_data = (kernel_ulong_t)&sdhci_jmicron,
8f230f45
TI		 890 },
891
892 {
893 .vendor = PCI_VENDOR_ID_JMICRON,
894 .device = PCI_DEVICE_ID_JMICRON_JMB388_SD,
895 .subvendor = PCI_ANY_ID,
896 .subdevice = PCI_ANY_ID,
897 .driver_data = (kernel_ulong_t)&sdhci_jmicron,
898 },
899
900 {
901 .vendor = PCI_VENDOR_ID_JMICRON,
902 .device = PCI_DEVICE_ID_JMICRON_JMB388_ESD,
903 .subvendor = PCI_ANY_ID,
904 .subdevice = PCI_ANY_ID,
905 .driver_data = (kernel_ulong_t)&sdhci_jmicron,
4489428a
PO		 906 },
907
a7a6186c
NP		 908 {
909 .vendor = PCI_VENDOR_ID_SYSKONNECT,
910 .device = 0x8000,
911 .subvendor = PCI_ANY_ID,
912 .subdevice = PCI_ANY_ID,
913 .driver_data = (kernel_ulong_t)&sdhci_syskt,
914 },
915
557b0697
HW		 916 {
917 .vendor = PCI_VENDOR_ID_VIA,
918 .device = 0x95d0,
919 .subvendor = PCI_ANY_ID,
920 .subdevice = PCI_ANY_ID,
921 .driver_data = (kernel_ulong_t)&sdhci_via,
9107ebbf
MC		 922 },
923
924 {
925 .vendor = PCI_VENDOR_ID_REALTEK,
926 .device = 0x5250,
927 .subvendor = PCI_ANY_ID,
928 .subdevice = PCI_ANY_ID,
929 .driver_data = (kernel_ulong_t)&sdhci_rtsx,
557b0697
HW		 930 },
931
43e968ce
DB		 932 {
933 .vendor = PCI_VENDOR_ID_INTEL,
934 .device = PCI_DEVICE_ID_INTEL_QRK_SD,
935 .subvendor = PCI_ANY_ID,
936 .subdevice = PCI_ANY_ID,
937 .driver_data = (kernel_ulong_t)&sdhci_intel_qrk,
938 },
939
29229052
XS		 940 {
941 .vendor = PCI_VENDOR_ID_INTEL,
f9ee3eab
AC		 942 .device = PCI_DEVICE_ID_INTEL_MRST_SD0,
943 .subvendor = PCI_ANY_ID,
944 .subdevice = PCI_ANY_ID,
945 .driver_data = (kernel_ulong_t)&sdhci_intel_mrst_hc0,
946 },
947
948 {
949 .vendor = PCI_VENDOR_ID_INTEL,
950 .device = PCI_DEVICE_ID_INTEL_MRST_SD1,
951 .subvendor = PCI_ANY_ID,
952 .subdevice = PCI_ANY_ID,
35ac6f08
JP		 953 .driver_data = (kernel_ulong_t)&sdhci_intel_mrst_hc1_hc2,
954 },
955
956 {
957 .vendor = PCI_VENDOR_ID_INTEL,
958 .device = PCI_DEVICE_ID_INTEL_MRST_SD2,
959 .subvendor = PCI_ANY_ID,
960 .subdevice = PCI_ANY_ID,
961 .driver_data = (kernel_ulong_t)&sdhci_intel_mrst_hc1_hc2,
f9ee3eab
AC		 962 },
963
964 {
965 .vendor = PCI_VENDOR_ID_INTEL,
29229052
XS		 966 .device = PCI_DEVICE_ID_INTEL_MFD_SD,
967 .subvendor = PCI_ANY_ID,
968 .subdevice = PCI_ANY_ID,
969 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sd,
970 },
971
972 {
973 .vendor = PCI_VENDOR_ID_INTEL,
974 .device = PCI_DEVICE_ID_INTEL_MFD_SDIO1,
975 .subvendor = PCI_ANY_ID,
976 .subdevice = PCI_ANY_ID,
0d013bcf 977 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sdio,
29229052
XS		 978 },
979
980 {
981 .vendor = PCI_VENDOR_ID_INTEL,
982 .device = PCI_DEVICE_ID_INTEL_MFD_SDIO2,
983 .subvendor = PCI_ANY_ID,
984 .subdevice = PCI_ANY_ID,
0d013bcf 985 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sdio,
29229052
XS		 986 },
987
988 {
989 .vendor = PCI_VENDOR_ID_INTEL,
990 .device = PCI_DEVICE_ID_INTEL_MFD_EMMC0,
991 .subvendor = PCI_ANY_ID,
992 .subdevice = PCI_ANY_ID,
0d013bcf 993 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc,
29229052
XS		 994 },
995
996 {
997 .vendor = PCI_VENDOR_ID_INTEL,
998 .device = PCI_DEVICE_ID_INTEL_MFD_EMMC1,
999 .subvendor = PCI_ANY_ID,
1000 .subdevice = PCI_ANY_ID,
0d013bcf 1001 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc,
29229052
XS		 1002 },
1003
296e0b03
AS		 1004 {
1005 .vendor = PCI_VENDOR_ID_INTEL,
1006 .device = PCI_DEVICE_ID_INTEL_PCH_SDIO0,
1007 .subvendor = PCI_ANY_ID,
1008 .subdevice = PCI_ANY_ID,
1009 .driver_data = (kernel_ulong_t)&sdhci_intel_pch_sdio,
1010 },
1011
1012 {
1013 .vendor = PCI_VENDOR_ID_INTEL,
1014 .device = PCI_DEVICE_ID_INTEL_PCH_SDIO1,
1015 .subvendor = PCI_ANY_ID,
1016 .subdevice = PCI_ANY_ID,
1017 .driver_data = (kernel_ulong_t)&sdhci_intel_pch_sdio,
1018 },
1019
728ef3d1
AH		 1020 {
1021 .vendor = PCI_VENDOR_ID_INTEL,
1022 .device = PCI_DEVICE_ID_INTEL_BYT_EMMC,
1023 .subvendor = PCI_ANY_ID,
1024 .subdevice = PCI_ANY_ID,
1025 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc,
1026 },
1027
1028 {
1029 .vendor = PCI_VENDOR_ID_INTEL,
1030 .device = PCI_DEVICE_ID_INTEL_BYT_SDIO,
1031 .subvendor = PCI_ANY_ID,
1032 .subdevice = PCI_ANY_ID,
1033 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio,
1034 },
1035
1036 {
1037 .vendor = PCI_VENDOR_ID_INTEL,
1038 .device = PCI_DEVICE_ID_INTEL_BYT_SD,
1039 .subvendor = PCI_ANY_ID,
1040 .subdevice = PCI_ANY_ID,
1041 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd,
1042 },
1043
30d025c0
AH		 1044 {
1045 .vendor = PCI_VENDOR_ID_INTEL,
1046 .device = PCI_DEVICE_ID_INTEL_BYT_EMMC2,
1047 .subvendor = PCI_ANY_ID,
1048 .subdevice = PCI_ANY_ID,
1049 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc,
1050 },
1051
066173b6
AC		 1052 {
1053 .vendor = PCI_VENDOR_ID_INTEL,
1054 .device = PCI_DEVICE_ID_INTEL_BSW_EMMC,
1055 .subvendor = PCI_ANY_ID,
1056 .subdevice = PCI_ANY_ID,
1057 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc,
1058 },
1059
1060 {
1061 .vendor = PCI_VENDOR_ID_INTEL,
1062 .device = PCI_DEVICE_ID_INTEL_BSW_SDIO,
1063 .subvendor = PCI_ANY_ID,
1064 .subdevice = PCI_ANY_ID,
1065 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio,
1066 },
1067
1068 {
1069 .vendor = PCI_VENDOR_ID_INTEL,
1070 .device = PCI_DEVICE_ID_INTEL_BSW_SD,
1071 .subvendor = PCI_ANY_ID,
1072 .subdevice = PCI_ANY_ID,
1073 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd,
1074 },
d052068a
EE		 1075
1076 {
1077 .vendor = PCI_VENDOR_ID_INTEL,
1078 .device = PCI_DEVICE_ID_INTEL_CLV_SDIO0,
1079 .subvendor = PCI_ANY_ID,
1080 .subdevice = PCI_ANY_ID,
1081 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sd,
1082 },
1083
1084 {
1085 .vendor = PCI_VENDOR_ID_INTEL,
1086 .device = PCI_DEVICE_ID_INTEL_CLV_SDIO1,
1087 .subvendor = PCI_ANY_ID,
1088 .subdevice = PCI_ANY_ID,
1089 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sdio,
1090 },
1091
1092 {
1093 .vendor = PCI_VENDOR_ID_INTEL,
1094 .device = PCI_DEVICE_ID_INTEL_CLV_SDIO2,
1095 .subvendor = PCI_ANY_ID,
1096 .subdevice = PCI_ANY_ID,
1097 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sdio,
1098 },
1099
1100 {
1101 .vendor = PCI_VENDOR_ID_INTEL,
1102 .device = PCI_DEVICE_ID_INTEL_CLV_EMMC0,
1103 .subvendor = PCI_ANY_ID,
1104 .subdevice = PCI_ANY_ID,
1105 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc,
1106 },
1107
1108 {
1109 .vendor = PCI_VENDOR_ID_INTEL,
1110 .device = PCI_DEVICE_ID_INTEL_CLV_EMMC1,
1111 .subvendor = PCI_ANY_ID,
1112 .subdevice = PCI_ANY_ID,
1113 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc,
1114 },
1115
8776a165
DC		 1116 {
1117 .vendor = PCI_VENDOR_ID_INTEL,
1f64cec2 1118 .device = PCI_DEVICE_ID_INTEL_MRFLD_MMC,
8776a165
DC		 1119 .subvendor = PCI_ANY_ID,
1120 .subdevice = PCI_ANY_ID,
1f64cec2 1121 .driver_data = (kernel_ulong_t)&sdhci_intel_mrfld_mmc,
8776a165 1122 },
1f7f2652
AH		 1123
1124 {
1125 .vendor = PCI_VENDOR_ID_INTEL,
1126 .device = PCI_DEVICE_ID_INTEL_SPT_EMMC,
1127 .subvendor = PCI_ANY_ID,
1128 .subdevice = PCI_ANY_ID,
1129 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc,
1130 },
1131
1132 {
1133 .vendor = PCI_VENDOR_ID_INTEL,
1134 .device = PCI_DEVICE_ID_INTEL_SPT_SDIO,
1135 .subvendor = PCI_ANY_ID,
1136 .subdevice = PCI_ANY_ID,
1137 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio,
1138 },
1139
1140 {
1141 .vendor = PCI_VENDOR_ID_INTEL,
1142 .device = PCI_DEVICE_ID_INTEL_SPT_SD,
1143 .subvendor = PCI_ANY_ID,
1144 .subdevice = PCI_ANY_ID,
1145 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd,
1146 },
1147
06bf9c56
AH		 1148 {
1149 .vendor = PCI_VENDOR_ID_INTEL,
1150 .device = PCI_DEVICE_ID_INTEL_DNV_EMMC,
1151 .subvendor = PCI_ANY_ID,
1152 .subdevice = PCI_ANY_ID,
1153 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc,
1154 },
1155
4fd4c065
AH		 1156 {
1157 .vendor = PCI_VENDOR_ID_INTEL,
1158 .device = PCI_DEVICE_ID_INTEL_BXT_EMMC,
1159 .subvendor = PCI_ANY_ID,
1160 .subdevice = PCI_ANY_ID,
1161 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc,
1162 },
1163
1164 {
1165 .vendor = PCI_VENDOR_ID_INTEL,
1166 .device = PCI_DEVICE_ID_INTEL_BXT_SDIO,
1167 .subvendor = PCI_ANY_ID,
1168 .subdevice = PCI_ANY_ID,
1169 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio,
1170 },
1171
1172 {
1173 .vendor = PCI_VENDOR_ID_INTEL,
1174 .device = PCI_DEVICE_ID_INTEL_BXT_SD,
1175 .subvendor = PCI_ANY_ID,
1176 .subdevice = PCI_ANY_ID,
1177 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd,
1178 },
1179
01d6b2a4
AH		 1180 {
1181 .vendor = PCI_VENDOR_ID_INTEL,
1182 .device = PCI_DEVICE_ID_INTEL_BXTM_EMMC,
1183 .subvendor = PCI_ANY_ID,
1184 .subdevice = PCI_ANY_ID,
1185 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc,
1186 },
1187
1188 {
1189 .vendor = PCI_VENDOR_ID_INTEL,
1190 .device = PCI_DEVICE_ID_INTEL_BXTM_SDIO,
1191 .subvendor = PCI_ANY_ID,
1192 .subdevice = PCI_ANY_ID,
1193 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio,
1194 },
1195
1196 {
1197 .vendor = PCI_VENDOR_ID_INTEL,
1198 .device = PCI_DEVICE_ID_INTEL_BXTM_SD,
1199 .subvendor = PCI_ANY_ID,
1200 .subdevice = PCI_ANY_ID,
1201 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd,
1202 },
1203
4fd4c065
AH		 1204 {
1205 .vendor = PCI_VENDOR_ID_INTEL,
1206 .device = PCI_DEVICE_ID_INTEL_APL_EMMC,
1207 .subvendor = PCI_ANY_ID,
1208 .subdevice = PCI_ANY_ID,
1209 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc,
1210 },
1211
1212 {
1213 .vendor = PCI_VENDOR_ID_INTEL,
1214 .device = PCI_DEVICE_ID_INTEL_APL_SDIO,
1215 .subvendor = PCI_ANY_ID,
1216 .subdevice = PCI_ANY_ID,
1217 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio,
1218 },
1219
1220 {
1221 .vendor = PCI_VENDOR_ID_INTEL,
1222 .device = PCI_DEVICE_ID_INTEL_APL_SD,
1223 .subvendor = PCI_ANY_ID,
1224 .subdevice = PCI_ANY_ID,
1225 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd,
1226 },
1227
26daa1ed
JL		 1228 {
1229 .vendor = PCI_VENDOR_ID_O2,
1230 .device = PCI_DEVICE_ID_O2_8120,
1231 .subvendor = PCI_ANY_ID,
1232 .subdevice = PCI_ANY_ID,
1233 .driver_data = (kernel_ulong_t)&sdhci_o2,
1234 },
1235
1236 {
1237 .vendor = PCI_VENDOR_ID_O2,
1238 .device = PCI_DEVICE_ID_O2_8220,
1239 .subvendor = PCI_ANY_ID,
1240 .subdevice = PCI_ANY_ID,
1241 .driver_data = (kernel_ulong_t)&sdhci_o2,
1242 },
1243
1244 {
1245 .vendor = PCI_VENDOR_ID_O2,
1246 .device = PCI_DEVICE_ID_O2_8221,
1247 .subvendor = PCI_ANY_ID,
1248 .subdevice = PCI_ANY_ID,
1249 .driver_data = (kernel_ulong_t)&sdhci_o2,
1250 },
1251
1252 {
1253 .vendor = PCI_VENDOR_ID_O2,
1254 .device = PCI_DEVICE_ID_O2_8320,
1255 .subvendor = PCI_ANY_ID,
1256 .subdevice = PCI_ANY_ID,
1257 .driver_data = (kernel_ulong_t)&sdhci_o2,
1258 },
1259
1260 {
1261 .vendor = PCI_VENDOR_ID_O2,
1262 .device = PCI_DEVICE_ID_O2_8321,
1263 .subvendor = PCI_ANY_ID,
1264 .subdevice = PCI_ANY_ID,
1265 .driver_data = (kernel_ulong_t)&sdhci_o2,
1266 },
1267
01acf691
AL		 1268 {
1269 .vendor = PCI_VENDOR_ID_O2,
1270 .device = PCI_DEVICE_ID_O2_FUJIN2,
1271 .subvendor = PCI_ANY_ID,
1272 .subdevice = PCI_ANY_ID,
1273 .driver_data = (kernel_ulong_t)&sdhci_o2,
1274 },
1275
1276 {
1277 .vendor = PCI_VENDOR_ID_O2,
1278 .device = PCI_DEVICE_ID_O2_SDS0,
1279 .subvendor = PCI_ANY_ID,
1280 .subdevice = PCI_ANY_ID,
1281 .driver_data = (kernel_ulong_t)&sdhci_o2,
1282 },
1283
1284 {
1285 .vendor = PCI_VENDOR_ID_O2,
1286 .device = PCI_DEVICE_ID_O2_SDS1,
1287 .subvendor = PCI_ANY_ID,
1288 .subdevice = PCI_ANY_ID,
1289 .driver_data = (kernel_ulong_t)&sdhci_o2,
1290 },
1291
1292 {
1293 .vendor = PCI_VENDOR_ID_O2,
1294 .device = PCI_DEVICE_ID_O2_SEABIRD0,
1295 .subvendor = PCI_ANY_ID,
1296 .subdevice = PCI_ANY_ID,
1297 .driver_data = (kernel_ulong_t)&sdhci_o2,
1298 },
1299
1300 {
1301 .vendor = PCI_VENDOR_ID_O2,
1302 .device = PCI_DEVICE_ID_O2_SEABIRD1,
1303 .subvendor = PCI_ANY_ID,
1304 .subdevice = PCI_ANY_ID,
1305 .driver_data = (kernel_ulong_t)&sdhci_o2,
1306 },
d44f88da
VW		 1307 {
1308 .vendor = PCI_VENDOR_ID_AMD,
1309 .device = PCI_ANY_ID,
1310 .class = PCI_CLASS_SYSTEM_SDHCI << 8,
1311 .class_mask = 0xFFFF00,
1312 .subvendor = PCI_ANY_ID,
1313 .subdevice = PCI_ANY_ID,
1314 .driver_data = (kernel_ulong_t)&sdhci_amd,
1315 },
b8c86fc5
PO		 1316 { /* Generic SD host controller */
1317 PCI_DEVICE_CLASS((PCI_CLASS_SYSTEM_SDHCI << 8), 0xFFFF00)
1318 },
1319
1320 { /* end: all zeroes */ },
1321};
1322
1323MODULE_DEVICE_TABLE(pci, pci_ids);
1324
b8c86fc5
PO		 1325/*****************************************************************************\
1326 * *
1327 * SDHCI core callbacks *
1328 * *
1329\*****************************************************************************/
1330
1331static int sdhci_pci_enable_dma(struct sdhci_host *host)
1332{
1333 struct sdhci_pci_slot *slot;
1334 struct pci_dev *pdev;
b8c86fc5
PO		 1335
1336 slot = sdhci_priv(host);
1337 pdev = slot->chip->pdev;
1338
1339 if (((pdev->class & 0xFFFF00) == (PCI_CLASS_SYSTEM_SDHCI << 8)) &&
1340 ((pdev->class & 0x0000FF) != PCI_SDHCI_IFDMA) &&
a13abc7b 1341 (host->flags & SDHCI_USE_SDMA)) {
b8c86fc5
PO		 1342 dev_warn(&pdev->dev, "Will use DMA mode even though HW "
1343 "doesn't fully claim to support it.\n");
1344 }
1345
b8c86fc5
PO		 1346 pci_set_master(pdev);
1347
1348 return 0;
1349}
1350
2317f56c 1351static void sdhci_pci_set_bus_width(struct sdhci_host *host, int width)
68077b02
ML		 1352{
1353 u8 ctrl;
1354
1355 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1356
1357 switch (width) {
1358 case MMC_BUS_WIDTH_8:
1359 ctrl |= SDHCI_CTRL_8BITBUS;
1360 ctrl &= ~SDHCI_CTRL_4BITBUS;
1361 break;
1362 case MMC_BUS_WIDTH_4:
1363 ctrl |= SDHCI_CTRL_4BITBUS;
1364 ctrl &= ~SDHCI_CTRL_8BITBUS;
1365 break;
1366 default:
1367 ctrl &= ~(SDHCI_CTRL_8BITBUS | SDHCI_CTRL_4BITBUS);
1368 break;
1369 }
1370
1371 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
68077b02
ML		 1372}
1373
c9faff6c 1374static void sdhci_pci_gpio_hw_reset(struct sdhci_host *host)
0f201655
AH		 1375{
1376 struct sdhci_pci_slot *slot = sdhci_priv(host);
1377 int rst_n_gpio = slot->rst_n_gpio;
1378
1379 if (!gpio_is_valid(rst_n_gpio))
1380 return;
1381 gpio_set_value_cansleep(rst_n_gpio, 0);
1382 /* For eMMC, minimum is 1us but give it 10us for good measure */
1383 udelay(10);
1384 gpio_set_value_cansleep(rst_n_gpio, 1);
1385 /* For eMMC, minimum is 200us but give it 300us for good measure */
1386 usleep_range(300, 1000);
1387}
1388
c9faff6c
AH		 1389static void sdhci_pci_hw_reset(struct sdhci_host *host)
1390{
1391 struct sdhci_pci_slot *slot = sdhci_priv(host);
1392
1393 if (slot->hw_reset)
1394 slot->hw_reset(host);
1395}
1396
e1bfad6d
AH		 1397static int sdhci_pci_select_drive_strength(struct sdhci_host *host,
1398 struct mmc_card *card,
1399 unsigned int max_dtr, int host_drv,
1400 int card_drv, int *drv_type)
1401{
1402 struct sdhci_pci_slot *slot = sdhci_priv(host);
1403
1404 if (!slot->select_drive_strength)
1405 return 0;
1406
1407 return slot->select_drive_strength(host, card, max_dtr, host_drv,
1408 card_drv, drv_type);
1409}
1410
c915568d 1411static const struct sdhci_ops sdhci_pci_ops = {
1771059c 1412 .set_clock = sdhci_set_clock,
b8c86fc5 1413 .enable_dma = sdhci_pci_enable_dma,
2317f56c 1414 .set_bus_width = sdhci_pci_set_bus_width,
03231f9b 1415 .reset = sdhci_reset,
96d7b78c 1416 .set_uhs_signaling = sdhci_set_uhs_signaling,
0f201655 1417 .hw_reset = sdhci_pci_hw_reset,
e1bfad6d 1418 .select_drive_strength = sdhci_pci_select_drive_strength,
b8c86fc5
PO		 1419};
1420
1421/*****************************************************************************\
1422 * *
1423 * Suspend/resume *
1424 * *
1425\*****************************************************************************/
1426
f9900f15 1427#ifdef CONFIG_PM_SLEEP
29495aa0 1428static int sdhci_pci_suspend(struct device *dev)
b8c86fc5 1429{
29495aa0 1430 struct pci_dev *pdev = to_pci_dev(dev);
b8c86fc5
PO		 1431 struct sdhci_pci_chip *chip;
1432 struct sdhci_pci_slot *slot;
5f619704 1433 mmc_pm_flag_t slot_pm_flags;
2f4cbb3d 1434 mmc_pm_flag_t pm_flags = 0;
b8c86fc5
PO		 1435 int i, ret;
1436
1437 chip = pci_get_drvdata(pdev);
1438 if (!chip)
1439 return 0;
1440
b177bc91 1441 for (i = 0; i < chip->num_slots; i++) {
b8c86fc5
PO		 1442 slot = chip->slots[i];
1443 if (!slot)
1444 continue;
1445
29495aa0 1446 ret = sdhci_suspend_host(slot->host);
b8c86fc5 1447
b678b91f
AL		 1448 if (ret)
1449 goto err_pci_suspend;
2f4cbb3d 1450
5f619704
DD		 1451 slot_pm_flags = slot->host->mmc->pm_flags;
1452 if (slot_pm_flags & MMC_PM_WAKE_SDIO_IRQ)
1453 sdhci_enable_irq_wakeups(slot->host);
1454
1455 pm_flags |= slot_pm_flags;
b8c86fc5
PO		 1456 }
1457
4489428a 1458 if (chip->fixes && chip->fixes->suspend) {
29495aa0 1459 ret = chip->fixes->suspend(chip);
b678b91f
AL		 1460 if (ret)
1461 goto err_pci_suspend;
4489428a
PO		 1462 }
1463
2f4cbb3d 1464 if (pm_flags & MMC_PM_KEEP_POWER) {
6b91f2d4
CD		 1465 if (pm_flags & MMC_PM_WAKE_SDIO_IRQ)
1466 device_init_wakeup(dev, true);
1467 else
1468 device_init_wakeup(dev, false);
1469 } else
1470 device_init_wakeup(dev, false);
b8c86fc5
PO		 1471
1472 return 0;
b678b91f
AL		 1473
1474err_pci_suspend:
1475 while (--i >= 0)
1476 sdhci_resume_host(chip->slots[i]->host);
1477 return ret;
b8c86fc5
PO		 1478}
1479
29495aa0 1480static int sdhci_pci_resume(struct device *dev)
b8c86fc5 1481{
29495aa0 1482 struct pci_dev *pdev = to_pci_dev(dev);
b8c86fc5
PO		 1483 struct sdhci_pci_chip *chip;
1484 struct sdhci_pci_slot *slot;
1485 int i, ret;
1486
1487 chip = pci_get_drvdata(pdev);
1488 if (!chip)
1489 return 0;
1490
45211e21
PO		 1491 if (chip->fixes && chip->fixes->resume) {
1492 ret = chip->fixes->resume(chip);
1493 if (ret)
1494 return ret;
1495 }
1496
b177bc91 1497 for (i = 0; i < chip->num_slots; i++) {
b8c86fc5
PO		 1498 slot = chip->slots[i];
1499 if (!slot)
1500 continue;
1501
1502 ret = sdhci_resume_host(slot->host);
1503 if (ret)
1504 return ret;
1505 }
1506
1507 return 0;
1508}
f9900f15 1509#endif
b8c86fc5 1510
f9900f15 1511#ifdef CONFIG_PM
66fd8ad5
AH		 1512static int sdhci_pci_runtime_suspend(struct device *dev)
1513{
923a231c 1514 struct pci_dev *pdev = to_pci_dev(dev);
66fd8ad5
AH		 1515 struct sdhci_pci_chip *chip;
1516 struct sdhci_pci_slot *slot;
66fd8ad5
AH		 1517 int i, ret;
1518
1519 chip = pci_get_drvdata(pdev);
1520 if (!chip)
1521 return 0;
1522
1523 for (i = 0; i < chip->num_slots; i++) {
1524 slot = chip->slots[i];
1525 if (!slot)
1526 continue;
1527
1528 ret = sdhci_runtime_suspend_host(slot->host);
1529
b678b91f
AL		 1530 if (ret)
1531 goto err_pci_runtime_suspend;
66fd8ad5
AH		 1532 }
1533
1534 if (chip->fixes && chip->fixes->suspend) {
29495aa0 1535 ret = chip->fixes->suspend(chip);
b678b91f
AL		 1536 if (ret)
1537 goto err_pci_runtime_suspend;
66fd8ad5
AH		 1538 }
1539
1540 return 0;
b678b91f
AL		 1541
1542err_pci_runtime_suspend:
1543 while (--i >= 0)
1544 sdhci_runtime_resume_host(chip->slots[i]->host);
1545 return ret;
66fd8ad5
AH		 1546}
1547
1548static int sdhci_pci_runtime_resume(struct device *dev)
1549{
923a231c 1550 struct pci_dev *pdev = to_pci_dev(dev);
66fd8ad5
AH		 1551 struct sdhci_pci_chip *chip;
1552 struct sdhci_pci_slot *slot;
1553 int i, ret;
1554
1555 chip = pci_get_drvdata(pdev);
1556 if (!chip)
1557 return 0;
1558
1559 if (chip->fixes && chip->fixes->resume) {
1560 ret = chip->fixes->resume(chip);
1561 if (ret)
1562 return ret;
1563 }
1564
1565 for (i = 0; i < chip->num_slots; i++) {
1566 slot = chip->slots[i];
1567 if (!slot)
1568 continue;
1569
1570 ret = sdhci_runtime_resume_host(slot->host);
1571 if (ret)
1572 return ret;
1573 }
1574
1575 return 0;
1576}
f9900f15 1577#endif
66fd8ad5
AH		 1578
1579static const struct dev_pm_ops sdhci_pci_pm_ops = {
f9900f15 1580 SET_SYSTEM_SLEEP_PM_OPS(sdhci_pci_suspend, sdhci_pci_resume)
f3a92b1a 1581 SET_RUNTIME_PM_OPS(sdhci_pci_runtime_suspend,
106276bb 1582 sdhci_pci_runtime_resume, NULL)
66fd8ad5
AH		 1583};
1584
b8c86fc5
PO		 1585/*****************************************************************************\
1586 * *
1587 * Device probing/removal *
1588 * *
1589\*****************************************************************************/
1590
c3be1efd 1591static struct sdhci_pci_slot *sdhci_pci_probe_slot(
52c506f0
AH		 1592 struct pci_dev *pdev, struct sdhci_pci_chip *chip, int first_bar,
1593 int slotno)
b8c86fc5
PO		 1594{
1595 struct sdhci_pci_slot *slot;
1596 struct sdhci_host *host;
52c506f0 1597 int ret, bar = first_bar + slotno;
b8c86fc5
PO		 1598
1599 if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) {
1600 dev_err(&pdev->dev, "BAR %d is not iomem. Aborting.\n", bar);
1601 return ERR_PTR(-ENODEV);
1602 }
1603
90b3e6c5 1604 if (pci_resource_len(pdev, bar) < 0x100) {
b8c86fc5
PO		 1605 dev_err(&pdev->dev, "Invalid iomem size. You may "
1606 "experience problems.\n");
1607 }
1608
1609 if ((pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) {
1610 dev_err(&pdev->dev, "Vendor specific interface. Aborting.\n");
1611 return ERR_PTR(-ENODEV);
1612 }
1613
1614 if ((pdev->class & 0x0000FF) > PCI_SDHCI_IFVENDOR) {
1615 dev_err(&pdev->dev, "Unknown interface. Aborting.\n");
1616 return ERR_PTR(-ENODEV);
1617 }
1618
1619 host = sdhci_alloc_host(&pdev->dev, sizeof(struct sdhci_pci_slot));
1620 if (IS_ERR(host)) {
c60a32cd 1621 dev_err(&pdev->dev, "cannot allocate host\n");
dc0fd7b5 1622 return ERR_CAST(host);
b8c86fc5
PO		 1623 }
1624
1625 slot = sdhci_priv(host);
1626
1627 slot->chip = chip;
1628 slot->host = host;
0f201655 1629 slot->rst_n_gpio = -EINVAL;
c5e027a4 1630 slot->cd_gpio = -EINVAL;
ff59c520 1631 slot->cd_idx = -1;
b8c86fc5 1632
52c506f0
AH		 1633 /* Retrieve platform data if there is any */
1634 if (*sdhci_pci_get_data)
1635 slot->data = sdhci_pci_get_data(pdev, slotno);
1636
1637 if (slot->data) {
1638 if (slot->data->setup) {
1639 ret = slot->data->setup(slot->data);
1640 if (ret) {
1641 dev_err(&pdev->dev, "platform setup failed\n");
1642 goto free;
1643 }
1644 }
c5e027a4
AH		 1645 slot->rst_n_gpio = slot->data->rst_n_gpio;
1646 slot->cd_gpio = slot->data->cd_gpio;
52c506f0
AH		 1647 }
1648
b8c86fc5
PO		 1649 host->hw_name = "PCI";
1650 host->ops = &sdhci_pci_ops;
1651 host->quirks = chip->quirks;
f3c55a7b 1652 host->quirks2 = chip->quirks2;
b8c86fc5
PO		 1653
1654 host->irq = pdev->irq;
1655
c10bc372 1656 ret = pcim_iomap_regions(pdev, BIT(bar), mmc_hostname(host->mmc));
b8c86fc5
PO		 1657 if (ret) {
1658 dev_err(&pdev->dev, "cannot request region\n");
52c506f0 1659 goto cleanup;
b8c86fc5
PO		 1660 }
1661
c10bc372 1662 host->ioaddr = pcim_iomap_table(pdev)[bar];
b8c86fc5 1663
4489428a
PO		 1664 if (chip->fixes && chip->fixes->probe_slot) {
1665 ret = chip->fixes->probe_slot(slot);
1666 if (ret)
c10bc372 1667 goto cleanup;
4489428a
PO		 1668 }
1669
c5e027a4 1670 if (gpio_is_valid(slot->rst_n_gpio)) {
c10bc372 1671 if (!devm_gpio_request(&pdev->dev, slot->rst_n_gpio, "eMMC_reset")) {
c5e027a4
AH		 1672 gpio_direction_output(slot->rst_n_gpio, 1);
1673 slot->host->mmc->caps |= MMC_CAP_HW_RESET;
c9faff6c 1674 slot->hw_reset = sdhci_pci_gpio_hw_reset;
c5e027a4
AH		 1675 } else {
1676 dev_warn(&pdev->dev, "failed to request rst_n_gpio\n");
1677 slot->rst_n_gpio = -EINVAL;
1678 }
1679 }
1680
2f4cbb3d 1681 host->mmc->pm_caps = MMC_PM_KEEP_POWER | MMC_PM_WAKE_SDIO_IRQ;
eed222ac 1682 host->mmc->slotno = slotno;
a08b17be 1683 host->mmc->caps2 |= MMC_CAP2_NO_PRESCAN_POWERUP;
2f4cbb3d 1684
ff59c520
AH		 1685 if (slot->cd_idx >= 0 &&
1686 mmc_gpiod_request_cd(host->mmc, slot->cd_con_id, slot->cd_idx,
1687 slot->cd_override_level, 0, NULL)) {
1688 dev_warn(&pdev->dev, "failed to setup card detect gpio\n");
1689 slot->cd_idx = -1;
1690 }
1691
b8c86fc5
PO		 1692 ret = sdhci_add_host(host);
1693 if (ret)
4489428a 1694 goto remove;
b8c86fc5 1695
c5e027a4
AH		 1696 sdhci_pci_add_own_cd(slot);
1697
77a0122e
AH		 1698 /*
1699 * Check if the chip needs a separate GPIO for card detect to wake up
1700 * from runtime suspend. If it is not there, don't allow runtime PM.
1701 * Note sdhci_pci_add_own_cd() sets slot->cd_gpio to -EINVAL on failure.
1702 */
945be38c 1703 if (chip->fixes && chip->fixes->own_cd_for_runtime_pm &&
ff59c520 1704 !gpio_is_valid(slot->cd_gpio) && slot->cd_idx < 0)
77a0122e
AH		 1705 chip->allow_runtime_pm = false;
1706
b8c86fc5
PO		 1707 return slot;
1708
4489428a
PO		 1709remove:
1710 if (chip->fixes && chip->fixes->remove_slot)
1e72859e 1711 chip->fixes->remove_slot(slot, 0);
4489428a 1712
52c506f0
AH		 1713cleanup:
1714 if (slot->data && slot->data->cleanup)
1715 slot->data->cleanup(slot->data);
1716
c60a32cd 1717free:
b8c86fc5
PO		 1718 sdhci_free_host(host);
1719
1720 return ERR_PTR(ret);
1721}
1722
1723static void sdhci_pci_remove_slot(struct sdhci_pci_slot *slot)
1724{
1e72859e
PO		 1725 int dead;
1726 u32 scratch;
1727
c5e027a4
AH		 1728 sdhci_pci_remove_own_cd(slot);
1729
1e72859e
PO		 1730 dead = 0;
1731 scratch = readl(slot->host->ioaddr + SDHCI_INT_STATUS);
1732 if (scratch == (u32)-1)
1733 dead = 1;
1734
1735 sdhci_remove_host(slot->host, dead);
4489428a
PO		 1736
1737 if (slot->chip->fixes && slot->chip->fixes->remove_slot)
1e72859e 1738 slot->chip->fixes->remove_slot(slot, dead);
4489428a 1739
52c506f0
AH		 1740 if (slot->data && slot->data->cleanup)
1741 slot->data->cleanup(slot->data);
1742
b8c86fc5
PO		 1743 sdhci_free_host(slot->host);
1744}
1745
c3be1efd 1746static void sdhci_pci_runtime_pm_allow(struct device *dev)
66fd8ad5 1747{
00884b61 1748 pm_suspend_ignore_children(dev, 1);
66fd8ad5
AH		 1749 pm_runtime_set_autosuspend_delay(dev, 50);
1750 pm_runtime_use_autosuspend(dev);
00884b61
AH		 1751 pm_runtime_allow(dev);
1752 /* Stay active until mmc core scans for a card */
1753 pm_runtime_put_noidle(dev);
66fd8ad5
AH		 1754}
1755
6e0ee714 1756static void sdhci_pci_runtime_pm_forbid(struct device *dev)
66fd8ad5
AH		 1757{
1758 pm_runtime_forbid(dev);
1759 pm_runtime_get_noresume(dev);
1760}
1761
c3be1efd 1762static int sdhci_pci_probe(struct pci_dev *pdev,
b8c86fc5
PO		 1763 const struct pci_device_id *ent)
1764{
1765 struct sdhci_pci_chip *chip;
1766 struct sdhci_pci_slot *slot;
1767
cf5e23e1 1768 u8 slots, first_bar;
b8c86fc5
PO		 1769 int ret, i;
1770
1771 BUG_ON(pdev == NULL);
1772 BUG_ON(ent == NULL);
1773
b8c86fc5 1774 dev_info(&pdev->dev, "SDHCI controller found [%04x:%04x] (rev %x)\n",
cf5e23e1 1775 (int)pdev->vendor, (int)pdev->device, (int)pdev->revision);
b8c86fc5
PO		 1776
1777 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &slots);
1778 if (ret)
1779 return ret;
1780
1781 slots = PCI_SLOT_INFO_SLOTS(slots) + 1;
1782 dev_dbg(&pdev->dev, "found %d slot(s)\n", slots);
1783 if (slots == 0)
1784 return -ENODEV;
1785
1786 BUG_ON(slots > MAX_SLOTS);
1787
1788 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &first_bar);
1789 if (ret)
1790 return ret;
1791
1792 first_bar &= PCI_SLOT_INFO_FIRST_BAR_MASK;
1793
1794 if (first_bar > 5) {
1795 dev_err(&pdev->dev, "Invalid first BAR. Aborting.\n");
1796 return -ENODEV;
1797 }
1798
52ac7acf 1799 ret = pcim_enable_device(pdev);
b8c86fc5
PO		 1800 if (ret)
1801 return ret;
1802
52ac7acf
AS		 1803 chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL);
1804 if (!chip)
1805 return -ENOMEM;
b8c86fc5
PO		 1806
1807 chip->pdev = pdev;
b177bc91 1808 chip->fixes = (const struct sdhci_pci_fixes *)ent->driver_data;
c43fd774 1809 if (chip->fixes) {
22606405 1810 chip->quirks = chip->fixes->quirks;
f3c55a7b 1811 chip->quirks2 = chip->fixes->quirks2;
c43fd774
AH		 1812 chip->allow_runtime_pm = chip->fixes->allow_runtime_pm;
1813 }
b8c86fc5
PO		 1814 chip->num_slots = slots;
1815
1816 pci_set_drvdata(pdev, chip);
1817
22606405
PO		 1818 if (chip->fixes && chip->fixes->probe) {
1819 ret = chip->fixes->probe(chip);
1820 if (ret)
52ac7acf 1821 return ret;
22606405
PO		 1822 }
1823
225d85fe
AC		 1824 slots = chip->num_slots; /* Quirk may have changed this */
1825
b177bc91 1826 for (i = 0; i < slots; i++) {
52c506f0 1827 slot = sdhci_pci_probe_slot(pdev, chip, first_bar, i);
b8c86fc5 1828 if (IS_ERR(slot)) {
b177bc91 1829 for (i--; i >= 0; i--)
b8c86fc5 1830 sdhci_pci_remove_slot(chip->slots[i]);
52ac7acf 1831 return PTR_ERR(slot);
b8c86fc5
PO		 1832 }
1833
1834 chip->slots[i] = slot;
1835 }
1836
c43fd774
AH		 1837 if (chip->allow_runtime_pm)
1838 sdhci_pci_runtime_pm_allow(&pdev->dev);
66fd8ad5 1839
b8c86fc5 1840 return 0;
b8c86fc5
PO		 1841}
1842
6e0ee714 1843static void sdhci_pci_remove(struct pci_dev *pdev)
b8c86fc5
PO		 1844{
1845 int i;
52ac7acf 1846 struct sdhci_pci_chip *chip = pci_get_drvdata(pdev);
c43fd774 1847
52ac7acf
AS		 1848 if (chip->allow_runtime_pm)
1849 sdhci_pci_runtime_pm_forbid(&pdev->dev);
b8c86fc5 1850
52ac7acf
AS		 1851 for (i = 0; i < chip->num_slots; i++)
1852 sdhci_pci_remove_slot(chip->slots[i]);
b8c86fc5
PO		 1853}
1854
1855static struct pci_driver sdhci_driver = {
b177bc91 1856 .name = "sdhci-pci",
b8c86fc5 1857 .id_table = pci_ids,
b177bc91 1858 .probe = sdhci_pci_probe,
0433c143 1859 .remove = sdhci_pci_remove,
66fd8ad5
AH		 1860 .driver = {
1861 .pm = &sdhci_pci_pm_ops
1862 },
b8c86fc5
PO		 1863};
1864
acc69646 1865module_pci_driver(sdhci_driver);
b8c86fc5 1866
32710e8f 1867MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
b8c86fc5
PO		 1868MODULE_DESCRIPTION("Secure Digital Host Controller Interface PCI driver");
1869MODULE_LICENSE("GPL");
Ubuntu Eoan Linux kernel mirror