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[mirror_ubuntu-eoan-kernel.git] / drivers / mmc / host / sdhci-pci-core.c
CommitLineData
2874c5fd 1// SPDX-License-Identifier: GPL-2.0-or-later
b8c86fc5
PO		 2/* linux/drivers/mmc/host/sdhci-pci.c - SDHCI on PCI bus interface
3 *
4 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
5 *
b8c86fc5
PO		 6 * Thanks to the following companies for their support:
7 *
8 * - JMicron (hardware and technical support)
9 */
10
5305ec6a 11#include <linux/bitfield.h>
a72016a4 12#include <linux/string.h>
b8c86fc5
PO		 13#include <linux/delay.h>
14#include <linux/highmem.h>
88b47679 15#include <linux/module.h>
b8c86fc5
PO		 16#include <linux/pci.h>
17#include <linux/dma-mapping.h>
5a0e3ad6 18#include <linux/slab.h>
ccc92c23 19#include <linux/device.h>
b8c86fc5 20#include <linux/mmc/host.h>
e1bfad6d 21#include <linux/mmc/mmc.h>
b177bc91
AP		 22#include <linux/scatterlist.h>
23#include <linux/io.h>
0f201655 24#include <linux/gpio.h>
66fd8ad5 25#include <linux/pm_runtime.h>
ff59c520 26#include <linux/mmc/slot-gpio.h>
52c506f0 27#include <linux/mmc/sdhci-pci-data.h>
3f23df72 28#include <linux/acpi.h>
b8c86fc5 29
0a49a619
AH		 30#ifdef CONFIG_X86
31#include <asm/iosf_mbi.h>
32#endif
33
8ee82bda
AH		 34#include "cqhci.h"
35
b8c86fc5 36#include "sdhci.h"
522624f9 37#include "sdhci-pci.h"
22606405 38
fee686b7 39static void sdhci_pci_hw_reset(struct sdhci_host *host);
fee686b7 40
30cf2803 41#ifdef CONFIG_PM_SLEEP
5c3c6126
AH		 42static int sdhci_pci_init_wakeup(struct sdhci_pci_chip *chip)
43{
44 mmc_pm_flag_t pm_flags = 0;
d56ee1ff 45 bool cap_cd_wake = false;
5c3c6126
AH		 46 int i;
47
48 for (i = 0; i < chip->num_slots; i++) {
49 struct sdhci_pci_slot *slot = chip->slots[i];
50
d56ee1ff 51 if (slot) {
5c3c6126 52 pm_flags |= slot->host->mmc->pm_flags;
d56ee1ff
AH		 53 if (slot->host->mmc->caps & MMC_CAP_CD_WAKE)
54 cap_cd_wake = true;
55 }
5c3c6126
AH		 56 }
57
d56ee1ff
AH		 58 if ((pm_flags & MMC_PM_KEEP_POWER) && (pm_flags & MMC_PM_WAKE_SDIO_IRQ))
59 return device_wakeup_enable(&chip->pdev->dev);
60 else if (!cap_cd_wake)
61 return device_wakeup_disable(&chip->pdev->dev);
62
63 return 0;
5c3c6126
AH		 64}
65
66static int sdhci_pci_suspend_host(struct sdhci_pci_chip *chip)
30cf2803
AH		 67{
68 int i, ret;
69
5c3c6126
AH		 70 sdhci_pci_init_wakeup(chip);
71
30cf2803
AH		 72 for (i = 0; i < chip->num_slots; i++) {
73 struct sdhci_pci_slot *slot = chip->slots[i];
74 struct sdhci_host *host;
75
76 if (!slot)
77 continue;
78
79 host = slot->host;
80
81 if (chip->pm_retune && host->tuning_mode != SDHCI_TUNING_MODE_3)
82 mmc_retune_needed(host->mmc);
83
84 ret = sdhci_suspend_host(host);
85 if (ret)
86 goto err_pci_suspend;
d56ee1ff
AH		 87
88 if (device_may_wakeup(&chip->pdev->dev))
89 mmc_gpio_set_cd_wake(host->mmc, true);
30cf2803
AH		 90 }
91
92 return 0;
93
94err_pci_suspend:
95 while (--i >= 0)
96 sdhci_resume_host(chip->slots[i]->host);
97 return ret;
98}
99
30cf2803
AH		 100int sdhci_pci_resume_host(struct sdhci_pci_chip *chip)
101{
102 struct sdhci_pci_slot *slot;
103 int i, ret;
104
105 for (i = 0; i < chip->num_slots; i++) {
106 slot = chip->slots[i];
107 if (!slot)
108 continue;
109
110 ret = sdhci_resume_host(slot->host);
111 if (ret)
112 return ret;
d56ee1ff
AH		 113
114 mmc_gpio_set_cd_wake(slot->host->mmc, false);
30cf2803
AH		 115 }
116
117 return 0;
118}
8ee82bda
AH		 119
120static int sdhci_cqhci_suspend(struct sdhci_pci_chip *chip)
121{
122 int ret;
123
124 ret = cqhci_suspend(chip->slots[0]->host->mmc);
125 if (ret)
126 return ret;
127
128 return sdhci_pci_suspend_host(chip);
129}
130
131static int sdhci_cqhci_resume(struct sdhci_pci_chip *chip)
132{
133 int ret;
134
135 ret = sdhci_pci_resume_host(chip);
136 if (ret)
137 return ret;
138
139 return cqhci_resume(chip->slots[0]->host->mmc);
140}
30cf2803
AH		 141#endif
142
966d696a
AH		 143#ifdef CONFIG_PM
144static int sdhci_pci_runtime_suspend_host(struct sdhci_pci_chip *chip)
145{
146 struct sdhci_pci_slot *slot;
147 struct sdhci_host *host;
148 int i, ret;
149
150 for (i = 0; i < chip->num_slots; i++) {
151 slot = chip->slots[i];
152 if (!slot)
153 continue;
154
155 host = slot->host;
156
157 ret = sdhci_runtime_suspend_host(host);
158 if (ret)
159 goto err_pci_runtime_suspend;
160
161 if (chip->rpm_retune &&
162 host->tuning_mode != SDHCI_TUNING_MODE_3)
163 mmc_retune_needed(host->mmc);
164 }
165
166 return 0;
167
168err_pci_runtime_suspend:
169 while (--i >= 0)
170 sdhci_runtime_resume_host(chip->slots[i]->host);
171 return ret;
172}
173
174static int sdhci_pci_runtime_resume_host(struct sdhci_pci_chip *chip)
175{
176 struct sdhci_pci_slot *slot;
177 int i, ret;
178
179 for (i = 0; i < chip->num_slots; i++) {
180 slot = chip->slots[i];
181 if (!slot)
182 continue;
183
184 ret = sdhci_runtime_resume_host(slot->host);
185 if (ret)
186 return ret;
187 }
188
189 return 0;
190}
8ee82bda
AH		 191
192static int sdhci_cqhci_runtime_suspend(struct sdhci_pci_chip *chip)
193{
194 int ret;
195
196 ret = cqhci_suspend(chip->slots[0]->host->mmc);
197 if (ret)
198 return ret;
199
200 return sdhci_pci_runtime_suspend_host(chip);
201}
202
203static int sdhci_cqhci_runtime_resume(struct sdhci_pci_chip *chip)
204{
205 int ret;
206
207 ret = sdhci_pci_runtime_resume_host(chip);
208 if (ret)
209 return ret;
210
211 return cqhci_resume(chip->slots[0]->host->mmc);
212}
966d696a
AH		 213#endif
214
8ee82bda
AH		 215static u32 sdhci_cqhci_irq(struct sdhci_host *host, u32 intmask)
216{
217 int cmd_error = 0;
218 int data_error = 0;
219
220 if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error))
221 return intmask;
222
223 cqhci_irq(host->mmc, intmask, cmd_error, data_error);
224
225 return 0;
226}
227
228static void sdhci_pci_dumpregs(struct mmc_host *mmc)
229{
230 sdhci_dumpregs(mmc_priv(mmc));
231}
232
22606405
PO		 233/*****************************************************************************\
234 * *
235 * Hardware specific quirk handling *
236 * *
237\*****************************************************************************/
238
239static int ricoh_probe(struct sdhci_pci_chip *chip)
240{
c99436fb
CB		 241 if (chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG ||
242 chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SONY)
22606405 243 chip->quirks |= SDHCI_QUIRK_NO_CARD_NO_RESET;
ccc92c23
ML		 244 return 0;
245}
246
247static int ricoh_mmc_probe_slot(struct sdhci_pci_slot *slot)
248{
249 slot->host->caps =
250 ((0x21 << SDHCI_TIMEOUT_CLK_SHIFT)
251 & SDHCI_TIMEOUT_CLK_MASK) |
22606405 252
ccc92c23
ML		 253 ((0x21 << SDHCI_CLOCK_BASE_SHIFT)
254 & SDHCI_CLOCK_BASE_MASK) |
255
256 SDHCI_TIMEOUT_CLK_UNIT |
257 SDHCI_CAN_VDD_330 |
1a1f1f04 258 SDHCI_CAN_DO_HISPD |
ccc92c23
ML		 259 SDHCI_CAN_DO_SDMA;
260 return 0;
261}
262
b7813f0f 263#ifdef CONFIG_PM_SLEEP
ccc92c23
ML		 264static int ricoh_mmc_resume(struct sdhci_pci_chip *chip)
265{
266 /* Apply a delay to allow controller to settle */
267 /* Otherwise it becomes confused if card state changed
268 during suspend */
269 msleep(500);
30cf2803 270 return sdhci_pci_resume_host(chip);
22606405 271}
b7813f0f 272#endif
22606405
PO		 273
274static const struct sdhci_pci_fixes sdhci_ricoh = {
275 .probe = ricoh_probe,
84938294
VK		 276 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR |
277 SDHCI_QUIRK_FORCE_DMA |
278 SDHCI_QUIRK_CLOCK_BEFORE_RESET,
22606405
PO		 279};
280
ccc92c23
ML		 281static const struct sdhci_pci_fixes sdhci_ricoh_mmc = {
282 .probe_slot = ricoh_mmc_probe_slot,
b7813f0f 283#ifdef CONFIG_PM_SLEEP
ccc92c23 284 .resume = ricoh_mmc_resume,
b7813f0f 285#endif
ccc92c23
ML		 286 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR |
287 SDHCI_QUIRK_CLOCK_BEFORE_RESET |
288 SDHCI_QUIRK_NO_CARD_NO_RESET |
289 SDHCI_QUIRK_MISSING_CAPS
290};
291
22606405
PO		 292static const struct sdhci_pci_fixes sdhci_ene_712 = {
293 .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE |
294 SDHCI_QUIRK_BROKEN_DMA,
295};
296
297static const struct sdhci_pci_fixes sdhci_ene_714 = {
298 .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE |
299 SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS |
300 SDHCI_QUIRK_BROKEN_DMA,
301};
302
303static const struct sdhci_pci_fixes sdhci_cafe = {
304 .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER |
a0874897 305 SDHCI_QUIRK_NO_BUSY_IRQ |
55fc05b7 306 SDHCI_QUIRK_BROKEN_CARD_DETECTION |
ee53ab5d 307 SDHCI_QUIRK_BROKEN_TIMEOUT_VAL,
22606405
PO		 308};
309
43e968ce
DB		 310static const struct sdhci_pci_fixes sdhci_intel_qrk = {
311 .quirks = SDHCI_QUIRK_NO_HISPD_BIT,
312};
313
68077b02
ML		 314static int mrst_hc_probe_slot(struct sdhci_pci_slot *slot)
315{
316 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA;
317 return 0;
318}
319
f9ee3eab
AC		 320/*
321 * ADMA operation is disabled for Moorestown platform due to
322 * hardware bugs.
323 */
35ac6f08 324static int mrst_hc_probe(struct sdhci_pci_chip *chip)
f9ee3eab
AC		 325{
326 /*
35ac6f08
JP		 327 * slots number is fixed here for MRST as SDIO3/5 are never used and
328 * have hardware bugs.
f9ee3eab
AC		 329 */
330 chip->num_slots = 1;
331 return 0;
332}
333
296e0b03
AS		 334static int pch_hc_probe_slot(struct sdhci_pci_slot *slot)
335{
336 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA;
337 return 0;
338}
339
162d6f98 340#ifdef CONFIG_PM
66fd8ad5 341
c5e027a4 342static irqreturn_t sdhci_pci_sd_cd(int irq, void *dev_id)
66fd8ad5
AH		 343{
344 struct sdhci_pci_slot *slot = dev_id;
345 struct sdhci_host *host = slot->host;
346
347 mmc_detect_change(host->mmc, msecs_to_jiffies(200));
348 return IRQ_HANDLED;
349}
350
c5e027a4 351static void sdhci_pci_add_own_cd(struct sdhci_pci_slot *slot)
66fd8ad5 352{
c5e027a4 353 int err, irq, gpio = slot->cd_gpio;
66fd8ad5
AH		 354
355 slot->cd_gpio = -EINVAL;
356 slot->cd_irq = -EINVAL;
357
c5e027a4
AH		 358 if (!gpio_is_valid(gpio))
359 return;
360
c10bc372 361 err = devm_gpio_request(&slot->chip->pdev->dev, gpio, "sd_cd");
66fd8ad5
AH		 362 if (err < 0)
363 goto out;
364
365 err = gpio_direction_input(gpio);
366 if (err < 0)
367 goto out_free;
368
369 irq = gpio_to_irq(gpio);
370 if (irq < 0)
371 goto out_free;
372
c5e027a4 373 err = request_irq(irq, sdhci_pci_sd_cd, IRQF_TRIGGER_RISING |
66fd8ad5
AH		 374 IRQF_TRIGGER_FALLING, "sd_cd", slot);
375 if (err)
376 goto out_free;
377
378 slot->cd_gpio = gpio;
379 slot->cd_irq = irq;
66fd8ad5 380
c5e027a4 381 return;
66fd8ad5
AH		 382
383out_free:
c10bc372 384 devm_gpio_free(&slot->chip->pdev->dev, gpio);
66fd8ad5
AH		 385out:
386 dev_warn(&slot->chip->pdev->dev, "failed to setup card detect wake up\n");
66fd8ad5
AH		 387}
388
c5e027a4 389static void sdhci_pci_remove_own_cd(struct sdhci_pci_slot *slot)
66fd8ad5
AH		 390{
391 if (slot->cd_irq >= 0)
392 free_irq(slot->cd_irq, slot);
66fd8ad5
AH		 393}
394
395#else
396
c5e027a4
AH		 397static inline void sdhci_pci_add_own_cd(struct sdhci_pci_slot *slot)
398{
399}
400
401static inline void sdhci_pci_remove_own_cd(struct sdhci_pci_slot *slot)
402{
403}
66fd8ad5
AH		 404
405#endif
406
0d013bcf
AH		 407static int mfd_emmc_probe_slot(struct sdhci_pci_slot *slot)
408{
66fd8ad5 409 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE;
d2a47176 410 slot->host->mmc->caps2 |= MMC_CAP2_BOOTPART_NOACC;
0d013bcf
AH		 411 return 0;
412}
413
93933508
AH		 414static int mfd_sdio_probe_slot(struct sdhci_pci_slot *slot)
415{
012e4671 416 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE;
93933508
AH		 417 return 0;
418}
419
f9ee3eab
AC		 420static const struct sdhci_pci_fixes sdhci_intel_mrst_hc0 = {
421 .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT,
68077b02 422 .probe_slot = mrst_hc_probe_slot,
f9ee3eab
AC		 423};
424
35ac6f08 425static const struct sdhci_pci_fixes sdhci_intel_mrst_hc1_hc2 = {
f9ee3eab 426 .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT,
35ac6f08 427 .probe = mrst_hc_probe,
f9ee3eab
AC		 428};
429
29229052
XS		 430static const struct sdhci_pci_fixes sdhci_intel_mfd_sd = {
431 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
c43fd774 432 .allow_runtime_pm = true,
77a0122e 433 .own_cd_for_runtime_pm = true,
29229052
XS		 434};
435
0d013bcf
AH		 436static const struct sdhci_pci_fixes sdhci_intel_mfd_sdio = {
437 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
f3c55a7b 438 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON,
c43fd774 439 .allow_runtime_pm = true,
93933508 440 .probe_slot = mfd_sdio_probe_slot,
0d013bcf
AH		 441};
442
443static const struct sdhci_pci_fixes sdhci_intel_mfd_emmc = {
29229052 444 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
c43fd774 445 .allow_runtime_pm = true,
0d013bcf 446 .probe_slot = mfd_emmc_probe_slot,
29229052
XS		 447};
448
296e0b03
AS		 449static const struct sdhci_pci_fixes sdhci_intel_pch_sdio = {
450 .quirks = SDHCI_QUIRK_BROKEN_ADMA,
451 .probe_slot = pch_hc_probe_slot,
452};
453
0a49a619
AH		 454#ifdef CONFIG_X86
455
456#define BYT_IOSF_SCCEP 0x63
457#define BYT_IOSF_OCP_NETCTRL0 0x1078
458#define BYT_IOSF_OCP_TIMEOUT_BASE GENMASK(10, 8)
459
460static void byt_ocp_setting(struct pci_dev *pdev)
461{
462 u32 val = 0;
463
464 if (pdev->device != PCI_DEVICE_ID_INTEL_BYT_EMMC &&
465 pdev->device != PCI_DEVICE_ID_INTEL_BYT_SDIO &&
466 pdev->device != PCI_DEVICE_ID_INTEL_BYT_SD &&
467 pdev->device != PCI_DEVICE_ID_INTEL_BYT_EMMC2)
468 return;
469
470 if (iosf_mbi_read(BYT_IOSF_SCCEP, MBI_CR_READ, BYT_IOSF_OCP_NETCTRL0,
471 &val)) {
472 dev_err(&pdev->dev, "%s read error\n", __func__);
473 return;
474 }
475
476 if (!(val & BYT_IOSF_OCP_TIMEOUT_BASE))
477 return;
478
479 val &= ~BYT_IOSF_OCP_TIMEOUT_BASE;
480
481 if (iosf_mbi_write(BYT_IOSF_SCCEP, MBI_CR_WRITE, BYT_IOSF_OCP_NETCTRL0,
482 val)) {
483 dev_err(&pdev->dev, "%s write error\n", __func__);
484 return;
485 }
486
487 dev_dbg(&pdev->dev, "%s completed\n", __func__);
488}
489
490#else
491
492static inline void byt_ocp_setting(struct pci_dev *pdev)
493{
494}
495
496#endif
497
c959a6b0
AH		 498enum {
499 INTEL_DSM_FNS = 0,
6ae03368 500 INTEL_DSM_V18_SWITCH = 3,
be17355a 501 INTEL_DSM_V33_SWITCH = 4,
51ced59c 502 INTEL_DSM_DRV_STRENGTH = 9,
c959a6b0
AH		 503 INTEL_DSM_D3_RETUNE = 10,
504};
505
506struct intel_host {
507 u32 dsm_fns;
51ced59c 508 int drv_strength;
c959a6b0 509 bool d3_retune;
5305ec6a
AH		 510 bool rpm_retune_ok;
511 u32 glk_rx_ctrl1;
512 u32 glk_tun_val;
c959a6b0
AH		 513};
514
c37f69ff 515static const guid_t intel_dsm_guid =
94116f81
AS		 516 GUID_INIT(0xF6C13EA5, 0x65CD, 0x461F,
517 0xAB, 0x7A, 0x29, 0xF7, 0xE8, 0xD5, 0xBD, 0x61);
c959a6b0
AH		 518
519static int __intel_dsm(struct intel_host *intel_host, struct device *dev,
520 unsigned int fn, u32 *result)
521{
522 union acpi_object *obj;
523 int err = 0;
a72016a4 524 size_t len;
c959a6b0 525
94116f81 526 obj = acpi_evaluate_dsm(ACPI_HANDLE(dev), &intel_dsm_guid, 0, fn, NULL);
c959a6b0
AH		 527 if (!obj)
528 return -EOPNOTSUPP;
529
530 if (obj->type != ACPI_TYPE_BUFFER || obj->buffer.length < 1) {
531 err = -EINVAL;
532 goto out;
533 }
534
a72016a4
AH		 535 len = min_t(size_t, obj->buffer.length, 4);
536
537 *result = 0;
538 memcpy(result, obj->buffer.pointer, len);
c959a6b0
AH		 539out:
540 ACPI_FREE(obj);
541
542 return err;
543}
544
545static int intel_dsm(struct intel_host *intel_host, struct device *dev,
546 unsigned int fn, u32 *result)
547{
548 if (fn > 31 || !(intel_host->dsm_fns & (1 << fn)))
549 return -EOPNOTSUPP;
550
551 return __intel_dsm(intel_host, dev, fn, result);
552}
553
554static void intel_dsm_init(struct intel_host *intel_host, struct device *dev,
555 struct mmc_host *mmc)
556{
557 int err;
558 u32 val;
559
eb701ce1
AH		 560 intel_host->d3_retune = true;
561
c959a6b0
AH		 562 err = __intel_dsm(intel_host, dev, INTEL_DSM_FNS, &intel_host->dsm_fns);
563 if (err) {
564 pr_debug("%s: DSM not supported, error %d\n",
565 mmc_hostname(mmc), err);
566 return;
567 }
568
569 pr_debug("%s: DSM function mask %#x\n",
570 mmc_hostname(mmc), intel_host->dsm_fns);
571
51ced59c
AH		 572 err = intel_dsm(intel_host, dev, INTEL_DSM_DRV_STRENGTH, &val);
573 intel_host->drv_strength = err ? 0 : val;
574
c959a6b0
AH		 575 err = intel_dsm(intel_host, dev, INTEL_DSM_D3_RETUNE, &val);
576 intel_host->d3_retune = err ? true : !!val;
577}
578
c9faff6c
AH		 579static void sdhci_pci_int_hw_reset(struct sdhci_host *host)
580{
581 u8 reg;
582
583 reg = sdhci_readb(host, SDHCI_POWER_CONTROL);
584 reg |= 0x10;
585 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL);
586 /* For eMMC, minimum is 1us but give it 9us for good measure */
587 udelay(9);
588 reg &= ~0x10;
589 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL);
590 /* For eMMC, minimum is 200us but give it 300us for good measure */
591 usleep_range(300, 1000);
592}
593
51ced59c
AH		 594static int intel_select_drive_strength(struct mmc_card *card,
595 unsigned int max_dtr, int host_drv,
596 int card_drv, int *drv_type)
e1bfad6d 597{
51ced59c
AH		 598 struct sdhci_host *host = mmc_priv(card->host);
599 struct sdhci_pci_slot *slot = sdhci_priv(host);
600 struct intel_host *intel_host = sdhci_pci_priv(slot);
e1bfad6d 601
51ced59c 602 return intel_host->drv_strength;
e1bfad6d
AH		 603}
604
163cbe31
AH		 605static int bxt_get_cd(struct mmc_host *mmc)
606{
607 int gpio_cd = mmc_gpio_get_cd(mmc);
608 struct sdhci_host *host = mmc_priv(mmc);
609 unsigned long flags;
610 int ret = 0;
611
612 if (!gpio_cd)
613 return 0;
614
163cbe31
AH		 615 spin_lock_irqsave(&host->lock, flags);
616
617 if (host->flags & SDHCI_DEVICE_DEAD)
618 goto out;
619
620 ret = !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
621out:
622 spin_unlock_irqrestore(&host->lock, flags);
623
163cbe31
AH		 624 return ret;
625}
626
48d685a2
AH		 627#define SDHCI_INTEL_PWR_TIMEOUT_CNT 20
628#define SDHCI_INTEL_PWR_TIMEOUT_UDELAY 100
629
630static void sdhci_intel_set_power(struct sdhci_host *host, unsigned char mode,
631 unsigned short vdd)
632{
633 int cntr;
634 u8 reg;
635
636 sdhci_set_power(host, mode, vdd);
637
638 if (mode == MMC_POWER_OFF)
639 return;
640
641 /*
642 * Bus power might not enable after D3 -> D0 transition due to the
643 * present state not yet having propagated. Retry for up to 2ms.
644 */
645 for (cntr = 0; cntr < SDHCI_INTEL_PWR_TIMEOUT_CNT; cntr++) {
646 reg = sdhci_readb(host, SDHCI_POWER_CONTROL);
647 if (reg & SDHCI_POWER_ON)
648 break;
649 udelay(SDHCI_INTEL_PWR_TIMEOUT_UDELAY);
650 reg |= SDHCI_POWER_ON;
651 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL);
652 }
653}
654
bc55dcd8
AH		 655#define INTEL_HS400_ES_REG 0x78
656#define INTEL_HS400_ES_BIT BIT(0)
657
658static void intel_hs400_enhanced_strobe(struct mmc_host *mmc,
659 struct mmc_ios *ios)
660{
661 struct sdhci_host *host = mmc_priv(mmc);
662 u32 val;
663
664 val = sdhci_readl(host, INTEL_HS400_ES_REG);
665 if (ios->enhanced_strobe)
666 val |= INTEL_HS400_ES_BIT;
667 else
668 val &= ~INTEL_HS400_ES_BIT;
669 sdhci_writel(host, val, INTEL_HS400_ES_REG);
670}
671
be17355a
AH		 672static int intel_start_signal_voltage_switch(struct mmc_host *mmc,
673 struct mmc_ios *ios)
6ae03368 674{
be17355a
AH		 675 struct device *dev = mmc_dev(mmc);
676 struct sdhci_host *host = mmc_priv(mmc);
6ae03368
AH		 677 struct sdhci_pci_slot *slot = sdhci_priv(host);
678 struct intel_host *intel_host = sdhci_pci_priv(slot);
be17355a 679 unsigned int fn;
6ae03368
AH		 680 u32 result = 0;
681 int err;
682
be17355a
AH		 683 err = sdhci_start_signal_voltage_switch(mmc, ios);
684 if (err)
685 return err;
686
687 switch (ios->signal_voltage) {
688 case MMC_SIGNAL_VOLTAGE_330:
689 fn = INTEL_DSM_V33_SWITCH;
690 break;
691 case MMC_SIGNAL_VOLTAGE_180:
692 fn = INTEL_DSM_V18_SWITCH;
693 break;
694 default:
695 return 0;
696 }
697
698 err = intel_dsm(intel_host, dev, fn, &result);
699 pr_debug("%s: %s DSM fn %u error %d result %u\n",
700 mmc_hostname(mmc), __func__, fn, err, result);
701
702 return 0;
6ae03368
AH		 703}
704
48d685a2
AH		 705static const struct sdhci_ops sdhci_intel_byt_ops = {
706 .set_clock = sdhci_set_clock,
707 .set_power = sdhci_intel_set_power,
708 .enable_dma = sdhci_pci_enable_dma,
adc16398 709 .set_bus_width = sdhci_set_bus_width,
48d685a2
AH		 710 .reset = sdhci_reset,
711 .set_uhs_signaling = sdhci_set_uhs_signaling,
712 .hw_reset = sdhci_pci_hw_reset,
713};
714
8ee82bda
AH		 715static const struct sdhci_ops sdhci_intel_glk_ops = {
716 .set_clock = sdhci_set_clock,
717 .set_power = sdhci_intel_set_power,
718 .enable_dma = sdhci_pci_enable_dma,
719 .set_bus_width = sdhci_set_bus_width,
720 .reset = sdhci_reset,
721 .set_uhs_signaling = sdhci_set_uhs_signaling,
722 .hw_reset = sdhci_pci_hw_reset,
8ee82bda
AH		 723 .irq = sdhci_cqhci_irq,
724};
725
c959a6b0
AH		 726static void byt_read_dsm(struct sdhci_pci_slot *slot)
727{
728 struct intel_host *intel_host = sdhci_pci_priv(slot);
729 struct device *dev = &slot->chip->pdev->dev;
730 struct mmc_host *mmc = slot->host->mmc;
731
732 intel_dsm_init(intel_host, dev, mmc);
733 slot->chip->rpm_retune = intel_host->d3_retune;
734}
735
f8870ae6
AH		 736static int intel_execute_tuning(struct mmc_host *mmc, u32 opcode)
737{
738 int err = sdhci_execute_tuning(mmc, opcode);
739 struct sdhci_host *host = mmc_priv(mmc);
740
741 if (err)
742 return err;
743
744 /*
745 * Tuning can leave the IP in an active state (Buffer Read Enable bit
746 * set) which prevents the entry to low power states (i.e. S0i3). Data
747 * reset will clear it.
748 */
749 sdhci_reset(host, SDHCI_RESET_DATA);
750
751 return 0;
752}
753
754static void byt_probe_slot(struct sdhci_pci_slot *slot)
728ef3d1 755{
f8870ae6 756 struct mmc_host_ops *ops = &slot->host->mmc_host_ops;
809090e8
AH		 757 struct device *dev = &slot->chip->pdev->dev;
758 struct mmc_host *mmc = slot->host->mmc;
f8870ae6 759
c959a6b0 760 byt_read_dsm(slot);
f8870ae6 761
0a49a619
AH		 762 byt_ocp_setting(slot->chip->pdev);
763
f8870ae6 764 ops->execute_tuning = intel_execute_tuning;
be17355a 765 ops->start_signal_voltage_switch = intel_start_signal_voltage_switch;
809090e8
AH		 766
767 device_property_read_u32(dev, "max-frequency", &mmc->f_max);
f8870ae6
AH		 768}
769
770static int byt_emmc_probe_slot(struct sdhci_pci_slot *slot)
771{
772 byt_probe_slot(slot);
c9faff6c 773 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE |
6aab23a8 774 MMC_CAP_HW_RESET | MMC_CAP_1_8V_DDR |
32828857 775 MMC_CAP_CMD_DURING_TFR |
6aab23a8 776 MMC_CAP_WAIT_WHILE_BUSY;
c9faff6c 777 slot->hw_reset = sdhci_pci_int_hw_reset;
a06586b6
AH		 778 if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BSW_EMMC)
779 slot->host->timeout_clk = 1000; /* 1000 kHz i.e. 1 MHz */
51ced59c
AH		 780 slot->host->mmc_host_ops.select_drive_strength =
781 intel_select_drive_strength;
728ef3d1
AH		 782 return 0;
783}
784
bc55dcd8
AH		 785static int glk_emmc_probe_slot(struct sdhci_pci_slot *slot)
786{
787 int ret = byt_emmc_probe_slot(slot);
788
8ee82bda
AH		 789 slot->host->mmc->caps2 |= MMC_CAP2_CQE;
790
bc55dcd8
AH		 791 if (slot->chip->pdev->device != PCI_DEVICE_ID_INTEL_GLK_EMMC) {
792 slot->host->mmc->caps2 |= MMC_CAP2_HS400_ES,
793 slot->host->mmc_host_ops.hs400_enhanced_strobe =
794 intel_hs400_enhanced_strobe;
8ee82bda 795 slot->host->mmc->caps2 |= MMC_CAP2_CQE_DCMD;
bc55dcd8
AH		 796 }
797
798 return ret;
799}
800
8ee82bda 801static const struct cqhci_host_ops glk_cqhci_ops = {
7b7d57fd 802 .enable = sdhci_cqe_enable,
8ee82bda
AH		 803 .disable = sdhci_cqe_disable,
804 .dumpregs = sdhci_pci_dumpregs,
805};
806
807static int glk_emmc_add_host(struct sdhci_pci_slot *slot)
808{
809 struct device *dev = &slot->chip->pdev->dev;
810 struct sdhci_host *host = slot->host;
811 struct cqhci_host *cq_host;
812 bool dma64;
813 int ret;
814
815 ret = sdhci_setup_host(host);
816 if (ret)
817 return ret;
818
819 cq_host = devm_kzalloc(dev, sizeof(*cq_host), GFP_KERNEL);
820 if (!cq_host) {
821 ret = -ENOMEM;
822 goto cleanup;
823 }
824
825 cq_host->mmio = host->ioaddr + 0x200;
826 cq_host->quirks |= CQHCI_QUIRK_SHORT_TXFR_DESC_SZ;
827 cq_host->ops = &glk_cqhci_ops;
828
829 dma64 = host->flags & SDHCI_USE_64_BIT_DMA;
830 if (dma64)
831 cq_host->caps |= CQHCI_TASK_DESC_SZ_128;
832
833 ret = cqhci_init(cq_host, host->mmc, dma64);
834 if (ret)
835 goto cleanup;
836
837 ret = __sdhci_add_host(host);
838 if (ret)
839 goto cleanup;
840
841 return 0;
842
843cleanup:
844 sdhci_cleanup_host(host);
845 return ret;
846}
847
5305ec6a
AH		 848#ifdef CONFIG_PM
849#define GLK_RX_CTRL1 0x834
850#define GLK_TUN_VAL 0x840
851#define GLK_PATH_PLL GENMASK(13, 8)
852#define GLK_DLY GENMASK(6, 0)
853/* Workaround firmware failing to restore the tuning value */
854static void glk_rpm_retune_wa(struct sdhci_pci_chip *chip, bool susp)
855{
856 struct sdhci_pci_slot *slot = chip->slots[0];
857 struct intel_host *intel_host = sdhci_pci_priv(slot);
858 struct sdhci_host *host = slot->host;
859 u32 glk_rx_ctrl1;
860 u32 glk_tun_val;
861 u32 dly;
862
863 if (intel_host->rpm_retune_ok || !mmc_can_retune(host->mmc))
864 return;
865
866 glk_rx_ctrl1 = sdhci_readl(host, GLK_RX_CTRL1);
867 glk_tun_val = sdhci_readl(host, GLK_TUN_VAL);
868
869 if (susp) {
870 intel_host->glk_rx_ctrl1 = glk_rx_ctrl1;
871 intel_host->glk_tun_val = glk_tun_val;
872 return;
873 }
874
875 if (!intel_host->glk_tun_val)
876 return;
877
878 if (glk_rx_ctrl1 != intel_host->glk_rx_ctrl1) {
879 intel_host->rpm_retune_ok = true;
880 return;
881 }
882
883 dly = FIELD_PREP(GLK_DLY, FIELD_GET(GLK_PATH_PLL, glk_rx_ctrl1) +
884 (intel_host->glk_tun_val << 1));
885 if (dly == FIELD_GET(GLK_DLY, glk_rx_ctrl1))
886 return;
887
888 glk_rx_ctrl1 = (glk_rx_ctrl1 & ~GLK_DLY) | dly;
889 sdhci_writel(host, glk_rx_ctrl1, GLK_RX_CTRL1);
890
891 intel_host->rpm_retune_ok = true;
892 chip->rpm_retune = true;
893 mmc_retune_needed(host->mmc);
894 pr_info("%s: Requiring re-tune after rpm resume", mmc_hostname(host->mmc));
895}
896
897static void glk_rpm_retune_chk(struct sdhci_pci_chip *chip, bool susp)
898{
899 if (chip->pdev->device == PCI_DEVICE_ID_INTEL_GLK_EMMC &&
900 !chip->rpm_retune)
901 glk_rpm_retune_wa(chip, susp);
902}
903
904static int glk_runtime_suspend(struct sdhci_pci_chip *chip)
905{
906 glk_rpm_retune_chk(chip, true);
907
908 return sdhci_cqhci_runtime_suspend(chip);
909}
910
911static int glk_runtime_resume(struct sdhci_pci_chip *chip)
912{
913 glk_rpm_retune_chk(chip, false);
914
915 return sdhci_cqhci_runtime_resume(chip);
916}
917#endif
918
3f23df72
ZB		 919#ifdef CONFIG_ACPI
920static int ni_set_max_freq(struct sdhci_pci_slot *slot)
921{
922 acpi_status status;
923 unsigned long long max_freq;
924
925 status = acpi_evaluate_integer(ACPI_HANDLE(&slot->chip->pdev->dev),
926 "MXFQ", NULL, &max_freq);
927 if (ACPI_FAILURE(status)) {
928 dev_err(&slot->chip->pdev->dev,
929 "MXFQ not found in acpi table\n");
930 return -EINVAL;
931 }
932
933 slot->host->mmc->f_max = max_freq * 1000000;
934
935 return 0;
936}
937#else
938static inline int ni_set_max_freq(struct sdhci_pci_slot *slot)
939{
940 return 0;
941}
942#endif
943
42b06496
ZB		 944static int ni_byt_sdio_probe_slot(struct sdhci_pci_slot *slot)
945{
3f23df72
ZB		 946 int err;
947
f8870ae6 948 byt_probe_slot(slot);
c959a6b0 949
3f23df72
ZB		 950 err = ni_set_max_freq(slot);
951 if (err)
952 return err;
953
42b06496
ZB		 954 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE |
955 MMC_CAP_WAIT_WHILE_BUSY;
956 return 0;
957}
958
728ef3d1
AH		 959static int byt_sdio_probe_slot(struct sdhci_pci_slot *slot)
960{
f8870ae6 961 byt_probe_slot(slot);
6aab23a8 962 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE |
6aab23a8 963 MMC_CAP_WAIT_WHILE_BUSY;
728ef3d1
AH		 964 return 0;
965}
966
ff59c520
AH		 967static int byt_sd_probe_slot(struct sdhci_pci_slot *slot)
968{
f8870ae6 969 byt_probe_slot(slot);
c2c49a2e 970 slot->host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY |
6cf4156c 971 MMC_CAP_AGGRESSIVE_PM | MMC_CAP_CD_WAKE;
ff59c520
AH		 972 slot->cd_idx = 0;
973 slot->cd_override_level = true;
163cbe31 974 if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BXT_SD ||
01d6b2a4 975 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BXTM_SD ||
2d1956d0 976 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_APL_SD ||
c2c49a2e 977 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_GLK_SD)
163cbe31
AH		 978 slot->host->mmc_host_ops.get_cd = bxt_get_cd;
979
bb26b841
KR		 980 if (slot->chip->pdev->subsystem_vendor == PCI_VENDOR_ID_NI &&
981 slot->chip->pdev->subsystem_device == PCI_SUBDEVICE_ID_NI_78E3)
982 slot->host->mmc->caps2 |= MMC_CAP2_AVOID_3_3V;
983
ff59c520
AH		 984 return 0;
985}
986
0a49a619
AH		 987#ifdef CONFIG_PM_SLEEP
988
989static int byt_resume(struct sdhci_pci_chip *chip)
990{
991 byt_ocp_setting(chip->pdev);
992
993 return sdhci_pci_resume_host(chip);
994}
995
996#endif
997
998#ifdef CONFIG_PM
999
1000static int byt_runtime_resume(struct sdhci_pci_chip *chip)
1001{
1002 byt_ocp_setting(chip->pdev);
1003
1004 return sdhci_pci_runtime_resume_host(chip);
1005}
1006
1007#endif
1008
728ef3d1 1009static const struct sdhci_pci_fixes sdhci_intel_byt_emmc = {
0a49a619
AH		 1010#ifdef CONFIG_PM_SLEEP
1011 .resume = byt_resume,
1012#endif
1013#ifdef CONFIG_PM
1014 .runtime_resume = byt_runtime_resume,
1015#endif
728ef3d1
AH		 1016 .allow_runtime_pm = true,
1017 .probe_slot = byt_emmc_probe_slot,
aeae6ad3
AH		 1018 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC |
1019 SDHCI_QUIRK_NO_LED,
e58e4a0d 1020 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
b69587e2 1021 SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 |
e58e4a0d 1022 SDHCI_QUIRK2_STOP_WITH_TC,
fee686b7 1023 .ops = &sdhci_intel_byt_ops,
c959a6b0 1024 .priv_size = sizeof(struct intel_host),
728ef3d1
AH		 1025};
1026
bc55dcd8
AH		 1027static const struct sdhci_pci_fixes sdhci_intel_glk_emmc = {
1028 .allow_runtime_pm = true,
1029 .probe_slot = glk_emmc_probe_slot,
8ee82bda
AH		 1030 .add_host = glk_emmc_add_host,
1031#ifdef CONFIG_PM_SLEEP
1032 .suspend = sdhci_cqhci_suspend,
1033 .resume = sdhci_cqhci_resume,
1034#endif
1035#ifdef CONFIG_PM
5305ec6a
AH		 1036 .runtime_suspend = glk_runtime_suspend,
1037 .runtime_resume = glk_runtime_resume,
8ee82bda 1038#endif
aeae6ad3
AH		 1039 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC |
1040 SDHCI_QUIRK_NO_LED,
bc55dcd8
AH		 1041 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
1042 SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 |
1043 SDHCI_QUIRK2_STOP_WITH_TC,
8ee82bda 1044 .ops = &sdhci_intel_glk_ops,
bc55dcd8
AH		 1045 .priv_size = sizeof(struct intel_host),
1046};
1047
42b06496 1048static const struct sdhci_pci_fixes sdhci_ni_byt_sdio = {
0a49a619
AH		 1049#ifdef CONFIG_PM_SLEEP
1050 .resume = byt_resume,
1051#endif
1052#ifdef CONFIG_PM
1053 .runtime_resume = byt_runtime_resume,
1054#endif
aeae6ad3
AH		 1055 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC |
1056 SDHCI_QUIRK_NO_LED,
42b06496
ZB		 1057 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON |
1058 SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
1059 .allow_runtime_pm = true,
1060 .probe_slot = ni_byt_sdio_probe_slot,
1061 .ops = &sdhci_intel_byt_ops,
c959a6b0 1062 .priv_size = sizeof(struct intel_host),
42b06496
ZB		 1063};
1064
728ef3d1 1065static const struct sdhci_pci_fixes sdhci_intel_byt_sdio = {
0a49a619
AH		 1066#ifdef CONFIG_PM_SLEEP
1067 .resume = byt_resume,
1068#endif
1069#ifdef CONFIG_PM
1070 .runtime_resume = byt_runtime_resume,
1071#endif
aeae6ad3
AH		 1072 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC |
1073 SDHCI_QUIRK_NO_LED,
b7574bad
GY		 1074 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON |
1075 SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
728ef3d1
AH		 1076 .allow_runtime_pm = true,
1077 .probe_slot = byt_sdio_probe_slot,
fee686b7 1078 .ops = &sdhci_intel_byt_ops,
c959a6b0 1079 .priv_size = sizeof(struct intel_host),
728ef3d1
AH		 1080};
1081
1082static const struct sdhci_pci_fixes sdhci_intel_byt_sd = {
0a49a619
AH		 1083#ifdef CONFIG_PM_SLEEP
1084 .resume = byt_resume,
1085#endif
1086#ifdef CONFIG_PM
1087 .runtime_resume = byt_runtime_resume,
1088#endif
aeae6ad3
AH		 1089 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC |
1090 SDHCI_QUIRK_NO_LED,
b7574bad 1091 .quirks2 = SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON |
e58e4a0d
AH		 1092 SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
1093 SDHCI_QUIRK2_STOP_WITH_TC,
7396e318 1094 .allow_runtime_pm = true,
77a0122e 1095 .own_cd_for_runtime_pm = true,
ff59c520 1096 .probe_slot = byt_sd_probe_slot,
fee686b7 1097 .ops = &sdhci_intel_byt_ops,
c959a6b0 1098 .priv_size = sizeof(struct intel_host),
728ef3d1
AH		 1099};
1100
8776a165 1101/* Define Host controllers for Intel Merrifield platform */
1f64cec2
AS		 1102#define INTEL_MRFLD_EMMC_0 0
1103#define INTEL_MRFLD_EMMC_1 1
4674b6c8 1104#define INTEL_MRFLD_SD 2
d5565577 1105#define INTEL_MRFLD_SDIO 3
8776a165 1106
0e39220e
AS		 1107#ifdef CONFIG_ACPI
1108static void intel_mrfld_mmc_fix_up_power_slot(struct sdhci_pci_slot *slot)
1109{
1110 struct acpi_device *device, *child;
1111
1112 device = ACPI_COMPANION(&slot->chip->pdev->dev);
1113 if (!device)
1114 return;
1115
1116 acpi_device_fix_up_power(device);
1117 list_for_each_entry(child, &device->children, node)
1118 if (child->status.present && child->status.enabled)
1119 acpi_device_fix_up_power(child);
1120}
1121#else
1122static inline void intel_mrfld_mmc_fix_up_power_slot(struct sdhci_pci_slot *slot) {}
1123#endif
1124
1f64cec2 1125static int intel_mrfld_mmc_probe_slot(struct sdhci_pci_slot *slot)
8776a165 1126{
2e57bbe2
AS		 1127 unsigned int func = PCI_FUNC(slot->chip->pdev->devfn);
1128
1129 switch (func) {
1130 case INTEL_MRFLD_EMMC_0:
1131 case INTEL_MRFLD_EMMC_1:
1132 slot->host->mmc->caps |= MMC_CAP_NONREMOVABLE |
1133 MMC_CAP_8_BIT_DATA |
1134 MMC_CAP_1_8V_DDR;
1135 break;
4674b6c8
AS		 1136 case INTEL_MRFLD_SD:
1137 slot->host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V;
1138 break;
d5565577 1139 case INTEL_MRFLD_SDIO:
2a609abe
AS		 1140 /* Advertise 2.0v for compatibility with the SDIO card's OCR */
1141 slot->host->ocr_mask = MMC_VDD_20_21 | MMC_VDD_165_195;
d5565577
AS		 1142 slot->host->mmc->caps |= MMC_CAP_NONREMOVABLE |
1143 MMC_CAP_POWER_OFF_CARD;
1144 break;
2e57bbe2 1145 default:
8776a165 1146 return -ENODEV;
2e57bbe2 1147 }
0e39220e
AS		 1148
1149 intel_mrfld_mmc_fix_up_power_slot(slot);
8776a165
DC		 1150 return 0;
1151}
1152
1f64cec2 1153static const struct sdhci_pci_fixes sdhci_intel_mrfld_mmc = {
8776a165 1154 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
b7574bad
GY		 1155 .quirks2 = SDHCI_QUIRK2_BROKEN_HS200 |
1156 SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
f1b55a55 1157 .allow_runtime_pm = true,
1f64cec2 1158 .probe_slot = intel_mrfld_mmc_probe_slot,
8776a165
DC		 1159};
1160
45211e21
PO		 1161static int jmicron_pmos(struct sdhci_pci_chip *chip, int on)
1162{
1163 u8 scratch;
1164 int ret;
1165
1166 ret = pci_read_config_byte(chip->pdev, 0xAE, &scratch);
1167 if (ret)
1168 return ret;
1169
1170 /*
1171 * Turn PMOS on [bit 0], set over current detection to 2.4 V
1172 * [bit 1:2] and enable over current debouncing [bit 6].
1173 */
1174 if (on)
1175 scratch |= 0x47;
1176 else
1177 scratch &= ~0x47;
1178
7582041f 1179 return pci_write_config_byte(chip->pdev, 0xAE, scratch);
45211e21
PO		 1180}
1181
1182static int jmicron_probe(struct sdhci_pci_chip *chip)
1183{
1184 int ret;
8f230f45 1185 u16 mmcdev = 0;
45211e21 1186
93fc48c7
PO		 1187 if (chip->pdev->revision == 0) {
1188 chip->quirks |= SDHCI_QUIRK_32BIT_DMA_ADDR |
1189 SDHCI_QUIRK_32BIT_DMA_SIZE |
2134a922 1190 SDHCI_QUIRK_32BIT_ADMA_SIZE |
4a3cba32 1191 SDHCI_QUIRK_RESET_AFTER_REQUEST |
86a6a874 1192 SDHCI_QUIRK_BROKEN_SMALL_PIO;
93fc48c7
PO		 1193 }
1194
4489428a
PO		 1195 /*
1196 * JMicron chips can have two interfaces to the same hardware
1197 * in order to work around limitations in Microsoft's driver.
1198 * We need to make sure we only bind to one of them.
1199 *
1200 * This code assumes two things:
1201 *
1202 * 1. The PCI code adds subfunctions in order.
1203 *
1204 * 2. The MMC interface has a lower subfunction number
1205 * than the SD interface.
1206 */
8f230f45
TI		 1207 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_SD)
1208 mmcdev = PCI_DEVICE_ID_JMICRON_JMB38X_MMC;
1209 else if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD)
1210 mmcdev = PCI_DEVICE_ID_JMICRON_JMB388_ESD;
1211
1212 if (mmcdev) {
4489428a
PO		 1213 struct pci_dev *sd_dev;
1214
1215 sd_dev = NULL;
1216 while ((sd_dev = pci_get_device(PCI_VENDOR_ID_JMICRON,
8f230f45 1217 mmcdev, sd_dev)) != NULL) {
4489428a
PO		 1218 if ((PCI_SLOT(chip->pdev->devfn) ==
1219 PCI_SLOT(sd_dev->devfn)) &&
1220 (chip->pdev->bus == sd_dev->bus))
1221 break;
1222 }
1223
1224 if (sd_dev) {
1225 pci_dev_put(sd_dev);
1226 dev_info(&chip->pdev->dev, "Refusing to bind to "
1227 "secondary interface.\n");
1228 return -ENODEV;
1229 }
1230 }
1231
45211e21
PO		 1232 /*
1233 * JMicron chips need a bit of a nudge to enable the power
1234 * output pins.
1235 */
1236 ret = jmicron_pmos(chip, 1);
1237 if (ret) {
1238 dev_err(&chip->pdev->dev, "Failure enabling card power\n");
1239 return ret;
1240 }
1241
82b0e23a
TI		 1242 /* quirk for unsable RO-detection on JM388 chips */
1243 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD ||
1244 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD)
1245 chip->quirks |= SDHCI_QUIRK_UNSTABLE_RO_DETECT;
1246
45211e21
PO		 1247 return 0;
1248}
1249
4489428a
PO		 1250static void jmicron_enable_mmc(struct sdhci_host *host, int on)
1251{
1252 u8 scratch;
1253
1254 scratch = readb(host->ioaddr + 0xC0);
1255
1256 if (on)
1257 scratch |= 0x01;
1258 else
1259 scratch &= ~0x01;
1260
1261 writeb(scratch, host->ioaddr + 0xC0);
1262}
1263
1264static int jmicron_probe_slot(struct sdhci_pci_slot *slot)
1265{
2134a922
PO		 1266 if (slot->chip->pdev->revision == 0) {
1267 u16 version;
1268
1269 version = readl(slot->host->ioaddr + SDHCI_HOST_VERSION);
1270 version = (version & SDHCI_VENDOR_VER_MASK) >>
1271 SDHCI_VENDOR_VER_SHIFT;
1272
1273 /*
1274 * Older versions of the chip have lots of nasty glitches
1275 * in the ADMA engine. It's best just to avoid it
1276 * completely.
1277 */
1278 if (version < 0xAC)
1279 slot->host->quirks |= SDHCI_QUIRK_BROKEN_ADMA;
1280 }
1281
8f230f45
TI		 1282 /* JM388 MMC doesn't support 1.8V while SD supports it */
1283 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) {
1284 slot->host->ocr_avail_sd = MMC_VDD_32_33 | MMC_VDD_33_34 |
1285 MMC_VDD_29_30 | MMC_VDD_30_31 |
1286 MMC_VDD_165_195; /* allow 1.8V */
1287 slot->host->ocr_avail_mmc = MMC_VDD_32_33 | MMC_VDD_33_34 |
1288 MMC_VDD_29_30 | MMC_VDD_30_31; /* no 1.8V for MMC */
1289 }
1290
4489428a
PO		 1291 /*
1292 * The secondary interface requires a bit set to get the
1293 * interrupts.
1294 */
8f230f45
TI		 1295 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
1296 slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD)
4489428a
PO		 1297 jmicron_enable_mmc(slot->host, 1);
1298
d75c1084
TI		 1299 slot->host->mmc->caps |= MMC_CAP_BUS_WIDTH_TEST;
1300
4489428a
PO		 1301 return 0;
1302}
1303
1e72859e 1304static void jmicron_remove_slot(struct sdhci_pci_slot *slot, int dead)
4489428a 1305{
1e72859e
PO		 1306 if (dead)
1307 return;
1308
8f230f45
TI		 1309 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
1310 slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD)
4489428a
PO		 1311 jmicron_enable_mmc(slot->host, 0);
1312}
1313
b7813f0f 1314#ifdef CONFIG_PM_SLEEP
29495aa0 1315static int jmicron_suspend(struct sdhci_pci_chip *chip)
4489428a 1316{
30cf2803
AH		 1317 int i, ret;
1318
5c3c6126 1319 ret = sdhci_pci_suspend_host(chip);
30cf2803
AH		 1320 if (ret)
1321 return ret;
4489428a 1322
8f230f45
TI		 1323 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
1324 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) {
b177bc91 1325 for (i = 0; i < chip->num_slots; i++)
4489428a
PO		 1326 jmicron_enable_mmc(chip->slots[i]->host, 0);
1327 }
1328
1329 return 0;
1330}
1331
45211e21
PO		 1332static int jmicron_resume(struct sdhci_pci_chip *chip)
1333{
4489428a
PO		 1334 int ret, i;
1335
8f230f45
TI		 1336 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
1337 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) {
b177bc91 1338 for (i = 0; i < chip->num_slots; i++)
4489428a
PO		 1339 jmicron_enable_mmc(chip->slots[i]->host, 1);
1340 }
45211e21
PO		 1341
1342 ret = jmicron_pmos(chip, 1);
1343 if (ret) {
1344 dev_err(&chip->pdev->dev, "Failure enabling card power\n");
1345 return ret;
1346 }
1347
30cf2803 1348 return sdhci_pci_resume_host(chip);
45211e21 1349}
b7813f0f 1350#endif
45211e21 1351
22606405 1352static const struct sdhci_pci_fixes sdhci_jmicron = {
45211e21
PO		 1353 .probe = jmicron_probe,
1354
4489428a
PO		 1355 .probe_slot = jmicron_probe_slot,
1356 .remove_slot = jmicron_remove_slot,
1357
b7813f0f 1358#ifdef CONFIG_PM_SLEEP
4489428a 1359 .suspend = jmicron_suspend,
45211e21 1360 .resume = jmicron_resume,
b7813f0f 1361#endif
22606405
PO		 1362};
1363
a7a6186c
NP		 1364/* SysKonnect CardBus2SDIO extra registers */
1365#define SYSKT_CTRL 0x200
1366#define SYSKT_RDFIFO_STAT 0x204
1367#define SYSKT_WRFIFO_STAT 0x208
1368#define SYSKT_POWER_DATA 0x20c
1369#define SYSKT_POWER_330 0xef
1370#define SYSKT_POWER_300 0xf8
1371#define SYSKT_POWER_184 0xcc
1372#define SYSKT_POWER_CMD 0x20d
1373#define SYSKT_POWER_START (1 << 7)
1374#define SYSKT_POWER_STATUS 0x20e
1375#define SYSKT_POWER_STATUS_OK (1 << 0)
1376#define SYSKT_BOARD_REV 0x210
1377#define SYSKT_CHIP_REV 0x211
1378#define SYSKT_CONF_DATA 0x212
1379#define SYSKT_CONF_DATA_1V8 (1 << 2)
1380#define SYSKT_CONF_DATA_2V5 (1 << 1)
1381#define SYSKT_CONF_DATA_3V3 (1 << 0)
1382
1383static int syskt_probe(struct sdhci_pci_chip *chip)
1384{
1385 if ((chip->pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) {
1386 chip->pdev->class &= ~0x0000FF;
1387 chip->pdev->class |= PCI_SDHCI_IFDMA;
1388 }
1389 return 0;
1390}
1391
1392static int syskt_probe_slot(struct sdhci_pci_slot *slot)
1393{
1394 int tm, ps;
1395
1396 u8 board_rev = readb(slot->host->ioaddr + SYSKT_BOARD_REV);
1397 u8 chip_rev = readb(slot->host->ioaddr + SYSKT_CHIP_REV);
1398 dev_info(&slot->chip->pdev->dev, "SysKonnect CardBus2SDIO, "
1399 "board rev %d.%d, chip rev %d.%d\n",
1400 board_rev >> 4, board_rev & 0xf,
1401 chip_rev >> 4, chip_rev & 0xf);
1402 if (chip_rev >= 0x20)
1403 slot->host->quirks |= SDHCI_QUIRK_FORCE_DMA;
1404
1405 writeb(SYSKT_POWER_330, slot->host->ioaddr + SYSKT_POWER_DATA);
1406 writeb(SYSKT_POWER_START, slot->host->ioaddr + SYSKT_POWER_CMD);
1407 udelay(50);
1408 tm = 10; /* Wait max 1 ms */
1409 do {
1410 ps = readw(slot->host->ioaddr + SYSKT_POWER_STATUS);
1411 if (ps & SYSKT_POWER_STATUS_OK)
1412 break;
1413 udelay(100);
1414 } while (--tm);
1415 if (!tm) {
1416 dev_err(&slot->chip->pdev->dev,
1417 "power regulator never stabilized");
1418 writeb(0, slot->host->ioaddr + SYSKT_POWER_CMD);
1419 return -ENODEV;
1420 }
1421
1422 return 0;
1423}
1424
1425static const struct sdhci_pci_fixes sdhci_syskt = {
1426 .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER,
1427 .probe = syskt_probe,
1428 .probe_slot = syskt_probe_slot,
1429};
1430
557b0697
HW		 1431static int via_probe(struct sdhci_pci_chip *chip)
1432{
1433 if (chip->pdev->revision == 0x10)
1434 chip->quirks |= SDHCI_QUIRK_DELAY_AFTER_POWER;
1435
1436 return 0;
1437}
1438
1439static const struct sdhci_pci_fixes sdhci_via = {
1440 .probe = via_probe,
1441};
1442
9107ebbf
MC		 1443static int rtsx_probe_slot(struct sdhci_pci_slot *slot)
1444{
1445 slot->host->mmc->caps2 |= MMC_CAP2_HS200;
1446 return 0;
1447}
1448
1449static const struct sdhci_pci_fixes sdhci_rtsx = {
1450 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
e30b978f 1451 SDHCI_QUIRK2_BROKEN_64_BIT_DMA |
9107ebbf
MC		 1452 SDHCI_QUIRK2_BROKEN_DDR50,
1453 .probe_slot = rtsx_probe_slot,
1454};
1455
b5e97d6e
VW		 1456/*AMD chipset generation*/
1457enum amd_chipset_gen {
1458 AMD_CHIPSET_BEFORE_ML,
1459 AMD_CHIPSET_CZ,
1460 AMD_CHIPSET_NL,
1461 AMD_CHIPSET_UNKNOWN,
1462};
1463
c31165d7
SS		 1464/* AMD registers */
1465#define AMD_SD_AUTO_PATTERN 0xB8
1466#define AMD_MSLEEP_DURATION 4
1467#define AMD_SD_MISC_CONTROL 0xD0
1468#define AMD_MAX_TUNE_VALUE 0x0B
1469#define AMD_AUTO_TUNE_SEL 0x10800
1470#define AMD_FIFO_PTR 0x30
1471#define AMD_BIT_MASK 0x1F
1472
1473static void amd_tuning_reset(struct sdhci_host *host)
1474{
1475 unsigned int val;
1476
1477 val = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1478 val |= SDHCI_CTRL_PRESET_VAL_ENABLE | SDHCI_CTRL_EXEC_TUNING;
1479 sdhci_writew(host, val, SDHCI_HOST_CONTROL2);
1480
1481 val = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1482 val &= ~SDHCI_CTRL_EXEC_TUNING;
1483 sdhci_writew(host, val, SDHCI_HOST_CONTROL2);
1484}
1485
1486static void amd_config_tuning_phase(struct pci_dev *pdev, u8 phase)
1487{
1488 unsigned int val;
1489
1490 pci_read_config_dword(pdev, AMD_SD_AUTO_PATTERN, &val);
1491 val &= ~AMD_BIT_MASK;
1492 val |= (AMD_AUTO_TUNE_SEL | (phase << 1));
1493 pci_write_config_dword(pdev, AMD_SD_AUTO_PATTERN, val);
1494}
1495
1496static void amd_enable_manual_tuning(struct pci_dev *pdev)
1497{
1498 unsigned int val;
1499
1500 pci_read_config_dword(pdev, AMD_SD_MISC_CONTROL, &val);
1501 val |= AMD_FIFO_PTR;
1502 pci_write_config_dword(pdev, AMD_SD_MISC_CONTROL, val);
1503}
1504
300ad899 1505static int amd_execute_tuning_hs200(struct sdhci_host *host, u32 opcode)
c31165d7
SS		 1506{
1507 struct sdhci_pci_slot *slot = sdhci_priv(host);
1508 struct pci_dev *pdev = slot->chip->pdev;
1509 u8 valid_win = 0;
1510 u8 valid_win_max = 0;
1511 u8 valid_win_end = 0;
1512 u8 ctrl, tune_around;
1513
1514 amd_tuning_reset(host);
1515
1516 for (tune_around = 0; tune_around < 12; tune_around++) {
1517 amd_config_tuning_phase(pdev, tune_around);
1518
1519 if (mmc_send_tuning(host->mmc, opcode, NULL)) {
1520 valid_win = 0;
1521 msleep(AMD_MSLEEP_DURATION);
1522 ctrl = SDHCI_RESET_CMD | SDHCI_RESET_DATA;
1523 sdhci_writeb(host, ctrl, SDHCI_SOFTWARE_RESET);
1524 } else if (++valid_win > valid_win_max) {
1525 valid_win_max = valid_win;
1526 valid_win_end = tune_around;
1527 }
1528 }
1529
1530 if (!valid_win_max) {
1531 dev_err(&pdev->dev, "no tuning point found\n");
1532 return -EIO;
1533 }
1534
1535 amd_config_tuning_phase(pdev, valid_win_end - valid_win_max / 2);
1536
1537 amd_enable_manual_tuning(pdev);
1538
1539 host->mmc->retune_period = 0;
1540
1541 return 0;
1542}
1543
300ad899
DK		 1544static int amd_execute_tuning(struct mmc_host *mmc, u32 opcode)
1545{
1546 struct sdhci_host *host = mmc_priv(mmc);
1547
1548 /* AMD requires custom HS200 tuning */
1549 if (host->timing == MMC_TIMING_MMC_HS200)
1550 return amd_execute_tuning_hs200(host, opcode);
1551
1552 /* Otherwise perform standard SDHCI tuning */
1553 return sdhci_execute_tuning(mmc, opcode);
1554}
1555
1556static int amd_probe_slot(struct sdhci_pci_slot *slot)
1557{
1558 struct mmc_host_ops *ops = &slot->host->mmc_host_ops;
1559
1560 ops->execute_tuning = amd_execute_tuning;
1561
1562 return 0;
1563}
1564
d44f88da
VW		 1565static int amd_probe(struct sdhci_pci_chip *chip)
1566{
1567 struct pci_dev *smbus_dev;
b5e97d6e 1568 enum amd_chipset_gen gen;
d44f88da
VW		 1569
1570 smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD,
1571 PCI_DEVICE_ID_AMD_HUDSON2_SMBUS, NULL);
b5e97d6e
VW		 1572 if (smbus_dev) {
1573 gen = AMD_CHIPSET_BEFORE_ML;
1574 } else {
1575 smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD,
1576 PCI_DEVICE_ID_AMD_KERNCZ_SMBUS, NULL);
1577 if (smbus_dev) {
1578 if (smbus_dev->revision < 0x51)
1579 gen = AMD_CHIPSET_CZ;
1580 else
1581 gen = AMD_CHIPSET_NL;
1582 } else {
1583 gen = AMD_CHIPSET_UNKNOWN;
1584 }
1585 }
d44f88da 1586
c31165d7 1587 if (gen == AMD_CHIPSET_BEFORE_ML || gen == AMD_CHIPSET_CZ)
d44f88da
VW		 1588 chip->quirks2 |= SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD;
1589
1590 return 0;
1591}
1592
c31165d7
SS		 1593static const struct sdhci_ops amd_sdhci_pci_ops = {
1594 .set_clock = sdhci_set_clock,
1595 .enable_dma = sdhci_pci_enable_dma,
adc16398 1596 .set_bus_width = sdhci_set_bus_width,
c31165d7
SS		 1597 .reset = sdhci_reset,
1598 .set_uhs_signaling = sdhci_set_uhs_signaling,
c31165d7
SS		 1599};
1600
d44f88da
VW		 1601static const struct sdhci_pci_fixes sdhci_amd = {
1602 .probe = amd_probe,
c31165d7 1603 .ops = &amd_sdhci_pci_ops,
300ad899 1604 .probe_slot = amd_probe_slot,
d44f88da
VW		 1605};
1606
9647f84d 1607static const struct pci_device_id pci_ids[] = {
c949c907
MK		 1608 SDHCI_PCI_DEVICE(RICOH, R5C822, ricoh),
1609 SDHCI_PCI_DEVICE(RICOH, R5C843, ricoh_mmc),
1610 SDHCI_PCI_DEVICE(RICOH, R5CE822, ricoh_mmc),
1611 SDHCI_PCI_DEVICE(RICOH, R5CE823, ricoh_mmc),
1612 SDHCI_PCI_DEVICE(ENE, CB712_SD, ene_712),
1613 SDHCI_PCI_DEVICE(ENE, CB712_SD_2, ene_712),
1614 SDHCI_PCI_DEVICE(ENE, CB714_SD, ene_714),
1615 SDHCI_PCI_DEVICE(ENE, CB714_SD_2, ene_714),
1616 SDHCI_PCI_DEVICE(MARVELL, 88ALP01_SD, cafe),
1617 SDHCI_PCI_DEVICE(JMICRON, JMB38X_SD, jmicron),
1618 SDHCI_PCI_DEVICE(JMICRON, JMB38X_MMC, jmicron),
1619 SDHCI_PCI_DEVICE(JMICRON, JMB388_SD, jmicron),
1620 SDHCI_PCI_DEVICE(JMICRON, JMB388_ESD, jmicron),
1621 SDHCI_PCI_DEVICE(SYSKONNECT, 8000, syskt),
1622 SDHCI_PCI_DEVICE(VIA, 95D0, via),
1623 SDHCI_PCI_DEVICE(REALTEK, 5250, rtsx),
1624 SDHCI_PCI_DEVICE(INTEL, QRK_SD, intel_qrk),
1625 SDHCI_PCI_DEVICE(INTEL, MRST_SD0, intel_mrst_hc0),
1626 SDHCI_PCI_DEVICE(INTEL, MRST_SD1, intel_mrst_hc1_hc2),
1627 SDHCI_PCI_DEVICE(INTEL, MRST_SD2, intel_mrst_hc1_hc2),
1628 SDHCI_PCI_DEVICE(INTEL, MFD_SD, intel_mfd_sd),
1629 SDHCI_PCI_DEVICE(INTEL, MFD_SDIO1, intel_mfd_sdio),
1630 SDHCI_PCI_DEVICE(INTEL, MFD_SDIO2, intel_mfd_sdio),
1631 SDHCI_PCI_DEVICE(INTEL, MFD_EMMC0, intel_mfd_emmc),
1632 SDHCI_PCI_DEVICE(INTEL, MFD_EMMC1, intel_mfd_emmc),
1633 SDHCI_PCI_DEVICE(INTEL, PCH_SDIO0, intel_pch_sdio),
1634 SDHCI_PCI_DEVICE(INTEL, PCH_SDIO1, intel_pch_sdio),
1635 SDHCI_PCI_DEVICE(INTEL, BYT_EMMC, intel_byt_emmc),
1636 SDHCI_PCI_SUBDEVICE(INTEL, BYT_SDIO, NI, 7884, ni_byt_sdio),
1637 SDHCI_PCI_DEVICE(INTEL, BYT_SDIO, intel_byt_sdio),
1638 SDHCI_PCI_DEVICE(INTEL, BYT_SD, intel_byt_sd),
1639 SDHCI_PCI_DEVICE(INTEL, BYT_EMMC2, intel_byt_emmc),
1640 SDHCI_PCI_DEVICE(INTEL, BSW_EMMC, intel_byt_emmc),
1641 SDHCI_PCI_DEVICE(INTEL, BSW_SDIO, intel_byt_sdio),
1642 SDHCI_PCI_DEVICE(INTEL, BSW_SD, intel_byt_sd),
1643 SDHCI_PCI_DEVICE(INTEL, CLV_SDIO0, intel_mfd_sd),
1644 SDHCI_PCI_DEVICE(INTEL, CLV_SDIO1, intel_mfd_sdio),
1645 SDHCI_PCI_DEVICE(INTEL, CLV_SDIO2, intel_mfd_sdio),
1646 SDHCI_PCI_DEVICE(INTEL, CLV_EMMC0, intel_mfd_emmc),
1647 SDHCI_PCI_DEVICE(INTEL, CLV_EMMC1, intel_mfd_emmc),
1648 SDHCI_PCI_DEVICE(INTEL, MRFLD_MMC, intel_mrfld_mmc),
1649 SDHCI_PCI_DEVICE(INTEL, SPT_EMMC, intel_byt_emmc),
1650 SDHCI_PCI_DEVICE(INTEL, SPT_SDIO, intel_byt_sdio),
1651 SDHCI_PCI_DEVICE(INTEL, SPT_SD, intel_byt_sd),
1652 SDHCI_PCI_DEVICE(INTEL, DNV_EMMC, intel_byt_emmc),
cdaba732 1653 SDHCI_PCI_DEVICE(INTEL, CDF_EMMC, intel_glk_emmc),
c949c907
MK		 1654 SDHCI_PCI_DEVICE(INTEL, BXT_EMMC, intel_byt_emmc),
1655 SDHCI_PCI_DEVICE(INTEL, BXT_SDIO, intel_byt_sdio),
1656 SDHCI_PCI_DEVICE(INTEL, BXT_SD, intel_byt_sd),
1657 SDHCI_PCI_DEVICE(INTEL, BXTM_EMMC, intel_byt_emmc),
1658 SDHCI_PCI_DEVICE(INTEL, BXTM_SDIO, intel_byt_sdio),
1659 SDHCI_PCI_DEVICE(INTEL, BXTM_SD, intel_byt_sd),
1660 SDHCI_PCI_DEVICE(INTEL, APL_EMMC, intel_byt_emmc),
1661 SDHCI_PCI_DEVICE(INTEL, APL_SDIO, intel_byt_sdio),
1662 SDHCI_PCI_DEVICE(INTEL, APL_SD, intel_byt_sd),
bc55dcd8 1663 SDHCI_PCI_DEVICE(INTEL, GLK_EMMC, intel_glk_emmc),
c949c907
MK		 1664 SDHCI_PCI_DEVICE(INTEL, GLK_SDIO, intel_byt_sdio),
1665 SDHCI_PCI_DEVICE(INTEL, GLK_SD, intel_byt_sd),
bc55dcd8
AH		 1666 SDHCI_PCI_DEVICE(INTEL, CNP_EMMC, intel_glk_emmc),
1667 SDHCI_PCI_DEVICE(INTEL, CNP_SD, intel_byt_sd),
1668 SDHCI_PCI_DEVICE(INTEL, CNPH_SD, intel_byt_sd),
5637ffad
AH		 1669 SDHCI_PCI_DEVICE(INTEL, ICP_EMMC, intel_glk_emmc),
1670 SDHCI_PCI_DEVICE(INTEL, ICP_SD, intel_byt_sd),
765c5967
AH		 1671 SDHCI_PCI_DEVICE(INTEL, CML_EMMC, intel_glk_emmc),
1672 SDHCI_PCI_DEVICE(INTEL, CML_SD, intel_byt_sd),
c949c907
MK		 1673 SDHCI_PCI_DEVICE(O2, 8120, o2),
1674 SDHCI_PCI_DEVICE(O2, 8220, o2),
1675 SDHCI_PCI_DEVICE(O2, 8221, o2),
1676 SDHCI_PCI_DEVICE(O2, 8320, o2),
1677 SDHCI_PCI_DEVICE(O2, 8321, o2),
1678 SDHCI_PCI_DEVICE(O2, FUJIN2, o2),
1679 SDHCI_PCI_DEVICE(O2, SDS0, o2),
1680 SDHCI_PCI_DEVICE(O2, SDS1, o2),
1681 SDHCI_PCI_DEVICE(O2, SEABIRD0, o2),
1682 SDHCI_PCI_DEVICE(O2, SEABIRD1, o2),
d72d72cd 1683 SDHCI_PCI_DEVICE(ARASAN, PHY_EMMC, arasan),
152f8204 1684 SDHCI_PCI_DEVICE(SYNOPSYS, DWC_MSHC, snps),
c949c907
MK		 1685 SDHCI_PCI_DEVICE_CLASS(AMD, SYSTEM_SDHCI, PCI_CLASS_MASK, amd),
1686 /* Generic SD host controller */
1687 {PCI_DEVICE_CLASS(SYSTEM_SDHCI, PCI_CLASS_MASK)},
b8c86fc5
PO		 1688 { /* end: all zeroes */ },
1689};
1690
1691MODULE_DEVICE_TABLE(pci, pci_ids);
1692
b8c86fc5
PO		 1693/*****************************************************************************\
1694 * *
1695 * SDHCI core callbacks *
1696 * *
1697\*****************************************************************************/
1698
d72d72cd 1699int sdhci_pci_enable_dma(struct sdhci_host *host)
b8c86fc5
PO		 1700{
1701 struct sdhci_pci_slot *slot;
1702 struct pci_dev *pdev;
b8c86fc5
PO		 1703
1704 slot = sdhci_priv(host);
1705 pdev = slot->chip->pdev;
1706
1707 if (((pdev->class & 0xFFFF00) == (PCI_CLASS_SYSTEM_SDHCI << 8)) &&
1708 ((pdev->class & 0x0000FF) != PCI_SDHCI_IFDMA) &&
a13abc7b 1709 (host->flags & SDHCI_USE_SDMA)) {
b8c86fc5
PO		 1710 dev_warn(&pdev->dev, "Will use DMA mode even though HW "
1711 "doesn't fully claim to support it.\n");
1712 }
1713
b8c86fc5
PO		 1714 pci_set_master(pdev);
1715
1716 return 0;
1717}
1718
c9faff6c 1719static void sdhci_pci_gpio_hw_reset(struct sdhci_host *host)
0f201655
AH		 1720{
1721 struct sdhci_pci_slot *slot = sdhci_priv(host);
1722 int rst_n_gpio = slot->rst_n_gpio;
1723
1724 if (!gpio_is_valid(rst_n_gpio))
1725 return;
1726 gpio_set_value_cansleep(rst_n_gpio, 0);
1727 /* For eMMC, minimum is 1us but give it 10us for good measure */
1728 udelay(10);
1729 gpio_set_value_cansleep(rst_n_gpio, 1);
1730 /* For eMMC, minimum is 200us but give it 300us for good measure */
1731 usleep_range(300, 1000);
1732}
1733
c9faff6c
AH		 1734static void sdhci_pci_hw_reset(struct sdhci_host *host)
1735{
1736 struct sdhci_pci_slot *slot = sdhci_priv(host);
1737
1738 if (slot->hw_reset)
1739 slot->hw_reset(host);
1740}
1741
c915568d 1742static const struct sdhci_ops sdhci_pci_ops = {
1771059c 1743 .set_clock = sdhci_set_clock,
b8c86fc5 1744 .enable_dma = sdhci_pci_enable_dma,
adc16398 1745 .set_bus_width = sdhci_set_bus_width,
03231f9b 1746 .reset = sdhci_reset,
96d7b78c 1747 .set_uhs_signaling = sdhci_set_uhs_signaling,
0f201655 1748 .hw_reset = sdhci_pci_hw_reset,
b8c86fc5
PO		 1749};
1750
1751/*****************************************************************************\
1752 * *
1753 * Suspend/resume *
1754 * *
1755\*****************************************************************************/
1756
f9900f15 1757#ifdef CONFIG_PM_SLEEP
29495aa0 1758static int sdhci_pci_suspend(struct device *dev)
b8c86fc5 1759{
29495aa0 1760 struct pci_dev *pdev = to_pci_dev(dev);
30cf2803 1761 struct sdhci_pci_chip *chip = pci_get_drvdata(pdev);
b8c86fc5 1762
b8c86fc5
PO		 1763 if (!chip)
1764 return 0;
1765
30cf2803
AH		 1766 if (chip->fixes && chip->fixes->suspend)
1767 return chip->fixes->suspend(chip);
b8c86fc5 1768
30cf2803 1769 return sdhci_pci_suspend_host(chip);
b8c86fc5
PO		 1770}
1771
29495aa0 1772static int sdhci_pci_resume(struct device *dev)
b8c86fc5 1773{
29495aa0 1774 struct pci_dev *pdev = to_pci_dev(dev);
30cf2803 1775 struct sdhci_pci_chip *chip = pci_get_drvdata(pdev);
b8c86fc5 1776
b8c86fc5
PO		 1777 if (!chip)
1778 return 0;
1779
30cf2803
AH		 1780 if (chip->fixes && chip->fixes->resume)
1781 return chip->fixes->resume(chip);
b8c86fc5 1782
30cf2803 1783 return sdhci_pci_resume_host(chip);
b8c86fc5 1784}
f9900f15 1785#endif
b8c86fc5 1786
f9900f15 1787#ifdef CONFIG_PM
66fd8ad5
AH		 1788static int sdhci_pci_runtime_suspend(struct device *dev)
1789{
923a231c 1790 struct pci_dev *pdev = to_pci_dev(dev);
966d696a 1791 struct sdhci_pci_chip *chip = pci_get_drvdata(pdev);
66fd8ad5 1792
66fd8ad5
AH		 1793 if (!chip)
1794 return 0;
1795
966d696a
AH		 1796 if (chip->fixes && chip->fixes->runtime_suspend)
1797 return chip->fixes->runtime_suspend(chip);
66fd8ad5 1798
966d696a 1799 return sdhci_pci_runtime_suspend_host(chip);
66fd8ad5
AH		 1800}
1801
1802static int sdhci_pci_runtime_resume(struct device *dev)
1803{
923a231c 1804 struct pci_dev *pdev = to_pci_dev(dev);
966d696a 1805 struct sdhci_pci_chip *chip = pci_get_drvdata(pdev);
66fd8ad5 1806
66fd8ad5
AH		 1807 if (!chip)
1808 return 0;
1809
966d696a
AH		 1810 if (chip->fixes && chip->fixes->runtime_resume)
1811 return chip->fixes->runtime_resume(chip);
66fd8ad5 1812
966d696a 1813 return sdhci_pci_runtime_resume_host(chip);
66fd8ad5 1814}
f9900f15 1815#endif
66fd8ad5
AH		 1816
1817static const struct dev_pm_ops sdhci_pci_pm_ops = {
f9900f15 1818 SET_SYSTEM_SLEEP_PM_OPS(sdhci_pci_suspend, sdhci_pci_resume)
f3a92b1a 1819 SET_RUNTIME_PM_OPS(sdhci_pci_runtime_suspend,
106276bb 1820 sdhci_pci_runtime_resume, NULL)
66fd8ad5
AH		 1821};
1822
b8c86fc5
PO		 1823/*****************************************************************************\
1824 * *
1825 * Device probing/removal *
1826 * *
1827\*****************************************************************************/
1828
c3be1efd 1829static struct sdhci_pci_slot *sdhci_pci_probe_slot(
52c506f0
AH		 1830 struct pci_dev *pdev, struct sdhci_pci_chip *chip, int first_bar,
1831 int slotno)
b8c86fc5
PO		 1832{
1833 struct sdhci_pci_slot *slot;
1834 struct sdhci_host *host;
52c506f0 1835 int ret, bar = first_bar + slotno;
ac9f67b5 1836 size_t priv_size = chip->fixes ? chip->fixes->priv_size : 0;
b8c86fc5
PO		 1837
1838 if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) {
1839 dev_err(&pdev->dev, "BAR %d is not iomem. Aborting.\n", bar);
1840 return ERR_PTR(-ENODEV);
1841 }
1842
90b3e6c5 1843 if (pci_resource_len(pdev, bar) < 0x100) {
b8c86fc5
PO		 1844 dev_err(&pdev->dev, "Invalid iomem size. You may "
1845 "experience problems.\n");
1846 }
1847
1848 if ((pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) {
1849 dev_err(&pdev->dev, "Vendor specific interface. Aborting.\n");
1850 return ERR_PTR(-ENODEV);
1851 }
1852
1853 if ((pdev->class & 0x0000FF) > PCI_SDHCI_IFVENDOR) {
1854 dev_err(&pdev->dev, "Unknown interface. Aborting.\n");
1855 return ERR_PTR(-ENODEV);
1856 }
1857
ac9f67b5 1858 host = sdhci_alloc_host(&pdev->dev, sizeof(*slot) + priv_size);
b8c86fc5 1859 if (IS_ERR(host)) {
c60a32cd 1860 dev_err(&pdev->dev, "cannot allocate host\n");
dc0fd7b5 1861 return ERR_CAST(host);
b8c86fc5
PO		 1862 }
1863
1864 slot = sdhci_priv(host);
1865
1866 slot->chip = chip;
1867 slot->host = host;
0f201655 1868 slot->rst_n_gpio = -EINVAL;
c5e027a4 1869 slot->cd_gpio = -EINVAL;
ff59c520 1870 slot->cd_idx = -1;
b8c86fc5 1871
52c506f0
AH		 1872 /* Retrieve platform data if there is any */
1873 if (*sdhci_pci_get_data)
1874 slot->data = sdhci_pci_get_data(pdev, slotno);
1875
1876 if (slot->data) {
1877 if (slot->data->setup) {
1878 ret = slot->data->setup(slot->data);
1879 if (ret) {
1880 dev_err(&pdev->dev, "platform setup failed\n");
1881 goto free;
1882 }
1883 }
c5e027a4
AH		 1884 slot->rst_n_gpio = slot->data->rst_n_gpio;
1885 slot->cd_gpio = slot->data->cd_gpio;
52c506f0
AH		 1886 }
1887
b8c86fc5 1888 host->hw_name = "PCI";
6bc09063
AH		 1889 host->ops = chip->fixes && chip->fixes->ops ?
1890 chip->fixes->ops :
1891 &sdhci_pci_ops;
b8c86fc5 1892 host->quirks = chip->quirks;
f3c55a7b 1893 host->quirks2 = chip->quirks2;
b8c86fc5
PO		 1894
1895 host->irq = pdev->irq;
1896
c10bc372 1897 ret = pcim_iomap_regions(pdev, BIT(bar), mmc_hostname(host->mmc));
b8c86fc5
PO		 1898 if (ret) {
1899 dev_err(&pdev->dev, "cannot request region\n");
52c506f0 1900 goto cleanup;
b8c86fc5
PO		 1901 }
1902
c10bc372 1903 host->ioaddr = pcim_iomap_table(pdev)[bar];
b8c86fc5 1904
4489428a
PO		 1905 if (chip->fixes && chip->fixes->probe_slot) {
1906 ret = chip->fixes->probe_slot(slot);
1907 if (ret)
c10bc372 1908 goto cleanup;
4489428a
PO		 1909 }
1910
c5e027a4 1911 if (gpio_is_valid(slot->rst_n_gpio)) {
c10bc372 1912 if (!devm_gpio_request(&pdev->dev, slot->rst_n_gpio, "eMMC_reset")) {
c5e027a4
AH		 1913 gpio_direction_output(slot->rst_n_gpio, 1);
1914 slot->host->mmc->caps |= MMC_CAP_HW_RESET;
c9faff6c 1915 slot->hw_reset = sdhci_pci_gpio_hw_reset;
c5e027a4
AH		 1916 } else {
1917 dev_warn(&pdev->dev, "failed to request rst_n_gpio\n");
1918 slot->rst_n_gpio = -EINVAL;
1919 }
1920 }
1921
e92cc35d 1922 host->mmc->pm_caps = MMC_PM_KEEP_POWER;
eed222ac 1923 host->mmc->slotno = slotno;
a08b17be 1924 host->mmc->caps2 |= MMC_CAP2_NO_PRESCAN_POWERUP;
2f4cbb3d 1925
e92cc35d
AH		 1926 if (device_can_wakeup(&pdev->dev))
1927 host->mmc->pm_caps |= MMC_PM_WAKE_SDIO_IRQ;
1928
d56ee1ff
AH		 1929 if (host->mmc->caps & MMC_CAP_CD_WAKE)
1930 device_init_wakeup(&pdev->dev, true);
1931
8f743d03 1932 if (slot->cd_idx >= 0) {
cdcefe6b 1933 ret = mmc_gpiod_request_cd(host->mmc, "cd", slot->cd_idx,
8f743d03 1934 slot->cd_override_level, 0, NULL);
cdcefe6b
RJ		 1935 if (ret && ret != -EPROBE_DEFER)
1936 ret = mmc_gpiod_request_cd(host->mmc, NULL,
1937 slot->cd_idx,
1938 slot->cd_override_level,
1939 0, NULL);
8f743d03
DB		 1940 if (ret == -EPROBE_DEFER)
1941 goto remove;
1942
1943 if (ret) {
1944 dev_warn(&pdev->dev, "failed to setup card detect gpio\n");
1945 slot->cd_idx = -1;
1946 }
ff59c520
AH		 1947 }
1948
61c951de
AH		 1949 if (chip->fixes && chip->fixes->add_host)
1950 ret = chip->fixes->add_host(slot);
1951 else
1952 ret = sdhci_add_host(host);
b8c86fc5 1953 if (ret)
4489428a 1954 goto remove;
b8c86fc5 1955
c5e027a4
AH		 1956 sdhci_pci_add_own_cd(slot);
1957
77a0122e
AH		 1958 /*
1959 * Check if the chip needs a separate GPIO for card detect to wake up
1960 * from runtime suspend. If it is not there, don't allow runtime PM.
1961 * Note sdhci_pci_add_own_cd() sets slot->cd_gpio to -EINVAL on failure.
1962 */
945be38c 1963 if (chip->fixes && chip->fixes->own_cd_for_runtime_pm &&
ff59c520 1964 !gpio_is_valid(slot->cd_gpio) && slot->cd_idx < 0)
77a0122e
AH		 1965 chip->allow_runtime_pm = false;
1966
b8c86fc5
PO		 1967 return slot;
1968
4489428a
PO		 1969remove:
1970 if (chip->fixes && chip->fixes->remove_slot)
1e72859e 1971 chip->fixes->remove_slot(slot, 0);
4489428a 1972
52c506f0
AH		 1973cleanup:
1974 if (slot->data && slot->data->cleanup)
1975 slot->data->cleanup(slot->data);
1976
c60a32cd 1977free:
b8c86fc5
PO		 1978 sdhci_free_host(host);
1979
1980 return ERR_PTR(ret);
1981}
1982
1983static void sdhci_pci_remove_slot(struct sdhci_pci_slot *slot)
1984{
1e72859e
PO		 1985 int dead;
1986 u32 scratch;
1987
c5e027a4
AH		 1988 sdhci_pci_remove_own_cd(slot);
1989
1e72859e
PO		 1990 dead = 0;
1991 scratch = readl(slot->host->ioaddr + SDHCI_INT_STATUS);
1992 if (scratch == (u32)-1)
1993 dead = 1;
1994
1995 sdhci_remove_host(slot->host, dead);
4489428a
PO		 1996
1997 if (slot->chip->fixes && slot->chip->fixes->remove_slot)
1e72859e 1998 slot->chip->fixes->remove_slot(slot, dead);
4489428a 1999
52c506f0
AH		 2000 if (slot->data && slot->data->cleanup)
2001 slot->data->cleanup(slot->data);
2002
b8c86fc5
PO		 2003 sdhci_free_host(slot->host);
2004}
2005
c3be1efd 2006static void sdhci_pci_runtime_pm_allow(struct device *dev)
66fd8ad5 2007{
00884b61 2008 pm_suspend_ignore_children(dev, 1);
66fd8ad5
AH		 2009 pm_runtime_set_autosuspend_delay(dev, 50);
2010 pm_runtime_use_autosuspend(dev);
00884b61
AH		 2011 pm_runtime_allow(dev);
2012 /* Stay active until mmc core scans for a card */
2013 pm_runtime_put_noidle(dev);
66fd8ad5
AH		 2014}
2015
6e0ee714 2016static void sdhci_pci_runtime_pm_forbid(struct device *dev)
66fd8ad5
AH		 2017{
2018 pm_runtime_forbid(dev);
2019 pm_runtime_get_noresume(dev);
2020}
2021
c3be1efd 2022static int sdhci_pci_probe(struct pci_dev *pdev,
b8c86fc5
PO		 2023 const struct pci_device_id *ent)
2024{
2025 struct sdhci_pci_chip *chip;
2026 struct sdhci_pci_slot *slot;
2027
cf5e23e1 2028 u8 slots, first_bar;
b8c86fc5
PO		 2029 int ret, i;
2030
2031 BUG_ON(pdev == NULL);
2032 BUG_ON(ent == NULL);
2033
b8c86fc5 2034 dev_info(&pdev->dev, "SDHCI controller found [%04x:%04x] (rev %x)\n",
cf5e23e1 2035 (int)pdev->vendor, (int)pdev->device, (int)pdev->revision);
b8c86fc5
PO		 2036
2037 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &slots);
2038 if (ret)
2039 return ret;
2040
2041 slots = PCI_SLOT_INFO_SLOTS(slots) + 1;
2042 dev_dbg(&pdev->dev, "found %d slot(s)\n", slots);
2043 if (slots == 0)
2044 return -ENODEV;
2045
2046 BUG_ON(slots > MAX_SLOTS);
2047
2048 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &first_bar);
2049 if (ret)
2050 return ret;
2051
2052 first_bar &= PCI_SLOT_INFO_FIRST_BAR_MASK;
2053
2054 if (first_bar > 5) {
2055 dev_err(&pdev->dev, "Invalid first BAR. Aborting.\n");
2056 return -ENODEV;
2057 }
2058
52ac7acf 2059 ret = pcim_enable_device(pdev);
b8c86fc5
PO		 2060 if (ret)
2061 return ret;
2062
52ac7acf
AS		 2063 chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL);
2064 if (!chip)
2065 return -ENOMEM;
b8c86fc5
PO		 2066
2067 chip->pdev = pdev;
b177bc91 2068 chip->fixes = (const struct sdhci_pci_fixes *)ent->driver_data;
c43fd774 2069 if (chip->fixes) {
22606405 2070 chip->quirks = chip->fixes->quirks;
f3c55a7b 2071 chip->quirks2 = chip->fixes->quirks2;
c43fd774
AH		 2072 chip->allow_runtime_pm = chip->fixes->allow_runtime_pm;
2073 }
b8c86fc5 2074 chip->num_slots = slots;
d38dcad4
AH		 2075 chip->pm_retune = true;
2076 chip->rpm_retune = true;
b8c86fc5
PO		 2077
2078 pci_set_drvdata(pdev, chip);
2079
22606405
PO		 2080 if (chip->fixes && chip->fixes->probe) {
2081 ret = chip->fixes->probe(chip);
2082 if (ret)
52ac7acf 2083 return ret;
22606405
PO		 2084 }
2085
225d85fe
AC		 2086 slots = chip->num_slots; /* Quirk may have changed this */
2087
b177bc91 2088 for (i = 0; i < slots; i++) {
52c506f0 2089 slot = sdhci_pci_probe_slot(pdev, chip, first_bar, i);
b8c86fc5 2090 if (IS_ERR(slot)) {
b177bc91 2091 for (i--; i >= 0; i--)
b8c86fc5 2092 sdhci_pci_remove_slot(chip->slots[i]);
52ac7acf 2093 return PTR_ERR(slot);
b8c86fc5
PO		 2094 }
2095
2096 chip->slots[i] = slot;
2097 }
2098
c43fd774
AH		 2099 if (chip->allow_runtime_pm)
2100 sdhci_pci_runtime_pm_allow(&pdev->dev);
66fd8ad5 2101
b8c86fc5 2102 return 0;
b8c86fc5
PO		 2103}
2104
6e0ee714 2105static void sdhci_pci_remove(struct pci_dev *pdev)
b8c86fc5
PO		 2106{
2107 int i;
52ac7acf 2108 struct sdhci_pci_chip *chip = pci_get_drvdata(pdev);
c43fd774 2109
52ac7acf
AS		 2110 if (chip->allow_runtime_pm)
2111 sdhci_pci_runtime_pm_forbid(&pdev->dev);
b8c86fc5 2112
52ac7acf
AS		 2113 for (i = 0; i < chip->num_slots; i++)
2114 sdhci_pci_remove_slot(chip->slots[i]);
b8c86fc5
PO		 2115}
2116
2117static struct pci_driver sdhci_driver = {
b177bc91 2118 .name = "sdhci-pci",
b8c86fc5 2119 .id_table = pci_ids,
b177bc91 2120 .probe = sdhci_pci_probe,
0433c143 2121 .remove = sdhci_pci_remove,
66fd8ad5
AH		 2122 .driver = {
2123 .pm = &sdhci_pci_pm_ops
2124 },
b8c86fc5
PO		 2125};
2126
acc69646 2127module_pci_driver(sdhci_driver);
b8c86fc5 2128
32710e8f 2129MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
b8c86fc5
PO		 2130MODULE_DESCRIPTION("Secure Digital Host Controller Interface PCI driver");
2131MODULE_LICENSE("GPL");
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