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mmc: sdhci: Rename sdhci_set_power() to sdhci_set_power_noreg()
[mirror_ubuntu-eoan-kernel.git] / drivers / mmc / host / sdhci-pci-core.c
CommitLineData
b8c86fc5
PO		 1/* linux/drivers/mmc/host/sdhci-pci.c - SDHCI on PCI bus interface
2 *
3 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or (at
8 * your option) any later version.
9 *
10 * Thanks to the following companies for their support:
11 *
12 * - JMicron (hardware and technical support)
13 */
14
15#include <linux/delay.h>
16#include <linux/highmem.h>
88b47679 17#include <linux/module.h>
b8c86fc5
PO		 18#include <linux/pci.h>
19#include <linux/dma-mapping.h>
5a0e3ad6 20#include <linux/slab.h>
ccc92c23 21#include <linux/device.h>
b8c86fc5 22#include <linux/mmc/host.h>
e1bfad6d 23#include <linux/mmc/mmc.h>
b177bc91
AP		 24#include <linux/scatterlist.h>
25#include <linux/io.h>
0f201655 26#include <linux/gpio.h>
66fd8ad5 27#include <linux/pm_runtime.h>
ff59c520 28#include <linux/mmc/slot-gpio.h>
52c506f0 29#include <linux/mmc/sdhci-pci-data.h>
b8c86fc5
PO		 30
31#include "sdhci.h"
522624f9 32#include "sdhci-pci.h"
01acf691 33#include "sdhci-pci-o2micro.h"
22606405
PO		 34
35/*****************************************************************************\
36 * *
37 * Hardware specific quirk handling *
38 * *
39\*****************************************************************************/
40
41static int ricoh_probe(struct sdhci_pci_chip *chip)
42{
c99436fb
CB		 43 if (chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG ||
44 chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SONY)
22606405 45 chip->quirks |= SDHCI_QUIRK_NO_CARD_NO_RESET;
ccc92c23
ML		 46 return 0;
47}
48
49static int ricoh_mmc_probe_slot(struct sdhci_pci_slot *slot)
50{
51 slot->host->caps =
52 ((0x21 << SDHCI_TIMEOUT_CLK_SHIFT)
53 & SDHCI_TIMEOUT_CLK_MASK) |
22606405 54
ccc92c23
ML		 55 ((0x21 << SDHCI_CLOCK_BASE_SHIFT)
56 & SDHCI_CLOCK_BASE_MASK) |
57
58 SDHCI_TIMEOUT_CLK_UNIT |
59 SDHCI_CAN_VDD_330 |
1a1f1f04 60 SDHCI_CAN_DO_HISPD |
ccc92c23
ML		 61 SDHCI_CAN_DO_SDMA;
62 return 0;
63}
64
65static int ricoh_mmc_resume(struct sdhci_pci_chip *chip)
66{
67 /* Apply a delay to allow controller to settle */
68 /* Otherwise it becomes confused if card state changed
69 during suspend */
70 msleep(500);
22606405
PO		 71 return 0;
72}
73
74static const struct sdhci_pci_fixes sdhci_ricoh = {
75 .probe = ricoh_probe,
84938294
VK		 76 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR |
77 SDHCI_QUIRK_FORCE_DMA |
78 SDHCI_QUIRK_CLOCK_BEFORE_RESET,
22606405
PO		 79};
80
ccc92c23
ML		 81static const struct sdhci_pci_fixes sdhci_ricoh_mmc = {
82 .probe_slot = ricoh_mmc_probe_slot,
83 .resume = ricoh_mmc_resume,
84 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR |
85 SDHCI_QUIRK_CLOCK_BEFORE_RESET |
86 SDHCI_QUIRK_NO_CARD_NO_RESET |
87 SDHCI_QUIRK_MISSING_CAPS
88};
89
22606405
PO		 90static const struct sdhci_pci_fixes sdhci_ene_712 = {
91 .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE |
92 SDHCI_QUIRK_BROKEN_DMA,
93};
94
95static const struct sdhci_pci_fixes sdhci_ene_714 = {
96 .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE |
97 SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS |
98 SDHCI_QUIRK_BROKEN_DMA,
99};
100
101static const struct sdhci_pci_fixes sdhci_cafe = {
102 .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER |
a0874897 103 SDHCI_QUIRK_NO_BUSY_IRQ |
55fc05b7 104 SDHCI_QUIRK_BROKEN_CARD_DETECTION |
ee53ab5d 105 SDHCI_QUIRK_BROKEN_TIMEOUT_VAL,
22606405
PO		 106};
107
43e968ce
DB		 108static const struct sdhci_pci_fixes sdhci_intel_qrk = {
109 .quirks = SDHCI_QUIRK_NO_HISPD_BIT,
110};
111
68077b02
ML		 112static int mrst_hc_probe_slot(struct sdhci_pci_slot *slot)
113{
114 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA;
115 return 0;
116}
117
f9ee3eab
AC		 118/*
119 * ADMA operation is disabled for Moorestown platform due to
120 * hardware bugs.
121 */
35ac6f08 122static int mrst_hc_probe(struct sdhci_pci_chip *chip)
f9ee3eab
AC		 123{
124 /*
35ac6f08
JP		 125 * slots number is fixed here for MRST as SDIO3/5 are never used and
126 * have hardware bugs.
f9ee3eab
AC		 127 */
128 chip->num_slots = 1;
129 return 0;
130}
131
296e0b03
AS		 132static int pch_hc_probe_slot(struct sdhci_pci_slot *slot)
133{
134 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA;
135 return 0;
136}
137
162d6f98 138#ifdef CONFIG_PM
66fd8ad5 139
c5e027a4 140static irqreturn_t sdhci_pci_sd_cd(int irq, void *dev_id)
66fd8ad5
AH		 141{
142 struct sdhci_pci_slot *slot = dev_id;
143 struct sdhci_host *host = slot->host;
144
145 mmc_detect_change(host->mmc, msecs_to_jiffies(200));
146 return IRQ_HANDLED;
147}
148
c5e027a4 149static void sdhci_pci_add_own_cd(struct sdhci_pci_slot *slot)
66fd8ad5 150{
c5e027a4 151 int err, irq, gpio = slot->cd_gpio;
66fd8ad5
AH		 152
153 slot->cd_gpio = -EINVAL;
154 slot->cd_irq = -EINVAL;
155
c5e027a4
AH		 156 if (!gpio_is_valid(gpio))
157 return;
158
c10bc372 159 err = devm_gpio_request(&slot->chip->pdev->dev, gpio, "sd_cd");
66fd8ad5
AH		 160 if (err < 0)
161 goto out;
162
163 err = gpio_direction_input(gpio);
164 if (err < 0)
165 goto out_free;
166
167 irq = gpio_to_irq(gpio);
168 if (irq < 0)
169 goto out_free;
170
c5e027a4 171 err = request_irq(irq, sdhci_pci_sd_cd, IRQF_TRIGGER_RISING |
66fd8ad5
AH		 172 IRQF_TRIGGER_FALLING, "sd_cd", slot);
173 if (err)
174 goto out_free;
175
176 slot->cd_gpio = gpio;
177 slot->cd_irq = irq;
66fd8ad5 178
c5e027a4 179 return;
66fd8ad5
AH		 180
181out_free:
c10bc372 182 devm_gpio_free(&slot->chip->pdev->dev, gpio);
66fd8ad5
AH		 183out:
184 dev_warn(&slot->chip->pdev->dev, "failed to setup card detect wake up\n");
66fd8ad5
AH		 185}
186
c5e027a4 187static void sdhci_pci_remove_own_cd(struct sdhci_pci_slot *slot)
66fd8ad5
AH		 188{
189 if (slot->cd_irq >= 0)
190 free_irq(slot->cd_irq, slot);
66fd8ad5
AH		 191}
192
193#else
194
c5e027a4
AH		 195static inline void sdhci_pci_add_own_cd(struct sdhci_pci_slot *slot)
196{
197}
198
199static inline void sdhci_pci_remove_own_cd(struct sdhci_pci_slot *slot)
200{
201}
66fd8ad5
AH		 202
203#endif
204
0d013bcf
AH		 205static int mfd_emmc_probe_slot(struct sdhci_pci_slot *slot)
206{
66fd8ad5 207 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE;
da721cf7
AH		 208 slot->host->mmc->caps2 |= MMC_CAP2_BOOTPART_NOACC |
209 MMC_CAP2_HC_ERASE_SZ;
0d013bcf
AH		 210 return 0;
211}
212
93933508
AH		 213static int mfd_sdio_probe_slot(struct sdhci_pci_slot *slot)
214{
012e4671 215 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE;
93933508
AH		 216 return 0;
217}
218
f9ee3eab
AC		 219static const struct sdhci_pci_fixes sdhci_intel_mrst_hc0 = {
220 .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT,
68077b02 221 .probe_slot = mrst_hc_probe_slot,
f9ee3eab
AC		 222};
223
35ac6f08 224static const struct sdhci_pci_fixes sdhci_intel_mrst_hc1_hc2 = {
f9ee3eab 225 .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT,
35ac6f08 226 .probe = mrst_hc_probe,
f9ee3eab
AC		 227};
228
29229052
XS		 229static const struct sdhci_pci_fixes sdhci_intel_mfd_sd = {
230 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
c43fd774 231 .allow_runtime_pm = true,
77a0122e 232 .own_cd_for_runtime_pm = true,
29229052
XS		 233};
234
0d013bcf
AH		 235static const struct sdhci_pci_fixes sdhci_intel_mfd_sdio = {
236 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
f3c55a7b 237 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON,
c43fd774 238 .allow_runtime_pm = true,
93933508 239 .probe_slot = mfd_sdio_probe_slot,
0d013bcf
AH		 240};
241
242static const struct sdhci_pci_fixes sdhci_intel_mfd_emmc = {
29229052 243 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
c43fd774 244 .allow_runtime_pm = true,
0d013bcf 245 .probe_slot = mfd_emmc_probe_slot,
29229052
XS		 246};
247
296e0b03
AS		 248static const struct sdhci_pci_fixes sdhci_intel_pch_sdio = {
249 .quirks = SDHCI_QUIRK_BROKEN_ADMA,
250 .probe_slot = pch_hc_probe_slot,
251};
252
c9faff6c
AH		 253static void sdhci_pci_int_hw_reset(struct sdhci_host *host)
254{
255 u8 reg;
256
257 reg = sdhci_readb(host, SDHCI_POWER_CONTROL);
258 reg |= 0x10;
259 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL);
260 /* For eMMC, minimum is 1us but give it 9us for good measure */
261 udelay(9);
262 reg &= ~0x10;
263 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL);
264 /* For eMMC, minimum is 200us but give it 300us for good measure */
265 usleep_range(300, 1000);
266}
267
e1bfad6d
AH		 268static int spt_select_drive_strength(struct sdhci_host *host,
269 struct mmc_card *card,
270 unsigned int max_dtr,
271 int host_drv, int card_drv, int *drv_type)
272{
273 int drive_strength;
274
275 if (sdhci_pci_spt_drive_strength > 0)
276 drive_strength = sdhci_pci_spt_drive_strength & 0xf;
277 else
1ca89685 278 drive_strength = 0; /* Default 50-ohm */
e1bfad6d
AH		 279
280 if ((mmc_driver_type_mask(drive_strength) & card_drv) == 0)
281 drive_strength = 0; /* Default 50-ohm */
282
283 return drive_strength;
284}
285
286/* Try to read the drive strength from the card */
287static void spt_read_drive_strength(struct sdhci_host *host)
288{
289 u32 val, i, t;
290 u16 m;
291
292 if (sdhci_pci_spt_drive_strength)
293 return;
294
295 sdhci_pci_spt_drive_strength = -1;
296
297 m = sdhci_readw(host, SDHCI_HOST_CONTROL2) & 0x7;
298 if (m != 3 && m != 5)
299 return;
300 val = sdhci_readl(host, SDHCI_PRESENT_STATE);
301 if (val & 0x3)
302 return;
303 sdhci_writel(host, 0x007f0023, SDHCI_INT_ENABLE);
304 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
305 sdhci_writew(host, 0x10, SDHCI_TRANSFER_MODE);
306 sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL);
307 sdhci_writew(host, 512, SDHCI_BLOCK_SIZE);
308 sdhci_writew(host, 1, SDHCI_BLOCK_COUNT);
309 sdhci_writel(host, 0, SDHCI_ARGUMENT);
310 sdhci_writew(host, 0x83b, SDHCI_COMMAND);
311 for (i = 0; i < 1000; i++) {
312 val = sdhci_readl(host, SDHCI_INT_STATUS);
313 if (val & 0xffff8000)
314 return;
315 if (val & 0x20)
316 break;
317 udelay(1);
318 }
319 val = sdhci_readl(host, SDHCI_PRESENT_STATE);
320 if (!(val & 0x800))
321 return;
322 for (i = 0; i < 47; i++)
323 val = sdhci_readl(host, SDHCI_BUFFER);
324 t = val & 0xf00;
325 if (t != 0x200 && t != 0x300)
326 return;
327
328 sdhci_pci_spt_drive_strength = 0x10 | ((val >> 12) & 0xf);
329}
330
163cbe31
AH		 331static int bxt_get_cd(struct mmc_host *mmc)
332{
333 int gpio_cd = mmc_gpio_get_cd(mmc);
334 struct sdhci_host *host = mmc_priv(mmc);
335 unsigned long flags;
336 int ret = 0;
337
338 if (!gpio_cd)
339 return 0;
340
163cbe31
AH		 341 spin_lock_irqsave(&host->lock, flags);
342
343 if (host->flags & SDHCI_DEVICE_DEAD)
344 goto out;
345
346 ret = !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
347out:
348 spin_unlock_irqrestore(&host->lock, flags);
349
163cbe31
AH		 350 return ret;
351}
352
728ef3d1
AH		 353static int byt_emmc_probe_slot(struct sdhci_pci_slot *slot)
354{
c9faff6c 355 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE |
6aab23a8 356 MMC_CAP_HW_RESET | MMC_CAP_1_8V_DDR |
32828857 357 MMC_CAP_CMD_DURING_TFR |
6aab23a8 358 MMC_CAP_WAIT_WHILE_BUSY;
728ef3d1 359 slot->host->mmc->caps2 |= MMC_CAP2_HC_ERASE_SZ;
c9faff6c 360 slot->hw_reset = sdhci_pci_int_hw_reset;
a06586b6
AH		 361 if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BSW_EMMC)
362 slot->host->timeout_clk = 1000; /* 1000 kHz i.e. 1 MHz */
e1bfad6d
AH		 363 if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_SPT_EMMC) {
364 spt_read_drive_strength(slot->host);
365 slot->select_drive_strength = spt_select_drive_strength;
366 }
728ef3d1
AH		 367 return 0;
368}
369
370static int byt_sdio_probe_slot(struct sdhci_pci_slot *slot)
371{
6aab23a8 372 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE |
6aab23a8 373 MMC_CAP_WAIT_WHILE_BUSY;
728ef3d1
AH		 374 return 0;
375}
376
ff59c520
AH		 377static int byt_sd_probe_slot(struct sdhci_pci_slot *slot)
378{
82296936 379 slot->host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY;
ff59c520
AH		 380 slot->cd_con_id = NULL;
381 slot->cd_idx = 0;
382 slot->cd_override_level = true;
163cbe31 383 if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BXT_SD ||
01d6b2a4 384 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BXTM_SD ||
e8ef5176 385 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_APL_SD) {
163cbe31 386 slot->host->mmc_host_ops.get_cd = bxt_get_cd;
e8ef5176
AH		 387 slot->host->mmc->caps |= MMC_CAP_AGGRESSIVE_PM;
388 }
163cbe31 389
ff59c520
AH		 390 return 0;
391}
392
728ef3d1
AH		 393static const struct sdhci_pci_fixes sdhci_intel_byt_emmc = {
394 .allow_runtime_pm = true,
395 .probe_slot = byt_emmc_probe_slot,
db6e8cdf 396 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
e58e4a0d 397 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
b69587e2 398 SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 |
e58e4a0d 399 SDHCI_QUIRK2_STOP_WITH_TC,
728ef3d1
AH		 400};
401
402static const struct sdhci_pci_fixes sdhci_intel_byt_sdio = {
db6e8cdf 403 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
b7574bad
GY		 404 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON |
405 SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
728ef3d1
AH		 406 .allow_runtime_pm = true,
407 .probe_slot = byt_sdio_probe_slot,
408};
409
410static const struct sdhci_pci_fixes sdhci_intel_byt_sd = {
db6e8cdf 411 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
b7574bad 412 .quirks2 = SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON |
e58e4a0d
AH		 413 SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
414 SDHCI_QUIRK2_STOP_WITH_TC,
7396e318 415 .allow_runtime_pm = true,
77a0122e 416 .own_cd_for_runtime_pm = true,
ff59c520 417 .probe_slot = byt_sd_probe_slot,
728ef3d1
AH		 418};
419
8776a165 420/* Define Host controllers for Intel Merrifield platform */
1f64cec2
AS		 421#define INTEL_MRFLD_EMMC_0 0
422#define INTEL_MRFLD_EMMC_1 1
4674b6c8 423#define INTEL_MRFLD_SD 2
d5565577 424#define INTEL_MRFLD_SDIO 3
8776a165 425
1f64cec2 426static int intel_mrfld_mmc_probe_slot(struct sdhci_pci_slot *slot)
8776a165 427{
2e57bbe2
AS		 428 unsigned int func = PCI_FUNC(slot->chip->pdev->devfn);
429
430 switch (func) {
431 case INTEL_MRFLD_EMMC_0:
432 case INTEL_MRFLD_EMMC_1:
433 slot->host->mmc->caps |= MMC_CAP_NONREMOVABLE |
434 MMC_CAP_8_BIT_DATA |
435 MMC_CAP_1_8V_DDR;
436 break;
4674b6c8
AS		 437 case INTEL_MRFLD_SD:
438 slot->host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V;
439 break;
d5565577
AS		 440 case INTEL_MRFLD_SDIO:
441 slot->host->mmc->caps |= MMC_CAP_NONREMOVABLE |
442 MMC_CAP_POWER_OFF_CARD;
443 break;
2e57bbe2 444 default:
8776a165 445 return -ENODEV;
2e57bbe2 446 }
8776a165
DC		 447 return 0;
448}
449
1f64cec2 450static const struct sdhci_pci_fixes sdhci_intel_mrfld_mmc = {
8776a165 451 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
b7574bad
GY		 452 .quirks2 = SDHCI_QUIRK2_BROKEN_HS200 |
453 SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
f1b55a55 454 .allow_runtime_pm = true,
1f64cec2 455 .probe_slot = intel_mrfld_mmc_probe_slot,
8776a165
DC		 456};
457
26daa1ed
JL		 458/* O2Micro extra registers */
459#define O2_SD_LOCK_WP 0xD3
460#define O2_SD_MULTI_VCC3V 0xEE
461#define O2_SD_CLKREQ 0xEC
462#define O2_SD_CAPS 0xE0
463#define O2_SD_ADMA1 0xE2
464#define O2_SD_ADMA2 0xE7
465#define O2_SD_INF_MOD 0xF1
466
45211e21
PO		 467static int jmicron_pmos(struct sdhci_pci_chip *chip, int on)
468{
469 u8 scratch;
470 int ret;
471
472 ret = pci_read_config_byte(chip->pdev, 0xAE, &scratch);
473 if (ret)
474 return ret;
475
476 /*
477 * Turn PMOS on [bit 0], set over current detection to 2.4 V
478 * [bit 1:2] and enable over current debouncing [bit 6].
479 */
480 if (on)
481 scratch |= 0x47;
482 else
483 scratch &= ~0x47;
484
7582041f 485 return pci_write_config_byte(chip->pdev, 0xAE, scratch);
45211e21
PO		 486}
487
488static int jmicron_probe(struct sdhci_pci_chip *chip)
489{
490 int ret;
8f230f45 491 u16 mmcdev = 0;
45211e21 492
93fc48c7
PO		 493 if (chip->pdev->revision == 0) {
494 chip->quirks |= SDHCI_QUIRK_32BIT_DMA_ADDR |
495 SDHCI_QUIRK_32BIT_DMA_SIZE |
2134a922 496 SDHCI_QUIRK_32BIT_ADMA_SIZE |
4a3cba32 497 SDHCI_QUIRK_RESET_AFTER_REQUEST |
86a6a874 498 SDHCI_QUIRK_BROKEN_SMALL_PIO;
93fc48c7
PO		 499 }
500
4489428a
PO		 501 /*
502 * JMicron chips can have two interfaces to the same hardware
503 * in order to work around limitations in Microsoft's driver.
504 * We need to make sure we only bind to one of them.
505 *
506 * This code assumes two things:
507 *
508 * 1. The PCI code adds subfunctions in order.
509 *
510 * 2. The MMC interface has a lower subfunction number
511 * than the SD interface.
512 */
8f230f45
TI		 513 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_SD)
514 mmcdev = PCI_DEVICE_ID_JMICRON_JMB38X_MMC;
515 else if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD)
516 mmcdev = PCI_DEVICE_ID_JMICRON_JMB388_ESD;
517
518 if (mmcdev) {
4489428a
PO		 519 struct pci_dev *sd_dev;
520
521 sd_dev = NULL;
522 while ((sd_dev = pci_get_device(PCI_VENDOR_ID_JMICRON,
8f230f45 523 mmcdev, sd_dev)) != NULL) {
4489428a
PO		 524 if ((PCI_SLOT(chip->pdev->devfn) ==
525 PCI_SLOT(sd_dev->devfn)) &&
526 (chip->pdev->bus == sd_dev->bus))
527 break;
528 }
529
530 if (sd_dev) {
531 pci_dev_put(sd_dev);
532 dev_info(&chip->pdev->dev, "Refusing to bind to "
533 "secondary interface.\n");
534 return -ENODEV;
535 }
536 }
537
45211e21
PO		 538 /*
539 * JMicron chips need a bit of a nudge to enable the power
540 * output pins.
541 */
542 ret = jmicron_pmos(chip, 1);
543 if (ret) {
544 dev_err(&chip->pdev->dev, "Failure enabling card power\n");
545 return ret;
546 }
547
82b0e23a
TI		 548 /* quirk for unsable RO-detection on JM388 chips */
549 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD ||
550 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD)
551 chip->quirks |= SDHCI_QUIRK_UNSTABLE_RO_DETECT;
552
45211e21
PO		 553 return 0;
554}
555
4489428a
PO		 556static void jmicron_enable_mmc(struct sdhci_host *host, int on)
557{
558 u8 scratch;
559
560 scratch = readb(host->ioaddr + 0xC0);
561
562 if (on)
563 scratch |= 0x01;
564 else
565 scratch &= ~0x01;
566
567 writeb(scratch, host->ioaddr + 0xC0);
568}
569
570static int jmicron_probe_slot(struct sdhci_pci_slot *slot)
571{
2134a922
PO		 572 if (slot->chip->pdev->revision == 0) {
573 u16 version;
574
575 version = readl(slot->host->ioaddr + SDHCI_HOST_VERSION);
576 version = (version & SDHCI_VENDOR_VER_MASK) >>
577 SDHCI_VENDOR_VER_SHIFT;
578
579 /*
580 * Older versions of the chip have lots of nasty glitches
581 * in the ADMA engine. It's best just to avoid it
582 * completely.
583 */
584 if (version < 0xAC)
585 slot->host->quirks |= SDHCI_QUIRK_BROKEN_ADMA;
586 }
587
8f230f45
TI		 588 /* JM388 MMC doesn't support 1.8V while SD supports it */
589 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) {
590 slot->host->ocr_avail_sd = MMC_VDD_32_33 | MMC_VDD_33_34 |
591 MMC_VDD_29_30 | MMC_VDD_30_31 |
592 MMC_VDD_165_195; /* allow 1.8V */
593 slot->host->ocr_avail_mmc = MMC_VDD_32_33 | MMC_VDD_33_34 |
594 MMC_VDD_29_30 | MMC_VDD_30_31; /* no 1.8V for MMC */
595 }
596
4489428a
PO		 597 /*
598 * The secondary interface requires a bit set to get the
599 * interrupts.
600 */
8f230f45
TI		 601 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
602 slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD)
4489428a
PO		 603 jmicron_enable_mmc(slot->host, 1);
604
d75c1084
TI		 605 slot->host->mmc->caps |= MMC_CAP_BUS_WIDTH_TEST;
606
4489428a
PO		 607 return 0;
608}
609
1e72859e 610static void jmicron_remove_slot(struct sdhci_pci_slot *slot, int dead)
4489428a 611{
1e72859e
PO		 612 if (dead)
613 return;
614
8f230f45
TI		 615 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
616 slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD)
4489428a
PO		 617 jmicron_enable_mmc(slot->host, 0);
618}
619
29495aa0 620static int jmicron_suspend(struct sdhci_pci_chip *chip)
4489428a
PO		 621{
622 int i;
623
8f230f45
TI		 624 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
625 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) {
b177bc91 626 for (i = 0; i < chip->num_slots; i++)
4489428a
PO		 627 jmicron_enable_mmc(chip->slots[i]->host, 0);
628 }
629
630 return 0;
631}
632
45211e21
PO		 633static int jmicron_resume(struct sdhci_pci_chip *chip)
634{
4489428a
PO		 635 int ret, i;
636
8f230f45
TI		 637 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
638 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) {
b177bc91 639 for (i = 0; i < chip->num_slots; i++)
4489428a
PO		 640 jmicron_enable_mmc(chip->slots[i]->host, 1);
641 }
45211e21
PO		 642
643 ret = jmicron_pmos(chip, 1);
644 if (ret) {
645 dev_err(&chip->pdev->dev, "Failure enabling card power\n");
646 return ret;
647 }
648
649 return 0;
650}
651
26daa1ed 652static const struct sdhci_pci_fixes sdhci_o2 = {
01acf691
AL		 653 .probe = sdhci_pci_o2_probe,
654 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
143b648d 655 .quirks2 = SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD,
01acf691
AL		 656 .probe_slot = sdhci_pci_o2_probe_slot,
657 .resume = sdhci_pci_o2_resume,
26daa1ed
JL		 658};
659
22606405 660static const struct sdhci_pci_fixes sdhci_jmicron = {
45211e21
PO		 661 .probe = jmicron_probe,
662
4489428a
PO		 663 .probe_slot = jmicron_probe_slot,
664 .remove_slot = jmicron_remove_slot,
665
666 .suspend = jmicron_suspend,
45211e21 667 .resume = jmicron_resume,
22606405
PO		 668};
669
a7a6186c
NP		 670/* SysKonnect CardBus2SDIO extra registers */
671#define SYSKT_CTRL 0x200
672#define SYSKT_RDFIFO_STAT 0x204
673#define SYSKT_WRFIFO_STAT 0x208
674#define SYSKT_POWER_DATA 0x20c
675#define SYSKT_POWER_330 0xef
676#define SYSKT_POWER_300 0xf8
677#define SYSKT_POWER_184 0xcc
678#define SYSKT_POWER_CMD 0x20d
679#define SYSKT_POWER_START (1 << 7)
680#define SYSKT_POWER_STATUS 0x20e
681#define SYSKT_POWER_STATUS_OK (1 << 0)
682#define SYSKT_BOARD_REV 0x210
683#define SYSKT_CHIP_REV 0x211
684#define SYSKT_CONF_DATA 0x212
685#define SYSKT_CONF_DATA_1V8 (1 << 2)
686#define SYSKT_CONF_DATA_2V5 (1 << 1)
687#define SYSKT_CONF_DATA_3V3 (1 << 0)
688
689static int syskt_probe(struct sdhci_pci_chip *chip)
690{
691 if ((chip->pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) {
692 chip->pdev->class &= ~0x0000FF;
693 chip->pdev->class |= PCI_SDHCI_IFDMA;
694 }
695 return 0;
696}
697
698static int syskt_probe_slot(struct sdhci_pci_slot *slot)
699{
700 int tm, ps;
701
702 u8 board_rev = readb(slot->host->ioaddr + SYSKT_BOARD_REV);
703 u8 chip_rev = readb(slot->host->ioaddr + SYSKT_CHIP_REV);
704 dev_info(&slot->chip->pdev->dev, "SysKonnect CardBus2SDIO, "
705 "board rev %d.%d, chip rev %d.%d\n",
706 board_rev >> 4, board_rev & 0xf,
707 chip_rev >> 4, chip_rev & 0xf);
708 if (chip_rev >= 0x20)
709 slot->host->quirks |= SDHCI_QUIRK_FORCE_DMA;
710
711 writeb(SYSKT_POWER_330, slot->host->ioaddr + SYSKT_POWER_DATA);
712 writeb(SYSKT_POWER_START, slot->host->ioaddr + SYSKT_POWER_CMD);
713 udelay(50);
714 tm = 10; /* Wait max 1 ms */
715 do {
716 ps = readw(slot->host->ioaddr + SYSKT_POWER_STATUS);
717 if (ps & SYSKT_POWER_STATUS_OK)
718 break;
719 udelay(100);
720 } while (--tm);
721 if (!tm) {
722 dev_err(&slot->chip->pdev->dev,
723 "power regulator never stabilized");
724 writeb(0, slot->host->ioaddr + SYSKT_POWER_CMD);
725 return -ENODEV;
726 }
727
728 return 0;
729}
730
731static const struct sdhci_pci_fixes sdhci_syskt = {
732 .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER,
733 .probe = syskt_probe,
734 .probe_slot = syskt_probe_slot,
735};
736
557b0697
HW		 737static int via_probe(struct sdhci_pci_chip *chip)
738{
739 if (chip->pdev->revision == 0x10)
740 chip->quirks |= SDHCI_QUIRK_DELAY_AFTER_POWER;
741
742 return 0;
743}
744
745static const struct sdhci_pci_fixes sdhci_via = {
746 .probe = via_probe,
747};
748
9107ebbf
MC		 749static int rtsx_probe_slot(struct sdhci_pci_slot *slot)
750{
751 slot->host->mmc->caps2 |= MMC_CAP2_HS200;
752 return 0;
753}
754
755static const struct sdhci_pci_fixes sdhci_rtsx = {
756 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
e30b978f 757 SDHCI_QUIRK2_BROKEN_64_BIT_DMA |
9107ebbf
MC		 758 SDHCI_QUIRK2_BROKEN_DDR50,
759 .probe_slot = rtsx_probe_slot,
760};
761
b5e97d6e
VW		 762/*AMD chipset generation*/
763enum amd_chipset_gen {
764 AMD_CHIPSET_BEFORE_ML,
765 AMD_CHIPSET_CZ,
766 AMD_CHIPSET_NL,
767 AMD_CHIPSET_UNKNOWN,
768};
769
d44f88da
VW		 770static int amd_probe(struct sdhci_pci_chip *chip)
771{
772 struct pci_dev *smbus_dev;
b5e97d6e 773 enum amd_chipset_gen gen;
d44f88da
VW		 774
775 smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD,
776 PCI_DEVICE_ID_AMD_HUDSON2_SMBUS, NULL);
b5e97d6e
VW		 777 if (smbus_dev) {
778 gen = AMD_CHIPSET_BEFORE_ML;
779 } else {
780 smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD,
781 PCI_DEVICE_ID_AMD_KERNCZ_SMBUS, NULL);
782 if (smbus_dev) {
783 if (smbus_dev->revision < 0x51)
784 gen = AMD_CHIPSET_CZ;
785 else
786 gen = AMD_CHIPSET_NL;
787 } else {
788 gen = AMD_CHIPSET_UNKNOWN;
789 }
790 }
d44f88da 791
b5e97d6e 792 if ((gen == AMD_CHIPSET_BEFORE_ML) || (gen == AMD_CHIPSET_CZ)) {
d44f88da 793 chip->quirks2 |= SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD;
e765bfa2
VW		 794 chip->quirks2 |= SDHCI_QUIRK2_BROKEN_HS200;
795 }
d44f88da
VW		 796
797 return 0;
798}
799
800static const struct sdhci_pci_fixes sdhci_amd = {
801 .probe = amd_probe,
802};
803
9647f84d 804static const struct pci_device_id pci_ids[] = {
b8c86fc5
PO		 805 {
806 .vendor = PCI_VENDOR_ID_RICOH,
807 .device = PCI_DEVICE_ID_RICOH_R5C822,
22606405 808 .subvendor = PCI_ANY_ID,
b8c86fc5 809 .subdevice = PCI_ANY_ID,
22606405 810 .driver_data = (kernel_ulong_t)&sdhci_ricoh,
b8c86fc5
PO		 811 },
812
ccc92c23
ML		 813 {
814 .vendor = PCI_VENDOR_ID_RICOH,
815 .device = 0x843,
816 .subvendor = PCI_ANY_ID,
817 .subdevice = PCI_ANY_ID,
818 .driver_data = (kernel_ulong_t)&sdhci_ricoh_mmc,
819 },
820
568133eb
PC		 821 {
822 .vendor = PCI_VENDOR_ID_RICOH,
823 .device = 0xe822,
824 .subvendor = PCI_ANY_ID,
825 .subdevice = PCI_ANY_ID,
826 .driver_data = (kernel_ulong_t)&sdhci_ricoh_mmc,
827 },
828
5fd11c07
MI		 829 {
830 .vendor = PCI_VENDOR_ID_RICOH,
831 .device = 0xe823,
832 .subvendor = PCI_ANY_ID,
833 .subdevice = PCI_ANY_ID,
834 .driver_data = (kernel_ulong_t)&sdhci_ricoh_mmc,
835 },
836
b8c86fc5
PO		 837 {
838 .vendor = PCI_VENDOR_ID_ENE,
839 .device = PCI_DEVICE_ID_ENE_CB712_SD,
840 .subvendor = PCI_ANY_ID,
841 .subdevice = PCI_ANY_ID,
22606405 842 .driver_data = (kernel_ulong_t)&sdhci_ene_712,
b8c86fc5
PO		 843 },
844
845 {
846 .vendor = PCI_VENDOR_ID_ENE,
847 .device = PCI_DEVICE_ID_ENE_CB712_SD_2,
848 .subvendor = PCI_ANY_ID,
849 .subdevice = PCI_ANY_ID,
22606405 850 .driver_data = (kernel_ulong_t)&sdhci_ene_712,
b8c86fc5
PO		 851 },
852
853 {
854 .vendor = PCI_VENDOR_ID_ENE,
855 .device = PCI_DEVICE_ID_ENE_CB714_SD,
856 .subvendor = PCI_ANY_ID,
857 .subdevice = PCI_ANY_ID,
22606405 858 .driver_data = (kernel_ulong_t)&sdhci_ene_714,
b8c86fc5
PO		 859 },
860
861 {
862 .vendor = PCI_VENDOR_ID_ENE,
863 .device = PCI_DEVICE_ID_ENE_CB714_SD_2,
864 .subvendor = PCI_ANY_ID,
865 .subdevice = PCI_ANY_ID,
22606405 866 .driver_data = (kernel_ulong_t)&sdhci_ene_714,
b8c86fc5
PO		 867 },
868
869 {
870 .vendor = PCI_VENDOR_ID_MARVELL,
8c5eb880 871 .device = PCI_DEVICE_ID_MARVELL_88ALP01_SD,
b8c86fc5
PO		 872 .subvendor = PCI_ANY_ID,
873 .subdevice = PCI_ANY_ID,
22606405 874 .driver_data = (kernel_ulong_t)&sdhci_cafe,
b8c86fc5
PO		 875 },
876
877 {
878 .vendor = PCI_VENDOR_ID_JMICRON,
879 .device = PCI_DEVICE_ID_JMICRON_JMB38X_SD,
880 .subvendor = PCI_ANY_ID,
881 .subdevice = PCI_ANY_ID,
22606405 882 .driver_data = (kernel_ulong_t)&sdhci_jmicron,
b8c86fc5
PO		 883 },
884
4489428a
PO		 885 {
886 .vendor = PCI_VENDOR_ID_JMICRON,
887 .device = PCI_DEVICE_ID_JMICRON_JMB38X_MMC,
888 .subvendor = PCI_ANY_ID,
889 .subdevice = PCI_ANY_ID,
890 .driver_data = (kernel_ulong_t)&sdhci_jmicron,
8f230f45
TI		 891 },
892
893 {
894 .vendor = PCI_VENDOR_ID_JMICRON,
895 .device = PCI_DEVICE_ID_JMICRON_JMB388_SD,
896 .subvendor = PCI_ANY_ID,
897 .subdevice = PCI_ANY_ID,
898 .driver_data = (kernel_ulong_t)&sdhci_jmicron,
899 },
900
901 {
902 .vendor = PCI_VENDOR_ID_JMICRON,
903 .device = PCI_DEVICE_ID_JMICRON_JMB388_ESD,
904 .subvendor = PCI_ANY_ID,
905 .subdevice = PCI_ANY_ID,
906 .driver_data = (kernel_ulong_t)&sdhci_jmicron,
4489428a
PO		 907 },
908
a7a6186c
NP		 909 {
910 .vendor = PCI_VENDOR_ID_SYSKONNECT,
911 .device = 0x8000,
912 .subvendor = PCI_ANY_ID,
913 .subdevice = PCI_ANY_ID,
914 .driver_data = (kernel_ulong_t)&sdhci_syskt,
915 },
916
557b0697
HW		 917 {
918 .vendor = PCI_VENDOR_ID_VIA,
919 .device = 0x95d0,
920 .subvendor = PCI_ANY_ID,
921 .subdevice = PCI_ANY_ID,
922 .driver_data = (kernel_ulong_t)&sdhci_via,
9107ebbf
MC		 923 },
924
925 {
926 .vendor = PCI_VENDOR_ID_REALTEK,
927 .device = 0x5250,
928 .subvendor = PCI_ANY_ID,
929 .subdevice = PCI_ANY_ID,
930 .driver_data = (kernel_ulong_t)&sdhci_rtsx,
557b0697
HW		 931 },
932
43e968ce
DB		 933 {
934 .vendor = PCI_VENDOR_ID_INTEL,
935 .device = PCI_DEVICE_ID_INTEL_QRK_SD,
936 .subvendor = PCI_ANY_ID,
937 .subdevice = PCI_ANY_ID,
938 .driver_data = (kernel_ulong_t)&sdhci_intel_qrk,
939 },
940
29229052
XS		 941 {
942 .vendor = PCI_VENDOR_ID_INTEL,
f9ee3eab
AC		 943 .device = PCI_DEVICE_ID_INTEL_MRST_SD0,
944 .subvendor = PCI_ANY_ID,
945 .subdevice = PCI_ANY_ID,
946 .driver_data = (kernel_ulong_t)&sdhci_intel_mrst_hc0,
947 },
948
949 {
950 .vendor = PCI_VENDOR_ID_INTEL,
951 .device = PCI_DEVICE_ID_INTEL_MRST_SD1,
952 .subvendor = PCI_ANY_ID,
953 .subdevice = PCI_ANY_ID,
35ac6f08
JP		 954 .driver_data = (kernel_ulong_t)&sdhci_intel_mrst_hc1_hc2,
955 },
956
957 {
958 .vendor = PCI_VENDOR_ID_INTEL,
959 .device = PCI_DEVICE_ID_INTEL_MRST_SD2,
960 .subvendor = PCI_ANY_ID,
961 .subdevice = PCI_ANY_ID,
962 .driver_data = (kernel_ulong_t)&sdhci_intel_mrst_hc1_hc2,
f9ee3eab
AC		 963 },
964
965 {
966 .vendor = PCI_VENDOR_ID_INTEL,
29229052
XS		 967 .device = PCI_DEVICE_ID_INTEL_MFD_SD,
968 .subvendor = PCI_ANY_ID,
969 .subdevice = PCI_ANY_ID,
970 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sd,
971 },
972
973 {
974 .vendor = PCI_VENDOR_ID_INTEL,
975 .device = PCI_DEVICE_ID_INTEL_MFD_SDIO1,
976 .subvendor = PCI_ANY_ID,
977 .subdevice = PCI_ANY_ID,
0d013bcf 978 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sdio,
29229052
XS		 979 },
980
981 {
982 .vendor = PCI_VENDOR_ID_INTEL,
983 .device = PCI_DEVICE_ID_INTEL_MFD_SDIO2,
984 .subvendor = PCI_ANY_ID,
985 .subdevice = PCI_ANY_ID,
0d013bcf 986 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sdio,
29229052
XS		 987 },
988
989 {
990 .vendor = PCI_VENDOR_ID_INTEL,
991 .device = PCI_DEVICE_ID_INTEL_MFD_EMMC0,
992 .subvendor = PCI_ANY_ID,
993 .subdevice = PCI_ANY_ID,
0d013bcf 994 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc,
29229052
XS		 995 },
996
997 {
998 .vendor = PCI_VENDOR_ID_INTEL,
999 .device = PCI_DEVICE_ID_INTEL_MFD_EMMC1,
1000 .subvendor = PCI_ANY_ID,
1001 .subdevice = PCI_ANY_ID,
0d013bcf 1002 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc,
29229052
XS		 1003 },
1004
296e0b03
AS		 1005 {
1006 .vendor = PCI_VENDOR_ID_INTEL,
1007 .device = PCI_DEVICE_ID_INTEL_PCH_SDIO0,
1008 .subvendor = PCI_ANY_ID,
1009 .subdevice = PCI_ANY_ID,
1010 .driver_data = (kernel_ulong_t)&sdhci_intel_pch_sdio,
1011 },
1012
1013 {
1014 .vendor = PCI_VENDOR_ID_INTEL,
1015 .device = PCI_DEVICE_ID_INTEL_PCH_SDIO1,
1016 .subvendor = PCI_ANY_ID,
1017 .subdevice = PCI_ANY_ID,
1018 .driver_data = (kernel_ulong_t)&sdhci_intel_pch_sdio,
1019 },
1020
728ef3d1
AH		 1021 {
1022 .vendor = PCI_VENDOR_ID_INTEL,
1023 .device = PCI_DEVICE_ID_INTEL_BYT_EMMC,
1024 .subvendor = PCI_ANY_ID,
1025 .subdevice = PCI_ANY_ID,
1026 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc,
1027 },
1028
1029 {
1030 .vendor = PCI_VENDOR_ID_INTEL,
1031 .device = PCI_DEVICE_ID_INTEL_BYT_SDIO,
1032 .subvendor = PCI_ANY_ID,
1033 .subdevice = PCI_ANY_ID,
1034 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio,
1035 },
1036
1037 {
1038 .vendor = PCI_VENDOR_ID_INTEL,
1039 .device = PCI_DEVICE_ID_INTEL_BYT_SD,
1040 .subvendor = PCI_ANY_ID,
1041 .subdevice = PCI_ANY_ID,
1042 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd,
1043 },
1044
30d025c0
AH		 1045 {
1046 .vendor = PCI_VENDOR_ID_INTEL,
1047 .device = PCI_DEVICE_ID_INTEL_BYT_EMMC2,
1048 .subvendor = PCI_ANY_ID,
1049 .subdevice = PCI_ANY_ID,
1050 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc,
1051 },
1052
066173b6
AC		 1053 {
1054 .vendor = PCI_VENDOR_ID_INTEL,
1055 .device = PCI_DEVICE_ID_INTEL_BSW_EMMC,
1056 .subvendor = PCI_ANY_ID,
1057 .subdevice = PCI_ANY_ID,
1058 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc,
1059 },
1060
1061 {
1062 .vendor = PCI_VENDOR_ID_INTEL,
1063 .device = PCI_DEVICE_ID_INTEL_BSW_SDIO,
1064 .subvendor = PCI_ANY_ID,
1065 .subdevice = PCI_ANY_ID,
1066 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio,
1067 },
1068
1069 {
1070 .vendor = PCI_VENDOR_ID_INTEL,
1071 .device = PCI_DEVICE_ID_INTEL_BSW_SD,
1072 .subvendor = PCI_ANY_ID,
1073 .subdevice = PCI_ANY_ID,
1074 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd,
1075 },
d052068a
EE		 1076
1077 {
1078 .vendor = PCI_VENDOR_ID_INTEL,
1079 .device = PCI_DEVICE_ID_INTEL_CLV_SDIO0,
1080 .subvendor = PCI_ANY_ID,
1081 .subdevice = PCI_ANY_ID,
1082 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sd,
1083 },
1084
1085 {
1086 .vendor = PCI_VENDOR_ID_INTEL,
1087 .device = PCI_DEVICE_ID_INTEL_CLV_SDIO1,
1088 .subvendor = PCI_ANY_ID,
1089 .subdevice = PCI_ANY_ID,
1090 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sdio,
1091 },
1092
1093 {
1094 .vendor = PCI_VENDOR_ID_INTEL,
1095 .device = PCI_DEVICE_ID_INTEL_CLV_SDIO2,
1096 .subvendor = PCI_ANY_ID,
1097 .subdevice = PCI_ANY_ID,
1098 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sdio,
1099 },
1100
1101 {
1102 .vendor = PCI_VENDOR_ID_INTEL,
1103 .device = PCI_DEVICE_ID_INTEL_CLV_EMMC0,
1104 .subvendor = PCI_ANY_ID,
1105 .subdevice = PCI_ANY_ID,
1106 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc,
1107 },
1108
1109 {
1110 .vendor = PCI_VENDOR_ID_INTEL,
1111 .device = PCI_DEVICE_ID_INTEL_CLV_EMMC1,
1112 .subvendor = PCI_ANY_ID,
1113 .subdevice = PCI_ANY_ID,
1114 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc,
1115 },
1116
8776a165
DC		 1117 {
1118 .vendor = PCI_VENDOR_ID_INTEL,
1f64cec2 1119 .device = PCI_DEVICE_ID_INTEL_MRFLD_MMC,
8776a165
DC		 1120 .subvendor = PCI_ANY_ID,
1121 .subdevice = PCI_ANY_ID,
1f64cec2 1122 .driver_data = (kernel_ulong_t)&sdhci_intel_mrfld_mmc,
8776a165 1123 },
1f7f2652
AH		 1124
1125 {
1126 .vendor = PCI_VENDOR_ID_INTEL,
1127 .device = PCI_DEVICE_ID_INTEL_SPT_EMMC,
1128 .subvendor = PCI_ANY_ID,
1129 .subdevice = PCI_ANY_ID,
1130 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc,
1131 },
1132
1133 {
1134 .vendor = PCI_VENDOR_ID_INTEL,
1135 .device = PCI_DEVICE_ID_INTEL_SPT_SDIO,
1136 .subvendor = PCI_ANY_ID,
1137 .subdevice = PCI_ANY_ID,
1138 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio,
1139 },
1140
1141 {
1142 .vendor = PCI_VENDOR_ID_INTEL,
1143 .device = PCI_DEVICE_ID_INTEL_SPT_SD,
1144 .subvendor = PCI_ANY_ID,
1145 .subdevice = PCI_ANY_ID,
1146 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd,
1147 },
1148
06bf9c56
AH		 1149 {
1150 .vendor = PCI_VENDOR_ID_INTEL,
1151 .device = PCI_DEVICE_ID_INTEL_DNV_EMMC,
1152 .subvendor = PCI_ANY_ID,
1153 .subdevice = PCI_ANY_ID,
1154 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc,
1155 },
1156
4fd4c065
AH		 1157 {
1158 .vendor = PCI_VENDOR_ID_INTEL,
1159 .device = PCI_DEVICE_ID_INTEL_BXT_EMMC,
1160 .subvendor = PCI_ANY_ID,
1161 .subdevice = PCI_ANY_ID,
1162 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc,
1163 },
1164
1165 {
1166 .vendor = PCI_VENDOR_ID_INTEL,
1167 .device = PCI_DEVICE_ID_INTEL_BXT_SDIO,
1168 .subvendor = PCI_ANY_ID,
1169 .subdevice = PCI_ANY_ID,
1170 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio,
1171 },
1172
1173 {
1174 .vendor = PCI_VENDOR_ID_INTEL,
1175 .device = PCI_DEVICE_ID_INTEL_BXT_SD,
1176 .subvendor = PCI_ANY_ID,
1177 .subdevice = PCI_ANY_ID,
1178 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd,
1179 },
1180
01d6b2a4
AH		 1181 {
1182 .vendor = PCI_VENDOR_ID_INTEL,
1183 .device = PCI_DEVICE_ID_INTEL_BXTM_EMMC,
1184 .subvendor = PCI_ANY_ID,
1185 .subdevice = PCI_ANY_ID,
1186 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc,
1187 },
1188
1189 {
1190 .vendor = PCI_VENDOR_ID_INTEL,
1191 .device = PCI_DEVICE_ID_INTEL_BXTM_SDIO,
1192 .subvendor = PCI_ANY_ID,
1193 .subdevice = PCI_ANY_ID,
1194 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio,
1195 },
1196
1197 {
1198 .vendor = PCI_VENDOR_ID_INTEL,
1199 .device = PCI_DEVICE_ID_INTEL_BXTM_SD,
1200 .subvendor = PCI_ANY_ID,
1201 .subdevice = PCI_ANY_ID,
1202 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd,
1203 },
1204
4fd4c065
AH		 1205 {
1206 .vendor = PCI_VENDOR_ID_INTEL,
1207 .device = PCI_DEVICE_ID_INTEL_APL_EMMC,
1208 .subvendor = PCI_ANY_ID,
1209 .subdevice = PCI_ANY_ID,
1210 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc,
1211 },
1212
1213 {
1214 .vendor = PCI_VENDOR_ID_INTEL,
1215 .device = PCI_DEVICE_ID_INTEL_APL_SDIO,
1216 .subvendor = PCI_ANY_ID,
1217 .subdevice = PCI_ANY_ID,
1218 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio,
1219 },
1220
1221 {
1222 .vendor = PCI_VENDOR_ID_INTEL,
1223 .device = PCI_DEVICE_ID_INTEL_APL_SD,
1224 .subvendor = PCI_ANY_ID,
1225 .subdevice = PCI_ANY_ID,
1226 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd,
1227 },
1228
26daa1ed
JL		 1229 {
1230 .vendor = PCI_VENDOR_ID_O2,
1231 .device = PCI_DEVICE_ID_O2_8120,
1232 .subvendor = PCI_ANY_ID,
1233 .subdevice = PCI_ANY_ID,
1234 .driver_data = (kernel_ulong_t)&sdhci_o2,
1235 },
1236
1237 {
1238 .vendor = PCI_VENDOR_ID_O2,
1239 .device = PCI_DEVICE_ID_O2_8220,
1240 .subvendor = PCI_ANY_ID,
1241 .subdevice = PCI_ANY_ID,
1242 .driver_data = (kernel_ulong_t)&sdhci_o2,
1243 },
1244
1245 {
1246 .vendor = PCI_VENDOR_ID_O2,
1247 .device = PCI_DEVICE_ID_O2_8221,
1248 .subvendor = PCI_ANY_ID,
1249 .subdevice = PCI_ANY_ID,
1250 .driver_data = (kernel_ulong_t)&sdhci_o2,
1251 },
1252
1253 {
1254 .vendor = PCI_VENDOR_ID_O2,
1255 .device = PCI_DEVICE_ID_O2_8320,
1256 .subvendor = PCI_ANY_ID,
1257 .subdevice = PCI_ANY_ID,
1258 .driver_data = (kernel_ulong_t)&sdhci_o2,
1259 },
1260
1261 {
1262 .vendor = PCI_VENDOR_ID_O2,
1263 .device = PCI_DEVICE_ID_O2_8321,
1264 .subvendor = PCI_ANY_ID,
1265 .subdevice = PCI_ANY_ID,
1266 .driver_data = (kernel_ulong_t)&sdhci_o2,
1267 },
1268
01acf691
AL		 1269 {
1270 .vendor = PCI_VENDOR_ID_O2,
1271 .device = PCI_DEVICE_ID_O2_FUJIN2,
1272 .subvendor = PCI_ANY_ID,
1273 .subdevice = PCI_ANY_ID,
1274 .driver_data = (kernel_ulong_t)&sdhci_o2,
1275 },
1276
1277 {
1278 .vendor = PCI_VENDOR_ID_O2,
1279 .device = PCI_DEVICE_ID_O2_SDS0,
1280 .subvendor = PCI_ANY_ID,
1281 .subdevice = PCI_ANY_ID,
1282 .driver_data = (kernel_ulong_t)&sdhci_o2,
1283 },
1284
1285 {
1286 .vendor = PCI_VENDOR_ID_O2,
1287 .device = PCI_DEVICE_ID_O2_SDS1,
1288 .subvendor = PCI_ANY_ID,
1289 .subdevice = PCI_ANY_ID,
1290 .driver_data = (kernel_ulong_t)&sdhci_o2,
1291 },
1292
1293 {
1294 .vendor = PCI_VENDOR_ID_O2,
1295 .device = PCI_DEVICE_ID_O2_SEABIRD0,
1296 .subvendor = PCI_ANY_ID,
1297 .subdevice = PCI_ANY_ID,
1298 .driver_data = (kernel_ulong_t)&sdhci_o2,
1299 },
1300
1301 {
1302 .vendor = PCI_VENDOR_ID_O2,
1303 .device = PCI_DEVICE_ID_O2_SEABIRD1,
1304 .subvendor = PCI_ANY_ID,
1305 .subdevice = PCI_ANY_ID,
1306 .driver_data = (kernel_ulong_t)&sdhci_o2,
1307 },
d44f88da
VW		 1308 {
1309 .vendor = PCI_VENDOR_ID_AMD,
1310 .device = PCI_ANY_ID,
1311 .class = PCI_CLASS_SYSTEM_SDHCI << 8,
1312 .class_mask = 0xFFFF00,
1313 .subvendor = PCI_ANY_ID,
1314 .subdevice = PCI_ANY_ID,
1315 .driver_data = (kernel_ulong_t)&sdhci_amd,
1316 },
b8c86fc5
PO		 1317 { /* Generic SD host controller */
1318 PCI_DEVICE_CLASS((PCI_CLASS_SYSTEM_SDHCI << 8), 0xFFFF00)
1319 },
1320
1321 { /* end: all zeroes */ },
1322};
1323
1324MODULE_DEVICE_TABLE(pci, pci_ids);
1325
b8c86fc5
PO		 1326/*****************************************************************************\
1327 * *
1328 * SDHCI core callbacks *
1329 * *
1330\*****************************************************************************/
1331
1332static int sdhci_pci_enable_dma(struct sdhci_host *host)
1333{
1334 struct sdhci_pci_slot *slot;
1335 struct pci_dev *pdev;
b8c86fc5
PO		 1336
1337 slot = sdhci_priv(host);
1338 pdev = slot->chip->pdev;
1339
1340 if (((pdev->class & 0xFFFF00) == (PCI_CLASS_SYSTEM_SDHCI << 8)) &&
1341 ((pdev->class & 0x0000FF) != PCI_SDHCI_IFDMA) &&
a13abc7b 1342 (host->flags & SDHCI_USE_SDMA)) {
b8c86fc5
PO		 1343 dev_warn(&pdev->dev, "Will use DMA mode even though HW "
1344 "doesn't fully claim to support it.\n");
1345 }
1346
b8c86fc5
PO		 1347 pci_set_master(pdev);
1348
1349 return 0;
1350}
1351
2317f56c 1352static void sdhci_pci_set_bus_width(struct sdhci_host *host, int width)
68077b02
ML		 1353{
1354 u8 ctrl;
1355
1356 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1357
1358 switch (width) {
1359 case MMC_BUS_WIDTH_8:
1360 ctrl |= SDHCI_CTRL_8BITBUS;
1361 ctrl &= ~SDHCI_CTRL_4BITBUS;
1362 break;
1363 case MMC_BUS_WIDTH_4:
1364 ctrl |= SDHCI_CTRL_4BITBUS;
1365 ctrl &= ~SDHCI_CTRL_8BITBUS;
1366 break;
1367 default:
1368 ctrl &= ~(SDHCI_CTRL_8BITBUS | SDHCI_CTRL_4BITBUS);
1369 break;
1370 }
1371
1372 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
68077b02
ML		 1373}
1374
c9faff6c 1375static void sdhci_pci_gpio_hw_reset(struct sdhci_host *host)
0f201655
AH		 1376{
1377 struct sdhci_pci_slot *slot = sdhci_priv(host);
1378 int rst_n_gpio = slot->rst_n_gpio;
1379
1380 if (!gpio_is_valid(rst_n_gpio))
1381 return;
1382 gpio_set_value_cansleep(rst_n_gpio, 0);
1383 /* For eMMC, minimum is 1us but give it 10us for good measure */
1384 udelay(10);
1385 gpio_set_value_cansleep(rst_n_gpio, 1);
1386 /* For eMMC, minimum is 200us but give it 300us for good measure */
1387 usleep_range(300, 1000);
1388}
1389
c9faff6c
AH		 1390static void sdhci_pci_hw_reset(struct sdhci_host *host)
1391{
1392 struct sdhci_pci_slot *slot = sdhci_priv(host);
1393
1394 if (slot->hw_reset)
1395 slot->hw_reset(host);
1396}
1397
e1bfad6d
AH		 1398static int sdhci_pci_select_drive_strength(struct sdhci_host *host,
1399 struct mmc_card *card,
1400 unsigned int max_dtr, int host_drv,
1401 int card_drv, int *drv_type)
1402{
1403 struct sdhci_pci_slot *slot = sdhci_priv(host);
1404
1405 if (!slot->select_drive_strength)
1406 return 0;
1407
1408 return slot->select_drive_strength(host, card, max_dtr, host_drv,
1409 card_drv, drv_type);
1410}
1411
c915568d 1412static const struct sdhci_ops sdhci_pci_ops = {
1771059c 1413 .set_clock = sdhci_set_clock,
b8c86fc5 1414 .enable_dma = sdhci_pci_enable_dma,
2317f56c 1415 .set_bus_width = sdhci_pci_set_bus_width,
03231f9b 1416 .reset = sdhci_reset,
96d7b78c 1417 .set_uhs_signaling = sdhci_set_uhs_signaling,
0f201655 1418 .hw_reset = sdhci_pci_hw_reset,
e1bfad6d 1419 .select_drive_strength = sdhci_pci_select_drive_strength,
b8c86fc5
PO		 1420};
1421
1422/*****************************************************************************\
1423 * *
1424 * Suspend/resume *
1425 * *
1426\*****************************************************************************/
1427
f9900f15 1428#ifdef CONFIG_PM_SLEEP
29495aa0 1429static int sdhci_pci_suspend(struct device *dev)
b8c86fc5 1430{
29495aa0 1431 struct pci_dev *pdev = to_pci_dev(dev);
b8c86fc5
PO		 1432 struct sdhci_pci_chip *chip;
1433 struct sdhci_pci_slot *slot;
5f619704 1434 mmc_pm_flag_t slot_pm_flags;
2f4cbb3d 1435 mmc_pm_flag_t pm_flags = 0;
b8c86fc5
PO		 1436 int i, ret;
1437
1438 chip = pci_get_drvdata(pdev);
1439 if (!chip)
1440 return 0;
1441
b177bc91 1442 for (i = 0; i < chip->num_slots; i++) {
b8c86fc5
PO		 1443 slot = chip->slots[i];
1444 if (!slot)
1445 continue;
1446
29495aa0 1447 ret = sdhci_suspend_host(slot->host);
b8c86fc5 1448
b678b91f
AL		 1449 if (ret)
1450 goto err_pci_suspend;
2f4cbb3d 1451
5f619704
DD		 1452 slot_pm_flags = slot->host->mmc->pm_flags;
1453 if (slot_pm_flags & MMC_PM_WAKE_SDIO_IRQ)
1454 sdhci_enable_irq_wakeups(slot->host);
1455
1456 pm_flags |= slot_pm_flags;
b8c86fc5
PO		 1457 }
1458
4489428a 1459 if (chip->fixes && chip->fixes->suspend) {
29495aa0 1460 ret = chip->fixes->suspend(chip);
b678b91f
AL		 1461 if (ret)
1462 goto err_pci_suspend;
4489428a
PO		 1463 }
1464
2f4cbb3d 1465 if (pm_flags & MMC_PM_KEEP_POWER) {
6b91f2d4
CD		 1466 if (pm_flags & MMC_PM_WAKE_SDIO_IRQ)
1467 device_init_wakeup(dev, true);
1468 else
1469 device_init_wakeup(dev, false);
1470 } else
1471 device_init_wakeup(dev, false);
b8c86fc5
PO		 1472
1473 return 0;
b678b91f
AL		 1474
1475err_pci_suspend:
1476 while (--i >= 0)
1477 sdhci_resume_host(chip->slots[i]->host);
1478 return ret;
b8c86fc5
PO		 1479}
1480
29495aa0 1481static int sdhci_pci_resume(struct device *dev)
b8c86fc5 1482{
29495aa0 1483 struct pci_dev *pdev = to_pci_dev(dev);
b8c86fc5
PO		 1484 struct sdhci_pci_chip *chip;
1485 struct sdhci_pci_slot *slot;
1486 int i, ret;
1487
1488 chip = pci_get_drvdata(pdev);
1489 if (!chip)
1490 return 0;
1491
45211e21
PO		 1492 if (chip->fixes && chip->fixes->resume) {
1493 ret = chip->fixes->resume(chip);
1494 if (ret)
1495 return ret;
1496 }
1497
b177bc91 1498 for (i = 0; i < chip->num_slots; i++) {
b8c86fc5
PO		 1499 slot = chip->slots[i];
1500 if (!slot)
1501 continue;
1502
1503 ret = sdhci_resume_host(slot->host);
1504 if (ret)
1505 return ret;
1506 }
1507
1508 return 0;
1509}
f9900f15 1510#endif
b8c86fc5 1511
f9900f15 1512#ifdef CONFIG_PM
66fd8ad5
AH		 1513static int sdhci_pci_runtime_suspend(struct device *dev)
1514{
923a231c 1515 struct pci_dev *pdev = to_pci_dev(dev);
66fd8ad5
AH		 1516 struct sdhci_pci_chip *chip;
1517 struct sdhci_pci_slot *slot;
66fd8ad5
AH		 1518 int i, ret;
1519
1520 chip = pci_get_drvdata(pdev);
1521 if (!chip)
1522 return 0;
1523
1524 for (i = 0; i < chip->num_slots; i++) {
1525 slot = chip->slots[i];
1526 if (!slot)
1527 continue;
1528
1529 ret = sdhci_runtime_suspend_host(slot->host);
1530
b678b91f
AL		 1531 if (ret)
1532 goto err_pci_runtime_suspend;
66fd8ad5
AH		 1533 }
1534
1535 if (chip->fixes && chip->fixes->suspend) {
29495aa0 1536 ret = chip->fixes->suspend(chip);
b678b91f
AL		 1537 if (ret)
1538 goto err_pci_runtime_suspend;
66fd8ad5
AH		 1539 }
1540
1541 return 0;
b678b91f
AL		 1542
1543err_pci_runtime_suspend:
1544 while (--i >= 0)
1545 sdhci_runtime_resume_host(chip->slots[i]->host);
1546 return ret;
66fd8ad5
AH		 1547}
1548
1549static int sdhci_pci_runtime_resume(struct device *dev)
1550{
923a231c 1551 struct pci_dev *pdev = to_pci_dev(dev);
66fd8ad5
AH		 1552 struct sdhci_pci_chip *chip;
1553 struct sdhci_pci_slot *slot;
1554 int i, ret;
1555
1556 chip = pci_get_drvdata(pdev);
1557 if (!chip)
1558 return 0;
1559
1560 if (chip->fixes && chip->fixes->resume) {
1561 ret = chip->fixes->resume(chip);
1562 if (ret)
1563 return ret;
1564 }
1565
1566 for (i = 0; i < chip->num_slots; i++) {
1567 slot = chip->slots[i];
1568 if (!slot)
1569 continue;
1570
1571 ret = sdhci_runtime_resume_host(slot->host);
1572 if (ret)
1573 return ret;
1574 }
1575
1576 return 0;
1577}
f9900f15 1578#endif
66fd8ad5
AH		 1579
1580static const struct dev_pm_ops sdhci_pci_pm_ops = {
f9900f15 1581 SET_SYSTEM_SLEEP_PM_OPS(sdhci_pci_suspend, sdhci_pci_resume)
f3a92b1a 1582 SET_RUNTIME_PM_OPS(sdhci_pci_runtime_suspend,
106276bb 1583 sdhci_pci_runtime_resume, NULL)
66fd8ad5
AH		 1584};
1585
b8c86fc5
PO		 1586/*****************************************************************************\
1587 * *
1588 * Device probing/removal *
1589 * *
1590\*****************************************************************************/
1591
c3be1efd 1592static struct sdhci_pci_slot *sdhci_pci_probe_slot(
52c506f0
AH		 1593 struct pci_dev *pdev, struct sdhci_pci_chip *chip, int first_bar,
1594 int slotno)
b8c86fc5
PO		 1595{
1596 struct sdhci_pci_slot *slot;
1597 struct sdhci_host *host;
52c506f0 1598 int ret, bar = first_bar + slotno;
b8c86fc5
PO		 1599
1600 if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) {
1601 dev_err(&pdev->dev, "BAR %d is not iomem. Aborting.\n", bar);
1602 return ERR_PTR(-ENODEV);
1603 }
1604
90b3e6c5 1605 if (pci_resource_len(pdev, bar) < 0x100) {
b8c86fc5
PO		 1606 dev_err(&pdev->dev, "Invalid iomem size. You may "
1607 "experience problems.\n");
1608 }
1609
1610 if ((pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) {
1611 dev_err(&pdev->dev, "Vendor specific interface. Aborting.\n");
1612 return ERR_PTR(-ENODEV);
1613 }
1614
1615 if ((pdev->class & 0x0000FF) > PCI_SDHCI_IFVENDOR) {
1616 dev_err(&pdev->dev, "Unknown interface. Aborting.\n");
1617 return ERR_PTR(-ENODEV);
1618 }
1619
1620 host = sdhci_alloc_host(&pdev->dev, sizeof(struct sdhci_pci_slot));
1621 if (IS_ERR(host)) {
c60a32cd 1622 dev_err(&pdev->dev, "cannot allocate host\n");
dc0fd7b5 1623 return ERR_CAST(host);
b8c86fc5
PO		 1624 }
1625
1626 slot = sdhci_priv(host);
1627
1628 slot->chip = chip;
1629 slot->host = host;
0f201655 1630 slot->rst_n_gpio = -EINVAL;
c5e027a4 1631 slot->cd_gpio = -EINVAL;
ff59c520 1632 slot->cd_idx = -1;
b8c86fc5 1633
52c506f0
AH		 1634 /* Retrieve platform data if there is any */
1635 if (*sdhci_pci_get_data)
1636 slot->data = sdhci_pci_get_data(pdev, slotno);
1637
1638 if (slot->data) {
1639 if (slot->data->setup) {
1640 ret = slot->data->setup(slot->data);
1641 if (ret) {
1642 dev_err(&pdev->dev, "platform setup failed\n");
1643 goto free;
1644 }
1645 }
c5e027a4
AH		 1646 slot->rst_n_gpio = slot->data->rst_n_gpio;
1647 slot->cd_gpio = slot->data->cd_gpio;
52c506f0
AH		 1648 }
1649
b8c86fc5
PO		 1650 host->hw_name = "PCI";
1651 host->ops = &sdhci_pci_ops;
1652 host->quirks = chip->quirks;
f3c55a7b 1653 host->quirks2 = chip->quirks2;
b8c86fc5
PO		 1654
1655 host->irq = pdev->irq;
1656
c10bc372 1657 ret = pcim_iomap_regions(pdev, BIT(bar), mmc_hostname(host->mmc));
b8c86fc5
PO		 1658 if (ret) {
1659 dev_err(&pdev->dev, "cannot request region\n");
52c506f0 1660 goto cleanup;
b8c86fc5
PO		 1661 }
1662
c10bc372 1663 host->ioaddr = pcim_iomap_table(pdev)[bar];
b8c86fc5 1664
4489428a
PO		 1665 if (chip->fixes && chip->fixes->probe_slot) {
1666 ret = chip->fixes->probe_slot(slot);
1667 if (ret)
c10bc372 1668 goto cleanup;
4489428a
PO		 1669 }
1670
c5e027a4 1671 if (gpio_is_valid(slot->rst_n_gpio)) {
c10bc372 1672 if (!devm_gpio_request(&pdev->dev, slot->rst_n_gpio, "eMMC_reset")) {
c5e027a4
AH		 1673 gpio_direction_output(slot->rst_n_gpio, 1);
1674 slot->host->mmc->caps |= MMC_CAP_HW_RESET;
c9faff6c 1675 slot->hw_reset = sdhci_pci_gpio_hw_reset;
c5e027a4
AH		 1676 } else {
1677 dev_warn(&pdev->dev, "failed to request rst_n_gpio\n");
1678 slot->rst_n_gpio = -EINVAL;
1679 }
1680 }
1681
2f4cbb3d 1682 host->mmc->pm_caps = MMC_PM_KEEP_POWER | MMC_PM_WAKE_SDIO_IRQ;
eed222ac 1683 host->mmc->slotno = slotno;
a08b17be 1684 host->mmc->caps2 |= MMC_CAP2_NO_PRESCAN_POWERUP;
2f4cbb3d 1685
ff59c520
AH		 1686 if (slot->cd_idx >= 0 &&
1687 mmc_gpiod_request_cd(host->mmc, slot->cd_con_id, slot->cd_idx,
1688 slot->cd_override_level, 0, NULL)) {
1689 dev_warn(&pdev->dev, "failed to setup card detect gpio\n");
1690 slot->cd_idx = -1;
1691 }
1692
b8c86fc5
PO		 1693 ret = sdhci_add_host(host);
1694 if (ret)
4489428a 1695 goto remove;
b8c86fc5 1696
c5e027a4
AH		 1697 sdhci_pci_add_own_cd(slot);
1698
77a0122e
AH		 1699 /*
1700 * Check if the chip needs a separate GPIO for card detect to wake up
1701 * from runtime suspend. If it is not there, don't allow runtime PM.
1702 * Note sdhci_pci_add_own_cd() sets slot->cd_gpio to -EINVAL on failure.
1703 */
945be38c 1704 if (chip->fixes && chip->fixes->own_cd_for_runtime_pm &&
ff59c520 1705 !gpio_is_valid(slot->cd_gpio) && slot->cd_idx < 0)
77a0122e
AH		 1706 chip->allow_runtime_pm = false;
1707
b8c86fc5
PO		 1708 return slot;
1709
4489428a
PO		 1710remove:
1711 if (chip->fixes && chip->fixes->remove_slot)
1e72859e 1712 chip->fixes->remove_slot(slot, 0);
4489428a 1713
52c506f0
AH		 1714cleanup:
1715 if (slot->data && slot->data->cleanup)
1716 slot->data->cleanup(slot->data);
1717
c60a32cd 1718free:
b8c86fc5
PO		 1719 sdhci_free_host(host);
1720
1721 return ERR_PTR(ret);
1722}
1723
1724static void sdhci_pci_remove_slot(struct sdhci_pci_slot *slot)
1725{
1e72859e
PO		 1726 int dead;
1727 u32 scratch;
1728
c5e027a4
AH		 1729 sdhci_pci_remove_own_cd(slot);
1730
1e72859e
PO		 1731 dead = 0;
1732 scratch = readl(slot->host->ioaddr + SDHCI_INT_STATUS);
1733 if (scratch == (u32)-1)
1734 dead = 1;
1735
1736 sdhci_remove_host(slot->host, dead);
4489428a
PO		 1737
1738 if (slot->chip->fixes && slot->chip->fixes->remove_slot)
1e72859e 1739 slot->chip->fixes->remove_slot(slot, dead);
4489428a 1740
52c506f0
AH		 1741 if (slot->data && slot->data->cleanup)
1742 slot->data->cleanup(slot->data);
1743
b8c86fc5
PO		 1744 sdhci_free_host(slot->host);
1745}
1746
c3be1efd 1747static void sdhci_pci_runtime_pm_allow(struct device *dev)
66fd8ad5 1748{
00884b61 1749 pm_suspend_ignore_children(dev, 1);
66fd8ad5
AH		 1750 pm_runtime_set_autosuspend_delay(dev, 50);
1751 pm_runtime_use_autosuspend(dev);
00884b61
AH		 1752 pm_runtime_allow(dev);
1753 /* Stay active until mmc core scans for a card */
1754 pm_runtime_put_noidle(dev);
66fd8ad5
AH		 1755}
1756
6e0ee714 1757static void sdhci_pci_runtime_pm_forbid(struct device *dev)
66fd8ad5
AH		 1758{
1759 pm_runtime_forbid(dev);
1760 pm_runtime_get_noresume(dev);
1761}
1762
c3be1efd 1763static int sdhci_pci_probe(struct pci_dev *pdev,
b8c86fc5
PO		 1764 const struct pci_device_id *ent)
1765{
1766 struct sdhci_pci_chip *chip;
1767 struct sdhci_pci_slot *slot;
1768
cf5e23e1 1769 u8 slots, first_bar;
b8c86fc5
PO		 1770 int ret, i;
1771
1772 BUG_ON(pdev == NULL);
1773 BUG_ON(ent == NULL);
1774
b8c86fc5 1775 dev_info(&pdev->dev, "SDHCI controller found [%04x:%04x] (rev %x)\n",
cf5e23e1 1776 (int)pdev->vendor, (int)pdev->device, (int)pdev->revision);
b8c86fc5
PO		 1777
1778 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &slots);
1779 if (ret)
1780 return ret;
1781
1782 slots = PCI_SLOT_INFO_SLOTS(slots) + 1;
1783 dev_dbg(&pdev->dev, "found %d slot(s)\n", slots);
1784 if (slots == 0)
1785 return -ENODEV;
1786
1787 BUG_ON(slots > MAX_SLOTS);
1788
1789 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &first_bar);
1790 if (ret)
1791 return ret;
1792
1793 first_bar &= PCI_SLOT_INFO_FIRST_BAR_MASK;
1794
1795 if (first_bar > 5) {
1796 dev_err(&pdev->dev, "Invalid first BAR. Aborting.\n");
1797 return -ENODEV;
1798 }
1799
52ac7acf 1800 ret = pcim_enable_device(pdev);
b8c86fc5
PO		 1801 if (ret)
1802 return ret;
1803
52ac7acf
AS		 1804 chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL);
1805 if (!chip)
1806 return -ENOMEM;
b8c86fc5
PO		 1807
1808 chip->pdev = pdev;
b177bc91 1809 chip->fixes = (const struct sdhci_pci_fixes *)ent->driver_data;
c43fd774 1810 if (chip->fixes) {
22606405 1811 chip->quirks = chip->fixes->quirks;
f3c55a7b 1812 chip->quirks2 = chip->fixes->quirks2;
c43fd774
AH		 1813 chip->allow_runtime_pm = chip->fixes->allow_runtime_pm;
1814 }
b8c86fc5
PO		 1815 chip->num_slots = slots;
1816
1817 pci_set_drvdata(pdev, chip);
1818
22606405
PO		 1819 if (chip->fixes && chip->fixes->probe) {
1820 ret = chip->fixes->probe(chip);
1821 if (ret)
52ac7acf 1822 return ret;
22606405
PO		 1823 }
1824
225d85fe
AC		 1825 slots = chip->num_slots; /* Quirk may have changed this */
1826
b177bc91 1827 for (i = 0; i < slots; i++) {
52c506f0 1828 slot = sdhci_pci_probe_slot(pdev, chip, first_bar, i);
b8c86fc5 1829 if (IS_ERR(slot)) {
b177bc91 1830 for (i--; i >= 0; i--)
b8c86fc5 1831 sdhci_pci_remove_slot(chip->slots[i]);
52ac7acf 1832 return PTR_ERR(slot);
b8c86fc5
PO		 1833 }
1834
1835 chip->slots[i] = slot;
1836 }
1837
c43fd774
AH		 1838 if (chip->allow_runtime_pm)
1839 sdhci_pci_runtime_pm_allow(&pdev->dev);
66fd8ad5 1840
b8c86fc5 1841 return 0;
b8c86fc5
PO		 1842}
1843
6e0ee714 1844static void sdhci_pci_remove(struct pci_dev *pdev)
b8c86fc5
PO		 1845{
1846 int i;
52ac7acf 1847 struct sdhci_pci_chip *chip = pci_get_drvdata(pdev);
c43fd774 1848
52ac7acf
AS		 1849 if (chip->allow_runtime_pm)
1850 sdhci_pci_runtime_pm_forbid(&pdev->dev);
b8c86fc5 1851
52ac7acf
AS		 1852 for (i = 0; i < chip->num_slots; i++)
1853 sdhci_pci_remove_slot(chip->slots[i]);
b8c86fc5
PO		 1854}
1855
1856static struct pci_driver sdhci_driver = {
b177bc91 1857 .name = "sdhci-pci",
b8c86fc5 1858 .id_table = pci_ids,
b177bc91 1859 .probe = sdhci_pci_probe,
0433c143 1860 .remove = sdhci_pci_remove,
66fd8ad5
AH		 1861 .driver = {
1862 .pm = &sdhci_pci_pm_ops
1863 },
b8c86fc5
PO		 1864};
1865
acc69646 1866module_pci_driver(sdhci_driver);
b8c86fc5 1867
32710e8f 1868MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
b8c86fc5
PO		 1869MODULE_DESCRIPTION("Secure Digital Host Controller Interface PCI driver");
1870MODULE_LICENSE("GPL");
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