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mmc: sdhci-esdhc-imx: Remove the ENGcm07207 workaround
[mirror_ubuntu-eoan-kernel.git] / drivers / mmc / host / sdhci-pci-core.c
CommitLineData
b8c86fc5
PO		 1/* linux/drivers/mmc/host/sdhci-pci.c - SDHCI on PCI bus interface
2 *
3 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or (at
8 * your option) any later version.
9 *
10 * Thanks to the following companies for their support:
11 *
12 * - JMicron (hardware and technical support)
13 */
14
a72016a4 15#include <linux/string.h>
b8c86fc5
PO		 16#include <linux/delay.h>
17#include <linux/highmem.h>
88b47679 18#include <linux/module.h>
b8c86fc5
PO		 19#include <linux/pci.h>
20#include <linux/dma-mapping.h>
5a0e3ad6 21#include <linux/slab.h>
ccc92c23 22#include <linux/device.h>
b8c86fc5 23#include <linux/mmc/host.h>
e1bfad6d 24#include <linux/mmc/mmc.h>
b177bc91
AP		 25#include <linux/scatterlist.h>
26#include <linux/io.h>
0f201655 27#include <linux/gpio.h>
66fd8ad5 28#include <linux/pm_runtime.h>
ff59c520 29#include <linux/mmc/slot-gpio.h>
52c506f0 30#include <linux/mmc/sdhci-pci-data.h>
3f23df72 31#include <linux/acpi.h>
b8c86fc5
PO		 32
33#include "sdhci.h"
522624f9 34#include "sdhci-pci.h"
01acf691 35#include "sdhci-pci-o2micro.h"
22606405 36
fee686b7
AH		 37static int sdhci_pci_enable_dma(struct sdhci_host *host);
38static void sdhci_pci_set_bus_width(struct sdhci_host *host, int width);
39static void sdhci_pci_hw_reset(struct sdhci_host *host);
fee686b7 40
30cf2803
AH		 41#ifdef CONFIG_PM_SLEEP
42static int __sdhci_pci_suspend_host(struct sdhci_pci_chip *chip)
43{
44 int i, ret;
45
46 for (i = 0; i < chip->num_slots; i++) {
47 struct sdhci_pci_slot *slot = chip->slots[i];
48 struct sdhci_host *host;
49
50 if (!slot)
51 continue;
52
53 host = slot->host;
54
55 if (chip->pm_retune && host->tuning_mode != SDHCI_TUNING_MODE_3)
56 mmc_retune_needed(host->mmc);
57
58 ret = sdhci_suspend_host(host);
59 if (ret)
60 goto err_pci_suspend;
61
62 if (host->mmc->pm_flags & MMC_PM_WAKE_SDIO_IRQ)
63 sdhci_enable_irq_wakeups(host);
64 }
65
66 return 0;
67
68err_pci_suspend:
69 while (--i >= 0)
70 sdhci_resume_host(chip->slots[i]->host);
71 return ret;
72}
73
74static int sdhci_pci_init_wakeup(struct sdhci_pci_chip *chip)
75{
76 mmc_pm_flag_t pm_flags = 0;
77 int i;
78
79 for (i = 0; i < chip->num_slots; i++) {
80 struct sdhci_pci_slot *slot = chip->slots[i];
81
82 if (slot)
83 pm_flags |= slot->host->mmc->pm_flags;
84 }
85
86 return device_init_wakeup(&chip->pdev->dev,
87 (pm_flags & MMC_PM_KEEP_POWER) &&
88 (pm_flags & MMC_PM_WAKE_SDIO_IRQ));
89}
90
91static int sdhci_pci_suspend_host(struct sdhci_pci_chip *chip)
92{
93 int ret;
94
95 ret = __sdhci_pci_suspend_host(chip);
96 if (ret)
97 return ret;
98
99 sdhci_pci_init_wakeup(chip);
100
101 return 0;
102}
103
104int sdhci_pci_resume_host(struct sdhci_pci_chip *chip)
105{
106 struct sdhci_pci_slot *slot;
107 int i, ret;
108
109 for (i = 0; i < chip->num_slots; i++) {
110 slot = chip->slots[i];
111 if (!slot)
112 continue;
113
114 ret = sdhci_resume_host(slot->host);
115 if (ret)
116 return ret;
117 }
118
119 return 0;
120}
121#endif
122
966d696a
AH		 123#ifdef CONFIG_PM
124static int sdhci_pci_runtime_suspend_host(struct sdhci_pci_chip *chip)
125{
126 struct sdhci_pci_slot *slot;
127 struct sdhci_host *host;
128 int i, ret;
129
130 for (i = 0; i < chip->num_slots; i++) {
131 slot = chip->slots[i];
132 if (!slot)
133 continue;
134
135 host = slot->host;
136
137 ret = sdhci_runtime_suspend_host(host);
138 if (ret)
139 goto err_pci_runtime_suspend;
140
141 if (chip->rpm_retune &&
142 host->tuning_mode != SDHCI_TUNING_MODE_3)
143 mmc_retune_needed(host->mmc);
144 }
145
146 return 0;
147
148err_pci_runtime_suspend:
149 while (--i >= 0)
150 sdhci_runtime_resume_host(chip->slots[i]->host);
151 return ret;
152}
153
154static int sdhci_pci_runtime_resume_host(struct sdhci_pci_chip *chip)
155{
156 struct sdhci_pci_slot *slot;
157 int i, ret;
158
159 for (i = 0; i < chip->num_slots; i++) {
160 slot = chip->slots[i];
161 if (!slot)
162 continue;
163
164 ret = sdhci_runtime_resume_host(slot->host);
165 if (ret)
166 return ret;
167 }
168
169 return 0;
170}
171#endif
172
22606405
PO		 173/*****************************************************************************\
174 * *
175 * Hardware specific quirk handling *
176 * *
177\*****************************************************************************/
178
179static int ricoh_probe(struct sdhci_pci_chip *chip)
180{
c99436fb
CB		 181 if (chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG ||
182 chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SONY)
22606405 183 chip->quirks |= SDHCI_QUIRK_NO_CARD_NO_RESET;
ccc92c23
ML		 184 return 0;
185}
186
187static int ricoh_mmc_probe_slot(struct sdhci_pci_slot *slot)
188{
189 slot->host->caps =
190 ((0x21 << SDHCI_TIMEOUT_CLK_SHIFT)
191 & SDHCI_TIMEOUT_CLK_MASK) |
22606405 192
ccc92c23
ML		 193 ((0x21 << SDHCI_CLOCK_BASE_SHIFT)
194 & SDHCI_CLOCK_BASE_MASK) |
195
196 SDHCI_TIMEOUT_CLK_UNIT |
197 SDHCI_CAN_VDD_330 |
1a1f1f04 198 SDHCI_CAN_DO_HISPD |
ccc92c23
ML		 199 SDHCI_CAN_DO_SDMA;
200 return 0;
201}
202
b7813f0f 203#ifdef CONFIG_PM_SLEEP
ccc92c23
ML		 204static int ricoh_mmc_resume(struct sdhci_pci_chip *chip)
205{
206 /* Apply a delay to allow controller to settle */
207 /* Otherwise it becomes confused if card state changed
208 during suspend */
209 msleep(500);
30cf2803 210 return sdhci_pci_resume_host(chip);
22606405 211}
b7813f0f 212#endif
22606405
PO		 213
214static const struct sdhci_pci_fixes sdhci_ricoh = {
215 .probe = ricoh_probe,
84938294
VK		 216 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR |
217 SDHCI_QUIRK_FORCE_DMA |
218 SDHCI_QUIRK_CLOCK_BEFORE_RESET,
22606405
PO		 219};
220
ccc92c23
ML		 221static const struct sdhci_pci_fixes sdhci_ricoh_mmc = {
222 .probe_slot = ricoh_mmc_probe_slot,
b7813f0f 223#ifdef CONFIG_PM_SLEEP
ccc92c23 224 .resume = ricoh_mmc_resume,
b7813f0f 225#endif
ccc92c23
ML		 226 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR |
227 SDHCI_QUIRK_CLOCK_BEFORE_RESET |
228 SDHCI_QUIRK_NO_CARD_NO_RESET |
229 SDHCI_QUIRK_MISSING_CAPS
230};
231
22606405
PO		 232static const struct sdhci_pci_fixes sdhci_ene_712 = {
233 .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE |
234 SDHCI_QUIRK_BROKEN_DMA,
235};
236
237static const struct sdhci_pci_fixes sdhci_ene_714 = {
238 .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE |
239 SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS |
240 SDHCI_QUIRK_BROKEN_DMA,
241};
242
243static const struct sdhci_pci_fixes sdhci_cafe = {
244 .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER |
a0874897 245 SDHCI_QUIRK_NO_BUSY_IRQ |
55fc05b7 246 SDHCI_QUIRK_BROKEN_CARD_DETECTION |
ee53ab5d 247 SDHCI_QUIRK_BROKEN_TIMEOUT_VAL,
22606405
PO		 248};
249
43e968ce
DB		 250static const struct sdhci_pci_fixes sdhci_intel_qrk = {
251 .quirks = SDHCI_QUIRK_NO_HISPD_BIT,
252};
253
68077b02
ML		 254static int mrst_hc_probe_slot(struct sdhci_pci_slot *slot)
255{
256 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA;
257 return 0;
258}
259
f9ee3eab
AC		 260/*
261 * ADMA operation is disabled for Moorestown platform due to
262 * hardware bugs.
263 */
35ac6f08 264static int mrst_hc_probe(struct sdhci_pci_chip *chip)
f9ee3eab
AC		 265{
266 /*
35ac6f08
JP		 267 * slots number is fixed here for MRST as SDIO3/5 are never used and
268 * have hardware bugs.
f9ee3eab
AC		 269 */
270 chip->num_slots = 1;
271 return 0;
272}
273
296e0b03
AS		 274static int pch_hc_probe_slot(struct sdhci_pci_slot *slot)
275{
276 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA;
277 return 0;
278}
279
162d6f98 280#ifdef CONFIG_PM
66fd8ad5 281
c5e027a4 282static irqreturn_t sdhci_pci_sd_cd(int irq, void *dev_id)
66fd8ad5
AH		 283{
284 struct sdhci_pci_slot *slot = dev_id;
285 struct sdhci_host *host = slot->host;
286
287 mmc_detect_change(host->mmc, msecs_to_jiffies(200));
288 return IRQ_HANDLED;
289}
290
c5e027a4 291static void sdhci_pci_add_own_cd(struct sdhci_pci_slot *slot)
66fd8ad5 292{
c5e027a4 293 int err, irq, gpio = slot->cd_gpio;
66fd8ad5
AH		 294
295 slot->cd_gpio = -EINVAL;
296 slot->cd_irq = -EINVAL;
297
c5e027a4
AH		 298 if (!gpio_is_valid(gpio))
299 return;
300
c10bc372 301 err = devm_gpio_request(&slot->chip->pdev->dev, gpio, "sd_cd");
66fd8ad5
AH		 302 if (err < 0)
303 goto out;
304
305 err = gpio_direction_input(gpio);
306 if (err < 0)
307 goto out_free;
308
309 irq = gpio_to_irq(gpio);
310 if (irq < 0)
311 goto out_free;
312
c5e027a4 313 err = request_irq(irq, sdhci_pci_sd_cd, IRQF_TRIGGER_RISING |
66fd8ad5
AH		 314 IRQF_TRIGGER_FALLING, "sd_cd", slot);
315 if (err)
316 goto out_free;
317
318 slot->cd_gpio = gpio;
319 slot->cd_irq = irq;
66fd8ad5 320
c5e027a4 321 return;
66fd8ad5
AH		 322
323out_free:
c10bc372 324 devm_gpio_free(&slot->chip->pdev->dev, gpio);
66fd8ad5
AH		 325out:
326 dev_warn(&slot->chip->pdev->dev, "failed to setup card detect wake up\n");
66fd8ad5
AH		 327}
328
c5e027a4 329static void sdhci_pci_remove_own_cd(struct sdhci_pci_slot *slot)
66fd8ad5
AH		 330{
331 if (slot->cd_irq >= 0)
332 free_irq(slot->cd_irq, slot);
66fd8ad5
AH		 333}
334
335#else
336
c5e027a4
AH		 337static inline void sdhci_pci_add_own_cd(struct sdhci_pci_slot *slot)
338{
339}
340
341static inline void sdhci_pci_remove_own_cd(struct sdhci_pci_slot *slot)
342{
343}
66fd8ad5
AH		 344
345#endif
346
0d013bcf
AH		 347static int mfd_emmc_probe_slot(struct sdhci_pci_slot *slot)
348{
66fd8ad5 349 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE;
da721cf7
AH		 350 slot->host->mmc->caps2 |= MMC_CAP2_BOOTPART_NOACC |
351 MMC_CAP2_HC_ERASE_SZ;
0d013bcf
AH		 352 return 0;
353}
354
93933508
AH		 355static int mfd_sdio_probe_slot(struct sdhci_pci_slot *slot)
356{
012e4671 357 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE;
93933508
AH		 358 return 0;
359}
360
f9ee3eab
AC		 361static const struct sdhci_pci_fixes sdhci_intel_mrst_hc0 = {
362 .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT,
68077b02 363 .probe_slot = mrst_hc_probe_slot,
f9ee3eab
AC		 364};
365
35ac6f08 366static const struct sdhci_pci_fixes sdhci_intel_mrst_hc1_hc2 = {
f9ee3eab 367 .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT,
35ac6f08 368 .probe = mrst_hc_probe,
f9ee3eab
AC		 369};
370
29229052
XS		 371static const struct sdhci_pci_fixes sdhci_intel_mfd_sd = {
372 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
c43fd774 373 .allow_runtime_pm = true,
77a0122e 374 .own_cd_for_runtime_pm = true,
29229052
XS		 375};
376
0d013bcf
AH		 377static const struct sdhci_pci_fixes sdhci_intel_mfd_sdio = {
378 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
f3c55a7b 379 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON,
c43fd774 380 .allow_runtime_pm = true,
93933508 381 .probe_slot = mfd_sdio_probe_slot,
0d013bcf
AH		 382};
383
384static const struct sdhci_pci_fixes sdhci_intel_mfd_emmc = {
29229052 385 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
c43fd774 386 .allow_runtime_pm = true,
0d013bcf 387 .probe_slot = mfd_emmc_probe_slot,
29229052
XS		 388};
389
296e0b03
AS		 390static const struct sdhci_pci_fixes sdhci_intel_pch_sdio = {
391 .quirks = SDHCI_QUIRK_BROKEN_ADMA,
392 .probe_slot = pch_hc_probe_slot,
393};
394
c959a6b0
AH		 395enum {
396 INTEL_DSM_FNS = 0,
51ced59c 397 INTEL_DSM_DRV_STRENGTH = 9,
c959a6b0
AH		 398 INTEL_DSM_D3_RETUNE = 10,
399};
400
401struct intel_host {
402 u32 dsm_fns;
51ced59c 403 int drv_strength;
c959a6b0
AH		 404 bool d3_retune;
405};
406
407const u8 intel_dsm_uuid[] = {
408 0xA5, 0x3E, 0xC1, 0xF6, 0xCD, 0x65, 0x1F, 0x46,
409 0xAB, 0x7A, 0x29, 0xF7, 0xE8, 0xD5, 0xBD, 0x61,
410};
411
412static int __intel_dsm(struct intel_host *intel_host, struct device *dev,
413 unsigned int fn, u32 *result)
414{
415 union acpi_object *obj;
416 int err = 0;
a72016a4 417 size_t len;
c959a6b0
AH		 418
419 obj = acpi_evaluate_dsm(ACPI_HANDLE(dev), intel_dsm_uuid, 0, fn, NULL);
420 if (!obj)
421 return -EOPNOTSUPP;
422
423 if (obj->type != ACPI_TYPE_BUFFER || obj->buffer.length < 1) {
424 err = -EINVAL;
425 goto out;
426 }
427
a72016a4
AH		 428 len = min_t(size_t, obj->buffer.length, 4);
429
430 *result = 0;
431 memcpy(result, obj->buffer.pointer, len);
c959a6b0
AH		 432out:
433 ACPI_FREE(obj);
434
435 return err;
436}
437
438static int intel_dsm(struct intel_host *intel_host, struct device *dev,
439 unsigned int fn, u32 *result)
440{
441 if (fn > 31 || !(intel_host->dsm_fns & (1 << fn)))
442 return -EOPNOTSUPP;
443
444 return __intel_dsm(intel_host, dev, fn, result);
445}
446
447static void intel_dsm_init(struct intel_host *intel_host, struct device *dev,
448 struct mmc_host *mmc)
449{
450 int err;
451 u32 val;
452
453 err = __intel_dsm(intel_host, dev, INTEL_DSM_FNS, &intel_host->dsm_fns);
454 if (err) {
455 pr_debug("%s: DSM not supported, error %d\n",
456 mmc_hostname(mmc), err);
457 return;
458 }
459
460 pr_debug("%s: DSM function mask %#x\n",
461 mmc_hostname(mmc), intel_host->dsm_fns);
462
51ced59c
AH		 463 err = intel_dsm(intel_host, dev, INTEL_DSM_DRV_STRENGTH, &val);
464 intel_host->drv_strength = err ? 0 : val;
465
c959a6b0
AH		 466 err = intel_dsm(intel_host, dev, INTEL_DSM_D3_RETUNE, &val);
467 intel_host->d3_retune = err ? true : !!val;
468}
469
c9faff6c
AH		 470static void sdhci_pci_int_hw_reset(struct sdhci_host *host)
471{
472 u8 reg;
473
474 reg = sdhci_readb(host, SDHCI_POWER_CONTROL);
475 reg |= 0x10;
476 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL);
477 /* For eMMC, minimum is 1us but give it 9us for good measure */
478 udelay(9);
479 reg &= ~0x10;
480 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL);
481 /* For eMMC, minimum is 200us but give it 300us for good measure */
482 usleep_range(300, 1000);
483}
484
51ced59c
AH		 485static int intel_select_drive_strength(struct mmc_card *card,
486 unsigned int max_dtr, int host_drv,
487 int card_drv, int *drv_type)
e1bfad6d 488{
51ced59c
AH		 489 struct sdhci_host *host = mmc_priv(card->host);
490 struct sdhci_pci_slot *slot = sdhci_priv(host);
491 struct intel_host *intel_host = sdhci_pci_priv(slot);
e1bfad6d 492
51ced59c 493 return intel_host->drv_strength;
e1bfad6d
AH		 494}
495
163cbe31
AH		 496static int bxt_get_cd(struct mmc_host *mmc)
497{
498 int gpio_cd = mmc_gpio_get_cd(mmc);
499 struct sdhci_host *host = mmc_priv(mmc);
500 unsigned long flags;
501 int ret = 0;
502
503 if (!gpio_cd)
504 return 0;
505
163cbe31
AH		 506 spin_lock_irqsave(&host->lock, flags);
507
508 if (host->flags & SDHCI_DEVICE_DEAD)
509 goto out;
510
511 ret = !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
512out:
513 spin_unlock_irqrestore(&host->lock, flags);
514
163cbe31
AH		 515 return ret;
516}
517
48d685a2
AH		 518#define SDHCI_INTEL_PWR_TIMEOUT_CNT 20
519#define SDHCI_INTEL_PWR_TIMEOUT_UDELAY 100
520
521static void sdhci_intel_set_power(struct sdhci_host *host, unsigned char mode,
522 unsigned short vdd)
523{
524 int cntr;
525 u8 reg;
526
527 sdhci_set_power(host, mode, vdd);
528
529 if (mode == MMC_POWER_OFF)
530 return;
531
532 /*
533 * Bus power might not enable after D3 -> D0 transition due to the
534 * present state not yet having propagated. Retry for up to 2ms.
535 */
536 for (cntr = 0; cntr < SDHCI_INTEL_PWR_TIMEOUT_CNT; cntr++) {
537 reg = sdhci_readb(host, SDHCI_POWER_CONTROL);
538 if (reg & SDHCI_POWER_ON)
539 break;
540 udelay(SDHCI_INTEL_PWR_TIMEOUT_UDELAY);
541 reg |= SDHCI_POWER_ON;
542 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL);
543 }
544}
545
546static const struct sdhci_ops sdhci_intel_byt_ops = {
547 .set_clock = sdhci_set_clock,
548 .set_power = sdhci_intel_set_power,
549 .enable_dma = sdhci_pci_enable_dma,
550 .set_bus_width = sdhci_pci_set_bus_width,
551 .reset = sdhci_reset,
552 .set_uhs_signaling = sdhci_set_uhs_signaling,
553 .hw_reset = sdhci_pci_hw_reset,
554};
555
c959a6b0
AH		 556static void byt_read_dsm(struct sdhci_pci_slot *slot)
557{
558 struct intel_host *intel_host = sdhci_pci_priv(slot);
559 struct device *dev = &slot->chip->pdev->dev;
560 struct mmc_host *mmc = slot->host->mmc;
561
562 intel_dsm_init(intel_host, dev, mmc);
563 slot->chip->rpm_retune = intel_host->d3_retune;
564}
565
728ef3d1
AH		 566static int byt_emmc_probe_slot(struct sdhci_pci_slot *slot)
567{
c959a6b0 568 byt_read_dsm(slot);
c9faff6c 569 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE |
6aab23a8 570 MMC_CAP_HW_RESET | MMC_CAP_1_8V_DDR |
32828857 571 MMC_CAP_CMD_DURING_TFR |
6aab23a8 572 MMC_CAP_WAIT_WHILE_BUSY;
728ef3d1 573 slot->host->mmc->caps2 |= MMC_CAP2_HC_ERASE_SZ;
c9faff6c 574 slot->hw_reset = sdhci_pci_int_hw_reset;
a06586b6
AH		 575 if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BSW_EMMC)
576 slot->host->timeout_clk = 1000; /* 1000 kHz i.e. 1 MHz */
51ced59c
AH		 577 slot->host->mmc_host_ops.select_drive_strength =
578 intel_select_drive_strength;
728ef3d1
AH		 579 return 0;
580}
581
3f23df72
ZB		 582#ifdef CONFIG_ACPI
583static int ni_set_max_freq(struct sdhci_pci_slot *slot)
584{
585 acpi_status status;
586 unsigned long long max_freq;
587
588 status = acpi_evaluate_integer(ACPI_HANDLE(&slot->chip->pdev->dev),
589 "MXFQ", NULL, &max_freq);
590 if (ACPI_FAILURE(status)) {
591 dev_err(&slot->chip->pdev->dev,
592 "MXFQ not found in acpi table\n");
593 return -EINVAL;
594 }
595
596 slot->host->mmc->f_max = max_freq * 1000000;
597
598 return 0;
599}
600#else
601static inline int ni_set_max_freq(struct sdhci_pci_slot *slot)
602{
603 return 0;
604}
605#endif
606
42b06496
ZB		 607static int ni_byt_sdio_probe_slot(struct sdhci_pci_slot *slot)
608{
3f23df72
ZB		 609 int err;
610
c959a6b0
AH		 611 byt_read_dsm(slot);
612
3f23df72
ZB		 613 err = ni_set_max_freq(slot);
614 if (err)
615 return err;
616
42b06496
ZB		 617 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE |
618 MMC_CAP_WAIT_WHILE_BUSY;
619 return 0;
620}
621
728ef3d1
AH		 622static int byt_sdio_probe_slot(struct sdhci_pci_slot *slot)
623{
c959a6b0 624 byt_read_dsm(slot);
6aab23a8 625 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE |
6aab23a8 626 MMC_CAP_WAIT_WHILE_BUSY;
728ef3d1
AH		 627 return 0;
628}
629
ff59c520
AH		 630static int byt_sd_probe_slot(struct sdhci_pci_slot *slot)
631{
c959a6b0 632 byt_read_dsm(slot);
c2c49a2e
AS		 633 slot->host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY |
634 MMC_CAP_AGGRESSIVE_PM;
ff59c520
AH		 635 slot->cd_idx = 0;
636 slot->cd_override_level = true;
163cbe31 637 if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BXT_SD ||
01d6b2a4 638 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BXTM_SD ||
2d1956d0 639 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_APL_SD ||
c2c49a2e 640 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_GLK_SD)
163cbe31
AH		 641 slot->host->mmc_host_ops.get_cd = bxt_get_cd;
642
ff59c520
AH		 643 return 0;
644}
645
728ef3d1
AH		 646static const struct sdhci_pci_fixes sdhci_intel_byt_emmc = {
647 .allow_runtime_pm = true,
648 .probe_slot = byt_emmc_probe_slot,
db6e8cdf 649 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
e58e4a0d 650 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
b69587e2 651 SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 |
e58e4a0d 652 SDHCI_QUIRK2_STOP_WITH_TC,
fee686b7 653 .ops = &sdhci_intel_byt_ops,
c959a6b0 654 .priv_size = sizeof(struct intel_host),
728ef3d1
AH		 655};
656
42b06496
ZB		 657static const struct sdhci_pci_fixes sdhci_ni_byt_sdio = {
658 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
659 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON |
660 SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
661 .allow_runtime_pm = true,
662 .probe_slot = ni_byt_sdio_probe_slot,
663 .ops = &sdhci_intel_byt_ops,
c959a6b0 664 .priv_size = sizeof(struct intel_host),
42b06496
ZB		 665};
666
728ef3d1 667static const struct sdhci_pci_fixes sdhci_intel_byt_sdio = {
db6e8cdf 668 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
b7574bad
GY		 669 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON |
670 SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
728ef3d1
AH		 671 .allow_runtime_pm = true,
672 .probe_slot = byt_sdio_probe_slot,
fee686b7 673 .ops = &sdhci_intel_byt_ops,
c959a6b0 674 .priv_size = sizeof(struct intel_host),
728ef3d1
AH		 675};
676
677static const struct sdhci_pci_fixes sdhci_intel_byt_sd = {
db6e8cdf 678 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
b7574bad 679 .quirks2 = SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON |
e58e4a0d
AH		 680 SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
681 SDHCI_QUIRK2_STOP_WITH_TC,
7396e318 682 .allow_runtime_pm = true,
77a0122e 683 .own_cd_for_runtime_pm = true,
ff59c520 684 .probe_slot = byt_sd_probe_slot,
fee686b7 685 .ops = &sdhci_intel_byt_ops,
c959a6b0 686 .priv_size = sizeof(struct intel_host),
728ef3d1
AH		 687};
688
8776a165 689/* Define Host controllers for Intel Merrifield platform */
1f64cec2
AS		 690#define INTEL_MRFLD_EMMC_0 0
691#define INTEL_MRFLD_EMMC_1 1
4674b6c8 692#define INTEL_MRFLD_SD 2
d5565577 693#define INTEL_MRFLD_SDIO 3
8776a165 694
1f64cec2 695static int intel_mrfld_mmc_probe_slot(struct sdhci_pci_slot *slot)
8776a165 696{
2e57bbe2
AS		 697 unsigned int func = PCI_FUNC(slot->chip->pdev->devfn);
698
699 switch (func) {
700 case INTEL_MRFLD_EMMC_0:
701 case INTEL_MRFLD_EMMC_1:
702 slot->host->mmc->caps |= MMC_CAP_NONREMOVABLE |
703 MMC_CAP_8_BIT_DATA |
704 MMC_CAP_1_8V_DDR;
705 break;
4674b6c8
AS		 706 case INTEL_MRFLD_SD:
707 slot->host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V;
708 break;
d5565577
AS		 709 case INTEL_MRFLD_SDIO:
710 slot->host->mmc->caps |= MMC_CAP_NONREMOVABLE |
711 MMC_CAP_POWER_OFF_CARD;
712 break;
2e57bbe2 713 default:
8776a165 714 return -ENODEV;
2e57bbe2 715 }
8776a165
DC		 716 return 0;
717}
718
1f64cec2 719static const struct sdhci_pci_fixes sdhci_intel_mrfld_mmc = {
8776a165 720 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
b7574bad
GY		 721 .quirks2 = SDHCI_QUIRK2_BROKEN_HS200 |
722 SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
f1b55a55 723 .allow_runtime_pm = true,
1f64cec2 724 .probe_slot = intel_mrfld_mmc_probe_slot,
8776a165
DC		 725};
726
26daa1ed
JL		 727/* O2Micro extra registers */
728#define O2_SD_LOCK_WP 0xD3
729#define O2_SD_MULTI_VCC3V 0xEE
730#define O2_SD_CLKREQ 0xEC
731#define O2_SD_CAPS 0xE0
732#define O2_SD_ADMA1 0xE2
733#define O2_SD_ADMA2 0xE7
734#define O2_SD_INF_MOD 0xF1
735
45211e21
PO		 736static int jmicron_pmos(struct sdhci_pci_chip *chip, int on)
737{
738 u8 scratch;
739 int ret;
740
741 ret = pci_read_config_byte(chip->pdev, 0xAE, &scratch);
742 if (ret)
743 return ret;
744
745 /*
746 * Turn PMOS on [bit 0], set over current detection to 2.4 V
747 * [bit 1:2] and enable over current debouncing [bit 6].
748 */
749 if (on)
750 scratch |= 0x47;
751 else
752 scratch &= ~0x47;
753
7582041f 754 return pci_write_config_byte(chip->pdev, 0xAE, scratch);
45211e21
PO		 755}
756
757static int jmicron_probe(struct sdhci_pci_chip *chip)
758{
759 int ret;
8f230f45 760 u16 mmcdev = 0;
45211e21 761
93fc48c7
PO		 762 if (chip->pdev->revision == 0) {
763 chip->quirks |= SDHCI_QUIRK_32BIT_DMA_ADDR |
764 SDHCI_QUIRK_32BIT_DMA_SIZE |
2134a922 765 SDHCI_QUIRK_32BIT_ADMA_SIZE |
4a3cba32 766 SDHCI_QUIRK_RESET_AFTER_REQUEST |
86a6a874 767 SDHCI_QUIRK_BROKEN_SMALL_PIO;
93fc48c7
PO		 768 }
769
4489428a
PO		 770 /*
771 * JMicron chips can have two interfaces to the same hardware
772 * in order to work around limitations in Microsoft's driver.
773 * We need to make sure we only bind to one of them.
774 *
775 * This code assumes two things:
776 *
777 * 1. The PCI code adds subfunctions in order.
778 *
779 * 2. The MMC interface has a lower subfunction number
780 * than the SD interface.
781 */
8f230f45
TI		 782 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_SD)
783 mmcdev = PCI_DEVICE_ID_JMICRON_JMB38X_MMC;
784 else if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD)
785 mmcdev = PCI_DEVICE_ID_JMICRON_JMB388_ESD;
786
787 if (mmcdev) {
4489428a
PO		 788 struct pci_dev *sd_dev;
789
790 sd_dev = NULL;
791 while ((sd_dev = pci_get_device(PCI_VENDOR_ID_JMICRON,
8f230f45 792 mmcdev, sd_dev)) != NULL) {
4489428a
PO		 793 if ((PCI_SLOT(chip->pdev->devfn) ==
794 PCI_SLOT(sd_dev->devfn)) &&
795 (chip->pdev->bus == sd_dev->bus))
796 break;
797 }
798
799 if (sd_dev) {
800 pci_dev_put(sd_dev);
801 dev_info(&chip->pdev->dev, "Refusing to bind to "
802 "secondary interface.\n");
803 return -ENODEV;
804 }
805 }
806
45211e21
PO		 807 /*
808 * JMicron chips need a bit of a nudge to enable the power
809 * output pins.
810 */
811 ret = jmicron_pmos(chip, 1);
812 if (ret) {
813 dev_err(&chip->pdev->dev, "Failure enabling card power\n");
814 return ret;
815 }
816
82b0e23a
TI		 817 /* quirk for unsable RO-detection on JM388 chips */
818 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD ||
819 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD)
820 chip->quirks |= SDHCI_QUIRK_UNSTABLE_RO_DETECT;
821
45211e21
PO		 822 return 0;
823}
824
4489428a
PO		 825static void jmicron_enable_mmc(struct sdhci_host *host, int on)
826{
827 u8 scratch;
828
829 scratch = readb(host->ioaddr + 0xC0);
830
831 if (on)
832 scratch |= 0x01;
833 else
834 scratch &= ~0x01;
835
836 writeb(scratch, host->ioaddr + 0xC0);
837}
838
839static int jmicron_probe_slot(struct sdhci_pci_slot *slot)
840{
2134a922
PO		 841 if (slot->chip->pdev->revision == 0) {
842 u16 version;
843
844 version = readl(slot->host->ioaddr + SDHCI_HOST_VERSION);
845 version = (version & SDHCI_VENDOR_VER_MASK) >>
846 SDHCI_VENDOR_VER_SHIFT;
847
848 /*
849 * Older versions of the chip have lots of nasty glitches
850 * in the ADMA engine. It's best just to avoid it
851 * completely.
852 */
853 if (version < 0xAC)
854 slot->host->quirks |= SDHCI_QUIRK_BROKEN_ADMA;
855 }
856
8f230f45
TI		 857 /* JM388 MMC doesn't support 1.8V while SD supports it */
858 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) {
859 slot->host->ocr_avail_sd = MMC_VDD_32_33 | MMC_VDD_33_34 |
860 MMC_VDD_29_30 | MMC_VDD_30_31 |
861 MMC_VDD_165_195; /* allow 1.8V */
862 slot->host->ocr_avail_mmc = MMC_VDD_32_33 | MMC_VDD_33_34 |
863 MMC_VDD_29_30 | MMC_VDD_30_31; /* no 1.8V for MMC */
864 }
865
4489428a
PO		 866 /*
867 * The secondary interface requires a bit set to get the
868 * interrupts.
869 */
8f230f45
TI		 870 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
871 slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD)
4489428a
PO		 872 jmicron_enable_mmc(slot->host, 1);
873
d75c1084
TI		 874 slot->host->mmc->caps |= MMC_CAP_BUS_WIDTH_TEST;
875
4489428a
PO		 876 return 0;
877}
878
1e72859e 879static void jmicron_remove_slot(struct sdhci_pci_slot *slot, int dead)
4489428a 880{
1e72859e
PO		 881 if (dead)
882 return;
883
8f230f45
TI		 884 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
885 slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD)
4489428a
PO		 886 jmicron_enable_mmc(slot->host, 0);
887}
888
b7813f0f 889#ifdef CONFIG_PM_SLEEP
29495aa0 890static int jmicron_suspend(struct sdhci_pci_chip *chip)
4489428a 891{
30cf2803
AH		 892 int i, ret;
893
894 ret = __sdhci_pci_suspend_host(chip);
895 if (ret)
896 return ret;
4489428a 897
8f230f45
TI		 898 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
899 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) {
b177bc91 900 for (i = 0; i < chip->num_slots; i++)
4489428a
PO		 901 jmicron_enable_mmc(chip->slots[i]->host, 0);
902 }
903
30cf2803
AH		 904 sdhci_pci_init_wakeup(chip);
905
4489428a
PO		 906 return 0;
907}
908
45211e21
PO		 909static int jmicron_resume(struct sdhci_pci_chip *chip)
910{
4489428a
PO		 911 int ret, i;
912
8f230f45
TI		 913 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
914 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) {
b177bc91 915 for (i = 0; i < chip->num_slots; i++)
4489428a
PO		 916 jmicron_enable_mmc(chip->slots[i]->host, 1);
917 }
45211e21
PO		 918
919 ret = jmicron_pmos(chip, 1);
920 if (ret) {
921 dev_err(&chip->pdev->dev, "Failure enabling card power\n");
922 return ret;
923 }
924
30cf2803 925 return sdhci_pci_resume_host(chip);
45211e21 926}
b7813f0f 927#endif
45211e21 928
26daa1ed 929static const struct sdhci_pci_fixes sdhci_o2 = {
01acf691
AL		 930 .probe = sdhci_pci_o2_probe,
931 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
143b648d 932 .quirks2 = SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD,
01acf691 933 .probe_slot = sdhci_pci_o2_probe_slot,
b7813f0f 934#ifdef CONFIG_PM_SLEEP
01acf691 935 .resume = sdhci_pci_o2_resume,
b7813f0f 936#endif
26daa1ed
JL		 937};
938
22606405 939static const struct sdhci_pci_fixes sdhci_jmicron = {
45211e21
PO		 940 .probe = jmicron_probe,
941
4489428a
PO		 942 .probe_slot = jmicron_probe_slot,
943 .remove_slot = jmicron_remove_slot,
944
b7813f0f 945#ifdef CONFIG_PM_SLEEP
4489428a 946 .suspend = jmicron_suspend,
45211e21 947 .resume = jmicron_resume,
b7813f0f 948#endif
22606405
PO		 949};
950
a7a6186c
NP		 951/* SysKonnect CardBus2SDIO extra registers */
952#define SYSKT_CTRL 0x200
953#define SYSKT_RDFIFO_STAT 0x204
954#define SYSKT_WRFIFO_STAT 0x208
955#define SYSKT_POWER_DATA 0x20c
956#define SYSKT_POWER_330 0xef
957#define SYSKT_POWER_300 0xf8
958#define SYSKT_POWER_184 0xcc
959#define SYSKT_POWER_CMD 0x20d
960#define SYSKT_POWER_START (1 << 7)
961#define SYSKT_POWER_STATUS 0x20e
962#define SYSKT_POWER_STATUS_OK (1 << 0)
963#define SYSKT_BOARD_REV 0x210
964#define SYSKT_CHIP_REV 0x211
965#define SYSKT_CONF_DATA 0x212
966#define SYSKT_CONF_DATA_1V8 (1 << 2)
967#define SYSKT_CONF_DATA_2V5 (1 << 1)
968#define SYSKT_CONF_DATA_3V3 (1 << 0)
969
970static int syskt_probe(struct sdhci_pci_chip *chip)
971{
972 if ((chip->pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) {
973 chip->pdev->class &= ~0x0000FF;
974 chip->pdev->class |= PCI_SDHCI_IFDMA;
975 }
976 return 0;
977}
978
979static int syskt_probe_slot(struct sdhci_pci_slot *slot)
980{
981 int tm, ps;
982
983 u8 board_rev = readb(slot->host->ioaddr + SYSKT_BOARD_REV);
984 u8 chip_rev = readb(slot->host->ioaddr + SYSKT_CHIP_REV);
985 dev_info(&slot->chip->pdev->dev, "SysKonnect CardBus2SDIO, "
986 "board rev %d.%d, chip rev %d.%d\n",
987 board_rev >> 4, board_rev & 0xf,
988 chip_rev >> 4, chip_rev & 0xf);
989 if (chip_rev >= 0x20)
990 slot->host->quirks |= SDHCI_QUIRK_FORCE_DMA;
991
992 writeb(SYSKT_POWER_330, slot->host->ioaddr + SYSKT_POWER_DATA);
993 writeb(SYSKT_POWER_START, slot->host->ioaddr + SYSKT_POWER_CMD);
994 udelay(50);
995 tm = 10; /* Wait max 1 ms */
996 do {
997 ps = readw(slot->host->ioaddr + SYSKT_POWER_STATUS);
998 if (ps & SYSKT_POWER_STATUS_OK)
999 break;
1000 udelay(100);
1001 } while (--tm);
1002 if (!tm) {
1003 dev_err(&slot->chip->pdev->dev,
1004 "power regulator never stabilized");
1005 writeb(0, slot->host->ioaddr + SYSKT_POWER_CMD);
1006 return -ENODEV;
1007 }
1008
1009 return 0;
1010}
1011
1012static const struct sdhci_pci_fixes sdhci_syskt = {
1013 .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER,
1014 .probe = syskt_probe,
1015 .probe_slot = syskt_probe_slot,
1016};
1017
557b0697
HW		 1018static int via_probe(struct sdhci_pci_chip *chip)
1019{
1020 if (chip->pdev->revision == 0x10)
1021 chip->quirks |= SDHCI_QUIRK_DELAY_AFTER_POWER;
1022
1023 return 0;
1024}
1025
1026static const struct sdhci_pci_fixes sdhci_via = {
1027 .probe = via_probe,
1028};
1029
9107ebbf
MC		 1030static int rtsx_probe_slot(struct sdhci_pci_slot *slot)
1031{
1032 slot->host->mmc->caps2 |= MMC_CAP2_HS200;
1033 return 0;
1034}
1035
1036static const struct sdhci_pci_fixes sdhci_rtsx = {
1037 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
e30b978f 1038 SDHCI_QUIRK2_BROKEN_64_BIT_DMA |
9107ebbf
MC		 1039 SDHCI_QUIRK2_BROKEN_DDR50,
1040 .probe_slot = rtsx_probe_slot,
1041};
1042
b5e97d6e
VW		 1043/*AMD chipset generation*/
1044enum amd_chipset_gen {
1045 AMD_CHIPSET_BEFORE_ML,
1046 AMD_CHIPSET_CZ,
1047 AMD_CHIPSET_NL,
1048 AMD_CHIPSET_UNKNOWN,
1049};
1050
c31165d7
SS		 1051/* AMD registers */
1052#define AMD_SD_AUTO_PATTERN 0xB8
1053#define AMD_MSLEEP_DURATION 4
1054#define AMD_SD_MISC_CONTROL 0xD0
1055#define AMD_MAX_TUNE_VALUE 0x0B
1056#define AMD_AUTO_TUNE_SEL 0x10800
1057#define AMD_FIFO_PTR 0x30
1058#define AMD_BIT_MASK 0x1F
1059
1060static void amd_tuning_reset(struct sdhci_host *host)
1061{
1062 unsigned int val;
1063
1064 val = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1065 val |= SDHCI_CTRL_PRESET_VAL_ENABLE | SDHCI_CTRL_EXEC_TUNING;
1066 sdhci_writew(host, val, SDHCI_HOST_CONTROL2);
1067
1068 val = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1069 val &= ~SDHCI_CTRL_EXEC_TUNING;
1070 sdhci_writew(host, val, SDHCI_HOST_CONTROL2);
1071}
1072
1073static void amd_config_tuning_phase(struct pci_dev *pdev, u8 phase)
1074{
1075 unsigned int val;
1076
1077 pci_read_config_dword(pdev, AMD_SD_AUTO_PATTERN, &val);
1078 val &= ~AMD_BIT_MASK;
1079 val |= (AMD_AUTO_TUNE_SEL | (phase << 1));
1080 pci_write_config_dword(pdev, AMD_SD_AUTO_PATTERN, val);
1081}
1082
1083static void amd_enable_manual_tuning(struct pci_dev *pdev)
1084{
1085 unsigned int val;
1086
1087 pci_read_config_dword(pdev, AMD_SD_MISC_CONTROL, &val);
1088 val |= AMD_FIFO_PTR;
1089 pci_write_config_dword(pdev, AMD_SD_MISC_CONTROL, val);
1090}
1091
1092static int amd_execute_tuning(struct sdhci_host *host, u32 opcode)
1093{
1094 struct sdhci_pci_slot *slot = sdhci_priv(host);
1095 struct pci_dev *pdev = slot->chip->pdev;
1096 u8 valid_win = 0;
1097 u8 valid_win_max = 0;
1098 u8 valid_win_end = 0;
1099 u8 ctrl, tune_around;
1100
1101 amd_tuning_reset(host);
1102
1103 for (tune_around = 0; tune_around < 12; tune_around++) {
1104 amd_config_tuning_phase(pdev, tune_around);
1105
1106 if (mmc_send_tuning(host->mmc, opcode, NULL)) {
1107 valid_win = 0;
1108 msleep(AMD_MSLEEP_DURATION);
1109 ctrl = SDHCI_RESET_CMD | SDHCI_RESET_DATA;
1110 sdhci_writeb(host, ctrl, SDHCI_SOFTWARE_RESET);
1111 } else if (++valid_win > valid_win_max) {
1112 valid_win_max = valid_win;
1113 valid_win_end = tune_around;
1114 }
1115 }
1116
1117 if (!valid_win_max) {
1118 dev_err(&pdev->dev, "no tuning point found\n");
1119 return -EIO;
1120 }
1121
1122 amd_config_tuning_phase(pdev, valid_win_end - valid_win_max / 2);
1123
1124 amd_enable_manual_tuning(pdev);
1125
1126 host->mmc->retune_period = 0;
1127
1128 return 0;
1129}
1130
d44f88da
VW		 1131static int amd_probe(struct sdhci_pci_chip *chip)
1132{
1133 struct pci_dev *smbus_dev;
b5e97d6e 1134 enum amd_chipset_gen gen;
d44f88da
VW		 1135
1136 smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD,
1137 PCI_DEVICE_ID_AMD_HUDSON2_SMBUS, NULL);
b5e97d6e
VW		 1138 if (smbus_dev) {
1139 gen = AMD_CHIPSET_BEFORE_ML;
1140 } else {
1141 smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD,
1142 PCI_DEVICE_ID_AMD_KERNCZ_SMBUS, NULL);
1143 if (smbus_dev) {
1144 if (smbus_dev->revision < 0x51)
1145 gen = AMD_CHIPSET_CZ;
1146 else
1147 gen = AMD_CHIPSET_NL;
1148 } else {
1149 gen = AMD_CHIPSET_UNKNOWN;
1150 }
1151 }
d44f88da 1152
c31165d7 1153 if (gen == AMD_CHIPSET_BEFORE_ML || gen == AMD_CHIPSET_CZ)
d44f88da
VW		 1154 chip->quirks2 |= SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD;
1155
1156 return 0;
1157}
1158
c31165d7
SS		 1159static const struct sdhci_ops amd_sdhci_pci_ops = {
1160 .set_clock = sdhci_set_clock,
1161 .enable_dma = sdhci_pci_enable_dma,
1162 .set_bus_width = sdhci_pci_set_bus_width,
1163 .reset = sdhci_reset,
1164 .set_uhs_signaling = sdhci_set_uhs_signaling,
1165 .platform_execute_tuning = amd_execute_tuning,
1166};
1167
d44f88da
VW		 1168static const struct sdhci_pci_fixes sdhci_amd = {
1169 .probe = amd_probe,
c31165d7 1170 .ops = &amd_sdhci_pci_ops,
d44f88da
VW		 1171};
1172
9647f84d 1173static const struct pci_device_id pci_ids[] = {
b8c86fc5
PO		 1174 {
1175 .vendor = PCI_VENDOR_ID_RICOH,
1176 .device = PCI_DEVICE_ID_RICOH_R5C822,
22606405 1177 .subvendor = PCI_ANY_ID,
b8c86fc5 1178 .subdevice = PCI_ANY_ID,
22606405 1179 .driver_data = (kernel_ulong_t)&sdhci_ricoh,
b8c86fc5
PO		 1180 },
1181
ccc92c23
ML		 1182 {
1183 .vendor = PCI_VENDOR_ID_RICOH,
1184 .device = 0x843,
1185 .subvendor = PCI_ANY_ID,
1186 .subdevice = PCI_ANY_ID,
1187 .driver_data = (kernel_ulong_t)&sdhci_ricoh_mmc,
1188 },
1189
568133eb
PC		 1190 {
1191 .vendor = PCI_VENDOR_ID_RICOH,
1192 .device = 0xe822,
1193 .subvendor = PCI_ANY_ID,
1194 .subdevice = PCI_ANY_ID,
1195 .driver_data = (kernel_ulong_t)&sdhci_ricoh_mmc,
1196 },
1197
5fd11c07
MI		 1198 {
1199 .vendor = PCI_VENDOR_ID_RICOH,
1200 .device = 0xe823,
1201 .subvendor = PCI_ANY_ID,
1202 .subdevice = PCI_ANY_ID,
1203 .driver_data = (kernel_ulong_t)&sdhci_ricoh_mmc,
1204 },
1205
b8c86fc5
PO		 1206 {
1207 .vendor = PCI_VENDOR_ID_ENE,
1208 .device = PCI_DEVICE_ID_ENE_CB712_SD,
1209 .subvendor = PCI_ANY_ID,
1210 .subdevice = PCI_ANY_ID,
22606405 1211 .driver_data = (kernel_ulong_t)&sdhci_ene_712,
b8c86fc5
PO		 1212 },
1213
1214 {
1215 .vendor = PCI_VENDOR_ID_ENE,
1216 .device = PCI_DEVICE_ID_ENE_CB712_SD_2,
1217 .subvendor = PCI_ANY_ID,
1218 .subdevice = PCI_ANY_ID,
22606405 1219 .driver_data = (kernel_ulong_t)&sdhci_ene_712,
b8c86fc5
PO		 1220 },
1221
1222 {
1223 .vendor = PCI_VENDOR_ID_ENE,
1224 .device = PCI_DEVICE_ID_ENE_CB714_SD,
1225 .subvendor = PCI_ANY_ID,
1226 .subdevice = PCI_ANY_ID,
22606405 1227 .driver_data = (kernel_ulong_t)&sdhci_ene_714,
b8c86fc5
PO		 1228 },
1229
1230 {
1231 .vendor = PCI_VENDOR_ID_ENE,
1232 .device = PCI_DEVICE_ID_ENE_CB714_SD_2,
1233 .subvendor = PCI_ANY_ID,
1234 .subdevice = PCI_ANY_ID,
22606405 1235 .driver_data = (kernel_ulong_t)&sdhci_ene_714,
b8c86fc5
PO		 1236 },
1237
1238 {
1239 .vendor = PCI_VENDOR_ID_MARVELL,
8c5eb880 1240 .device = PCI_DEVICE_ID_MARVELL_88ALP01_SD,
b8c86fc5
PO		 1241 .subvendor = PCI_ANY_ID,
1242 .subdevice = PCI_ANY_ID,
22606405 1243 .driver_data = (kernel_ulong_t)&sdhci_cafe,
b8c86fc5
PO		 1244 },
1245
1246 {
1247 .vendor = PCI_VENDOR_ID_JMICRON,
1248 .device = PCI_DEVICE_ID_JMICRON_JMB38X_SD,
1249 .subvendor = PCI_ANY_ID,
1250 .subdevice = PCI_ANY_ID,
22606405 1251 .driver_data = (kernel_ulong_t)&sdhci_jmicron,
b8c86fc5
PO		 1252 },
1253
4489428a
PO		 1254 {
1255 .vendor = PCI_VENDOR_ID_JMICRON,
1256 .device = PCI_DEVICE_ID_JMICRON_JMB38X_MMC,
1257 .subvendor = PCI_ANY_ID,
1258 .subdevice = PCI_ANY_ID,
1259 .driver_data = (kernel_ulong_t)&sdhci_jmicron,
8f230f45
TI		 1260 },
1261
1262 {
1263 .vendor = PCI_VENDOR_ID_JMICRON,
1264 .device = PCI_DEVICE_ID_JMICRON_JMB388_SD,
1265 .subvendor = PCI_ANY_ID,
1266 .subdevice = PCI_ANY_ID,
1267 .driver_data = (kernel_ulong_t)&sdhci_jmicron,
1268 },
1269
1270 {
1271 .vendor = PCI_VENDOR_ID_JMICRON,
1272 .device = PCI_DEVICE_ID_JMICRON_JMB388_ESD,
1273 .subvendor = PCI_ANY_ID,
1274 .subdevice = PCI_ANY_ID,
1275 .driver_data = (kernel_ulong_t)&sdhci_jmicron,
4489428a
PO		 1276 },
1277
a7a6186c
NP		 1278 {
1279 .vendor = PCI_VENDOR_ID_SYSKONNECT,
1280 .device = 0x8000,
1281 .subvendor = PCI_ANY_ID,
1282 .subdevice = PCI_ANY_ID,
1283 .driver_data = (kernel_ulong_t)&sdhci_syskt,
1284 },
1285
557b0697
HW		 1286 {
1287 .vendor = PCI_VENDOR_ID_VIA,
1288 .device = 0x95d0,
1289 .subvendor = PCI_ANY_ID,
1290 .subdevice = PCI_ANY_ID,
1291 .driver_data = (kernel_ulong_t)&sdhci_via,
9107ebbf
MC		 1292 },
1293
1294 {
1295 .vendor = PCI_VENDOR_ID_REALTEK,
1296 .device = 0x5250,
1297 .subvendor = PCI_ANY_ID,
1298 .subdevice = PCI_ANY_ID,
1299 .driver_data = (kernel_ulong_t)&sdhci_rtsx,
557b0697
HW		 1300 },
1301
43e968ce
DB		 1302 {
1303 .vendor = PCI_VENDOR_ID_INTEL,
1304 .device = PCI_DEVICE_ID_INTEL_QRK_SD,
1305 .subvendor = PCI_ANY_ID,
1306 .subdevice = PCI_ANY_ID,
1307 .driver_data = (kernel_ulong_t)&sdhci_intel_qrk,
1308 },
1309
29229052
XS		 1310 {
1311 .vendor = PCI_VENDOR_ID_INTEL,
f9ee3eab
AC		 1312 .device = PCI_DEVICE_ID_INTEL_MRST_SD0,
1313 .subvendor = PCI_ANY_ID,
1314 .subdevice = PCI_ANY_ID,
1315 .driver_data = (kernel_ulong_t)&sdhci_intel_mrst_hc0,
1316 },
1317
1318 {
1319 .vendor = PCI_VENDOR_ID_INTEL,
1320 .device = PCI_DEVICE_ID_INTEL_MRST_SD1,
1321 .subvendor = PCI_ANY_ID,
1322 .subdevice = PCI_ANY_ID,
35ac6f08
JP		 1323 .driver_data = (kernel_ulong_t)&sdhci_intel_mrst_hc1_hc2,
1324 },
1325
1326 {
1327 .vendor = PCI_VENDOR_ID_INTEL,
1328 .device = PCI_DEVICE_ID_INTEL_MRST_SD2,
1329 .subvendor = PCI_ANY_ID,
1330 .subdevice = PCI_ANY_ID,
1331 .driver_data = (kernel_ulong_t)&sdhci_intel_mrst_hc1_hc2,
f9ee3eab
AC		 1332 },
1333
1334 {
1335 .vendor = PCI_VENDOR_ID_INTEL,
29229052
XS		 1336 .device = PCI_DEVICE_ID_INTEL_MFD_SD,
1337 .subvendor = PCI_ANY_ID,
1338 .subdevice = PCI_ANY_ID,
1339 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sd,
1340 },
1341
1342 {
1343 .vendor = PCI_VENDOR_ID_INTEL,
1344 .device = PCI_DEVICE_ID_INTEL_MFD_SDIO1,
1345 .subvendor = PCI_ANY_ID,
1346 .subdevice = PCI_ANY_ID,
0d013bcf 1347 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sdio,
29229052
XS		 1348 },
1349
1350 {
1351 .vendor = PCI_VENDOR_ID_INTEL,
1352 .device = PCI_DEVICE_ID_INTEL_MFD_SDIO2,
1353 .subvendor = PCI_ANY_ID,
1354 .subdevice = PCI_ANY_ID,
0d013bcf 1355 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sdio,
29229052
XS		 1356 },
1357
1358 {
1359 .vendor = PCI_VENDOR_ID_INTEL,
1360 .device = PCI_DEVICE_ID_INTEL_MFD_EMMC0,
1361 .subvendor = PCI_ANY_ID,
1362 .subdevice = PCI_ANY_ID,
0d013bcf 1363 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc,
29229052
XS		 1364 },
1365
1366 {
1367 .vendor = PCI_VENDOR_ID_INTEL,
1368 .device = PCI_DEVICE_ID_INTEL_MFD_EMMC1,
1369 .subvendor = PCI_ANY_ID,
1370 .subdevice = PCI_ANY_ID,
0d013bcf 1371 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc,
29229052
XS		 1372 },
1373
296e0b03
AS		 1374 {
1375 .vendor = PCI_VENDOR_ID_INTEL,
1376 .device = PCI_DEVICE_ID_INTEL_PCH_SDIO0,
1377 .subvendor = PCI_ANY_ID,
1378 .subdevice = PCI_ANY_ID,
1379 .driver_data = (kernel_ulong_t)&sdhci_intel_pch_sdio,
1380 },
1381
1382 {
1383 .vendor = PCI_VENDOR_ID_INTEL,
1384 .device = PCI_DEVICE_ID_INTEL_PCH_SDIO1,
1385 .subvendor = PCI_ANY_ID,
1386 .subdevice = PCI_ANY_ID,
1387 .driver_data = (kernel_ulong_t)&sdhci_intel_pch_sdio,
1388 },
1389
728ef3d1
AH		 1390 {
1391 .vendor = PCI_VENDOR_ID_INTEL,
1392 .device = PCI_DEVICE_ID_INTEL_BYT_EMMC,
1393 .subvendor = PCI_ANY_ID,
1394 .subdevice = PCI_ANY_ID,
1395 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc,
1396 },
1397
42b06496
ZB		 1398 {
1399 .vendor = PCI_VENDOR_ID_INTEL,
1400 .device = PCI_DEVICE_ID_INTEL_BYT_SDIO,
1401 .subvendor = PCI_VENDOR_ID_NI,
1402 .subdevice = 0x7884,
1403 .driver_data = (kernel_ulong_t)&sdhci_ni_byt_sdio,
1404 },
1405
728ef3d1
AH		 1406 {
1407 .vendor = PCI_VENDOR_ID_INTEL,
1408 .device = PCI_DEVICE_ID_INTEL_BYT_SDIO,
1409 .subvendor = PCI_ANY_ID,
1410 .subdevice = PCI_ANY_ID,
1411 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio,
1412 },
1413
1414 {
1415 .vendor = PCI_VENDOR_ID_INTEL,
1416 .device = PCI_DEVICE_ID_INTEL_BYT_SD,
1417 .subvendor = PCI_ANY_ID,
1418 .subdevice = PCI_ANY_ID,
1419 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd,
1420 },
1421
30d025c0
AH		 1422 {
1423 .vendor = PCI_VENDOR_ID_INTEL,
1424 .device = PCI_DEVICE_ID_INTEL_BYT_EMMC2,
1425 .subvendor = PCI_ANY_ID,
1426 .subdevice = PCI_ANY_ID,
1427 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc,
1428 },
1429
066173b6
AC		 1430 {
1431 .vendor = PCI_VENDOR_ID_INTEL,
1432 .device = PCI_DEVICE_ID_INTEL_BSW_EMMC,
1433 .subvendor = PCI_ANY_ID,
1434 .subdevice = PCI_ANY_ID,
1435 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc,
1436 },
1437
1438 {
1439 .vendor = PCI_VENDOR_ID_INTEL,
1440 .device = PCI_DEVICE_ID_INTEL_BSW_SDIO,
1441 .subvendor = PCI_ANY_ID,
1442 .subdevice = PCI_ANY_ID,
1443 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio,
1444 },
1445
1446 {
1447 .vendor = PCI_VENDOR_ID_INTEL,
1448 .device = PCI_DEVICE_ID_INTEL_BSW_SD,
1449 .subvendor = PCI_ANY_ID,
1450 .subdevice = PCI_ANY_ID,
1451 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd,
1452 },
d052068a
EE		 1453
1454 {
1455 .vendor = PCI_VENDOR_ID_INTEL,
1456 .device = PCI_DEVICE_ID_INTEL_CLV_SDIO0,
1457 .subvendor = PCI_ANY_ID,
1458 .subdevice = PCI_ANY_ID,
1459 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sd,
1460 },
1461
1462 {
1463 .vendor = PCI_VENDOR_ID_INTEL,
1464 .device = PCI_DEVICE_ID_INTEL_CLV_SDIO1,
1465 .subvendor = PCI_ANY_ID,
1466 .subdevice = PCI_ANY_ID,
1467 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sdio,
1468 },
1469
1470 {
1471 .vendor = PCI_VENDOR_ID_INTEL,
1472 .device = PCI_DEVICE_ID_INTEL_CLV_SDIO2,
1473 .subvendor = PCI_ANY_ID,
1474 .subdevice = PCI_ANY_ID,
1475 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sdio,
1476 },
1477
1478 {
1479 .vendor = PCI_VENDOR_ID_INTEL,
1480 .device = PCI_DEVICE_ID_INTEL_CLV_EMMC0,
1481 .subvendor = PCI_ANY_ID,
1482 .subdevice = PCI_ANY_ID,
1483 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc,
1484 },
1485
1486 {
1487 .vendor = PCI_VENDOR_ID_INTEL,
1488 .device = PCI_DEVICE_ID_INTEL_CLV_EMMC1,
1489 .subvendor = PCI_ANY_ID,
1490 .subdevice = PCI_ANY_ID,
1491 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc,
1492 },
1493
8776a165
DC		 1494 {
1495 .vendor = PCI_VENDOR_ID_INTEL,
1f64cec2 1496 .device = PCI_DEVICE_ID_INTEL_MRFLD_MMC,
8776a165
DC		 1497 .subvendor = PCI_ANY_ID,
1498 .subdevice = PCI_ANY_ID,
1f64cec2 1499 .driver_data = (kernel_ulong_t)&sdhci_intel_mrfld_mmc,
8776a165 1500 },
1f7f2652
AH		 1501
1502 {
1503 .vendor = PCI_VENDOR_ID_INTEL,
1504 .device = PCI_DEVICE_ID_INTEL_SPT_EMMC,
1505 .subvendor = PCI_ANY_ID,
1506 .subdevice = PCI_ANY_ID,
1507 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc,
1508 },
1509
1510 {
1511 .vendor = PCI_VENDOR_ID_INTEL,
1512 .device = PCI_DEVICE_ID_INTEL_SPT_SDIO,
1513 .subvendor = PCI_ANY_ID,
1514 .subdevice = PCI_ANY_ID,
1515 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio,
1516 },
1517
1518 {
1519 .vendor = PCI_VENDOR_ID_INTEL,
1520 .device = PCI_DEVICE_ID_INTEL_SPT_SD,
1521 .subvendor = PCI_ANY_ID,
1522 .subdevice = PCI_ANY_ID,
1523 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd,
1524 },
1525
06bf9c56
AH		 1526 {
1527 .vendor = PCI_VENDOR_ID_INTEL,
1528 .device = PCI_DEVICE_ID_INTEL_DNV_EMMC,
1529 .subvendor = PCI_ANY_ID,
1530 .subdevice = PCI_ANY_ID,
1531 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc,
1532 },
1533
4fd4c065
AH		 1534 {
1535 .vendor = PCI_VENDOR_ID_INTEL,
1536 .device = PCI_DEVICE_ID_INTEL_BXT_EMMC,
1537 .subvendor = PCI_ANY_ID,
1538 .subdevice = PCI_ANY_ID,
1539 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc,
1540 },
1541
1542 {
1543 .vendor = PCI_VENDOR_ID_INTEL,
1544 .device = PCI_DEVICE_ID_INTEL_BXT_SDIO,
1545 .subvendor = PCI_ANY_ID,
1546 .subdevice = PCI_ANY_ID,
1547 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio,
1548 },
1549
1550 {
1551 .vendor = PCI_VENDOR_ID_INTEL,
1552 .device = PCI_DEVICE_ID_INTEL_BXT_SD,
1553 .subvendor = PCI_ANY_ID,
1554 .subdevice = PCI_ANY_ID,
1555 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd,
1556 },
1557
01d6b2a4
AH		 1558 {
1559 .vendor = PCI_VENDOR_ID_INTEL,
1560 .device = PCI_DEVICE_ID_INTEL_BXTM_EMMC,
1561 .subvendor = PCI_ANY_ID,
1562 .subdevice = PCI_ANY_ID,
1563 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc,
1564 },
1565
1566 {
1567 .vendor = PCI_VENDOR_ID_INTEL,
1568 .device = PCI_DEVICE_ID_INTEL_BXTM_SDIO,
1569 .subvendor = PCI_ANY_ID,
1570 .subdevice = PCI_ANY_ID,
1571 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio,
1572 },
1573
1574 {
1575 .vendor = PCI_VENDOR_ID_INTEL,
1576 .device = PCI_DEVICE_ID_INTEL_BXTM_SD,
1577 .subvendor = PCI_ANY_ID,
1578 .subdevice = PCI_ANY_ID,
1579 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd,
1580 },
1581
4fd4c065
AH		 1582 {
1583 .vendor = PCI_VENDOR_ID_INTEL,
1584 .device = PCI_DEVICE_ID_INTEL_APL_EMMC,
1585 .subvendor = PCI_ANY_ID,
1586 .subdevice = PCI_ANY_ID,
1587 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc,
1588 },
1589
1590 {
1591 .vendor = PCI_VENDOR_ID_INTEL,
1592 .device = PCI_DEVICE_ID_INTEL_APL_SDIO,
1593 .subvendor = PCI_ANY_ID,
1594 .subdevice = PCI_ANY_ID,
1595 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio,
1596 },
1597
1598 {
1599 .vendor = PCI_VENDOR_ID_INTEL,
1600 .device = PCI_DEVICE_ID_INTEL_APL_SD,
1601 .subvendor = PCI_ANY_ID,
1602 .subdevice = PCI_ANY_ID,
1603 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd,
2d1956d0
AH		 1604 },
1605
1606 {
1607 .vendor = PCI_VENDOR_ID_INTEL,
1608 .device = PCI_DEVICE_ID_INTEL_GLK_EMMC,
1609 .subvendor = PCI_ANY_ID,
1610 .subdevice = PCI_ANY_ID,
1611 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc,
1612 },
1613
1614 {
1615 .vendor = PCI_VENDOR_ID_INTEL,
1616 .device = PCI_DEVICE_ID_INTEL_GLK_SDIO,
1617 .subvendor = PCI_ANY_ID,
1618 .subdevice = PCI_ANY_ID,
1619 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio,
1620 },
1621
1622 {
1623 .vendor = PCI_VENDOR_ID_INTEL,
1624 .device = PCI_DEVICE_ID_INTEL_GLK_SD,
1625 .subvendor = PCI_ANY_ID,
1626 .subdevice = PCI_ANY_ID,
1627 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd,
4fd4c065
AH		 1628 },
1629
26daa1ed
JL		 1630 {
1631 .vendor = PCI_VENDOR_ID_O2,
1632 .device = PCI_DEVICE_ID_O2_8120,
1633 .subvendor = PCI_ANY_ID,
1634 .subdevice = PCI_ANY_ID,
1635 .driver_data = (kernel_ulong_t)&sdhci_o2,
1636 },
1637
1638 {
1639 .vendor = PCI_VENDOR_ID_O2,
1640 .device = PCI_DEVICE_ID_O2_8220,
1641 .subvendor = PCI_ANY_ID,
1642 .subdevice = PCI_ANY_ID,
1643 .driver_data = (kernel_ulong_t)&sdhci_o2,
1644 },
1645
1646 {
1647 .vendor = PCI_VENDOR_ID_O2,
1648 .device = PCI_DEVICE_ID_O2_8221,
1649 .subvendor = PCI_ANY_ID,
1650 .subdevice = PCI_ANY_ID,
1651 .driver_data = (kernel_ulong_t)&sdhci_o2,
1652 },
1653
1654 {
1655 .vendor = PCI_VENDOR_ID_O2,
1656 .device = PCI_DEVICE_ID_O2_8320,
1657 .subvendor = PCI_ANY_ID,
1658 .subdevice = PCI_ANY_ID,
1659 .driver_data = (kernel_ulong_t)&sdhci_o2,
1660 },
1661
1662 {
1663 .vendor = PCI_VENDOR_ID_O2,
1664 .device = PCI_DEVICE_ID_O2_8321,
1665 .subvendor = PCI_ANY_ID,
1666 .subdevice = PCI_ANY_ID,
1667 .driver_data = (kernel_ulong_t)&sdhci_o2,
1668 },
1669
01acf691
AL		 1670 {
1671 .vendor = PCI_VENDOR_ID_O2,
1672 .device = PCI_DEVICE_ID_O2_FUJIN2,
1673 .subvendor = PCI_ANY_ID,
1674 .subdevice = PCI_ANY_ID,
1675 .driver_data = (kernel_ulong_t)&sdhci_o2,
1676 },
1677
1678 {
1679 .vendor = PCI_VENDOR_ID_O2,
1680 .device = PCI_DEVICE_ID_O2_SDS0,
1681 .subvendor = PCI_ANY_ID,
1682 .subdevice = PCI_ANY_ID,
1683 .driver_data = (kernel_ulong_t)&sdhci_o2,
1684 },
1685
1686 {
1687 .vendor = PCI_VENDOR_ID_O2,
1688 .device = PCI_DEVICE_ID_O2_SDS1,
1689 .subvendor = PCI_ANY_ID,
1690 .subdevice = PCI_ANY_ID,
1691 .driver_data = (kernel_ulong_t)&sdhci_o2,
1692 },
1693
1694 {
1695 .vendor = PCI_VENDOR_ID_O2,
1696 .device = PCI_DEVICE_ID_O2_SEABIRD0,
1697 .subvendor = PCI_ANY_ID,
1698 .subdevice = PCI_ANY_ID,
1699 .driver_data = (kernel_ulong_t)&sdhci_o2,
1700 },
1701
1702 {
1703 .vendor = PCI_VENDOR_ID_O2,
1704 .device = PCI_DEVICE_ID_O2_SEABIRD1,
1705 .subvendor = PCI_ANY_ID,
1706 .subdevice = PCI_ANY_ID,
1707 .driver_data = (kernel_ulong_t)&sdhci_o2,
1708 },
d44f88da
VW		 1709 {
1710 .vendor = PCI_VENDOR_ID_AMD,
1711 .device = PCI_ANY_ID,
1712 .class = PCI_CLASS_SYSTEM_SDHCI << 8,
1713 .class_mask = 0xFFFF00,
1714 .subvendor = PCI_ANY_ID,
1715 .subdevice = PCI_ANY_ID,
1716 .driver_data = (kernel_ulong_t)&sdhci_amd,
1717 },
b8c86fc5
PO		 1718 { /* Generic SD host controller */
1719 PCI_DEVICE_CLASS((PCI_CLASS_SYSTEM_SDHCI << 8), 0xFFFF00)
1720 },
1721
1722 { /* end: all zeroes */ },
1723};
1724
1725MODULE_DEVICE_TABLE(pci, pci_ids);
1726
b8c86fc5
PO		 1727/*****************************************************************************\
1728 * *
1729 * SDHCI core callbacks *
1730 * *
1731\*****************************************************************************/
1732
1733static int sdhci_pci_enable_dma(struct sdhci_host *host)
1734{
1735 struct sdhci_pci_slot *slot;
1736 struct pci_dev *pdev;
b8c86fc5
PO		 1737
1738 slot = sdhci_priv(host);
1739 pdev = slot->chip->pdev;
1740
1741 if (((pdev->class & 0xFFFF00) == (PCI_CLASS_SYSTEM_SDHCI << 8)) &&
1742 ((pdev->class & 0x0000FF) != PCI_SDHCI_IFDMA) &&
a13abc7b 1743 (host->flags & SDHCI_USE_SDMA)) {
b8c86fc5
PO		 1744 dev_warn(&pdev->dev, "Will use DMA mode even though HW "
1745 "doesn't fully claim to support it.\n");
1746 }
1747
b8c86fc5
PO		 1748 pci_set_master(pdev);
1749
1750 return 0;
1751}
1752
2317f56c 1753static void sdhci_pci_set_bus_width(struct sdhci_host *host, int width)
68077b02
ML		 1754{
1755 u8 ctrl;
1756
1757 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1758
1759 switch (width) {
1760 case MMC_BUS_WIDTH_8:
1761 ctrl |= SDHCI_CTRL_8BITBUS;
1762 ctrl &= ~SDHCI_CTRL_4BITBUS;
1763 break;
1764 case MMC_BUS_WIDTH_4:
1765 ctrl |= SDHCI_CTRL_4BITBUS;
1766 ctrl &= ~SDHCI_CTRL_8BITBUS;
1767 break;
1768 default:
1769 ctrl &= ~(SDHCI_CTRL_8BITBUS | SDHCI_CTRL_4BITBUS);
1770 break;
1771 }
1772
1773 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
68077b02
ML		 1774}
1775
c9faff6c 1776static void sdhci_pci_gpio_hw_reset(struct sdhci_host *host)
0f201655
AH		 1777{
1778 struct sdhci_pci_slot *slot = sdhci_priv(host);
1779 int rst_n_gpio = slot->rst_n_gpio;
1780
1781 if (!gpio_is_valid(rst_n_gpio))
1782 return;
1783 gpio_set_value_cansleep(rst_n_gpio, 0);
1784 /* For eMMC, minimum is 1us but give it 10us for good measure */
1785 udelay(10);
1786 gpio_set_value_cansleep(rst_n_gpio, 1);
1787 /* For eMMC, minimum is 200us but give it 300us for good measure */
1788 usleep_range(300, 1000);
1789}
1790
c9faff6c
AH		 1791static void sdhci_pci_hw_reset(struct sdhci_host *host)
1792{
1793 struct sdhci_pci_slot *slot = sdhci_priv(host);
1794
1795 if (slot->hw_reset)
1796 slot->hw_reset(host);
1797}
1798
c915568d 1799static const struct sdhci_ops sdhci_pci_ops = {
1771059c 1800 .set_clock = sdhci_set_clock,
b8c86fc5 1801 .enable_dma = sdhci_pci_enable_dma,
2317f56c 1802 .set_bus_width = sdhci_pci_set_bus_width,
03231f9b 1803 .reset = sdhci_reset,
96d7b78c 1804 .set_uhs_signaling = sdhci_set_uhs_signaling,
0f201655 1805 .hw_reset = sdhci_pci_hw_reset,
b8c86fc5
PO		 1806};
1807
1808/*****************************************************************************\
1809 * *
1810 * Suspend/resume *
1811 * *
1812\*****************************************************************************/
1813
f9900f15 1814#ifdef CONFIG_PM_SLEEP
29495aa0 1815static int sdhci_pci_suspend(struct device *dev)
b8c86fc5 1816{
29495aa0 1817 struct pci_dev *pdev = to_pci_dev(dev);
30cf2803 1818 struct sdhci_pci_chip *chip = pci_get_drvdata(pdev);
b8c86fc5 1819
b8c86fc5
PO		 1820 if (!chip)
1821 return 0;
1822
30cf2803
AH		 1823 if (chip->fixes && chip->fixes->suspend)
1824 return chip->fixes->suspend(chip);
b8c86fc5 1825
30cf2803 1826 return sdhci_pci_suspend_host(chip);
b8c86fc5
PO		 1827}
1828
29495aa0 1829static int sdhci_pci_resume(struct device *dev)
b8c86fc5 1830{
29495aa0 1831 struct pci_dev *pdev = to_pci_dev(dev);
30cf2803 1832 struct sdhci_pci_chip *chip = pci_get_drvdata(pdev);
b8c86fc5 1833
b8c86fc5
PO		 1834 if (!chip)
1835 return 0;
1836
30cf2803
AH		 1837 if (chip->fixes && chip->fixes->resume)
1838 return chip->fixes->resume(chip);
b8c86fc5 1839
30cf2803 1840 return sdhci_pci_resume_host(chip);
b8c86fc5 1841}
f9900f15 1842#endif
b8c86fc5 1843
f9900f15 1844#ifdef CONFIG_PM
66fd8ad5
AH		 1845static int sdhci_pci_runtime_suspend(struct device *dev)
1846{
923a231c 1847 struct pci_dev *pdev = to_pci_dev(dev);
966d696a 1848 struct sdhci_pci_chip *chip = pci_get_drvdata(pdev);
66fd8ad5 1849
66fd8ad5
AH		 1850 if (!chip)
1851 return 0;
1852
966d696a
AH		 1853 if (chip->fixes && chip->fixes->runtime_suspend)
1854 return chip->fixes->runtime_suspend(chip);
66fd8ad5 1855
966d696a 1856 return sdhci_pci_runtime_suspend_host(chip);
66fd8ad5
AH		 1857}
1858
1859static int sdhci_pci_runtime_resume(struct device *dev)
1860{
923a231c 1861 struct pci_dev *pdev = to_pci_dev(dev);
966d696a 1862 struct sdhci_pci_chip *chip = pci_get_drvdata(pdev);
66fd8ad5 1863
66fd8ad5
AH		 1864 if (!chip)
1865 return 0;
1866
966d696a
AH		 1867 if (chip->fixes && chip->fixes->runtime_resume)
1868 return chip->fixes->runtime_resume(chip);
66fd8ad5 1869
966d696a 1870 return sdhci_pci_runtime_resume_host(chip);
66fd8ad5 1871}
f9900f15 1872#endif
66fd8ad5
AH		 1873
1874static const struct dev_pm_ops sdhci_pci_pm_ops = {
f9900f15 1875 SET_SYSTEM_SLEEP_PM_OPS(sdhci_pci_suspend, sdhci_pci_resume)
f3a92b1a 1876 SET_RUNTIME_PM_OPS(sdhci_pci_runtime_suspend,
106276bb 1877 sdhci_pci_runtime_resume, NULL)
66fd8ad5
AH		 1878};
1879
b8c86fc5
PO		 1880/*****************************************************************************\
1881 * *
1882 * Device probing/removal *
1883 * *
1884\*****************************************************************************/
1885
c3be1efd 1886static struct sdhci_pci_slot *sdhci_pci_probe_slot(
52c506f0
AH		 1887 struct pci_dev *pdev, struct sdhci_pci_chip *chip, int first_bar,
1888 int slotno)
b8c86fc5
PO		 1889{
1890 struct sdhci_pci_slot *slot;
1891 struct sdhci_host *host;
52c506f0 1892 int ret, bar = first_bar + slotno;
ac9f67b5 1893 size_t priv_size = chip->fixes ? chip->fixes->priv_size : 0;
b8c86fc5
PO		 1894
1895 if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) {
1896 dev_err(&pdev->dev, "BAR %d is not iomem. Aborting.\n", bar);
1897 return ERR_PTR(-ENODEV);
1898 }
1899
90b3e6c5 1900 if (pci_resource_len(pdev, bar) < 0x100) {
b8c86fc5
PO		 1901 dev_err(&pdev->dev, "Invalid iomem size. You may "
1902 "experience problems.\n");
1903 }
1904
1905 if ((pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) {
1906 dev_err(&pdev->dev, "Vendor specific interface. Aborting.\n");
1907 return ERR_PTR(-ENODEV);
1908 }
1909
1910 if ((pdev->class & 0x0000FF) > PCI_SDHCI_IFVENDOR) {
1911 dev_err(&pdev->dev, "Unknown interface. Aborting.\n");
1912 return ERR_PTR(-ENODEV);
1913 }
1914
ac9f67b5 1915 host = sdhci_alloc_host(&pdev->dev, sizeof(*slot) + priv_size);
b8c86fc5 1916 if (IS_ERR(host)) {
c60a32cd 1917 dev_err(&pdev->dev, "cannot allocate host\n");
dc0fd7b5 1918 return ERR_CAST(host);
b8c86fc5
PO		 1919 }
1920
1921 slot = sdhci_priv(host);
1922
1923 slot->chip = chip;
1924 slot->host = host;
0f201655 1925 slot->rst_n_gpio = -EINVAL;
c5e027a4 1926 slot->cd_gpio = -EINVAL;
ff59c520 1927 slot->cd_idx = -1;
b8c86fc5 1928
52c506f0
AH		 1929 /* Retrieve platform data if there is any */
1930 if (*sdhci_pci_get_data)
1931 slot->data = sdhci_pci_get_data(pdev, slotno);
1932
1933 if (slot->data) {
1934 if (slot->data->setup) {
1935 ret = slot->data->setup(slot->data);
1936 if (ret) {
1937 dev_err(&pdev->dev, "platform setup failed\n");
1938 goto free;
1939 }
1940 }
c5e027a4
AH		 1941 slot->rst_n_gpio = slot->data->rst_n_gpio;
1942 slot->cd_gpio = slot->data->cd_gpio;
52c506f0
AH		 1943 }
1944
b8c86fc5 1945 host->hw_name = "PCI";
6bc09063
AH		 1946 host->ops = chip->fixes && chip->fixes->ops ?
1947 chip->fixes->ops :
1948 &sdhci_pci_ops;
b8c86fc5 1949 host->quirks = chip->quirks;
f3c55a7b 1950 host->quirks2 = chip->quirks2;
b8c86fc5
PO		 1951
1952 host->irq = pdev->irq;
1953
c10bc372 1954 ret = pcim_iomap_regions(pdev, BIT(bar), mmc_hostname(host->mmc));
b8c86fc5
PO		 1955 if (ret) {
1956 dev_err(&pdev->dev, "cannot request region\n");
52c506f0 1957 goto cleanup;
b8c86fc5
PO		 1958 }
1959
c10bc372 1960 host->ioaddr = pcim_iomap_table(pdev)[bar];
b8c86fc5 1961
4489428a
PO		 1962 if (chip->fixes && chip->fixes->probe_slot) {
1963 ret = chip->fixes->probe_slot(slot);
1964 if (ret)
c10bc372 1965 goto cleanup;
4489428a
PO		 1966 }
1967
c5e027a4 1968 if (gpio_is_valid(slot->rst_n_gpio)) {
c10bc372 1969 if (!devm_gpio_request(&pdev->dev, slot->rst_n_gpio, "eMMC_reset")) {
c5e027a4
AH		 1970 gpio_direction_output(slot->rst_n_gpio, 1);
1971 slot->host->mmc->caps |= MMC_CAP_HW_RESET;
c9faff6c 1972 slot->hw_reset = sdhci_pci_gpio_hw_reset;
c5e027a4
AH		 1973 } else {
1974 dev_warn(&pdev->dev, "failed to request rst_n_gpio\n");
1975 slot->rst_n_gpio = -EINVAL;
1976 }
1977 }
1978
2f4cbb3d 1979 host->mmc->pm_caps = MMC_PM_KEEP_POWER | MMC_PM_WAKE_SDIO_IRQ;
eed222ac 1980 host->mmc->slotno = slotno;
a08b17be 1981 host->mmc->caps2 |= MMC_CAP2_NO_PRESCAN_POWERUP;
2f4cbb3d 1982
8f743d03 1983 if (slot->cd_idx >= 0) {
6ac9b837 1984 ret = mmc_gpiod_request_cd(host->mmc, NULL, slot->cd_idx,
8f743d03
DB		 1985 slot->cd_override_level, 0, NULL);
1986 if (ret == -EPROBE_DEFER)
1987 goto remove;
1988
1989 if (ret) {
1990 dev_warn(&pdev->dev, "failed to setup card detect gpio\n");
1991 slot->cd_idx = -1;
1992 }
ff59c520
AH		 1993 }
1994
61c951de
AH		 1995 if (chip->fixes && chip->fixes->add_host)
1996 ret = chip->fixes->add_host(slot);
1997 else
1998 ret = sdhci_add_host(host);
b8c86fc5 1999 if (ret)
4489428a 2000 goto remove;
b8c86fc5 2001
c5e027a4
AH		 2002 sdhci_pci_add_own_cd(slot);
2003
77a0122e
AH		 2004 /*
2005 * Check if the chip needs a separate GPIO for card detect to wake up
2006 * from runtime suspend. If it is not there, don't allow runtime PM.
2007 * Note sdhci_pci_add_own_cd() sets slot->cd_gpio to -EINVAL on failure.
2008 */
945be38c 2009 if (chip->fixes && chip->fixes->own_cd_for_runtime_pm &&
ff59c520 2010 !gpio_is_valid(slot->cd_gpio) && slot->cd_idx < 0)
77a0122e
AH		 2011 chip->allow_runtime_pm = false;
2012
b8c86fc5
PO		 2013 return slot;
2014
4489428a
PO		 2015remove:
2016 if (chip->fixes && chip->fixes->remove_slot)
1e72859e 2017 chip->fixes->remove_slot(slot, 0);
4489428a 2018
52c506f0
AH		 2019cleanup:
2020 if (slot->data && slot->data->cleanup)
2021 slot->data->cleanup(slot->data);
2022
c60a32cd 2023free:
b8c86fc5
PO		 2024 sdhci_free_host(host);
2025
2026 return ERR_PTR(ret);
2027}
2028
2029static void sdhci_pci_remove_slot(struct sdhci_pci_slot *slot)
2030{
1e72859e
PO		 2031 int dead;
2032 u32 scratch;
2033
c5e027a4
AH		 2034 sdhci_pci_remove_own_cd(slot);
2035
1e72859e
PO		 2036 dead = 0;
2037 scratch = readl(slot->host->ioaddr + SDHCI_INT_STATUS);
2038 if (scratch == (u32)-1)
2039 dead = 1;
2040
2041 sdhci_remove_host(slot->host, dead);
4489428a
PO		 2042
2043 if (slot->chip->fixes && slot->chip->fixes->remove_slot)
1e72859e 2044 slot->chip->fixes->remove_slot(slot, dead);
4489428a 2045
52c506f0
AH		 2046 if (slot->data && slot->data->cleanup)
2047 slot->data->cleanup(slot->data);
2048
b8c86fc5
PO		 2049 sdhci_free_host(slot->host);
2050}
2051
c3be1efd 2052static void sdhci_pci_runtime_pm_allow(struct device *dev)
66fd8ad5 2053{
00884b61 2054 pm_suspend_ignore_children(dev, 1);
66fd8ad5
AH		 2055 pm_runtime_set_autosuspend_delay(dev, 50);
2056 pm_runtime_use_autosuspend(dev);
00884b61
AH		 2057 pm_runtime_allow(dev);
2058 /* Stay active until mmc core scans for a card */
2059 pm_runtime_put_noidle(dev);
66fd8ad5
AH		 2060}
2061
6e0ee714 2062static void sdhci_pci_runtime_pm_forbid(struct device *dev)
66fd8ad5
AH		 2063{
2064 pm_runtime_forbid(dev);
2065 pm_runtime_get_noresume(dev);
2066}
2067
c3be1efd 2068static int sdhci_pci_probe(struct pci_dev *pdev,
b8c86fc5
PO		 2069 const struct pci_device_id *ent)
2070{
2071 struct sdhci_pci_chip *chip;
2072 struct sdhci_pci_slot *slot;
2073
cf5e23e1 2074 u8 slots, first_bar;
b8c86fc5
PO		 2075 int ret, i;
2076
2077 BUG_ON(pdev == NULL);
2078 BUG_ON(ent == NULL);
2079
b8c86fc5 2080 dev_info(&pdev->dev, "SDHCI controller found [%04x:%04x] (rev %x)\n",
cf5e23e1 2081 (int)pdev->vendor, (int)pdev->device, (int)pdev->revision);
b8c86fc5
PO		 2082
2083 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &slots);
2084 if (ret)
2085 return ret;
2086
2087 slots = PCI_SLOT_INFO_SLOTS(slots) + 1;
2088 dev_dbg(&pdev->dev, "found %d slot(s)\n", slots);
2089 if (slots == 0)
2090 return -ENODEV;
2091
2092 BUG_ON(slots > MAX_SLOTS);
2093
2094 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &first_bar);
2095 if (ret)
2096 return ret;
2097
2098 first_bar &= PCI_SLOT_INFO_FIRST_BAR_MASK;
2099
2100 if (first_bar > 5) {
2101 dev_err(&pdev->dev, "Invalid first BAR. Aborting.\n");
2102 return -ENODEV;
2103 }
2104
52ac7acf 2105 ret = pcim_enable_device(pdev);
b8c86fc5
PO		 2106 if (ret)
2107 return ret;
2108
52ac7acf
AS		 2109 chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL);
2110 if (!chip)
2111 return -ENOMEM;
b8c86fc5
PO		 2112
2113 chip->pdev = pdev;
b177bc91 2114 chip->fixes = (const struct sdhci_pci_fixes *)ent->driver_data;
c43fd774 2115 if (chip->fixes) {
22606405 2116 chip->quirks = chip->fixes->quirks;
f3c55a7b 2117 chip->quirks2 = chip->fixes->quirks2;
c43fd774
AH		 2118 chip->allow_runtime_pm = chip->fixes->allow_runtime_pm;
2119 }
b8c86fc5 2120 chip->num_slots = slots;
d38dcad4
AH		 2121 chip->pm_retune = true;
2122 chip->rpm_retune = true;
b8c86fc5
PO		 2123
2124 pci_set_drvdata(pdev, chip);
2125
22606405
PO		 2126 if (chip->fixes && chip->fixes->probe) {
2127 ret = chip->fixes->probe(chip);
2128 if (ret)
52ac7acf 2129 return ret;
22606405
PO		 2130 }
2131
225d85fe
AC		 2132 slots = chip->num_slots; /* Quirk may have changed this */
2133
b177bc91 2134 for (i = 0; i < slots; i++) {
52c506f0 2135 slot = sdhci_pci_probe_slot(pdev, chip, first_bar, i);
b8c86fc5 2136 if (IS_ERR(slot)) {
b177bc91 2137 for (i--; i >= 0; i--)
b8c86fc5 2138 sdhci_pci_remove_slot(chip->slots[i]);
52ac7acf 2139 return PTR_ERR(slot);
b8c86fc5
PO		 2140 }
2141
2142 chip->slots[i] = slot;
2143 }
2144
c43fd774
AH		 2145 if (chip->allow_runtime_pm)
2146 sdhci_pci_runtime_pm_allow(&pdev->dev);
66fd8ad5 2147
b8c86fc5 2148 return 0;
b8c86fc5
PO		 2149}
2150
6e0ee714 2151static void sdhci_pci_remove(struct pci_dev *pdev)
b8c86fc5
PO		 2152{
2153 int i;
52ac7acf 2154 struct sdhci_pci_chip *chip = pci_get_drvdata(pdev);
c43fd774 2155
52ac7acf
AS		 2156 if (chip->allow_runtime_pm)
2157 sdhci_pci_runtime_pm_forbid(&pdev->dev);
b8c86fc5 2158
52ac7acf
AS		 2159 for (i = 0; i < chip->num_slots; i++)
2160 sdhci_pci_remove_slot(chip->slots[i]);
b8c86fc5
PO		 2161}
2162
2163static struct pci_driver sdhci_driver = {
b177bc91 2164 .name = "sdhci-pci",
b8c86fc5 2165 .id_table = pci_ids,
b177bc91 2166 .probe = sdhci_pci_probe,
0433c143 2167 .remove = sdhci_pci_remove,
66fd8ad5
AH		 2168 .driver = {
2169 .pm = &sdhci_pci_pm_ops
2170 },
b8c86fc5
PO		 2171};
2172
acc69646 2173module_pci_driver(sdhci_driver);
b8c86fc5 2174
32710e8f 2175MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
b8c86fc5
PO		 2176MODULE_DESCRIPTION("Secure Digital Host Controller Interface PCI driver");
2177MODULE_LICENSE("GPL");
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