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b8c86fc5 PO |
1 | /* linux/drivers/mmc/host/sdhci-pci.c - SDHCI on PCI bus interface |
2 | * | |
3 | * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved. | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License as published by | |
7 | * the Free Software Foundation; either version 2 of the License, or (at | |
8 | * your option) any later version. | |
9 | * | |
10 | * Thanks to the following companies for their support: | |
11 | * | |
12 | * - JMicron (hardware and technical support) | |
13 | */ | |
14 | ||
a72016a4 | 15 | #include <linux/string.h> |
b8c86fc5 PO |
16 | #include <linux/delay.h> |
17 | #include <linux/highmem.h> | |
88b47679 | 18 | #include <linux/module.h> |
b8c86fc5 PO |
19 | #include <linux/pci.h> |
20 | #include <linux/dma-mapping.h> | |
5a0e3ad6 | 21 | #include <linux/slab.h> |
ccc92c23 | 22 | #include <linux/device.h> |
b8c86fc5 | 23 | #include <linux/mmc/host.h> |
e1bfad6d | 24 | #include <linux/mmc/mmc.h> |
b177bc91 AP |
25 | #include <linux/scatterlist.h> |
26 | #include <linux/io.h> | |
0f201655 | 27 | #include <linux/gpio.h> |
66fd8ad5 | 28 | #include <linux/pm_runtime.h> |
ff59c520 | 29 | #include <linux/mmc/slot-gpio.h> |
52c506f0 | 30 | #include <linux/mmc/sdhci-pci-data.h> |
3f23df72 | 31 | #include <linux/acpi.h> |
b8c86fc5 | 32 | |
8ee82bda AH |
33 | #include "cqhci.h" |
34 | ||
b8c86fc5 | 35 | #include "sdhci.h" |
522624f9 | 36 | #include "sdhci-pci.h" |
22606405 | 37 | |
fee686b7 | 38 | static void sdhci_pci_hw_reset(struct sdhci_host *host); |
fee686b7 | 39 | |
30cf2803 | 40 | #ifdef CONFIG_PM_SLEEP |
5c3c6126 AH |
41 | static int sdhci_pci_init_wakeup(struct sdhci_pci_chip *chip) |
42 | { | |
43 | mmc_pm_flag_t pm_flags = 0; | |
d56ee1ff | 44 | bool cap_cd_wake = false; |
5c3c6126 AH |
45 | int i; |
46 | ||
47 | for (i = 0; i < chip->num_slots; i++) { | |
48 | struct sdhci_pci_slot *slot = chip->slots[i]; | |
49 | ||
d56ee1ff | 50 | if (slot) { |
5c3c6126 | 51 | pm_flags |= slot->host->mmc->pm_flags; |
d56ee1ff AH |
52 | if (slot->host->mmc->caps & MMC_CAP_CD_WAKE) |
53 | cap_cd_wake = true; | |
54 | } | |
5c3c6126 AH |
55 | } |
56 | ||
d56ee1ff AH |
57 | if ((pm_flags & MMC_PM_KEEP_POWER) && (pm_flags & MMC_PM_WAKE_SDIO_IRQ)) |
58 | return device_wakeup_enable(&chip->pdev->dev); | |
59 | else if (!cap_cd_wake) | |
60 | return device_wakeup_disable(&chip->pdev->dev); | |
61 | ||
62 | return 0; | |
5c3c6126 AH |
63 | } |
64 | ||
65 | static int sdhci_pci_suspend_host(struct sdhci_pci_chip *chip) | |
30cf2803 AH |
66 | { |
67 | int i, ret; | |
68 | ||
5c3c6126 AH |
69 | sdhci_pci_init_wakeup(chip); |
70 | ||
30cf2803 AH |
71 | for (i = 0; i < chip->num_slots; i++) { |
72 | struct sdhci_pci_slot *slot = chip->slots[i]; | |
73 | struct sdhci_host *host; | |
74 | ||
75 | if (!slot) | |
76 | continue; | |
77 | ||
78 | host = slot->host; | |
79 | ||
80 | if (chip->pm_retune && host->tuning_mode != SDHCI_TUNING_MODE_3) | |
81 | mmc_retune_needed(host->mmc); | |
82 | ||
83 | ret = sdhci_suspend_host(host); | |
84 | if (ret) | |
85 | goto err_pci_suspend; | |
d56ee1ff AH |
86 | |
87 | if (device_may_wakeup(&chip->pdev->dev)) | |
88 | mmc_gpio_set_cd_wake(host->mmc, true); | |
30cf2803 AH |
89 | } |
90 | ||
91 | return 0; | |
92 | ||
93 | err_pci_suspend: | |
94 | while (--i >= 0) | |
95 | sdhci_resume_host(chip->slots[i]->host); | |
96 | return ret; | |
97 | } | |
98 | ||
30cf2803 AH |
99 | int sdhci_pci_resume_host(struct sdhci_pci_chip *chip) |
100 | { | |
101 | struct sdhci_pci_slot *slot; | |
102 | int i, ret; | |
103 | ||
104 | for (i = 0; i < chip->num_slots; i++) { | |
105 | slot = chip->slots[i]; | |
106 | if (!slot) | |
107 | continue; | |
108 | ||
109 | ret = sdhci_resume_host(slot->host); | |
110 | if (ret) | |
111 | return ret; | |
d56ee1ff AH |
112 | |
113 | mmc_gpio_set_cd_wake(slot->host->mmc, false); | |
30cf2803 AH |
114 | } |
115 | ||
116 | return 0; | |
117 | } | |
8ee82bda AH |
118 | |
119 | static int sdhci_cqhci_suspend(struct sdhci_pci_chip *chip) | |
120 | { | |
121 | int ret; | |
122 | ||
123 | ret = cqhci_suspend(chip->slots[0]->host->mmc); | |
124 | if (ret) | |
125 | return ret; | |
126 | ||
127 | return sdhci_pci_suspend_host(chip); | |
128 | } | |
129 | ||
130 | static int sdhci_cqhci_resume(struct sdhci_pci_chip *chip) | |
131 | { | |
132 | int ret; | |
133 | ||
134 | ret = sdhci_pci_resume_host(chip); | |
135 | if (ret) | |
136 | return ret; | |
137 | ||
138 | return cqhci_resume(chip->slots[0]->host->mmc); | |
139 | } | |
30cf2803 AH |
140 | #endif |
141 | ||
966d696a AH |
142 | #ifdef CONFIG_PM |
143 | static int sdhci_pci_runtime_suspend_host(struct sdhci_pci_chip *chip) | |
144 | { | |
145 | struct sdhci_pci_slot *slot; | |
146 | struct sdhci_host *host; | |
147 | int i, ret; | |
148 | ||
149 | for (i = 0; i < chip->num_slots; i++) { | |
150 | slot = chip->slots[i]; | |
151 | if (!slot) | |
152 | continue; | |
153 | ||
154 | host = slot->host; | |
155 | ||
156 | ret = sdhci_runtime_suspend_host(host); | |
157 | if (ret) | |
158 | goto err_pci_runtime_suspend; | |
159 | ||
160 | if (chip->rpm_retune && | |
161 | host->tuning_mode != SDHCI_TUNING_MODE_3) | |
162 | mmc_retune_needed(host->mmc); | |
163 | } | |
164 | ||
165 | return 0; | |
166 | ||
167 | err_pci_runtime_suspend: | |
168 | while (--i >= 0) | |
169 | sdhci_runtime_resume_host(chip->slots[i]->host); | |
170 | return ret; | |
171 | } | |
172 | ||
173 | static int sdhci_pci_runtime_resume_host(struct sdhci_pci_chip *chip) | |
174 | { | |
175 | struct sdhci_pci_slot *slot; | |
176 | int i, ret; | |
177 | ||
178 | for (i = 0; i < chip->num_slots; i++) { | |
179 | slot = chip->slots[i]; | |
180 | if (!slot) | |
181 | continue; | |
182 | ||
183 | ret = sdhci_runtime_resume_host(slot->host); | |
184 | if (ret) | |
185 | return ret; | |
186 | } | |
187 | ||
188 | return 0; | |
189 | } | |
8ee82bda AH |
190 | |
191 | static int sdhci_cqhci_runtime_suspend(struct sdhci_pci_chip *chip) | |
192 | { | |
193 | int ret; | |
194 | ||
195 | ret = cqhci_suspend(chip->slots[0]->host->mmc); | |
196 | if (ret) | |
197 | return ret; | |
198 | ||
199 | return sdhci_pci_runtime_suspend_host(chip); | |
200 | } | |
201 | ||
202 | static int sdhci_cqhci_runtime_resume(struct sdhci_pci_chip *chip) | |
203 | { | |
204 | int ret; | |
205 | ||
206 | ret = sdhci_pci_runtime_resume_host(chip); | |
207 | if (ret) | |
208 | return ret; | |
209 | ||
210 | return cqhci_resume(chip->slots[0]->host->mmc); | |
211 | } | |
966d696a AH |
212 | #endif |
213 | ||
8ee82bda AH |
214 | static u32 sdhci_cqhci_irq(struct sdhci_host *host, u32 intmask) |
215 | { | |
216 | int cmd_error = 0; | |
217 | int data_error = 0; | |
218 | ||
219 | if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error)) | |
220 | return intmask; | |
221 | ||
222 | cqhci_irq(host->mmc, intmask, cmd_error, data_error); | |
223 | ||
224 | return 0; | |
225 | } | |
226 | ||
227 | static void sdhci_pci_dumpregs(struct mmc_host *mmc) | |
228 | { | |
229 | sdhci_dumpregs(mmc_priv(mmc)); | |
230 | } | |
231 | ||
22606405 PO |
232 | /*****************************************************************************\ |
233 | * * | |
234 | * Hardware specific quirk handling * | |
235 | * * | |
236 | \*****************************************************************************/ | |
237 | ||
238 | static int ricoh_probe(struct sdhci_pci_chip *chip) | |
239 | { | |
c99436fb CB |
240 | if (chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG || |
241 | chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SONY) | |
22606405 | 242 | chip->quirks |= SDHCI_QUIRK_NO_CARD_NO_RESET; |
ccc92c23 ML |
243 | return 0; |
244 | } | |
245 | ||
246 | static int ricoh_mmc_probe_slot(struct sdhci_pci_slot *slot) | |
247 | { | |
248 | slot->host->caps = | |
249 | ((0x21 << SDHCI_TIMEOUT_CLK_SHIFT) | |
250 | & SDHCI_TIMEOUT_CLK_MASK) | | |
22606405 | 251 | |
ccc92c23 ML |
252 | ((0x21 << SDHCI_CLOCK_BASE_SHIFT) |
253 | & SDHCI_CLOCK_BASE_MASK) | | |
254 | ||
255 | SDHCI_TIMEOUT_CLK_UNIT | | |
256 | SDHCI_CAN_VDD_330 | | |
1a1f1f04 | 257 | SDHCI_CAN_DO_HISPD | |
ccc92c23 ML |
258 | SDHCI_CAN_DO_SDMA; |
259 | return 0; | |
260 | } | |
261 | ||
b7813f0f | 262 | #ifdef CONFIG_PM_SLEEP |
ccc92c23 ML |
263 | static int ricoh_mmc_resume(struct sdhci_pci_chip *chip) |
264 | { | |
265 | /* Apply a delay to allow controller to settle */ | |
266 | /* Otherwise it becomes confused if card state changed | |
267 | during suspend */ | |
268 | msleep(500); | |
30cf2803 | 269 | return sdhci_pci_resume_host(chip); |
22606405 | 270 | } |
b7813f0f | 271 | #endif |
22606405 PO |
272 | |
273 | static const struct sdhci_pci_fixes sdhci_ricoh = { | |
274 | .probe = ricoh_probe, | |
84938294 VK |
275 | .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR | |
276 | SDHCI_QUIRK_FORCE_DMA | | |
277 | SDHCI_QUIRK_CLOCK_BEFORE_RESET, | |
22606405 PO |
278 | }; |
279 | ||
ccc92c23 ML |
280 | static const struct sdhci_pci_fixes sdhci_ricoh_mmc = { |
281 | .probe_slot = ricoh_mmc_probe_slot, | |
b7813f0f | 282 | #ifdef CONFIG_PM_SLEEP |
ccc92c23 | 283 | .resume = ricoh_mmc_resume, |
b7813f0f | 284 | #endif |
ccc92c23 ML |
285 | .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR | |
286 | SDHCI_QUIRK_CLOCK_BEFORE_RESET | | |
287 | SDHCI_QUIRK_NO_CARD_NO_RESET | | |
288 | SDHCI_QUIRK_MISSING_CAPS | |
289 | }; | |
290 | ||
22606405 PO |
291 | static const struct sdhci_pci_fixes sdhci_ene_712 = { |
292 | .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE | | |
293 | SDHCI_QUIRK_BROKEN_DMA, | |
294 | }; | |
295 | ||
296 | static const struct sdhci_pci_fixes sdhci_ene_714 = { | |
297 | .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE | | |
298 | SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS | | |
299 | SDHCI_QUIRK_BROKEN_DMA, | |
300 | }; | |
301 | ||
302 | static const struct sdhci_pci_fixes sdhci_cafe = { | |
303 | .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER | | |
a0874897 | 304 | SDHCI_QUIRK_NO_BUSY_IRQ | |
55fc05b7 | 305 | SDHCI_QUIRK_BROKEN_CARD_DETECTION | |
ee53ab5d | 306 | SDHCI_QUIRK_BROKEN_TIMEOUT_VAL, |
22606405 PO |
307 | }; |
308 | ||
43e968ce DB |
309 | static const struct sdhci_pci_fixes sdhci_intel_qrk = { |
310 | .quirks = SDHCI_QUIRK_NO_HISPD_BIT, | |
311 | }; | |
312 | ||
68077b02 ML |
313 | static int mrst_hc_probe_slot(struct sdhci_pci_slot *slot) |
314 | { | |
315 | slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA; | |
316 | return 0; | |
317 | } | |
318 | ||
f9ee3eab AC |
319 | /* |
320 | * ADMA operation is disabled for Moorestown platform due to | |
321 | * hardware bugs. | |
322 | */ | |
35ac6f08 | 323 | static int mrst_hc_probe(struct sdhci_pci_chip *chip) |
f9ee3eab AC |
324 | { |
325 | /* | |
35ac6f08 JP |
326 | * slots number is fixed here for MRST as SDIO3/5 are never used and |
327 | * have hardware bugs. | |
f9ee3eab AC |
328 | */ |
329 | chip->num_slots = 1; | |
330 | return 0; | |
331 | } | |
332 | ||
296e0b03 AS |
333 | static int pch_hc_probe_slot(struct sdhci_pci_slot *slot) |
334 | { | |
335 | slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA; | |
336 | return 0; | |
337 | } | |
338 | ||
162d6f98 | 339 | #ifdef CONFIG_PM |
66fd8ad5 | 340 | |
c5e027a4 | 341 | static irqreturn_t sdhci_pci_sd_cd(int irq, void *dev_id) |
66fd8ad5 AH |
342 | { |
343 | struct sdhci_pci_slot *slot = dev_id; | |
344 | struct sdhci_host *host = slot->host; | |
345 | ||
346 | mmc_detect_change(host->mmc, msecs_to_jiffies(200)); | |
347 | return IRQ_HANDLED; | |
348 | } | |
349 | ||
c5e027a4 | 350 | static void sdhci_pci_add_own_cd(struct sdhci_pci_slot *slot) |
66fd8ad5 | 351 | { |
c5e027a4 | 352 | int err, irq, gpio = slot->cd_gpio; |
66fd8ad5 AH |
353 | |
354 | slot->cd_gpio = -EINVAL; | |
355 | slot->cd_irq = -EINVAL; | |
356 | ||
c5e027a4 AH |
357 | if (!gpio_is_valid(gpio)) |
358 | return; | |
359 | ||
c10bc372 | 360 | err = devm_gpio_request(&slot->chip->pdev->dev, gpio, "sd_cd"); |
66fd8ad5 AH |
361 | if (err < 0) |
362 | goto out; | |
363 | ||
364 | err = gpio_direction_input(gpio); | |
365 | if (err < 0) | |
366 | goto out_free; | |
367 | ||
368 | irq = gpio_to_irq(gpio); | |
369 | if (irq < 0) | |
370 | goto out_free; | |
371 | ||
c5e027a4 | 372 | err = request_irq(irq, sdhci_pci_sd_cd, IRQF_TRIGGER_RISING | |
66fd8ad5 AH |
373 | IRQF_TRIGGER_FALLING, "sd_cd", slot); |
374 | if (err) | |
375 | goto out_free; | |
376 | ||
377 | slot->cd_gpio = gpio; | |
378 | slot->cd_irq = irq; | |
66fd8ad5 | 379 | |
c5e027a4 | 380 | return; |
66fd8ad5 AH |
381 | |
382 | out_free: | |
c10bc372 | 383 | devm_gpio_free(&slot->chip->pdev->dev, gpio); |
66fd8ad5 AH |
384 | out: |
385 | dev_warn(&slot->chip->pdev->dev, "failed to setup card detect wake up\n"); | |
66fd8ad5 AH |
386 | } |
387 | ||
c5e027a4 | 388 | static void sdhci_pci_remove_own_cd(struct sdhci_pci_slot *slot) |
66fd8ad5 AH |
389 | { |
390 | if (slot->cd_irq >= 0) | |
391 | free_irq(slot->cd_irq, slot); | |
66fd8ad5 AH |
392 | } |
393 | ||
394 | #else | |
395 | ||
c5e027a4 AH |
396 | static inline void sdhci_pci_add_own_cd(struct sdhci_pci_slot *slot) |
397 | { | |
398 | } | |
399 | ||
400 | static inline void sdhci_pci_remove_own_cd(struct sdhci_pci_slot *slot) | |
401 | { | |
402 | } | |
66fd8ad5 AH |
403 | |
404 | #endif | |
405 | ||
0d013bcf AH |
406 | static int mfd_emmc_probe_slot(struct sdhci_pci_slot *slot) |
407 | { | |
66fd8ad5 | 408 | slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE; |
d2a47176 | 409 | slot->host->mmc->caps2 |= MMC_CAP2_BOOTPART_NOACC; |
0d013bcf AH |
410 | return 0; |
411 | } | |
412 | ||
93933508 AH |
413 | static int mfd_sdio_probe_slot(struct sdhci_pci_slot *slot) |
414 | { | |
012e4671 | 415 | slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE; |
93933508 AH |
416 | return 0; |
417 | } | |
418 | ||
f9ee3eab AC |
419 | static const struct sdhci_pci_fixes sdhci_intel_mrst_hc0 = { |
420 | .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT, | |
68077b02 | 421 | .probe_slot = mrst_hc_probe_slot, |
f9ee3eab AC |
422 | }; |
423 | ||
35ac6f08 | 424 | static const struct sdhci_pci_fixes sdhci_intel_mrst_hc1_hc2 = { |
f9ee3eab | 425 | .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT, |
35ac6f08 | 426 | .probe = mrst_hc_probe, |
f9ee3eab AC |
427 | }; |
428 | ||
29229052 XS |
429 | static const struct sdhci_pci_fixes sdhci_intel_mfd_sd = { |
430 | .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, | |
c43fd774 | 431 | .allow_runtime_pm = true, |
77a0122e | 432 | .own_cd_for_runtime_pm = true, |
29229052 XS |
433 | }; |
434 | ||
0d013bcf AH |
435 | static const struct sdhci_pci_fixes sdhci_intel_mfd_sdio = { |
436 | .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, | |
f3c55a7b | 437 | .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON, |
c43fd774 | 438 | .allow_runtime_pm = true, |
93933508 | 439 | .probe_slot = mfd_sdio_probe_slot, |
0d013bcf AH |
440 | }; |
441 | ||
442 | static const struct sdhci_pci_fixes sdhci_intel_mfd_emmc = { | |
29229052 | 443 | .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, |
c43fd774 | 444 | .allow_runtime_pm = true, |
0d013bcf | 445 | .probe_slot = mfd_emmc_probe_slot, |
29229052 XS |
446 | }; |
447 | ||
296e0b03 AS |
448 | static const struct sdhci_pci_fixes sdhci_intel_pch_sdio = { |
449 | .quirks = SDHCI_QUIRK_BROKEN_ADMA, | |
450 | .probe_slot = pch_hc_probe_slot, | |
451 | }; | |
452 | ||
c959a6b0 AH |
453 | enum { |
454 | INTEL_DSM_FNS = 0, | |
6ae03368 | 455 | INTEL_DSM_V18_SWITCH = 3, |
be17355a | 456 | INTEL_DSM_V33_SWITCH = 4, |
51ced59c | 457 | INTEL_DSM_DRV_STRENGTH = 9, |
c959a6b0 AH |
458 | INTEL_DSM_D3_RETUNE = 10, |
459 | }; | |
460 | ||
461 | struct intel_host { | |
462 | u32 dsm_fns; | |
51ced59c | 463 | int drv_strength; |
c959a6b0 AH |
464 | bool d3_retune; |
465 | }; | |
466 | ||
c37f69ff | 467 | static const guid_t intel_dsm_guid = |
94116f81 AS |
468 | GUID_INIT(0xF6C13EA5, 0x65CD, 0x461F, |
469 | 0xAB, 0x7A, 0x29, 0xF7, 0xE8, 0xD5, 0xBD, 0x61); | |
c959a6b0 AH |
470 | |
471 | static int __intel_dsm(struct intel_host *intel_host, struct device *dev, | |
472 | unsigned int fn, u32 *result) | |
473 | { | |
474 | union acpi_object *obj; | |
475 | int err = 0; | |
a72016a4 | 476 | size_t len; |
c959a6b0 | 477 | |
94116f81 | 478 | obj = acpi_evaluate_dsm(ACPI_HANDLE(dev), &intel_dsm_guid, 0, fn, NULL); |
c959a6b0 AH |
479 | if (!obj) |
480 | return -EOPNOTSUPP; | |
481 | ||
482 | if (obj->type != ACPI_TYPE_BUFFER || obj->buffer.length < 1) { | |
483 | err = -EINVAL; | |
484 | goto out; | |
485 | } | |
486 | ||
a72016a4 AH |
487 | len = min_t(size_t, obj->buffer.length, 4); |
488 | ||
489 | *result = 0; | |
490 | memcpy(result, obj->buffer.pointer, len); | |
c959a6b0 AH |
491 | out: |
492 | ACPI_FREE(obj); | |
493 | ||
494 | return err; | |
495 | } | |
496 | ||
497 | static int intel_dsm(struct intel_host *intel_host, struct device *dev, | |
498 | unsigned int fn, u32 *result) | |
499 | { | |
500 | if (fn > 31 || !(intel_host->dsm_fns & (1 << fn))) | |
501 | return -EOPNOTSUPP; | |
502 | ||
503 | return __intel_dsm(intel_host, dev, fn, result); | |
504 | } | |
505 | ||
506 | static void intel_dsm_init(struct intel_host *intel_host, struct device *dev, | |
507 | struct mmc_host *mmc) | |
508 | { | |
509 | int err; | |
510 | u32 val; | |
511 | ||
eb701ce1 AH |
512 | intel_host->d3_retune = true; |
513 | ||
c959a6b0 AH |
514 | err = __intel_dsm(intel_host, dev, INTEL_DSM_FNS, &intel_host->dsm_fns); |
515 | if (err) { | |
516 | pr_debug("%s: DSM not supported, error %d\n", | |
517 | mmc_hostname(mmc), err); | |
518 | return; | |
519 | } | |
520 | ||
521 | pr_debug("%s: DSM function mask %#x\n", | |
522 | mmc_hostname(mmc), intel_host->dsm_fns); | |
523 | ||
51ced59c AH |
524 | err = intel_dsm(intel_host, dev, INTEL_DSM_DRV_STRENGTH, &val); |
525 | intel_host->drv_strength = err ? 0 : val; | |
526 | ||
c959a6b0 AH |
527 | err = intel_dsm(intel_host, dev, INTEL_DSM_D3_RETUNE, &val); |
528 | intel_host->d3_retune = err ? true : !!val; | |
529 | } | |
530 | ||
c9faff6c AH |
531 | static void sdhci_pci_int_hw_reset(struct sdhci_host *host) |
532 | { | |
533 | u8 reg; | |
534 | ||
535 | reg = sdhci_readb(host, SDHCI_POWER_CONTROL); | |
536 | reg |= 0x10; | |
537 | sdhci_writeb(host, reg, SDHCI_POWER_CONTROL); | |
538 | /* For eMMC, minimum is 1us but give it 9us for good measure */ | |
539 | udelay(9); | |
540 | reg &= ~0x10; | |
541 | sdhci_writeb(host, reg, SDHCI_POWER_CONTROL); | |
542 | /* For eMMC, minimum is 200us but give it 300us for good measure */ | |
543 | usleep_range(300, 1000); | |
544 | } | |
545 | ||
51ced59c AH |
546 | static int intel_select_drive_strength(struct mmc_card *card, |
547 | unsigned int max_dtr, int host_drv, | |
548 | int card_drv, int *drv_type) | |
e1bfad6d | 549 | { |
51ced59c AH |
550 | struct sdhci_host *host = mmc_priv(card->host); |
551 | struct sdhci_pci_slot *slot = sdhci_priv(host); | |
552 | struct intel_host *intel_host = sdhci_pci_priv(slot); | |
e1bfad6d | 553 | |
51ced59c | 554 | return intel_host->drv_strength; |
e1bfad6d AH |
555 | } |
556 | ||
163cbe31 AH |
557 | static int bxt_get_cd(struct mmc_host *mmc) |
558 | { | |
559 | int gpio_cd = mmc_gpio_get_cd(mmc); | |
560 | struct sdhci_host *host = mmc_priv(mmc); | |
561 | unsigned long flags; | |
562 | int ret = 0; | |
563 | ||
564 | if (!gpio_cd) | |
565 | return 0; | |
566 | ||
163cbe31 AH |
567 | spin_lock_irqsave(&host->lock, flags); |
568 | ||
569 | if (host->flags & SDHCI_DEVICE_DEAD) | |
570 | goto out; | |
571 | ||
572 | ret = !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT); | |
573 | out: | |
574 | spin_unlock_irqrestore(&host->lock, flags); | |
575 | ||
163cbe31 AH |
576 | return ret; |
577 | } | |
578 | ||
48d685a2 AH |
579 | #define SDHCI_INTEL_PWR_TIMEOUT_CNT 20 |
580 | #define SDHCI_INTEL_PWR_TIMEOUT_UDELAY 100 | |
581 | ||
582 | static void sdhci_intel_set_power(struct sdhci_host *host, unsigned char mode, | |
583 | unsigned short vdd) | |
584 | { | |
585 | int cntr; | |
586 | u8 reg; | |
587 | ||
588 | sdhci_set_power(host, mode, vdd); | |
589 | ||
590 | if (mode == MMC_POWER_OFF) | |
591 | return; | |
592 | ||
593 | /* | |
594 | * Bus power might not enable after D3 -> D0 transition due to the | |
595 | * present state not yet having propagated. Retry for up to 2ms. | |
596 | */ | |
597 | for (cntr = 0; cntr < SDHCI_INTEL_PWR_TIMEOUT_CNT; cntr++) { | |
598 | reg = sdhci_readb(host, SDHCI_POWER_CONTROL); | |
599 | if (reg & SDHCI_POWER_ON) | |
600 | break; | |
601 | udelay(SDHCI_INTEL_PWR_TIMEOUT_UDELAY); | |
602 | reg |= SDHCI_POWER_ON; | |
603 | sdhci_writeb(host, reg, SDHCI_POWER_CONTROL); | |
604 | } | |
605 | } | |
606 | ||
bc55dcd8 AH |
607 | #define INTEL_HS400_ES_REG 0x78 |
608 | #define INTEL_HS400_ES_BIT BIT(0) | |
609 | ||
610 | static void intel_hs400_enhanced_strobe(struct mmc_host *mmc, | |
611 | struct mmc_ios *ios) | |
612 | { | |
613 | struct sdhci_host *host = mmc_priv(mmc); | |
614 | u32 val; | |
615 | ||
616 | val = sdhci_readl(host, INTEL_HS400_ES_REG); | |
617 | if (ios->enhanced_strobe) | |
618 | val |= INTEL_HS400_ES_BIT; | |
619 | else | |
620 | val &= ~INTEL_HS400_ES_BIT; | |
621 | sdhci_writel(host, val, INTEL_HS400_ES_REG); | |
622 | } | |
623 | ||
be17355a AH |
624 | static int intel_start_signal_voltage_switch(struct mmc_host *mmc, |
625 | struct mmc_ios *ios) | |
6ae03368 | 626 | { |
be17355a AH |
627 | struct device *dev = mmc_dev(mmc); |
628 | struct sdhci_host *host = mmc_priv(mmc); | |
6ae03368 AH |
629 | struct sdhci_pci_slot *slot = sdhci_priv(host); |
630 | struct intel_host *intel_host = sdhci_pci_priv(slot); | |
be17355a | 631 | unsigned int fn; |
6ae03368 AH |
632 | u32 result = 0; |
633 | int err; | |
634 | ||
be17355a AH |
635 | err = sdhci_start_signal_voltage_switch(mmc, ios); |
636 | if (err) | |
637 | return err; | |
638 | ||
639 | switch (ios->signal_voltage) { | |
640 | case MMC_SIGNAL_VOLTAGE_330: | |
641 | fn = INTEL_DSM_V33_SWITCH; | |
642 | break; | |
643 | case MMC_SIGNAL_VOLTAGE_180: | |
644 | fn = INTEL_DSM_V18_SWITCH; | |
645 | break; | |
646 | default: | |
647 | return 0; | |
648 | } | |
649 | ||
650 | err = intel_dsm(intel_host, dev, fn, &result); | |
651 | pr_debug("%s: %s DSM fn %u error %d result %u\n", | |
652 | mmc_hostname(mmc), __func__, fn, err, result); | |
653 | ||
654 | return 0; | |
6ae03368 AH |
655 | } |
656 | ||
48d685a2 AH |
657 | static const struct sdhci_ops sdhci_intel_byt_ops = { |
658 | .set_clock = sdhci_set_clock, | |
659 | .set_power = sdhci_intel_set_power, | |
660 | .enable_dma = sdhci_pci_enable_dma, | |
adc16398 | 661 | .set_bus_width = sdhci_set_bus_width, |
48d685a2 AH |
662 | .reset = sdhci_reset, |
663 | .set_uhs_signaling = sdhci_set_uhs_signaling, | |
664 | .hw_reset = sdhci_pci_hw_reset, | |
665 | }; | |
666 | ||
8ee82bda AH |
667 | static const struct sdhci_ops sdhci_intel_glk_ops = { |
668 | .set_clock = sdhci_set_clock, | |
669 | .set_power = sdhci_intel_set_power, | |
670 | .enable_dma = sdhci_pci_enable_dma, | |
671 | .set_bus_width = sdhci_set_bus_width, | |
672 | .reset = sdhci_reset, | |
673 | .set_uhs_signaling = sdhci_set_uhs_signaling, | |
674 | .hw_reset = sdhci_pci_hw_reset, | |
8ee82bda AH |
675 | .irq = sdhci_cqhci_irq, |
676 | }; | |
677 | ||
c959a6b0 AH |
678 | static void byt_read_dsm(struct sdhci_pci_slot *slot) |
679 | { | |
680 | struct intel_host *intel_host = sdhci_pci_priv(slot); | |
681 | struct device *dev = &slot->chip->pdev->dev; | |
682 | struct mmc_host *mmc = slot->host->mmc; | |
683 | ||
684 | intel_dsm_init(intel_host, dev, mmc); | |
685 | slot->chip->rpm_retune = intel_host->d3_retune; | |
686 | } | |
687 | ||
f8870ae6 AH |
688 | static int intel_execute_tuning(struct mmc_host *mmc, u32 opcode) |
689 | { | |
690 | int err = sdhci_execute_tuning(mmc, opcode); | |
691 | struct sdhci_host *host = mmc_priv(mmc); | |
692 | ||
693 | if (err) | |
694 | return err; | |
695 | ||
696 | /* | |
697 | * Tuning can leave the IP in an active state (Buffer Read Enable bit | |
698 | * set) which prevents the entry to low power states (i.e. S0i3). Data | |
699 | * reset will clear it. | |
700 | */ | |
701 | sdhci_reset(host, SDHCI_RESET_DATA); | |
702 | ||
703 | return 0; | |
704 | } | |
705 | ||
706 | static void byt_probe_slot(struct sdhci_pci_slot *slot) | |
728ef3d1 | 707 | { |
f8870ae6 AH |
708 | struct mmc_host_ops *ops = &slot->host->mmc_host_ops; |
709 | ||
c959a6b0 | 710 | byt_read_dsm(slot); |
f8870ae6 AH |
711 | |
712 | ops->execute_tuning = intel_execute_tuning; | |
be17355a | 713 | ops->start_signal_voltage_switch = intel_start_signal_voltage_switch; |
f8870ae6 AH |
714 | } |
715 | ||
716 | static int byt_emmc_probe_slot(struct sdhci_pci_slot *slot) | |
717 | { | |
718 | byt_probe_slot(slot); | |
c9faff6c | 719 | slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE | |
6aab23a8 | 720 | MMC_CAP_HW_RESET | MMC_CAP_1_8V_DDR | |
32828857 | 721 | MMC_CAP_CMD_DURING_TFR | |
6aab23a8 | 722 | MMC_CAP_WAIT_WHILE_BUSY; |
c9faff6c | 723 | slot->hw_reset = sdhci_pci_int_hw_reset; |
a06586b6 AH |
724 | if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BSW_EMMC) |
725 | slot->host->timeout_clk = 1000; /* 1000 kHz i.e. 1 MHz */ | |
51ced59c AH |
726 | slot->host->mmc_host_ops.select_drive_strength = |
727 | intel_select_drive_strength; | |
728ef3d1 AH |
728 | return 0; |
729 | } | |
730 | ||
bc55dcd8 AH |
731 | static int glk_emmc_probe_slot(struct sdhci_pci_slot *slot) |
732 | { | |
733 | int ret = byt_emmc_probe_slot(slot); | |
734 | ||
8ee82bda AH |
735 | slot->host->mmc->caps2 |= MMC_CAP2_CQE; |
736 | ||
bc55dcd8 AH |
737 | if (slot->chip->pdev->device != PCI_DEVICE_ID_INTEL_GLK_EMMC) { |
738 | slot->host->mmc->caps2 |= MMC_CAP2_HS400_ES, | |
739 | slot->host->mmc_host_ops.hs400_enhanced_strobe = | |
740 | intel_hs400_enhanced_strobe; | |
8ee82bda | 741 | slot->host->mmc->caps2 |= MMC_CAP2_CQE_DCMD; |
bc55dcd8 AH |
742 | } |
743 | ||
744 | return ret; | |
745 | } | |
746 | ||
8ee82bda | 747 | static const struct cqhci_host_ops glk_cqhci_ops = { |
7b7d57fd | 748 | .enable = sdhci_cqe_enable, |
8ee82bda AH |
749 | .disable = sdhci_cqe_disable, |
750 | .dumpregs = sdhci_pci_dumpregs, | |
751 | }; | |
752 | ||
753 | static int glk_emmc_add_host(struct sdhci_pci_slot *slot) | |
754 | { | |
755 | struct device *dev = &slot->chip->pdev->dev; | |
756 | struct sdhci_host *host = slot->host; | |
757 | struct cqhci_host *cq_host; | |
758 | bool dma64; | |
759 | int ret; | |
760 | ||
761 | ret = sdhci_setup_host(host); | |
762 | if (ret) | |
763 | return ret; | |
764 | ||
765 | cq_host = devm_kzalloc(dev, sizeof(*cq_host), GFP_KERNEL); | |
766 | if (!cq_host) { | |
767 | ret = -ENOMEM; | |
768 | goto cleanup; | |
769 | } | |
770 | ||
771 | cq_host->mmio = host->ioaddr + 0x200; | |
772 | cq_host->quirks |= CQHCI_QUIRK_SHORT_TXFR_DESC_SZ; | |
773 | cq_host->ops = &glk_cqhci_ops; | |
774 | ||
775 | dma64 = host->flags & SDHCI_USE_64_BIT_DMA; | |
776 | if (dma64) | |
777 | cq_host->caps |= CQHCI_TASK_DESC_SZ_128; | |
778 | ||
779 | ret = cqhci_init(cq_host, host->mmc, dma64); | |
780 | if (ret) | |
781 | goto cleanup; | |
782 | ||
783 | ret = __sdhci_add_host(host); | |
784 | if (ret) | |
785 | goto cleanup; | |
786 | ||
787 | return 0; | |
788 | ||
789 | cleanup: | |
790 | sdhci_cleanup_host(host); | |
791 | return ret; | |
792 | } | |
793 | ||
3f23df72 ZB |
794 | #ifdef CONFIG_ACPI |
795 | static int ni_set_max_freq(struct sdhci_pci_slot *slot) | |
796 | { | |
797 | acpi_status status; | |
798 | unsigned long long max_freq; | |
799 | ||
800 | status = acpi_evaluate_integer(ACPI_HANDLE(&slot->chip->pdev->dev), | |
801 | "MXFQ", NULL, &max_freq); | |
802 | if (ACPI_FAILURE(status)) { | |
803 | dev_err(&slot->chip->pdev->dev, | |
804 | "MXFQ not found in acpi table\n"); | |
805 | return -EINVAL; | |
806 | } | |
807 | ||
808 | slot->host->mmc->f_max = max_freq * 1000000; | |
809 | ||
810 | return 0; | |
811 | } | |
812 | #else | |
813 | static inline int ni_set_max_freq(struct sdhci_pci_slot *slot) | |
814 | { | |
815 | return 0; | |
816 | } | |
817 | #endif | |
818 | ||
42b06496 ZB |
819 | static int ni_byt_sdio_probe_slot(struct sdhci_pci_slot *slot) |
820 | { | |
3f23df72 ZB |
821 | int err; |
822 | ||
f8870ae6 | 823 | byt_probe_slot(slot); |
c959a6b0 | 824 | |
3f23df72 ZB |
825 | err = ni_set_max_freq(slot); |
826 | if (err) | |
827 | return err; | |
828 | ||
42b06496 ZB |
829 | slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE | |
830 | MMC_CAP_WAIT_WHILE_BUSY; | |
831 | return 0; | |
832 | } | |
833 | ||
728ef3d1 AH |
834 | static int byt_sdio_probe_slot(struct sdhci_pci_slot *slot) |
835 | { | |
f8870ae6 | 836 | byt_probe_slot(slot); |
6aab23a8 | 837 | slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE | |
6aab23a8 | 838 | MMC_CAP_WAIT_WHILE_BUSY; |
728ef3d1 AH |
839 | return 0; |
840 | } | |
841 | ||
ff59c520 AH |
842 | static int byt_sd_probe_slot(struct sdhci_pci_slot *slot) |
843 | { | |
f8870ae6 | 844 | byt_probe_slot(slot); |
c2c49a2e | 845 | slot->host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY | |
6cf4156c | 846 | MMC_CAP_AGGRESSIVE_PM | MMC_CAP_CD_WAKE; |
ff59c520 AH |
847 | slot->cd_idx = 0; |
848 | slot->cd_override_level = true; | |
163cbe31 | 849 | if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BXT_SD || |
01d6b2a4 | 850 | slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BXTM_SD || |
2d1956d0 | 851 | slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_APL_SD || |
c2c49a2e | 852 | slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_GLK_SD) |
163cbe31 AH |
853 | slot->host->mmc_host_ops.get_cd = bxt_get_cd; |
854 | ||
bb26b841 KR |
855 | if (slot->chip->pdev->subsystem_vendor == PCI_VENDOR_ID_NI && |
856 | slot->chip->pdev->subsystem_device == PCI_SUBDEVICE_ID_NI_78E3) | |
857 | slot->host->mmc->caps2 |= MMC_CAP2_AVOID_3_3V; | |
858 | ||
ff59c520 AH |
859 | return 0; |
860 | } | |
861 | ||
728ef3d1 AH |
862 | static const struct sdhci_pci_fixes sdhci_intel_byt_emmc = { |
863 | .allow_runtime_pm = true, | |
864 | .probe_slot = byt_emmc_probe_slot, | |
db6e8cdf | 865 | .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, |
e58e4a0d | 866 | .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | |
b69587e2 | 867 | SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 | |
e58e4a0d | 868 | SDHCI_QUIRK2_STOP_WITH_TC, |
fee686b7 | 869 | .ops = &sdhci_intel_byt_ops, |
c959a6b0 | 870 | .priv_size = sizeof(struct intel_host), |
728ef3d1 AH |
871 | }; |
872 | ||
bc55dcd8 AH |
873 | static const struct sdhci_pci_fixes sdhci_intel_glk_emmc = { |
874 | .allow_runtime_pm = true, | |
875 | .probe_slot = glk_emmc_probe_slot, | |
8ee82bda AH |
876 | .add_host = glk_emmc_add_host, |
877 | #ifdef CONFIG_PM_SLEEP | |
878 | .suspend = sdhci_cqhci_suspend, | |
879 | .resume = sdhci_cqhci_resume, | |
880 | #endif | |
881 | #ifdef CONFIG_PM | |
882 | .runtime_suspend = sdhci_cqhci_runtime_suspend, | |
883 | .runtime_resume = sdhci_cqhci_runtime_resume, | |
884 | #endif | |
bc55dcd8 AH |
885 | .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, |
886 | .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | | |
887 | SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 | | |
888 | SDHCI_QUIRK2_STOP_WITH_TC, | |
8ee82bda | 889 | .ops = &sdhci_intel_glk_ops, |
bc55dcd8 AH |
890 | .priv_size = sizeof(struct intel_host), |
891 | }; | |
892 | ||
42b06496 ZB |
893 | static const struct sdhci_pci_fixes sdhci_ni_byt_sdio = { |
894 | .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, | |
895 | .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON | | |
896 | SDHCI_QUIRK2_PRESET_VALUE_BROKEN, | |
897 | .allow_runtime_pm = true, | |
898 | .probe_slot = ni_byt_sdio_probe_slot, | |
899 | .ops = &sdhci_intel_byt_ops, | |
c959a6b0 | 900 | .priv_size = sizeof(struct intel_host), |
42b06496 ZB |
901 | }; |
902 | ||
728ef3d1 | 903 | static const struct sdhci_pci_fixes sdhci_intel_byt_sdio = { |
db6e8cdf | 904 | .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, |
b7574bad GY |
905 | .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON | |
906 | SDHCI_QUIRK2_PRESET_VALUE_BROKEN, | |
728ef3d1 AH |
907 | .allow_runtime_pm = true, |
908 | .probe_slot = byt_sdio_probe_slot, | |
fee686b7 | 909 | .ops = &sdhci_intel_byt_ops, |
c959a6b0 | 910 | .priv_size = sizeof(struct intel_host), |
728ef3d1 AH |
911 | }; |
912 | ||
913 | static const struct sdhci_pci_fixes sdhci_intel_byt_sd = { | |
db6e8cdf | 914 | .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, |
b7574bad | 915 | .quirks2 = SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON | |
e58e4a0d AH |
916 | SDHCI_QUIRK2_PRESET_VALUE_BROKEN | |
917 | SDHCI_QUIRK2_STOP_WITH_TC, | |
7396e318 | 918 | .allow_runtime_pm = true, |
77a0122e | 919 | .own_cd_for_runtime_pm = true, |
ff59c520 | 920 | .probe_slot = byt_sd_probe_slot, |
fee686b7 | 921 | .ops = &sdhci_intel_byt_ops, |
c959a6b0 | 922 | .priv_size = sizeof(struct intel_host), |
728ef3d1 AH |
923 | }; |
924 | ||
8776a165 | 925 | /* Define Host controllers for Intel Merrifield platform */ |
1f64cec2 AS |
926 | #define INTEL_MRFLD_EMMC_0 0 |
927 | #define INTEL_MRFLD_EMMC_1 1 | |
4674b6c8 | 928 | #define INTEL_MRFLD_SD 2 |
d5565577 | 929 | #define INTEL_MRFLD_SDIO 3 |
8776a165 | 930 | |
0e39220e AS |
931 | #ifdef CONFIG_ACPI |
932 | static void intel_mrfld_mmc_fix_up_power_slot(struct sdhci_pci_slot *slot) | |
933 | { | |
934 | struct acpi_device *device, *child; | |
935 | ||
936 | device = ACPI_COMPANION(&slot->chip->pdev->dev); | |
937 | if (!device) | |
938 | return; | |
939 | ||
940 | acpi_device_fix_up_power(device); | |
941 | list_for_each_entry(child, &device->children, node) | |
942 | if (child->status.present && child->status.enabled) | |
943 | acpi_device_fix_up_power(child); | |
944 | } | |
945 | #else | |
946 | static inline void intel_mrfld_mmc_fix_up_power_slot(struct sdhci_pci_slot *slot) {} | |
947 | #endif | |
948 | ||
1f64cec2 | 949 | static int intel_mrfld_mmc_probe_slot(struct sdhci_pci_slot *slot) |
8776a165 | 950 | { |
2e57bbe2 AS |
951 | unsigned int func = PCI_FUNC(slot->chip->pdev->devfn); |
952 | ||
953 | switch (func) { | |
954 | case INTEL_MRFLD_EMMC_0: | |
955 | case INTEL_MRFLD_EMMC_1: | |
956 | slot->host->mmc->caps |= MMC_CAP_NONREMOVABLE | | |
957 | MMC_CAP_8_BIT_DATA | | |
958 | MMC_CAP_1_8V_DDR; | |
959 | break; | |
4674b6c8 AS |
960 | case INTEL_MRFLD_SD: |
961 | slot->host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V; | |
962 | break; | |
d5565577 | 963 | case INTEL_MRFLD_SDIO: |
2a609abe AS |
964 | /* Advertise 2.0v for compatibility with the SDIO card's OCR */ |
965 | slot->host->ocr_mask = MMC_VDD_20_21 | MMC_VDD_165_195; | |
d5565577 AS |
966 | slot->host->mmc->caps |= MMC_CAP_NONREMOVABLE | |
967 | MMC_CAP_POWER_OFF_CARD; | |
968 | break; | |
2e57bbe2 | 969 | default: |
8776a165 | 970 | return -ENODEV; |
2e57bbe2 | 971 | } |
0e39220e AS |
972 | |
973 | intel_mrfld_mmc_fix_up_power_slot(slot); | |
8776a165 DC |
974 | return 0; |
975 | } | |
976 | ||
1f64cec2 | 977 | static const struct sdhci_pci_fixes sdhci_intel_mrfld_mmc = { |
8776a165 | 978 | .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, |
b7574bad GY |
979 | .quirks2 = SDHCI_QUIRK2_BROKEN_HS200 | |
980 | SDHCI_QUIRK2_PRESET_VALUE_BROKEN, | |
f1b55a55 | 981 | .allow_runtime_pm = true, |
1f64cec2 | 982 | .probe_slot = intel_mrfld_mmc_probe_slot, |
8776a165 DC |
983 | }; |
984 | ||
45211e21 PO |
985 | static int jmicron_pmos(struct sdhci_pci_chip *chip, int on) |
986 | { | |
987 | u8 scratch; | |
988 | int ret; | |
989 | ||
990 | ret = pci_read_config_byte(chip->pdev, 0xAE, &scratch); | |
991 | if (ret) | |
992 | return ret; | |
993 | ||
994 | /* | |
995 | * Turn PMOS on [bit 0], set over current detection to 2.4 V | |
996 | * [bit 1:2] and enable over current debouncing [bit 6]. | |
997 | */ | |
998 | if (on) | |
999 | scratch |= 0x47; | |
1000 | else | |
1001 | scratch &= ~0x47; | |
1002 | ||
7582041f | 1003 | return pci_write_config_byte(chip->pdev, 0xAE, scratch); |
45211e21 PO |
1004 | } |
1005 | ||
1006 | static int jmicron_probe(struct sdhci_pci_chip *chip) | |
1007 | { | |
1008 | int ret; | |
8f230f45 | 1009 | u16 mmcdev = 0; |
45211e21 | 1010 | |
93fc48c7 PO |
1011 | if (chip->pdev->revision == 0) { |
1012 | chip->quirks |= SDHCI_QUIRK_32BIT_DMA_ADDR | | |
1013 | SDHCI_QUIRK_32BIT_DMA_SIZE | | |
2134a922 | 1014 | SDHCI_QUIRK_32BIT_ADMA_SIZE | |
4a3cba32 | 1015 | SDHCI_QUIRK_RESET_AFTER_REQUEST | |
86a6a874 | 1016 | SDHCI_QUIRK_BROKEN_SMALL_PIO; |
93fc48c7 PO |
1017 | } |
1018 | ||
4489428a PO |
1019 | /* |
1020 | * JMicron chips can have two interfaces to the same hardware | |
1021 | * in order to work around limitations in Microsoft's driver. | |
1022 | * We need to make sure we only bind to one of them. | |
1023 | * | |
1024 | * This code assumes two things: | |
1025 | * | |
1026 | * 1. The PCI code adds subfunctions in order. | |
1027 | * | |
1028 | * 2. The MMC interface has a lower subfunction number | |
1029 | * than the SD interface. | |
1030 | */ | |
8f230f45 TI |
1031 | if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_SD) |
1032 | mmcdev = PCI_DEVICE_ID_JMICRON_JMB38X_MMC; | |
1033 | else if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD) | |
1034 | mmcdev = PCI_DEVICE_ID_JMICRON_JMB388_ESD; | |
1035 | ||
1036 | if (mmcdev) { | |
4489428a PO |
1037 | struct pci_dev *sd_dev; |
1038 | ||
1039 | sd_dev = NULL; | |
1040 | while ((sd_dev = pci_get_device(PCI_VENDOR_ID_JMICRON, | |
8f230f45 | 1041 | mmcdev, sd_dev)) != NULL) { |
4489428a PO |
1042 | if ((PCI_SLOT(chip->pdev->devfn) == |
1043 | PCI_SLOT(sd_dev->devfn)) && | |
1044 | (chip->pdev->bus == sd_dev->bus)) | |
1045 | break; | |
1046 | } | |
1047 | ||
1048 | if (sd_dev) { | |
1049 | pci_dev_put(sd_dev); | |
1050 | dev_info(&chip->pdev->dev, "Refusing to bind to " | |
1051 | "secondary interface.\n"); | |
1052 | return -ENODEV; | |
1053 | } | |
1054 | } | |
1055 | ||
45211e21 PO |
1056 | /* |
1057 | * JMicron chips need a bit of a nudge to enable the power | |
1058 | * output pins. | |
1059 | */ | |
1060 | ret = jmicron_pmos(chip, 1); | |
1061 | if (ret) { | |
1062 | dev_err(&chip->pdev->dev, "Failure enabling card power\n"); | |
1063 | return ret; | |
1064 | } | |
1065 | ||
82b0e23a TI |
1066 | /* quirk for unsable RO-detection on JM388 chips */ |
1067 | if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD || | |
1068 | chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) | |
1069 | chip->quirks |= SDHCI_QUIRK_UNSTABLE_RO_DETECT; | |
1070 | ||
45211e21 PO |
1071 | return 0; |
1072 | } | |
1073 | ||
4489428a PO |
1074 | static void jmicron_enable_mmc(struct sdhci_host *host, int on) |
1075 | { | |
1076 | u8 scratch; | |
1077 | ||
1078 | scratch = readb(host->ioaddr + 0xC0); | |
1079 | ||
1080 | if (on) | |
1081 | scratch |= 0x01; | |
1082 | else | |
1083 | scratch &= ~0x01; | |
1084 | ||
1085 | writeb(scratch, host->ioaddr + 0xC0); | |
1086 | } | |
1087 | ||
1088 | static int jmicron_probe_slot(struct sdhci_pci_slot *slot) | |
1089 | { | |
2134a922 PO |
1090 | if (slot->chip->pdev->revision == 0) { |
1091 | u16 version; | |
1092 | ||
1093 | version = readl(slot->host->ioaddr + SDHCI_HOST_VERSION); | |
1094 | version = (version & SDHCI_VENDOR_VER_MASK) >> | |
1095 | SDHCI_VENDOR_VER_SHIFT; | |
1096 | ||
1097 | /* | |
1098 | * Older versions of the chip have lots of nasty glitches | |
1099 | * in the ADMA engine. It's best just to avoid it | |
1100 | * completely. | |
1101 | */ | |
1102 | if (version < 0xAC) | |
1103 | slot->host->quirks |= SDHCI_QUIRK_BROKEN_ADMA; | |
1104 | } | |
1105 | ||
8f230f45 TI |
1106 | /* JM388 MMC doesn't support 1.8V while SD supports it */ |
1107 | if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) { | |
1108 | slot->host->ocr_avail_sd = MMC_VDD_32_33 | MMC_VDD_33_34 | | |
1109 | MMC_VDD_29_30 | MMC_VDD_30_31 | | |
1110 | MMC_VDD_165_195; /* allow 1.8V */ | |
1111 | slot->host->ocr_avail_mmc = MMC_VDD_32_33 | MMC_VDD_33_34 | | |
1112 | MMC_VDD_29_30 | MMC_VDD_30_31; /* no 1.8V for MMC */ | |
1113 | } | |
1114 | ||
4489428a PO |
1115 | /* |
1116 | * The secondary interface requires a bit set to get the | |
1117 | * interrupts. | |
1118 | */ | |
8f230f45 TI |
1119 | if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || |
1120 | slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) | |
4489428a PO |
1121 | jmicron_enable_mmc(slot->host, 1); |
1122 | ||
d75c1084 TI |
1123 | slot->host->mmc->caps |= MMC_CAP_BUS_WIDTH_TEST; |
1124 | ||
4489428a PO |
1125 | return 0; |
1126 | } | |
1127 | ||
1e72859e | 1128 | static void jmicron_remove_slot(struct sdhci_pci_slot *slot, int dead) |
4489428a | 1129 | { |
1e72859e PO |
1130 | if (dead) |
1131 | return; | |
1132 | ||
8f230f45 TI |
1133 | if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || |
1134 | slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) | |
4489428a PO |
1135 | jmicron_enable_mmc(slot->host, 0); |
1136 | } | |
1137 | ||
b7813f0f | 1138 | #ifdef CONFIG_PM_SLEEP |
29495aa0 | 1139 | static int jmicron_suspend(struct sdhci_pci_chip *chip) |
4489428a | 1140 | { |
30cf2803 AH |
1141 | int i, ret; |
1142 | ||
5c3c6126 | 1143 | ret = sdhci_pci_suspend_host(chip); |
30cf2803 AH |
1144 | if (ret) |
1145 | return ret; | |
4489428a | 1146 | |
8f230f45 TI |
1147 | if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || |
1148 | chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) { | |
b177bc91 | 1149 | for (i = 0; i < chip->num_slots; i++) |
4489428a PO |
1150 | jmicron_enable_mmc(chip->slots[i]->host, 0); |
1151 | } | |
1152 | ||
1153 | return 0; | |
1154 | } | |
1155 | ||
45211e21 PO |
1156 | static int jmicron_resume(struct sdhci_pci_chip *chip) |
1157 | { | |
4489428a PO |
1158 | int ret, i; |
1159 | ||
8f230f45 TI |
1160 | if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || |
1161 | chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) { | |
b177bc91 | 1162 | for (i = 0; i < chip->num_slots; i++) |
4489428a PO |
1163 | jmicron_enable_mmc(chip->slots[i]->host, 1); |
1164 | } | |
45211e21 PO |
1165 | |
1166 | ret = jmicron_pmos(chip, 1); | |
1167 | if (ret) { | |
1168 | dev_err(&chip->pdev->dev, "Failure enabling card power\n"); | |
1169 | return ret; | |
1170 | } | |
1171 | ||
30cf2803 | 1172 | return sdhci_pci_resume_host(chip); |
45211e21 | 1173 | } |
b7813f0f | 1174 | #endif |
45211e21 | 1175 | |
26daa1ed | 1176 | static const struct sdhci_pci_fixes sdhci_o2 = { |
01acf691 AL |
1177 | .probe = sdhci_pci_o2_probe, |
1178 | .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, | |
143b648d | 1179 | .quirks2 = SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD, |
01acf691 | 1180 | .probe_slot = sdhci_pci_o2_probe_slot, |
b7813f0f | 1181 | #ifdef CONFIG_PM_SLEEP |
01acf691 | 1182 | .resume = sdhci_pci_o2_resume, |
b7813f0f | 1183 | #endif |
26daa1ed JL |
1184 | }; |
1185 | ||
22606405 | 1186 | static const struct sdhci_pci_fixes sdhci_jmicron = { |
45211e21 PO |
1187 | .probe = jmicron_probe, |
1188 | ||
4489428a PO |
1189 | .probe_slot = jmicron_probe_slot, |
1190 | .remove_slot = jmicron_remove_slot, | |
1191 | ||
b7813f0f | 1192 | #ifdef CONFIG_PM_SLEEP |
4489428a | 1193 | .suspend = jmicron_suspend, |
45211e21 | 1194 | .resume = jmicron_resume, |
b7813f0f | 1195 | #endif |
22606405 PO |
1196 | }; |
1197 | ||
a7a6186c NP |
1198 | /* SysKonnect CardBus2SDIO extra registers */ |
1199 | #define SYSKT_CTRL 0x200 | |
1200 | #define SYSKT_RDFIFO_STAT 0x204 | |
1201 | #define SYSKT_WRFIFO_STAT 0x208 | |
1202 | #define SYSKT_POWER_DATA 0x20c | |
1203 | #define SYSKT_POWER_330 0xef | |
1204 | #define SYSKT_POWER_300 0xf8 | |
1205 | #define SYSKT_POWER_184 0xcc | |
1206 | #define SYSKT_POWER_CMD 0x20d | |
1207 | #define SYSKT_POWER_START (1 << 7) | |
1208 | #define SYSKT_POWER_STATUS 0x20e | |
1209 | #define SYSKT_POWER_STATUS_OK (1 << 0) | |
1210 | #define SYSKT_BOARD_REV 0x210 | |
1211 | #define SYSKT_CHIP_REV 0x211 | |
1212 | #define SYSKT_CONF_DATA 0x212 | |
1213 | #define SYSKT_CONF_DATA_1V8 (1 << 2) | |
1214 | #define SYSKT_CONF_DATA_2V5 (1 << 1) | |
1215 | #define SYSKT_CONF_DATA_3V3 (1 << 0) | |
1216 | ||
1217 | static int syskt_probe(struct sdhci_pci_chip *chip) | |
1218 | { | |
1219 | if ((chip->pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) { | |
1220 | chip->pdev->class &= ~0x0000FF; | |
1221 | chip->pdev->class |= PCI_SDHCI_IFDMA; | |
1222 | } | |
1223 | return 0; | |
1224 | } | |
1225 | ||
1226 | static int syskt_probe_slot(struct sdhci_pci_slot *slot) | |
1227 | { | |
1228 | int tm, ps; | |
1229 | ||
1230 | u8 board_rev = readb(slot->host->ioaddr + SYSKT_BOARD_REV); | |
1231 | u8 chip_rev = readb(slot->host->ioaddr + SYSKT_CHIP_REV); | |
1232 | dev_info(&slot->chip->pdev->dev, "SysKonnect CardBus2SDIO, " | |
1233 | "board rev %d.%d, chip rev %d.%d\n", | |
1234 | board_rev >> 4, board_rev & 0xf, | |
1235 | chip_rev >> 4, chip_rev & 0xf); | |
1236 | if (chip_rev >= 0x20) | |
1237 | slot->host->quirks |= SDHCI_QUIRK_FORCE_DMA; | |
1238 | ||
1239 | writeb(SYSKT_POWER_330, slot->host->ioaddr + SYSKT_POWER_DATA); | |
1240 | writeb(SYSKT_POWER_START, slot->host->ioaddr + SYSKT_POWER_CMD); | |
1241 | udelay(50); | |
1242 | tm = 10; /* Wait max 1 ms */ | |
1243 | do { | |
1244 | ps = readw(slot->host->ioaddr + SYSKT_POWER_STATUS); | |
1245 | if (ps & SYSKT_POWER_STATUS_OK) | |
1246 | break; | |
1247 | udelay(100); | |
1248 | } while (--tm); | |
1249 | if (!tm) { | |
1250 | dev_err(&slot->chip->pdev->dev, | |
1251 | "power regulator never stabilized"); | |
1252 | writeb(0, slot->host->ioaddr + SYSKT_POWER_CMD); | |
1253 | return -ENODEV; | |
1254 | } | |
1255 | ||
1256 | return 0; | |
1257 | } | |
1258 | ||
1259 | static const struct sdhci_pci_fixes sdhci_syskt = { | |
1260 | .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER, | |
1261 | .probe = syskt_probe, | |
1262 | .probe_slot = syskt_probe_slot, | |
1263 | }; | |
1264 | ||
557b0697 HW |
1265 | static int via_probe(struct sdhci_pci_chip *chip) |
1266 | { | |
1267 | if (chip->pdev->revision == 0x10) | |
1268 | chip->quirks |= SDHCI_QUIRK_DELAY_AFTER_POWER; | |
1269 | ||
1270 | return 0; | |
1271 | } | |
1272 | ||
1273 | static const struct sdhci_pci_fixes sdhci_via = { | |
1274 | .probe = via_probe, | |
1275 | }; | |
1276 | ||
9107ebbf MC |
1277 | static int rtsx_probe_slot(struct sdhci_pci_slot *slot) |
1278 | { | |
1279 | slot->host->mmc->caps2 |= MMC_CAP2_HS200; | |
1280 | return 0; | |
1281 | } | |
1282 | ||
1283 | static const struct sdhci_pci_fixes sdhci_rtsx = { | |
1284 | .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | | |
e30b978f | 1285 | SDHCI_QUIRK2_BROKEN_64_BIT_DMA | |
9107ebbf MC |
1286 | SDHCI_QUIRK2_BROKEN_DDR50, |
1287 | .probe_slot = rtsx_probe_slot, | |
1288 | }; | |
1289 | ||
b5e97d6e VW |
1290 | /*AMD chipset generation*/ |
1291 | enum amd_chipset_gen { | |
1292 | AMD_CHIPSET_BEFORE_ML, | |
1293 | AMD_CHIPSET_CZ, | |
1294 | AMD_CHIPSET_NL, | |
1295 | AMD_CHIPSET_UNKNOWN, | |
1296 | }; | |
1297 | ||
c31165d7 SS |
1298 | /* AMD registers */ |
1299 | #define AMD_SD_AUTO_PATTERN 0xB8 | |
1300 | #define AMD_MSLEEP_DURATION 4 | |
1301 | #define AMD_SD_MISC_CONTROL 0xD0 | |
1302 | #define AMD_MAX_TUNE_VALUE 0x0B | |
1303 | #define AMD_AUTO_TUNE_SEL 0x10800 | |
1304 | #define AMD_FIFO_PTR 0x30 | |
1305 | #define AMD_BIT_MASK 0x1F | |
1306 | ||
1307 | static void amd_tuning_reset(struct sdhci_host *host) | |
1308 | { | |
1309 | unsigned int val; | |
1310 | ||
1311 | val = sdhci_readw(host, SDHCI_HOST_CONTROL2); | |
1312 | val |= SDHCI_CTRL_PRESET_VAL_ENABLE | SDHCI_CTRL_EXEC_TUNING; | |
1313 | sdhci_writew(host, val, SDHCI_HOST_CONTROL2); | |
1314 | ||
1315 | val = sdhci_readw(host, SDHCI_HOST_CONTROL2); | |
1316 | val &= ~SDHCI_CTRL_EXEC_TUNING; | |
1317 | sdhci_writew(host, val, SDHCI_HOST_CONTROL2); | |
1318 | } | |
1319 | ||
1320 | static void amd_config_tuning_phase(struct pci_dev *pdev, u8 phase) | |
1321 | { | |
1322 | unsigned int val; | |
1323 | ||
1324 | pci_read_config_dword(pdev, AMD_SD_AUTO_PATTERN, &val); | |
1325 | val &= ~AMD_BIT_MASK; | |
1326 | val |= (AMD_AUTO_TUNE_SEL | (phase << 1)); | |
1327 | pci_write_config_dword(pdev, AMD_SD_AUTO_PATTERN, val); | |
1328 | } | |
1329 | ||
1330 | static void amd_enable_manual_tuning(struct pci_dev *pdev) | |
1331 | { | |
1332 | unsigned int val; | |
1333 | ||
1334 | pci_read_config_dword(pdev, AMD_SD_MISC_CONTROL, &val); | |
1335 | val |= AMD_FIFO_PTR; | |
1336 | pci_write_config_dword(pdev, AMD_SD_MISC_CONTROL, val); | |
1337 | } | |
1338 | ||
300ad899 | 1339 | static int amd_execute_tuning_hs200(struct sdhci_host *host, u32 opcode) |
c31165d7 SS |
1340 | { |
1341 | struct sdhci_pci_slot *slot = sdhci_priv(host); | |
1342 | struct pci_dev *pdev = slot->chip->pdev; | |
1343 | u8 valid_win = 0; | |
1344 | u8 valid_win_max = 0; | |
1345 | u8 valid_win_end = 0; | |
1346 | u8 ctrl, tune_around; | |
1347 | ||
1348 | amd_tuning_reset(host); | |
1349 | ||
1350 | for (tune_around = 0; tune_around < 12; tune_around++) { | |
1351 | amd_config_tuning_phase(pdev, tune_around); | |
1352 | ||
1353 | if (mmc_send_tuning(host->mmc, opcode, NULL)) { | |
1354 | valid_win = 0; | |
1355 | msleep(AMD_MSLEEP_DURATION); | |
1356 | ctrl = SDHCI_RESET_CMD | SDHCI_RESET_DATA; | |
1357 | sdhci_writeb(host, ctrl, SDHCI_SOFTWARE_RESET); | |
1358 | } else if (++valid_win > valid_win_max) { | |
1359 | valid_win_max = valid_win; | |
1360 | valid_win_end = tune_around; | |
1361 | } | |
1362 | } | |
1363 | ||
1364 | if (!valid_win_max) { | |
1365 | dev_err(&pdev->dev, "no tuning point found\n"); | |
1366 | return -EIO; | |
1367 | } | |
1368 | ||
1369 | amd_config_tuning_phase(pdev, valid_win_end - valid_win_max / 2); | |
1370 | ||
1371 | amd_enable_manual_tuning(pdev); | |
1372 | ||
1373 | host->mmc->retune_period = 0; | |
1374 | ||
1375 | return 0; | |
1376 | } | |
1377 | ||
300ad899 DK |
1378 | static int amd_execute_tuning(struct mmc_host *mmc, u32 opcode) |
1379 | { | |
1380 | struct sdhci_host *host = mmc_priv(mmc); | |
1381 | ||
1382 | /* AMD requires custom HS200 tuning */ | |
1383 | if (host->timing == MMC_TIMING_MMC_HS200) | |
1384 | return amd_execute_tuning_hs200(host, opcode); | |
1385 | ||
1386 | /* Otherwise perform standard SDHCI tuning */ | |
1387 | return sdhci_execute_tuning(mmc, opcode); | |
1388 | } | |
1389 | ||
1390 | static int amd_probe_slot(struct sdhci_pci_slot *slot) | |
1391 | { | |
1392 | struct mmc_host_ops *ops = &slot->host->mmc_host_ops; | |
1393 | ||
1394 | ops->execute_tuning = amd_execute_tuning; | |
1395 | ||
1396 | return 0; | |
1397 | } | |
1398 | ||
d44f88da VW |
1399 | static int amd_probe(struct sdhci_pci_chip *chip) |
1400 | { | |
1401 | struct pci_dev *smbus_dev; | |
b5e97d6e | 1402 | enum amd_chipset_gen gen; |
d44f88da VW |
1403 | |
1404 | smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD, | |
1405 | PCI_DEVICE_ID_AMD_HUDSON2_SMBUS, NULL); | |
b5e97d6e VW |
1406 | if (smbus_dev) { |
1407 | gen = AMD_CHIPSET_BEFORE_ML; | |
1408 | } else { | |
1409 | smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD, | |
1410 | PCI_DEVICE_ID_AMD_KERNCZ_SMBUS, NULL); | |
1411 | if (smbus_dev) { | |
1412 | if (smbus_dev->revision < 0x51) | |
1413 | gen = AMD_CHIPSET_CZ; | |
1414 | else | |
1415 | gen = AMD_CHIPSET_NL; | |
1416 | } else { | |
1417 | gen = AMD_CHIPSET_UNKNOWN; | |
1418 | } | |
1419 | } | |
d44f88da | 1420 | |
c31165d7 | 1421 | if (gen == AMD_CHIPSET_BEFORE_ML || gen == AMD_CHIPSET_CZ) |
d44f88da VW |
1422 | chip->quirks2 |= SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD; |
1423 | ||
1424 | return 0; | |
1425 | } | |
1426 | ||
c31165d7 SS |
1427 | static const struct sdhci_ops amd_sdhci_pci_ops = { |
1428 | .set_clock = sdhci_set_clock, | |
1429 | .enable_dma = sdhci_pci_enable_dma, | |
adc16398 | 1430 | .set_bus_width = sdhci_set_bus_width, |
c31165d7 SS |
1431 | .reset = sdhci_reset, |
1432 | .set_uhs_signaling = sdhci_set_uhs_signaling, | |
c31165d7 SS |
1433 | }; |
1434 | ||
d44f88da VW |
1435 | static const struct sdhci_pci_fixes sdhci_amd = { |
1436 | .probe = amd_probe, | |
c31165d7 | 1437 | .ops = &amd_sdhci_pci_ops, |
300ad899 | 1438 | .probe_slot = amd_probe_slot, |
d44f88da VW |
1439 | }; |
1440 | ||
9647f84d | 1441 | static const struct pci_device_id pci_ids[] = { |
c949c907 MK |
1442 | SDHCI_PCI_DEVICE(RICOH, R5C822, ricoh), |
1443 | SDHCI_PCI_DEVICE(RICOH, R5C843, ricoh_mmc), | |
1444 | SDHCI_PCI_DEVICE(RICOH, R5CE822, ricoh_mmc), | |
1445 | SDHCI_PCI_DEVICE(RICOH, R5CE823, ricoh_mmc), | |
1446 | SDHCI_PCI_DEVICE(ENE, CB712_SD, ene_712), | |
1447 | SDHCI_PCI_DEVICE(ENE, CB712_SD_2, ene_712), | |
1448 | SDHCI_PCI_DEVICE(ENE, CB714_SD, ene_714), | |
1449 | SDHCI_PCI_DEVICE(ENE, CB714_SD_2, ene_714), | |
1450 | SDHCI_PCI_DEVICE(MARVELL, 88ALP01_SD, cafe), | |
1451 | SDHCI_PCI_DEVICE(JMICRON, JMB38X_SD, jmicron), | |
1452 | SDHCI_PCI_DEVICE(JMICRON, JMB38X_MMC, jmicron), | |
1453 | SDHCI_PCI_DEVICE(JMICRON, JMB388_SD, jmicron), | |
1454 | SDHCI_PCI_DEVICE(JMICRON, JMB388_ESD, jmicron), | |
1455 | SDHCI_PCI_DEVICE(SYSKONNECT, 8000, syskt), | |
1456 | SDHCI_PCI_DEVICE(VIA, 95D0, via), | |
1457 | SDHCI_PCI_DEVICE(REALTEK, 5250, rtsx), | |
1458 | SDHCI_PCI_DEVICE(INTEL, QRK_SD, intel_qrk), | |
1459 | SDHCI_PCI_DEVICE(INTEL, MRST_SD0, intel_mrst_hc0), | |
1460 | SDHCI_PCI_DEVICE(INTEL, MRST_SD1, intel_mrst_hc1_hc2), | |
1461 | SDHCI_PCI_DEVICE(INTEL, MRST_SD2, intel_mrst_hc1_hc2), | |
1462 | SDHCI_PCI_DEVICE(INTEL, MFD_SD, intel_mfd_sd), | |
1463 | SDHCI_PCI_DEVICE(INTEL, MFD_SDIO1, intel_mfd_sdio), | |
1464 | SDHCI_PCI_DEVICE(INTEL, MFD_SDIO2, intel_mfd_sdio), | |
1465 | SDHCI_PCI_DEVICE(INTEL, MFD_EMMC0, intel_mfd_emmc), | |
1466 | SDHCI_PCI_DEVICE(INTEL, MFD_EMMC1, intel_mfd_emmc), | |
1467 | SDHCI_PCI_DEVICE(INTEL, PCH_SDIO0, intel_pch_sdio), | |
1468 | SDHCI_PCI_DEVICE(INTEL, PCH_SDIO1, intel_pch_sdio), | |
1469 | SDHCI_PCI_DEVICE(INTEL, BYT_EMMC, intel_byt_emmc), | |
1470 | SDHCI_PCI_SUBDEVICE(INTEL, BYT_SDIO, NI, 7884, ni_byt_sdio), | |
1471 | SDHCI_PCI_DEVICE(INTEL, BYT_SDIO, intel_byt_sdio), | |
1472 | SDHCI_PCI_DEVICE(INTEL, BYT_SD, intel_byt_sd), | |
1473 | SDHCI_PCI_DEVICE(INTEL, BYT_EMMC2, intel_byt_emmc), | |
1474 | SDHCI_PCI_DEVICE(INTEL, BSW_EMMC, intel_byt_emmc), | |
1475 | SDHCI_PCI_DEVICE(INTEL, BSW_SDIO, intel_byt_sdio), | |
1476 | SDHCI_PCI_DEVICE(INTEL, BSW_SD, intel_byt_sd), | |
1477 | SDHCI_PCI_DEVICE(INTEL, CLV_SDIO0, intel_mfd_sd), | |
1478 | SDHCI_PCI_DEVICE(INTEL, CLV_SDIO1, intel_mfd_sdio), | |
1479 | SDHCI_PCI_DEVICE(INTEL, CLV_SDIO2, intel_mfd_sdio), | |
1480 | SDHCI_PCI_DEVICE(INTEL, CLV_EMMC0, intel_mfd_emmc), | |
1481 | SDHCI_PCI_DEVICE(INTEL, CLV_EMMC1, intel_mfd_emmc), | |
1482 | SDHCI_PCI_DEVICE(INTEL, MRFLD_MMC, intel_mrfld_mmc), | |
1483 | SDHCI_PCI_DEVICE(INTEL, SPT_EMMC, intel_byt_emmc), | |
1484 | SDHCI_PCI_DEVICE(INTEL, SPT_SDIO, intel_byt_sdio), | |
1485 | SDHCI_PCI_DEVICE(INTEL, SPT_SD, intel_byt_sd), | |
1486 | SDHCI_PCI_DEVICE(INTEL, DNV_EMMC, intel_byt_emmc), | |
cdaba732 | 1487 | SDHCI_PCI_DEVICE(INTEL, CDF_EMMC, intel_glk_emmc), |
c949c907 MK |
1488 | SDHCI_PCI_DEVICE(INTEL, BXT_EMMC, intel_byt_emmc), |
1489 | SDHCI_PCI_DEVICE(INTEL, BXT_SDIO, intel_byt_sdio), | |
1490 | SDHCI_PCI_DEVICE(INTEL, BXT_SD, intel_byt_sd), | |
1491 | SDHCI_PCI_DEVICE(INTEL, BXTM_EMMC, intel_byt_emmc), | |
1492 | SDHCI_PCI_DEVICE(INTEL, BXTM_SDIO, intel_byt_sdio), | |
1493 | SDHCI_PCI_DEVICE(INTEL, BXTM_SD, intel_byt_sd), | |
1494 | SDHCI_PCI_DEVICE(INTEL, APL_EMMC, intel_byt_emmc), | |
1495 | SDHCI_PCI_DEVICE(INTEL, APL_SDIO, intel_byt_sdio), | |
1496 | SDHCI_PCI_DEVICE(INTEL, APL_SD, intel_byt_sd), | |
bc55dcd8 | 1497 | SDHCI_PCI_DEVICE(INTEL, GLK_EMMC, intel_glk_emmc), |
c949c907 MK |
1498 | SDHCI_PCI_DEVICE(INTEL, GLK_SDIO, intel_byt_sdio), |
1499 | SDHCI_PCI_DEVICE(INTEL, GLK_SD, intel_byt_sd), | |
bc55dcd8 AH |
1500 | SDHCI_PCI_DEVICE(INTEL, CNP_EMMC, intel_glk_emmc), |
1501 | SDHCI_PCI_DEVICE(INTEL, CNP_SD, intel_byt_sd), | |
1502 | SDHCI_PCI_DEVICE(INTEL, CNPH_SD, intel_byt_sd), | |
5637ffad AH |
1503 | SDHCI_PCI_DEVICE(INTEL, ICP_EMMC, intel_glk_emmc), |
1504 | SDHCI_PCI_DEVICE(INTEL, ICP_SD, intel_byt_sd), | |
c949c907 MK |
1505 | SDHCI_PCI_DEVICE(O2, 8120, o2), |
1506 | SDHCI_PCI_DEVICE(O2, 8220, o2), | |
1507 | SDHCI_PCI_DEVICE(O2, 8221, o2), | |
1508 | SDHCI_PCI_DEVICE(O2, 8320, o2), | |
1509 | SDHCI_PCI_DEVICE(O2, 8321, o2), | |
1510 | SDHCI_PCI_DEVICE(O2, FUJIN2, o2), | |
1511 | SDHCI_PCI_DEVICE(O2, SDS0, o2), | |
1512 | SDHCI_PCI_DEVICE(O2, SDS1, o2), | |
1513 | SDHCI_PCI_DEVICE(O2, SEABIRD0, o2), | |
1514 | SDHCI_PCI_DEVICE(O2, SEABIRD1, o2), | |
d72d72cd | 1515 | SDHCI_PCI_DEVICE(ARASAN, PHY_EMMC, arasan), |
c949c907 MK |
1516 | SDHCI_PCI_DEVICE_CLASS(AMD, SYSTEM_SDHCI, PCI_CLASS_MASK, amd), |
1517 | /* Generic SD host controller */ | |
1518 | {PCI_DEVICE_CLASS(SYSTEM_SDHCI, PCI_CLASS_MASK)}, | |
b8c86fc5 PO |
1519 | { /* end: all zeroes */ }, |
1520 | }; | |
1521 | ||
1522 | MODULE_DEVICE_TABLE(pci, pci_ids); | |
1523 | ||
b8c86fc5 PO |
1524 | /*****************************************************************************\ |
1525 | * * | |
1526 | * SDHCI core callbacks * | |
1527 | * * | |
1528 | \*****************************************************************************/ | |
1529 | ||
d72d72cd | 1530 | int sdhci_pci_enable_dma(struct sdhci_host *host) |
b8c86fc5 PO |
1531 | { |
1532 | struct sdhci_pci_slot *slot; | |
1533 | struct pci_dev *pdev; | |
b8c86fc5 PO |
1534 | |
1535 | slot = sdhci_priv(host); | |
1536 | pdev = slot->chip->pdev; | |
1537 | ||
1538 | if (((pdev->class & 0xFFFF00) == (PCI_CLASS_SYSTEM_SDHCI << 8)) && | |
1539 | ((pdev->class & 0x0000FF) != PCI_SDHCI_IFDMA) && | |
a13abc7b | 1540 | (host->flags & SDHCI_USE_SDMA)) { |
b8c86fc5 PO |
1541 | dev_warn(&pdev->dev, "Will use DMA mode even though HW " |
1542 | "doesn't fully claim to support it.\n"); | |
1543 | } | |
1544 | ||
b8c86fc5 PO |
1545 | pci_set_master(pdev); |
1546 | ||
1547 | return 0; | |
1548 | } | |
1549 | ||
c9faff6c | 1550 | static void sdhci_pci_gpio_hw_reset(struct sdhci_host *host) |
0f201655 AH |
1551 | { |
1552 | struct sdhci_pci_slot *slot = sdhci_priv(host); | |
1553 | int rst_n_gpio = slot->rst_n_gpio; | |
1554 | ||
1555 | if (!gpio_is_valid(rst_n_gpio)) | |
1556 | return; | |
1557 | gpio_set_value_cansleep(rst_n_gpio, 0); | |
1558 | /* For eMMC, minimum is 1us but give it 10us for good measure */ | |
1559 | udelay(10); | |
1560 | gpio_set_value_cansleep(rst_n_gpio, 1); | |
1561 | /* For eMMC, minimum is 200us but give it 300us for good measure */ | |
1562 | usleep_range(300, 1000); | |
1563 | } | |
1564 | ||
c9faff6c AH |
1565 | static void sdhci_pci_hw_reset(struct sdhci_host *host) |
1566 | { | |
1567 | struct sdhci_pci_slot *slot = sdhci_priv(host); | |
1568 | ||
1569 | if (slot->hw_reset) | |
1570 | slot->hw_reset(host); | |
1571 | } | |
1572 | ||
c915568d | 1573 | static const struct sdhci_ops sdhci_pci_ops = { |
1771059c | 1574 | .set_clock = sdhci_set_clock, |
b8c86fc5 | 1575 | .enable_dma = sdhci_pci_enable_dma, |
adc16398 | 1576 | .set_bus_width = sdhci_set_bus_width, |
03231f9b | 1577 | .reset = sdhci_reset, |
96d7b78c | 1578 | .set_uhs_signaling = sdhci_set_uhs_signaling, |
0f201655 | 1579 | .hw_reset = sdhci_pci_hw_reset, |
b8c86fc5 PO |
1580 | }; |
1581 | ||
1582 | /*****************************************************************************\ | |
1583 | * * | |
1584 | * Suspend/resume * | |
1585 | * * | |
1586 | \*****************************************************************************/ | |
1587 | ||
f9900f15 | 1588 | #ifdef CONFIG_PM_SLEEP |
29495aa0 | 1589 | static int sdhci_pci_suspend(struct device *dev) |
b8c86fc5 | 1590 | { |
29495aa0 | 1591 | struct pci_dev *pdev = to_pci_dev(dev); |
30cf2803 | 1592 | struct sdhci_pci_chip *chip = pci_get_drvdata(pdev); |
b8c86fc5 | 1593 | |
b8c86fc5 PO |
1594 | if (!chip) |
1595 | return 0; | |
1596 | ||
30cf2803 AH |
1597 | if (chip->fixes && chip->fixes->suspend) |
1598 | return chip->fixes->suspend(chip); | |
b8c86fc5 | 1599 | |
30cf2803 | 1600 | return sdhci_pci_suspend_host(chip); |
b8c86fc5 PO |
1601 | } |
1602 | ||
29495aa0 | 1603 | static int sdhci_pci_resume(struct device *dev) |
b8c86fc5 | 1604 | { |
29495aa0 | 1605 | struct pci_dev *pdev = to_pci_dev(dev); |
30cf2803 | 1606 | struct sdhci_pci_chip *chip = pci_get_drvdata(pdev); |
b8c86fc5 | 1607 | |
b8c86fc5 PO |
1608 | if (!chip) |
1609 | return 0; | |
1610 | ||
30cf2803 AH |
1611 | if (chip->fixes && chip->fixes->resume) |
1612 | return chip->fixes->resume(chip); | |
b8c86fc5 | 1613 | |
30cf2803 | 1614 | return sdhci_pci_resume_host(chip); |
b8c86fc5 | 1615 | } |
f9900f15 | 1616 | #endif |
b8c86fc5 | 1617 | |
f9900f15 | 1618 | #ifdef CONFIG_PM |
66fd8ad5 AH |
1619 | static int sdhci_pci_runtime_suspend(struct device *dev) |
1620 | { | |
923a231c | 1621 | struct pci_dev *pdev = to_pci_dev(dev); |
966d696a | 1622 | struct sdhci_pci_chip *chip = pci_get_drvdata(pdev); |
66fd8ad5 | 1623 | |
66fd8ad5 AH |
1624 | if (!chip) |
1625 | return 0; | |
1626 | ||
966d696a AH |
1627 | if (chip->fixes && chip->fixes->runtime_suspend) |
1628 | return chip->fixes->runtime_suspend(chip); | |
66fd8ad5 | 1629 | |
966d696a | 1630 | return sdhci_pci_runtime_suspend_host(chip); |
66fd8ad5 AH |
1631 | } |
1632 | ||
1633 | static int sdhci_pci_runtime_resume(struct device *dev) | |
1634 | { | |
923a231c | 1635 | struct pci_dev *pdev = to_pci_dev(dev); |
966d696a | 1636 | struct sdhci_pci_chip *chip = pci_get_drvdata(pdev); |
66fd8ad5 | 1637 | |
66fd8ad5 AH |
1638 | if (!chip) |
1639 | return 0; | |
1640 | ||
966d696a AH |
1641 | if (chip->fixes && chip->fixes->runtime_resume) |
1642 | return chip->fixes->runtime_resume(chip); | |
66fd8ad5 | 1643 | |
966d696a | 1644 | return sdhci_pci_runtime_resume_host(chip); |
66fd8ad5 | 1645 | } |
f9900f15 | 1646 | #endif |
66fd8ad5 AH |
1647 | |
1648 | static const struct dev_pm_ops sdhci_pci_pm_ops = { | |
f9900f15 | 1649 | SET_SYSTEM_SLEEP_PM_OPS(sdhci_pci_suspend, sdhci_pci_resume) |
f3a92b1a | 1650 | SET_RUNTIME_PM_OPS(sdhci_pci_runtime_suspend, |
106276bb | 1651 | sdhci_pci_runtime_resume, NULL) |
66fd8ad5 AH |
1652 | }; |
1653 | ||
b8c86fc5 PO |
1654 | /*****************************************************************************\ |
1655 | * * | |
1656 | * Device probing/removal * | |
1657 | * * | |
1658 | \*****************************************************************************/ | |
1659 | ||
c3be1efd | 1660 | static struct sdhci_pci_slot *sdhci_pci_probe_slot( |
52c506f0 AH |
1661 | struct pci_dev *pdev, struct sdhci_pci_chip *chip, int first_bar, |
1662 | int slotno) | |
b8c86fc5 PO |
1663 | { |
1664 | struct sdhci_pci_slot *slot; | |
1665 | struct sdhci_host *host; | |
52c506f0 | 1666 | int ret, bar = first_bar + slotno; |
ac9f67b5 | 1667 | size_t priv_size = chip->fixes ? chip->fixes->priv_size : 0; |
b8c86fc5 PO |
1668 | |
1669 | if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) { | |
1670 | dev_err(&pdev->dev, "BAR %d is not iomem. Aborting.\n", bar); | |
1671 | return ERR_PTR(-ENODEV); | |
1672 | } | |
1673 | ||
90b3e6c5 | 1674 | if (pci_resource_len(pdev, bar) < 0x100) { |
b8c86fc5 PO |
1675 | dev_err(&pdev->dev, "Invalid iomem size. You may " |
1676 | "experience problems.\n"); | |
1677 | } | |
1678 | ||
1679 | if ((pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) { | |
1680 | dev_err(&pdev->dev, "Vendor specific interface. Aborting.\n"); | |
1681 | return ERR_PTR(-ENODEV); | |
1682 | } | |
1683 | ||
1684 | if ((pdev->class & 0x0000FF) > PCI_SDHCI_IFVENDOR) { | |
1685 | dev_err(&pdev->dev, "Unknown interface. Aborting.\n"); | |
1686 | return ERR_PTR(-ENODEV); | |
1687 | } | |
1688 | ||
ac9f67b5 | 1689 | host = sdhci_alloc_host(&pdev->dev, sizeof(*slot) + priv_size); |
b8c86fc5 | 1690 | if (IS_ERR(host)) { |
c60a32cd | 1691 | dev_err(&pdev->dev, "cannot allocate host\n"); |
dc0fd7b5 | 1692 | return ERR_CAST(host); |
b8c86fc5 PO |
1693 | } |
1694 | ||
1695 | slot = sdhci_priv(host); | |
1696 | ||
1697 | slot->chip = chip; | |
1698 | slot->host = host; | |
0f201655 | 1699 | slot->rst_n_gpio = -EINVAL; |
c5e027a4 | 1700 | slot->cd_gpio = -EINVAL; |
ff59c520 | 1701 | slot->cd_idx = -1; |
b8c86fc5 | 1702 | |
52c506f0 AH |
1703 | /* Retrieve platform data if there is any */ |
1704 | if (*sdhci_pci_get_data) | |
1705 | slot->data = sdhci_pci_get_data(pdev, slotno); | |
1706 | ||
1707 | if (slot->data) { | |
1708 | if (slot->data->setup) { | |
1709 | ret = slot->data->setup(slot->data); | |
1710 | if (ret) { | |
1711 | dev_err(&pdev->dev, "platform setup failed\n"); | |
1712 | goto free; | |
1713 | } | |
1714 | } | |
c5e027a4 AH |
1715 | slot->rst_n_gpio = slot->data->rst_n_gpio; |
1716 | slot->cd_gpio = slot->data->cd_gpio; | |
52c506f0 AH |
1717 | } |
1718 | ||
b8c86fc5 | 1719 | host->hw_name = "PCI"; |
6bc09063 AH |
1720 | host->ops = chip->fixes && chip->fixes->ops ? |
1721 | chip->fixes->ops : | |
1722 | &sdhci_pci_ops; | |
b8c86fc5 | 1723 | host->quirks = chip->quirks; |
f3c55a7b | 1724 | host->quirks2 = chip->quirks2; |
b8c86fc5 PO |
1725 | |
1726 | host->irq = pdev->irq; | |
1727 | ||
c10bc372 | 1728 | ret = pcim_iomap_regions(pdev, BIT(bar), mmc_hostname(host->mmc)); |
b8c86fc5 PO |
1729 | if (ret) { |
1730 | dev_err(&pdev->dev, "cannot request region\n"); | |
52c506f0 | 1731 | goto cleanup; |
b8c86fc5 PO |
1732 | } |
1733 | ||
c10bc372 | 1734 | host->ioaddr = pcim_iomap_table(pdev)[bar]; |
b8c86fc5 | 1735 | |
4489428a PO |
1736 | if (chip->fixes && chip->fixes->probe_slot) { |
1737 | ret = chip->fixes->probe_slot(slot); | |
1738 | if (ret) | |
c10bc372 | 1739 | goto cleanup; |
4489428a PO |
1740 | } |
1741 | ||
c5e027a4 | 1742 | if (gpio_is_valid(slot->rst_n_gpio)) { |
c10bc372 | 1743 | if (!devm_gpio_request(&pdev->dev, slot->rst_n_gpio, "eMMC_reset")) { |
c5e027a4 AH |
1744 | gpio_direction_output(slot->rst_n_gpio, 1); |
1745 | slot->host->mmc->caps |= MMC_CAP_HW_RESET; | |
c9faff6c | 1746 | slot->hw_reset = sdhci_pci_gpio_hw_reset; |
c5e027a4 AH |
1747 | } else { |
1748 | dev_warn(&pdev->dev, "failed to request rst_n_gpio\n"); | |
1749 | slot->rst_n_gpio = -EINVAL; | |
1750 | } | |
1751 | } | |
1752 | ||
e92cc35d | 1753 | host->mmc->pm_caps = MMC_PM_KEEP_POWER; |
eed222ac | 1754 | host->mmc->slotno = slotno; |
a08b17be | 1755 | host->mmc->caps2 |= MMC_CAP2_NO_PRESCAN_POWERUP; |
2f4cbb3d | 1756 | |
e92cc35d AH |
1757 | if (device_can_wakeup(&pdev->dev)) |
1758 | host->mmc->pm_caps |= MMC_PM_WAKE_SDIO_IRQ; | |
1759 | ||
d56ee1ff AH |
1760 | if (host->mmc->caps & MMC_CAP_CD_WAKE) |
1761 | device_init_wakeup(&pdev->dev, true); | |
1762 | ||
8f743d03 | 1763 | if (slot->cd_idx >= 0) { |
6ac9b837 | 1764 | ret = mmc_gpiod_request_cd(host->mmc, NULL, slot->cd_idx, |
8f743d03 DB |
1765 | slot->cd_override_level, 0, NULL); |
1766 | if (ret == -EPROBE_DEFER) | |
1767 | goto remove; | |
1768 | ||
1769 | if (ret) { | |
1770 | dev_warn(&pdev->dev, "failed to setup card detect gpio\n"); | |
1771 | slot->cd_idx = -1; | |
1772 | } | |
ff59c520 AH |
1773 | } |
1774 | ||
61c951de AH |
1775 | if (chip->fixes && chip->fixes->add_host) |
1776 | ret = chip->fixes->add_host(slot); | |
1777 | else | |
1778 | ret = sdhci_add_host(host); | |
b8c86fc5 | 1779 | if (ret) |
4489428a | 1780 | goto remove; |
b8c86fc5 | 1781 | |
c5e027a4 AH |
1782 | sdhci_pci_add_own_cd(slot); |
1783 | ||
77a0122e AH |
1784 | /* |
1785 | * Check if the chip needs a separate GPIO for card detect to wake up | |
1786 | * from runtime suspend. If it is not there, don't allow runtime PM. | |
1787 | * Note sdhci_pci_add_own_cd() sets slot->cd_gpio to -EINVAL on failure. | |
1788 | */ | |
945be38c | 1789 | if (chip->fixes && chip->fixes->own_cd_for_runtime_pm && |
ff59c520 | 1790 | !gpio_is_valid(slot->cd_gpio) && slot->cd_idx < 0) |
77a0122e AH |
1791 | chip->allow_runtime_pm = false; |
1792 | ||
b8c86fc5 PO |
1793 | return slot; |
1794 | ||
4489428a PO |
1795 | remove: |
1796 | if (chip->fixes && chip->fixes->remove_slot) | |
1e72859e | 1797 | chip->fixes->remove_slot(slot, 0); |
4489428a | 1798 | |
52c506f0 AH |
1799 | cleanup: |
1800 | if (slot->data && slot->data->cleanup) | |
1801 | slot->data->cleanup(slot->data); | |
1802 | ||
c60a32cd | 1803 | free: |
b8c86fc5 PO |
1804 | sdhci_free_host(host); |
1805 | ||
1806 | return ERR_PTR(ret); | |
1807 | } | |
1808 | ||
1809 | static void sdhci_pci_remove_slot(struct sdhci_pci_slot *slot) | |
1810 | { | |
1e72859e PO |
1811 | int dead; |
1812 | u32 scratch; | |
1813 | ||
c5e027a4 AH |
1814 | sdhci_pci_remove_own_cd(slot); |
1815 | ||
1e72859e PO |
1816 | dead = 0; |
1817 | scratch = readl(slot->host->ioaddr + SDHCI_INT_STATUS); | |
1818 | if (scratch == (u32)-1) | |
1819 | dead = 1; | |
1820 | ||
1821 | sdhci_remove_host(slot->host, dead); | |
4489428a PO |
1822 | |
1823 | if (slot->chip->fixes && slot->chip->fixes->remove_slot) | |
1e72859e | 1824 | slot->chip->fixes->remove_slot(slot, dead); |
4489428a | 1825 | |
52c506f0 AH |
1826 | if (slot->data && slot->data->cleanup) |
1827 | slot->data->cleanup(slot->data); | |
1828 | ||
b8c86fc5 PO |
1829 | sdhci_free_host(slot->host); |
1830 | } | |
1831 | ||
c3be1efd | 1832 | static void sdhci_pci_runtime_pm_allow(struct device *dev) |
66fd8ad5 | 1833 | { |
00884b61 | 1834 | pm_suspend_ignore_children(dev, 1); |
66fd8ad5 AH |
1835 | pm_runtime_set_autosuspend_delay(dev, 50); |
1836 | pm_runtime_use_autosuspend(dev); | |
00884b61 AH |
1837 | pm_runtime_allow(dev); |
1838 | /* Stay active until mmc core scans for a card */ | |
1839 | pm_runtime_put_noidle(dev); | |
66fd8ad5 AH |
1840 | } |
1841 | ||
6e0ee714 | 1842 | static void sdhci_pci_runtime_pm_forbid(struct device *dev) |
66fd8ad5 AH |
1843 | { |
1844 | pm_runtime_forbid(dev); | |
1845 | pm_runtime_get_noresume(dev); | |
1846 | } | |
1847 | ||
c3be1efd | 1848 | static int sdhci_pci_probe(struct pci_dev *pdev, |
b8c86fc5 PO |
1849 | const struct pci_device_id *ent) |
1850 | { | |
1851 | struct sdhci_pci_chip *chip; | |
1852 | struct sdhci_pci_slot *slot; | |
1853 | ||
cf5e23e1 | 1854 | u8 slots, first_bar; |
b8c86fc5 PO |
1855 | int ret, i; |
1856 | ||
1857 | BUG_ON(pdev == NULL); | |
1858 | BUG_ON(ent == NULL); | |
1859 | ||
b8c86fc5 | 1860 | dev_info(&pdev->dev, "SDHCI controller found [%04x:%04x] (rev %x)\n", |
cf5e23e1 | 1861 | (int)pdev->vendor, (int)pdev->device, (int)pdev->revision); |
b8c86fc5 PO |
1862 | |
1863 | ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &slots); | |
1864 | if (ret) | |
1865 | return ret; | |
1866 | ||
1867 | slots = PCI_SLOT_INFO_SLOTS(slots) + 1; | |
1868 | dev_dbg(&pdev->dev, "found %d slot(s)\n", slots); | |
1869 | if (slots == 0) | |
1870 | return -ENODEV; | |
1871 | ||
1872 | BUG_ON(slots > MAX_SLOTS); | |
1873 | ||
1874 | ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &first_bar); | |
1875 | if (ret) | |
1876 | return ret; | |
1877 | ||
1878 | first_bar &= PCI_SLOT_INFO_FIRST_BAR_MASK; | |
1879 | ||
1880 | if (first_bar > 5) { | |
1881 | dev_err(&pdev->dev, "Invalid first BAR. Aborting.\n"); | |
1882 | return -ENODEV; | |
1883 | } | |
1884 | ||
52ac7acf | 1885 | ret = pcim_enable_device(pdev); |
b8c86fc5 PO |
1886 | if (ret) |
1887 | return ret; | |
1888 | ||
52ac7acf AS |
1889 | chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL); |
1890 | if (!chip) | |
1891 | return -ENOMEM; | |
b8c86fc5 PO |
1892 | |
1893 | chip->pdev = pdev; | |
b177bc91 | 1894 | chip->fixes = (const struct sdhci_pci_fixes *)ent->driver_data; |
c43fd774 | 1895 | if (chip->fixes) { |
22606405 | 1896 | chip->quirks = chip->fixes->quirks; |
f3c55a7b | 1897 | chip->quirks2 = chip->fixes->quirks2; |
c43fd774 AH |
1898 | chip->allow_runtime_pm = chip->fixes->allow_runtime_pm; |
1899 | } | |
b8c86fc5 | 1900 | chip->num_slots = slots; |
d38dcad4 AH |
1901 | chip->pm_retune = true; |
1902 | chip->rpm_retune = true; | |
b8c86fc5 PO |
1903 | |
1904 | pci_set_drvdata(pdev, chip); | |
1905 | ||
22606405 PO |
1906 | if (chip->fixes && chip->fixes->probe) { |
1907 | ret = chip->fixes->probe(chip); | |
1908 | if (ret) | |
52ac7acf | 1909 | return ret; |
22606405 PO |
1910 | } |
1911 | ||
225d85fe AC |
1912 | slots = chip->num_slots; /* Quirk may have changed this */ |
1913 | ||
b177bc91 | 1914 | for (i = 0; i < slots; i++) { |
52c506f0 | 1915 | slot = sdhci_pci_probe_slot(pdev, chip, first_bar, i); |
b8c86fc5 | 1916 | if (IS_ERR(slot)) { |
b177bc91 | 1917 | for (i--; i >= 0; i--) |
b8c86fc5 | 1918 | sdhci_pci_remove_slot(chip->slots[i]); |
52ac7acf | 1919 | return PTR_ERR(slot); |
b8c86fc5 PO |
1920 | } |
1921 | ||
1922 | chip->slots[i] = slot; | |
1923 | } | |
1924 | ||
c43fd774 AH |
1925 | if (chip->allow_runtime_pm) |
1926 | sdhci_pci_runtime_pm_allow(&pdev->dev); | |
66fd8ad5 | 1927 | |
b8c86fc5 | 1928 | return 0; |
b8c86fc5 PO |
1929 | } |
1930 | ||
6e0ee714 | 1931 | static void sdhci_pci_remove(struct pci_dev *pdev) |
b8c86fc5 PO |
1932 | { |
1933 | int i; | |
52ac7acf | 1934 | struct sdhci_pci_chip *chip = pci_get_drvdata(pdev); |
c43fd774 | 1935 | |
52ac7acf AS |
1936 | if (chip->allow_runtime_pm) |
1937 | sdhci_pci_runtime_pm_forbid(&pdev->dev); | |
b8c86fc5 | 1938 | |
52ac7acf AS |
1939 | for (i = 0; i < chip->num_slots; i++) |
1940 | sdhci_pci_remove_slot(chip->slots[i]); | |
b8c86fc5 PO |
1941 | } |
1942 | ||
1943 | static struct pci_driver sdhci_driver = { | |
b177bc91 | 1944 | .name = "sdhci-pci", |
b8c86fc5 | 1945 | .id_table = pci_ids, |
b177bc91 | 1946 | .probe = sdhci_pci_probe, |
0433c143 | 1947 | .remove = sdhci_pci_remove, |
66fd8ad5 AH |
1948 | .driver = { |
1949 | .pm = &sdhci_pci_pm_ops | |
1950 | }, | |
b8c86fc5 PO |
1951 | }; |
1952 | ||
acc69646 | 1953 | module_pci_driver(sdhci_driver); |
b8c86fc5 | 1954 | |
32710e8f | 1955 | MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>"); |
b8c86fc5 PO |
1956 | MODULE_DESCRIPTION("Secure Digital Host Controller Interface PCI driver"); |
1957 | MODULE_LICENSE("GPL"); |