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mmc: tmio, renesas_sdhi: Remove unneeded NULL check
[mirror_ubuntu-eoan-kernel.git] / drivers / mmc / host / sdhci-pci-core.c
CommitLineData
b8c86fc5
PO		 1/* linux/drivers/mmc/host/sdhci-pci.c - SDHCI on PCI bus interface
2 *
3 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or (at
8 * your option) any later version.
9 *
10 * Thanks to the following companies for their support:
11 *
12 * - JMicron (hardware and technical support)
13 */
14
a72016a4 15#include <linux/string.h>
b8c86fc5
PO		 16#include <linux/delay.h>
17#include <linux/highmem.h>
88b47679 18#include <linux/module.h>
b8c86fc5
PO		 19#include <linux/pci.h>
20#include <linux/dma-mapping.h>
5a0e3ad6 21#include <linux/slab.h>
ccc92c23 22#include <linux/device.h>
b8c86fc5 23#include <linux/mmc/host.h>
e1bfad6d 24#include <linux/mmc/mmc.h>
b177bc91
AP		 25#include <linux/scatterlist.h>
26#include <linux/io.h>
0f201655 27#include <linux/gpio.h>
66fd8ad5 28#include <linux/pm_runtime.h>
ff59c520 29#include <linux/mmc/slot-gpio.h>
52c506f0 30#include <linux/mmc/sdhci-pci-data.h>
3f23df72 31#include <linux/acpi.h>
b8c86fc5 32
8ee82bda
AH		 33#include "cqhci.h"
34
b8c86fc5 35#include "sdhci.h"
522624f9 36#include "sdhci-pci.h"
22606405 37
fee686b7 38static void sdhci_pci_hw_reset(struct sdhci_host *host);
fee686b7 39
30cf2803
AH		 40#ifdef CONFIG_PM_SLEEP
41static int __sdhci_pci_suspend_host(struct sdhci_pci_chip *chip)
42{
43 int i, ret;
44
45 for (i = 0; i < chip->num_slots; i++) {
46 struct sdhci_pci_slot *slot = chip->slots[i];
47 struct sdhci_host *host;
48
49 if (!slot)
50 continue;
51
52 host = slot->host;
53
54 if (chip->pm_retune && host->tuning_mode != SDHCI_TUNING_MODE_3)
55 mmc_retune_needed(host->mmc);
56
57 ret = sdhci_suspend_host(host);
58 if (ret)
59 goto err_pci_suspend;
60
61 if (host->mmc->pm_flags & MMC_PM_WAKE_SDIO_IRQ)
62 sdhci_enable_irq_wakeups(host);
63 }
64
65 return 0;
66
67err_pci_suspend:
68 while (--i >= 0)
69 sdhci_resume_host(chip->slots[i]->host);
70 return ret;
71}
72
73static int sdhci_pci_init_wakeup(struct sdhci_pci_chip *chip)
74{
75 mmc_pm_flag_t pm_flags = 0;
76 int i;
77
78 for (i = 0; i < chip->num_slots; i++) {
79 struct sdhci_pci_slot *slot = chip->slots[i];
80
81 if (slot)
82 pm_flags |= slot->host->mmc->pm_flags;
83 }
84
85 return device_init_wakeup(&chip->pdev->dev,
86 (pm_flags & MMC_PM_KEEP_POWER) &&
87 (pm_flags & MMC_PM_WAKE_SDIO_IRQ));
88}
89
90static int sdhci_pci_suspend_host(struct sdhci_pci_chip *chip)
91{
92 int ret;
93
94 ret = __sdhci_pci_suspend_host(chip);
95 if (ret)
96 return ret;
97
98 sdhci_pci_init_wakeup(chip);
99
100 return 0;
101}
102
103int sdhci_pci_resume_host(struct sdhci_pci_chip *chip)
104{
105 struct sdhci_pci_slot *slot;
106 int i, ret;
107
108 for (i = 0; i < chip->num_slots; i++) {
109 slot = chip->slots[i];
110 if (!slot)
111 continue;
112
113 ret = sdhci_resume_host(slot->host);
114 if (ret)
115 return ret;
116 }
117
118 return 0;
119}
8ee82bda
AH		 120
121static int sdhci_cqhci_suspend(struct sdhci_pci_chip *chip)
122{
123 int ret;
124
125 ret = cqhci_suspend(chip->slots[0]->host->mmc);
126 if (ret)
127 return ret;
128
129 return sdhci_pci_suspend_host(chip);
130}
131
132static int sdhci_cqhci_resume(struct sdhci_pci_chip *chip)
133{
134 int ret;
135
136 ret = sdhci_pci_resume_host(chip);
137 if (ret)
138 return ret;
139
140 return cqhci_resume(chip->slots[0]->host->mmc);
141}
30cf2803
AH		 142#endif
143
966d696a
AH		 144#ifdef CONFIG_PM
145static int sdhci_pci_runtime_suspend_host(struct sdhci_pci_chip *chip)
146{
147 struct sdhci_pci_slot *slot;
148 struct sdhci_host *host;
149 int i, ret;
150
151 for (i = 0; i < chip->num_slots; i++) {
152 slot = chip->slots[i];
153 if (!slot)
154 continue;
155
156 host = slot->host;
157
158 ret = sdhci_runtime_suspend_host(host);
159 if (ret)
160 goto err_pci_runtime_suspend;
161
162 if (chip->rpm_retune &&
163 host->tuning_mode != SDHCI_TUNING_MODE_3)
164 mmc_retune_needed(host->mmc);
165 }
166
167 return 0;
168
169err_pci_runtime_suspend:
170 while (--i >= 0)
171 sdhci_runtime_resume_host(chip->slots[i]->host);
172 return ret;
173}
174
175static int sdhci_pci_runtime_resume_host(struct sdhci_pci_chip *chip)
176{
177 struct sdhci_pci_slot *slot;
178 int i, ret;
179
180 for (i = 0; i < chip->num_slots; i++) {
181 slot = chip->slots[i];
182 if (!slot)
183 continue;
184
185 ret = sdhci_runtime_resume_host(slot->host);
186 if (ret)
187 return ret;
188 }
189
190 return 0;
191}
8ee82bda
AH		 192
193static int sdhci_cqhci_runtime_suspend(struct sdhci_pci_chip *chip)
194{
195 int ret;
196
197 ret = cqhci_suspend(chip->slots[0]->host->mmc);
198 if (ret)
199 return ret;
200
201 return sdhci_pci_runtime_suspend_host(chip);
202}
203
204static int sdhci_cqhci_runtime_resume(struct sdhci_pci_chip *chip)
205{
206 int ret;
207
208 ret = sdhci_pci_runtime_resume_host(chip);
209 if (ret)
210 return ret;
211
212 return cqhci_resume(chip->slots[0]->host->mmc);
213}
966d696a
AH		 214#endif
215
8ee82bda
AH		 216static u32 sdhci_cqhci_irq(struct sdhci_host *host, u32 intmask)
217{
218 int cmd_error = 0;
219 int data_error = 0;
220
221 if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error))
222 return intmask;
223
224 cqhci_irq(host->mmc, intmask, cmd_error, data_error);
225
226 return 0;
227}
228
229static void sdhci_pci_dumpregs(struct mmc_host *mmc)
230{
231 sdhci_dumpregs(mmc_priv(mmc));
232}
233
22606405
PO		 234/*****************************************************************************\
235 * *
236 * Hardware specific quirk handling *
237 * *
238\*****************************************************************************/
239
240static int ricoh_probe(struct sdhci_pci_chip *chip)
241{
c99436fb
CB		 242 if (chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG ||
243 chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SONY)
22606405 244 chip->quirks |= SDHCI_QUIRK_NO_CARD_NO_RESET;
ccc92c23
ML		 245 return 0;
246}
247
248static int ricoh_mmc_probe_slot(struct sdhci_pci_slot *slot)
249{
250 slot->host->caps =
251 ((0x21 << SDHCI_TIMEOUT_CLK_SHIFT)
252 & SDHCI_TIMEOUT_CLK_MASK) |
22606405 253
ccc92c23
ML		 254 ((0x21 << SDHCI_CLOCK_BASE_SHIFT)
255 & SDHCI_CLOCK_BASE_MASK) |
256
257 SDHCI_TIMEOUT_CLK_UNIT |
258 SDHCI_CAN_VDD_330 |
1a1f1f04 259 SDHCI_CAN_DO_HISPD |
ccc92c23
ML		 260 SDHCI_CAN_DO_SDMA;
261 return 0;
262}
263
b7813f0f 264#ifdef CONFIG_PM_SLEEP
ccc92c23
ML		 265static int ricoh_mmc_resume(struct sdhci_pci_chip *chip)
266{
267 /* Apply a delay to allow controller to settle */
268 /* Otherwise it becomes confused if card state changed
269 during suspend */
270 msleep(500);
30cf2803 271 return sdhci_pci_resume_host(chip);
22606405 272}
b7813f0f 273#endif
22606405
PO		 274
275static const struct sdhci_pci_fixes sdhci_ricoh = {
276 .probe = ricoh_probe,
84938294
VK		 277 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR |
278 SDHCI_QUIRK_FORCE_DMA |
279 SDHCI_QUIRK_CLOCK_BEFORE_RESET,
22606405
PO		 280};
281
ccc92c23
ML		 282static const struct sdhci_pci_fixes sdhci_ricoh_mmc = {
283 .probe_slot = ricoh_mmc_probe_slot,
b7813f0f 284#ifdef CONFIG_PM_SLEEP
ccc92c23 285 .resume = ricoh_mmc_resume,
b7813f0f 286#endif
ccc92c23
ML		 287 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR |
288 SDHCI_QUIRK_CLOCK_BEFORE_RESET |
289 SDHCI_QUIRK_NO_CARD_NO_RESET |
290 SDHCI_QUIRK_MISSING_CAPS
291};
292
22606405
PO		 293static const struct sdhci_pci_fixes sdhci_ene_712 = {
294 .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE |
295 SDHCI_QUIRK_BROKEN_DMA,
296};
297
298static const struct sdhci_pci_fixes sdhci_ene_714 = {
299 .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE |
300 SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS |
301 SDHCI_QUIRK_BROKEN_DMA,
302};
303
304static const struct sdhci_pci_fixes sdhci_cafe = {
305 .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER |
a0874897 306 SDHCI_QUIRK_NO_BUSY_IRQ |
55fc05b7 307 SDHCI_QUIRK_BROKEN_CARD_DETECTION |
ee53ab5d 308 SDHCI_QUIRK_BROKEN_TIMEOUT_VAL,
22606405
PO		 309};
310
43e968ce
DB		 311static const struct sdhci_pci_fixes sdhci_intel_qrk = {
312 .quirks = SDHCI_QUIRK_NO_HISPD_BIT,
313};
314
68077b02
ML		 315static int mrst_hc_probe_slot(struct sdhci_pci_slot *slot)
316{
317 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA;
318 return 0;
319}
320
f9ee3eab
AC		 321/*
322 * ADMA operation is disabled for Moorestown platform due to
323 * hardware bugs.
324 */
35ac6f08 325static int mrst_hc_probe(struct sdhci_pci_chip *chip)
f9ee3eab
AC		 326{
327 /*
35ac6f08
JP		 328 * slots number is fixed here for MRST as SDIO3/5 are never used and
329 * have hardware bugs.
f9ee3eab
AC		 330 */
331 chip->num_slots = 1;
332 return 0;
333}
334
296e0b03
AS		 335static int pch_hc_probe_slot(struct sdhci_pci_slot *slot)
336{
337 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA;
338 return 0;
339}
340
162d6f98 341#ifdef CONFIG_PM
66fd8ad5 342
c5e027a4 343static irqreturn_t sdhci_pci_sd_cd(int irq, void *dev_id)
66fd8ad5
AH		 344{
345 struct sdhci_pci_slot *slot = dev_id;
346 struct sdhci_host *host = slot->host;
347
348 mmc_detect_change(host->mmc, msecs_to_jiffies(200));
349 return IRQ_HANDLED;
350}
351
c5e027a4 352static void sdhci_pci_add_own_cd(struct sdhci_pci_slot *slot)
66fd8ad5 353{
c5e027a4 354 int err, irq, gpio = slot->cd_gpio;
66fd8ad5
AH		 355
356 slot->cd_gpio = -EINVAL;
357 slot->cd_irq = -EINVAL;
358
c5e027a4
AH		 359 if (!gpio_is_valid(gpio))
360 return;
361
c10bc372 362 err = devm_gpio_request(&slot->chip->pdev->dev, gpio, "sd_cd");
66fd8ad5
AH		 363 if (err < 0)
364 goto out;
365
366 err = gpio_direction_input(gpio);
367 if (err < 0)
368 goto out_free;
369
370 irq = gpio_to_irq(gpio);
371 if (irq < 0)
372 goto out_free;
373
c5e027a4 374 err = request_irq(irq, sdhci_pci_sd_cd, IRQF_TRIGGER_RISING |
66fd8ad5
AH		 375 IRQF_TRIGGER_FALLING, "sd_cd", slot);
376 if (err)
377 goto out_free;
378
379 slot->cd_gpio = gpio;
380 slot->cd_irq = irq;
66fd8ad5 381
c5e027a4 382 return;
66fd8ad5
AH		 383
384out_free:
c10bc372 385 devm_gpio_free(&slot->chip->pdev->dev, gpio);
66fd8ad5
AH		 386out:
387 dev_warn(&slot->chip->pdev->dev, "failed to setup card detect wake up\n");
66fd8ad5
AH		 388}
389
c5e027a4 390static void sdhci_pci_remove_own_cd(struct sdhci_pci_slot *slot)
66fd8ad5
AH		 391{
392 if (slot->cd_irq >= 0)
393 free_irq(slot->cd_irq, slot);
66fd8ad5
AH		 394}
395
396#else
397
c5e027a4
AH		 398static inline void sdhci_pci_add_own_cd(struct sdhci_pci_slot *slot)
399{
400}
401
402static inline void sdhci_pci_remove_own_cd(struct sdhci_pci_slot *slot)
403{
404}
66fd8ad5
AH		 405
406#endif
407
0d013bcf
AH		 408static int mfd_emmc_probe_slot(struct sdhci_pci_slot *slot)
409{
66fd8ad5 410 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE;
d2a47176 411 slot->host->mmc->caps2 |= MMC_CAP2_BOOTPART_NOACC;
0d013bcf
AH		 412 return 0;
413}
414
93933508
AH		 415static int mfd_sdio_probe_slot(struct sdhci_pci_slot *slot)
416{
012e4671 417 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE;
93933508
AH		 418 return 0;
419}
420
f9ee3eab
AC		 421static const struct sdhci_pci_fixes sdhci_intel_mrst_hc0 = {
422 .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT,
68077b02 423 .probe_slot = mrst_hc_probe_slot,
f9ee3eab
AC		 424};
425
35ac6f08 426static const struct sdhci_pci_fixes sdhci_intel_mrst_hc1_hc2 = {
f9ee3eab 427 .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT,
35ac6f08 428 .probe = mrst_hc_probe,
f9ee3eab
AC		 429};
430
29229052
XS		 431static const struct sdhci_pci_fixes sdhci_intel_mfd_sd = {
432 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
c43fd774 433 .allow_runtime_pm = true,
77a0122e 434 .own_cd_for_runtime_pm = true,
29229052
XS		 435};
436
0d013bcf
AH		 437static const struct sdhci_pci_fixes sdhci_intel_mfd_sdio = {
438 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
f3c55a7b 439 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON,
c43fd774 440 .allow_runtime_pm = true,
93933508 441 .probe_slot = mfd_sdio_probe_slot,
0d013bcf
AH		 442};
443
444static const struct sdhci_pci_fixes sdhci_intel_mfd_emmc = {
29229052 445 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
c43fd774 446 .allow_runtime_pm = true,
0d013bcf 447 .probe_slot = mfd_emmc_probe_slot,
29229052
XS		 448};
449
296e0b03
AS		 450static const struct sdhci_pci_fixes sdhci_intel_pch_sdio = {
451 .quirks = SDHCI_QUIRK_BROKEN_ADMA,
452 .probe_slot = pch_hc_probe_slot,
453};
454
c959a6b0
AH		 455enum {
456 INTEL_DSM_FNS = 0,
6ae03368 457 INTEL_DSM_V18_SWITCH = 3,
51ced59c 458 INTEL_DSM_DRV_STRENGTH = 9,
c959a6b0
AH		 459 INTEL_DSM_D3_RETUNE = 10,
460};
461
462struct intel_host {
463 u32 dsm_fns;
51ced59c 464 int drv_strength;
c959a6b0
AH		 465 bool d3_retune;
466};
467
c37f69ff 468static const guid_t intel_dsm_guid =
94116f81
AS		 469 GUID_INIT(0xF6C13EA5, 0x65CD, 0x461F,
470 0xAB, 0x7A, 0x29, 0xF7, 0xE8, 0xD5, 0xBD, 0x61);
c959a6b0
AH		 471
472static int __intel_dsm(struct intel_host *intel_host, struct device *dev,
473 unsigned int fn, u32 *result)
474{
475 union acpi_object *obj;
476 int err = 0;
a72016a4 477 size_t len;
c959a6b0 478
94116f81 479 obj = acpi_evaluate_dsm(ACPI_HANDLE(dev), &intel_dsm_guid, 0, fn, NULL);
c959a6b0
AH		 480 if (!obj)
481 return -EOPNOTSUPP;
482
483 if (obj->type != ACPI_TYPE_BUFFER || obj->buffer.length < 1) {
484 err = -EINVAL;
485 goto out;
486 }
487
a72016a4
AH		 488 len = min_t(size_t, obj->buffer.length, 4);
489
490 *result = 0;
491 memcpy(result, obj->buffer.pointer, len);
c959a6b0
AH		 492out:
493 ACPI_FREE(obj);
494
495 return err;
496}
497
498static int intel_dsm(struct intel_host *intel_host, struct device *dev,
499 unsigned int fn, u32 *result)
500{
501 if (fn > 31 || !(intel_host->dsm_fns & (1 << fn)))
502 return -EOPNOTSUPP;
503
504 return __intel_dsm(intel_host, dev, fn, result);
505}
506
507static void intel_dsm_init(struct intel_host *intel_host, struct device *dev,
508 struct mmc_host *mmc)
509{
510 int err;
511 u32 val;
512
eb701ce1
AH		 513 intel_host->d3_retune = true;
514
c959a6b0
AH		 515 err = __intel_dsm(intel_host, dev, INTEL_DSM_FNS, &intel_host->dsm_fns);
516 if (err) {
517 pr_debug("%s: DSM not supported, error %d\n",
518 mmc_hostname(mmc), err);
519 return;
520 }
521
522 pr_debug("%s: DSM function mask %#x\n",
523 mmc_hostname(mmc), intel_host->dsm_fns);
524
51ced59c
AH		 525 err = intel_dsm(intel_host, dev, INTEL_DSM_DRV_STRENGTH, &val);
526 intel_host->drv_strength = err ? 0 : val;
527
c959a6b0
AH		 528 err = intel_dsm(intel_host, dev, INTEL_DSM_D3_RETUNE, &val);
529 intel_host->d3_retune = err ? true : !!val;
530}
531
c9faff6c
AH		 532static void sdhci_pci_int_hw_reset(struct sdhci_host *host)
533{
534 u8 reg;
535
536 reg = sdhci_readb(host, SDHCI_POWER_CONTROL);
537 reg |= 0x10;
538 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL);
539 /* For eMMC, minimum is 1us but give it 9us for good measure */
540 udelay(9);
541 reg &= ~0x10;
542 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL);
543 /* For eMMC, minimum is 200us but give it 300us for good measure */
544 usleep_range(300, 1000);
545}
546
51ced59c
AH		 547static int intel_select_drive_strength(struct mmc_card *card,
548 unsigned int max_dtr, int host_drv,
549 int card_drv, int *drv_type)
e1bfad6d 550{
51ced59c
AH		 551 struct sdhci_host *host = mmc_priv(card->host);
552 struct sdhci_pci_slot *slot = sdhci_priv(host);
553 struct intel_host *intel_host = sdhci_pci_priv(slot);
e1bfad6d 554
51ced59c 555 return intel_host->drv_strength;
e1bfad6d
AH		 556}
557
163cbe31
AH		 558static int bxt_get_cd(struct mmc_host *mmc)
559{
560 int gpio_cd = mmc_gpio_get_cd(mmc);
561 struct sdhci_host *host = mmc_priv(mmc);
562 unsigned long flags;
563 int ret = 0;
564
565 if (!gpio_cd)
566 return 0;
567
163cbe31
AH		 568 spin_lock_irqsave(&host->lock, flags);
569
570 if (host->flags & SDHCI_DEVICE_DEAD)
571 goto out;
572
573 ret = !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
574out:
575 spin_unlock_irqrestore(&host->lock, flags);
576
163cbe31
AH		 577 return ret;
578}
579
48d685a2
AH		 580#define SDHCI_INTEL_PWR_TIMEOUT_CNT 20
581#define SDHCI_INTEL_PWR_TIMEOUT_UDELAY 100
582
583static void sdhci_intel_set_power(struct sdhci_host *host, unsigned char mode,
584 unsigned short vdd)
585{
586 int cntr;
587 u8 reg;
588
589 sdhci_set_power(host, mode, vdd);
590
591 if (mode == MMC_POWER_OFF)
592 return;
593
594 /*
595 * Bus power might not enable after D3 -> D0 transition due to the
596 * present state not yet having propagated. Retry for up to 2ms.
597 */
598 for (cntr = 0; cntr < SDHCI_INTEL_PWR_TIMEOUT_CNT; cntr++) {
599 reg = sdhci_readb(host, SDHCI_POWER_CONTROL);
600 if (reg & SDHCI_POWER_ON)
601 break;
602 udelay(SDHCI_INTEL_PWR_TIMEOUT_UDELAY);
603 reg |= SDHCI_POWER_ON;
604 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL);
605 }
606}
607
bc55dcd8
AH		 608#define INTEL_HS400_ES_REG 0x78
609#define INTEL_HS400_ES_BIT BIT(0)
610
611static void intel_hs400_enhanced_strobe(struct mmc_host *mmc,
612 struct mmc_ios *ios)
613{
614 struct sdhci_host *host = mmc_priv(mmc);
615 u32 val;
616
617 val = sdhci_readl(host, INTEL_HS400_ES_REG);
618 if (ios->enhanced_strobe)
619 val |= INTEL_HS400_ES_BIT;
620 else
621 val &= ~INTEL_HS400_ES_BIT;
622 sdhci_writel(host, val, INTEL_HS400_ES_REG);
623}
624
6ae03368
AH		 625static void sdhci_intel_voltage_switch(struct sdhci_host *host)
626{
627 struct sdhci_pci_slot *slot = sdhci_priv(host);
628 struct intel_host *intel_host = sdhci_pci_priv(slot);
629 struct device *dev = &slot->chip->pdev->dev;
630 u32 result = 0;
631 int err;
632
633 err = intel_dsm(intel_host, dev, INTEL_DSM_V18_SWITCH, &result);
634 pr_debug("%s: %s DSM error %d result %u\n",
635 mmc_hostname(host->mmc), __func__, err, result);
636}
637
48d685a2
AH		 638static const struct sdhci_ops sdhci_intel_byt_ops = {
639 .set_clock = sdhci_set_clock,
640 .set_power = sdhci_intel_set_power,
641 .enable_dma = sdhci_pci_enable_dma,
adc16398 642 .set_bus_width = sdhci_set_bus_width,
48d685a2
AH		 643 .reset = sdhci_reset,
644 .set_uhs_signaling = sdhci_set_uhs_signaling,
645 .hw_reset = sdhci_pci_hw_reset,
6ae03368 646 .voltage_switch = sdhci_intel_voltage_switch,
48d685a2
AH		 647};
648
8ee82bda
AH		 649static const struct sdhci_ops sdhci_intel_glk_ops = {
650 .set_clock = sdhci_set_clock,
651 .set_power = sdhci_intel_set_power,
652 .enable_dma = sdhci_pci_enable_dma,
653 .set_bus_width = sdhci_set_bus_width,
654 .reset = sdhci_reset,
655 .set_uhs_signaling = sdhci_set_uhs_signaling,
656 .hw_reset = sdhci_pci_hw_reset,
657 .voltage_switch = sdhci_intel_voltage_switch,
658 .irq = sdhci_cqhci_irq,
659};
660
c959a6b0
AH		 661static void byt_read_dsm(struct sdhci_pci_slot *slot)
662{
663 struct intel_host *intel_host = sdhci_pci_priv(slot);
664 struct device *dev = &slot->chip->pdev->dev;
665 struct mmc_host *mmc = slot->host->mmc;
666
667 intel_dsm_init(intel_host, dev, mmc);
668 slot->chip->rpm_retune = intel_host->d3_retune;
669}
670
728ef3d1
AH		 671static int byt_emmc_probe_slot(struct sdhci_pci_slot *slot)
672{
c959a6b0 673 byt_read_dsm(slot);
c9faff6c 674 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE |
6aab23a8 675 MMC_CAP_HW_RESET | MMC_CAP_1_8V_DDR |
32828857 676 MMC_CAP_CMD_DURING_TFR |
6aab23a8 677 MMC_CAP_WAIT_WHILE_BUSY;
c9faff6c 678 slot->hw_reset = sdhci_pci_int_hw_reset;
a06586b6
AH		 679 if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BSW_EMMC)
680 slot->host->timeout_clk = 1000; /* 1000 kHz i.e. 1 MHz */
51ced59c
AH		 681 slot->host->mmc_host_ops.select_drive_strength =
682 intel_select_drive_strength;
728ef3d1
AH		 683 return 0;
684}
685
bc55dcd8
AH		 686static int glk_emmc_probe_slot(struct sdhci_pci_slot *slot)
687{
688 int ret = byt_emmc_probe_slot(slot);
689
8ee82bda
AH		 690 slot->host->mmc->caps2 |= MMC_CAP2_CQE;
691
bc55dcd8
AH		 692 if (slot->chip->pdev->device != PCI_DEVICE_ID_INTEL_GLK_EMMC) {
693 slot->host->mmc->caps2 |= MMC_CAP2_HS400_ES,
694 slot->host->mmc_host_ops.hs400_enhanced_strobe =
695 intel_hs400_enhanced_strobe;
8ee82bda 696 slot->host->mmc->caps2 |= MMC_CAP2_CQE_DCMD;
bc55dcd8
AH		 697 }
698
699 return ret;
700}
701
8ee82bda
AH		 702static void glk_cqe_enable(struct mmc_host *mmc)
703{
704 struct sdhci_host *host = mmc_priv(mmc);
705 u32 reg;
706
707 /*
708 * CQE gets stuck if it sees Buffer Read Enable bit set, which can be
709 * the case after tuning, so ensure the buffer is drained.
710 */
711 reg = sdhci_readl(host, SDHCI_PRESENT_STATE);
712 while (reg & SDHCI_DATA_AVAILABLE) {
713 sdhci_readl(host, SDHCI_BUFFER);
714 reg = sdhci_readl(host, SDHCI_PRESENT_STATE);
715 }
716
717 sdhci_cqe_enable(mmc);
718}
719
720static const struct cqhci_host_ops glk_cqhci_ops = {
721 .enable = glk_cqe_enable,
722 .disable = sdhci_cqe_disable,
723 .dumpregs = sdhci_pci_dumpregs,
724};
725
726static int glk_emmc_add_host(struct sdhci_pci_slot *slot)
727{
728 struct device *dev = &slot->chip->pdev->dev;
729 struct sdhci_host *host = slot->host;
730 struct cqhci_host *cq_host;
731 bool dma64;
732 int ret;
733
734 ret = sdhci_setup_host(host);
735 if (ret)
736 return ret;
737
738 cq_host = devm_kzalloc(dev, sizeof(*cq_host), GFP_KERNEL);
739 if (!cq_host) {
740 ret = -ENOMEM;
741 goto cleanup;
742 }
743
744 cq_host->mmio = host->ioaddr + 0x200;
745 cq_host->quirks |= CQHCI_QUIRK_SHORT_TXFR_DESC_SZ;
746 cq_host->ops = &glk_cqhci_ops;
747
748 dma64 = host->flags & SDHCI_USE_64_BIT_DMA;
749 if (dma64)
750 cq_host->caps |= CQHCI_TASK_DESC_SZ_128;
751
752 ret = cqhci_init(cq_host, host->mmc, dma64);
753 if (ret)
754 goto cleanup;
755
756 ret = __sdhci_add_host(host);
757 if (ret)
758 goto cleanup;
759
760 return 0;
761
762cleanup:
763 sdhci_cleanup_host(host);
764 return ret;
765}
766
3f23df72
ZB		 767#ifdef CONFIG_ACPI
768static int ni_set_max_freq(struct sdhci_pci_slot *slot)
769{
770 acpi_status status;
771 unsigned long long max_freq;
772
773 status = acpi_evaluate_integer(ACPI_HANDLE(&slot->chip->pdev->dev),
774 "MXFQ", NULL, &max_freq);
775 if (ACPI_FAILURE(status)) {
776 dev_err(&slot->chip->pdev->dev,
777 "MXFQ not found in acpi table\n");
778 return -EINVAL;
779 }
780
781 slot->host->mmc->f_max = max_freq * 1000000;
782
783 return 0;
784}
785#else
786static inline int ni_set_max_freq(struct sdhci_pci_slot *slot)
787{
788 return 0;
789}
790#endif
791
42b06496
ZB		 792static int ni_byt_sdio_probe_slot(struct sdhci_pci_slot *slot)
793{
3f23df72
ZB		 794 int err;
795
c959a6b0
AH		 796 byt_read_dsm(slot);
797
3f23df72
ZB		 798 err = ni_set_max_freq(slot);
799 if (err)
800 return err;
801
42b06496
ZB		 802 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE |
803 MMC_CAP_WAIT_WHILE_BUSY;
804 return 0;
805}
806
728ef3d1
AH		 807static int byt_sdio_probe_slot(struct sdhci_pci_slot *slot)
808{
c959a6b0 809 byt_read_dsm(slot);
6aab23a8 810 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE |
6aab23a8 811 MMC_CAP_WAIT_WHILE_BUSY;
728ef3d1
AH		 812 return 0;
813}
814
ff59c520
AH		 815static int byt_sd_probe_slot(struct sdhci_pci_slot *slot)
816{
c959a6b0 817 byt_read_dsm(slot);
c2c49a2e 818 slot->host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY |
6cf4156c 819 MMC_CAP_AGGRESSIVE_PM | MMC_CAP_CD_WAKE;
ff59c520
AH		 820 slot->cd_idx = 0;
821 slot->cd_override_level = true;
163cbe31 822 if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BXT_SD ||
01d6b2a4 823 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BXTM_SD ||
2d1956d0 824 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_APL_SD ||
c2c49a2e 825 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_GLK_SD)
163cbe31
AH		 826 slot->host->mmc_host_ops.get_cd = bxt_get_cd;
827
ff59c520
AH		 828 return 0;
829}
830
728ef3d1
AH		 831static const struct sdhci_pci_fixes sdhci_intel_byt_emmc = {
832 .allow_runtime_pm = true,
833 .probe_slot = byt_emmc_probe_slot,
db6e8cdf 834 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
e58e4a0d 835 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
b69587e2 836 SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 |
e58e4a0d 837 SDHCI_QUIRK2_STOP_WITH_TC,
fee686b7 838 .ops = &sdhci_intel_byt_ops,
c959a6b0 839 .priv_size = sizeof(struct intel_host),
728ef3d1
AH		 840};
841
bc55dcd8
AH		 842static const struct sdhci_pci_fixes sdhci_intel_glk_emmc = {
843 .allow_runtime_pm = true,
844 .probe_slot = glk_emmc_probe_slot,
8ee82bda
AH		 845 .add_host = glk_emmc_add_host,
846#ifdef CONFIG_PM_SLEEP
847 .suspend = sdhci_cqhci_suspend,
848 .resume = sdhci_cqhci_resume,
849#endif
850#ifdef CONFIG_PM
851 .runtime_suspend = sdhci_cqhci_runtime_suspend,
852 .runtime_resume = sdhci_cqhci_runtime_resume,
853#endif
bc55dcd8
AH		 854 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
855 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
856 SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 |
857 SDHCI_QUIRK2_STOP_WITH_TC,
8ee82bda 858 .ops = &sdhci_intel_glk_ops,
bc55dcd8
AH		 859 .priv_size = sizeof(struct intel_host),
860};
861
42b06496
ZB		 862static const struct sdhci_pci_fixes sdhci_ni_byt_sdio = {
863 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
864 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON |
865 SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
866 .allow_runtime_pm = true,
867 .probe_slot = ni_byt_sdio_probe_slot,
868 .ops = &sdhci_intel_byt_ops,
c959a6b0 869 .priv_size = sizeof(struct intel_host),
42b06496
ZB		 870};
871
728ef3d1 872static const struct sdhci_pci_fixes sdhci_intel_byt_sdio = {
db6e8cdf 873 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
b7574bad
GY		 874 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON |
875 SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
728ef3d1
AH		 876 .allow_runtime_pm = true,
877 .probe_slot = byt_sdio_probe_slot,
fee686b7 878 .ops = &sdhci_intel_byt_ops,
c959a6b0 879 .priv_size = sizeof(struct intel_host),
728ef3d1
AH		 880};
881
882static const struct sdhci_pci_fixes sdhci_intel_byt_sd = {
db6e8cdf 883 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
b7574bad 884 .quirks2 = SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON |
e58e4a0d
AH		 885 SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
886 SDHCI_QUIRK2_STOP_WITH_TC,
7396e318 887 .allow_runtime_pm = true,
77a0122e 888 .own_cd_for_runtime_pm = true,
ff59c520 889 .probe_slot = byt_sd_probe_slot,
fee686b7 890 .ops = &sdhci_intel_byt_ops,
c959a6b0 891 .priv_size = sizeof(struct intel_host),
728ef3d1
AH		 892};
893
8776a165 894/* Define Host controllers for Intel Merrifield platform */
1f64cec2
AS		 895#define INTEL_MRFLD_EMMC_0 0
896#define INTEL_MRFLD_EMMC_1 1
4674b6c8 897#define INTEL_MRFLD_SD 2
d5565577 898#define INTEL_MRFLD_SDIO 3
8776a165 899
0e39220e
AS		 900#ifdef CONFIG_ACPI
901static void intel_mrfld_mmc_fix_up_power_slot(struct sdhci_pci_slot *slot)
902{
903 struct acpi_device *device, *child;
904
905 device = ACPI_COMPANION(&slot->chip->pdev->dev);
906 if (!device)
907 return;
908
909 acpi_device_fix_up_power(device);
910 list_for_each_entry(child, &device->children, node)
911 if (child->status.present && child->status.enabled)
912 acpi_device_fix_up_power(child);
913}
914#else
915static inline void intel_mrfld_mmc_fix_up_power_slot(struct sdhci_pci_slot *slot) {}
916#endif
917
1f64cec2 918static int intel_mrfld_mmc_probe_slot(struct sdhci_pci_slot *slot)
8776a165 919{
2e57bbe2
AS		 920 unsigned int func = PCI_FUNC(slot->chip->pdev->devfn);
921
922 switch (func) {
923 case INTEL_MRFLD_EMMC_0:
924 case INTEL_MRFLD_EMMC_1:
925 slot->host->mmc->caps |= MMC_CAP_NONREMOVABLE |
926 MMC_CAP_8_BIT_DATA |
927 MMC_CAP_1_8V_DDR;
928 break;
4674b6c8
AS		 929 case INTEL_MRFLD_SD:
930 slot->host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V;
931 break;
d5565577
AS		 932 case INTEL_MRFLD_SDIO:
933 slot->host->mmc->caps |= MMC_CAP_NONREMOVABLE |
934 MMC_CAP_POWER_OFF_CARD;
935 break;
2e57bbe2 936 default:
8776a165 937 return -ENODEV;
2e57bbe2 938 }
0e39220e
AS		 939
940 intel_mrfld_mmc_fix_up_power_slot(slot);
8776a165
DC		 941 return 0;
942}
943
1f64cec2 944static const struct sdhci_pci_fixes sdhci_intel_mrfld_mmc = {
8776a165 945 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
b7574bad
GY		 946 .quirks2 = SDHCI_QUIRK2_BROKEN_HS200 |
947 SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
f1b55a55 948 .allow_runtime_pm = true,
1f64cec2 949 .probe_slot = intel_mrfld_mmc_probe_slot,
8776a165
DC		 950};
951
45211e21
PO		 952static int jmicron_pmos(struct sdhci_pci_chip *chip, int on)
953{
954 u8 scratch;
955 int ret;
956
957 ret = pci_read_config_byte(chip->pdev, 0xAE, &scratch);
958 if (ret)
959 return ret;
960
961 /*
962 * Turn PMOS on [bit 0], set over current detection to 2.4 V
963 * [bit 1:2] and enable over current debouncing [bit 6].
964 */
965 if (on)
966 scratch |= 0x47;
967 else
968 scratch &= ~0x47;
969
7582041f 970 return pci_write_config_byte(chip->pdev, 0xAE, scratch);
45211e21
PO		 971}
972
973static int jmicron_probe(struct sdhci_pci_chip *chip)
974{
975 int ret;
8f230f45 976 u16 mmcdev = 0;
45211e21 977
93fc48c7
PO		 978 if (chip->pdev->revision == 0) {
979 chip->quirks |= SDHCI_QUIRK_32BIT_DMA_ADDR |
980 SDHCI_QUIRK_32BIT_DMA_SIZE |
2134a922 981 SDHCI_QUIRK_32BIT_ADMA_SIZE |
4a3cba32 982 SDHCI_QUIRK_RESET_AFTER_REQUEST |
86a6a874 983 SDHCI_QUIRK_BROKEN_SMALL_PIO;
93fc48c7
PO		 984 }
985
4489428a
PO		 986 /*
987 * JMicron chips can have two interfaces to the same hardware
988 * in order to work around limitations in Microsoft's driver.
989 * We need to make sure we only bind to one of them.
990 *
991 * This code assumes two things:
992 *
993 * 1. The PCI code adds subfunctions in order.
994 *
995 * 2. The MMC interface has a lower subfunction number
996 * than the SD interface.
997 */
8f230f45
TI		 998 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_SD)
999 mmcdev = PCI_DEVICE_ID_JMICRON_JMB38X_MMC;
1000 else if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD)
1001 mmcdev = PCI_DEVICE_ID_JMICRON_JMB388_ESD;
1002
1003 if (mmcdev) {
4489428a
PO		 1004 struct pci_dev *sd_dev;
1005
1006 sd_dev = NULL;
1007 while ((sd_dev = pci_get_device(PCI_VENDOR_ID_JMICRON,
8f230f45 1008 mmcdev, sd_dev)) != NULL) {
4489428a
PO		 1009 if ((PCI_SLOT(chip->pdev->devfn) ==
1010 PCI_SLOT(sd_dev->devfn)) &&
1011 (chip->pdev->bus == sd_dev->bus))
1012 break;
1013 }
1014
1015 if (sd_dev) {
1016 pci_dev_put(sd_dev);
1017 dev_info(&chip->pdev->dev, "Refusing to bind to "
1018 "secondary interface.\n");
1019 return -ENODEV;
1020 }
1021 }
1022
45211e21
PO		 1023 /*
1024 * JMicron chips need a bit of a nudge to enable the power
1025 * output pins.
1026 */
1027 ret = jmicron_pmos(chip, 1);
1028 if (ret) {
1029 dev_err(&chip->pdev->dev, "Failure enabling card power\n");
1030 return ret;
1031 }
1032
82b0e23a
TI		 1033 /* quirk for unsable RO-detection on JM388 chips */
1034 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD ||
1035 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD)
1036 chip->quirks |= SDHCI_QUIRK_UNSTABLE_RO_DETECT;
1037
45211e21
PO		 1038 return 0;
1039}
1040
4489428a
PO		 1041static void jmicron_enable_mmc(struct sdhci_host *host, int on)
1042{
1043 u8 scratch;
1044
1045 scratch = readb(host->ioaddr + 0xC0);
1046
1047 if (on)
1048 scratch |= 0x01;
1049 else
1050 scratch &= ~0x01;
1051
1052 writeb(scratch, host->ioaddr + 0xC0);
1053}
1054
1055static int jmicron_probe_slot(struct sdhci_pci_slot *slot)
1056{
2134a922
PO		 1057 if (slot->chip->pdev->revision == 0) {
1058 u16 version;
1059
1060 version = readl(slot->host->ioaddr + SDHCI_HOST_VERSION);
1061 version = (version & SDHCI_VENDOR_VER_MASK) >>
1062 SDHCI_VENDOR_VER_SHIFT;
1063
1064 /*
1065 * Older versions of the chip have lots of nasty glitches
1066 * in the ADMA engine. It's best just to avoid it
1067 * completely.
1068 */
1069 if (version < 0xAC)
1070 slot->host->quirks |= SDHCI_QUIRK_BROKEN_ADMA;
1071 }
1072
8f230f45
TI		 1073 /* JM388 MMC doesn't support 1.8V while SD supports it */
1074 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) {
1075 slot->host->ocr_avail_sd = MMC_VDD_32_33 | MMC_VDD_33_34 |
1076 MMC_VDD_29_30 | MMC_VDD_30_31 |
1077 MMC_VDD_165_195; /* allow 1.8V */
1078 slot->host->ocr_avail_mmc = MMC_VDD_32_33 | MMC_VDD_33_34 |
1079 MMC_VDD_29_30 | MMC_VDD_30_31; /* no 1.8V for MMC */
1080 }
1081
4489428a
PO		 1082 /*
1083 * The secondary interface requires a bit set to get the
1084 * interrupts.
1085 */
8f230f45
TI		 1086 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
1087 slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD)
4489428a
PO		 1088 jmicron_enable_mmc(slot->host, 1);
1089
d75c1084
TI		 1090 slot->host->mmc->caps |= MMC_CAP_BUS_WIDTH_TEST;
1091
4489428a
PO		 1092 return 0;
1093}
1094
1e72859e 1095static void jmicron_remove_slot(struct sdhci_pci_slot *slot, int dead)
4489428a 1096{
1e72859e
PO		 1097 if (dead)
1098 return;
1099
8f230f45
TI		 1100 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
1101 slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD)
4489428a
PO		 1102 jmicron_enable_mmc(slot->host, 0);
1103}
1104
b7813f0f 1105#ifdef CONFIG_PM_SLEEP
29495aa0 1106static int jmicron_suspend(struct sdhci_pci_chip *chip)
4489428a 1107{
30cf2803
AH		 1108 int i, ret;
1109
1110 ret = __sdhci_pci_suspend_host(chip);
1111 if (ret)
1112 return ret;
4489428a 1113
8f230f45
TI		 1114 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
1115 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) {
b177bc91 1116 for (i = 0; i < chip->num_slots; i++)
4489428a
PO		 1117 jmicron_enable_mmc(chip->slots[i]->host, 0);
1118 }
1119
30cf2803
AH		 1120 sdhci_pci_init_wakeup(chip);
1121
4489428a
PO		 1122 return 0;
1123}
1124
45211e21
PO		 1125static int jmicron_resume(struct sdhci_pci_chip *chip)
1126{
4489428a
PO		 1127 int ret, i;
1128
8f230f45
TI		 1129 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
1130 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) {
b177bc91 1131 for (i = 0; i < chip->num_slots; i++)
4489428a
PO		 1132 jmicron_enable_mmc(chip->slots[i]->host, 1);
1133 }
45211e21
PO		 1134
1135 ret = jmicron_pmos(chip, 1);
1136 if (ret) {
1137 dev_err(&chip->pdev->dev, "Failure enabling card power\n");
1138 return ret;
1139 }
1140
30cf2803 1141 return sdhci_pci_resume_host(chip);
45211e21 1142}
b7813f0f 1143#endif
45211e21 1144
26daa1ed 1145static const struct sdhci_pci_fixes sdhci_o2 = {
01acf691
AL		 1146 .probe = sdhci_pci_o2_probe,
1147 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
143b648d 1148 .quirks2 = SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD,
01acf691 1149 .probe_slot = sdhci_pci_o2_probe_slot,
b7813f0f 1150#ifdef CONFIG_PM_SLEEP
01acf691 1151 .resume = sdhci_pci_o2_resume,
b7813f0f 1152#endif
26daa1ed
JL		 1153};
1154
22606405 1155static const struct sdhci_pci_fixes sdhci_jmicron = {
45211e21
PO		 1156 .probe = jmicron_probe,
1157
4489428a
PO		 1158 .probe_slot = jmicron_probe_slot,
1159 .remove_slot = jmicron_remove_slot,
1160
b7813f0f 1161#ifdef CONFIG_PM_SLEEP
4489428a 1162 .suspend = jmicron_suspend,
45211e21 1163 .resume = jmicron_resume,
b7813f0f 1164#endif
22606405
PO		 1165};
1166
a7a6186c
NP		 1167/* SysKonnect CardBus2SDIO extra registers */
1168#define SYSKT_CTRL 0x200
1169#define SYSKT_RDFIFO_STAT 0x204
1170#define SYSKT_WRFIFO_STAT 0x208
1171#define SYSKT_POWER_DATA 0x20c
1172#define SYSKT_POWER_330 0xef
1173#define SYSKT_POWER_300 0xf8
1174#define SYSKT_POWER_184 0xcc
1175#define SYSKT_POWER_CMD 0x20d
1176#define SYSKT_POWER_START (1 << 7)
1177#define SYSKT_POWER_STATUS 0x20e
1178#define SYSKT_POWER_STATUS_OK (1 << 0)
1179#define SYSKT_BOARD_REV 0x210
1180#define SYSKT_CHIP_REV 0x211
1181#define SYSKT_CONF_DATA 0x212
1182#define SYSKT_CONF_DATA_1V8 (1 << 2)
1183#define SYSKT_CONF_DATA_2V5 (1 << 1)
1184#define SYSKT_CONF_DATA_3V3 (1 << 0)
1185
1186static int syskt_probe(struct sdhci_pci_chip *chip)
1187{
1188 if ((chip->pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) {
1189 chip->pdev->class &= ~0x0000FF;
1190 chip->pdev->class |= PCI_SDHCI_IFDMA;
1191 }
1192 return 0;
1193}
1194
1195static int syskt_probe_slot(struct sdhci_pci_slot *slot)
1196{
1197 int tm, ps;
1198
1199 u8 board_rev = readb(slot->host->ioaddr + SYSKT_BOARD_REV);
1200 u8 chip_rev = readb(slot->host->ioaddr + SYSKT_CHIP_REV);
1201 dev_info(&slot->chip->pdev->dev, "SysKonnect CardBus2SDIO, "
1202 "board rev %d.%d, chip rev %d.%d\n",
1203 board_rev >> 4, board_rev & 0xf,
1204 chip_rev >> 4, chip_rev & 0xf);
1205 if (chip_rev >= 0x20)
1206 slot->host->quirks |= SDHCI_QUIRK_FORCE_DMA;
1207
1208 writeb(SYSKT_POWER_330, slot->host->ioaddr + SYSKT_POWER_DATA);
1209 writeb(SYSKT_POWER_START, slot->host->ioaddr + SYSKT_POWER_CMD);
1210 udelay(50);
1211 tm = 10; /* Wait max 1 ms */
1212 do {
1213 ps = readw(slot->host->ioaddr + SYSKT_POWER_STATUS);
1214 if (ps & SYSKT_POWER_STATUS_OK)
1215 break;
1216 udelay(100);
1217 } while (--tm);
1218 if (!tm) {
1219 dev_err(&slot->chip->pdev->dev,
1220 "power regulator never stabilized");
1221 writeb(0, slot->host->ioaddr + SYSKT_POWER_CMD);
1222 return -ENODEV;
1223 }
1224
1225 return 0;
1226}
1227
1228static const struct sdhci_pci_fixes sdhci_syskt = {
1229 .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER,
1230 .probe = syskt_probe,
1231 .probe_slot = syskt_probe_slot,
1232};
1233
557b0697
HW		 1234static int via_probe(struct sdhci_pci_chip *chip)
1235{
1236 if (chip->pdev->revision == 0x10)
1237 chip->quirks |= SDHCI_QUIRK_DELAY_AFTER_POWER;
1238
1239 return 0;
1240}
1241
1242static const struct sdhci_pci_fixes sdhci_via = {
1243 .probe = via_probe,
1244};
1245
9107ebbf
MC		 1246static int rtsx_probe_slot(struct sdhci_pci_slot *slot)
1247{
1248 slot->host->mmc->caps2 |= MMC_CAP2_HS200;
1249 return 0;
1250}
1251
1252static const struct sdhci_pci_fixes sdhci_rtsx = {
1253 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
e30b978f 1254 SDHCI_QUIRK2_BROKEN_64_BIT_DMA |
9107ebbf
MC		 1255 SDHCI_QUIRK2_BROKEN_DDR50,
1256 .probe_slot = rtsx_probe_slot,
1257};
1258
b5e97d6e
VW		 1259/*AMD chipset generation*/
1260enum amd_chipset_gen {
1261 AMD_CHIPSET_BEFORE_ML,
1262 AMD_CHIPSET_CZ,
1263 AMD_CHIPSET_NL,
1264 AMD_CHIPSET_UNKNOWN,
1265};
1266
c31165d7
SS		 1267/* AMD registers */
1268#define AMD_SD_AUTO_PATTERN 0xB8
1269#define AMD_MSLEEP_DURATION 4
1270#define AMD_SD_MISC_CONTROL 0xD0
1271#define AMD_MAX_TUNE_VALUE 0x0B
1272#define AMD_AUTO_TUNE_SEL 0x10800
1273#define AMD_FIFO_PTR 0x30
1274#define AMD_BIT_MASK 0x1F
1275
1276static void amd_tuning_reset(struct sdhci_host *host)
1277{
1278 unsigned int val;
1279
1280 val = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1281 val |= SDHCI_CTRL_PRESET_VAL_ENABLE | SDHCI_CTRL_EXEC_TUNING;
1282 sdhci_writew(host, val, SDHCI_HOST_CONTROL2);
1283
1284 val = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1285 val &= ~SDHCI_CTRL_EXEC_TUNING;
1286 sdhci_writew(host, val, SDHCI_HOST_CONTROL2);
1287}
1288
1289static void amd_config_tuning_phase(struct pci_dev *pdev, u8 phase)
1290{
1291 unsigned int val;
1292
1293 pci_read_config_dword(pdev, AMD_SD_AUTO_PATTERN, &val);
1294 val &= ~AMD_BIT_MASK;
1295 val |= (AMD_AUTO_TUNE_SEL | (phase << 1));
1296 pci_write_config_dword(pdev, AMD_SD_AUTO_PATTERN, val);
1297}
1298
1299static void amd_enable_manual_tuning(struct pci_dev *pdev)
1300{
1301 unsigned int val;
1302
1303 pci_read_config_dword(pdev, AMD_SD_MISC_CONTROL, &val);
1304 val |= AMD_FIFO_PTR;
1305 pci_write_config_dword(pdev, AMD_SD_MISC_CONTROL, val);
1306}
1307
1308static int amd_execute_tuning(struct sdhci_host *host, u32 opcode)
1309{
1310 struct sdhci_pci_slot *slot = sdhci_priv(host);
1311 struct pci_dev *pdev = slot->chip->pdev;
1312 u8 valid_win = 0;
1313 u8 valid_win_max = 0;
1314 u8 valid_win_end = 0;
1315 u8 ctrl, tune_around;
1316
1317 amd_tuning_reset(host);
1318
1319 for (tune_around = 0; tune_around < 12; tune_around++) {
1320 amd_config_tuning_phase(pdev, tune_around);
1321
1322 if (mmc_send_tuning(host->mmc, opcode, NULL)) {
1323 valid_win = 0;
1324 msleep(AMD_MSLEEP_DURATION);
1325 ctrl = SDHCI_RESET_CMD | SDHCI_RESET_DATA;
1326 sdhci_writeb(host, ctrl, SDHCI_SOFTWARE_RESET);
1327 } else if (++valid_win > valid_win_max) {
1328 valid_win_max = valid_win;
1329 valid_win_end = tune_around;
1330 }
1331 }
1332
1333 if (!valid_win_max) {
1334 dev_err(&pdev->dev, "no tuning point found\n");
1335 return -EIO;
1336 }
1337
1338 amd_config_tuning_phase(pdev, valid_win_end - valid_win_max / 2);
1339
1340 amd_enable_manual_tuning(pdev);
1341
1342 host->mmc->retune_period = 0;
1343
1344 return 0;
1345}
1346
d44f88da
VW		 1347static int amd_probe(struct sdhci_pci_chip *chip)
1348{
1349 struct pci_dev *smbus_dev;
b5e97d6e 1350 enum amd_chipset_gen gen;
d44f88da
VW		 1351
1352 smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD,
1353 PCI_DEVICE_ID_AMD_HUDSON2_SMBUS, NULL);
b5e97d6e
VW		 1354 if (smbus_dev) {
1355 gen = AMD_CHIPSET_BEFORE_ML;
1356 } else {
1357 smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD,
1358 PCI_DEVICE_ID_AMD_KERNCZ_SMBUS, NULL);
1359 if (smbus_dev) {
1360 if (smbus_dev->revision < 0x51)
1361 gen = AMD_CHIPSET_CZ;
1362 else
1363 gen = AMD_CHIPSET_NL;
1364 } else {
1365 gen = AMD_CHIPSET_UNKNOWN;
1366 }
1367 }
d44f88da 1368
c31165d7 1369 if (gen == AMD_CHIPSET_BEFORE_ML || gen == AMD_CHIPSET_CZ)
d44f88da
VW		 1370 chip->quirks2 |= SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD;
1371
1372 return 0;
1373}
1374
c31165d7
SS		 1375static const struct sdhci_ops amd_sdhci_pci_ops = {
1376 .set_clock = sdhci_set_clock,
1377 .enable_dma = sdhci_pci_enable_dma,
adc16398 1378 .set_bus_width = sdhci_set_bus_width,
c31165d7
SS		 1379 .reset = sdhci_reset,
1380 .set_uhs_signaling = sdhci_set_uhs_signaling,
1381 .platform_execute_tuning = amd_execute_tuning,
1382};
1383
d44f88da
VW		 1384static const struct sdhci_pci_fixes sdhci_amd = {
1385 .probe = amd_probe,
c31165d7 1386 .ops = &amd_sdhci_pci_ops,
d44f88da
VW		 1387};
1388
9647f84d 1389static const struct pci_device_id pci_ids[] = {
c949c907
MK		 1390 SDHCI_PCI_DEVICE(RICOH, R5C822, ricoh),
1391 SDHCI_PCI_DEVICE(RICOH, R5C843, ricoh_mmc),
1392 SDHCI_PCI_DEVICE(RICOH, R5CE822, ricoh_mmc),
1393 SDHCI_PCI_DEVICE(RICOH, R5CE823, ricoh_mmc),
1394 SDHCI_PCI_DEVICE(ENE, CB712_SD, ene_712),
1395 SDHCI_PCI_DEVICE(ENE, CB712_SD_2, ene_712),
1396 SDHCI_PCI_DEVICE(ENE, CB714_SD, ene_714),
1397 SDHCI_PCI_DEVICE(ENE, CB714_SD_2, ene_714),
1398 SDHCI_PCI_DEVICE(MARVELL, 88ALP01_SD, cafe),
1399 SDHCI_PCI_DEVICE(JMICRON, JMB38X_SD, jmicron),
1400 SDHCI_PCI_DEVICE(JMICRON, JMB38X_MMC, jmicron),
1401 SDHCI_PCI_DEVICE(JMICRON, JMB388_SD, jmicron),
1402 SDHCI_PCI_DEVICE(JMICRON, JMB388_ESD, jmicron),
1403 SDHCI_PCI_DEVICE(SYSKONNECT, 8000, syskt),
1404 SDHCI_PCI_DEVICE(VIA, 95D0, via),
1405 SDHCI_PCI_DEVICE(REALTEK, 5250, rtsx),
1406 SDHCI_PCI_DEVICE(INTEL, QRK_SD, intel_qrk),
1407 SDHCI_PCI_DEVICE(INTEL, MRST_SD0, intel_mrst_hc0),
1408 SDHCI_PCI_DEVICE(INTEL, MRST_SD1, intel_mrst_hc1_hc2),
1409 SDHCI_PCI_DEVICE(INTEL, MRST_SD2, intel_mrst_hc1_hc2),
1410 SDHCI_PCI_DEVICE(INTEL, MFD_SD, intel_mfd_sd),
1411 SDHCI_PCI_DEVICE(INTEL, MFD_SDIO1, intel_mfd_sdio),
1412 SDHCI_PCI_DEVICE(INTEL, MFD_SDIO2, intel_mfd_sdio),
1413 SDHCI_PCI_DEVICE(INTEL, MFD_EMMC0, intel_mfd_emmc),
1414 SDHCI_PCI_DEVICE(INTEL, MFD_EMMC1, intel_mfd_emmc),
1415 SDHCI_PCI_DEVICE(INTEL, PCH_SDIO0, intel_pch_sdio),
1416 SDHCI_PCI_DEVICE(INTEL, PCH_SDIO1, intel_pch_sdio),
1417 SDHCI_PCI_DEVICE(INTEL, BYT_EMMC, intel_byt_emmc),
1418 SDHCI_PCI_SUBDEVICE(INTEL, BYT_SDIO, NI, 7884, ni_byt_sdio),
1419 SDHCI_PCI_DEVICE(INTEL, BYT_SDIO, intel_byt_sdio),
1420 SDHCI_PCI_DEVICE(INTEL, BYT_SD, intel_byt_sd),
1421 SDHCI_PCI_DEVICE(INTEL, BYT_EMMC2, intel_byt_emmc),
1422 SDHCI_PCI_DEVICE(INTEL, BSW_EMMC, intel_byt_emmc),
1423 SDHCI_PCI_DEVICE(INTEL, BSW_SDIO, intel_byt_sdio),
1424 SDHCI_PCI_DEVICE(INTEL, BSW_SD, intel_byt_sd),
1425 SDHCI_PCI_DEVICE(INTEL, CLV_SDIO0, intel_mfd_sd),
1426 SDHCI_PCI_DEVICE(INTEL, CLV_SDIO1, intel_mfd_sdio),
1427 SDHCI_PCI_DEVICE(INTEL, CLV_SDIO2, intel_mfd_sdio),
1428 SDHCI_PCI_DEVICE(INTEL, CLV_EMMC0, intel_mfd_emmc),
1429 SDHCI_PCI_DEVICE(INTEL, CLV_EMMC1, intel_mfd_emmc),
1430 SDHCI_PCI_DEVICE(INTEL, MRFLD_MMC, intel_mrfld_mmc),
1431 SDHCI_PCI_DEVICE(INTEL, SPT_EMMC, intel_byt_emmc),
1432 SDHCI_PCI_DEVICE(INTEL, SPT_SDIO, intel_byt_sdio),
1433 SDHCI_PCI_DEVICE(INTEL, SPT_SD, intel_byt_sd),
1434 SDHCI_PCI_DEVICE(INTEL, DNV_EMMC, intel_byt_emmc),
cdaba732 1435 SDHCI_PCI_DEVICE(INTEL, CDF_EMMC, intel_glk_emmc),
c949c907
MK		 1436 SDHCI_PCI_DEVICE(INTEL, BXT_EMMC, intel_byt_emmc),
1437 SDHCI_PCI_DEVICE(INTEL, BXT_SDIO, intel_byt_sdio),
1438 SDHCI_PCI_DEVICE(INTEL, BXT_SD, intel_byt_sd),
1439 SDHCI_PCI_DEVICE(INTEL, BXTM_EMMC, intel_byt_emmc),
1440 SDHCI_PCI_DEVICE(INTEL, BXTM_SDIO, intel_byt_sdio),
1441 SDHCI_PCI_DEVICE(INTEL, BXTM_SD, intel_byt_sd),
1442 SDHCI_PCI_DEVICE(INTEL, APL_EMMC, intel_byt_emmc),
1443 SDHCI_PCI_DEVICE(INTEL, APL_SDIO, intel_byt_sdio),
1444 SDHCI_PCI_DEVICE(INTEL, APL_SD, intel_byt_sd),
bc55dcd8 1445 SDHCI_PCI_DEVICE(INTEL, GLK_EMMC, intel_glk_emmc),
c949c907
MK		 1446 SDHCI_PCI_DEVICE(INTEL, GLK_SDIO, intel_byt_sdio),
1447 SDHCI_PCI_DEVICE(INTEL, GLK_SD, intel_byt_sd),
bc55dcd8
AH		 1448 SDHCI_PCI_DEVICE(INTEL, CNP_EMMC, intel_glk_emmc),
1449 SDHCI_PCI_DEVICE(INTEL, CNP_SD, intel_byt_sd),
1450 SDHCI_PCI_DEVICE(INTEL, CNPH_SD, intel_byt_sd),
c949c907
MK		 1451 SDHCI_PCI_DEVICE(O2, 8120, o2),
1452 SDHCI_PCI_DEVICE(O2, 8220, o2),
1453 SDHCI_PCI_DEVICE(O2, 8221, o2),
1454 SDHCI_PCI_DEVICE(O2, 8320, o2),
1455 SDHCI_PCI_DEVICE(O2, 8321, o2),
1456 SDHCI_PCI_DEVICE(O2, FUJIN2, o2),
1457 SDHCI_PCI_DEVICE(O2, SDS0, o2),
1458 SDHCI_PCI_DEVICE(O2, SDS1, o2),
1459 SDHCI_PCI_DEVICE(O2, SEABIRD0, o2),
1460 SDHCI_PCI_DEVICE(O2, SEABIRD1, o2),
d72d72cd 1461 SDHCI_PCI_DEVICE(ARASAN, PHY_EMMC, arasan),
c949c907
MK		 1462 SDHCI_PCI_DEVICE_CLASS(AMD, SYSTEM_SDHCI, PCI_CLASS_MASK, amd),
1463 /* Generic SD host controller */
1464 {PCI_DEVICE_CLASS(SYSTEM_SDHCI, PCI_CLASS_MASK)},
b8c86fc5
PO		 1465 { /* end: all zeroes */ },
1466};
1467
1468MODULE_DEVICE_TABLE(pci, pci_ids);
1469
b8c86fc5
PO		 1470/*****************************************************************************\
1471 * *
1472 * SDHCI core callbacks *
1473 * *
1474\*****************************************************************************/
1475
d72d72cd 1476int sdhci_pci_enable_dma(struct sdhci_host *host)
b8c86fc5
PO		 1477{
1478 struct sdhci_pci_slot *slot;
1479 struct pci_dev *pdev;
b8c86fc5
PO		 1480
1481 slot = sdhci_priv(host);
1482 pdev = slot->chip->pdev;
1483
1484 if (((pdev->class & 0xFFFF00) == (PCI_CLASS_SYSTEM_SDHCI << 8)) &&
1485 ((pdev->class & 0x0000FF) != PCI_SDHCI_IFDMA) &&
a13abc7b 1486 (host->flags & SDHCI_USE_SDMA)) {
b8c86fc5
PO		 1487 dev_warn(&pdev->dev, "Will use DMA mode even though HW "
1488 "doesn't fully claim to support it.\n");
1489 }
1490
b8c86fc5
PO		 1491 pci_set_master(pdev);
1492
1493 return 0;
1494}
1495
c9faff6c 1496static void sdhci_pci_gpio_hw_reset(struct sdhci_host *host)
0f201655
AH		 1497{
1498 struct sdhci_pci_slot *slot = sdhci_priv(host);
1499 int rst_n_gpio = slot->rst_n_gpio;
1500
1501 if (!gpio_is_valid(rst_n_gpio))
1502 return;
1503 gpio_set_value_cansleep(rst_n_gpio, 0);
1504 /* For eMMC, minimum is 1us but give it 10us for good measure */
1505 udelay(10);
1506 gpio_set_value_cansleep(rst_n_gpio, 1);
1507 /* For eMMC, minimum is 200us but give it 300us for good measure */
1508 usleep_range(300, 1000);
1509}
1510
c9faff6c
AH		 1511static void sdhci_pci_hw_reset(struct sdhci_host *host)
1512{
1513 struct sdhci_pci_slot *slot = sdhci_priv(host);
1514
1515 if (slot->hw_reset)
1516 slot->hw_reset(host);
1517}
1518
c915568d 1519static const struct sdhci_ops sdhci_pci_ops = {
1771059c 1520 .set_clock = sdhci_set_clock,
b8c86fc5 1521 .enable_dma = sdhci_pci_enable_dma,
adc16398 1522 .set_bus_width = sdhci_set_bus_width,
03231f9b 1523 .reset = sdhci_reset,
96d7b78c 1524 .set_uhs_signaling = sdhci_set_uhs_signaling,
0f201655 1525 .hw_reset = sdhci_pci_hw_reset,
b8c86fc5
PO		 1526};
1527
1528/*****************************************************************************\
1529 * *
1530 * Suspend/resume *
1531 * *
1532\*****************************************************************************/
1533
f9900f15 1534#ifdef CONFIG_PM_SLEEP
29495aa0 1535static int sdhci_pci_suspend(struct device *dev)
b8c86fc5 1536{
29495aa0 1537 struct pci_dev *pdev = to_pci_dev(dev);
30cf2803 1538 struct sdhci_pci_chip *chip = pci_get_drvdata(pdev);
b8c86fc5 1539
b8c86fc5
PO		 1540 if (!chip)
1541 return 0;
1542
30cf2803
AH		 1543 if (chip->fixes && chip->fixes->suspend)
1544 return chip->fixes->suspend(chip);
b8c86fc5 1545
30cf2803 1546 return sdhci_pci_suspend_host(chip);
b8c86fc5
PO		 1547}
1548
29495aa0 1549static int sdhci_pci_resume(struct device *dev)
b8c86fc5 1550{
29495aa0 1551 struct pci_dev *pdev = to_pci_dev(dev);
30cf2803 1552 struct sdhci_pci_chip *chip = pci_get_drvdata(pdev);
b8c86fc5 1553
b8c86fc5
PO		 1554 if (!chip)
1555 return 0;
1556
30cf2803
AH		 1557 if (chip->fixes && chip->fixes->resume)
1558 return chip->fixes->resume(chip);
b8c86fc5 1559
30cf2803 1560 return sdhci_pci_resume_host(chip);
b8c86fc5 1561}
f9900f15 1562#endif
b8c86fc5 1563
f9900f15 1564#ifdef CONFIG_PM
66fd8ad5
AH		 1565static int sdhci_pci_runtime_suspend(struct device *dev)
1566{
923a231c 1567 struct pci_dev *pdev = to_pci_dev(dev);
966d696a 1568 struct sdhci_pci_chip *chip = pci_get_drvdata(pdev);
66fd8ad5 1569
66fd8ad5
AH		 1570 if (!chip)
1571 return 0;
1572
966d696a
AH		 1573 if (chip->fixes && chip->fixes->runtime_suspend)
1574 return chip->fixes->runtime_suspend(chip);
66fd8ad5 1575
966d696a 1576 return sdhci_pci_runtime_suspend_host(chip);
66fd8ad5
AH		 1577}
1578
1579static int sdhci_pci_runtime_resume(struct device *dev)
1580{
923a231c 1581 struct pci_dev *pdev = to_pci_dev(dev);
966d696a 1582 struct sdhci_pci_chip *chip = pci_get_drvdata(pdev);
66fd8ad5 1583
66fd8ad5
AH		 1584 if (!chip)
1585 return 0;
1586
966d696a
AH		 1587 if (chip->fixes && chip->fixes->runtime_resume)
1588 return chip->fixes->runtime_resume(chip);
66fd8ad5 1589
966d696a 1590 return sdhci_pci_runtime_resume_host(chip);
66fd8ad5 1591}
f9900f15 1592#endif
66fd8ad5
AH		 1593
1594static const struct dev_pm_ops sdhci_pci_pm_ops = {
f9900f15 1595 SET_SYSTEM_SLEEP_PM_OPS(sdhci_pci_suspend, sdhci_pci_resume)
f3a92b1a 1596 SET_RUNTIME_PM_OPS(sdhci_pci_runtime_suspend,
106276bb 1597 sdhci_pci_runtime_resume, NULL)
66fd8ad5
AH		 1598};
1599
b8c86fc5
PO		 1600/*****************************************************************************\
1601 * *
1602 * Device probing/removal *
1603 * *
1604\*****************************************************************************/
1605
c3be1efd 1606static struct sdhci_pci_slot *sdhci_pci_probe_slot(
52c506f0
AH		 1607 struct pci_dev *pdev, struct sdhci_pci_chip *chip, int first_bar,
1608 int slotno)
b8c86fc5
PO		 1609{
1610 struct sdhci_pci_slot *slot;
1611 struct sdhci_host *host;
52c506f0 1612 int ret, bar = first_bar + slotno;
ac9f67b5 1613 size_t priv_size = chip->fixes ? chip->fixes->priv_size : 0;
b8c86fc5
PO		 1614
1615 if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) {
1616 dev_err(&pdev->dev, "BAR %d is not iomem. Aborting.\n", bar);
1617 return ERR_PTR(-ENODEV);
1618 }
1619
90b3e6c5 1620 if (pci_resource_len(pdev, bar) < 0x100) {
b8c86fc5
PO		 1621 dev_err(&pdev->dev, "Invalid iomem size. You may "
1622 "experience problems.\n");
1623 }
1624
1625 if ((pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) {
1626 dev_err(&pdev->dev, "Vendor specific interface. Aborting.\n");
1627 return ERR_PTR(-ENODEV);
1628 }
1629
1630 if ((pdev->class & 0x0000FF) > PCI_SDHCI_IFVENDOR) {
1631 dev_err(&pdev->dev, "Unknown interface. Aborting.\n");
1632 return ERR_PTR(-ENODEV);
1633 }
1634
ac9f67b5 1635 host = sdhci_alloc_host(&pdev->dev, sizeof(*slot) + priv_size);
b8c86fc5 1636 if (IS_ERR(host)) {
c60a32cd 1637 dev_err(&pdev->dev, "cannot allocate host\n");
dc0fd7b5 1638 return ERR_CAST(host);
b8c86fc5
PO		 1639 }
1640
1641 slot = sdhci_priv(host);
1642
1643 slot->chip = chip;
1644 slot->host = host;
0f201655 1645 slot->rst_n_gpio = -EINVAL;
c5e027a4 1646 slot->cd_gpio = -EINVAL;
ff59c520 1647 slot->cd_idx = -1;
b8c86fc5 1648
52c506f0
AH		 1649 /* Retrieve platform data if there is any */
1650 if (*sdhci_pci_get_data)
1651 slot->data = sdhci_pci_get_data(pdev, slotno);
1652
1653 if (slot->data) {
1654 if (slot->data->setup) {
1655 ret = slot->data->setup(slot->data);
1656 if (ret) {
1657 dev_err(&pdev->dev, "platform setup failed\n");
1658 goto free;
1659 }
1660 }
c5e027a4
AH		 1661 slot->rst_n_gpio = slot->data->rst_n_gpio;
1662 slot->cd_gpio = slot->data->cd_gpio;
52c506f0
AH		 1663 }
1664
b8c86fc5 1665 host->hw_name = "PCI";
6bc09063
AH		 1666 host->ops = chip->fixes && chip->fixes->ops ?
1667 chip->fixes->ops :
1668 &sdhci_pci_ops;
b8c86fc5 1669 host->quirks = chip->quirks;
f3c55a7b 1670 host->quirks2 = chip->quirks2;
b8c86fc5
PO		 1671
1672 host->irq = pdev->irq;
1673
c10bc372 1674 ret = pcim_iomap_regions(pdev, BIT(bar), mmc_hostname(host->mmc));
b8c86fc5
PO		 1675 if (ret) {
1676 dev_err(&pdev->dev, "cannot request region\n");
52c506f0 1677 goto cleanup;
b8c86fc5
PO		 1678 }
1679
c10bc372 1680 host->ioaddr = pcim_iomap_table(pdev)[bar];
b8c86fc5 1681
4489428a
PO		 1682 if (chip->fixes && chip->fixes->probe_slot) {
1683 ret = chip->fixes->probe_slot(slot);
1684 if (ret)
c10bc372 1685 goto cleanup;
4489428a
PO		 1686 }
1687
c5e027a4 1688 if (gpio_is_valid(slot->rst_n_gpio)) {
c10bc372 1689 if (!devm_gpio_request(&pdev->dev, slot->rst_n_gpio, "eMMC_reset")) {
c5e027a4
AH		 1690 gpio_direction_output(slot->rst_n_gpio, 1);
1691 slot->host->mmc->caps |= MMC_CAP_HW_RESET;
c9faff6c 1692 slot->hw_reset = sdhci_pci_gpio_hw_reset;
c5e027a4
AH		 1693 } else {
1694 dev_warn(&pdev->dev, "failed to request rst_n_gpio\n");
1695 slot->rst_n_gpio = -EINVAL;
1696 }
1697 }
1698
2f4cbb3d 1699 host->mmc->pm_caps = MMC_PM_KEEP_POWER | MMC_PM_WAKE_SDIO_IRQ;
eed222ac 1700 host->mmc->slotno = slotno;
a08b17be 1701 host->mmc->caps2 |= MMC_CAP2_NO_PRESCAN_POWERUP;
2f4cbb3d 1702
8f743d03 1703 if (slot->cd_idx >= 0) {
6ac9b837 1704 ret = mmc_gpiod_request_cd(host->mmc, NULL, slot->cd_idx,
8f743d03
DB		 1705 slot->cd_override_level, 0, NULL);
1706 if (ret == -EPROBE_DEFER)
1707 goto remove;
1708
1709 if (ret) {
1710 dev_warn(&pdev->dev, "failed to setup card detect gpio\n");
1711 slot->cd_idx = -1;
1712 }
ff59c520
AH		 1713 }
1714
61c951de
AH		 1715 if (chip->fixes && chip->fixes->add_host)
1716 ret = chip->fixes->add_host(slot);
1717 else
1718 ret = sdhci_add_host(host);
b8c86fc5 1719 if (ret)
4489428a 1720 goto remove;
b8c86fc5 1721
c5e027a4
AH		 1722 sdhci_pci_add_own_cd(slot);
1723
77a0122e
AH		 1724 /*
1725 * Check if the chip needs a separate GPIO for card detect to wake up
1726 * from runtime suspend. If it is not there, don't allow runtime PM.
1727 * Note sdhci_pci_add_own_cd() sets slot->cd_gpio to -EINVAL on failure.
1728 */
945be38c 1729 if (chip->fixes && chip->fixes->own_cd_for_runtime_pm &&
ff59c520 1730 !gpio_is_valid(slot->cd_gpio) && slot->cd_idx < 0)
77a0122e
AH		 1731 chip->allow_runtime_pm = false;
1732
b8c86fc5
PO		 1733 return slot;
1734
4489428a
PO		 1735remove:
1736 if (chip->fixes && chip->fixes->remove_slot)
1e72859e 1737 chip->fixes->remove_slot(slot, 0);
4489428a 1738
52c506f0
AH		 1739cleanup:
1740 if (slot->data && slot->data->cleanup)
1741 slot->data->cleanup(slot->data);
1742
c60a32cd 1743free:
b8c86fc5
PO		 1744 sdhci_free_host(host);
1745
1746 return ERR_PTR(ret);
1747}
1748
1749static void sdhci_pci_remove_slot(struct sdhci_pci_slot *slot)
1750{
1e72859e
PO		 1751 int dead;
1752 u32 scratch;
1753
c5e027a4
AH		 1754 sdhci_pci_remove_own_cd(slot);
1755
1e72859e
PO		 1756 dead = 0;
1757 scratch = readl(slot->host->ioaddr + SDHCI_INT_STATUS);
1758 if (scratch == (u32)-1)
1759 dead = 1;
1760
1761 sdhci_remove_host(slot->host, dead);
4489428a
PO		 1762
1763 if (slot->chip->fixes && slot->chip->fixes->remove_slot)
1e72859e 1764 slot->chip->fixes->remove_slot(slot, dead);
4489428a 1765
52c506f0
AH		 1766 if (slot->data && slot->data->cleanup)
1767 slot->data->cleanup(slot->data);
1768
b8c86fc5
PO		 1769 sdhci_free_host(slot->host);
1770}
1771
c3be1efd 1772static void sdhci_pci_runtime_pm_allow(struct device *dev)
66fd8ad5 1773{
00884b61 1774 pm_suspend_ignore_children(dev, 1);
66fd8ad5
AH		 1775 pm_runtime_set_autosuspend_delay(dev, 50);
1776 pm_runtime_use_autosuspend(dev);
00884b61
AH		 1777 pm_runtime_allow(dev);
1778 /* Stay active until mmc core scans for a card */
1779 pm_runtime_put_noidle(dev);
66fd8ad5
AH		 1780}
1781
6e0ee714 1782static void sdhci_pci_runtime_pm_forbid(struct device *dev)
66fd8ad5
AH		 1783{
1784 pm_runtime_forbid(dev);
1785 pm_runtime_get_noresume(dev);
1786}
1787
c3be1efd 1788static int sdhci_pci_probe(struct pci_dev *pdev,
b8c86fc5
PO		 1789 const struct pci_device_id *ent)
1790{
1791 struct sdhci_pci_chip *chip;
1792 struct sdhci_pci_slot *slot;
1793
cf5e23e1 1794 u8 slots, first_bar;
b8c86fc5
PO		 1795 int ret, i;
1796
1797 BUG_ON(pdev == NULL);
1798 BUG_ON(ent == NULL);
1799
b8c86fc5 1800 dev_info(&pdev->dev, "SDHCI controller found [%04x:%04x] (rev %x)\n",
cf5e23e1 1801 (int)pdev->vendor, (int)pdev->device, (int)pdev->revision);
b8c86fc5
PO		 1802
1803 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &slots);
1804 if (ret)
1805 return ret;
1806
1807 slots = PCI_SLOT_INFO_SLOTS(slots) + 1;
1808 dev_dbg(&pdev->dev, "found %d slot(s)\n", slots);
1809 if (slots == 0)
1810 return -ENODEV;
1811
1812 BUG_ON(slots > MAX_SLOTS);
1813
1814 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &first_bar);
1815 if (ret)
1816 return ret;
1817
1818 first_bar &= PCI_SLOT_INFO_FIRST_BAR_MASK;
1819
1820 if (first_bar > 5) {
1821 dev_err(&pdev->dev, "Invalid first BAR. Aborting.\n");
1822 return -ENODEV;
1823 }
1824
52ac7acf 1825 ret = pcim_enable_device(pdev);
b8c86fc5
PO		 1826 if (ret)
1827 return ret;
1828
52ac7acf
AS		 1829 chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL);
1830 if (!chip)
1831 return -ENOMEM;
b8c86fc5
PO		 1832
1833 chip->pdev = pdev;
b177bc91 1834 chip->fixes = (const struct sdhci_pci_fixes *)ent->driver_data;
c43fd774 1835 if (chip->fixes) {
22606405 1836 chip->quirks = chip->fixes->quirks;
f3c55a7b 1837 chip->quirks2 = chip->fixes->quirks2;
c43fd774
AH		 1838 chip->allow_runtime_pm = chip->fixes->allow_runtime_pm;
1839 }
b8c86fc5 1840 chip->num_slots = slots;
d38dcad4
AH		 1841 chip->pm_retune = true;
1842 chip->rpm_retune = true;
b8c86fc5
PO		 1843
1844 pci_set_drvdata(pdev, chip);
1845
22606405
PO		 1846 if (chip->fixes && chip->fixes->probe) {
1847 ret = chip->fixes->probe(chip);
1848 if (ret)
52ac7acf 1849 return ret;
22606405
PO		 1850 }
1851
225d85fe
AC		 1852 slots = chip->num_slots; /* Quirk may have changed this */
1853
b177bc91 1854 for (i = 0; i < slots; i++) {
52c506f0 1855 slot = sdhci_pci_probe_slot(pdev, chip, first_bar, i);
b8c86fc5 1856 if (IS_ERR(slot)) {
b177bc91 1857 for (i--; i >= 0; i--)
b8c86fc5 1858 sdhci_pci_remove_slot(chip->slots[i]);
52ac7acf 1859 return PTR_ERR(slot);
b8c86fc5
PO		 1860 }
1861
1862 chip->slots[i] = slot;
1863 }
1864
c43fd774
AH		 1865 if (chip->allow_runtime_pm)
1866 sdhci_pci_runtime_pm_allow(&pdev->dev);
66fd8ad5 1867
b8c86fc5 1868 return 0;
b8c86fc5
PO		 1869}
1870
6e0ee714 1871static void sdhci_pci_remove(struct pci_dev *pdev)
b8c86fc5
PO		 1872{
1873 int i;
52ac7acf 1874 struct sdhci_pci_chip *chip = pci_get_drvdata(pdev);
c43fd774 1875
52ac7acf
AS		 1876 if (chip->allow_runtime_pm)
1877 sdhci_pci_runtime_pm_forbid(&pdev->dev);
b8c86fc5 1878
52ac7acf
AS		 1879 for (i = 0; i < chip->num_slots; i++)
1880 sdhci_pci_remove_slot(chip->slots[i]);
b8c86fc5
PO		 1881}
1882
1883static struct pci_driver sdhci_driver = {
b177bc91 1884 .name = "sdhci-pci",
b8c86fc5 1885 .id_table = pci_ids,
b177bc91 1886 .probe = sdhci_pci_probe,
0433c143 1887 .remove = sdhci_pci_remove,
66fd8ad5
AH		 1888 .driver = {
1889 .pm = &sdhci_pci_pm_ops
1890 },
b8c86fc5
PO		 1891};
1892
acc69646 1893module_pci_driver(sdhci_driver);
b8c86fc5 1894
32710e8f 1895MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
b8c86fc5
PO		 1896MODULE_DESCRIPTION("Secure Digital Host Controller Interface PCI driver");
1897MODULE_LICENSE("GPL");
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