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mmc: sdhci: Add quirk to disable LED control
[mirror_ubuntu-eoan-kernel.git] / drivers / mmc / host / sdhci-pci-core.c
CommitLineData
b8c86fc5
PO		 1/* linux/drivers/mmc/host/sdhci-pci.c - SDHCI on PCI bus interface
2 *
3 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or (at
8 * your option) any later version.
9 *
10 * Thanks to the following companies for their support:
11 *
12 * - JMicron (hardware and technical support)
13 */
14
5305ec6a 15#include <linux/bitfield.h>
a72016a4 16#include <linux/string.h>
b8c86fc5
PO		 17#include <linux/delay.h>
18#include <linux/highmem.h>
88b47679 19#include <linux/module.h>
b8c86fc5
PO		 20#include <linux/pci.h>
21#include <linux/dma-mapping.h>
5a0e3ad6 22#include <linux/slab.h>
ccc92c23 23#include <linux/device.h>
b8c86fc5 24#include <linux/mmc/host.h>
e1bfad6d 25#include <linux/mmc/mmc.h>
b177bc91
AP		 26#include <linux/scatterlist.h>
27#include <linux/io.h>
0f201655 28#include <linux/gpio.h>
66fd8ad5 29#include <linux/pm_runtime.h>
ff59c520 30#include <linux/mmc/slot-gpio.h>
52c506f0 31#include <linux/mmc/sdhci-pci-data.h>
3f23df72 32#include <linux/acpi.h>
b8c86fc5 33
8ee82bda
AH		 34#include "cqhci.h"
35
b8c86fc5 36#include "sdhci.h"
522624f9 37#include "sdhci-pci.h"
22606405 38
fee686b7 39static void sdhci_pci_hw_reset(struct sdhci_host *host);
fee686b7 40
30cf2803 41#ifdef CONFIG_PM_SLEEP
5c3c6126
AH		 42static int sdhci_pci_init_wakeup(struct sdhci_pci_chip *chip)
43{
44 mmc_pm_flag_t pm_flags = 0;
d56ee1ff 45 bool cap_cd_wake = false;
5c3c6126
AH		 46 int i;
47
48 for (i = 0; i < chip->num_slots; i++) {
49 struct sdhci_pci_slot *slot = chip->slots[i];
50
d56ee1ff 51 if (slot) {
5c3c6126 52 pm_flags |= slot->host->mmc->pm_flags;
d56ee1ff
AH		 53 if (slot->host->mmc->caps & MMC_CAP_CD_WAKE)
54 cap_cd_wake = true;
55 }
5c3c6126
AH		 56 }
57
d56ee1ff
AH		 58 if ((pm_flags & MMC_PM_KEEP_POWER) && (pm_flags & MMC_PM_WAKE_SDIO_IRQ))
59 return device_wakeup_enable(&chip->pdev->dev);
60 else if (!cap_cd_wake)
61 return device_wakeup_disable(&chip->pdev->dev);
62
63 return 0;
5c3c6126
AH		 64}
65
66static int sdhci_pci_suspend_host(struct sdhci_pci_chip *chip)
30cf2803
AH		 67{
68 int i, ret;
69
5c3c6126
AH		 70 sdhci_pci_init_wakeup(chip);
71
30cf2803
AH		 72 for (i = 0; i < chip->num_slots; i++) {
73 struct sdhci_pci_slot *slot = chip->slots[i];
74 struct sdhci_host *host;
75
76 if (!slot)
77 continue;
78
79 host = slot->host;
80
81 if (chip->pm_retune && host->tuning_mode != SDHCI_TUNING_MODE_3)
82 mmc_retune_needed(host->mmc);
83
84 ret = sdhci_suspend_host(host);
85 if (ret)
86 goto err_pci_suspend;
d56ee1ff
AH		 87
88 if (device_may_wakeup(&chip->pdev->dev))
89 mmc_gpio_set_cd_wake(host->mmc, true);
30cf2803
AH		 90 }
91
92 return 0;
93
94err_pci_suspend:
95 while (--i >= 0)
96 sdhci_resume_host(chip->slots[i]->host);
97 return ret;
98}
99
30cf2803
AH		 100int sdhci_pci_resume_host(struct sdhci_pci_chip *chip)
101{
102 struct sdhci_pci_slot *slot;
103 int i, ret;
104
105 for (i = 0; i < chip->num_slots; i++) {
106 slot = chip->slots[i];
107 if (!slot)
108 continue;
109
110 ret = sdhci_resume_host(slot->host);
111 if (ret)
112 return ret;
d56ee1ff
AH		 113
114 mmc_gpio_set_cd_wake(slot->host->mmc, false);
30cf2803
AH		 115 }
116
117 return 0;
118}
8ee82bda
AH		 119
120static int sdhci_cqhci_suspend(struct sdhci_pci_chip *chip)
121{
122 int ret;
123
124 ret = cqhci_suspend(chip->slots[0]->host->mmc);
125 if (ret)
126 return ret;
127
128 return sdhci_pci_suspend_host(chip);
129}
130
131static int sdhci_cqhci_resume(struct sdhci_pci_chip *chip)
132{
133 int ret;
134
135 ret = sdhci_pci_resume_host(chip);
136 if (ret)
137 return ret;
138
139 return cqhci_resume(chip->slots[0]->host->mmc);
140}
30cf2803
AH		 141#endif
142
966d696a
AH		 143#ifdef CONFIG_PM
144static int sdhci_pci_runtime_suspend_host(struct sdhci_pci_chip *chip)
145{
146 struct sdhci_pci_slot *slot;
147 struct sdhci_host *host;
148 int i, ret;
149
150 for (i = 0; i < chip->num_slots; i++) {
151 slot = chip->slots[i];
152 if (!slot)
153 continue;
154
155 host = slot->host;
156
157 ret = sdhci_runtime_suspend_host(host);
158 if (ret)
159 goto err_pci_runtime_suspend;
160
161 if (chip->rpm_retune &&
162 host->tuning_mode != SDHCI_TUNING_MODE_3)
163 mmc_retune_needed(host->mmc);
164 }
165
166 return 0;
167
168err_pci_runtime_suspend:
169 while (--i >= 0)
170 sdhci_runtime_resume_host(chip->slots[i]->host);
171 return ret;
172}
173
174static int sdhci_pci_runtime_resume_host(struct sdhci_pci_chip *chip)
175{
176 struct sdhci_pci_slot *slot;
177 int i, ret;
178
179 for (i = 0; i < chip->num_slots; i++) {
180 slot = chip->slots[i];
181 if (!slot)
182 continue;
183
184 ret = sdhci_runtime_resume_host(slot->host);
185 if (ret)
186 return ret;
187 }
188
189 return 0;
190}
8ee82bda
AH		 191
192static int sdhci_cqhci_runtime_suspend(struct sdhci_pci_chip *chip)
193{
194 int ret;
195
196 ret = cqhci_suspend(chip->slots[0]->host->mmc);
197 if (ret)
198 return ret;
199
200 return sdhci_pci_runtime_suspend_host(chip);
201}
202
203static int sdhci_cqhci_runtime_resume(struct sdhci_pci_chip *chip)
204{
205 int ret;
206
207 ret = sdhci_pci_runtime_resume_host(chip);
208 if (ret)
209 return ret;
210
211 return cqhci_resume(chip->slots[0]->host->mmc);
212}
966d696a
AH		 213#endif
214
8ee82bda
AH		 215static u32 sdhci_cqhci_irq(struct sdhci_host *host, u32 intmask)
216{
217 int cmd_error = 0;
218 int data_error = 0;
219
220 if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error))
221 return intmask;
222
223 cqhci_irq(host->mmc, intmask, cmd_error, data_error);
224
225 return 0;
226}
227
228static void sdhci_pci_dumpregs(struct mmc_host *mmc)
229{
230 sdhci_dumpregs(mmc_priv(mmc));
231}
232
22606405
PO		 233/*****************************************************************************\
234 * *
235 * Hardware specific quirk handling *
236 * *
237\*****************************************************************************/
238
239static int ricoh_probe(struct sdhci_pci_chip *chip)
240{
c99436fb
CB		 241 if (chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG ||
242 chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SONY)
22606405 243 chip->quirks |= SDHCI_QUIRK_NO_CARD_NO_RESET;
ccc92c23
ML		 244 return 0;
245}
246
247static int ricoh_mmc_probe_slot(struct sdhci_pci_slot *slot)
248{
249 slot->host->caps =
250 ((0x21 << SDHCI_TIMEOUT_CLK_SHIFT)
251 & SDHCI_TIMEOUT_CLK_MASK) |
22606405 252
ccc92c23
ML		 253 ((0x21 << SDHCI_CLOCK_BASE_SHIFT)
254 & SDHCI_CLOCK_BASE_MASK) |
255
256 SDHCI_TIMEOUT_CLK_UNIT |
257 SDHCI_CAN_VDD_330 |
1a1f1f04 258 SDHCI_CAN_DO_HISPD |
ccc92c23
ML		 259 SDHCI_CAN_DO_SDMA;
260 return 0;
261}
262
b7813f0f 263#ifdef CONFIG_PM_SLEEP
ccc92c23
ML		 264static int ricoh_mmc_resume(struct sdhci_pci_chip *chip)
265{
266 /* Apply a delay to allow controller to settle */
267 /* Otherwise it becomes confused if card state changed
268 during suspend */
269 msleep(500);
30cf2803 270 return sdhci_pci_resume_host(chip);
22606405 271}
b7813f0f 272#endif
22606405
PO		 273
274static const struct sdhci_pci_fixes sdhci_ricoh = {
275 .probe = ricoh_probe,
84938294
VK		 276 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR |
277 SDHCI_QUIRK_FORCE_DMA |
278 SDHCI_QUIRK_CLOCK_BEFORE_RESET,
22606405
PO		 279};
280
ccc92c23
ML		 281static const struct sdhci_pci_fixes sdhci_ricoh_mmc = {
282 .probe_slot = ricoh_mmc_probe_slot,
b7813f0f 283#ifdef CONFIG_PM_SLEEP
ccc92c23 284 .resume = ricoh_mmc_resume,
b7813f0f 285#endif
ccc92c23
ML		 286 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR |
287 SDHCI_QUIRK_CLOCK_BEFORE_RESET |
288 SDHCI_QUIRK_NO_CARD_NO_RESET |
289 SDHCI_QUIRK_MISSING_CAPS
290};
291
22606405
PO		 292static const struct sdhci_pci_fixes sdhci_ene_712 = {
293 .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE |
294 SDHCI_QUIRK_BROKEN_DMA,
295};
296
297static const struct sdhci_pci_fixes sdhci_ene_714 = {
298 .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE |
299 SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS |
300 SDHCI_QUIRK_BROKEN_DMA,
301};
302
303static const struct sdhci_pci_fixes sdhci_cafe = {
304 .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER |
a0874897 305 SDHCI_QUIRK_NO_BUSY_IRQ |
55fc05b7 306 SDHCI_QUIRK_BROKEN_CARD_DETECTION |
ee53ab5d 307 SDHCI_QUIRK_BROKEN_TIMEOUT_VAL,
22606405
PO		 308};
309
43e968ce
DB		 310static const struct sdhci_pci_fixes sdhci_intel_qrk = {
311 .quirks = SDHCI_QUIRK_NO_HISPD_BIT,
312};
313
68077b02
ML		 314static int mrst_hc_probe_slot(struct sdhci_pci_slot *slot)
315{
316 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA;
317 return 0;
318}
319
f9ee3eab
AC		 320/*
321 * ADMA operation is disabled for Moorestown platform due to
322 * hardware bugs.
323 */
35ac6f08 324static int mrst_hc_probe(struct sdhci_pci_chip *chip)
f9ee3eab
AC		 325{
326 /*
35ac6f08
JP		 327 * slots number is fixed here for MRST as SDIO3/5 are never used and
328 * have hardware bugs.
f9ee3eab
AC		 329 */
330 chip->num_slots = 1;
331 return 0;
332}
333
296e0b03
AS		 334static int pch_hc_probe_slot(struct sdhci_pci_slot *slot)
335{
336 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA;
337 return 0;
338}
339
162d6f98 340#ifdef CONFIG_PM
66fd8ad5 341
c5e027a4 342static irqreturn_t sdhci_pci_sd_cd(int irq, void *dev_id)
66fd8ad5
AH		 343{
344 struct sdhci_pci_slot *slot = dev_id;
345 struct sdhci_host *host = slot->host;
346
347 mmc_detect_change(host->mmc, msecs_to_jiffies(200));
348 return IRQ_HANDLED;
349}
350
c5e027a4 351static void sdhci_pci_add_own_cd(struct sdhci_pci_slot *slot)
66fd8ad5 352{
c5e027a4 353 int err, irq, gpio = slot->cd_gpio;
66fd8ad5
AH		 354
355 slot->cd_gpio = -EINVAL;
356 slot->cd_irq = -EINVAL;
357
c5e027a4
AH		 358 if (!gpio_is_valid(gpio))
359 return;
360
c10bc372 361 err = devm_gpio_request(&slot->chip->pdev->dev, gpio, "sd_cd");
66fd8ad5
AH		 362 if (err < 0)
363 goto out;
364
365 err = gpio_direction_input(gpio);
366 if (err < 0)
367 goto out_free;
368
369 irq = gpio_to_irq(gpio);
370 if (irq < 0)
371 goto out_free;
372
c5e027a4 373 err = request_irq(irq, sdhci_pci_sd_cd, IRQF_TRIGGER_RISING |
66fd8ad5
AH		 374 IRQF_TRIGGER_FALLING, "sd_cd", slot);
375 if (err)
376 goto out_free;
377
378 slot->cd_gpio = gpio;
379 slot->cd_irq = irq;
66fd8ad5 380
c5e027a4 381 return;
66fd8ad5
AH		 382
383out_free:
c10bc372 384 devm_gpio_free(&slot->chip->pdev->dev, gpio);
66fd8ad5
AH		 385out:
386 dev_warn(&slot->chip->pdev->dev, "failed to setup card detect wake up\n");
66fd8ad5
AH		 387}
388
c5e027a4 389static void sdhci_pci_remove_own_cd(struct sdhci_pci_slot *slot)
66fd8ad5
AH		 390{
391 if (slot->cd_irq >= 0)
392 free_irq(slot->cd_irq, slot);
66fd8ad5
AH		 393}
394
395#else
396
c5e027a4
AH		 397static inline void sdhci_pci_add_own_cd(struct sdhci_pci_slot *slot)
398{
399}
400
401static inline void sdhci_pci_remove_own_cd(struct sdhci_pci_slot *slot)
402{
403}
66fd8ad5
AH		 404
405#endif
406
0d013bcf
AH		 407static int mfd_emmc_probe_slot(struct sdhci_pci_slot *slot)
408{
66fd8ad5 409 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE;
d2a47176 410 slot->host->mmc->caps2 |= MMC_CAP2_BOOTPART_NOACC;
0d013bcf
AH		 411 return 0;
412}
413
93933508
AH		 414static int mfd_sdio_probe_slot(struct sdhci_pci_slot *slot)
415{
012e4671 416 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE;
93933508
AH		 417 return 0;
418}
419
f9ee3eab
AC		 420static const struct sdhci_pci_fixes sdhci_intel_mrst_hc0 = {
421 .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT,
68077b02 422 .probe_slot = mrst_hc_probe_slot,
f9ee3eab
AC		 423};
424
35ac6f08 425static const struct sdhci_pci_fixes sdhci_intel_mrst_hc1_hc2 = {
f9ee3eab 426 .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT,
35ac6f08 427 .probe = mrst_hc_probe,
f9ee3eab
AC		 428};
429
29229052
XS		 430static const struct sdhci_pci_fixes sdhci_intel_mfd_sd = {
431 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
c43fd774 432 .allow_runtime_pm = true,
77a0122e 433 .own_cd_for_runtime_pm = true,
29229052
XS		 434};
435
0d013bcf
AH		 436static const struct sdhci_pci_fixes sdhci_intel_mfd_sdio = {
437 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
f3c55a7b 438 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON,
c43fd774 439 .allow_runtime_pm = true,
93933508 440 .probe_slot = mfd_sdio_probe_slot,
0d013bcf
AH		 441};
442
443static const struct sdhci_pci_fixes sdhci_intel_mfd_emmc = {
29229052 444 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
c43fd774 445 .allow_runtime_pm = true,
0d013bcf 446 .probe_slot = mfd_emmc_probe_slot,
29229052
XS		 447};
448
296e0b03
AS		 449static const struct sdhci_pci_fixes sdhci_intel_pch_sdio = {
450 .quirks = SDHCI_QUIRK_BROKEN_ADMA,
451 .probe_slot = pch_hc_probe_slot,
452};
453
c959a6b0
AH		 454enum {
455 INTEL_DSM_FNS = 0,
6ae03368 456 INTEL_DSM_V18_SWITCH = 3,
be17355a 457 INTEL_DSM_V33_SWITCH = 4,
51ced59c 458 INTEL_DSM_DRV_STRENGTH = 9,
c959a6b0
AH		 459 INTEL_DSM_D3_RETUNE = 10,
460};
461
462struct intel_host {
463 u32 dsm_fns;
51ced59c 464 int drv_strength;
c959a6b0 465 bool d3_retune;
5305ec6a
AH		 466 bool rpm_retune_ok;
467 u32 glk_rx_ctrl1;
468 u32 glk_tun_val;
c959a6b0
AH		 469};
470
c37f69ff 471static const guid_t intel_dsm_guid =
94116f81
AS		 472 GUID_INIT(0xF6C13EA5, 0x65CD, 0x461F,
473 0xAB, 0x7A, 0x29, 0xF7, 0xE8, 0xD5, 0xBD, 0x61);
c959a6b0
AH		 474
475static int __intel_dsm(struct intel_host *intel_host, struct device *dev,
476 unsigned int fn, u32 *result)
477{
478 union acpi_object *obj;
479 int err = 0;
a72016a4 480 size_t len;
c959a6b0 481
94116f81 482 obj = acpi_evaluate_dsm(ACPI_HANDLE(dev), &intel_dsm_guid, 0, fn, NULL);
c959a6b0
AH		 483 if (!obj)
484 return -EOPNOTSUPP;
485
486 if (obj->type != ACPI_TYPE_BUFFER || obj->buffer.length < 1) {
487 err = -EINVAL;
488 goto out;
489 }
490
a72016a4
AH		 491 len = min_t(size_t, obj->buffer.length, 4);
492
493 *result = 0;
494 memcpy(result, obj->buffer.pointer, len);
c959a6b0
AH		 495out:
496 ACPI_FREE(obj);
497
498 return err;
499}
500
501static int intel_dsm(struct intel_host *intel_host, struct device *dev,
502 unsigned int fn, u32 *result)
503{
504 if (fn > 31 || !(intel_host->dsm_fns & (1 << fn)))
505 return -EOPNOTSUPP;
506
507 return __intel_dsm(intel_host, dev, fn, result);
508}
509
510static void intel_dsm_init(struct intel_host *intel_host, struct device *dev,
511 struct mmc_host *mmc)
512{
513 int err;
514 u32 val;
515
eb701ce1
AH		 516 intel_host->d3_retune = true;
517
c959a6b0
AH		 518 err = __intel_dsm(intel_host, dev, INTEL_DSM_FNS, &intel_host->dsm_fns);
519 if (err) {
520 pr_debug("%s: DSM not supported, error %d\n",
521 mmc_hostname(mmc), err);
522 return;
523 }
524
525 pr_debug("%s: DSM function mask %#x\n",
526 mmc_hostname(mmc), intel_host->dsm_fns);
527
51ced59c
AH		 528 err = intel_dsm(intel_host, dev, INTEL_DSM_DRV_STRENGTH, &val);
529 intel_host->drv_strength = err ? 0 : val;
530
c959a6b0
AH		 531 err = intel_dsm(intel_host, dev, INTEL_DSM_D3_RETUNE, &val);
532 intel_host->d3_retune = err ? true : !!val;
533}
534
c9faff6c
AH		 535static void sdhci_pci_int_hw_reset(struct sdhci_host *host)
536{
537 u8 reg;
538
539 reg = sdhci_readb(host, SDHCI_POWER_CONTROL);
540 reg |= 0x10;
541 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL);
542 /* For eMMC, minimum is 1us but give it 9us for good measure */
543 udelay(9);
544 reg &= ~0x10;
545 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL);
546 /* For eMMC, minimum is 200us but give it 300us for good measure */
547 usleep_range(300, 1000);
548}
549
51ced59c
AH		 550static int intel_select_drive_strength(struct mmc_card *card,
551 unsigned int max_dtr, int host_drv,
552 int card_drv, int *drv_type)
e1bfad6d 553{
51ced59c
AH		 554 struct sdhci_host *host = mmc_priv(card->host);
555 struct sdhci_pci_slot *slot = sdhci_priv(host);
556 struct intel_host *intel_host = sdhci_pci_priv(slot);
e1bfad6d 557
51ced59c 558 return intel_host->drv_strength;
e1bfad6d
AH		 559}
560
163cbe31
AH		 561static int bxt_get_cd(struct mmc_host *mmc)
562{
563 int gpio_cd = mmc_gpio_get_cd(mmc);
564 struct sdhci_host *host = mmc_priv(mmc);
565 unsigned long flags;
566 int ret = 0;
567
568 if (!gpio_cd)
569 return 0;
570
163cbe31
AH		 571 spin_lock_irqsave(&host->lock, flags);
572
573 if (host->flags & SDHCI_DEVICE_DEAD)
574 goto out;
575
576 ret = !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
577out:
578 spin_unlock_irqrestore(&host->lock, flags);
579
163cbe31
AH		 580 return ret;
581}
582
48d685a2
AH		 583#define SDHCI_INTEL_PWR_TIMEOUT_CNT 20
584#define SDHCI_INTEL_PWR_TIMEOUT_UDELAY 100
585
586static void sdhci_intel_set_power(struct sdhci_host *host, unsigned char mode,
587 unsigned short vdd)
588{
589 int cntr;
590 u8 reg;
591
592 sdhci_set_power(host, mode, vdd);
593
594 if (mode == MMC_POWER_OFF)
595 return;
596
597 /*
598 * Bus power might not enable after D3 -> D0 transition due to the
599 * present state not yet having propagated. Retry for up to 2ms.
600 */
601 for (cntr = 0; cntr < SDHCI_INTEL_PWR_TIMEOUT_CNT; cntr++) {
602 reg = sdhci_readb(host, SDHCI_POWER_CONTROL);
603 if (reg & SDHCI_POWER_ON)
604 break;
605 udelay(SDHCI_INTEL_PWR_TIMEOUT_UDELAY);
606 reg |= SDHCI_POWER_ON;
607 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL);
608 }
609}
610
bc55dcd8
AH		 611#define INTEL_HS400_ES_REG 0x78
612#define INTEL_HS400_ES_BIT BIT(0)
613
614static void intel_hs400_enhanced_strobe(struct mmc_host *mmc,
615 struct mmc_ios *ios)
616{
617 struct sdhci_host *host = mmc_priv(mmc);
618 u32 val;
619
620 val = sdhci_readl(host, INTEL_HS400_ES_REG);
621 if (ios->enhanced_strobe)
622 val |= INTEL_HS400_ES_BIT;
623 else
624 val &= ~INTEL_HS400_ES_BIT;
625 sdhci_writel(host, val, INTEL_HS400_ES_REG);
626}
627
be17355a
AH		 628static int intel_start_signal_voltage_switch(struct mmc_host *mmc,
629 struct mmc_ios *ios)
6ae03368 630{
be17355a
AH		 631 struct device *dev = mmc_dev(mmc);
632 struct sdhci_host *host = mmc_priv(mmc);
6ae03368
AH		 633 struct sdhci_pci_slot *slot = sdhci_priv(host);
634 struct intel_host *intel_host = sdhci_pci_priv(slot);
be17355a 635 unsigned int fn;
6ae03368
AH		 636 u32 result = 0;
637 int err;
638
be17355a
AH		 639 err = sdhci_start_signal_voltage_switch(mmc, ios);
640 if (err)
641 return err;
642
643 switch (ios->signal_voltage) {
644 case MMC_SIGNAL_VOLTAGE_330:
645 fn = INTEL_DSM_V33_SWITCH;
646 break;
647 case MMC_SIGNAL_VOLTAGE_180:
648 fn = INTEL_DSM_V18_SWITCH;
649 break;
650 default:
651 return 0;
652 }
653
654 err = intel_dsm(intel_host, dev, fn, &result);
655 pr_debug("%s: %s DSM fn %u error %d result %u\n",
656 mmc_hostname(mmc), __func__, fn, err, result);
657
658 return 0;
6ae03368
AH		 659}
660
48d685a2
AH		 661static const struct sdhci_ops sdhci_intel_byt_ops = {
662 .set_clock = sdhci_set_clock,
663 .set_power = sdhci_intel_set_power,
664 .enable_dma = sdhci_pci_enable_dma,
adc16398 665 .set_bus_width = sdhci_set_bus_width,
48d685a2
AH		 666 .reset = sdhci_reset,
667 .set_uhs_signaling = sdhci_set_uhs_signaling,
668 .hw_reset = sdhci_pci_hw_reset,
669};
670
8ee82bda
AH		 671static const struct sdhci_ops sdhci_intel_glk_ops = {
672 .set_clock = sdhci_set_clock,
673 .set_power = sdhci_intel_set_power,
674 .enable_dma = sdhci_pci_enable_dma,
675 .set_bus_width = sdhci_set_bus_width,
676 .reset = sdhci_reset,
677 .set_uhs_signaling = sdhci_set_uhs_signaling,
678 .hw_reset = sdhci_pci_hw_reset,
8ee82bda
AH		 679 .irq = sdhci_cqhci_irq,
680};
681
c959a6b0
AH		 682static void byt_read_dsm(struct sdhci_pci_slot *slot)
683{
684 struct intel_host *intel_host = sdhci_pci_priv(slot);
685 struct device *dev = &slot->chip->pdev->dev;
686 struct mmc_host *mmc = slot->host->mmc;
687
688 intel_dsm_init(intel_host, dev, mmc);
689 slot->chip->rpm_retune = intel_host->d3_retune;
690}
691
f8870ae6
AH		 692static int intel_execute_tuning(struct mmc_host *mmc, u32 opcode)
693{
694 int err = sdhci_execute_tuning(mmc, opcode);
695 struct sdhci_host *host = mmc_priv(mmc);
696
697 if (err)
698 return err;
699
700 /*
701 * Tuning can leave the IP in an active state (Buffer Read Enable bit
702 * set) which prevents the entry to low power states (i.e. S0i3). Data
703 * reset will clear it.
704 */
705 sdhci_reset(host, SDHCI_RESET_DATA);
706
707 return 0;
708}
709
710static void byt_probe_slot(struct sdhci_pci_slot *slot)
728ef3d1 711{
f8870ae6 712 struct mmc_host_ops *ops = &slot->host->mmc_host_ops;
809090e8
AH		 713 struct device *dev = &slot->chip->pdev->dev;
714 struct mmc_host *mmc = slot->host->mmc;
f8870ae6 715
c959a6b0 716 byt_read_dsm(slot);
f8870ae6
AH		 717
718 ops->execute_tuning = intel_execute_tuning;
be17355a 719 ops->start_signal_voltage_switch = intel_start_signal_voltage_switch;
809090e8
AH		 720
721 device_property_read_u32(dev, "max-frequency", &mmc->f_max);
f8870ae6
AH		 722}
723
724static int byt_emmc_probe_slot(struct sdhci_pci_slot *slot)
725{
726 byt_probe_slot(slot);
c9faff6c 727 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE |
6aab23a8 728 MMC_CAP_HW_RESET | MMC_CAP_1_8V_DDR |
32828857 729 MMC_CAP_CMD_DURING_TFR |
6aab23a8 730 MMC_CAP_WAIT_WHILE_BUSY;
c9faff6c 731 slot->hw_reset = sdhci_pci_int_hw_reset;
a06586b6
AH		 732 if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BSW_EMMC)
733 slot->host->timeout_clk = 1000; /* 1000 kHz i.e. 1 MHz */
51ced59c
AH		 734 slot->host->mmc_host_ops.select_drive_strength =
735 intel_select_drive_strength;
728ef3d1
AH		 736 return 0;
737}
738
bc55dcd8
AH		 739static int glk_emmc_probe_slot(struct sdhci_pci_slot *slot)
740{
741 int ret = byt_emmc_probe_slot(slot);
742
8ee82bda
AH		 743 slot->host->mmc->caps2 |= MMC_CAP2_CQE;
744
bc55dcd8
AH		 745 if (slot->chip->pdev->device != PCI_DEVICE_ID_INTEL_GLK_EMMC) {
746 slot->host->mmc->caps2 |= MMC_CAP2_HS400_ES,
747 slot->host->mmc_host_ops.hs400_enhanced_strobe =
748 intel_hs400_enhanced_strobe;
8ee82bda 749 slot->host->mmc->caps2 |= MMC_CAP2_CQE_DCMD;
bc55dcd8
AH		 750 }
751
752 return ret;
753}
754
8ee82bda 755static const struct cqhci_host_ops glk_cqhci_ops = {
7b7d57fd 756 .enable = sdhci_cqe_enable,
8ee82bda
AH		 757 .disable = sdhci_cqe_disable,
758 .dumpregs = sdhci_pci_dumpregs,
759};
760
761static int glk_emmc_add_host(struct sdhci_pci_slot *slot)
762{
763 struct device *dev = &slot->chip->pdev->dev;
764 struct sdhci_host *host = slot->host;
765 struct cqhci_host *cq_host;
766 bool dma64;
767 int ret;
768
769 ret = sdhci_setup_host(host);
770 if (ret)
771 return ret;
772
773 cq_host = devm_kzalloc(dev, sizeof(*cq_host), GFP_KERNEL);
774 if (!cq_host) {
775 ret = -ENOMEM;
776 goto cleanup;
777 }
778
779 cq_host->mmio = host->ioaddr + 0x200;
780 cq_host->quirks |= CQHCI_QUIRK_SHORT_TXFR_DESC_SZ;
781 cq_host->ops = &glk_cqhci_ops;
782
783 dma64 = host->flags & SDHCI_USE_64_BIT_DMA;
784 if (dma64)
785 cq_host->caps |= CQHCI_TASK_DESC_SZ_128;
786
787 ret = cqhci_init(cq_host, host->mmc, dma64);
788 if (ret)
789 goto cleanup;
790
791 ret = __sdhci_add_host(host);
792 if (ret)
793 goto cleanup;
794
795 return 0;
796
797cleanup:
798 sdhci_cleanup_host(host);
799 return ret;
800}
801
5305ec6a
AH		 802#ifdef CONFIG_PM
803#define GLK_RX_CTRL1 0x834
804#define GLK_TUN_VAL 0x840
805#define GLK_PATH_PLL GENMASK(13, 8)
806#define GLK_DLY GENMASK(6, 0)
807/* Workaround firmware failing to restore the tuning value */
808static void glk_rpm_retune_wa(struct sdhci_pci_chip *chip, bool susp)
809{
810 struct sdhci_pci_slot *slot = chip->slots[0];
811 struct intel_host *intel_host = sdhci_pci_priv(slot);
812 struct sdhci_host *host = slot->host;
813 u32 glk_rx_ctrl1;
814 u32 glk_tun_val;
815 u32 dly;
816
817 if (intel_host->rpm_retune_ok || !mmc_can_retune(host->mmc))
818 return;
819
820 glk_rx_ctrl1 = sdhci_readl(host, GLK_RX_CTRL1);
821 glk_tun_val = sdhci_readl(host, GLK_TUN_VAL);
822
823 if (susp) {
824 intel_host->glk_rx_ctrl1 = glk_rx_ctrl1;
825 intel_host->glk_tun_val = glk_tun_val;
826 return;
827 }
828
829 if (!intel_host->glk_tun_val)
830 return;
831
832 if (glk_rx_ctrl1 != intel_host->glk_rx_ctrl1) {
833 intel_host->rpm_retune_ok = true;
834 return;
835 }
836
837 dly = FIELD_PREP(GLK_DLY, FIELD_GET(GLK_PATH_PLL, glk_rx_ctrl1) +
838 (intel_host->glk_tun_val << 1));
839 if (dly == FIELD_GET(GLK_DLY, glk_rx_ctrl1))
840 return;
841
842 glk_rx_ctrl1 = (glk_rx_ctrl1 & ~GLK_DLY) | dly;
843 sdhci_writel(host, glk_rx_ctrl1, GLK_RX_CTRL1);
844
845 intel_host->rpm_retune_ok = true;
846 chip->rpm_retune = true;
847 mmc_retune_needed(host->mmc);
848 pr_info("%s: Requiring re-tune after rpm resume", mmc_hostname(host->mmc));
849}
850
851static void glk_rpm_retune_chk(struct sdhci_pci_chip *chip, bool susp)
852{
853 if (chip->pdev->device == PCI_DEVICE_ID_INTEL_GLK_EMMC &&
854 !chip->rpm_retune)
855 glk_rpm_retune_wa(chip, susp);
856}
857
858static int glk_runtime_suspend(struct sdhci_pci_chip *chip)
859{
860 glk_rpm_retune_chk(chip, true);
861
862 return sdhci_cqhci_runtime_suspend(chip);
863}
864
865static int glk_runtime_resume(struct sdhci_pci_chip *chip)
866{
867 glk_rpm_retune_chk(chip, false);
868
869 return sdhci_cqhci_runtime_resume(chip);
870}
871#endif
872
3f23df72
ZB		 873#ifdef CONFIG_ACPI
874static int ni_set_max_freq(struct sdhci_pci_slot *slot)
875{
876 acpi_status status;
877 unsigned long long max_freq;
878
879 status = acpi_evaluate_integer(ACPI_HANDLE(&slot->chip->pdev->dev),
880 "MXFQ", NULL, &max_freq);
881 if (ACPI_FAILURE(status)) {
882 dev_err(&slot->chip->pdev->dev,
883 "MXFQ not found in acpi table\n");
884 return -EINVAL;
885 }
886
887 slot->host->mmc->f_max = max_freq * 1000000;
888
889 return 0;
890}
891#else
892static inline int ni_set_max_freq(struct sdhci_pci_slot *slot)
893{
894 return 0;
895}
896#endif
897
42b06496
ZB		 898static int ni_byt_sdio_probe_slot(struct sdhci_pci_slot *slot)
899{
3f23df72
ZB		 900 int err;
901
f8870ae6 902 byt_probe_slot(slot);
c959a6b0 903
3f23df72
ZB		 904 err = ni_set_max_freq(slot);
905 if (err)
906 return err;
907
42b06496
ZB		 908 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE |
909 MMC_CAP_WAIT_WHILE_BUSY;
910 return 0;
911}
912
728ef3d1
AH		 913static int byt_sdio_probe_slot(struct sdhci_pci_slot *slot)
914{
f8870ae6 915 byt_probe_slot(slot);
6aab23a8 916 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE |
6aab23a8 917 MMC_CAP_WAIT_WHILE_BUSY;
728ef3d1
AH		 918 return 0;
919}
920
ff59c520
AH		 921static int byt_sd_probe_slot(struct sdhci_pci_slot *slot)
922{
f8870ae6 923 byt_probe_slot(slot);
c2c49a2e 924 slot->host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY |
6cf4156c 925 MMC_CAP_AGGRESSIVE_PM | MMC_CAP_CD_WAKE;
ff59c520
AH		 926 slot->cd_idx = 0;
927 slot->cd_override_level = true;
163cbe31 928 if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BXT_SD ||
01d6b2a4 929 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BXTM_SD ||
2d1956d0 930 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_APL_SD ||
c2c49a2e 931 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_GLK_SD)
163cbe31
AH		 932 slot->host->mmc_host_ops.get_cd = bxt_get_cd;
933
bb26b841
KR		 934 if (slot->chip->pdev->subsystem_vendor == PCI_VENDOR_ID_NI &&
935 slot->chip->pdev->subsystem_device == PCI_SUBDEVICE_ID_NI_78E3)
936 slot->host->mmc->caps2 |= MMC_CAP2_AVOID_3_3V;
937
ff59c520
AH		 938 return 0;
939}
940
728ef3d1
AH		 941static const struct sdhci_pci_fixes sdhci_intel_byt_emmc = {
942 .allow_runtime_pm = true,
943 .probe_slot = byt_emmc_probe_slot,
db6e8cdf 944 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
e58e4a0d 945 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
b69587e2 946 SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 |
e58e4a0d 947 SDHCI_QUIRK2_STOP_WITH_TC,
fee686b7 948 .ops = &sdhci_intel_byt_ops,
c959a6b0 949 .priv_size = sizeof(struct intel_host),
728ef3d1
AH		 950};
951
bc55dcd8
AH		 952static const struct sdhci_pci_fixes sdhci_intel_glk_emmc = {
953 .allow_runtime_pm = true,
954 .probe_slot = glk_emmc_probe_slot,
8ee82bda
AH		 955 .add_host = glk_emmc_add_host,
956#ifdef CONFIG_PM_SLEEP
957 .suspend = sdhci_cqhci_suspend,
958 .resume = sdhci_cqhci_resume,
959#endif
960#ifdef CONFIG_PM
5305ec6a
AH		 961 .runtime_suspend = glk_runtime_suspend,
962 .runtime_resume = glk_runtime_resume,
8ee82bda 963#endif
bc55dcd8
AH		 964 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
965 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
966 SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 |
967 SDHCI_QUIRK2_STOP_WITH_TC,
8ee82bda 968 .ops = &sdhci_intel_glk_ops,
bc55dcd8
AH		 969 .priv_size = sizeof(struct intel_host),
970};
971
42b06496
ZB		 972static const struct sdhci_pci_fixes sdhci_ni_byt_sdio = {
973 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
974 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON |
975 SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
976 .allow_runtime_pm = true,
977 .probe_slot = ni_byt_sdio_probe_slot,
978 .ops = &sdhci_intel_byt_ops,
c959a6b0 979 .priv_size = sizeof(struct intel_host),
42b06496
ZB		 980};
981
728ef3d1 982static const struct sdhci_pci_fixes sdhci_intel_byt_sdio = {
db6e8cdf 983 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
b7574bad
GY		 984 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON |
985 SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
728ef3d1
AH		 986 .allow_runtime_pm = true,
987 .probe_slot = byt_sdio_probe_slot,
fee686b7 988 .ops = &sdhci_intel_byt_ops,
c959a6b0 989 .priv_size = sizeof(struct intel_host),
728ef3d1
AH		 990};
991
992static const struct sdhci_pci_fixes sdhci_intel_byt_sd = {
db6e8cdf 993 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
b7574bad 994 .quirks2 = SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON |
e58e4a0d
AH		 995 SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
996 SDHCI_QUIRK2_STOP_WITH_TC,
7396e318 997 .allow_runtime_pm = true,
77a0122e 998 .own_cd_for_runtime_pm = true,
ff59c520 999 .probe_slot = byt_sd_probe_slot,
fee686b7 1000 .ops = &sdhci_intel_byt_ops,
c959a6b0 1001 .priv_size = sizeof(struct intel_host),
728ef3d1
AH		 1002};
1003
8776a165 1004/* Define Host controllers for Intel Merrifield platform */
1f64cec2
AS		 1005#define INTEL_MRFLD_EMMC_0 0
1006#define INTEL_MRFLD_EMMC_1 1
4674b6c8 1007#define INTEL_MRFLD_SD 2
d5565577 1008#define INTEL_MRFLD_SDIO 3
8776a165 1009
0e39220e
AS		 1010#ifdef CONFIG_ACPI
1011static void intel_mrfld_mmc_fix_up_power_slot(struct sdhci_pci_slot *slot)
1012{
1013 struct acpi_device *device, *child;
1014
1015 device = ACPI_COMPANION(&slot->chip->pdev->dev);
1016 if (!device)
1017 return;
1018
1019 acpi_device_fix_up_power(device);
1020 list_for_each_entry(child, &device->children, node)
1021 if (child->status.present && child->status.enabled)
1022 acpi_device_fix_up_power(child);
1023}
1024#else
1025static inline void intel_mrfld_mmc_fix_up_power_slot(struct sdhci_pci_slot *slot) {}
1026#endif
1027
1f64cec2 1028static int intel_mrfld_mmc_probe_slot(struct sdhci_pci_slot *slot)
8776a165 1029{
2e57bbe2
AS		 1030 unsigned int func = PCI_FUNC(slot->chip->pdev->devfn);
1031
1032 switch (func) {
1033 case INTEL_MRFLD_EMMC_0:
1034 case INTEL_MRFLD_EMMC_1:
1035 slot->host->mmc->caps |= MMC_CAP_NONREMOVABLE |
1036 MMC_CAP_8_BIT_DATA |
1037 MMC_CAP_1_8V_DDR;
1038 break;
4674b6c8
AS		 1039 case INTEL_MRFLD_SD:
1040 slot->host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V;
1041 break;
d5565577 1042 case INTEL_MRFLD_SDIO:
2a609abe
AS		 1043 /* Advertise 2.0v for compatibility with the SDIO card's OCR */
1044 slot->host->ocr_mask = MMC_VDD_20_21 | MMC_VDD_165_195;
d5565577
AS		 1045 slot->host->mmc->caps |= MMC_CAP_NONREMOVABLE |
1046 MMC_CAP_POWER_OFF_CARD;
1047 break;
2e57bbe2 1048 default:
8776a165 1049 return -ENODEV;
2e57bbe2 1050 }
0e39220e
AS		 1051
1052 intel_mrfld_mmc_fix_up_power_slot(slot);
8776a165
DC		 1053 return 0;
1054}
1055
1f64cec2 1056static const struct sdhci_pci_fixes sdhci_intel_mrfld_mmc = {
8776a165 1057 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
b7574bad
GY		 1058 .quirks2 = SDHCI_QUIRK2_BROKEN_HS200 |
1059 SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
f1b55a55 1060 .allow_runtime_pm = true,
1f64cec2 1061 .probe_slot = intel_mrfld_mmc_probe_slot,
8776a165
DC		 1062};
1063
45211e21
PO		 1064static int jmicron_pmos(struct sdhci_pci_chip *chip, int on)
1065{
1066 u8 scratch;
1067 int ret;
1068
1069 ret = pci_read_config_byte(chip->pdev, 0xAE, &scratch);
1070 if (ret)
1071 return ret;
1072
1073 /*
1074 * Turn PMOS on [bit 0], set over current detection to 2.4 V
1075 * [bit 1:2] and enable over current debouncing [bit 6].
1076 */
1077 if (on)
1078 scratch |= 0x47;
1079 else
1080 scratch &= ~0x47;
1081
7582041f 1082 return pci_write_config_byte(chip->pdev, 0xAE, scratch);
45211e21
PO		 1083}
1084
1085static int jmicron_probe(struct sdhci_pci_chip *chip)
1086{
1087 int ret;
8f230f45 1088 u16 mmcdev = 0;
45211e21 1089
93fc48c7
PO		 1090 if (chip->pdev->revision == 0) {
1091 chip->quirks |= SDHCI_QUIRK_32BIT_DMA_ADDR |
1092 SDHCI_QUIRK_32BIT_DMA_SIZE |
2134a922 1093 SDHCI_QUIRK_32BIT_ADMA_SIZE |
4a3cba32 1094 SDHCI_QUIRK_RESET_AFTER_REQUEST |
86a6a874 1095 SDHCI_QUIRK_BROKEN_SMALL_PIO;
93fc48c7
PO		 1096 }
1097
4489428a
PO		 1098 /*
1099 * JMicron chips can have two interfaces to the same hardware
1100 * in order to work around limitations in Microsoft's driver.
1101 * We need to make sure we only bind to one of them.
1102 *
1103 * This code assumes two things:
1104 *
1105 * 1. The PCI code adds subfunctions in order.
1106 *
1107 * 2. The MMC interface has a lower subfunction number
1108 * than the SD interface.
1109 */
8f230f45
TI		 1110 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_SD)
1111 mmcdev = PCI_DEVICE_ID_JMICRON_JMB38X_MMC;
1112 else if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD)
1113 mmcdev = PCI_DEVICE_ID_JMICRON_JMB388_ESD;
1114
1115 if (mmcdev) {
4489428a
PO		 1116 struct pci_dev *sd_dev;
1117
1118 sd_dev = NULL;
1119 while ((sd_dev = pci_get_device(PCI_VENDOR_ID_JMICRON,
8f230f45 1120 mmcdev, sd_dev)) != NULL) {
4489428a
PO		 1121 if ((PCI_SLOT(chip->pdev->devfn) ==
1122 PCI_SLOT(sd_dev->devfn)) &&
1123 (chip->pdev->bus == sd_dev->bus))
1124 break;
1125 }
1126
1127 if (sd_dev) {
1128 pci_dev_put(sd_dev);
1129 dev_info(&chip->pdev->dev, "Refusing to bind to "
1130 "secondary interface.\n");
1131 return -ENODEV;
1132 }
1133 }
1134
45211e21
PO		 1135 /*
1136 * JMicron chips need a bit of a nudge to enable the power
1137 * output pins.
1138 */
1139 ret = jmicron_pmos(chip, 1);
1140 if (ret) {
1141 dev_err(&chip->pdev->dev, "Failure enabling card power\n");
1142 return ret;
1143 }
1144
82b0e23a
TI		 1145 /* quirk for unsable RO-detection on JM388 chips */
1146 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD ||
1147 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD)
1148 chip->quirks |= SDHCI_QUIRK_UNSTABLE_RO_DETECT;
1149
45211e21
PO		 1150 return 0;
1151}
1152
4489428a
PO		 1153static void jmicron_enable_mmc(struct sdhci_host *host, int on)
1154{
1155 u8 scratch;
1156
1157 scratch = readb(host->ioaddr + 0xC0);
1158
1159 if (on)
1160 scratch |= 0x01;
1161 else
1162 scratch &= ~0x01;
1163
1164 writeb(scratch, host->ioaddr + 0xC0);
1165}
1166
1167static int jmicron_probe_slot(struct sdhci_pci_slot *slot)
1168{
2134a922
PO		 1169 if (slot->chip->pdev->revision == 0) {
1170 u16 version;
1171
1172 version = readl(slot->host->ioaddr + SDHCI_HOST_VERSION);
1173 version = (version & SDHCI_VENDOR_VER_MASK) >>
1174 SDHCI_VENDOR_VER_SHIFT;
1175
1176 /*
1177 * Older versions of the chip have lots of nasty glitches
1178 * in the ADMA engine. It's best just to avoid it
1179 * completely.
1180 */
1181 if (version < 0xAC)
1182 slot->host->quirks |= SDHCI_QUIRK_BROKEN_ADMA;
1183 }
1184
8f230f45
TI		 1185 /* JM388 MMC doesn't support 1.8V while SD supports it */
1186 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) {
1187 slot->host->ocr_avail_sd = MMC_VDD_32_33 | MMC_VDD_33_34 |
1188 MMC_VDD_29_30 | MMC_VDD_30_31 |
1189 MMC_VDD_165_195; /* allow 1.8V */
1190 slot->host->ocr_avail_mmc = MMC_VDD_32_33 | MMC_VDD_33_34 |
1191 MMC_VDD_29_30 | MMC_VDD_30_31; /* no 1.8V for MMC */
1192 }
1193
4489428a
PO		 1194 /*
1195 * The secondary interface requires a bit set to get the
1196 * interrupts.
1197 */
8f230f45
TI		 1198 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
1199 slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD)
4489428a
PO		 1200 jmicron_enable_mmc(slot->host, 1);
1201
d75c1084
TI		 1202 slot->host->mmc->caps |= MMC_CAP_BUS_WIDTH_TEST;
1203
4489428a
PO		 1204 return 0;
1205}
1206
1e72859e 1207static void jmicron_remove_slot(struct sdhci_pci_slot *slot, int dead)
4489428a 1208{
1e72859e
PO		 1209 if (dead)
1210 return;
1211
8f230f45
TI		 1212 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
1213 slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD)
4489428a
PO		 1214 jmicron_enable_mmc(slot->host, 0);
1215}
1216
b7813f0f 1217#ifdef CONFIG_PM_SLEEP
29495aa0 1218static int jmicron_suspend(struct sdhci_pci_chip *chip)
4489428a 1219{
30cf2803
AH		 1220 int i, ret;
1221
5c3c6126 1222 ret = sdhci_pci_suspend_host(chip);
30cf2803
AH		 1223 if (ret)
1224 return ret;
4489428a 1225
8f230f45
TI		 1226 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
1227 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) {
b177bc91 1228 for (i = 0; i < chip->num_slots; i++)
4489428a
PO		 1229 jmicron_enable_mmc(chip->slots[i]->host, 0);
1230 }
1231
1232 return 0;
1233}
1234
45211e21
PO		 1235static int jmicron_resume(struct sdhci_pci_chip *chip)
1236{
4489428a
PO		 1237 int ret, i;
1238
8f230f45
TI		 1239 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
1240 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) {
b177bc91 1241 for (i = 0; i < chip->num_slots; i++)
4489428a
PO		 1242 jmicron_enable_mmc(chip->slots[i]->host, 1);
1243 }
45211e21
PO		 1244
1245 ret = jmicron_pmos(chip, 1);
1246 if (ret) {
1247 dev_err(&chip->pdev->dev, "Failure enabling card power\n");
1248 return ret;
1249 }
1250
30cf2803 1251 return sdhci_pci_resume_host(chip);
45211e21 1252}
b7813f0f 1253#endif
45211e21 1254
26daa1ed 1255static const struct sdhci_pci_fixes sdhci_o2 = {
01acf691
AL		 1256 .probe = sdhci_pci_o2_probe,
1257 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
143b648d 1258 .quirks2 = SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD,
01acf691 1259 .probe_slot = sdhci_pci_o2_probe_slot,
b7813f0f 1260#ifdef CONFIG_PM_SLEEP
01acf691 1261 .resume = sdhci_pci_o2_resume,
b7813f0f 1262#endif
26daa1ed
JL		 1263};
1264
22606405 1265static const struct sdhci_pci_fixes sdhci_jmicron = {
45211e21
PO		 1266 .probe = jmicron_probe,
1267
4489428a
PO		 1268 .probe_slot = jmicron_probe_slot,
1269 .remove_slot = jmicron_remove_slot,
1270
b7813f0f 1271#ifdef CONFIG_PM_SLEEP
4489428a 1272 .suspend = jmicron_suspend,
45211e21 1273 .resume = jmicron_resume,
b7813f0f 1274#endif
22606405
PO		 1275};
1276
a7a6186c
NP		 1277/* SysKonnect CardBus2SDIO extra registers */
1278#define SYSKT_CTRL 0x200
1279#define SYSKT_RDFIFO_STAT 0x204
1280#define SYSKT_WRFIFO_STAT 0x208
1281#define SYSKT_POWER_DATA 0x20c
1282#define SYSKT_POWER_330 0xef
1283#define SYSKT_POWER_300 0xf8
1284#define SYSKT_POWER_184 0xcc
1285#define SYSKT_POWER_CMD 0x20d
1286#define SYSKT_POWER_START (1 << 7)
1287#define SYSKT_POWER_STATUS 0x20e
1288#define SYSKT_POWER_STATUS_OK (1 << 0)
1289#define SYSKT_BOARD_REV 0x210
1290#define SYSKT_CHIP_REV 0x211
1291#define SYSKT_CONF_DATA 0x212
1292#define SYSKT_CONF_DATA_1V8 (1 << 2)
1293#define SYSKT_CONF_DATA_2V5 (1 << 1)
1294#define SYSKT_CONF_DATA_3V3 (1 << 0)
1295
1296static int syskt_probe(struct sdhci_pci_chip *chip)
1297{
1298 if ((chip->pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) {
1299 chip->pdev->class &= ~0x0000FF;
1300 chip->pdev->class |= PCI_SDHCI_IFDMA;
1301 }
1302 return 0;
1303}
1304
1305static int syskt_probe_slot(struct sdhci_pci_slot *slot)
1306{
1307 int tm, ps;
1308
1309 u8 board_rev = readb(slot->host->ioaddr + SYSKT_BOARD_REV);
1310 u8 chip_rev = readb(slot->host->ioaddr + SYSKT_CHIP_REV);
1311 dev_info(&slot->chip->pdev->dev, "SysKonnect CardBus2SDIO, "
1312 "board rev %d.%d, chip rev %d.%d\n",
1313 board_rev >> 4, board_rev & 0xf,
1314 chip_rev >> 4, chip_rev & 0xf);
1315 if (chip_rev >= 0x20)
1316 slot->host->quirks |= SDHCI_QUIRK_FORCE_DMA;
1317
1318 writeb(SYSKT_POWER_330, slot->host->ioaddr + SYSKT_POWER_DATA);
1319 writeb(SYSKT_POWER_START, slot->host->ioaddr + SYSKT_POWER_CMD);
1320 udelay(50);
1321 tm = 10; /* Wait max 1 ms */
1322 do {
1323 ps = readw(slot->host->ioaddr + SYSKT_POWER_STATUS);
1324 if (ps & SYSKT_POWER_STATUS_OK)
1325 break;
1326 udelay(100);
1327 } while (--tm);
1328 if (!tm) {
1329 dev_err(&slot->chip->pdev->dev,
1330 "power regulator never stabilized");
1331 writeb(0, slot->host->ioaddr + SYSKT_POWER_CMD);
1332 return -ENODEV;
1333 }
1334
1335 return 0;
1336}
1337
1338static const struct sdhci_pci_fixes sdhci_syskt = {
1339 .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER,
1340 .probe = syskt_probe,
1341 .probe_slot = syskt_probe_slot,
1342};
1343
557b0697
HW		 1344static int via_probe(struct sdhci_pci_chip *chip)
1345{
1346 if (chip->pdev->revision == 0x10)
1347 chip->quirks |= SDHCI_QUIRK_DELAY_AFTER_POWER;
1348
1349 return 0;
1350}
1351
1352static const struct sdhci_pci_fixes sdhci_via = {
1353 .probe = via_probe,
1354};
1355
9107ebbf
MC		 1356static int rtsx_probe_slot(struct sdhci_pci_slot *slot)
1357{
1358 slot->host->mmc->caps2 |= MMC_CAP2_HS200;
1359 return 0;
1360}
1361
1362static const struct sdhci_pci_fixes sdhci_rtsx = {
1363 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
e30b978f 1364 SDHCI_QUIRK2_BROKEN_64_BIT_DMA |
9107ebbf
MC		 1365 SDHCI_QUIRK2_BROKEN_DDR50,
1366 .probe_slot = rtsx_probe_slot,
1367};
1368
b5e97d6e
VW		 1369/*AMD chipset generation*/
1370enum amd_chipset_gen {
1371 AMD_CHIPSET_BEFORE_ML,
1372 AMD_CHIPSET_CZ,
1373 AMD_CHIPSET_NL,
1374 AMD_CHIPSET_UNKNOWN,
1375};
1376
c31165d7
SS		 1377/* AMD registers */
1378#define AMD_SD_AUTO_PATTERN 0xB8
1379#define AMD_MSLEEP_DURATION 4
1380#define AMD_SD_MISC_CONTROL 0xD0
1381#define AMD_MAX_TUNE_VALUE 0x0B
1382#define AMD_AUTO_TUNE_SEL 0x10800
1383#define AMD_FIFO_PTR 0x30
1384#define AMD_BIT_MASK 0x1F
1385
1386static void amd_tuning_reset(struct sdhci_host *host)
1387{
1388 unsigned int val;
1389
1390 val = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1391 val |= SDHCI_CTRL_PRESET_VAL_ENABLE | SDHCI_CTRL_EXEC_TUNING;
1392 sdhci_writew(host, val, SDHCI_HOST_CONTROL2);
1393
1394 val = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1395 val &= ~SDHCI_CTRL_EXEC_TUNING;
1396 sdhci_writew(host, val, SDHCI_HOST_CONTROL2);
1397}
1398
1399static void amd_config_tuning_phase(struct pci_dev *pdev, u8 phase)
1400{
1401 unsigned int val;
1402
1403 pci_read_config_dword(pdev, AMD_SD_AUTO_PATTERN, &val);
1404 val &= ~AMD_BIT_MASK;
1405 val |= (AMD_AUTO_TUNE_SEL | (phase << 1));
1406 pci_write_config_dword(pdev, AMD_SD_AUTO_PATTERN, val);
1407}
1408
1409static void amd_enable_manual_tuning(struct pci_dev *pdev)
1410{
1411 unsigned int val;
1412
1413 pci_read_config_dword(pdev, AMD_SD_MISC_CONTROL, &val);
1414 val |= AMD_FIFO_PTR;
1415 pci_write_config_dword(pdev, AMD_SD_MISC_CONTROL, val);
1416}
1417
300ad899 1418static int amd_execute_tuning_hs200(struct sdhci_host *host, u32 opcode)
c31165d7
SS		 1419{
1420 struct sdhci_pci_slot *slot = sdhci_priv(host);
1421 struct pci_dev *pdev = slot->chip->pdev;
1422 u8 valid_win = 0;
1423 u8 valid_win_max = 0;
1424 u8 valid_win_end = 0;
1425 u8 ctrl, tune_around;
1426
1427 amd_tuning_reset(host);
1428
1429 for (tune_around = 0; tune_around < 12; tune_around++) {
1430 amd_config_tuning_phase(pdev, tune_around);
1431
1432 if (mmc_send_tuning(host->mmc, opcode, NULL)) {
1433 valid_win = 0;
1434 msleep(AMD_MSLEEP_DURATION);
1435 ctrl = SDHCI_RESET_CMD | SDHCI_RESET_DATA;
1436 sdhci_writeb(host, ctrl, SDHCI_SOFTWARE_RESET);
1437 } else if (++valid_win > valid_win_max) {
1438 valid_win_max = valid_win;
1439 valid_win_end = tune_around;
1440 }
1441 }
1442
1443 if (!valid_win_max) {
1444 dev_err(&pdev->dev, "no tuning point found\n");
1445 return -EIO;
1446 }
1447
1448 amd_config_tuning_phase(pdev, valid_win_end - valid_win_max / 2);
1449
1450 amd_enable_manual_tuning(pdev);
1451
1452 host->mmc->retune_period = 0;
1453
1454 return 0;
1455}
1456
300ad899
DK		 1457static int amd_execute_tuning(struct mmc_host *mmc, u32 opcode)
1458{
1459 struct sdhci_host *host = mmc_priv(mmc);
1460
1461 /* AMD requires custom HS200 tuning */
1462 if (host->timing == MMC_TIMING_MMC_HS200)
1463 return amd_execute_tuning_hs200(host, opcode);
1464
1465 /* Otherwise perform standard SDHCI tuning */
1466 return sdhci_execute_tuning(mmc, opcode);
1467}
1468
1469static int amd_probe_slot(struct sdhci_pci_slot *slot)
1470{
1471 struct mmc_host_ops *ops = &slot->host->mmc_host_ops;
1472
1473 ops->execute_tuning = amd_execute_tuning;
1474
1475 return 0;
1476}
1477
d44f88da
VW		 1478static int amd_probe(struct sdhci_pci_chip *chip)
1479{
1480 struct pci_dev *smbus_dev;
b5e97d6e 1481 enum amd_chipset_gen gen;
d44f88da
VW		 1482
1483 smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD,
1484 PCI_DEVICE_ID_AMD_HUDSON2_SMBUS, NULL);
b5e97d6e
VW		 1485 if (smbus_dev) {
1486 gen = AMD_CHIPSET_BEFORE_ML;
1487 } else {
1488 smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD,
1489 PCI_DEVICE_ID_AMD_KERNCZ_SMBUS, NULL);
1490 if (smbus_dev) {
1491 if (smbus_dev->revision < 0x51)
1492 gen = AMD_CHIPSET_CZ;
1493 else
1494 gen = AMD_CHIPSET_NL;
1495 } else {
1496 gen = AMD_CHIPSET_UNKNOWN;
1497 }
1498 }
d44f88da 1499
c31165d7 1500 if (gen == AMD_CHIPSET_BEFORE_ML || gen == AMD_CHIPSET_CZ)
d44f88da
VW		 1501 chip->quirks2 |= SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD;
1502
1503 return 0;
1504}
1505
c31165d7
SS		 1506static const struct sdhci_ops amd_sdhci_pci_ops = {
1507 .set_clock = sdhci_set_clock,
1508 .enable_dma = sdhci_pci_enable_dma,
adc16398 1509 .set_bus_width = sdhci_set_bus_width,
c31165d7
SS		 1510 .reset = sdhci_reset,
1511 .set_uhs_signaling = sdhci_set_uhs_signaling,
c31165d7
SS		 1512};
1513
d44f88da
VW		 1514static const struct sdhci_pci_fixes sdhci_amd = {
1515 .probe = amd_probe,
c31165d7 1516 .ops = &amd_sdhci_pci_ops,
300ad899 1517 .probe_slot = amd_probe_slot,
d44f88da
VW		 1518};
1519
9647f84d 1520static const struct pci_device_id pci_ids[] = {
c949c907
MK		 1521 SDHCI_PCI_DEVICE(RICOH, R5C822, ricoh),
1522 SDHCI_PCI_DEVICE(RICOH, R5C843, ricoh_mmc),
1523 SDHCI_PCI_DEVICE(RICOH, R5CE822, ricoh_mmc),
1524 SDHCI_PCI_DEVICE(RICOH, R5CE823, ricoh_mmc),
1525 SDHCI_PCI_DEVICE(ENE, CB712_SD, ene_712),
1526 SDHCI_PCI_DEVICE(ENE, CB712_SD_2, ene_712),
1527 SDHCI_PCI_DEVICE(ENE, CB714_SD, ene_714),
1528 SDHCI_PCI_DEVICE(ENE, CB714_SD_2, ene_714),
1529 SDHCI_PCI_DEVICE(MARVELL, 88ALP01_SD, cafe),
1530 SDHCI_PCI_DEVICE(JMICRON, JMB38X_SD, jmicron),
1531 SDHCI_PCI_DEVICE(JMICRON, JMB38X_MMC, jmicron),
1532 SDHCI_PCI_DEVICE(JMICRON, JMB388_SD, jmicron),
1533 SDHCI_PCI_DEVICE(JMICRON, JMB388_ESD, jmicron),
1534 SDHCI_PCI_DEVICE(SYSKONNECT, 8000, syskt),
1535 SDHCI_PCI_DEVICE(VIA, 95D0, via),
1536 SDHCI_PCI_DEVICE(REALTEK, 5250, rtsx),
1537 SDHCI_PCI_DEVICE(INTEL, QRK_SD, intel_qrk),
1538 SDHCI_PCI_DEVICE(INTEL, MRST_SD0, intel_mrst_hc0),
1539 SDHCI_PCI_DEVICE(INTEL, MRST_SD1, intel_mrst_hc1_hc2),
1540 SDHCI_PCI_DEVICE(INTEL, MRST_SD2, intel_mrst_hc1_hc2),
1541 SDHCI_PCI_DEVICE(INTEL, MFD_SD, intel_mfd_sd),
1542 SDHCI_PCI_DEVICE(INTEL, MFD_SDIO1, intel_mfd_sdio),
1543 SDHCI_PCI_DEVICE(INTEL, MFD_SDIO2, intel_mfd_sdio),
1544 SDHCI_PCI_DEVICE(INTEL, MFD_EMMC0, intel_mfd_emmc),
1545 SDHCI_PCI_DEVICE(INTEL, MFD_EMMC1, intel_mfd_emmc),
1546 SDHCI_PCI_DEVICE(INTEL, PCH_SDIO0, intel_pch_sdio),
1547 SDHCI_PCI_DEVICE(INTEL, PCH_SDIO1, intel_pch_sdio),
1548 SDHCI_PCI_DEVICE(INTEL, BYT_EMMC, intel_byt_emmc),
1549 SDHCI_PCI_SUBDEVICE(INTEL, BYT_SDIO, NI, 7884, ni_byt_sdio),
1550 SDHCI_PCI_DEVICE(INTEL, BYT_SDIO, intel_byt_sdio),
1551 SDHCI_PCI_DEVICE(INTEL, BYT_SD, intel_byt_sd),
1552 SDHCI_PCI_DEVICE(INTEL, BYT_EMMC2, intel_byt_emmc),
1553 SDHCI_PCI_DEVICE(INTEL, BSW_EMMC, intel_byt_emmc),
1554 SDHCI_PCI_DEVICE(INTEL, BSW_SDIO, intel_byt_sdio),
1555 SDHCI_PCI_DEVICE(INTEL, BSW_SD, intel_byt_sd),
1556 SDHCI_PCI_DEVICE(INTEL, CLV_SDIO0, intel_mfd_sd),
1557 SDHCI_PCI_DEVICE(INTEL, CLV_SDIO1, intel_mfd_sdio),
1558 SDHCI_PCI_DEVICE(INTEL, CLV_SDIO2, intel_mfd_sdio),
1559 SDHCI_PCI_DEVICE(INTEL, CLV_EMMC0, intel_mfd_emmc),
1560 SDHCI_PCI_DEVICE(INTEL, CLV_EMMC1, intel_mfd_emmc),
1561 SDHCI_PCI_DEVICE(INTEL, MRFLD_MMC, intel_mrfld_mmc),
1562 SDHCI_PCI_DEVICE(INTEL, SPT_EMMC, intel_byt_emmc),
1563 SDHCI_PCI_DEVICE(INTEL, SPT_SDIO, intel_byt_sdio),
1564 SDHCI_PCI_DEVICE(INTEL, SPT_SD, intel_byt_sd),
1565 SDHCI_PCI_DEVICE(INTEL, DNV_EMMC, intel_byt_emmc),
cdaba732 1566 SDHCI_PCI_DEVICE(INTEL, CDF_EMMC, intel_glk_emmc),
c949c907
MK		 1567 SDHCI_PCI_DEVICE(INTEL, BXT_EMMC, intel_byt_emmc),
1568 SDHCI_PCI_DEVICE(INTEL, BXT_SDIO, intel_byt_sdio),
1569 SDHCI_PCI_DEVICE(INTEL, BXT_SD, intel_byt_sd),
1570 SDHCI_PCI_DEVICE(INTEL, BXTM_EMMC, intel_byt_emmc),
1571 SDHCI_PCI_DEVICE(INTEL, BXTM_SDIO, intel_byt_sdio),
1572 SDHCI_PCI_DEVICE(INTEL, BXTM_SD, intel_byt_sd),
1573 SDHCI_PCI_DEVICE(INTEL, APL_EMMC, intel_byt_emmc),
1574 SDHCI_PCI_DEVICE(INTEL, APL_SDIO, intel_byt_sdio),
1575 SDHCI_PCI_DEVICE(INTEL, APL_SD, intel_byt_sd),
bc55dcd8 1576 SDHCI_PCI_DEVICE(INTEL, GLK_EMMC, intel_glk_emmc),
c949c907
MK		 1577 SDHCI_PCI_DEVICE(INTEL, GLK_SDIO, intel_byt_sdio),
1578 SDHCI_PCI_DEVICE(INTEL, GLK_SD, intel_byt_sd),
bc55dcd8
AH		 1579 SDHCI_PCI_DEVICE(INTEL, CNP_EMMC, intel_glk_emmc),
1580 SDHCI_PCI_DEVICE(INTEL, CNP_SD, intel_byt_sd),
1581 SDHCI_PCI_DEVICE(INTEL, CNPH_SD, intel_byt_sd),
5637ffad
AH		 1582 SDHCI_PCI_DEVICE(INTEL, ICP_EMMC, intel_glk_emmc),
1583 SDHCI_PCI_DEVICE(INTEL, ICP_SD, intel_byt_sd),
c949c907
MK		 1584 SDHCI_PCI_DEVICE(O2, 8120, o2),
1585 SDHCI_PCI_DEVICE(O2, 8220, o2),
1586 SDHCI_PCI_DEVICE(O2, 8221, o2),
1587 SDHCI_PCI_DEVICE(O2, 8320, o2),
1588 SDHCI_PCI_DEVICE(O2, 8321, o2),
1589 SDHCI_PCI_DEVICE(O2, FUJIN2, o2),
1590 SDHCI_PCI_DEVICE(O2, SDS0, o2),
1591 SDHCI_PCI_DEVICE(O2, SDS1, o2),
1592 SDHCI_PCI_DEVICE(O2, SEABIRD0, o2),
1593 SDHCI_PCI_DEVICE(O2, SEABIRD1, o2),
d72d72cd 1594 SDHCI_PCI_DEVICE(ARASAN, PHY_EMMC, arasan),
152f8204 1595 SDHCI_PCI_DEVICE(SYNOPSYS, DWC_MSHC, snps),
c949c907
MK		 1596 SDHCI_PCI_DEVICE_CLASS(AMD, SYSTEM_SDHCI, PCI_CLASS_MASK, amd),
1597 /* Generic SD host controller */
1598 {PCI_DEVICE_CLASS(SYSTEM_SDHCI, PCI_CLASS_MASK)},
b8c86fc5
PO		 1599 { /* end: all zeroes */ },
1600};
1601
1602MODULE_DEVICE_TABLE(pci, pci_ids);
1603
b8c86fc5
PO		 1604/*****************************************************************************\
1605 * *
1606 * SDHCI core callbacks *
1607 * *
1608\*****************************************************************************/
1609
d72d72cd 1610int sdhci_pci_enable_dma(struct sdhci_host *host)
b8c86fc5
PO		 1611{
1612 struct sdhci_pci_slot *slot;
1613 struct pci_dev *pdev;
b8c86fc5
PO		 1614
1615 slot = sdhci_priv(host);
1616 pdev = slot->chip->pdev;
1617
1618 if (((pdev->class & 0xFFFF00) == (PCI_CLASS_SYSTEM_SDHCI << 8)) &&
1619 ((pdev->class & 0x0000FF) != PCI_SDHCI_IFDMA) &&
a13abc7b 1620 (host->flags & SDHCI_USE_SDMA)) {
b8c86fc5
PO		 1621 dev_warn(&pdev->dev, "Will use DMA mode even though HW "
1622 "doesn't fully claim to support it.\n");
1623 }
1624
b8c86fc5
PO		 1625 pci_set_master(pdev);
1626
1627 return 0;
1628}
1629
c9faff6c 1630static void sdhci_pci_gpio_hw_reset(struct sdhci_host *host)
0f201655
AH		 1631{
1632 struct sdhci_pci_slot *slot = sdhci_priv(host);
1633 int rst_n_gpio = slot->rst_n_gpio;
1634
1635 if (!gpio_is_valid(rst_n_gpio))
1636 return;
1637 gpio_set_value_cansleep(rst_n_gpio, 0);
1638 /* For eMMC, minimum is 1us but give it 10us for good measure */
1639 udelay(10);
1640 gpio_set_value_cansleep(rst_n_gpio, 1);
1641 /* For eMMC, minimum is 200us but give it 300us for good measure */
1642 usleep_range(300, 1000);
1643}
1644
c9faff6c
AH		 1645static void sdhci_pci_hw_reset(struct sdhci_host *host)
1646{
1647 struct sdhci_pci_slot *slot = sdhci_priv(host);
1648
1649 if (slot->hw_reset)
1650 slot->hw_reset(host);
1651}
1652
c915568d 1653static const struct sdhci_ops sdhci_pci_ops = {
1771059c 1654 .set_clock = sdhci_set_clock,
b8c86fc5 1655 .enable_dma = sdhci_pci_enable_dma,
adc16398 1656 .set_bus_width = sdhci_set_bus_width,
03231f9b 1657 .reset = sdhci_reset,
96d7b78c 1658 .set_uhs_signaling = sdhci_set_uhs_signaling,
0f201655 1659 .hw_reset = sdhci_pci_hw_reset,
b8c86fc5
PO		 1660};
1661
1662/*****************************************************************************\
1663 * *
1664 * Suspend/resume *
1665 * *
1666\*****************************************************************************/
1667
f9900f15 1668#ifdef CONFIG_PM_SLEEP
29495aa0 1669static int sdhci_pci_suspend(struct device *dev)
b8c86fc5 1670{
29495aa0 1671 struct pci_dev *pdev = to_pci_dev(dev);
30cf2803 1672 struct sdhci_pci_chip *chip = pci_get_drvdata(pdev);
b8c86fc5 1673
b8c86fc5
PO		 1674 if (!chip)
1675 return 0;
1676
30cf2803
AH		 1677 if (chip->fixes && chip->fixes->suspend)
1678 return chip->fixes->suspend(chip);
b8c86fc5 1679
30cf2803 1680 return sdhci_pci_suspend_host(chip);
b8c86fc5
PO		 1681}
1682
29495aa0 1683static int sdhci_pci_resume(struct device *dev)
b8c86fc5 1684{
29495aa0 1685 struct pci_dev *pdev = to_pci_dev(dev);
30cf2803 1686 struct sdhci_pci_chip *chip = pci_get_drvdata(pdev);
b8c86fc5 1687
b8c86fc5
PO		 1688 if (!chip)
1689 return 0;
1690
30cf2803
AH		 1691 if (chip->fixes && chip->fixes->resume)
1692 return chip->fixes->resume(chip);
b8c86fc5 1693
30cf2803 1694 return sdhci_pci_resume_host(chip);
b8c86fc5 1695}
f9900f15 1696#endif
b8c86fc5 1697
f9900f15 1698#ifdef CONFIG_PM
66fd8ad5
AH		 1699static int sdhci_pci_runtime_suspend(struct device *dev)
1700{
923a231c 1701 struct pci_dev *pdev = to_pci_dev(dev);
966d696a 1702 struct sdhci_pci_chip *chip = pci_get_drvdata(pdev);
66fd8ad5 1703
66fd8ad5
AH		 1704 if (!chip)
1705 return 0;
1706
966d696a
AH		 1707 if (chip->fixes && chip->fixes->runtime_suspend)
1708 return chip->fixes->runtime_suspend(chip);
66fd8ad5 1709
966d696a 1710 return sdhci_pci_runtime_suspend_host(chip);
66fd8ad5
AH		 1711}
1712
1713static int sdhci_pci_runtime_resume(struct device *dev)
1714{
923a231c 1715 struct pci_dev *pdev = to_pci_dev(dev);
966d696a 1716 struct sdhci_pci_chip *chip = pci_get_drvdata(pdev);
66fd8ad5 1717
66fd8ad5
AH		 1718 if (!chip)
1719 return 0;
1720
966d696a
AH		 1721 if (chip->fixes && chip->fixes->runtime_resume)
1722 return chip->fixes->runtime_resume(chip);
66fd8ad5 1723
966d696a 1724 return sdhci_pci_runtime_resume_host(chip);
66fd8ad5 1725}
f9900f15 1726#endif
66fd8ad5
AH		 1727
1728static const struct dev_pm_ops sdhci_pci_pm_ops = {
f9900f15 1729 SET_SYSTEM_SLEEP_PM_OPS(sdhci_pci_suspend, sdhci_pci_resume)
f3a92b1a 1730 SET_RUNTIME_PM_OPS(sdhci_pci_runtime_suspend,
106276bb 1731 sdhci_pci_runtime_resume, NULL)
66fd8ad5
AH		 1732};
1733
b8c86fc5
PO		 1734/*****************************************************************************\
1735 * *
1736 * Device probing/removal *
1737 * *
1738\*****************************************************************************/
1739
c3be1efd 1740static struct sdhci_pci_slot *sdhci_pci_probe_slot(
52c506f0
AH		 1741 struct pci_dev *pdev, struct sdhci_pci_chip *chip, int first_bar,
1742 int slotno)
b8c86fc5
PO		 1743{
1744 struct sdhci_pci_slot *slot;
1745 struct sdhci_host *host;
52c506f0 1746 int ret, bar = first_bar + slotno;
ac9f67b5 1747 size_t priv_size = chip->fixes ? chip->fixes->priv_size : 0;
b8c86fc5
PO		 1748
1749 if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) {
1750 dev_err(&pdev->dev, "BAR %d is not iomem. Aborting.\n", bar);
1751 return ERR_PTR(-ENODEV);
1752 }
1753
90b3e6c5 1754 if (pci_resource_len(pdev, bar) < 0x100) {
b8c86fc5
PO		 1755 dev_err(&pdev->dev, "Invalid iomem size. You may "
1756 "experience problems.\n");
1757 }
1758
1759 if ((pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) {
1760 dev_err(&pdev->dev, "Vendor specific interface. Aborting.\n");
1761 return ERR_PTR(-ENODEV);
1762 }
1763
1764 if ((pdev->class & 0x0000FF) > PCI_SDHCI_IFVENDOR) {
1765 dev_err(&pdev->dev, "Unknown interface. Aborting.\n");
1766 return ERR_PTR(-ENODEV);
1767 }
1768
ac9f67b5 1769 host = sdhci_alloc_host(&pdev->dev, sizeof(*slot) + priv_size);
b8c86fc5 1770 if (IS_ERR(host)) {
c60a32cd 1771 dev_err(&pdev->dev, "cannot allocate host\n");
dc0fd7b5 1772 return ERR_CAST(host);
b8c86fc5
PO		 1773 }
1774
1775 slot = sdhci_priv(host);
1776
1777 slot->chip = chip;
1778 slot->host = host;
0f201655 1779 slot->rst_n_gpio = -EINVAL;
c5e027a4 1780 slot->cd_gpio = -EINVAL;
ff59c520 1781 slot->cd_idx = -1;
b8c86fc5 1782
52c506f0
AH		 1783 /* Retrieve platform data if there is any */
1784 if (*sdhci_pci_get_data)
1785 slot->data = sdhci_pci_get_data(pdev, slotno);
1786
1787 if (slot->data) {
1788 if (slot->data->setup) {
1789 ret = slot->data->setup(slot->data);
1790 if (ret) {
1791 dev_err(&pdev->dev, "platform setup failed\n");
1792 goto free;
1793 }
1794 }
c5e027a4
AH		 1795 slot->rst_n_gpio = slot->data->rst_n_gpio;
1796 slot->cd_gpio = slot->data->cd_gpio;
52c506f0
AH		 1797 }
1798
b8c86fc5 1799 host->hw_name = "PCI";
6bc09063
AH		 1800 host->ops = chip->fixes && chip->fixes->ops ?
1801 chip->fixes->ops :
1802 &sdhci_pci_ops;
b8c86fc5 1803 host->quirks = chip->quirks;
f3c55a7b 1804 host->quirks2 = chip->quirks2;
b8c86fc5
PO		 1805
1806 host->irq = pdev->irq;
1807
c10bc372 1808 ret = pcim_iomap_regions(pdev, BIT(bar), mmc_hostname(host->mmc));
b8c86fc5
PO		 1809 if (ret) {
1810 dev_err(&pdev->dev, "cannot request region\n");
52c506f0 1811 goto cleanup;
b8c86fc5
PO		 1812 }
1813
c10bc372 1814 host->ioaddr = pcim_iomap_table(pdev)[bar];
b8c86fc5 1815
4489428a
PO		 1816 if (chip->fixes && chip->fixes->probe_slot) {
1817 ret = chip->fixes->probe_slot(slot);
1818 if (ret)
c10bc372 1819 goto cleanup;
4489428a
PO		 1820 }
1821
c5e027a4 1822 if (gpio_is_valid(slot->rst_n_gpio)) {
c10bc372 1823 if (!devm_gpio_request(&pdev->dev, slot->rst_n_gpio, "eMMC_reset")) {
c5e027a4
AH		 1824 gpio_direction_output(slot->rst_n_gpio, 1);
1825 slot->host->mmc->caps |= MMC_CAP_HW_RESET;
c9faff6c 1826 slot->hw_reset = sdhci_pci_gpio_hw_reset;
c5e027a4
AH		 1827 } else {
1828 dev_warn(&pdev->dev, "failed to request rst_n_gpio\n");
1829 slot->rst_n_gpio = -EINVAL;
1830 }
1831 }
1832
e92cc35d 1833 host->mmc->pm_caps = MMC_PM_KEEP_POWER;
eed222ac 1834 host->mmc->slotno = slotno;
a08b17be 1835 host->mmc->caps2 |= MMC_CAP2_NO_PRESCAN_POWERUP;
2f4cbb3d 1836
e92cc35d
AH		 1837 if (device_can_wakeup(&pdev->dev))
1838 host->mmc->pm_caps |= MMC_PM_WAKE_SDIO_IRQ;
1839
d56ee1ff
AH		 1840 if (host->mmc->caps & MMC_CAP_CD_WAKE)
1841 device_init_wakeup(&pdev->dev, true);
1842
8f743d03 1843 if (slot->cd_idx >= 0) {
cdcefe6b 1844 ret = mmc_gpiod_request_cd(host->mmc, "cd", slot->cd_idx,
8f743d03 1845 slot->cd_override_level, 0, NULL);
cdcefe6b
RJ		 1846 if (ret && ret != -EPROBE_DEFER)
1847 ret = mmc_gpiod_request_cd(host->mmc, NULL,
1848 slot->cd_idx,
1849 slot->cd_override_level,
1850 0, NULL);
8f743d03
DB		 1851 if (ret == -EPROBE_DEFER)
1852 goto remove;
1853
1854 if (ret) {
1855 dev_warn(&pdev->dev, "failed to setup card detect gpio\n");
1856 slot->cd_idx = -1;
1857 }
ff59c520
AH		 1858 }
1859
61c951de
AH		 1860 if (chip->fixes && chip->fixes->add_host)
1861 ret = chip->fixes->add_host(slot);
1862 else
1863 ret = sdhci_add_host(host);
b8c86fc5 1864 if (ret)
4489428a 1865 goto remove;
b8c86fc5 1866
c5e027a4
AH		 1867 sdhci_pci_add_own_cd(slot);
1868
77a0122e
AH		 1869 /*
1870 * Check if the chip needs a separate GPIO for card detect to wake up
1871 * from runtime suspend. If it is not there, don't allow runtime PM.
1872 * Note sdhci_pci_add_own_cd() sets slot->cd_gpio to -EINVAL on failure.
1873 */
945be38c 1874 if (chip->fixes && chip->fixes->own_cd_for_runtime_pm &&
ff59c520 1875 !gpio_is_valid(slot->cd_gpio) && slot->cd_idx < 0)
77a0122e
AH		 1876 chip->allow_runtime_pm = false;
1877
b8c86fc5
PO		 1878 return slot;
1879
4489428a
PO		 1880remove:
1881 if (chip->fixes && chip->fixes->remove_slot)
1e72859e 1882 chip->fixes->remove_slot(slot, 0);
4489428a 1883
52c506f0
AH		 1884cleanup:
1885 if (slot->data && slot->data->cleanup)
1886 slot->data->cleanup(slot->data);
1887
c60a32cd 1888free:
b8c86fc5
PO		 1889 sdhci_free_host(host);
1890
1891 return ERR_PTR(ret);
1892}
1893
1894static void sdhci_pci_remove_slot(struct sdhci_pci_slot *slot)
1895{
1e72859e
PO		 1896 int dead;
1897 u32 scratch;
1898
c5e027a4
AH		 1899 sdhci_pci_remove_own_cd(slot);
1900
1e72859e
PO		 1901 dead = 0;
1902 scratch = readl(slot->host->ioaddr + SDHCI_INT_STATUS);
1903 if (scratch == (u32)-1)
1904 dead = 1;
1905
1906 sdhci_remove_host(slot->host, dead);
4489428a
PO		 1907
1908 if (slot->chip->fixes && slot->chip->fixes->remove_slot)
1e72859e 1909 slot->chip->fixes->remove_slot(slot, dead);
4489428a 1910
52c506f0
AH		 1911 if (slot->data && slot->data->cleanup)
1912 slot->data->cleanup(slot->data);
1913
b8c86fc5
PO		 1914 sdhci_free_host(slot->host);
1915}
1916
c3be1efd 1917static void sdhci_pci_runtime_pm_allow(struct device *dev)
66fd8ad5 1918{
00884b61 1919 pm_suspend_ignore_children(dev, 1);
66fd8ad5
AH		 1920 pm_runtime_set_autosuspend_delay(dev, 50);
1921 pm_runtime_use_autosuspend(dev);
00884b61
AH		 1922 pm_runtime_allow(dev);
1923 /* Stay active until mmc core scans for a card */
1924 pm_runtime_put_noidle(dev);
66fd8ad5
AH		 1925}
1926
6e0ee714 1927static void sdhci_pci_runtime_pm_forbid(struct device *dev)
66fd8ad5
AH		 1928{
1929 pm_runtime_forbid(dev);
1930 pm_runtime_get_noresume(dev);
1931}
1932
c3be1efd 1933static int sdhci_pci_probe(struct pci_dev *pdev,
b8c86fc5
PO		 1934 const struct pci_device_id *ent)
1935{
1936 struct sdhci_pci_chip *chip;
1937 struct sdhci_pci_slot *slot;
1938
cf5e23e1 1939 u8 slots, first_bar;
b8c86fc5
PO		 1940 int ret, i;
1941
1942 BUG_ON(pdev == NULL);
1943 BUG_ON(ent == NULL);
1944
b8c86fc5 1945 dev_info(&pdev->dev, "SDHCI controller found [%04x:%04x] (rev %x)\n",
cf5e23e1 1946 (int)pdev->vendor, (int)pdev->device, (int)pdev->revision);
b8c86fc5
PO		 1947
1948 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &slots);
1949 if (ret)
1950 return ret;
1951
1952 slots = PCI_SLOT_INFO_SLOTS(slots) + 1;
1953 dev_dbg(&pdev->dev, "found %d slot(s)\n", slots);
1954 if (slots == 0)
1955 return -ENODEV;
1956
1957 BUG_ON(slots > MAX_SLOTS);
1958
1959 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &first_bar);
1960 if (ret)
1961 return ret;
1962
1963 first_bar &= PCI_SLOT_INFO_FIRST_BAR_MASK;
1964
1965 if (first_bar > 5) {
1966 dev_err(&pdev->dev, "Invalid first BAR. Aborting.\n");
1967 return -ENODEV;
1968 }
1969
52ac7acf 1970 ret = pcim_enable_device(pdev);
b8c86fc5
PO		 1971 if (ret)
1972 return ret;
1973
52ac7acf
AS		 1974 chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL);
1975 if (!chip)
1976 return -ENOMEM;
b8c86fc5
PO		 1977
1978 chip->pdev = pdev;
b177bc91 1979 chip->fixes = (const struct sdhci_pci_fixes *)ent->driver_data;
c43fd774 1980 if (chip->fixes) {
22606405 1981 chip->quirks = chip->fixes->quirks;
f3c55a7b 1982 chip->quirks2 = chip->fixes->quirks2;
c43fd774
AH		 1983 chip->allow_runtime_pm = chip->fixes->allow_runtime_pm;
1984 }
b8c86fc5 1985 chip->num_slots = slots;
d38dcad4
AH		 1986 chip->pm_retune = true;
1987 chip->rpm_retune = true;
b8c86fc5
PO		 1988
1989 pci_set_drvdata(pdev, chip);
1990
22606405
PO		 1991 if (chip->fixes && chip->fixes->probe) {
1992 ret = chip->fixes->probe(chip);
1993 if (ret)
52ac7acf 1994 return ret;
22606405
PO		 1995 }
1996
225d85fe
AC		 1997 slots = chip->num_slots; /* Quirk may have changed this */
1998
b177bc91 1999 for (i = 0; i < slots; i++) {
52c506f0 2000 slot = sdhci_pci_probe_slot(pdev, chip, first_bar, i);
b8c86fc5 2001 if (IS_ERR(slot)) {
b177bc91 2002 for (i--; i >= 0; i--)
b8c86fc5 2003 sdhci_pci_remove_slot(chip->slots[i]);
52ac7acf 2004 return PTR_ERR(slot);
b8c86fc5
PO		 2005 }
2006
2007 chip->slots[i] = slot;
2008 }
2009
c43fd774
AH		 2010 if (chip->allow_runtime_pm)
2011 sdhci_pci_runtime_pm_allow(&pdev->dev);
66fd8ad5 2012
b8c86fc5 2013 return 0;
b8c86fc5
PO		 2014}
2015
6e0ee714 2016static void sdhci_pci_remove(struct pci_dev *pdev)
b8c86fc5
PO		 2017{
2018 int i;
52ac7acf 2019 struct sdhci_pci_chip *chip = pci_get_drvdata(pdev);
c43fd774 2020
52ac7acf
AS		 2021 if (chip->allow_runtime_pm)
2022 sdhci_pci_runtime_pm_forbid(&pdev->dev);
b8c86fc5 2023
52ac7acf
AS		 2024 for (i = 0; i < chip->num_slots; i++)
2025 sdhci_pci_remove_slot(chip->slots[i]);
b8c86fc5
PO		 2026}
2027
2028static struct pci_driver sdhci_driver = {
b177bc91 2029 .name = "sdhci-pci",
b8c86fc5 2030 .id_table = pci_ids,
b177bc91 2031 .probe = sdhci_pci_probe,
0433c143 2032 .remove = sdhci_pci_remove,
66fd8ad5
AH		 2033 .driver = {
2034 .pm = &sdhci_pci_pm_ops
2035 },
b8c86fc5
PO		 2036};
2037
acc69646 2038module_pci_driver(sdhci_driver);
b8c86fc5 2039
32710e8f 2040MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
b8c86fc5
PO		 2041MODULE_DESCRIPTION("Secure Digital Host Controller Interface PCI driver");
2042MODULE_LICENSE("GPL");
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