[mirror_ubuntu-focal-kernel.git] / drivers / mmc / host / sdhci-pci-o2micro.c

/*
 * Copyright (C) 2013 BayHub Technology Ltd.
 *
 * Authors: Peter Guo <peter.guo@bayhubtech.com>
 *          Adam Lee <adam.lee@canonical.com>
 *
 * This software is licensed under the terms of the GNU General Public
 * License version 2, as published by the Free Software Foundation, and
 * may be copied, distributed, and modified under those terms.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 */

#include <linux/pci.h>

#include "sdhci.h"
#include "sdhci-pci.h"
#include "sdhci-pci-o2micro.h"

static void o2_pci_set_baseclk(struct sdhci_pci_chip *chip, u32 value)
{
	u32 scratch_32;
	pci_read_config_dword(chip->pdev,
			      O2_SD_PLL_SETTING, &scratch_32);

	scratch_32 &= 0x0000FFFF;
	scratch_32 |= value;

	pci_write_config_dword(chip->pdev,
			       O2_SD_PLL_SETTING, scratch_32);
}

static void o2_pci_led_enable(struct sdhci_pci_chip *chip)
{
	int ret;
	u32 scratch_32;

	/* Set led of SD host function enable */
	ret = pci_read_config_dword(chip->pdev,
				    O2_SD_FUNC_REG0, &scratch_32);
	if (ret)
		return;

	scratch_32 &= ~O2_SD_FREG0_LEDOFF;
	pci_write_config_dword(chip->pdev,
			       O2_SD_FUNC_REG0, scratch_32);

	ret = pci_read_config_dword(chip->pdev,
				    O2_SD_TEST_REG, &scratch_32);
	if (ret)
		return;

	scratch_32 |= O2_SD_LED_ENABLE;
	pci_write_config_dword(chip->pdev,
			       O2_SD_TEST_REG, scratch_32);

}

void sdhci_pci_o2_fujin2_pci_init(struct sdhci_pci_chip *chip)
{
	u32 scratch_32;
	int ret;
	/* Improve write performance for SD3.0 */
	ret = pci_read_config_dword(chip->pdev, O2_SD_DEV_CTRL, &scratch_32);
	if (ret)
		return;
	scratch_32 &= ~((1 << 12) | (1 << 13) | (1 << 14));
	pci_write_config_dword(chip->pdev, O2_SD_DEV_CTRL, scratch_32);

	/* Enable Link abnormal reset generating Reset */
	ret = pci_read_config_dword(chip->pdev, O2_SD_MISC_REG5, &scratch_32);
	if (ret)
		return;
	scratch_32 &= ~((1 << 19) | (1 << 11));
	scratch_32 |= (1 << 10);
	pci_write_config_dword(chip->pdev, O2_SD_MISC_REG5, scratch_32);

	/* set card power over current protection */
	ret = pci_read_config_dword(chip->pdev, O2_SD_TEST_REG, &scratch_32);
	if (ret)
		return;
	scratch_32 |= (1 << 4);
	pci_write_config_dword(chip->pdev, O2_SD_TEST_REG, scratch_32);

	/* adjust the output delay for SD mode */
	pci_write_config_dword(chip->pdev, O2_SD_DELAY_CTRL, 0x00002492);

	/* Set the output voltage setting of Aux 1.2v LDO */
	ret = pci_read_config_dword(chip->pdev, O2_SD_LD0_CTRL, &scratch_32);
	if (ret)
		return;
	scratch_32 &= ~(3 << 12);
	pci_write_config_dword(chip->pdev, O2_SD_LD0_CTRL, scratch_32);

	/* Set Max power supply capability of SD host */
	ret = pci_read_config_dword(chip->pdev, O2_SD_CAP_REG0, &scratch_32);
	if (ret)
		return;
	scratch_32 &= ~(0x01FE);
	scratch_32 |= 0x00CC;
	pci_write_config_dword(chip->pdev, O2_SD_CAP_REG0, scratch_32);
	/* Set DLL Tuning Window */
	ret = pci_read_config_dword(chip->pdev,
				    O2_SD_TUNING_CTRL, &scratch_32);
	if (ret)
		return;
	scratch_32 &= ~(0x000000FF);
	scratch_32 |= 0x00000066;
	pci_write_config_dword(chip->pdev, O2_SD_TUNING_CTRL, scratch_32);

	/* Set UHS2 T_EIDLE */
	ret = pci_read_config_dword(chip->pdev,
				    O2_SD_UHS2_L1_CTRL, &scratch_32);
	if (ret)
		return;
	scratch_32 &= ~(0x000000FC);
	scratch_32 |= 0x00000084;
	pci_write_config_dword(chip->pdev, O2_SD_UHS2_L1_CTRL, scratch_32);

	/* Set UHS2 Termination */
	ret = pci_read_config_dword(chip->pdev, O2_SD_FUNC_REG3, &scratch_32);
	if (ret)
		return;
	scratch_32 &= ~((1 << 21) | (1 << 30));

	pci_write_config_dword(chip->pdev, O2_SD_FUNC_REG3, scratch_32);

	/* Set L1 Entrance Timer */
	ret = pci_read_config_dword(chip->pdev, O2_SD_CAPS, &scratch_32);
	if (ret)
		return;
	scratch_32 &= ~(0xf0000000);
	scratch_32 |= 0x30000000;
	pci_write_config_dword(chip->pdev, O2_SD_CAPS, scratch_32);

	ret = pci_read_config_dword(chip->pdev,
				    O2_SD_MISC_CTRL4, &scratch_32);
	if (ret)
		return;
	scratch_32 &= ~(0x000f0000);
	scratch_32 |= 0x00080000;
	pci_write_config_dword(chip->pdev, O2_SD_MISC_CTRL4, scratch_32);
}
EXPORT_SYMBOL_GPL(sdhci_pci_o2_fujin2_pci_init);

int sdhci_pci_o2_probe_slot(struct sdhci_pci_slot *slot)
{
	struct sdhci_pci_chip *chip;
	struct sdhci_host *host;
	u32 reg;

	chip = slot->chip;
	host = slot->host;
	switch (chip->pdev->device) {
	case PCI_DEVICE_ID_O2_SDS0:
	case PCI_DEVICE_ID_O2_SEABIRD0:
	case PCI_DEVICE_ID_O2_SEABIRD1:
	case PCI_DEVICE_ID_O2_SDS1:
	case PCI_DEVICE_ID_O2_FUJIN2:
		reg = sdhci_readl(host, O2_SD_VENDOR_SETTING);
		if (reg & 0x1)
			host->quirks |= SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12;

		if (chip->pdev->device != PCI_DEVICE_ID_O2_FUJIN2)
			break;
		/* set dll watch dog timer */
		reg = sdhci_readl(host, O2_SD_VENDOR_SETTING2);
		reg |= (1 << 12);
		sdhci_writel(host, reg, O2_SD_VENDOR_SETTING2);

		break;
	default:
		break;
	}

	return 0;
}
EXPORT_SYMBOL_GPL(sdhci_pci_o2_probe_slot);

int sdhci_pci_o2_probe(struct sdhci_pci_chip *chip)
{
	int ret;
	u8 scratch;
	u32 scratch_32;

	switch (chip->pdev->device) {
	case PCI_DEVICE_ID_O2_8220:
	case PCI_DEVICE_ID_O2_8221:
	case PCI_DEVICE_ID_O2_8320:
	case PCI_DEVICE_ID_O2_8321:
		/* This extra setup is required due to broken ADMA. */
		ret = pci_read_config_byte(chip->pdev,
				O2_SD_LOCK_WP, &scratch);
		if (ret)
			return ret;
		scratch &= 0x7f;
		pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);

		/* Set Multi 3 to VCC3V# */
		pci_write_config_byte(chip->pdev, O2_SD_MULTI_VCC3V, 0x08);

		/* Disable CLK_REQ# support after media DET */
		ret = pci_read_config_byte(chip->pdev,
				O2_SD_CLKREQ, &scratch);
		if (ret)
			return ret;
		scratch |= 0x20;
		pci_write_config_byte(chip->pdev, O2_SD_CLKREQ, scratch);

		/* Choose capabilities, enable SDMA.  We have to write 0x01
		 * to the capabilities register first to unlock it.
		 */
		ret = pci_read_config_byte(chip->pdev, O2_SD_CAPS, &scratch);
		if (ret)
			return ret;
		scratch |= 0x01;
		pci_write_config_byte(chip->pdev, O2_SD_CAPS, scratch);
		pci_write_config_byte(chip->pdev, O2_SD_CAPS, 0x73);

		/* Disable ADMA1/2 */
		pci_write_config_byte(chip->pdev, O2_SD_ADMA1, 0x39);
		pci_write_config_byte(chip->pdev, O2_SD_ADMA2, 0x08);

		/* Disable the infinite transfer mode */
		ret = pci_read_config_byte(chip->pdev,
				O2_SD_INF_MOD, &scratch);
		if (ret)
			return ret;
		scratch |= 0x08;
		pci_write_config_byte(chip->pdev, O2_SD_INF_MOD, scratch);

		/* Lock WP */
		ret = pci_read_config_byte(chip->pdev,
				O2_SD_LOCK_WP, &scratch);
		if (ret)
			return ret;
		scratch |= 0x80;
		pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
		break;
	case PCI_DEVICE_ID_O2_SDS0:
	case PCI_DEVICE_ID_O2_SDS1:
	case PCI_DEVICE_ID_O2_FUJIN2:
		/* UnLock WP */
		ret = pci_read_config_byte(chip->pdev,
				O2_SD_LOCK_WP, &scratch);
		if (ret)
			return ret;

		scratch &= 0x7f;
		pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);

		/* DevId=8520 subId= 0x11 or 0x12  Type Chip support */
		if (chip->pdev->device == PCI_DEVICE_ID_O2_FUJIN2) {
			ret = pci_read_config_dword(chip->pdev,
						    O2_SD_FUNC_REG0,
						    &scratch_32);
			scratch_32 = ((scratch_32 & 0xFF000000) >> 24);

			/* Check Whether subId is 0x11 or 0x12 */
			if ((scratch_32 == 0x11) || (scratch_32 == 0x12)) {
				scratch_32 = 0x2c280000;

				/* Set Base Clock to 208MZ */
				o2_pci_set_baseclk(chip, scratch_32);
				ret = pci_read_config_dword(chip->pdev,
							    O2_SD_FUNC_REG4,
							    &scratch_32);

				/* Enable Base Clk setting change */
				scratch_32 |= O2_SD_FREG4_ENABLE_CLK_SET;
				pci_write_config_dword(chip->pdev,
						       O2_SD_FUNC_REG4,
						       scratch_32);

				/* Set Tuning Window to 4 */
				pci_write_config_byte(chip->pdev,
						      O2_SD_TUNING_CTRL, 0x44);

				break;
			}
		}

		/* Enable 8520 led function */
		o2_pci_led_enable(chip);

		/* Set timeout CLK */
		ret = pci_read_config_dword(chip->pdev,
					    O2_SD_CLK_SETTING, &scratch_32);
		if (ret)
			return ret;

		scratch_32 &= ~(0xFF00);
		scratch_32 |= 0x07E0C800;
		pci_write_config_dword(chip->pdev,
				       O2_SD_CLK_SETTING, scratch_32);

		ret = pci_read_config_dword(chip->pdev,
					    O2_SD_CLKREQ, &scratch_32);
		if (ret)
			return ret;
		scratch_32 |= 0x3;
		pci_write_config_dword(chip->pdev, O2_SD_CLKREQ, scratch_32);

		ret = pci_read_config_dword(chip->pdev,
					    O2_SD_PLL_SETTING, &scratch_32);
		if (ret)
			return ret;

		scratch_32 &= ~(0x1F3F070E);
		scratch_32 |= 0x18270106;
		pci_write_config_dword(chip->pdev,
				       O2_SD_PLL_SETTING, scratch_32);

		/* Disable UHS1 funciton */
		ret = pci_read_config_dword(chip->pdev,
					    O2_SD_CAP_REG2, &scratch_32);
		if (ret)
			return ret;
		scratch_32 &= ~(0xE0);
		pci_write_config_dword(chip->pdev,
				       O2_SD_CAP_REG2, scratch_32);

		if (chip->pdev->device == PCI_DEVICE_ID_O2_FUJIN2)
			sdhci_pci_o2_fujin2_pci_init(chip);

		/* Lock WP */
		ret = pci_read_config_byte(chip->pdev,
					   O2_SD_LOCK_WP, &scratch);
		if (ret)
			return ret;
		scratch |= 0x80;
		pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
		break;
	case PCI_DEVICE_ID_O2_SEABIRD0:
	case PCI_DEVICE_ID_O2_SEABIRD1:
		/* UnLock WP */
		ret = pci_read_config_byte(chip->pdev,
				O2_SD_LOCK_WP, &scratch);
		if (ret)
			return ret;

		scratch &= 0x7f;
		pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);

		ret = pci_read_config_dword(chip->pdev,
					    O2_SD_PLL_SETTING, &scratch_32);

		if ((scratch_32 & 0xff000000) == 0x01000000) {
			scratch_32 &= 0x0000FFFF;
			scratch_32 |= 0x1F340000;

			pci_write_config_dword(chip->pdev,
					       O2_SD_PLL_SETTING, scratch_32);
		} else {
			scratch_32 &= 0x0000FFFF;
			scratch_32 |= 0x2c280000;

			pci_write_config_dword(chip->pdev,
					       O2_SD_PLL_SETTING, scratch_32);

			ret = pci_read_config_dword(chip->pdev,
						    O2_SD_FUNC_REG4,
						    &scratch_32);
			scratch_32 |= (1 << 22);
			pci_write_config_dword(chip->pdev,
					       O2_SD_FUNC_REG4, scratch_32);
		}

		/* Set Tuning Windows to 5 */
		pci_write_config_byte(chip->pdev,
				O2_SD_TUNING_CTRL, 0x55);
		/* Lock WP */
		ret = pci_read_config_byte(chip->pdev,
					   O2_SD_LOCK_WP, &scratch);
		if (ret)
			return ret;
		scratch |= 0x80;
		pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
		break;
	}

	return 0;
}
EXPORT_SYMBOL_GPL(sdhci_pci_o2_probe);

int sdhci_pci_o2_resume(struct sdhci_pci_chip *chip)
{
	sdhci_pci_o2_probe(chip);
	return 0;
}
EXPORT_SYMBOL_GPL(sdhci_pci_o2_resume);
Commit	Line	Data
01acf691 AL	1	/*
	2	* Copyright (C) 2013 BayHub Technology Ltd.
	3	*
	4	* Authors: Peter Guo <peter.guo@bayhubtech.com>
	5	* Adam Lee <adam.lee@canonical.com>
	6	*
	7	* This software is licensed under the terms of the GNU General Public
	8	* License version 2, as published by the Free Software Foundation, and
	9	* may be copied, distributed, and modified under those terms.
	10	*
	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	* GNU General Public License for more details.
	15	*
	16	*/
	17
	18	#include <linux/pci.h>
	19
	20	#include "sdhci.h"
	21	#include "sdhci-pci.h"
	22	#include "sdhci-pci-o2micro.h"
	23
706adf6b PG	24	static void o2_pci_set_baseclk(struct sdhci_pci_chip *chip, u32 value)
	25	{
	26	u32 scratch_32;
	27	pci_read_config_dword(chip->pdev,
	28	O2_SD_PLL_SETTING, &scratch_32);
	29
	30	scratch_32 &= 0x0000FFFF;
	31	scratch_32 \|= value;
	32
	33	pci_write_config_dword(chip->pdev,
	34	O2_SD_PLL_SETTING, scratch_32);
	35	}
	36
	37	static void o2_pci_led_enable(struct sdhci_pci_chip *chip)
	38	{
	39	int ret;
	40	u32 scratch_32;
	41
	42	/* Set led of SD host function enable */
	43	ret = pci_read_config_dword(chip->pdev,
	44	O2_SD_FUNC_REG0, &scratch_32);
	45	if (ret)
	46	return;
	47
	48	scratch_32 &= ~O2_SD_FREG0_LEDOFF;
	49	pci_write_config_dword(chip->pdev,
	50	O2_SD_FUNC_REG0, scratch_32);
	51
	52	ret = pci_read_config_dword(chip->pdev,
	53	O2_SD_TEST_REG, &scratch_32);
	54	if (ret)
	55	return;
	56
	57	scratch_32 \|= O2_SD_LED_ENABLE;
	58	pci_write_config_dword(chip->pdev,
	59	O2_SD_TEST_REG, scratch_32);
	60
	61	}
	62
01acf691 AL	63	void sdhci_pci_o2_fujin2_pci_init(struct sdhci_pci_chip *chip)
	64	{
	65	u32 scratch_32;
	66	int ret;
	67	/* Improve write performance for SD3.0 */
	68	ret = pci_read_config_dword(chip->pdev, O2_SD_DEV_CTRL, &scratch_32);
	69	if (ret)
	70	return;
	71	scratch_32 &= ~((1 << 12) \| (1 << 13) \| (1 << 14));
	72	pci_write_config_dword(chip->pdev, O2_SD_DEV_CTRL, scratch_32);
	73
	74	/* Enable Link abnormal reset generating Reset */
	75	ret = pci_read_config_dword(chip->pdev, O2_SD_MISC_REG5, &scratch_32);
	76	if (ret)
	77	return;
	78	scratch_32 &= ~((1 << 19) \| (1 << 11));
	79	scratch_32 \|= (1 << 10);
	80	pci_write_config_dword(chip->pdev, O2_SD_MISC_REG5, scratch_32);
	81
	82	/* set card power over current protection */
	83	ret = pci_read_config_dword(chip->pdev, O2_SD_TEST_REG, &scratch_32);
	84	if (ret)
	85	return;
	86	scratch_32 \|= (1 << 4);
	87	pci_write_config_dword(chip->pdev, O2_SD_TEST_REG, scratch_32);
	88
	89	/* adjust the output delay for SD mode */
	90	pci_write_config_dword(chip->pdev, O2_SD_DELAY_CTRL, 0x00002492);
	91
	92	/* Set the output voltage setting of Aux 1.2v LDO */
	93	ret = pci_read_config_dword(chip->pdev, O2_SD_LD0_CTRL, &scratch_32);
	94	if (ret)
	95	return;
	96	scratch_32 &= ~(3 << 12);
	97	pci_write_config_dword(chip->pdev, O2_SD_LD0_CTRL, scratch_32);
	98
	99	/* Set Max power supply capability of SD host */
	100	ret = pci_read_config_dword(chip->pdev, O2_SD_CAP_REG0, &scratch_32);
	101	if (ret)
	102	return;
	103	scratch_32 &= ~(0x01FE);
	104	scratch_32 \|= 0x00CC;
	105	pci_write_config_dword(chip->pdev, O2_SD_CAP_REG0, scratch_32);
	106	/* Set DLL Tuning Window */
	107	ret = pci_read_config_dword(chip->pdev,
	108	O2_SD_TUNING_CTRL, &scratch_32);
	109	if (ret)
	110	return;
	111	scratch_32 &= ~(0x000000FF);
	112	scratch_32 \|= 0x00000066;
	113	pci_write_config_dword(chip->pdev, O2_SD_TUNING_CTRL, scratch_32);
	114
	115	/* Set UHS2 T_EIDLE */
	116	ret = pci_read_config_dword(chip->pdev,
	117	O2_SD_UHS2_L1_CTRL, &scratch_32);
	118	if (ret)
	119	return;
	120	scratch_32 &= ~(0x000000FC);
	121	scratch_32 \|= 0x00000084;
	122	pci_write_config_dword(chip->pdev, O2_SD_UHS2_L1_CTRL, scratch_32);
	123
	124	/* Set UHS2 Termination */
	125	ret = pci_read_config_dword(chip->pdev, O2_SD_FUNC_REG3, &scratch_32);
	126	if (ret)
127	return;
128	scratch_32 &= ~((1 << 21) \| (1 << 30));
129
01acf691 AL	130	pci_write_config_dword(chip->pdev, O2_SD_FUNC_REG3, scratch_32);
	131
	132	/* Set L1 Entrance Timer */
	133	ret = pci_read_config_dword(chip->pdev, O2_SD_CAPS, &scratch_32);
	134	if (ret)
	135	return;
	136	scratch_32 &= ~(0xf0000000);
	137	scratch_32 \|= 0x30000000;
	138	pci_write_config_dword(chip->pdev, O2_SD_CAPS, scratch_32);
	139
	140	ret = pci_read_config_dword(chip->pdev,
	141	O2_SD_MISC_CTRL4, &scratch_32);
	142	if (ret)
	143	return;
	144	scratch_32 &= ~(0x000f0000);
	145	scratch_32 \|= 0x00080000;
	146	pci_write_config_dword(chip->pdev, O2_SD_MISC_CTRL4, scratch_32);
	147	}
	148	EXPORT_SYMBOL_GPL(sdhci_pci_o2_fujin2_pci_init);
	149
	150	int sdhci_pci_o2_probe_slot(struct sdhci_pci_slot *slot)
	151	{
	152	struct sdhci_pci_chip *chip;
	153	struct sdhci_host *host;
	154	u32 reg;
	155
	156	chip = slot->chip;
	157	host = slot->host;
	158	switch (chip->pdev->device) {
	159	case PCI_DEVICE_ID_O2_SDS0:
	160	case PCI_DEVICE_ID_O2_SEABIRD0:
	161	case PCI_DEVICE_ID_O2_SEABIRD1:
	162	case PCI_DEVICE_ID_O2_SDS1:
	163	case PCI_DEVICE_ID_O2_FUJIN2:
	164	reg = sdhci_readl(host, O2_SD_VENDOR_SETTING);
	165	if (reg & 0x1)
	166	host->quirks \|= SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12;
	167
	168	if (chip->pdev->device != PCI_DEVICE_ID_O2_FUJIN2)
	169	break;
	170	/* set dll watch dog timer */
	171	reg = sdhci_readl(host, O2_SD_VENDOR_SETTING2);
	172	reg \|= (1 << 12);
	173	sdhci_writel(host, reg, O2_SD_VENDOR_SETTING2);
	174
	175	break;
	176	default:
	177	break;
	178	}
	179
	180	return 0;
	181	}
	182	EXPORT_SYMBOL_GPL(sdhci_pci_o2_probe_slot);
	183
	184	int sdhci_pci_o2_probe(struct sdhci_pci_chip *chip)
	185	{
	186	int ret;
	187	u8 scratch;
	188	u32 scratch_32;
	189
	190	switch (chip->pdev->device) {
	191	case PCI_DEVICE_ID_O2_8220:
	192	case PCI_DEVICE_ID_O2_8221:
	193	case PCI_DEVICE_ID_O2_8320:
194	case PCI_DEVICE_ID_O2_8321:
195	/* This extra setup is required due to broken ADMA. */
196	ret = pci_read_config_byte(chip->pdev,
197	O2_SD_LOCK_WP, &scratch);
198	if (ret)
199	return ret;
200	scratch &= 0x7f;
201	pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
202
203	/* Set Multi 3 to VCC3V# */
204	pci_write_config_byte(chip->pdev, O2_SD_MULTI_VCC3V, 0x08);
205
206	/* Disable CLK_REQ# support after media DET */
207	ret = pci_read_config_byte(chip->pdev,
208	O2_SD_CLKREQ, &scratch);
209	if (ret)
210	return ret;
211	scratch \|= 0x20;
212	pci_write_config_byte(chip->pdev, O2_SD_CLKREQ, scratch);
213
214	/* Choose capabilities, enable SDMA. We have to write 0x01
215	* to the capabilities register first to unlock it.
216	*/
217	ret = pci_read_config_byte(chip->pdev, O2_SD_CAPS, &scratch);
218	if (ret)
219	return ret;
220	scratch \|= 0x01;
221	pci_write_config_byte(chip->pdev, O2_SD_CAPS, scratch);
222	pci_write_config_byte(chip->pdev, O2_SD_CAPS, 0x73);
223
224	/* Disable ADMA1/2 */
225	pci_write_config_byte(chip->pdev, O2_SD_ADMA1, 0x39);
226	pci_write_config_byte(chip->pdev, O2_SD_ADMA2, 0x08);
227
228	/* Disable the infinite transfer mode */
229	ret = pci_read_config_byte(chip->pdev,
230	O2_SD_INF_MOD, &scratch);
231	if (ret)
232	return ret;
233	scratch \|= 0x08;
234	pci_write_config_byte(chip->pdev, O2_SD_INF_MOD, scratch);
235
236	/* Lock WP */
237	ret = pci_read_config_byte(chip->pdev,
238	O2_SD_LOCK_WP, &scratch);
239	if (ret)
240	return ret;
241	scratch \|= 0x80;
242	pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
243	break;
244	case PCI_DEVICE_ID_O2_SDS0:
245	case PCI_DEVICE_ID_O2_SDS1:
246	case PCI_DEVICE_ID_O2_FUJIN2:
247	/* UnLock WP */
248	ret = pci_read_config_byte(chip->pdev,
249	O2_SD_LOCK_WP, &scratch);
250	if (ret)
251	return ret;
252
253	scratch &= 0x7f;
254	pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
255
706adf6b PG	256	/* DevId=8520 subId= 0x11 or 0x12 Type Chip support */
	257	if (chip->pdev->device == PCI_DEVICE_ID_O2_FUJIN2) {
	258	ret = pci_read_config_dword(chip->pdev,
	259	O2_SD_FUNC_REG0,
	260	&scratch_32);
	261	scratch_32 = ((scratch_32 & 0xFF000000) >> 24);
	262
	263	/* Check Whether subId is 0x11 or 0x12 */
	264	if ((scratch_32 == 0x11) \|\| (scratch_32 == 0x12)) {
	265	scratch_32 = 0x2c280000;
	266
	267	/* Set Base Clock to 208MZ */
	268	o2_pci_set_baseclk(chip, scratch_32);
	269	ret = pci_read_config_dword(chip->pdev,
	270	O2_SD_FUNC_REG4,
	271	&scratch_32);
	272
	273	/* Enable Base Clk setting change */
	274	scratch_32 \|= O2_SD_FREG4_ENABLE_CLK_SET;
	275	pci_write_config_dword(chip->pdev,
	276	O2_SD_FUNC_REG4,
	277	scratch_32);
	278
	279	/* Set Tuning Window to 4 */
	280	pci_write_config_byte(chip->pdev,
	281	O2_SD_TUNING_CTRL, 0x44);
	282
	283	break;
	284	}
	285	}
	286
	287	/* Enable 8520 led function */
	288	o2_pci_led_enable(chip);
	289
01acf691 AL	290	/* Set timeout CLK */
	291	ret = pci_read_config_dword(chip->pdev,
	292	O2_SD_CLK_SETTING, &scratch_32);
	293	if (ret)
	294	return ret;
	295
	296	scratch_32 &= ~(0xFF00);
	297	scratch_32 \|= 0x07E0C800;
	298	pci_write_config_dword(chip->pdev,
	299	O2_SD_CLK_SETTING, scratch_32);
	300
	301	ret = pci_read_config_dword(chip->pdev,
	302	O2_SD_CLKREQ, &scratch_32);
	303	if (ret)
	304	return ret;
	305	scratch_32 \|= 0x3;
	306	pci_write_config_dword(chip->pdev, O2_SD_CLKREQ, scratch_32);
	307
	308	ret = pci_read_config_dword(chip->pdev,
	309	O2_SD_PLL_SETTING, &scratch_32);
	310	if (ret)
	311	return ret;
	312
	313	scratch_32 &= ~(0x1F3F070E);
	314	scratch_32 \|= 0x18270106;
	315	pci_write_config_dword(chip->pdev,
	316	O2_SD_PLL_SETTING, scratch_32);
	317
	318	/* Disable UHS1 funciton */
	319	ret = pci_read_config_dword(chip->pdev,
	320	O2_SD_CAP_REG2, &scratch_32);
	321	if (ret)
	322	return ret;
	323	scratch_32 &= ~(0xE0);
	324	pci_write_config_dword(chip->pdev,
	325	O2_SD_CAP_REG2, scratch_32);
	326
	327	if (chip->pdev->device == PCI_DEVICE_ID_O2_FUJIN2)
	328	sdhci_pci_o2_fujin2_pci_init(chip);
	329
	330	/* Lock WP */
	331	ret = pci_read_config_byte(chip->pdev,
	332	O2_SD_LOCK_WP, &scratch);
	333	if (ret)
	334	return ret;
	335	scratch \|= 0x80;
	336	pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
	337	break;
	338	case PCI_DEVICE_ID_O2_SEABIRD0:
	339	case PCI_DEVICE_ID_O2_SEABIRD1:
	340	/* UnLock WP */
	341	ret = pci_read_config_byte(chip->pdev,
	342	O2_SD_LOCK_WP, &scratch);
	343	if (ret)
	344	return ret;
	345
	346	scratch &= 0x7f;
	347	pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
	348
	349	ret = pci_read_config_dword(chip->pdev,
706adf6b	350	O2_SD_PLL_SETTING, &scratch_32);
01acf691 AL	351
	352	if ((scratch_32 & 0xff000000) == 0x01000000) {
	353	scratch_32 &= 0x0000FFFF;
	354	scratch_32 \|= 0x1F340000;
	355
	356	pci_write_config_dword(chip->pdev,
	357	O2_SD_PLL_SETTING, scratch_32);
	358	} else {
	359	scratch_32 &= 0x0000FFFF;
	360	scratch_32 \|= 0x2c280000;
	361
	362	pci_write_config_dword(chip->pdev,
	363	O2_SD_PLL_SETTING, scratch_32);
	364
	365	ret = pci_read_config_dword(chip->pdev,
	366	O2_SD_FUNC_REG4,
	367	&scratch_32);
	368	scratch_32 \|= (1 << 22);
	369	pci_write_config_dword(chip->pdev,
	370	O2_SD_FUNC_REG4, scratch_32);
	371	}
	372
706adf6b PG	373	/* Set Tuning Windows to 5 */
	374	pci_write_config_byte(chip->pdev,
	375	O2_SD_TUNING_CTRL, 0x55);
01acf691 AL	376	/* Lock WP */
	377	ret = pci_read_config_byte(chip->pdev,
	378	O2_SD_LOCK_WP, &scratch);
	379	if (ret)
	380	return ret;
	381	scratch \|= 0x80;
	382	pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
	383	break;
	384	}
	385
	386	return 0;
	387	}
	388	EXPORT_SYMBOL_GPL(sdhci_pci_o2_probe);
	389
	390	int sdhci_pci_o2_resume(struct sdhci_pci_chip *chip)
	391	{
	392	sdhci_pci_o2_probe(chip);
	393	return 0;
	394	}
	395	EXPORT_SYMBOL_GPL(sdhci_pci_o2_resume);