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mmc: sdhci-acpi: add more device ids
[mirror_ubuntu-zesty-kernel.git] / drivers / mmc / host / sdhci-pci.c
CommitLineData
b8c86fc5
PO		 1/* linux/drivers/mmc/host/sdhci-pci.c - SDHCI on PCI bus interface
2 *
3 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or (at
8 * your option) any later version.
9 *
10 * Thanks to the following companies for their support:
11 *
12 * - JMicron (hardware and technical support)
13 */
14
15#include <linux/delay.h>
16#include <linux/highmem.h>
88b47679 17#include <linux/module.h>
b8c86fc5
PO		 18#include <linux/pci.h>
19#include <linux/dma-mapping.h>
5a0e3ad6 20#include <linux/slab.h>
ccc92c23 21#include <linux/device.h>
b8c86fc5 22#include <linux/mmc/host.h>
b177bc91
AP		 23#include <linux/scatterlist.h>
24#include <linux/io.h>
0f201655 25#include <linux/gpio.h>
66fd8ad5 26#include <linux/pm_runtime.h>
52c506f0 27#include <linux/mmc/sdhci-pci-data.h>
b8c86fc5
PO		 28
29#include "sdhci.h"
30
296e0b03
AS		 31/*
32 * PCI device IDs
33 */
34#define PCI_DEVICE_ID_INTEL_PCH_SDIO0 0x8809
35#define PCI_DEVICE_ID_INTEL_PCH_SDIO1 0x880a
36
b8c86fc5
PO		 37/*
38 * PCI registers
39 */
40
41#define PCI_SDHCI_IFPIO 0x00
42#define PCI_SDHCI_IFDMA 0x01
43#define PCI_SDHCI_IFVENDOR 0x02
44
45#define PCI_SLOT_INFO 0x40 /* 8 bits */
46#define PCI_SLOT_INFO_SLOTS(x) ((x >> 4) & 7)
47#define PCI_SLOT_INFO_FIRST_BAR_MASK 0x07
48
49#define MAX_SLOTS 8
50
22606405 51struct sdhci_pci_chip;
4489428a 52struct sdhci_pci_slot;
22606405
PO		 53
54struct sdhci_pci_fixes {
55 unsigned int quirks;
f3c55a7b 56 unsigned int quirks2;
c43fd774 57 bool allow_runtime_pm;
22606405 58
b177bc91 59 int (*probe) (struct sdhci_pci_chip *);
45211e21 60
b177bc91
AP		 61 int (*probe_slot) (struct sdhci_pci_slot *);
62 void (*remove_slot) (struct sdhci_pci_slot *, int);
4489428a 63
29495aa0 64 int (*suspend) (struct sdhci_pci_chip *);
b177bc91 65 int (*resume) (struct sdhci_pci_chip *);
22606405
PO		 66};
67
68struct sdhci_pci_slot {
69 struct sdhci_pci_chip *chip;
70 struct sdhci_host *host;
52c506f0 71 struct sdhci_pci_data *data;
b8c86fc5 72
22606405 73 int pci_bar;
0f201655 74 int rst_n_gpio;
66fd8ad5
AH		 75 int cd_gpio;
76 int cd_irq;
22606405
PO		 77};
78
79struct sdhci_pci_chip {
80 struct pci_dev *pdev;
81
82 unsigned int quirks;
f3c55a7b 83 unsigned int quirks2;
c43fd774 84 bool allow_runtime_pm;
22606405
PO		 85 const struct sdhci_pci_fixes *fixes;
86
87 int num_slots; /* Slots on controller */
88 struct sdhci_pci_slot *slots[MAX_SLOTS]; /* Pointers to host slots */
89};
90
91
92/*****************************************************************************\
93 * *
94 * Hardware specific quirk handling *
95 * *
96\*****************************************************************************/
97
98static int ricoh_probe(struct sdhci_pci_chip *chip)
99{
c99436fb
CB		 100 if (chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG ||
101 chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SONY)
22606405 102 chip->quirks |= SDHCI_QUIRK_NO_CARD_NO_RESET;
ccc92c23
ML		 103 return 0;
104}
105
106static int ricoh_mmc_probe_slot(struct sdhci_pci_slot *slot)
107{
108 slot->host->caps =
109 ((0x21 << SDHCI_TIMEOUT_CLK_SHIFT)
110 & SDHCI_TIMEOUT_CLK_MASK) |
22606405 111
ccc92c23
ML		 112 ((0x21 << SDHCI_CLOCK_BASE_SHIFT)
113 & SDHCI_CLOCK_BASE_MASK) |
114
115 SDHCI_TIMEOUT_CLK_UNIT |
116 SDHCI_CAN_VDD_330 |
1a1f1f04 117 SDHCI_CAN_DO_HISPD |
ccc92c23
ML		 118 SDHCI_CAN_DO_SDMA;
119 return 0;
120}
121
122static int ricoh_mmc_resume(struct sdhci_pci_chip *chip)
123{
124 /* Apply a delay to allow controller to settle */
125 /* Otherwise it becomes confused if card state changed
126 during suspend */
127 msleep(500);
22606405
PO		 128 return 0;
129}
130
131static const struct sdhci_pci_fixes sdhci_ricoh = {
132 .probe = ricoh_probe,
84938294
VK		 133 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR |
134 SDHCI_QUIRK_FORCE_DMA |
135 SDHCI_QUIRK_CLOCK_BEFORE_RESET,
22606405
PO		 136};
137
ccc92c23
ML		 138static const struct sdhci_pci_fixes sdhci_ricoh_mmc = {
139 .probe_slot = ricoh_mmc_probe_slot,
140 .resume = ricoh_mmc_resume,
141 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR |
142 SDHCI_QUIRK_CLOCK_BEFORE_RESET |
143 SDHCI_QUIRK_NO_CARD_NO_RESET |
144 SDHCI_QUIRK_MISSING_CAPS
145};
146
22606405
PO		 147static const struct sdhci_pci_fixes sdhci_ene_712 = {
148 .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE |
149 SDHCI_QUIRK_BROKEN_DMA,
150};
151
152static const struct sdhci_pci_fixes sdhci_ene_714 = {
153 .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE |
154 SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS |
155 SDHCI_QUIRK_BROKEN_DMA,
156};
157
158static const struct sdhci_pci_fixes sdhci_cafe = {
159 .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER |
a0874897 160 SDHCI_QUIRK_NO_BUSY_IRQ |
55fc05b7 161 SDHCI_QUIRK_BROKEN_CARD_DETECTION |
ee53ab5d 162 SDHCI_QUIRK_BROKEN_TIMEOUT_VAL,
22606405
PO		 163};
164
68077b02
ML		 165static int mrst_hc_probe_slot(struct sdhci_pci_slot *slot)
166{
167 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA;
168 return 0;
169}
170
f9ee3eab
AC		 171/*
172 * ADMA operation is disabled for Moorestown platform due to
173 * hardware bugs.
174 */
35ac6f08 175static int mrst_hc_probe(struct sdhci_pci_chip *chip)
f9ee3eab
AC		 176{
177 /*
35ac6f08
JP		 178 * slots number is fixed here for MRST as SDIO3/5 are never used and
179 * have hardware bugs.
f9ee3eab
AC		 180 */
181 chip->num_slots = 1;
182 return 0;
183}
184
296e0b03
AS		 185static int pch_hc_probe_slot(struct sdhci_pci_slot *slot)
186{
187 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA;
188 return 0;
189}
190
66fd8ad5
AH		 191#ifdef CONFIG_PM_RUNTIME
192
c5e027a4 193static irqreturn_t sdhci_pci_sd_cd(int irq, void *dev_id)
66fd8ad5
AH		 194{
195 struct sdhci_pci_slot *slot = dev_id;
196 struct sdhci_host *host = slot->host;
197
198 mmc_detect_change(host->mmc, msecs_to_jiffies(200));
199 return IRQ_HANDLED;
200}
201
c5e027a4 202static void sdhci_pci_add_own_cd(struct sdhci_pci_slot *slot)
66fd8ad5 203{
c5e027a4 204 int err, irq, gpio = slot->cd_gpio;
66fd8ad5
AH		 205
206 slot->cd_gpio = -EINVAL;
207 slot->cd_irq = -EINVAL;
208
c5e027a4
AH		 209 if (!gpio_is_valid(gpio))
210 return;
211
66fd8ad5
AH		 212 err = gpio_request(gpio, "sd_cd");
213 if (err < 0)
214 goto out;
215
216 err = gpio_direction_input(gpio);
217 if (err < 0)
218 goto out_free;
219
220 irq = gpio_to_irq(gpio);
221 if (irq < 0)
222 goto out_free;
223
c5e027a4 224 err = request_irq(irq, sdhci_pci_sd_cd, IRQF_TRIGGER_RISING |
66fd8ad5
AH		 225 IRQF_TRIGGER_FALLING, "sd_cd", slot);
226 if (err)
227 goto out_free;
228
229 slot->cd_gpio = gpio;
230 slot->cd_irq = irq;
66fd8ad5 231
c5e027a4 232 return;
66fd8ad5
AH		 233
234out_free:
235 gpio_free(gpio);
236out:
237 dev_warn(&slot->chip->pdev->dev, "failed to setup card detect wake up\n");
66fd8ad5
AH		 238}
239
c5e027a4 240static void sdhci_pci_remove_own_cd(struct sdhci_pci_slot *slot)
66fd8ad5
AH		 241{
242 if (slot->cd_irq >= 0)
243 free_irq(slot->cd_irq, slot);
c5e027a4
AH		 244 if (gpio_is_valid(slot->cd_gpio))
245 gpio_free(slot->cd_gpio);
66fd8ad5
AH		 246}
247
248#else
249
c5e027a4
AH		 250static inline void sdhci_pci_add_own_cd(struct sdhci_pci_slot *slot)
251{
252}
253
254static inline void sdhci_pci_remove_own_cd(struct sdhci_pci_slot *slot)
255{
256}
66fd8ad5
AH		 257
258#endif
259
0d013bcf
AH		 260static int mfd_emmc_probe_slot(struct sdhci_pci_slot *slot)
261{
66fd8ad5 262 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE;
da721cf7
AH		 263 slot->host->mmc->caps2 |= MMC_CAP2_BOOTPART_NOACC |
264 MMC_CAP2_HC_ERASE_SZ;
0d013bcf
AH		 265 return 0;
266}
267
93933508
AH		 268static int mfd_sdio_probe_slot(struct sdhci_pci_slot *slot)
269{
012e4671 270 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE;
93933508
AH		 271 return 0;
272}
273
f9ee3eab
AC		 274static const struct sdhci_pci_fixes sdhci_intel_mrst_hc0 = {
275 .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT,
68077b02 276 .probe_slot = mrst_hc_probe_slot,
f9ee3eab
AC		 277};
278
35ac6f08 279static const struct sdhci_pci_fixes sdhci_intel_mrst_hc1_hc2 = {
f9ee3eab 280 .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT,
35ac6f08 281 .probe = mrst_hc_probe,
f9ee3eab
AC		 282};
283
29229052
XS		 284static const struct sdhci_pci_fixes sdhci_intel_mfd_sd = {
285 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
c43fd774 286 .allow_runtime_pm = true,
29229052
XS		 287};
288
0d013bcf
AH		 289static const struct sdhci_pci_fixes sdhci_intel_mfd_sdio = {
290 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
f3c55a7b 291 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON,
c43fd774 292 .allow_runtime_pm = true,
93933508 293 .probe_slot = mfd_sdio_probe_slot,
0d013bcf
AH		 294};
295
296static const struct sdhci_pci_fixes sdhci_intel_mfd_emmc = {
29229052 297 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
c43fd774 298 .allow_runtime_pm = true,
0d013bcf 299 .probe_slot = mfd_emmc_probe_slot,
29229052
XS		 300};
301
296e0b03
AS		 302static const struct sdhci_pci_fixes sdhci_intel_pch_sdio = {
303 .quirks = SDHCI_QUIRK_BROKEN_ADMA,
304 .probe_slot = pch_hc_probe_slot,
305};
306
26daa1ed
JL		 307/* O2Micro extra registers */
308#define O2_SD_LOCK_WP 0xD3
309#define O2_SD_MULTI_VCC3V 0xEE
310#define O2_SD_CLKREQ 0xEC
311#define O2_SD_CAPS 0xE0
312#define O2_SD_ADMA1 0xE2
313#define O2_SD_ADMA2 0xE7
314#define O2_SD_INF_MOD 0xF1
315
316static int o2_probe(struct sdhci_pci_chip *chip)
317{
318 int ret;
319 u8 scratch;
320
321 switch (chip->pdev->device) {
322 case PCI_DEVICE_ID_O2_8220:
323 case PCI_DEVICE_ID_O2_8221:
324 case PCI_DEVICE_ID_O2_8320:
325 case PCI_DEVICE_ID_O2_8321:
326 /* This extra setup is required due to broken ADMA. */
327 ret = pci_read_config_byte(chip->pdev, O2_SD_LOCK_WP, &scratch);
328 if (ret)
329 return ret;
330 scratch &= 0x7f;
331 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
332
333 /* Set Multi 3 to VCC3V# */
334 pci_write_config_byte(chip->pdev, O2_SD_MULTI_VCC3V, 0x08);
335
336 /* Disable CLK_REQ# support after media DET */
337 ret = pci_read_config_byte(chip->pdev, O2_SD_CLKREQ, &scratch);
338 if (ret)
339 return ret;
340 scratch |= 0x20;
341 pci_write_config_byte(chip->pdev, O2_SD_CLKREQ, scratch);
342
343 /* Choose capabilities, enable SDMA. We have to write 0x01
344 * to the capabilities register first to unlock it.
345 */
346 ret = pci_read_config_byte(chip->pdev, O2_SD_CAPS, &scratch);
347 if (ret)
348 return ret;
349 scratch |= 0x01;
350 pci_write_config_byte(chip->pdev, O2_SD_CAPS, scratch);
351 pci_write_config_byte(chip->pdev, O2_SD_CAPS, 0x73);
352
353 /* Disable ADMA1/2 */
354 pci_write_config_byte(chip->pdev, O2_SD_ADMA1, 0x39);
355 pci_write_config_byte(chip->pdev, O2_SD_ADMA2, 0x08);
356
357 /* Disable the infinite transfer mode */
358 ret = pci_read_config_byte(chip->pdev, O2_SD_INF_MOD, &scratch);
359 if (ret)
360 return ret;
361 scratch |= 0x08;
362 pci_write_config_byte(chip->pdev, O2_SD_INF_MOD, scratch);
363
364 /* Lock WP */
365 ret = pci_read_config_byte(chip->pdev, O2_SD_LOCK_WP, &scratch);
366 if (ret)
367 return ret;
368 scratch |= 0x80;
369 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
370 }
371
372 return 0;
373}
374
45211e21
PO		 375static int jmicron_pmos(struct sdhci_pci_chip *chip, int on)
376{
377 u8 scratch;
378 int ret;
379
380 ret = pci_read_config_byte(chip->pdev, 0xAE, &scratch);
381 if (ret)
382 return ret;
383
384 /*
385 * Turn PMOS on [bit 0], set over current detection to 2.4 V
386 * [bit 1:2] and enable over current debouncing [bit 6].
387 */
388 if (on)
389 scratch |= 0x47;
390 else
391 scratch &= ~0x47;
392
393 ret = pci_write_config_byte(chip->pdev, 0xAE, scratch);
394 if (ret)
395 return ret;
396
397 return 0;
398}
399
400static int jmicron_probe(struct sdhci_pci_chip *chip)
401{
402 int ret;
8f230f45 403 u16 mmcdev = 0;
45211e21 404
93fc48c7
PO		 405 if (chip->pdev->revision == 0) {
406 chip->quirks |= SDHCI_QUIRK_32BIT_DMA_ADDR |
407 SDHCI_QUIRK_32BIT_DMA_SIZE |
2134a922 408 SDHCI_QUIRK_32BIT_ADMA_SIZE |
4a3cba32 409 SDHCI_QUIRK_RESET_AFTER_REQUEST |
86a6a874 410 SDHCI_QUIRK_BROKEN_SMALL_PIO;
93fc48c7
PO		 411 }
412
4489428a
PO		 413 /*
414 * JMicron chips can have two interfaces to the same hardware
415 * in order to work around limitations in Microsoft's driver.
416 * We need to make sure we only bind to one of them.
417 *
418 * This code assumes two things:
419 *
420 * 1. The PCI code adds subfunctions in order.
421 *
422 * 2. The MMC interface has a lower subfunction number
423 * than the SD interface.
424 */
8f230f45
TI		 425 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_SD)
426 mmcdev = PCI_DEVICE_ID_JMICRON_JMB38X_MMC;
427 else if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD)
428 mmcdev = PCI_DEVICE_ID_JMICRON_JMB388_ESD;
429
430 if (mmcdev) {
4489428a
PO		 431 struct pci_dev *sd_dev;
432
433 sd_dev = NULL;
434 while ((sd_dev = pci_get_device(PCI_VENDOR_ID_JMICRON,
8f230f45 435 mmcdev, sd_dev)) != NULL) {
4489428a
PO		 436 if ((PCI_SLOT(chip->pdev->devfn) ==
437 PCI_SLOT(sd_dev->devfn)) &&
438 (chip->pdev->bus == sd_dev->bus))
439 break;
440 }
441
442 if (sd_dev) {
443 pci_dev_put(sd_dev);
444 dev_info(&chip->pdev->dev, "Refusing to bind to "
445 "secondary interface.\n");
446 return -ENODEV;
447 }
448 }
449
45211e21
PO		 450 /*
451 * JMicron chips need a bit of a nudge to enable the power
452 * output pins.
453 */
454 ret = jmicron_pmos(chip, 1);
455 if (ret) {
456 dev_err(&chip->pdev->dev, "Failure enabling card power\n");
457 return ret;
458 }
459
82b0e23a
TI		 460 /* quirk for unsable RO-detection on JM388 chips */
461 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD ||
462 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD)
463 chip->quirks |= SDHCI_QUIRK_UNSTABLE_RO_DETECT;
464
45211e21
PO		 465 return 0;
466}
467
4489428a
PO		 468static void jmicron_enable_mmc(struct sdhci_host *host, int on)
469{
470 u8 scratch;
471
472 scratch = readb(host->ioaddr + 0xC0);
473
474 if (on)
475 scratch |= 0x01;
476 else
477 scratch &= ~0x01;
478
479 writeb(scratch, host->ioaddr + 0xC0);
480}
481
482static int jmicron_probe_slot(struct sdhci_pci_slot *slot)
483{
2134a922
PO		 484 if (slot->chip->pdev->revision == 0) {
485 u16 version;
486
487 version = readl(slot->host->ioaddr + SDHCI_HOST_VERSION);
488 version = (version & SDHCI_VENDOR_VER_MASK) >>
489 SDHCI_VENDOR_VER_SHIFT;
490
491 /*
492 * Older versions of the chip have lots of nasty glitches
493 * in the ADMA engine. It's best just to avoid it
494 * completely.
495 */
496 if (version < 0xAC)
497 slot->host->quirks |= SDHCI_QUIRK_BROKEN_ADMA;
498 }
499
8f230f45
TI		 500 /* JM388 MMC doesn't support 1.8V while SD supports it */
501 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) {
502 slot->host->ocr_avail_sd = MMC_VDD_32_33 | MMC_VDD_33_34 |
503 MMC_VDD_29_30 | MMC_VDD_30_31 |
504 MMC_VDD_165_195; /* allow 1.8V */
505 slot->host->ocr_avail_mmc = MMC_VDD_32_33 | MMC_VDD_33_34 |
506 MMC_VDD_29_30 | MMC_VDD_30_31; /* no 1.8V for MMC */
507 }
508
4489428a
PO		 509 /*
510 * The secondary interface requires a bit set to get the
511 * interrupts.
512 */
8f230f45
TI		 513 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
514 slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD)
4489428a
PO		 515 jmicron_enable_mmc(slot->host, 1);
516
d75c1084
TI		 517 slot->host->mmc->caps |= MMC_CAP_BUS_WIDTH_TEST;
518
4489428a
PO		 519 return 0;
520}
521
1e72859e 522static void jmicron_remove_slot(struct sdhci_pci_slot *slot, int dead)
4489428a 523{
1e72859e
PO		 524 if (dead)
525 return;
526
8f230f45
TI		 527 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
528 slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD)
4489428a
PO		 529 jmicron_enable_mmc(slot->host, 0);
530}
531
29495aa0 532static int jmicron_suspend(struct sdhci_pci_chip *chip)
4489428a
PO		 533{
534 int i;
535
8f230f45
TI		 536 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
537 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) {
b177bc91 538 for (i = 0; i < chip->num_slots; i++)
4489428a
PO		 539 jmicron_enable_mmc(chip->slots[i]->host, 0);
540 }
541
542 return 0;
543}
544
45211e21
PO		 545static int jmicron_resume(struct sdhci_pci_chip *chip)
546{
4489428a
PO		 547 int ret, i;
548
8f230f45
TI		 549 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
550 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) {
b177bc91 551 for (i = 0; i < chip->num_slots; i++)
4489428a
PO		 552 jmicron_enable_mmc(chip->slots[i]->host, 1);
553 }
45211e21
PO		 554
555 ret = jmicron_pmos(chip, 1);
556 if (ret) {
557 dev_err(&chip->pdev->dev, "Failure enabling card power\n");
558 return ret;
559 }
560
561 return 0;
562}
563
26daa1ed
JL		 564static const struct sdhci_pci_fixes sdhci_o2 = {
565 .probe = o2_probe,
566};
567
22606405 568static const struct sdhci_pci_fixes sdhci_jmicron = {
45211e21
PO		 569 .probe = jmicron_probe,
570
4489428a
PO		 571 .probe_slot = jmicron_probe_slot,
572 .remove_slot = jmicron_remove_slot,
573
574 .suspend = jmicron_suspend,
45211e21 575 .resume = jmicron_resume,
22606405
PO		 576};
577
a7a6186c
NP		 578/* SysKonnect CardBus2SDIO extra registers */
579#define SYSKT_CTRL 0x200
580#define SYSKT_RDFIFO_STAT 0x204
581#define SYSKT_WRFIFO_STAT 0x208
582#define SYSKT_POWER_DATA 0x20c
583#define SYSKT_POWER_330 0xef
584#define SYSKT_POWER_300 0xf8
585#define SYSKT_POWER_184 0xcc
586#define SYSKT_POWER_CMD 0x20d
587#define SYSKT_POWER_START (1 << 7)
588#define SYSKT_POWER_STATUS 0x20e
589#define SYSKT_POWER_STATUS_OK (1 << 0)
590#define SYSKT_BOARD_REV 0x210
591#define SYSKT_CHIP_REV 0x211
592#define SYSKT_CONF_DATA 0x212
593#define SYSKT_CONF_DATA_1V8 (1 << 2)
594#define SYSKT_CONF_DATA_2V5 (1 << 1)
595#define SYSKT_CONF_DATA_3V3 (1 << 0)
596
597static int syskt_probe(struct sdhci_pci_chip *chip)
598{
599 if ((chip->pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) {
600 chip->pdev->class &= ~0x0000FF;
601 chip->pdev->class |= PCI_SDHCI_IFDMA;
602 }
603 return 0;
604}
605
606static int syskt_probe_slot(struct sdhci_pci_slot *slot)
607{
608 int tm, ps;
609
610 u8 board_rev = readb(slot->host->ioaddr + SYSKT_BOARD_REV);
611 u8 chip_rev = readb(slot->host->ioaddr + SYSKT_CHIP_REV);
612 dev_info(&slot->chip->pdev->dev, "SysKonnect CardBus2SDIO, "
613 "board rev %d.%d, chip rev %d.%d\n",
614 board_rev >> 4, board_rev & 0xf,
615 chip_rev >> 4, chip_rev & 0xf);
616 if (chip_rev >= 0x20)
617 slot->host->quirks |= SDHCI_QUIRK_FORCE_DMA;
618
619 writeb(SYSKT_POWER_330, slot->host->ioaddr + SYSKT_POWER_DATA);
620 writeb(SYSKT_POWER_START, slot->host->ioaddr + SYSKT_POWER_CMD);
621 udelay(50);
622 tm = 10; /* Wait max 1 ms */
623 do {
624 ps = readw(slot->host->ioaddr + SYSKT_POWER_STATUS);
625 if (ps & SYSKT_POWER_STATUS_OK)
626 break;
627 udelay(100);
628 } while (--tm);
629 if (!tm) {
630 dev_err(&slot->chip->pdev->dev,
631 "power regulator never stabilized");
632 writeb(0, slot->host->ioaddr + SYSKT_POWER_CMD);
633 return -ENODEV;
634 }
635
636 return 0;
637}
638
639static const struct sdhci_pci_fixes sdhci_syskt = {
640 .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER,
641 .probe = syskt_probe,
642 .probe_slot = syskt_probe_slot,
643};
644
557b0697
HW		 645static int via_probe(struct sdhci_pci_chip *chip)
646{
647 if (chip->pdev->revision == 0x10)
648 chip->quirks |= SDHCI_QUIRK_DELAY_AFTER_POWER;
649
650 return 0;
651}
652
653static const struct sdhci_pci_fixes sdhci_via = {
654 .probe = via_probe,
655};
656
9647f84d 657static const struct pci_device_id pci_ids[] = {
b8c86fc5
PO		 658 {
659 .vendor = PCI_VENDOR_ID_RICOH,
660 .device = PCI_DEVICE_ID_RICOH_R5C822,
22606405 661 .subvendor = PCI_ANY_ID,
b8c86fc5 662 .subdevice = PCI_ANY_ID,
22606405 663 .driver_data = (kernel_ulong_t)&sdhci_ricoh,
b8c86fc5
PO		 664 },
665
ccc92c23
ML		 666 {
667 .vendor = PCI_VENDOR_ID_RICOH,
668 .device = 0x843,
669 .subvendor = PCI_ANY_ID,
670 .subdevice = PCI_ANY_ID,
671 .driver_data = (kernel_ulong_t)&sdhci_ricoh_mmc,
672 },
673
568133eb
PC		 674 {
675 .vendor = PCI_VENDOR_ID_RICOH,
676 .device = 0xe822,
677 .subvendor = PCI_ANY_ID,
678 .subdevice = PCI_ANY_ID,
679 .driver_data = (kernel_ulong_t)&sdhci_ricoh_mmc,
680 },
681
5fd11c07
MI		 682 {
683 .vendor = PCI_VENDOR_ID_RICOH,
684 .device = 0xe823,
685 .subvendor = PCI_ANY_ID,
686 .subdevice = PCI_ANY_ID,
687 .driver_data = (kernel_ulong_t)&sdhci_ricoh_mmc,
688 },
689
b8c86fc5
PO		 690 {
691 .vendor = PCI_VENDOR_ID_ENE,
692 .device = PCI_DEVICE_ID_ENE_CB712_SD,
693 .subvendor = PCI_ANY_ID,
694 .subdevice = PCI_ANY_ID,
22606405 695 .driver_data = (kernel_ulong_t)&sdhci_ene_712,
b8c86fc5
PO		 696 },
697
698 {
699 .vendor = PCI_VENDOR_ID_ENE,
700 .device = PCI_DEVICE_ID_ENE_CB712_SD_2,
701 .subvendor = PCI_ANY_ID,
702 .subdevice = PCI_ANY_ID,
22606405 703 .driver_data = (kernel_ulong_t)&sdhci_ene_712,
b8c86fc5
PO		 704 },
705
706 {
707 .vendor = PCI_VENDOR_ID_ENE,
708 .device = PCI_DEVICE_ID_ENE_CB714_SD,
709 .subvendor = PCI_ANY_ID,
710 .subdevice = PCI_ANY_ID,
22606405 711 .driver_data = (kernel_ulong_t)&sdhci_ene_714,
b8c86fc5
PO		 712 },
713
714 {
715 .vendor = PCI_VENDOR_ID_ENE,
716 .device = PCI_DEVICE_ID_ENE_CB714_SD_2,
717 .subvendor = PCI_ANY_ID,
718 .subdevice = PCI_ANY_ID,
22606405 719 .driver_data = (kernel_ulong_t)&sdhci_ene_714,
b8c86fc5
PO		 720 },
721
722 {
723 .vendor = PCI_VENDOR_ID_MARVELL,
8c5eb880 724 .device = PCI_DEVICE_ID_MARVELL_88ALP01_SD,
b8c86fc5
PO		 725 .subvendor = PCI_ANY_ID,
726 .subdevice = PCI_ANY_ID,
22606405 727 .driver_data = (kernel_ulong_t)&sdhci_cafe,
b8c86fc5
PO		 728 },
729
730 {
731 .vendor = PCI_VENDOR_ID_JMICRON,
732 .device = PCI_DEVICE_ID_JMICRON_JMB38X_SD,
733 .subvendor = PCI_ANY_ID,
734 .subdevice = PCI_ANY_ID,
22606405 735 .driver_data = (kernel_ulong_t)&sdhci_jmicron,
b8c86fc5
PO		 736 },
737
4489428a
PO		 738 {
739 .vendor = PCI_VENDOR_ID_JMICRON,
740 .device = PCI_DEVICE_ID_JMICRON_JMB38X_MMC,
741 .subvendor = PCI_ANY_ID,
742 .subdevice = PCI_ANY_ID,
743 .driver_data = (kernel_ulong_t)&sdhci_jmicron,
8f230f45
TI		 744 },
745
746 {
747 .vendor = PCI_VENDOR_ID_JMICRON,
748 .device = PCI_DEVICE_ID_JMICRON_JMB388_SD,
749 .subvendor = PCI_ANY_ID,
750 .subdevice = PCI_ANY_ID,
751 .driver_data = (kernel_ulong_t)&sdhci_jmicron,
752 },
753
754 {
755 .vendor = PCI_VENDOR_ID_JMICRON,
756 .device = PCI_DEVICE_ID_JMICRON_JMB388_ESD,
757 .subvendor = PCI_ANY_ID,
758 .subdevice = PCI_ANY_ID,
759 .driver_data = (kernel_ulong_t)&sdhci_jmicron,
4489428a
PO		 760 },
761
a7a6186c
NP		 762 {
763 .vendor = PCI_VENDOR_ID_SYSKONNECT,
764 .device = 0x8000,
765 .subvendor = PCI_ANY_ID,
766 .subdevice = PCI_ANY_ID,
767 .driver_data = (kernel_ulong_t)&sdhci_syskt,
768 },
769
557b0697
HW		 770 {
771 .vendor = PCI_VENDOR_ID_VIA,
772 .device = 0x95d0,
773 .subvendor = PCI_ANY_ID,
774 .subdevice = PCI_ANY_ID,
775 .driver_data = (kernel_ulong_t)&sdhci_via,
776 },
777
29229052
XS		 778 {
779 .vendor = PCI_VENDOR_ID_INTEL,
f9ee3eab
AC		 780 .device = PCI_DEVICE_ID_INTEL_MRST_SD0,
781 .subvendor = PCI_ANY_ID,
782 .subdevice = PCI_ANY_ID,
783 .driver_data = (kernel_ulong_t)&sdhci_intel_mrst_hc0,
784 },
785
786 {
787 .vendor = PCI_VENDOR_ID_INTEL,
788 .device = PCI_DEVICE_ID_INTEL_MRST_SD1,
789 .subvendor = PCI_ANY_ID,
790 .subdevice = PCI_ANY_ID,
35ac6f08
JP		 791 .driver_data = (kernel_ulong_t)&sdhci_intel_mrst_hc1_hc2,
792 },
793
794 {
795 .vendor = PCI_VENDOR_ID_INTEL,
796 .device = PCI_DEVICE_ID_INTEL_MRST_SD2,
797 .subvendor = PCI_ANY_ID,
798 .subdevice = PCI_ANY_ID,
799 .driver_data = (kernel_ulong_t)&sdhci_intel_mrst_hc1_hc2,
f9ee3eab
AC		 800 },
801
802 {
803 .vendor = PCI_VENDOR_ID_INTEL,
29229052
XS		 804 .device = PCI_DEVICE_ID_INTEL_MFD_SD,
805 .subvendor = PCI_ANY_ID,
806 .subdevice = PCI_ANY_ID,
807 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sd,
808 },
809
810 {
811 .vendor = PCI_VENDOR_ID_INTEL,
812 .device = PCI_DEVICE_ID_INTEL_MFD_SDIO1,
813 .subvendor = PCI_ANY_ID,
814 .subdevice = PCI_ANY_ID,
0d013bcf 815 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sdio,
29229052
XS		 816 },
817
818 {
819 .vendor = PCI_VENDOR_ID_INTEL,
820 .device = PCI_DEVICE_ID_INTEL_MFD_SDIO2,
821 .subvendor = PCI_ANY_ID,
822 .subdevice = PCI_ANY_ID,
0d013bcf 823 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sdio,
29229052
XS		 824 },
825
826 {
827 .vendor = PCI_VENDOR_ID_INTEL,
828 .device = PCI_DEVICE_ID_INTEL_MFD_EMMC0,
829 .subvendor = PCI_ANY_ID,
830 .subdevice = PCI_ANY_ID,
0d013bcf 831 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc,
29229052
XS		 832 },
833
834 {
835 .vendor = PCI_VENDOR_ID_INTEL,
836 .device = PCI_DEVICE_ID_INTEL_MFD_EMMC1,
837 .subvendor = PCI_ANY_ID,
838 .subdevice = PCI_ANY_ID,
0d013bcf 839 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc,
29229052
XS		 840 },
841
296e0b03
AS		 842 {
843 .vendor = PCI_VENDOR_ID_INTEL,
844 .device = PCI_DEVICE_ID_INTEL_PCH_SDIO0,
845 .subvendor = PCI_ANY_ID,
846 .subdevice = PCI_ANY_ID,
847 .driver_data = (kernel_ulong_t)&sdhci_intel_pch_sdio,
848 },
849
850 {
851 .vendor = PCI_VENDOR_ID_INTEL,
852 .device = PCI_DEVICE_ID_INTEL_PCH_SDIO1,
853 .subvendor = PCI_ANY_ID,
854 .subdevice = PCI_ANY_ID,
855 .driver_data = (kernel_ulong_t)&sdhci_intel_pch_sdio,
856 },
857
26daa1ed
JL		 858 {
859 .vendor = PCI_VENDOR_ID_O2,
860 .device = PCI_DEVICE_ID_O2_8120,
861 .subvendor = PCI_ANY_ID,
862 .subdevice = PCI_ANY_ID,
863 .driver_data = (kernel_ulong_t)&sdhci_o2,
864 },
865
866 {
867 .vendor = PCI_VENDOR_ID_O2,
868 .device = PCI_DEVICE_ID_O2_8220,
869 .subvendor = PCI_ANY_ID,
870 .subdevice = PCI_ANY_ID,
871 .driver_data = (kernel_ulong_t)&sdhci_o2,
872 },
873
874 {
875 .vendor = PCI_VENDOR_ID_O2,
876 .device = PCI_DEVICE_ID_O2_8221,
877 .subvendor = PCI_ANY_ID,
878 .subdevice = PCI_ANY_ID,
879 .driver_data = (kernel_ulong_t)&sdhci_o2,
880 },
881
882 {
883 .vendor = PCI_VENDOR_ID_O2,
884 .device = PCI_DEVICE_ID_O2_8320,
885 .subvendor = PCI_ANY_ID,
886 .subdevice = PCI_ANY_ID,
887 .driver_data = (kernel_ulong_t)&sdhci_o2,
888 },
889
890 {
891 .vendor = PCI_VENDOR_ID_O2,
892 .device = PCI_DEVICE_ID_O2_8321,
893 .subvendor = PCI_ANY_ID,
894 .subdevice = PCI_ANY_ID,
895 .driver_data = (kernel_ulong_t)&sdhci_o2,
896 },
897
b8c86fc5
PO		 898 { /* Generic SD host controller */
899 PCI_DEVICE_CLASS((PCI_CLASS_SYSTEM_SDHCI << 8), 0xFFFF00)
900 },
901
902 { /* end: all zeroes */ },
903};
904
905MODULE_DEVICE_TABLE(pci, pci_ids);
906
b8c86fc5
PO		 907/*****************************************************************************\
908 * *
909 * SDHCI core callbacks *
910 * *
911\*****************************************************************************/
912
913static int sdhci_pci_enable_dma(struct sdhci_host *host)
914{
915 struct sdhci_pci_slot *slot;
916 struct pci_dev *pdev;
917 int ret;
918
919 slot = sdhci_priv(host);
920 pdev = slot->chip->pdev;
921
922 if (((pdev->class & 0xFFFF00) == (PCI_CLASS_SYSTEM_SDHCI << 8)) &&
923 ((pdev->class & 0x0000FF) != PCI_SDHCI_IFDMA) &&
a13abc7b 924 (host->flags & SDHCI_USE_SDMA)) {
b8c86fc5
PO		 925 dev_warn(&pdev->dev, "Will use DMA mode even though HW "
926 "doesn't fully claim to support it.\n");
927 }
928
284901a9 929 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
b8c86fc5
PO		 930 if (ret)
931 return ret;
932
933 pci_set_master(pdev);
934
935 return 0;
936}
937
7bc088d3 938static int sdhci_pci_bus_width(struct sdhci_host *host, int width)
68077b02
ML		 939{
940 u8 ctrl;
941
942 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
943
944 switch (width) {
945 case MMC_BUS_WIDTH_8:
946 ctrl |= SDHCI_CTRL_8BITBUS;
947 ctrl &= ~SDHCI_CTRL_4BITBUS;
948 break;
949 case MMC_BUS_WIDTH_4:
950 ctrl |= SDHCI_CTRL_4BITBUS;
951 ctrl &= ~SDHCI_CTRL_8BITBUS;
952 break;
953 default:
954 ctrl &= ~(SDHCI_CTRL_8BITBUS | SDHCI_CTRL_4BITBUS);
955 break;
956 }
957
958 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
959
960 return 0;
961}
962
0f201655
AH		 963static void sdhci_pci_hw_reset(struct sdhci_host *host)
964{
965 struct sdhci_pci_slot *slot = sdhci_priv(host);
966 int rst_n_gpio = slot->rst_n_gpio;
967
968 if (!gpio_is_valid(rst_n_gpio))
969 return;
970 gpio_set_value_cansleep(rst_n_gpio, 0);
971 /* For eMMC, minimum is 1us but give it 10us for good measure */
972 udelay(10);
973 gpio_set_value_cansleep(rst_n_gpio, 1);
974 /* For eMMC, minimum is 200us but give it 300us for good measure */
975 usleep_range(300, 1000);
976}
977
c915568d 978static const struct sdhci_ops sdhci_pci_ops = {
b8c86fc5 979 .enable_dma = sdhci_pci_enable_dma,
7bc088d3 980 .platform_bus_width = sdhci_pci_bus_width,
0f201655 981 .hw_reset = sdhci_pci_hw_reset,
b8c86fc5
PO		 982};
983
984/*****************************************************************************\
985 * *
986 * Suspend/resume *
987 * *
988\*****************************************************************************/
989
990#ifdef CONFIG_PM
991
29495aa0 992static int sdhci_pci_suspend(struct device *dev)
b8c86fc5 993{
29495aa0 994 struct pci_dev *pdev = to_pci_dev(dev);
b8c86fc5
PO		 995 struct sdhci_pci_chip *chip;
996 struct sdhci_pci_slot *slot;
5f619704 997 mmc_pm_flag_t slot_pm_flags;
2f4cbb3d 998 mmc_pm_flag_t pm_flags = 0;
b8c86fc5
PO		 999 int i, ret;
1000
1001 chip = pci_get_drvdata(pdev);
1002 if (!chip)
1003 return 0;
1004
b177bc91 1005 for (i = 0; i < chip->num_slots; i++) {
b8c86fc5
PO		 1006 slot = chip->slots[i];
1007 if (!slot)
1008 continue;
1009
29495aa0 1010 ret = sdhci_suspend_host(slot->host);
b8c86fc5 1011
b678b91f
AL		 1012 if (ret)
1013 goto err_pci_suspend;
2f4cbb3d 1014
5f619704
DD		 1015 slot_pm_flags = slot->host->mmc->pm_flags;
1016 if (slot_pm_flags & MMC_PM_WAKE_SDIO_IRQ)
1017 sdhci_enable_irq_wakeups(slot->host);
1018
1019 pm_flags |= slot_pm_flags;
b8c86fc5
PO		 1020 }
1021
4489428a 1022 if (chip->fixes && chip->fixes->suspend) {
29495aa0 1023 ret = chip->fixes->suspend(chip);
b678b91f
AL		 1024 if (ret)
1025 goto err_pci_suspend;
4489428a
PO		 1026 }
1027
b8c86fc5 1028 pci_save_state(pdev);
2f4cbb3d 1029 if (pm_flags & MMC_PM_KEEP_POWER) {
5f619704
DD		 1030 if (pm_flags & MMC_PM_WAKE_SDIO_IRQ) {
1031 pci_pme_active(pdev, true);
2f4cbb3d 1032 pci_enable_wake(pdev, PCI_D3hot, 1);
5f619704 1033 }
2f4cbb3d
NP		 1034 pci_set_power_state(pdev, PCI_D3hot);
1035 } else {
29495aa0 1036 pci_enable_wake(pdev, PCI_D3hot, 0);
2f4cbb3d 1037 pci_disable_device(pdev);
29495aa0 1038 pci_set_power_state(pdev, PCI_D3hot);
2f4cbb3d 1039 }
b8c86fc5
PO		 1040
1041 return 0;
b678b91f
AL		 1042
1043err_pci_suspend:
1044 while (--i >= 0)
1045 sdhci_resume_host(chip->slots[i]->host);
1046 return ret;
b8c86fc5
PO		 1047}
1048
29495aa0 1049static int sdhci_pci_resume(struct device *dev)
b8c86fc5 1050{
29495aa0 1051 struct pci_dev *pdev = to_pci_dev(dev);
b8c86fc5
PO		 1052 struct sdhci_pci_chip *chip;
1053 struct sdhci_pci_slot *slot;
1054 int i, ret;
1055
1056 chip = pci_get_drvdata(pdev);
1057 if (!chip)
1058 return 0;
1059
1060 pci_set_power_state(pdev, PCI_D0);
1061 pci_restore_state(pdev);
1062 ret = pci_enable_device(pdev);
1063 if (ret)
1064 return ret;
1065
45211e21
PO		 1066 if (chip->fixes && chip->fixes->resume) {
1067 ret = chip->fixes->resume(chip);
1068 if (ret)
1069 return ret;
1070 }
1071
b177bc91 1072 for (i = 0; i < chip->num_slots; i++) {
b8c86fc5
PO		 1073 slot = chip->slots[i];
1074 if (!slot)
1075 continue;
1076
1077 ret = sdhci_resume_host(slot->host);
1078 if (ret)
1079 return ret;
1080 }
1081
1082 return 0;
1083}
1084
1085#else /* CONFIG_PM */
1086
1087#define sdhci_pci_suspend NULL
1088#define sdhci_pci_resume NULL
1089
1090#endif /* CONFIG_PM */
1091
66fd8ad5
AH		 1092#ifdef CONFIG_PM_RUNTIME
1093
1094static int sdhci_pci_runtime_suspend(struct device *dev)
1095{
1096 struct pci_dev *pdev = container_of(dev, struct pci_dev, dev);
1097 struct sdhci_pci_chip *chip;
1098 struct sdhci_pci_slot *slot;
66fd8ad5
AH		 1099 int i, ret;
1100
1101 chip = pci_get_drvdata(pdev);
1102 if (!chip)
1103 return 0;
1104
1105 for (i = 0; i < chip->num_slots; i++) {
1106 slot = chip->slots[i];
1107 if (!slot)
1108 continue;
1109
1110 ret = sdhci_runtime_suspend_host(slot->host);
1111
b678b91f
AL		 1112 if (ret)
1113 goto err_pci_runtime_suspend;
66fd8ad5
AH		 1114 }
1115
1116 if (chip->fixes && chip->fixes->suspend) {
29495aa0 1117 ret = chip->fixes->suspend(chip);
b678b91f
AL		 1118 if (ret)
1119 goto err_pci_runtime_suspend;
66fd8ad5
AH		 1120 }
1121
1122 return 0;
b678b91f
AL		 1123
1124err_pci_runtime_suspend:
1125 while (--i >= 0)
1126 sdhci_runtime_resume_host(chip->slots[i]->host);
1127 return ret;
66fd8ad5
AH		 1128}
1129
1130static int sdhci_pci_runtime_resume(struct device *dev)
1131{
1132 struct pci_dev *pdev = container_of(dev, struct pci_dev, dev);
1133 struct sdhci_pci_chip *chip;
1134 struct sdhci_pci_slot *slot;
1135 int i, ret;
1136
1137 chip = pci_get_drvdata(pdev);
1138 if (!chip)
1139 return 0;
1140
1141 if (chip->fixes && chip->fixes->resume) {
1142 ret = chip->fixes->resume(chip);
1143 if (ret)
1144 return ret;
1145 }
1146
1147 for (i = 0; i < chip->num_slots; i++) {
1148 slot = chip->slots[i];
1149 if (!slot)
1150 continue;
1151
1152 ret = sdhci_runtime_resume_host(slot->host);
1153 if (ret)
1154 return ret;
1155 }
1156
1157 return 0;
1158}
1159
1160static int sdhci_pci_runtime_idle(struct device *dev)
1161{
1162 return 0;
1163}
1164
1165#else
1166
1167#define sdhci_pci_runtime_suspend NULL
1168#define sdhci_pci_runtime_resume NULL
1169#define sdhci_pci_runtime_idle NULL
1170
1171#endif
1172
1173static const struct dev_pm_ops sdhci_pci_pm_ops = {
29495aa0
ML		 1174 .suspend = sdhci_pci_suspend,
1175 .resume = sdhci_pci_resume,
66fd8ad5
AH		 1176 .runtime_suspend = sdhci_pci_runtime_suspend,
1177 .runtime_resume = sdhci_pci_runtime_resume,
1178 .runtime_idle = sdhci_pci_runtime_idle,
1179};
1180
b8c86fc5
PO		 1181/*****************************************************************************\
1182 * *
1183 * Device probing/removal *
1184 * *
1185\*****************************************************************************/
1186
c3be1efd 1187static struct sdhci_pci_slot *sdhci_pci_probe_slot(
52c506f0
AH		 1188 struct pci_dev *pdev, struct sdhci_pci_chip *chip, int first_bar,
1189 int slotno)
b8c86fc5
PO		 1190{
1191 struct sdhci_pci_slot *slot;
1192 struct sdhci_host *host;
52c506f0 1193 int ret, bar = first_bar + slotno;
b8c86fc5
PO		 1194
1195 if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) {
1196 dev_err(&pdev->dev, "BAR %d is not iomem. Aborting.\n", bar);
1197 return ERR_PTR(-ENODEV);
1198 }
1199
90b3e6c5 1200 if (pci_resource_len(pdev, bar) < 0x100) {
b8c86fc5
PO		 1201 dev_err(&pdev->dev, "Invalid iomem size. You may "
1202 "experience problems.\n");
1203 }
1204
1205 if ((pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) {
1206 dev_err(&pdev->dev, "Vendor specific interface. Aborting.\n");
1207 return ERR_PTR(-ENODEV);
1208 }
1209
1210 if ((pdev->class & 0x0000FF) > PCI_SDHCI_IFVENDOR) {
1211 dev_err(&pdev->dev, "Unknown interface. Aborting.\n");
1212 return ERR_PTR(-ENODEV);
1213 }
1214
1215 host = sdhci_alloc_host(&pdev->dev, sizeof(struct sdhci_pci_slot));
1216 if (IS_ERR(host)) {
c60a32cd 1217 dev_err(&pdev->dev, "cannot allocate host\n");
dc0fd7b5 1218 return ERR_CAST(host);
b8c86fc5
PO		 1219 }
1220
1221 slot = sdhci_priv(host);
1222
1223 slot->chip = chip;
1224 slot->host = host;
1225 slot->pci_bar = bar;
0f201655 1226 slot->rst_n_gpio = -EINVAL;
c5e027a4 1227 slot->cd_gpio = -EINVAL;
b8c86fc5 1228
52c506f0
AH		 1229 /* Retrieve platform data if there is any */
1230 if (*sdhci_pci_get_data)
1231 slot->data = sdhci_pci_get_data(pdev, slotno);
1232
1233 if (slot->data) {
1234 if (slot->data->setup) {
1235 ret = slot->data->setup(slot->data);
1236 if (ret) {
1237 dev_err(&pdev->dev, "platform setup failed\n");
1238 goto free;
1239 }
1240 }
c5e027a4
AH		 1241 slot->rst_n_gpio = slot->data->rst_n_gpio;
1242 slot->cd_gpio = slot->data->cd_gpio;
52c506f0
AH		 1243 }
1244
b8c86fc5
PO		 1245 host->hw_name = "PCI";
1246 host->ops = &sdhci_pci_ops;
1247 host->quirks = chip->quirks;
f3c55a7b 1248 host->quirks2 = chip->quirks2;
b8c86fc5
PO		 1249
1250 host->irq = pdev->irq;
1251
1252 ret = pci_request_region(pdev, bar, mmc_hostname(host->mmc));
1253 if (ret) {
1254 dev_err(&pdev->dev, "cannot request region\n");
52c506f0 1255 goto cleanup;
b8c86fc5
PO		 1256 }
1257
092f82ed 1258 host->ioaddr = pci_ioremap_bar(pdev, bar);
b8c86fc5
PO		 1259 if (!host->ioaddr) {
1260 dev_err(&pdev->dev, "failed to remap registers\n");
9fdcdbb0 1261 ret = -ENOMEM;
b8c86fc5
PO		 1262 goto release;
1263 }
1264
4489428a
PO		 1265 if (chip->fixes && chip->fixes->probe_slot) {
1266 ret = chip->fixes->probe_slot(slot);
1267 if (ret)
1268 goto unmap;
1269 }
1270
c5e027a4
AH		 1271 if (gpio_is_valid(slot->rst_n_gpio)) {
1272 if (!gpio_request(slot->rst_n_gpio, "eMMC_reset")) {
1273 gpio_direction_output(slot->rst_n_gpio, 1);
1274 slot->host->mmc->caps |= MMC_CAP_HW_RESET;
1275 } else {
1276 dev_warn(&pdev->dev, "failed to request rst_n_gpio\n");
1277 slot->rst_n_gpio = -EINVAL;
1278 }
1279 }
1280
2f4cbb3d 1281 host->mmc->pm_caps = MMC_PM_KEEP_POWER | MMC_PM_WAKE_SDIO_IRQ;
eed222ac 1282 host->mmc->slotno = slotno;
a08b17be 1283 host->mmc->caps2 |= MMC_CAP2_NO_PRESCAN_POWERUP;
2f4cbb3d 1284
b8c86fc5
PO		 1285 ret = sdhci_add_host(host);
1286 if (ret)
4489428a 1287 goto remove;
b8c86fc5 1288
c5e027a4
AH		 1289 sdhci_pci_add_own_cd(slot);
1290
b8c86fc5
PO		 1291 return slot;
1292
4489428a 1293remove:
c5e027a4
AH		 1294 if (gpio_is_valid(slot->rst_n_gpio))
1295 gpio_free(slot->rst_n_gpio);
1296
4489428a 1297 if (chip->fixes && chip->fixes->remove_slot)
1e72859e 1298 chip->fixes->remove_slot(slot, 0);
4489428a 1299
b8c86fc5
PO		 1300unmap:
1301 iounmap(host->ioaddr);
1302
1303release:
1304 pci_release_region(pdev, bar);
c60a32cd 1305
52c506f0
AH		 1306cleanup:
1307 if (slot->data && slot->data->cleanup)
1308 slot->data->cleanup(slot->data);
1309
c60a32cd 1310free:
b8c86fc5
PO		 1311 sdhci_free_host(host);
1312
1313 return ERR_PTR(ret);
1314}
1315
1316static void sdhci_pci_remove_slot(struct sdhci_pci_slot *slot)
1317{
1e72859e
PO		 1318 int dead;
1319 u32 scratch;
1320
c5e027a4
AH		 1321 sdhci_pci_remove_own_cd(slot);
1322
1e72859e
PO		 1323 dead = 0;
1324 scratch = readl(slot->host->ioaddr + SDHCI_INT_STATUS);
1325 if (scratch == (u32)-1)
1326 dead = 1;
1327
1328 sdhci_remove_host(slot->host, dead);
4489428a 1329
c5e027a4
AH		 1330 if (gpio_is_valid(slot->rst_n_gpio))
1331 gpio_free(slot->rst_n_gpio);
1332
4489428a 1333 if (slot->chip->fixes && slot->chip->fixes->remove_slot)
1e72859e 1334 slot->chip->fixes->remove_slot(slot, dead);
4489428a 1335
52c506f0
AH		 1336 if (slot->data && slot->data->cleanup)
1337 slot->data->cleanup(slot->data);
1338
b8c86fc5 1339 pci_release_region(slot->chip->pdev, slot->pci_bar);
4489428a 1340
b8c86fc5
PO		 1341 sdhci_free_host(slot->host);
1342}
1343
c3be1efd 1344static void sdhci_pci_runtime_pm_allow(struct device *dev)
66fd8ad5
AH		 1345{
1346 pm_runtime_put_noidle(dev);
1347 pm_runtime_allow(dev);
1348 pm_runtime_set_autosuspend_delay(dev, 50);
1349 pm_runtime_use_autosuspend(dev);
1350 pm_suspend_ignore_children(dev, 1);
1351}
1352
6e0ee714 1353static void sdhci_pci_runtime_pm_forbid(struct device *dev)
66fd8ad5
AH		 1354{
1355 pm_runtime_forbid(dev);
1356 pm_runtime_get_noresume(dev);
1357}
1358
c3be1efd 1359static int sdhci_pci_probe(struct pci_dev *pdev,
b8c86fc5
PO		 1360 const struct pci_device_id *ent)
1361{
1362 struct sdhci_pci_chip *chip;
1363 struct sdhci_pci_slot *slot;
1364
cf5e23e1 1365 u8 slots, first_bar;
b8c86fc5
PO		 1366 int ret, i;
1367
1368 BUG_ON(pdev == NULL);
1369 BUG_ON(ent == NULL);
1370
b8c86fc5 1371 dev_info(&pdev->dev, "SDHCI controller found [%04x:%04x] (rev %x)\n",
cf5e23e1 1372 (int)pdev->vendor, (int)pdev->device, (int)pdev->revision);
b8c86fc5
PO		 1373
1374 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &slots);
1375 if (ret)
1376 return ret;
1377
1378 slots = PCI_SLOT_INFO_SLOTS(slots) + 1;
1379 dev_dbg(&pdev->dev, "found %d slot(s)\n", slots);
1380 if (slots == 0)
1381 return -ENODEV;
1382
1383 BUG_ON(slots > MAX_SLOTS);
1384
1385 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &first_bar);
1386 if (ret)
1387 return ret;
1388
1389 first_bar &= PCI_SLOT_INFO_FIRST_BAR_MASK;
1390
1391 if (first_bar > 5) {
1392 dev_err(&pdev->dev, "Invalid first BAR. Aborting.\n");
1393 return -ENODEV;
1394 }
1395
1396 ret = pci_enable_device(pdev);
1397 if (ret)
1398 return ret;
1399
1400 chip = kzalloc(sizeof(struct sdhci_pci_chip), GFP_KERNEL);
1401 if (!chip) {
1402 ret = -ENOMEM;
1403 goto err;
1404 }
1405
1406 chip->pdev = pdev;
b177bc91 1407 chip->fixes = (const struct sdhci_pci_fixes *)ent->driver_data;
c43fd774 1408 if (chip->fixes) {
22606405 1409 chip->quirks = chip->fixes->quirks;
f3c55a7b 1410 chip->quirks2 = chip->fixes->quirks2;
c43fd774
AH		 1411 chip->allow_runtime_pm = chip->fixes->allow_runtime_pm;
1412 }
b8c86fc5
PO		 1413 chip->num_slots = slots;
1414
1415 pci_set_drvdata(pdev, chip);
1416
22606405
PO		 1417 if (chip->fixes && chip->fixes->probe) {
1418 ret = chip->fixes->probe(chip);
1419 if (ret)
1420 goto free;
1421 }
1422
225d85fe
AC		 1423 slots = chip->num_slots; /* Quirk may have changed this */
1424
b177bc91 1425 for (i = 0; i < slots; i++) {
52c506f0 1426 slot = sdhci_pci_probe_slot(pdev, chip, first_bar, i);
b8c86fc5 1427 if (IS_ERR(slot)) {
b177bc91 1428 for (i--; i >= 0; i--)
b8c86fc5
PO		 1429 sdhci_pci_remove_slot(chip->slots[i]);
1430 ret = PTR_ERR(slot);
1431 goto free;
1432 }
1433
1434 chip->slots[i] = slot;
1435 }
1436
c43fd774
AH		 1437 if (chip->allow_runtime_pm)
1438 sdhci_pci_runtime_pm_allow(&pdev->dev);
66fd8ad5 1439
b8c86fc5
PO		 1440 return 0;
1441
1442free:
1443 pci_set_drvdata(pdev, NULL);
1444 kfree(chip);
1445
1446err:
1447 pci_disable_device(pdev);
1448 return ret;
1449}
1450
6e0ee714 1451static void sdhci_pci_remove(struct pci_dev *pdev)
b8c86fc5
PO		 1452{
1453 int i;
1454 struct sdhci_pci_chip *chip;
1455
1456 chip = pci_get_drvdata(pdev);
1457
1458 if (chip) {
c43fd774
AH		 1459 if (chip->allow_runtime_pm)
1460 sdhci_pci_runtime_pm_forbid(&pdev->dev);
1461
b177bc91 1462 for (i = 0; i < chip->num_slots; i++)
b8c86fc5
PO		 1463 sdhci_pci_remove_slot(chip->slots[i]);
1464
1465 pci_set_drvdata(pdev, NULL);
1466 kfree(chip);
1467 }
1468
1469 pci_disable_device(pdev);
1470}
1471
1472static struct pci_driver sdhci_driver = {
b177bc91 1473 .name = "sdhci-pci",
b8c86fc5 1474 .id_table = pci_ids,
b177bc91 1475 .probe = sdhci_pci_probe,
0433c143 1476 .remove = sdhci_pci_remove,
66fd8ad5
AH		 1477 .driver = {
1478 .pm = &sdhci_pci_pm_ops
1479 },
b8c86fc5
PO		 1480};
1481
acc69646 1482module_pci_driver(sdhci_driver);
b8c86fc5 1483
32710e8f 1484MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
b8c86fc5
PO		 1485MODULE_DESCRIPTION("Secure Digital Host Controller Interface PCI driver");
1486MODULE_LICENSE("GPL");
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