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mmc: Add .multi_io_quirk callback for multi I/O HW bug
[mirror_ubuntu-eoan-kernel.git] / drivers / mmc / host / sdhci-pci.c
CommitLineData
b8c86fc5
PO		 1/* linux/drivers/mmc/host/sdhci-pci.c - SDHCI on PCI bus interface
2 *
3 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or (at
8 * your option) any later version.
9 *
10 * Thanks to the following companies for their support:
11 *
12 * - JMicron (hardware and technical support)
13 */
14
15#include <linux/delay.h>
16#include <linux/highmem.h>
88b47679 17#include <linux/module.h>
b8c86fc5
PO		 18#include <linux/pci.h>
19#include <linux/dma-mapping.h>
5a0e3ad6 20#include <linux/slab.h>
ccc92c23 21#include <linux/device.h>
b8c86fc5 22#include <linux/mmc/host.h>
b177bc91
AP		 23#include <linux/scatterlist.h>
24#include <linux/io.h>
0f201655 25#include <linux/gpio.h>
66fd8ad5 26#include <linux/pm_runtime.h>
52c506f0 27#include <linux/mmc/sdhci-pci-data.h>
b8c86fc5
PO		 28
29#include "sdhci.h"
522624f9 30#include "sdhci-pci.h"
01acf691 31#include "sdhci-pci-o2micro.h"
22606405
PO		 32
33/*****************************************************************************\
34 * *
35 * Hardware specific quirk handling *
36 * *
37\*****************************************************************************/
38
39static int ricoh_probe(struct sdhci_pci_chip *chip)
40{
c99436fb
CB		 41 if (chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG ||
42 chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SONY)
22606405 43 chip->quirks |= SDHCI_QUIRK_NO_CARD_NO_RESET;
ccc92c23
ML		 44 return 0;
45}
46
47static int ricoh_mmc_probe_slot(struct sdhci_pci_slot *slot)
48{
49 slot->host->caps =
50 ((0x21 << SDHCI_TIMEOUT_CLK_SHIFT)
51 & SDHCI_TIMEOUT_CLK_MASK) |
22606405 52
ccc92c23
ML		 53 ((0x21 << SDHCI_CLOCK_BASE_SHIFT)
54 & SDHCI_CLOCK_BASE_MASK) |
55
56 SDHCI_TIMEOUT_CLK_UNIT |
57 SDHCI_CAN_VDD_330 |
1a1f1f04 58 SDHCI_CAN_DO_HISPD |
ccc92c23
ML		 59 SDHCI_CAN_DO_SDMA;
60 return 0;
61}
62
63static int ricoh_mmc_resume(struct sdhci_pci_chip *chip)
64{
65 /* Apply a delay to allow controller to settle */
66 /* Otherwise it becomes confused if card state changed
67 during suspend */
68 msleep(500);
22606405
PO		 69 return 0;
70}
71
72static const struct sdhci_pci_fixes sdhci_ricoh = {
73 .probe = ricoh_probe,
84938294
VK		 74 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR |
75 SDHCI_QUIRK_FORCE_DMA |
76 SDHCI_QUIRK_CLOCK_BEFORE_RESET,
22606405
PO		 77};
78
ccc92c23
ML		 79static const struct sdhci_pci_fixes sdhci_ricoh_mmc = {
80 .probe_slot = ricoh_mmc_probe_slot,
81 .resume = ricoh_mmc_resume,
82 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR |
83 SDHCI_QUIRK_CLOCK_BEFORE_RESET |
84 SDHCI_QUIRK_NO_CARD_NO_RESET |
85 SDHCI_QUIRK_MISSING_CAPS
86};
87
22606405
PO		 88static const struct sdhci_pci_fixes sdhci_ene_712 = {
89 .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE |
90 SDHCI_QUIRK_BROKEN_DMA,
91};
92
93static const struct sdhci_pci_fixes sdhci_ene_714 = {
94 .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE |
95 SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS |
96 SDHCI_QUIRK_BROKEN_DMA,
97};
98
99static const struct sdhci_pci_fixes sdhci_cafe = {
100 .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER |
a0874897 101 SDHCI_QUIRK_NO_BUSY_IRQ |
55fc05b7 102 SDHCI_QUIRK_BROKEN_CARD_DETECTION |
ee53ab5d 103 SDHCI_QUIRK_BROKEN_TIMEOUT_VAL,
22606405
PO		 104};
105
43e968ce
DB		 106static const struct sdhci_pci_fixes sdhci_intel_qrk = {
107 .quirks = SDHCI_QUIRK_NO_HISPD_BIT,
108};
109
68077b02
ML		 110static int mrst_hc_probe_slot(struct sdhci_pci_slot *slot)
111{
112 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA;
113 return 0;
114}
115
f9ee3eab
AC		 116/*
117 * ADMA operation is disabled for Moorestown platform due to
118 * hardware bugs.
119 */
35ac6f08 120static int mrst_hc_probe(struct sdhci_pci_chip *chip)
f9ee3eab
AC		 121{
122 /*
35ac6f08
JP		 123 * slots number is fixed here for MRST as SDIO3/5 are never used and
124 * have hardware bugs.
f9ee3eab
AC		 125 */
126 chip->num_slots = 1;
127 return 0;
128}
129
296e0b03
AS		 130static int pch_hc_probe_slot(struct sdhci_pci_slot *slot)
131{
132 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA;
133 return 0;
134}
135
66fd8ad5
AH		 136#ifdef CONFIG_PM_RUNTIME
137
c5e027a4 138static irqreturn_t sdhci_pci_sd_cd(int irq, void *dev_id)
66fd8ad5
AH		 139{
140 struct sdhci_pci_slot *slot = dev_id;
141 struct sdhci_host *host = slot->host;
142
143 mmc_detect_change(host->mmc, msecs_to_jiffies(200));
144 return IRQ_HANDLED;
145}
146
c5e027a4 147static void sdhci_pci_add_own_cd(struct sdhci_pci_slot *slot)
66fd8ad5 148{
c5e027a4 149 int err, irq, gpio = slot->cd_gpio;
66fd8ad5
AH		 150
151 slot->cd_gpio = -EINVAL;
152 slot->cd_irq = -EINVAL;
153
c5e027a4
AH		 154 if (!gpio_is_valid(gpio))
155 return;
156
66fd8ad5
AH		 157 err = gpio_request(gpio, "sd_cd");
158 if (err < 0)
159 goto out;
160
161 err = gpio_direction_input(gpio);
162 if (err < 0)
163 goto out_free;
164
165 irq = gpio_to_irq(gpio);
166 if (irq < 0)
167 goto out_free;
168
c5e027a4 169 err = request_irq(irq, sdhci_pci_sd_cd, IRQF_TRIGGER_RISING |
66fd8ad5
AH		 170 IRQF_TRIGGER_FALLING, "sd_cd", slot);
171 if (err)
172 goto out_free;
173
174 slot->cd_gpio = gpio;
175 slot->cd_irq = irq;
66fd8ad5 176
c5e027a4 177 return;
66fd8ad5
AH		 178
179out_free:
180 gpio_free(gpio);
181out:
182 dev_warn(&slot->chip->pdev->dev, "failed to setup card detect wake up\n");
66fd8ad5
AH		 183}
184
c5e027a4 185static void sdhci_pci_remove_own_cd(struct sdhci_pci_slot *slot)
66fd8ad5
AH		 186{
187 if (slot->cd_irq >= 0)
188 free_irq(slot->cd_irq, slot);
c5e027a4
AH		 189 if (gpio_is_valid(slot->cd_gpio))
190 gpio_free(slot->cd_gpio);
66fd8ad5
AH		 191}
192
193#else
194
c5e027a4
AH		 195static inline void sdhci_pci_add_own_cd(struct sdhci_pci_slot *slot)
196{
197}
198
199static inline void sdhci_pci_remove_own_cd(struct sdhci_pci_slot *slot)
200{
201}
66fd8ad5
AH		 202
203#endif
204
0d013bcf
AH		 205static int mfd_emmc_probe_slot(struct sdhci_pci_slot *slot)
206{
66fd8ad5 207 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE;
da721cf7
AH		 208 slot->host->mmc->caps2 |= MMC_CAP2_BOOTPART_NOACC |
209 MMC_CAP2_HC_ERASE_SZ;
0d013bcf
AH		 210 return 0;
211}
212
93933508
AH		 213static int mfd_sdio_probe_slot(struct sdhci_pci_slot *slot)
214{
012e4671 215 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE;
93933508
AH		 216 return 0;
217}
218
f9ee3eab
AC		 219static const struct sdhci_pci_fixes sdhci_intel_mrst_hc0 = {
220 .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT,
68077b02 221 .probe_slot = mrst_hc_probe_slot,
f9ee3eab
AC		 222};
223
35ac6f08 224static const struct sdhci_pci_fixes sdhci_intel_mrst_hc1_hc2 = {
f9ee3eab 225 .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT,
35ac6f08 226 .probe = mrst_hc_probe,
f9ee3eab
AC		 227};
228
29229052
XS		 229static const struct sdhci_pci_fixes sdhci_intel_mfd_sd = {
230 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
c43fd774 231 .allow_runtime_pm = true,
77a0122e 232 .own_cd_for_runtime_pm = true,
29229052
XS		 233};
234
0d013bcf
AH		 235static const struct sdhci_pci_fixes sdhci_intel_mfd_sdio = {
236 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
f3c55a7b 237 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON,
c43fd774 238 .allow_runtime_pm = true,
93933508 239 .probe_slot = mfd_sdio_probe_slot,
0d013bcf
AH		 240};
241
242static const struct sdhci_pci_fixes sdhci_intel_mfd_emmc = {
29229052 243 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
c43fd774 244 .allow_runtime_pm = true,
0d013bcf 245 .probe_slot = mfd_emmc_probe_slot,
29229052
XS		 246};
247
296e0b03
AS		 248static const struct sdhci_pci_fixes sdhci_intel_pch_sdio = {
249 .quirks = SDHCI_QUIRK_BROKEN_ADMA,
250 .probe_slot = pch_hc_probe_slot,
251};
252
c9faff6c
AH		 253static void sdhci_pci_int_hw_reset(struct sdhci_host *host)
254{
255 u8 reg;
256
257 reg = sdhci_readb(host, SDHCI_POWER_CONTROL);
258 reg |= 0x10;
259 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL);
260 /* For eMMC, minimum is 1us but give it 9us for good measure */
261 udelay(9);
262 reg &= ~0x10;
263 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL);
264 /* For eMMC, minimum is 200us but give it 300us for good measure */
265 usleep_range(300, 1000);
266}
267
728ef3d1
AH		 268static int byt_emmc_probe_slot(struct sdhci_pci_slot *slot)
269{
c9faff6c 270 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE |
f25c3372 271 MMC_CAP_HW_RESET | MMC_CAP_1_8V_DDR;
728ef3d1 272 slot->host->mmc->caps2 |= MMC_CAP2_HC_ERASE_SZ;
c9faff6c 273 slot->hw_reset = sdhci_pci_int_hw_reset;
728ef3d1
AH		 274 return 0;
275}
276
277static int byt_sdio_probe_slot(struct sdhci_pci_slot *slot)
278{
279 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE;
280 return 0;
281}
282
283static const struct sdhci_pci_fixes sdhci_intel_byt_emmc = {
284 .allow_runtime_pm = true,
285 .probe_slot = byt_emmc_probe_slot,
d61b5946 286 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
728ef3d1
AH		 287};
288
289static const struct sdhci_pci_fixes sdhci_intel_byt_sdio = {
290 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON,
291 .allow_runtime_pm = true,
292 .probe_slot = byt_sdio_probe_slot,
293};
294
295static const struct sdhci_pci_fixes sdhci_intel_byt_sd = {
7396e318
AH		 296 .quirks2 = SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON,
297 .allow_runtime_pm = true,
77a0122e 298 .own_cd_for_runtime_pm = true,
728ef3d1
AH		 299};
300
8776a165
DC		 301/* Define Host controllers for Intel Merrifield platform */
302#define INTEL_MRFL_EMMC_0 0
303#define INTEL_MRFL_EMMC_1 1
304
305static int intel_mrfl_mmc_probe_slot(struct sdhci_pci_slot *slot)
306{
307 if ((PCI_FUNC(slot->chip->pdev->devfn) != INTEL_MRFL_EMMC_0) &&
308 (PCI_FUNC(slot->chip->pdev->devfn) != INTEL_MRFL_EMMC_1))
309 /* SD support is not ready yet */
310 return -ENODEV;
311
312 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE |
313 MMC_CAP_1_8V_DDR;
314
315 return 0;
316}
317
318static const struct sdhci_pci_fixes sdhci_intel_mrfl_mmc = {
319 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
390145f9 320 .quirks2 = SDHCI_QUIRK2_BROKEN_HS200,
f1b55a55 321 .allow_runtime_pm = true,
8776a165
DC		 322 .probe_slot = intel_mrfl_mmc_probe_slot,
323};
324
26daa1ed
JL		 325/* O2Micro extra registers */
326#define O2_SD_LOCK_WP 0xD3
327#define O2_SD_MULTI_VCC3V 0xEE
328#define O2_SD_CLKREQ 0xEC
329#define O2_SD_CAPS 0xE0
330#define O2_SD_ADMA1 0xE2
331#define O2_SD_ADMA2 0xE7
332#define O2_SD_INF_MOD 0xF1
333
45211e21
PO		 334static int jmicron_pmos(struct sdhci_pci_chip *chip, int on)
335{
336 u8 scratch;
337 int ret;
338
339 ret = pci_read_config_byte(chip->pdev, 0xAE, &scratch);
340 if (ret)
341 return ret;
342
343 /*
344 * Turn PMOS on [bit 0], set over current detection to 2.4 V
345 * [bit 1:2] and enable over current debouncing [bit 6].
346 */
347 if (on)
348 scratch |= 0x47;
349 else
350 scratch &= ~0x47;
351
352 ret = pci_write_config_byte(chip->pdev, 0xAE, scratch);
353 if (ret)
354 return ret;
355
356 return 0;
357}
358
359static int jmicron_probe(struct sdhci_pci_chip *chip)
360{
361 int ret;
8f230f45 362 u16 mmcdev = 0;
45211e21 363
93fc48c7
PO		 364 if (chip->pdev->revision == 0) {
365 chip->quirks |= SDHCI_QUIRK_32BIT_DMA_ADDR |
366 SDHCI_QUIRK_32BIT_DMA_SIZE |
2134a922 367 SDHCI_QUIRK_32BIT_ADMA_SIZE |
4a3cba32 368 SDHCI_QUIRK_RESET_AFTER_REQUEST |
86a6a874 369 SDHCI_QUIRK_BROKEN_SMALL_PIO;
93fc48c7
PO		 370 }
371
4489428a
PO		 372 /*
373 * JMicron chips can have two interfaces to the same hardware
374 * in order to work around limitations in Microsoft's driver.
375 * We need to make sure we only bind to one of them.
376 *
377 * This code assumes two things:
378 *
379 * 1. The PCI code adds subfunctions in order.
380 *
381 * 2. The MMC interface has a lower subfunction number
382 * than the SD interface.
383 */
8f230f45
TI		 384 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_SD)
385 mmcdev = PCI_DEVICE_ID_JMICRON_JMB38X_MMC;
386 else if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD)
387 mmcdev = PCI_DEVICE_ID_JMICRON_JMB388_ESD;
388
389 if (mmcdev) {
4489428a
PO		 390 struct pci_dev *sd_dev;
391
392 sd_dev = NULL;
393 while ((sd_dev = pci_get_device(PCI_VENDOR_ID_JMICRON,
8f230f45 394 mmcdev, sd_dev)) != NULL) {
4489428a
PO		 395 if ((PCI_SLOT(chip->pdev->devfn) ==
396 PCI_SLOT(sd_dev->devfn)) &&
397 (chip->pdev->bus == sd_dev->bus))
398 break;
399 }
400
401 if (sd_dev) {
402 pci_dev_put(sd_dev);
403 dev_info(&chip->pdev->dev, "Refusing to bind to "
404 "secondary interface.\n");
405 return -ENODEV;
406 }
407 }
408
45211e21
PO		 409 /*
410 * JMicron chips need a bit of a nudge to enable the power
411 * output pins.
412 */
413 ret = jmicron_pmos(chip, 1);
414 if (ret) {
415 dev_err(&chip->pdev->dev, "Failure enabling card power\n");
416 return ret;
417 }
418
82b0e23a
TI		 419 /* quirk for unsable RO-detection on JM388 chips */
420 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD ||
421 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD)
422 chip->quirks |= SDHCI_QUIRK_UNSTABLE_RO_DETECT;
423
45211e21
PO		 424 return 0;
425}
426
4489428a
PO		 427static void jmicron_enable_mmc(struct sdhci_host *host, int on)
428{
429 u8 scratch;
430
431 scratch = readb(host->ioaddr + 0xC0);
432
433 if (on)
434 scratch |= 0x01;
435 else
436 scratch &= ~0x01;
437
438 writeb(scratch, host->ioaddr + 0xC0);
439}
440
441static int jmicron_probe_slot(struct sdhci_pci_slot *slot)
442{
2134a922
PO		 443 if (slot->chip->pdev->revision == 0) {
444 u16 version;
445
446 version = readl(slot->host->ioaddr + SDHCI_HOST_VERSION);
447 version = (version & SDHCI_VENDOR_VER_MASK) >>
448 SDHCI_VENDOR_VER_SHIFT;
449
450 /*
451 * Older versions of the chip have lots of nasty glitches
452 * in the ADMA engine. It's best just to avoid it
453 * completely.
454 */
455 if (version < 0xAC)
456 slot->host->quirks |= SDHCI_QUIRK_BROKEN_ADMA;
457 }
458
8f230f45
TI		 459 /* JM388 MMC doesn't support 1.8V while SD supports it */
460 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) {
461 slot->host->ocr_avail_sd = MMC_VDD_32_33 | MMC_VDD_33_34 |
462 MMC_VDD_29_30 | MMC_VDD_30_31 |
463 MMC_VDD_165_195; /* allow 1.8V */
464 slot->host->ocr_avail_mmc = MMC_VDD_32_33 | MMC_VDD_33_34 |
465 MMC_VDD_29_30 | MMC_VDD_30_31; /* no 1.8V for MMC */
466 }
467
4489428a
PO		 468 /*
469 * The secondary interface requires a bit set to get the
470 * interrupts.
471 */
8f230f45
TI		 472 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
473 slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD)
4489428a
PO		 474 jmicron_enable_mmc(slot->host, 1);
475
d75c1084
TI		 476 slot->host->mmc->caps |= MMC_CAP_BUS_WIDTH_TEST;
477
4489428a
PO		 478 return 0;
479}
480
1e72859e 481static void jmicron_remove_slot(struct sdhci_pci_slot *slot, int dead)
4489428a 482{
1e72859e
PO		 483 if (dead)
484 return;
485
8f230f45
TI		 486 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
487 slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD)
4489428a
PO		 488 jmicron_enable_mmc(slot->host, 0);
489}
490
29495aa0 491static int jmicron_suspend(struct sdhci_pci_chip *chip)
4489428a
PO		 492{
493 int i;
494
8f230f45
TI		 495 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
496 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) {
b177bc91 497 for (i = 0; i < chip->num_slots; i++)
4489428a
PO		 498 jmicron_enable_mmc(chip->slots[i]->host, 0);
499 }
500
501 return 0;
502}
503
45211e21
PO		 504static int jmicron_resume(struct sdhci_pci_chip *chip)
505{
4489428a
PO		 506 int ret, i;
507
8f230f45
TI		 508 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
509 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) {
b177bc91 510 for (i = 0; i < chip->num_slots; i++)
4489428a
PO		 511 jmicron_enable_mmc(chip->slots[i]->host, 1);
512 }
45211e21
PO		 513
514 ret = jmicron_pmos(chip, 1);
515 if (ret) {
516 dev_err(&chip->pdev->dev, "Failure enabling card power\n");
517 return ret;
518 }
519
520 return 0;
521}
522
26daa1ed 523static const struct sdhci_pci_fixes sdhci_o2 = {
01acf691
AL		 524 .probe = sdhci_pci_o2_probe,
525 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
526 .probe_slot = sdhci_pci_o2_probe_slot,
527 .resume = sdhci_pci_o2_resume,
26daa1ed
JL		 528};
529
22606405 530static const struct sdhci_pci_fixes sdhci_jmicron = {
45211e21
PO		 531 .probe = jmicron_probe,
532
4489428a
PO		 533 .probe_slot = jmicron_probe_slot,
534 .remove_slot = jmicron_remove_slot,
535
536 .suspend = jmicron_suspend,
45211e21 537 .resume = jmicron_resume,
22606405
PO		 538};
539
a7a6186c
NP		 540/* SysKonnect CardBus2SDIO extra registers */
541#define SYSKT_CTRL 0x200
542#define SYSKT_RDFIFO_STAT 0x204
543#define SYSKT_WRFIFO_STAT 0x208
544#define SYSKT_POWER_DATA 0x20c
545#define SYSKT_POWER_330 0xef
546#define SYSKT_POWER_300 0xf8
547#define SYSKT_POWER_184 0xcc
548#define SYSKT_POWER_CMD 0x20d
549#define SYSKT_POWER_START (1 << 7)
550#define SYSKT_POWER_STATUS 0x20e
551#define SYSKT_POWER_STATUS_OK (1 << 0)
552#define SYSKT_BOARD_REV 0x210
553#define SYSKT_CHIP_REV 0x211
554#define SYSKT_CONF_DATA 0x212
555#define SYSKT_CONF_DATA_1V8 (1 << 2)
556#define SYSKT_CONF_DATA_2V5 (1 << 1)
557#define SYSKT_CONF_DATA_3V3 (1 << 0)
558
559static int syskt_probe(struct sdhci_pci_chip *chip)
560{
561 if ((chip->pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) {
562 chip->pdev->class &= ~0x0000FF;
563 chip->pdev->class |= PCI_SDHCI_IFDMA;
564 }
565 return 0;
566}
567
568static int syskt_probe_slot(struct sdhci_pci_slot *slot)
569{
570 int tm, ps;
571
572 u8 board_rev = readb(slot->host->ioaddr + SYSKT_BOARD_REV);
573 u8 chip_rev = readb(slot->host->ioaddr + SYSKT_CHIP_REV);
574 dev_info(&slot->chip->pdev->dev, "SysKonnect CardBus2SDIO, "
575 "board rev %d.%d, chip rev %d.%d\n",
576 board_rev >> 4, board_rev & 0xf,
577 chip_rev >> 4, chip_rev & 0xf);
578 if (chip_rev >= 0x20)
579 slot->host->quirks |= SDHCI_QUIRK_FORCE_DMA;
580
581 writeb(SYSKT_POWER_330, slot->host->ioaddr + SYSKT_POWER_DATA);
582 writeb(SYSKT_POWER_START, slot->host->ioaddr + SYSKT_POWER_CMD);
583 udelay(50);
584 tm = 10; /* Wait max 1 ms */
585 do {
586 ps = readw(slot->host->ioaddr + SYSKT_POWER_STATUS);
587 if (ps & SYSKT_POWER_STATUS_OK)
588 break;
589 udelay(100);
590 } while (--tm);
591 if (!tm) {
592 dev_err(&slot->chip->pdev->dev,
593 "power regulator never stabilized");
594 writeb(0, slot->host->ioaddr + SYSKT_POWER_CMD);
595 return -ENODEV;
596 }
597
598 return 0;
599}
600
601static const struct sdhci_pci_fixes sdhci_syskt = {
602 .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER,
603 .probe = syskt_probe,
604 .probe_slot = syskt_probe_slot,
605};
606
557b0697
HW		 607static int via_probe(struct sdhci_pci_chip *chip)
608{
609 if (chip->pdev->revision == 0x10)
610 chip->quirks |= SDHCI_QUIRK_DELAY_AFTER_POWER;
611
612 return 0;
613}
614
615static const struct sdhci_pci_fixes sdhci_via = {
616 .probe = via_probe,
617};
618
9107ebbf
MC		 619static int rtsx_probe_slot(struct sdhci_pci_slot *slot)
620{
621 slot->host->mmc->caps2 |= MMC_CAP2_HS200;
622 return 0;
623}
624
625static const struct sdhci_pci_fixes sdhci_rtsx = {
626 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
627 SDHCI_QUIRK2_BROKEN_DDR50,
628 .probe_slot = rtsx_probe_slot,
629};
630
9647f84d 631static const struct pci_device_id pci_ids[] = {
b8c86fc5
PO		 632 {
633 .vendor = PCI_VENDOR_ID_RICOH,
634 .device = PCI_DEVICE_ID_RICOH_R5C822,
22606405 635 .subvendor = PCI_ANY_ID,
b8c86fc5 636 .subdevice = PCI_ANY_ID,
22606405 637 .driver_data = (kernel_ulong_t)&sdhci_ricoh,
b8c86fc5
PO		 638 },
639
ccc92c23
ML		 640 {
641 .vendor = PCI_VENDOR_ID_RICOH,
642 .device = 0x843,
643 .subvendor = PCI_ANY_ID,
644 .subdevice = PCI_ANY_ID,
645 .driver_data = (kernel_ulong_t)&sdhci_ricoh_mmc,
646 },
647
568133eb
PC		 648 {
649 .vendor = PCI_VENDOR_ID_RICOH,
650 .device = 0xe822,
651 .subvendor = PCI_ANY_ID,
652 .subdevice = PCI_ANY_ID,
653 .driver_data = (kernel_ulong_t)&sdhci_ricoh_mmc,
654 },
655
5fd11c07
MI		 656 {
657 .vendor = PCI_VENDOR_ID_RICOH,
658 .device = 0xe823,
659 .subvendor = PCI_ANY_ID,
660 .subdevice = PCI_ANY_ID,
661 .driver_data = (kernel_ulong_t)&sdhci_ricoh_mmc,
662 },
663
b8c86fc5
PO		 664 {
665 .vendor = PCI_VENDOR_ID_ENE,
666 .device = PCI_DEVICE_ID_ENE_CB712_SD,
667 .subvendor = PCI_ANY_ID,
668 .subdevice = PCI_ANY_ID,
22606405 669 .driver_data = (kernel_ulong_t)&sdhci_ene_712,
b8c86fc5
PO		 670 },
671
672 {
673 .vendor = PCI_VENDOR_ID_ENE,
674 .device = PCI_DEVICE_ID_ENE_CB712_SD_2,
675 .subvendor = PCI_ANY_ID,
676 .subdevice = PCI_ANY_ID,
22606405 677 .driver_data = (kernel_ulong_t)&sdhci_ene_712,
b8c86fc5
PO		 678 },
679
680 {
681 .vendor = PCI_VENDOR_ID_ENE,
682 .device = PCI_DEVICE_ID_ENE_CB714_SD,
683 .subvendor = PCI_ANY_ID,
684 .subdevice = PCI_ANY_ID,
22606405 685 .driver_data = (kernel_ulong_t)&sdhci_ene_714,
b8c86fc5
PO		 686 },
687
688 {
689 .vendor = PCI_VENDOR_ID_ENE,
690 .device = PCI_DEVICE_ID_ENE_CB714_SD_2,
691 .subvendor = PCI_ANY_ID,
692 .subdevice = PCI_ANY_ID,
22606405 693 .driver_data = (kernel_ulong_t)&sdhci_ene_714,
b8c86fc5
PO		 694 },
695
696 {
697 .vendor = PCI_VENDOR_ID_MARVELL,
8c5eb880 698 .device = PCI_DEVICE_ID_MARVELL_88ALP01_SD,
b8c86fc5
PO		 699 .subvendor = PCI_ANY_ID,
700 .subdevice = PCI_ANY_ID,
22606405 701 .driver_data = (kernel_ulong_t)&sdhci_cafe,
b8c86fc5
PO		 702 },
703
704 {
705 .vendor = PCI_VENDOR_ID_JMICRON,
706 .device = PCI_DEVICE_ID_JMICRON_JMB38X_SD,
707 .subvendor = PCI_ANY_ID,
708 .subdevice = PCI_ANY_ID,
22606405 709 .driver_data = (kernel_ulong_t)&sdhci_jmicron,
b8c86fc5
PO		 710 },
711
4489428a
PO		 712 {
713 .vendor = PCI_VENDOR_ID_JMICRON,
714 .device = PCI_DEVICE_ID_JMICRON_JMB38X_MMC,
715 .subvendor = PCI_ANY_ID,
716 .subdevice = PCI_ANY_ID,
717 .driver_data = (kernel_ulong_t)&sdhci_jmicron,
8f230f45
TI		 718 },
719
720 {
721 .vendor = PCI_VENDOR_ID_JMICRON,
722 .device = PCI_DEVICE_ID_JMICRON_JMB388_SD,
723 .subvendor = PCI_ANY_ID,
724 .subdevice = PCI_ANY_ID,
725 .driver_data = (kernel_ulong_t)&sdhci_jmicron,
726 },
727
728 {
729 .vendor = PCI_VENDOR_ID_JMICRON,
730 .device = PCI_DEVICE_ID_JMICRON_JMB388_ESD,
731 .subvendor = PCI_ANY_ID,
732 .subdevice = PCI_ANY_ID,
733 .driver_data = (kernel_ulong_t)&sdhci_jmicron,
4489428a
PO		 734 },
735
a7a6186c
NP		 736 {
737 .vendor = PCI_VENDOR_ID_SYSKONNECT,
738 .device = 0x8000,
739 .subvendor = PCI_ANY_ID,
740 .subdevice = PCI_ANY_ID,
741 .driver_data = (kernel_ulong_t)&sdhci_syskt,
742 },
743
557b0697
HW		 744 {
745 .vendor = PCI_VENDOR_ID_VIA,
746 .device = 0x95d0,
747 .subvendor = PCI_ANY_ID,
748 .subdevice = PCI_ANY_ID,
749 .driver_data = (kernel_ulong_t)&sdhci_via,
9107ebbf
MC		 750 },
751
752 {
753 .vendor = PCI_VENDOR_ID_REALTEK,
754 .device = 0x5250,
755 .subvendor = PCI_ANY_ID,
756 .subdevice = PCI_ANY_ID,
757 .driver_data = (kernel_ulong_t)&sdhci_rtsx,
557b0697
HW		 758 },
759
43e968ce
DB		 760 {
761 .vendor = PCI_VENDOR_ID_INTEL,
762 .device = PCI_DEVICE_ID_INTEL_QRK_SD,
763 .subvendor = PCI_ANY_ID,
764 .subdevice = PCI_ANY_ID,
765 .driver_data = (kernel_ulong_t)&sdhci_intel_qrk,
766 },
767
29229052
XS		 768 {
769 .vendor = PCI_VENDOR_ID_INTEL,
f9ee3eab
AC		 770 .device = PCI_DEVICE_ID_INTEL_MRST_SD0,
771 .subvendor = PCI_ANY_ID,
772 .subdevice = PCI_ANY_ID,
773 .driver_data = (kernel_ulong_t)&sdhci_intel_mrst_hc0,
774 },
775
776 {
777 .vendor = PCI_VENDOR_ID_INTEL,
778 .device = PCI_DEVICE_ID_INTEL_MRST_SD1,
779 .subvendor = PCI_ANY_ID,
780 .subdevice = PCI_ANY_ID,
35ac6f08
JP		 781 .driver_data = (kernel_ulong_t)&sdhci_intel_mrst_hc1_hc2,
782 },
783
784 {
785 .vendor = PCI_VENDOR_ID_INTEL,
786 .device = PCI_DEVICE_ID_INTEL_MRST_SD2,
787 .subvendor = PCI_ANY_ID,
788 .subdevice = PCI_ANY_ID,
789 .driver_data = (kernel_ulong_t)&sdhci_intel_mrst_hc1_hc2,
f9ee3eab
AC		 790 },
791
792 {
793 .vendor = PCI_VENDOR_ID_INTEL,
29229052
XS		 794 .device = PCI_DEVICE_ID_INTEL_MFD_SD,
795 .subvendor = PCI_ANY_ID,
796 .subdevice = PCI_ANY_ID,
797 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sd,
798 },
799
800 {
801 .vendor = PCI_VENDOR_ID_INTEL,
802 .device = PCI_DEVICE_ID_INTEL_MFD_SDIO1,
803 .subvendor = PCI_ANY_ID,
804 .subdevice = PCI_ANY_ID,
0d013bcf 805 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sdio,
29229052
XS		 806 },
807
808 {
809 .vendor = PCI_VENDOR_ID_INTEL,
810 .device = PCI_DEVICE_ID_INTEL_MFD_SDIO2,
811 .subvendor = PCI_ANY_ID,
812 .subdevice = PCI_ANY_ID,
0d013bcf 813 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sdio,
29229052
XS		 814 },
815
816 {
817 .vendor = PCI_VENDOR_ID_INTEL,
818 .device = PCI_DEVICE_ID_INTEL_MFD_EMMC0,
819 .subvendor = PCI_ANY_ID,
820 .subdevice = PCI_ANY_ID,
0d013bcf 821 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc,
29229052
XS		 822 },
823
824 {
825 .vendor = PCI_VENDOR_ID_INTEL,
826 .device = PCI_DEVICE_ID_INTEL_MFD_EMMC1,
827 .subvendor = PCI_ANY_ID,
828 .subdevice = PCI_ANY_ID,
0d013bcf 829 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc,
29229052
XS		 830 },
831
296e0b03
AS		 832 {
833 .vendor = PCI_VENDOR_ID_INTEL,
834 .device = PCI_DEVICE_ID_INTEL_PCH_SDIO0,
835 .subvendor = PCI_ANY_ID,
836 .subdevice = PCI_ANY_ID,
837 .driver_data = (kernel_ulong_t)&sdhci_intel_pch_sdio,
838 },
839
840 {
841 .vendor = PCI_VENDOR_ID_INTEL,
842 .device = PCI_DEVICE_ID_INTEL_PCH_SDIO1,
843 .subvendor = PCI_ANY_ID,
844 .subdevice = PCI_ANY_ID,
845 .driver_data = (kernel_ulong_t)&sdhci_intel_pch_sdio,
846 },
847
728ef3d1
AH		 848 {
849 .vendor = PCI_VENDOR_ID_INTEL,
850 .device = PCI_DEVICE_ID_INTEL_BYT_EMMC,
851 .subvendor = PCI_ANY_ID,
852 .subdevice = PCI_ANY_ID,
853 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc,
854 },
855
856 {
857 .vendor = PCI_VENDOR_ID_INTEL,
858 .device = PCI_DEVICE_ID_INTEL_BYT_SDIO,
859 .subvendor = PCI_ANY_ID,
860 .subdevice = PCI_ANY_ID,
861 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio,
862 },
863
864 {
865 .vendor = PCI_VENDOR_ID_INTEL,
866 .device = PCI_DEVICE_ID_INTEL_BYT_SD,
867 .subvendor = PCI_ANY_ID,
868 .subdevice = PCI_ANY_ID,
869 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd,
870 },
871
30d025c0
AH		 872 {
873 .vendor = PCI_VENDOR_ID_INTEL,
874 .device = PCI_DEVICE_ID_INTEL_BYT_EMMC2,
875 .subvendor = PCI_ANY_ID,
876 .subdevice = PCI_ANY_ID,
877 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc,
878 },
879
066173b6
AC		 880 {
881 .vendor = PCI_VENDOR_ID_INTEL,
882 .device = PCI_DEVICE_ID_INTEL_BSW_EMMC,
883 .subvendor = PCI_ANY_ID,
884 .subdevice = PCI_ANY_ID,
885 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc,
886 },
887
888 {
889 .vendor = PCI_VENDOR_ID_INTEL,
890 .device = PCI_DEVICE_ID_INTEL_BSW_SDIO,
891 .subvendor = PCI_ANY_ID,
892 .subdevice = PCI_ANY_ID,
893 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio,
894 },
895
896 {
897 .vendor = PCI_VENDOR_ID_INTEL,
898 .device = PCI_DEVICE_ID_INTEL_BSW_SD,
899 .subvendor = PCI_ANY_ID,
900 .subdevice = PCI_ANY_ID,
901 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd,
902 },
d052068a
EE		 903
904 {
905 .vendor = PCI_VENDOR_ID_INTEL,
906 .device = PCI_DEVICE_ID_INTEL_CLV_SDIO0,
907 .subvendor = PCI_ANY_ID,
908 .subdevice = PCI_ANY_ID,
909 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sd,
910 },
911
912 {
913 .vendor = PCI_VENDOR_ID_INTEL,
914 .device = PCI_DEVICE_ID_INTEL_CLV_SDIO1,
915 .subvendor = PCI_ANY_ID,
916 .subdevice = PCI_ANY_ID,
917 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sdio,
918 },
919
920 {
921 .vendor = PCI_VENDOR_ID_INTEL,
922 .device = PCI_DEVICE_ID_INTEL_CLV_SDIO2,
923 .subvendor = PCI_ANY_ID,
924 .subdevice = PCI_ANY_ID,
925 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sdio,
926 },
927
928 {
929 .vendor = PCI_VENDOR_ID_INTEL,
930 .device = PCI_DEVICE_ID_INTEL_CLV_EMMC0,
931 .subvendor = PCI_ANY_ID,
932 .subdevice = PCI_ANY_ID,
933 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc,
934 },
935
936 {
937 .vendor = PCI_VENDOR_ID_INTEL,
938 .device = PCI_DEVICE_ID_INTEL_CLV_EMMC1,
939 .subvendor = PCI_ANY_ID,
940 .subdevice = PCI_ANY_ID,
941 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc,
942 },
943
8776a165
DC		 944 {
945 .vendor = PCI_VENDOR_ID_INTEL,
946 .device = PCI_DEVICE_ID_INTEL_MRFL_MMC,
947 .subvendor = PCI_ANY_ID,
948 .subdevice = PCI_ANY_ID,
949 .driver_data = (kernel_ulong_t)&sdhci_intel_mrfl_mmc,
950 },
26daa1ed
JL		 951 {
952 .vendor = PCI_VENDOR_ID_O2,
953 .device = PCI_DEVICE_ID_O2_8120,
954 .subvendor = PCI_ANY_ID,
955 .subdevice = PCI_ANY_ID,
956 .driver_data = (kernel_ulong_t)&sdhci_o2,
957 },
958
959 {
960 .vendor = PCI_VENDOR_ID_O2,
961 .device = PCI_DEVICE_ID_O2_8220,
962 .subvendor = PCI_ANY_ID,
963 .subdevice = PCI_ANY_ID,
964 .driver_data = (kernel_ulong_t)&sdhci_o2,
965 },
966
967 {
968 .vendor = PCI_VENDOR_ID_O2,
969 .device = PCI_DEVICE_ID_O2_8221,
970 .subvendor = PCI_ANY_ID,
971 .subdevice = PCI_ANY_ID,
972 .driver_data = (kernel_ulong_t)&sdhci_o2,
973 },
974
975 {
976 .vendor = PCI_VENDOR_ID_O2,
977 .device = PCI_DEVICE_ID_O2_8320,
978 .subvendor = PCI_ANY_ID,
979 .subdevice = PCI_ANY_ID,
980 .driver_data = (kernel_ulong_t)&sdhci_o2,
981 },
982
983 {
984 .vendor = PCI_VENDOR_ID_O2,
985 .device = PCI_DEVICE_ID_O2_8321,
986 .subvendor = PCI_ANY_ID,
987 .subdevice = PCI_ANY_ID,
988 .driver_data = (kernel_ulong_t)&sdhci_o2,
989 },
990
01acf691
AL		 991 {
992 .vendor = PCI_VENDOR_ID_O2,
993 .device = PCI_DEVICE_ID_O2_FUJIN2,
994 .subvendor = PCI_ANY_ID,
995 .subdevice = PCI_ANY_ID,
996 .driver_data = (kernel_ulong_t)&sdhci_o2,
997 },
998
999 {
1000 .vendor = PCI_VENDOR_ID_O2,
1001 .device = PCI_DEVICE_ID_O2_SDS0,
1002 .subvendor = PCI_ANY_ID,
1003 .subdevice = PCI_ANY_ID,
1004 .driver_data = (kernel_ulong_t)&sdhci_o2,
1005 },
1006
1007 {
1008 .vendor = PCI_VENDOR_ID_O2,
1009 .device = PCI_DEVICE_ID_O2_SDS1,
1010 .subvendor = PCI_ANY_ID,
1011 .subdevice = PCI_ANY_ID,
1012 .driver_data = (kernel_ulong_t)&sdhci_o2,
1013 },
1014
1015 {
1016 .vendor = PCI_VENDOR_ID_O2,
1017 .device = PCI_DEVICE_ID_O2_SEABIRD0,
1018 .subvendor = PCI_ANY_ID,
1019 .subdevice = PCI_ANY_ID,
1020 .driver_data = (kernel_ulong_t)&sdhci_o2,
1021 },
1022
1023 {
1024 .vendor = PCI_VENDOR_ID_O2,
1025 .device = PCI_DEVICE_ID_O2_SEABIRD1,
1026 .subvendor = PCI_ANY_ID,
1027 .subdevice = PCI_ANY_ID,
1028 .driver_data = (kernel_ulong_t)&sdhci_o2,
1029 },
1030
b8c86fc5
PO		 1031 { /* Generic SD host controller */
1032 PCI_DEVICE_CLASS((PCI_CLASS_SYSTEM_SDHCI << 8), 0xFFFF00)
1033 },
1034
1035 { /* end: all zeroes */ },
1036};
1037
1038MODULE_DEVICE_TABLE(pci, pci_ids);
1039
b8c86fc5
PO		 1040/*****************************************************************************\
1041 * *
1042 * SDHCI core callbacks *
1043 * *
1044\*****************************************************************************/
1045
1046static int sdhci_pci_enable_dma(struct sdhci_host *host)
1047{
1048 struct sdhci_pci_slot *slot;
1049 struct pci_dev *pdev;
1050 int ret;
1051
1052 slot = sdhci_priv(host);
1053 pdev = slot->chip->pdev;
1054
1055 if (((pdev->class & 0xFFFF00) == (PCI_CLASS_SYSTEM_SDHCI << 8)) &&
1056 ((pdev->class & 0x0000FF) != PCI_SDHCI_IFDMA) &&
a13abc7b 1057 (host->flags & SDHCI_USE_SDMA)) {
b8c86fc5
PO		 1058 dev_warn(&pdev->dev, "Will use DMA mode even though HW "
1059 "doesn't fully claim to support it.\n");
1060 }
1061
284901a9 1062 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
b8c86fc5
PO		 1063 if (ret)
1064 return ret;
1065
1066 pci_set_master(pdev);
1067
1068 return 0;
1069}
1070
2317f56c 1071static void sdhci_pci_set_bus_width(struct sdhci_host *host, int width)
68077b02
ML		 1072{
1073 u8 ctrl;
1074
1075 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1076
1077 switch (width) {
1078 case MMC_BUS_WIDTH_8:
1079 ctrl |= SDHCI_CTRL_8BITBUS;
1080 ctrl &= ~SDHCI_CTRL_4BITBUS;
1081 break;
1082 case MMC_BUS_WIDTH_4:
1083 ctrl |= SDHCI_CTRL_4BITBUS;
1084 ctrl &= ~SDHCI_CTRL_8BITBUS;
1085 break;
1086 default:
1087 ctrl &= ~(SDHCI_CTRL_8BITBUS | SDHCI_CTRL_4BITBUS);
1088 break;
1089 }
1090
1091 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
68077b02
ML		 1092}
1093
c9faff6c 1094static void sdhci_pci_gpio_hw_reset(struct sdhci_host *host)
0f201655
AH		 1095{
1096 struct sdhci_pci_slot *slot = sdhci_priv(host);
1097 int rst_n_gpio = slot->rst_n_gpio;
1098
1099 if (!gpio_is_valid(rst_n_gpio))
1100 return;
1101 gpio_set_value_cansleep(rst_n_gpio, 0);
1102 /* For eMMC, minimum is 1us but give it 10us for good measure */
1103 udelay(10);
1104 gpio_set_value_cansleep(rst_n_gpio, 1);
1105 /* For eMMC, minimum is 200us but give it 300us for good measure */
1106 usleep_range(300, 1000);
1107}
1108
c9faff6c
AH		 1109static void sdhci_pci_hw_reset(struct sdhci_host *host)
1110{
1111 struct sdhci_pci_slot *slot = sdhci_priv(host);
1112
1113 if (slot->hw_reset)
1114 slot->hw_reset(host);
1115}
1116
c915568d 1117static const struct sdhci_ops sdhci_pci_ops = {
1771059c 1118 .set_clock = sdhci_set_clock,
b8c86fc5 1119 .enable_dma = sdhci_pci_enable_dma,
2317f56c 1120 .set_bus_width = sdhci_pci_set_bus_width,
03231f9b 1121 .reset = sdhci_reset,
96d7b78c 1122 .set_uhs_signaling = sdhci_set_uhs_signaling,
0f201655 1123 .hw_reset = sdhci_pci_hw_reset,
b8c86fc5
PO		 1124};
1125
1126/*****************************************************************************\
1127 * *
1128 * Suspend/resume *
1129 * *
1130\*****************************************************************************/
1131
1132#ifdef CONFIG_PM
1133
29495aa0 1134static int sdhci_pci_suspend(struct device *dev)
b8c86fc5 1135{
29495aa0 1136 struct pci_dev *pdev = to_pci_dev(dev);
b8c86fc5
PO		 1137 struct sdhci_pci_chip *chip;
1138 struct sdhci_pci_slot *slot;
5f619704 1139 mmc_pm_flag_t slot_pm_flags;
2f4cbb3d 1140 mmc_pm_flag_t pm_flags = 0;
b8c86fc5
PO		 1141 int i, ret;
1142
1143 chip = pci_get_drvdata(pdev);
1144 if (!chip)
1145 return 0;
1146
b177bc91 1147 for (i = 0; i < chip->num_slots; i++) {
b8c86fc5
PO		 1148 slot = chip->slots[i];
1149 if (!slot)
1150 continue;
1151
29495aa0 1152 ret = sdhci_suspend_host(slot->host);
b8c86fc5 1153
b678b91f
AL		 1154 if (ret)
1155 goto err_pci_suspend;
2f4cbb3d 1156
5f619704
DD		 1157 slot_pm_flags = slot->host->mmc->pm_flags;
1158 if (slot_pm_flags & MMC_PM_WAKE_SDIO_IRQ)
1159 sdhci_enable_irq_wakeups(slot->host);
1160
1161 pm_flags |= slot_pm_flags;
b8c86fc5
PO		 1162 }
1163
4489428a 1164 if (chip->fixes && chip->fixes->suspend) {
29495aa0 1165 ret = chip->fixes->suspend(chip);
b678b91f
AL		 1166 if (ret)
1167 goto err_pci_suspend;
4489428a
PO		 1168 }
1169
2f4cbb3d 1170 if (pm_flags & MMC_PM_KEEP_POWER) {
6b91f2d4
CD		 1171 if (pm_flags & MMC_PM_WAKE_SDIO_IRQ)
1172 device_init_wakeup(dev, true);
1173 else
1174 device_init_wakeup(dev, false);
1175 } else
1176 device_init_wakeup(dev, false);
b8c86fc5
PO		 1177
1178 return 0;
b678b91f
AL		 1179
1180err_pci_suspend:
1181 while (--i >= 0)
1182 sdhci_resume_host(chip->slots[i]->host);
1183 return ret;
b8c86fc5
PO		 1184}
1185
29495aa0 1186static int sdhci_pci_resume(struct device *dev)
b8c86fc5 1187{
29495aa0 1188 struct pci_dev *pdev = to_pci_dev(dev);
b8c86fc5
PO		 1189 struct sdhci_pci_chip *chip;
1190 struct sdhci_pci_slot *slot;
1191 int i, ret;
1192
1193 chip = pci_get_drvdata(pdev);
1194 if (!chip)
1195 return 0;
1196
45211e21
PO		 1197 if (chip->fixes && chip->fixes->resume) {
1198 ret = chip->fixes->resume(chip);
1199 if (ret)
1200 return ret;
1201 }
1202
b177bc91 1203 for (i = 0; i < chip->num_slots; i++) {
b8c86fc5
PO		 1204 slot = chip->slots[i];
1205 if (!slot)
1206 continue;
1207
1208 ret = sdhci_resume_host(slot->host);
1209 if (ret)
1210 return ret;
1211 }
1212
1213 return 0;
1214}
1215
1216#else /* CONFIG_PM */
1217
1218#define sdhci_pci_suspend NULL
1219#define sdhci_pci_resume NULL
1220
1221#endif /* CONFIG_PM */
1222
66fd8ad5
AH		 1223#ifdef CONFIG_PM_RUNTIME
1224
1225static int sdhci_pci_runtime_suspend(struct device *dev)
1226{
1227 struct pci_dev *pdev = container_of(dev, struct pci_dev, dev);
1228 struct sdhci_pci_chip *chip;
1229 struct sdhci_pci_slot *slot;
66fd8ad5
AH		 1230 int i, ret;
1231
1232 chip = pci_get_drvdata(pdev);
1233 if (!chip)
1234 return 0;
1235
1236 for (i = 0; i < chip->num_slots; i++) {
1237 slot = chip->slots[i];
1238 if (!slot)
1239 continue;
1240
1241 ret = sdhci_runtime_suspend_host(slot->host);
1242
b678b91f
AL		 1243 if (ret)
1244 goto err_pci_runtime_suspend;
66fd8ad5
AH		 1245 }
1246
1247 if (chip->fixes && chip->fixes->suspend) {
29495aa0 1248 ret = chip->fixes->suspend(chip);
b678b91f
AL		 1249 if (ret)
1250 goto err_pci_runtime_suspend;
66fd8ad5
AH		 1251 }
1252
1253 return 0;
b678b91f
AL		 1254
1255err_pci_runtime_suspend:
1256 while (--i >= 0)
1257 sdhci_runtime_resume_host(chip->slots[i]->host);
1258 return ret;
66fd8ad5
AH		 1259}
1260
1261static int sdhci_pci_runtime_resume(struct device *dev)
1262{
1263 struct pci_dev *pdev = container_of(dev, struct pci_dev, dev);
1264 struct sdhci_pci_chip *chip;
1265 struct sdhci_pci_slot *slot;
1266 int i, ret;
1267
1268 chip = pci_get_drvdata(pdev);
1269 if (!chip)
1270 return 0;
1271
1272 if (chip->fixes && chip->fixes->resume) {
1273 ret = chip->fixes->resume(chip);
1274 if (ret)
1275 return ret;
1276 }
1277
1278 for (i = 0; i < chip->num_slots; i++) {
1279 slot = chip->slots[i];
1280 if (!slot)
1281 continue;
1282
1283 ret = sdhci_runtime_resume_host(slot->host);
1284 if (ret)
1285 return ret;
1286 }
1287
1288 return 0;
1289}
1290
1291static int sdhci_pci_runtime_idle(struct device *dev)
1292{
1293 return 0;
1294}
1295
66fd8ad5
AH		 1296#endif
1297
1298static const struct dev_pm_ops sdhci_pci_pm_ops = {
29495aa0
ML		 1299 .suspend = sdhci_pci_suspend,
1300 .resume = sdhci_pci_resume,
f3a92b1a
PG		 1301 SET_RUNTIME_PM_OPS(sdhci_pci_runtime_suspend,
1302 sdhci_pci_runtime_resume, sdhci_pci_runtime_idle)
66fd8ad5
AH		 1303};
1304
b8c86fc5
PO		 1305/*****************************************************************************\
1306 * *
1307 * Device probing/removal *
1308 * *
1309\*****************************************************************************/
1310
c3be1efd 1311static struct sdhci_pci_slot *sdhci_pci_probe_slot(
52c506f0
AH		 1312 struct pci_dev *pdev, struct sdhci_pci_chip *chip, int first_bar,
1313 int slotno)
b8c86fc5
PO		 1314{
1315 struct sdhci_pci_slot *slot;
1316 struct sdhci_host *host;
52c506f0 1317 int ret, bar = first_bar + slotno;
b8c86fc5
PO		 1318
1319 if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) {
1320 dev_err(&pdev->dev, "BAR %d is not iomem. Aborting.\n", bar);
1321 return ERR_PTR(-ENODEV);
1322 }
1323
90b3e6c5 1324 if (pci_resource_len(pdev, bar) < 0x100) {
b8c86fc5
PO		 1325 dev_err(&pdev->dev, "Invalid iomem size. You may "
1326 "experience problems.\n");
1327 }
1328
1329 if ((pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) {
1330 dev_err(&pdev->dev, "Vendor specific interface. Aborting.\n");
1331 return ERR_PTR(-ENODEV);
1332 }
1333
1334 if ((pdev->class & 0x0000FF) > PCI_SDHCI_IFVENDOR) {
1335 dev_err(&pdev->dev, "Unknown interface. Aborting.\n");
1336 return ERR_PTR(-ENODEV);
1337 }
1338
1339 host = sdhci_alloc_host(&pdev->dev, sizeof(struct sdhci_pci_slot));
1340 if (IS_ERR(host)) {
c60a32cd 1341 dev_err(&pdev->dev, "cannot allocate host\n");
dc0fd7b5 1342 return ERR_CAST(host);
b8c86fc5
PO		 1343 }
1344
1345 slot = sdhci_priv(host);
1346
1347 slot->chip = chip;
1348 slot->host = host;
1349 slot->pci_bar = bar;
0f201655 1350 slot->rst_n_gpio = -EINVAL;
c5e027a4 1351 slot->cd_gpio = -EINVAL;
b8c86fc5 1352
52c506f0
AH		 1353 /* Retrieve platform data if there is any */
1354 if (*sdhci_pci_get_data)
1355 slot->data = sdhci_pci_get_data(pdev, slotno);
1356
1357 if (slot->data) {
1358 if (slot->data->setup) {
1359 ret = slot->data->setup(slot->data);
1360 if (ret) {
1361 dev_err(&pdev->dev, "platform setup failed\n");
1362 goto free;
1363 }
1364 }
c5e027a4
AH		 1365 slot->rst_n_gpio = slot->data->rst_n_gpio;
1366 slot->cd_gpio = slot->data->cd_gpio;
52c506f0
AH		 1367 }
1368
b8c86fc5
PO		 1369 host->hw_name = "PCI";
1370 host->ops = &sdhci_pci_ops;
1371 host->quirks = chip->quirks;
f3c55a7b 1372 host->quirks2 = chip->quirks2;
b8c86fc5
PO		 1373
1374 host->irq = pdev->irq;
1375
1376 ret = pci_request_region(pdev, bar, mmc_hostname(host->mmc));
1377 if (ret) {
1378 dev_err(&pdev->dev, "cannot request region\n");
52c506f0 1379 goto cleanup;
b8c86fc5
PO		 1380 }
1381
092f82ed 1382 host->ioaddr = pci_ioremap_bar(pdev, bar);
b8c86fc5
PO		 1383 if (!host->ioaddr) {
1384 dev_err(&pdev->dev, "failed to remap registers\n");
9fdcdbb0 1385 ret = -ENOMEM;
b8c86fc5
PO		 1386 goto release;
1387 }
1388
4489428a
PO		 1389 if (chip->fixes && chip->fixes->probe_slot) {
1390 ret = chip->fixes->probe_slot(slot);
1391 if (ret)
1392 goto unmap;
1393 }
1394
c5e027a4
AH		 1395 if (gpio_is_valid(slot->rst_n_gpio)) {
1396 if (!gpio_request(slot->rst_n_gpio, "eMMC_reset")) {
1397 gpio_direction_output(slot->rst_n_gpio, 1);
1398 slot->host->mmc->caps |= MMC_CAP_HW_RESET;
c9faff6c 1399 slot->hw_reset = sdhci_pci_gpio_hw_reset;
c5e027a4
AH		 1400 } else {
1401 dev_warn(&pdev->dev, "failed to request rst_n_gpio\n");
1402 slot->rst_n_gpio = -EINVAL;
1403 }
1404 }
1405
2f4cbb3d 1406 host->mmc->pm_caps = MMC_PM_KEEP_POWER | MMC_PM_WAKE_SDIO_IRQ;
eed222ac 1407 host->mmc->slotno = slotno;
a08b17be 1408 host->mmc->caps2 |= MMC_CAP2_NO_PRESCAN_POWERUP;
2f4cbb3d 1409
b8c86fc5
PO		 1410 ret = sdhci_add_host(host);
1411 if (ret)
4489428a 1412 goto remove;
b8c86fc5 1413
c5e027a4
AH		 1414 sdhci_pci_add_own_cd(slot);
1415
77a0122e
AH		 1416 /*
1417 * Check if the chip needs a separate GPIO for card detect to wake up
1418 * from runtime suspend. If it is not there, don't allow runtime PM.
1419 * Note sdhci_pci_add_own_cd() sets slot->cd_gpio to -EINVAL on failure.
1420 */
945be38c
AH		 1421 if (chip->fixes && chip->fixes->own_cd_for_runtime_pm &&
1422 !gpio_is_valid(slot->cd_gpio))
77a0122e
AH		 1423 chip->allow_runtime_pm = false;
1424
b8c86fc5
PO		 1425 return slot;
1426
4489428a 1427remove:
c5e027a4
AH		 1428 if (gpio_is_valid(slot->rst_n_gpio))
1429 gpio_free(slot->rst_n_gpio);
1430
4489428a 1431 if (chip->fixes && chip->fixes->remove_slot)
1e72859e 1432 chip->fixes->remove_slot(slot, 0);
4489428a 1433
b8c86fc5
PO		 1434unmap:
1435 iounmap(host->ioaddr);
1436
1437release:
1438 pci_release_region(pdev, bar);
c60a32cd 1439
52c506f0
AH		 1440cleanup:
1441 if (slot->data && slot->data->cleanup)
1442 slot->data->cleanup(slot->data);
1443
c60a32cd 1444free:
b8c86fc5
PO		 1445 sdhci_free_host(host);
1446
1447 return ERR_PTR(ret);
1448}
1449
1450static void sdhci_pci_remove_slot(struct sdhci_pci_slot *slot)
1451{
1e72859e
PO		 1452 int dead;
1453 u32 scratch;
1454
c5e027a4
AH		 1455 sdhci_pci_remove_own_cd(slot);
1456
1e72859e
PO		 1457 dead = 0;
1458 scratch = readl(slot->host->ioaddr + SDHCI_INT_STATUS);
1459 if (scratch == (u32)-1)
1460 dead = 1;
1461
1462 sdhci_remove_host(slot->host, dead);
4489428a 1463
c5e027a4
AH		 1464 if (gpio_is_valid(slot->rst_n_gpio))
1465 gpio_free(slot->rst_n_gpio);
1466
4489428a 1467 if (slot->chip->fixes && slot->chip->fixes->remove_slot)
1e72859e 1468 slot->chip->fixes->remove_slot(slot, dead);
4489428a 1469
52c506f0
AH		 1470 if (slot->data && slot->data->cleanup)
1471 slot->data->cleanup(slot->data);
1472
b8c86fc5 1473 pci_release_region(slot->chip->pdev, slot->pci_bar);
4489428a 1474
b8c86fc5
PO		 1475 sdhci_free_host(slot->host);
1476}
1477
c3be1efd 1478static void sdhci_pci_runtime_pm_allow(struct device *dev)
66fd8ad5
AH		 1479{
1480 pm_runtime_put_noidle(dev);
1481 pm_runtime_allow(dev);
1482 pm_runtime_set_autosuspend_delay(dev, 50);
1483 pm_runtime_use_autosuspend(dev);
1484 pm_suspend_ignore_children(dev, 1);
1485}
1486
6e0ee714 1487static void sdhci_pci_runtime_pm_forbid(struct device *dev)
66fd8ad5
AH		 1488{
1489 pm_runtime_forbid(dev);
1490 pm_runtime_get_noresume(dev);
1491}
1492
c3be1efd 1493static int sdhci_pci_probe(struct pci_dev *pdev,
b8c86fc5
PO		 1494 const struct pci_device_id *ent)
1495{
1496 struct sdhci_pci_chip *chip;
1497 struct sdhci_pci_slot *slot;
1498
cf5e23e1 1499 u8 slots, first_bar;
b8c86fc5
PO		 1500 int ret, i;
1501
1502 BUG_ON(pdev == NULL);
1503 BUG_ON(ent == NULL);
1504
b8c86fc5 1505 dev_info(&pdev->dev, "SDHCI controller found [%04x:%04x] (rev %x)\n",
cf5e23e1 1506 (int)pdev->vendor, (int)pdev->device, (int)pdev->revision);
b8c86fc5
PO		 1507
1508 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &slots);
1509 if (ret)
1510 return ret;
1511
1512 slots = PCI_SLOT_INFO_SLOTS(slots) + 1;
1513 dev_dbg(&pdev->dev, "found %d slot(s)\n", slots);
1514 if (slots == 0)
1515 return -ENODEV;
1516
1517 BUG_ON(slots > MAX_SLOTS);
1518
1519 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &first_bar);
1520 if (ret)
1521 return ret;
1522
1523 first_bar &= PCI_SLOT_INFO_FIRST_BAR_MASK;
1524
1525 if (first_bar > 5) {
1526 dev_err(&pdev->dev, "Invalid first BAR. Aborting.\n");
1527 return -ENODEV;
1528 }
1529
1530 ret = pci_enable_device(pdev);
1531 if (ret)
1532 return ret;
1533
1534 chip = kzalloc(sizeof(struct sdhci_pci_chip), GFP_KERNEL);
1535 if (!chip) {
1536 ret = -ENOMEM;
1537 goto err;
1538 }
1539
1540 chip->pdev = pdev;
b177bc91 1541 chip->fixes = (const struct sdhci_pci_fixes *)ent->driver_data;
c43fd774 1542 if (chip->fixes) {
22606405 1543 chip->quirks = chip->fixes->quirks;
f3c55a7b 1544 chip->quirks2 = chip->fixes->quirks2;
c43fd774
AH		 1545 chip->allow_runtime_pm = chip->fixes->allow_runtime_pm;
1546 }
b8c86fc5
PO		 1547 chip->num_slots = slots;
1548
1549 pci_set_drvdata(pdev, chip);
1550
22606405
PO		 1551 if (chip->fixes && chip->fixes->probe) {
1552 ret = chip->fixes->probe(chip);
1553 if (ret)
1554 goto free;
1555 }
1556
225d85fe
AC		 1557 slots = chip->num_slots; /* Quirk may have changed this */
1558
b177bc91 1559 for (i = 0; i < slots; i++) {
52c506f0 1560 slot = sdhci_pci_probe_slot(pdev, chip, first_bar, i);
b8c86fc5 1561 if (IS_ERR(slot)) {
b177bc91 1562 for (i--; i >= 0; i--)
b8c86fc5
PO		 1563 sdhci_pci_remove_slot(chip->slots[i]);
1564 ret = PTR_ERR(slot);
1565 goto free;
1566 }
1567
1568 chip->slots[i] = slot;
1569 }
1570
c43fd774
AH		 1571 if (chip->allow_runtime_pm)
1572 sdhci_pci_runtime_pm_allow(&pdev->dev);
66fd8ad5 1573
b8c86fc5
PO		 1574 return 0;
1575
1576free:
1577 pci_set_drvdata(pdev, NULL);
1578 kfree(chip);
1579
1580err:
1581 pci_disable_device(pdev);
1582 return ret;
1583}
1584
6e0ee714 1585static void sdhci_pci_remove(struct pci_dev *pdev)
b8c86fc5
PO		 1586{
1587 int i;
1588 struct sdhci_pci_chip *chip;
1589
1590 chip = pci_get_drvdata(pdev);
1591
1592 if (chip) {
c43fd774
AH		 1593 if (chip->allow_runtime_pm)
1594 sdhci_pci_runtime_pm_forbid(&pdev->dev);
1595
b177bc91 1596 for (i = 0; i < chip->num_slots; i++)
b8c86fc5
PO		 1597 sdhci_pci_remove_slot(chip->slots[i]);
1598
1599 pci_set_drvdata(pdev, NULL);
1600 kfree(chip);
1601 }
1602
1603 pci_disable_device(pdev);
1604}
1605
1606static struct pci_driver sdhci_driver = {
b177bc91 1607 .name = "sdhci-pci",
b8c86fc5 1608 .id_table = pci_ids,
b177bc91 1609 .probe = sdhci_pci_probe,
0433c143 1610 .remove = sdhci_pci_remove,
66fd8ad5
AH		 1611 .driver = {
1612 .pm = &sdhci_pci_pm_ops
1613 },
b8c86fc5
PO		 1614};
1615
acc69646 1616module_pci_driver(sdhci_driver);
b8c86fc5 1617
32710e8f 1618MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
b8c86fc5
PO		 1619MODULE_DESCRIPTION("Secure Digital Host Controller Interface PCI driver");
1620MODULE_LICENSE("GPL");
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