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b8c86fc5 PO |
1 | /* linux/drivers/mmc/host/sdhci-pci.c - SDHCI on PCI bus interface |
2 | * | |
3 | * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved. | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License as published by | |
7 | * the Free Software Foundation; either version 2 of the License, or (at | |
8 | * your option) any later version. | |
9 | * | |
10 | * Thanks to the following companies for their support: | |
11 | * | |
12 | * - JMicron (hardware and technical support) | |
13 | */ | |
14 | ||
15 | #include <linux/delay.h> | |
16 | #include <linux/highmem.h> | |
88b47679 | 17 | #include <linux/module.h> |
b8c86fc5 PO |
18 | #include <linux/pci.h> |
19 | #include <linux/dma-mapping.h> | |
5a0e3ad6 | 20 | #include <linux/slab.h> |
ccc92c23 | 21 | #include <linux/device.h> |
b8c86fc5 | 22 | #include <linux/mmc/host.h> |
b177bc91 AP |
23 | #include <linux/scatterlist.h> |
24 | #include <linux/io.h> | |
0f201655 | 25 | #include <linux/gpio.h> |
66fd8ad5 | 26 | #include <linux/pm_runtime.h> |
52c506f0 | 27 | #include <linux/mmc/sdhci-pci-data.h> |
b8c86fc5 PO |
28 | |
29 | #include "sdhci.h" | |
30 | ||
31 | /* | |
32 | * PCI registers | |
33 | */ | |
34 | ||
35 | #define PCI_SDHCI_IFPIO 0x00 | |
36 | #define PCI_SDHCI_IFDMA 0x01 | |
37 | #define PCI_SDHCI_IFVENDOR 0x02 | |
38 | ||
39 | #define PCI_SLOT_INFO 0x40 /* 8 bits */ | |
40 | #define PCI_SLOT_INFO_SLOTS(x) ((x >> 4) & 7) | |
41 | #define PCI_SLOT_INFO_FIRST_BAR_MASK 0x07 | |
42 | ||
43 | #define MAX_SLOTS 8 | |
44 | ||
22606405 | 45 | struct sdhci_pci_chip; |
4489428a | 46 | struct sdhci_pci_slot; |
22606405 PO |
47 | |
48 | struct sdhci_pci_fixes { | |
49 | unsigned int quirks; | |
f3c55a7b | 50 | unsigned int quirks2; |
c43fd774 | 51 | bool allow_runtime_pm; |
22606405 | 52 | |
b177bc91 | 53 | int (*probe) (struct sdhci_pci_chip *); |
45211e21 | 54 | |
b177bc91 AP |
55 | int (*probe_slot) (struct sdhci_pci_slot *); |
56 | void (*remove_slot) (struct sdhci_pci_slot *, int); | |
4489428a | 57 | |
29495aa0 | 58 | int (*suspend) (struct sdhci_pci_chip *); |
b177bc91 | 59 | int (*resume) (struct sdhci_pci_chip *); |
22606405 PO |
60 | }; |
61 | ||
62 | struct sdhci_pci_slot { | |
63 | struct sdhci_pci_chip *chip; | |
64 | struct sdhci_host *host; | |
52c506f0 | 65 | struct sdhci_pci_data *data; |
b8c86fc5 | 66 | |
22606405 | 67 | int pci_bar; |
0f201655 | 68 | int rst_n_gpio; |
66fd8ad5 AH |
69 | int cd_gpio; |
70 | int cd_irq; | |
22606405 PO |
71 | }; |
72 | ||
73 | struct sdhci_pci_chip { | |
74 | struct pci_dev *pdev; | |
75 | ||
76 | unsigned int quirks; | |
f3c55a7b | 77 | unsigned int quirks2; |
c43fd774 | 78 | bool allow_runtime_pm; |
22606405 PO |
79 | const struct sdhci_pci_fixes *fixes; |
80 | ||
81 | int num_slots; /* Slots on controller */ | |
82 | struct sdhci_pci_slot *slots[MAX_SLOTS]; /* Pointers to host slots */ | |
83 | }; | |
84 | ||
85 | ||
86 | /*****************************************************************************\ | |
87 | * * | |
88 | * Hardware specific quirk handling * | |
89 | * * | |
90 | \*****************************************************************************/ | |
91 | ||
92 | static int ricoh_probe(struct sdhci_pci_chip *chip) | |
93 | { | |
c99436fb CB |
94 | if (chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG || |
95 | chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SONY) | |
22606405 | 96 | chip->quirks |= SDHCI_QUIRK_NO_CARD_NO_RESET; |
ccc92c23 ML |
97 | return 0; |
98 | } | |
99 | ||
100 | static int ricoh_mmc_probe_slot(struct sdhci_pci_slot *slot) | |
101 | { | |
102 | slot->host->caps = | |
103 | ((0x21 << SDHCI_TIMEOUT_CLK_SHIFT) | |
104 | & SDHCI_TIMEOUT_CLK_MASK) | | |
22606405 | 105 | |
ccc92c23 ML |
106 | ((0x21 << SDHCI_CLOCK_BASE_SHIFT) |
107 | & SDHCI_CLOCK_BASE_MASK) | | |
108 | ||
109 | SDHCI_TIMEOUT_CLK_UNIT | | |
110 | SDHCI_CAN_VDD_330 | | |
111 | SDHCI_CAN_DO_SDMA; | |
112 | return 0; | |
113 | } | |
114 | ||
115 | static int ricoh_mmc_resume(struct sdhci_pci_chip *chip) | |
116 | { | |
117 | /* Apply a delay to allow controller to settle */ | |
118 | /* Otherwise it becomes confused if card state changed | |
119 | during suspend */ | |
120 | msleep(500); | |
22606405 PO |
121 | return 0; |
122 | } | |
123 | ||
124 | static const struct sdhci_pci_fixes sdhci_ricoh = { | |
125 | .probe = ricoh_probe, | |
84938294 VK |
126 | .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR | |
127 | SDHCI_QUIRK_FORCE_DMA | | |
128 | SDHCI_QUIRK_CLOCK_BEFORE_RESET, | |
22606405 PO |
129 | }; |
130 | ||
ccc92c23 ML |
131 | static const struct sdhci_pci_fixes sdhci_ricoh_mmc = { |
132 | .probe_slot = ricoh_mmc_probe_slot, | |
133 | .resume = ricoh_mmc_resume, | |
134 | .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR | | |
135 | SDHCI_QUIRK_CLOCK_BEFORE_RESET | | |
136 | SDHCI_QUIRK_NO_CARD_NO_RESET | | |
137 | SDHCI_QUIRK_MISSING_CAPS | |
138 | }; | |
139 | ||
22606405 PO |
140 | static const struct sdhci_pci_fixes sdhci_ene_712 = { |
141 | .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE | | |
142 | SDHCI_QUIRK_BROKEN_DMA, | |
143 | }; | |
144 | ||
145 | static const struct sdhci_pci_fixes sdhci_ene_714 = { | |
146 | .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE | | |
147 | SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS | | |
148 | SDHCI_QUIRK_BROKEN_DMA, | |
149 | }; | |
150 | ||
151 | static const struct sdhci_pci_fixes sdhci_cafe = { | |
152 | .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER | | |
a0874897 | 153 | SDHCI_QUIRK_NO_BUSY_IRQ | |
ee53ab5d | 154 | SDHCI_QUIRK_BROKEN_TIMEOUT_VAL, |
22606405 PO |
155 | }; |
156 | ||
68077b02 ML |
157 | static int mrst_hc_probe_slot(struct sdhci_pci_slot *slot) |
158 | { | |
159 | slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA; | |
160 | return 0; | |
161 | } | |
162 | ||
f9ee3eab AC |
163 | /* |
164 | * ADMA operation is disabled for Moorestown platform due to | |
165 | * hardware bugs. | |
166 | */ | |
35ac6f08 | 167 | static int mrst_hc_probe(struct sdhci_pci_chip *chip) |
f9ee3eab AC |
168 | { |
169 | /* | |
35ac6f08 JP |
170 | * slots number is fixed here for MRST as SDIO3/5 are never used and |
171 | * have hardware bugs. | |
f9ee3eab AC |
172 | */ |
173 | chip->num_slots = 1; | |
174 | return 0; | |
175 | } | |
176 | ||
66fd8ad5 AH |
177 | #ifdef CONFIG_PM_RUNTIME |
178 | ||
c5e027a4 | 179 | static irqreturn_t sdhci_pci_sd_cd(int irq, void *dev_id) |
66fd8ad5 AH |
180 | { |
181 | struct sdhci_pci_slot *slot = dev_id; | |
182 | struct sdhci_host *host = slot->host; | |
183 | ||
184 | mmc_detect_change(host->mmc, msecs_to_jiffies(200)); | |
185 | return IRQ_HANDLED; | |
186 | } | |
187 | ||
c5e027a4 | 188 | static void sdhci_pci_add_own_cd(struct sdhci_pci_slot *slot) |
66fd8ad5 | 189 | { |
c5e027a4 | 190 | int err, irq, gpio = slot->cd_gpio; |
66fd8ad5 AH |
191 | |
192 | slot->cd_gpio = -EINVAL; | |
193 | slot->cd_irq = -EINVAL; | |
194 | ||
c5e027a4 AH |
195 | if (!gpio_is_valid(gpio)) |
196 | return; | |
197 | ||
66fd8ad5 AH |
198 | err = gpio_request(gpio, "sd_cd"); |
199 | if (err < 0) | |
200 | goto out; | |
201 | ||
202 | err = gpio_direction_input(gpio); | |
203 | if (err < 0) | |
204 | goto out_free; | |
205 | ||
206 | irq = gpio_to_irq(gpio); | |
207 | if (irq < 0) | |
208 | goto out_free; | |
209 | ||
c5e027a4 | 210 | err = request_irq(irq, sdhci_pci_sd_cd, IRQF_TRIGGER_RISING | |
66fd8ad5 AH |
211 | IRQF_TRIGGER_FALLING, "sd_cd", slot); |
212 | if (err) | |
213 | goto out_free; | |
214 | ||
215 | slot->cd_gpio = gpio; | |
216 | slot->cd_irq = irq; | |
66fd8ad5 | 217 | |
c5e027a4 | 218 | return; |
66fd8ad5 AH |
219 | |
220 | out_free: | |
221 | gpio_free(gpio); | |
222 | out: | |
223 | dev_warn(&slot->chip->pdev->dev, "failed to setup card detect wake up\n"); | |
66fd8ad5 AH |
224 | } |
225 | ||
c5e027a4 | 226 | static void sdhci_pci_remove_own_cd(struct sdhci_pci_slot *slot) |
66fd8ad5 AH |
227 | { |
228 | if (slot->cd_irq >= 0) | |
229 | free_irq(slot->cd_irq, slot); | |
c5e027a4 AH |
230 | if (gpio_is_valid(slot->cd_gpio)) |
231 | gpio_free(slot->cd_gpio); | |
66fd8ad5 AH |
232 | } |
233 | ||
234 | #else | |
235 | ||
c5e027a4 AH |
236 | static inline void sdhci_pci_add_own_cd(struct sdhci_pci_slot *slot) |
237 | { | |
238 | } | |
239 | ||
240 | static inline void sdhci_pci_remove_own_cd(struct sdhci_pci_slot *slot) | |
241 | { | |
242 | } | |
66fd8ad5 AH |
243 | |
244 | #endif | |
245 | ||
0d013bcf AH |
246 | static int mfd_emmc_probe_slot(struct sdhci_pci_slot *slot) |
247 | { | |
66fd8ad5 | 248 | slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE; |
da721cf7 AH |
249 | slot->host->mmc->caps2 |= MMC_CAP2_BOOTPART_NOACC | |
250 | MMC_CAP2_HC_ERASE_SZ; | |
0d013bcf AH |
251 | return 0; |
252 | } | |
253 | ||
93933508 AH |
254 | static int mfd_sdio_probe_slot(struct sdhci_pci_slot *slot) |
255 | { | |
012e4671 | 256 | slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE; |
93933508 AH |
257 | return 0; |
258 | } | |
259 | ||
f9ee3eab AC |
260 | static const struct sdhci_pci_fixes sdhci_intel_mrst_hc0 = { |
261 | .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT, | |
68077b02 | 262 | .probe_slot = mrst_hc_probe_slot, |
f9ee3eab AC |
263 | }; |
264 | ||
35ac6f08 | 265 | static const struct sdhci_pci_fixes sdhci_intel_mrst_hc1_hc2 = { |
f9ee3eab | 266 | .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT, |
35ac6f08 | 267 | .probe = mrst_hc_probe, |
f9ee3eab AC |
268 | }; |
269 | ||
29229052 XS |
270 | static const struct sdhci_pci_fixes sdhci_intel_mfd_sd = { |
271 | .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, | |
c43fd774 | 272 | .allow_runtime_pm = true, |
29229052 XS |
273 | }; |
274 | ||
0d013bcf AH |
275 | static const struct sdhci_pci_fixes sdhci_intel_mfd_sdio = { |
276 | .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, | |
f3c55a7b | 277 | .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON, |
c43fd774 | 278 | .allow_runtime_pm = true, |
93933508 | 279 | .probe_slot = mfd_sdio_probe_slot, |
0d013bcf AH |
280 | }; |
281 | ||
282 | static const struct sdhci_pci_fixes sdhci_intel_mfd_emmc = { | |
29229052 | 283 | .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, |
c43fd774 | 284 | .allow_runtime_pm = true, |
0d013bcf | 285 | .probe_slot = mfd_emmc_probe_slot, |
29229052 XS |
286 | }; |
287 | ||
26daa1ed JL |
288 | /* O2Micro extra registers */ |
289 | #define O2_SD_LOCK_WP 0xD3 | |
290 | #define O2_SD_MULTI_VCC3V 0xEE | |
291 | #define O2_SD_CLKREQ 0xEC | |
292 | #define O2_SD_CAPS 0xE0 | |
293 | #define O2_SD_ADMA1 0xE2 | |
294 | #define O2_SD_ADMA2 0xE7 | |
295 | #define O2_SD_INF_MOD 0xF1 | |
296 | ||
297 | static int o2_probe(struct sdhci_pci_chip *chip) | |
298 | { | |
299 | int ret; | |
300 | u8 scratch; | |
301 | ||
302 | switch (chip->pdev->device) { | |
303 | case PCI_DEVICE_ID_O2_8220: | |
304 | case PCI_DEVICE_ID_O2_8221: | |
305 | case PCI_DEVICE_ID_O2_8320: | |
306 | case PCI_DEVICE_ID_O2_8321: | |
307 | /* This extra setup is required due to broken ADMA. */ | |
308 | ret = pci_read_config_byte(chip->pdev, O2_SD_LOCK_WP, &scratch); | |
309 | if (ret) | |
310 | return ret; | |
311 | scratch &= 0x7f; | |
312 | pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch); | |
313 | ||
314 | /* Set Multi 3 to VCC3V# */ | |
315 | pci_write_config_byte(chip->pdev, O2_SD_MULTI_VCC3V, 0x08); | |
316 | ||
317 | /* Disable CLK_REQ# support after media DET */ | |
318 | ret = pci_read_config_byte(chip->pdev, O2_SD_CLKREQ, &scratch); | |
319 | if (ret) | |
320 | return ret; | |
321 | scratch |= 0x20; | |
322 | pci_write_config_byte(chip->pdev, O2_SD_CLKREQ, scratch); | |
323 | ||
324 | /* Choose capabilities, enable SDMA. We have to write 0x01 | |
325 | * to the capabilities register first to unlock it. | |
326 | */ | |
327 | ret = pci_read_config_byte(chip->pdev, O2_SD_CAPS, &scratch); | |
328 | if (ret) | |
329 | return ret; | |
330 | scratch |= 0x01; | |
331 | pci_write_config_byte(chip->pdev, O2_SD_CAPS, scratch); | |
332 | pci_write_config_byte(chip->pdev, O2_SD_CAPS, 0x73); | |
333 | ||
334 | /* Disable ADMA1/2 */ | |
335 | pci_write_config_byte(chip->pdev, O2_SD_ADMA1, 0x39); | |
336 | pci_write_config_byte(chip->pdev, O2_SD_ADMA2, 0x08); | |
337 | ||
338 | /* Disable the infinite transfer mode */ | |
339 | ret = pci_read_config_byte(chip->pdev, O2_SD_INF_MOD, &scratch); | |
340 | if (ret) | |
341 | return ret; | |
342 | scratch |= 0x08; | |
343 | pci_write_config_byte(chip->pdev, O2_SD_INF_MOD, scratch); | |
344 | ||
345 | /* Lock WP */ | |
346 | ret = pci_read_config_byte(chip->pdev, O2_SD_LOCK_WP, &scratch); | |
347 | if (ret) | |
348 | return ret; | |
349 | scratch |= 0x80; | |
350 | pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch); | |
351 | } | |
352 | ||
353 | return 0; | |
354 | } | |
355 | ||
45211e21 PO |
356 | static int jmicron_pmos(struct sdhci_pci_chip *chip, int on) |
357 | { | |
358 | u8 scratch; | |
359 | int ret; | |
360 | ||
361 | ret = pci_read_config_byte(chip->pdev, 0xAE, &scratch); | |
362 | if (ret) | |
363 | return ret; | |
364 | ||
365 | /* | |
366 | * Turn PMOS on [bit 0], set over current detection to 2.4 V | |
367 | * [bit 1:2] and enable over current debouncing [bit 6]. | |
368 | */ | |
369 | if (on) | |
370 | scratch |= 0x47; | |
371 | else | |
372 | scratch &= ~0x47; | |
373 | ||
374 | ret = pci_write_config_byte(chip->pdev, 0xAE, scratch); | |
375 | if (ret) | |
376 | return ret; | |
377 | ||
378 | return 0; | |
379 | } | |
380 | ||
381 | static int jmicron_probe(struct sdhci_pci_chip *chip) | |
382 | { | |
383 | int ret; | |
8f230f45 | 384 | u16 mmcdev = 0; |
45211e21 | 385 | |
93fc48c7 PO |
386 | if (chip->pdev->revision == 0) { |
387 | chip->quirks |= SDHCI_QUIRK_32BIT_DMA_ADDR | | |
388 | SDHCI_QUIRK_32BIT_DMA_SIZE | | |
2134a922 | 389 | SDHCI_QUIRK_32BIT_ADMA_SIZE | |
4a3cba32 | 390 | SDHCI_QUIRK_RESET_AFTER_REQUEST | |
86a6a874 | 391 | SDHCI_QUIRK_BROKEN_SMALL_PIO; |
93fc48c7 PO |
392 | } |
393 | ||
4489428a PO |
394 | /* |
395 | * JMicron chips can have two interfaces to the same hardware | |
396 | * in order to work around limitations in Microsoft's driver. | |
397 | * We need to make sure we only bind to one of them. | |
398 | * | |
399 | * This code assumes two things: | |
400 | * | |
401 | * 1. The PCI code adds subfunctions in order. | |
402 | * | |
403 | * 2. The MMC interface has a lower subfunction number | |
404 | * than the SD interface. | |
405 | */ | |
8f230f45 TI |
406 | if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_SD) |
407 | mmcdev = PCI_DEVICE_ID_JMICRON_JMB38X_MMC; | |
408 | else if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD) | |
409 | mmcdev = PCI_DEVICE_ID_JMICRON_JMB388_ESD; | |
410 | ||
411 | if (mmcdev) { | |
4489428a PO |
412 | struct pci_dev *sd_dev; |
413 | ||
414 | sd_dev = NULL; | |
415 | while ((sd_dev = pci_get_device(PCI_VENDOR_ID_JMICRON, | |
8f230f45 | 416 | mmcdev, sd_dev)) != NULL) { |
4489428a PO |
417 | if ((PCI_SLOT(chip->pdev->devfn) == |
418 | PCI_SLOT(sd_dev->devfn)) && | |
419 | (chip->pdev->bus == sd_dev->bus)) | |
420 | break; | |
421 | } | |
422 | ||
423 | if (sd_dev) { | |
424 | pci_dev_put(sd_dev); | |
425 | dev_info(&chip->pdev->dev, "Refusing to bind to " | |
426 | "secondary interface.\n"); | |
427 | return -ENODEV; | |
428 | } | |
429 | } | |
430 | ||
45211e21 PO |
431 | /* |
432 | * JMicron chips need a bit of a nudge to enable the power | |
433 | * output pins. | |
434 | */ | |
435 | ret = jmicron_pmos(chip, 1); | |
436 | if (ret) { | |
437 | dev_err(&chip->pdev->dev, "Failure enabling card power\n"); | |
438 | return ret; | |
439 | } | |
440 | ||
82b0e23a TI |
441 | /* quirk for unsable RO-detection on JM388 chips */ |
442 | if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD || | |
443 | chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) | |
444 | chip->quirks |= SDHCI_QUIRK_UNSTABLE_RO_DETECT; | |
445 | ||
45211e21 PO |
446 | return 0; |
447 | } | |
448 | ||
4489428a PO |
449 | static void jmicron_enable_mmc(struct sdhci_host *host, int on) |
450 | { | |
451 | u8 scratch; | |
452 | ||
453 | scratch = readb(host->ioaddr + 0xC0); | |
454 | ||
455 | if (on) | |
456 | scratch |= 0x01; | |
457 | else | |
458 | scratch &= ~0x01; | |
459 | ||
460 | writeb(scratch, host->ioaddr + 0xC0); | |
461 | } | |
462 | ||
463 | static int jmicron_probe_slot(struct sdhci_pci_slot *slot) | |
464 | { | |
2134a922 PO |
465 | if (slot->chip->pdev->revision == 0) { |
466 | u16 version; | |
467 | ||
468 | version = readl(slot->host->ioaddr + SDHCI_HOST_VERSION); | |
469 | version = (version & SDHCI_VENDOR_VER_MASK) >> | |
470 | SDHCI_VENDOR_VER_SHIFT; | |
471 | ||
472 | /* | |
473 | * Older versions of the chip have lots of nasty glitches | |
474 | * in the ADMA engine. It's best just to avoid it | |
475 | * completely. | |
476 | */ | |
477 | if (version < 0xAC) | |
478 | slot->host->quirks |= SDHCI_QUIRK_BROKEN_ADMA; | |
479 | } | |
480 | ||
8f230f45 TI |
481 | /* JM388 MMC doesn't support 1.8V while SD supports it */ |
482 | if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) { | |
483 | slot->host->ocr_avail_sd = MMC_VDD_32_33 | MMC_VDD_33_34 | | |
484 | MMC_VDD_29_30 | MMC_VDD_30_31 | | |
485 | MMC_VDD_165_195; /* allow 1.8V */ | |
486 | slot->host->ocr_avail_mmc = MMC_VDD_32_33 | MMC_VDD_33_34 | | |
487 | MMC_VDD_29_30 | MMC_VDD_30_31; /* no 1.8V for MMC */ | |
488 | } | |
489 | ||
4489428a PO |
490 | /* |
491 | * The secondary interface requires a bit set to get the | |
492 | * interrupts. | |
493 | */ | |
8f230f45 TI |
494 | if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || |
495 | slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) | |
4489428a PO |
496 | jmicron_enable_mmc(slot->host, 1); |
497 | ||
d75c1084 TI |
498 | slot->host->mmc->caps |= MMC_CAP_BUS_WIDTH_TEST; |
499 | ||
4489428a PO |
500 | return 0; |
501 | } | |
502 | ||
1e72859e | 503 | static void jmicron_remove_slot(struct sdhci_pci_slot *slot, int dead) |
4489428a | 504 | { |
1e72859e PO |
505 | if (dead) |
506 | return; | |
507 | ||
8f230f45 TI |
508 | if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || |
509 | slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) | |
4489428a PO |
510 | jmicron_enable_mmc(slot->host, 0); |
511 | } | |
512 | ||
29495aa0 | 513 | static int jmicron_suspend(struct sdhci_pci_chip *chip) |
4489428a PO |
514 | { |
515 | int i; | |
516 | ||
8f230f45 TI |
517 | if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || |
518 | chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) { | |
b177bc91 | 519 | for (i = 0; i < chip->num_slots; i++) |
4489428a PO |
520 | jmicron_enable_mmc(chip->slots[i]->host, 0); |
521 | } | |
522 | ||
523 | return 0; | |
524 | } | |
525 | ||
45211e21 PO |
526 | static int jmicron_resume(struct sdhci_pci_chip *chip) |
527 | { | |
4489428a PO |
528 | int ret, i; |
529 | ||
8f230f45 TI |
530 | if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || |
531 | chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) { | |
b177bc91 | 532 | for (i = 0; i < chip->num_slots; i++) |
4489428a PO |
533 | jmicron_enable_mmc(chip->slots[i]->host, 1); |
534 | } | |
45211e21 PO |
535 | |
536 | ret = jmicron_pmos(chip, 1); | |
537 | if (ret) { | |
538 | dev_err(&chip->pdev->dev, "Failure enabling card power\n"); | |
539 | return ret; | |
540 | } | |
541 | ||
542 | return 0; | |
543 | } | |
544 | ||
26daa1ed JL |
545 | static const struct sdhci_pci_fixes sdhci_o2 = { |
546 | .probe = o2_probe, | |
547 | }; | |
548 | ||
22606405 | 549 | static const struct sdhci_pci_fixes sdhci_jmicron = { |
45211e21 PO |
550 | .probe = jmicron_probe, |
551 | ||
4489428a PO |
552 | .probe_slot = jmicron_probe_slot, |
553 | .remove_slot = jmicron_remove_slot, | |
554 | ||
555 | .suspend = jmicron_suspend, | |
45211e21 | 556 | .resume = jmicron_resume, |
22606405 PO |
557 | }; |
558 | ||
a7a6186c NP |
559 | /* SysKonnect CardBus2SDIO extra registers */ |
560 | #define SYSKT_CTRL 0x200 | |
561 | #define SYSKT_RDFIFO_STAT 0x204 | |
562 | #define SYSKT_WRFIFO_STAT 0x208 | |
563 | #define SYSKT_POWER_DATA 0x20c | |
564 | #define SYSKT_POWER_330 0xef | |
565 | #define SYSKT_POWER_300 0xf8 | |
566 | #define SYSKT_POWER_184 0xcc | |
567 | #define SYSKT_POWER_CMD 0x20d | |
568 | #define SYSKT_POWER_START (1 << 7) | |
569 | #define SYSKT_POWER_STATUS 0x20e | |
570 | #define SYSKT_POWER_STATUS_OK (1 << 0) | |
571 | #define SYSKT_BOARD_REV 0x210 | |
572 | #define SYSKT_CHIP_REV 0x211 | |
573 | #define SYSKT_CONF_DATA 0x212 | |
574 | #define SYSKT_CONF_DATA_1V8 (1 << 2) | |
575 | #define SYSKT_CONF_DATA_2V5 (1 << 1) | |
576 | #define SYSKT_CONF_DATA_3V3 (1 << 0) | |
577 | ||
578 | static int syskt_probe(struct sdhci_pci_chip *chip) | |
579 | { | |
580 | if ((chip->pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) { | |
581 | chip->pdev->class &= ~0x0000FF; | |
582 | chip->pdev->class |= PCI_SDHCI_IFDMA; | |
583 | } | |
584 | return 0; | |
585 | } | |
586 | ||
587 | static int syskt_probe_slot(struct sdhci_pci_slot *slot) | |
588 | { | |
589 | int tm, ps; | |
590 | ||
591 | u8 board_rev = readb(slot->host->ioaddr + SYSKT_BOARD_REV); | |
592 | u8 chip_rev = readb(slot->host->ioaddr + SYSKT_CHIP_REV); | |
593 | dev_info(&slot->chip->pdev->dev, "SysKonnect CardBus2SDIO, " | |
594 | "board rev %d.%d, chip rev %d.%d\n", | |
595 | board_rev >> 4, board_rev & 0xf, | |
596 | chip_rev >> 4, chip_rev & 0xf); | |
597 | if (chip_rev >= 0x20) | |
598 | slot->host->quirks |= SDHCI_QUIRK_FORCE_DMA; | |
599 | ||
600 | writeb(SYSKT_POWER_330, slot->host->ioaddr + SYSKT_POWER_DATA); | |
601 | writeb(SYSKT_POWER_START, slot->host->ioaddr + SYSKT_POWER_CMD); | |
602 | udelay(50); | |
603 | tm = 10; /* Wait max 1 ms */ | |
604 | do { | |
605 | ps = readw(slot->host->ioaddr + SYSKT_POWER_STATUS); | |
606 | if (ps & SYSKT_POWER_STATUS_OK) | |
607 | break; | |
608 | udelay(100); | |
609 | } while (--tm); | |
610 | if (!tm) { | |
611 | dev_err(&slot->chip->pdev->dev, | |
612 | "power regulator never stabilized"); | |
613 | writeb(0, slot->host->ioaddr + SYSKT_POWER_CMD); | |
614 | return -ENODEV; | |
615 | } | |
616 | ||
617 | return 0; | |
618 | } | |
619 | ||
620 | static const struct sdhci_pci_fixes sdhci_syskt = { | |
621 | .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER, | |
622 | .probe = syskt_probe, | |
623 | .probe_slot = syskt_probe_slot, | |
624 | }; | |
625 | ||
557b0697 HW |
626 | static int via_probe(struct sdhci_pci_chip *chip) |
627 | { | |
628 | if (chip->pdev->revision == 0x10) | |
629 | chip->quirks |= SDHCI_QUIRK_DELAY_AFTER_POWER; | |
630 | ||
631 | return 0; | |
632 | } | |
633 | ||
634 | static const struct sdhci_pci_fixes sdhci_via = { | |
635 | .probe = via_probe, | |
636 | }; | |
637 | ||
22606405 | 638 | static const struct pci_device_id pci_ids[] __devinitdata = { |
b8c86fc5 PO |
639 | { |
640 | .vendor = PCI_VENDOR_ID_RICOH, | |
641 | .device = PCI_DEVICE_ID_RICOH_R5C822, | |
22606405 | 642 | .subvendor = PCI_ANY_ID, |
b8c86fc5 | 643 | .subdevice = PCI_ANY_ID, |
22606405 | 644 | .driver_data = (kernel_ulong_t)&sdhci_ricoh, |
b8c86fc5 PO |
645 | }, |
646 | ||
ccc92c23 ML |
647 | { |
648 | .vendor = PCI_VENDOR_ID_RICOH, | |
649 | .device = 0x843, | |
650 | .subvendor = PCI_ANY_ID, | |
651 | .subdevice = PCI_ANY_ID, | |
652 | .driver_data = (kernel_ulong_t)&sdhci_ricoh_mmc, | |
653 | }, | |
654 | ||
568133eb PC |
655 | { |
656 | .vendor = PCI_VENDOR_ID_RICOH, | |
657 | .device = 0xe822, | |
658 | .subvendor = PCI_ANY_ID, | |
659 | .subdevice = PCI_ANY_ID, | |
660 | .driver_data = (kernel_ulong_t)&sdhci_ricoh_mmc, | |
661 | }, | |
662 | ||
5fd11c07 MI |
663 | { |
664 | .vendor = PCI_VENDOR_ID_RICOH, | |
665 | .device = 0xe823, | |
666 | .subvendor = PCI_ANY_ID, | |
667 | .subdevice = PCI_ANY_ID, | |
668 | .driver_data = (kernel_ulong_t)&sdhci_ricoh_mmc, | |
669 | }, | |
670 | ||
b8c86fc5 PO |
671 | { |
672 | .vendor = PCI_VENDOR_ID_ENE, | |
673 | .device = PCI_DEVICE_ID_ENE_CB712_SD, | |
674 | .subvendor = PCI_ANY_ID, | |
675 | .subdevice = PCI_ANY_ID, | |
22606405 | 676 | .driver_data = (kernel_ulong_t)&sdhci_ene_712, |
b8c86fc5 PO |
677 | }, |
678 | ||
679 | { | |
680 | .vendor = PCI_VENDOR_ID_ENE, | |
681 | .device = PCI_DEVICE_ID_ENE_CB712_SD_2, | |
682 | .subvendor = PCI_ANY_ID, | |
683 | .subdevice = PCI_ANY_ID, | |
22606405 | 684 | .driver_data = (kernel_ulong_t)&sdhci_ene_712, |
b8c86fc5 PO |
685 | }, |
686 | ||
687 | { | |
688 | .vendor = PCI_VENDOR_ID_ENE, | |
689 | .device = PCI_DEVICE_ID_ENE_CB714_SD, | |
690 | .subvendor = PCI_ANY_ID, | |
691 | .subdevice = PCI_ANY_ID, | |
22606405 | 692 | .driver_data = (kernel_ulong_t)&sdhci_ene_714, |
b8c86fc5 PO |
693 | }, |
694 | ||
695 | { | |
696 | .vendor = PCI_VENDOR_ID_ENE, | |
697 | .device = PCI_DEVICE_ID_ENE_CB714_SD_2, | |
698 | .subvendor = PCI_ANY_ID, | |
699 | .subdevice = PCI_ANY_ID, | |
22606405 | 700 | .driver_data = (kernel_ulong_t)&sdhci_ene_714, |
b8c86fc5 PO |
701 | }, |
702 | ||
703 | { | |
704 | .vendor = PCI_VENDOR_ID_MARVELL, | |
8c5eb880 | 705 | .device = PCI_DEVICE_ID_MARVELL_88ALP01_SD, |
b8c86fc5 PO |
706 | .subvendor = PCI_ANY_ID, |
707 | .subdevice = PCI_ANY_ID, | |
22606405 | 708 | .driver_data = (kernel_ulong_t)&sdhci_cafe, |
b8c86fc5 PO |
709 | }, |
710 | ||
711 | { | |
712 | .vendor = PCI_VENDOR_ID_JMICRON, | |
713 | .device = PCI_DEVICE_ID_JMICRON_JMB38X_SD, | |
714 | .subvendor = PCI_ANY_ID, | |
715 | .subdevice = PCI_ANY_ID, | |
22606405 | 716 | .driver_data = (kernel_ulong_t)&sdhci_jmicron, |
b8c86fc5 PO |
717 | }, |
718 | ||
4489428a PO |
719 | { |
720 | .vendor = PCI_VENDOR_ID_JMICRON, | |
721 | .device = PCI_DEVICE_ID_JMICRON_JMB38X_MMC, | |
722 | .subvendor = PCI_ANY_ID, | |
723 | .subdevice = PCI_ANY_ID, | |
724 | .driver_data = (kernel_ulong_t)&sdhci_jmicron, | |
8f230f45 TI |
725 | }, |
726 | ||
727 | { | |
728 | .vendor = PCI_VENDOR_ID_JMICRON, | |
729 | .device = PCI_DEVICE_ID_JMICRON_JMB388_SD, | |
730 | .subvendor = PCI_ANY_ID, | |
731 | .subdevice = PCI_ANY_ID, | |
732 | .driver_data = (kernel_ulong_t)&sdhci_jmicron, | |
733 | }, | |
734 | ||
735 | { | |
736 | .vendor = PCI_VENDOR_ID_JMICRON, | |
737 | .device = PCI_DEVICE_ID_JMICRON_JMB388_ESD, | |
738 | .subvendor = PCI_ANY_ID, | |
739 | .subdevice = PCI_ANY_ID, | |
740 | .driver_data = (kernel_ulong_t)&sdhci_jmicron, | |
4489428a PO |
741 | }, |
742 | ||
a7a6186c NP |
743 | { |
744 | .vendor = PCI_VENDOR_ID_SYSKONNECT, | |
745 | .device = 0x8000, | |
746 | .subvendor = PCI_ANY_ID, | |
747 | .subdevice = PCI_ANY_ID, | |
748 | .driver_data = (kernel_ulong_t)&sdhci_syskt, | |
749 | }, | |
750 | ||
557b0697 HW |
751 | { |
752 | .vendor = PCI_VENDOR_ID_VIA, | |
753 | .device = 0x95d0, | |
754 | .subvendor = PCI_ANY_ID, | |
755 | .subdevice = PCI_ANY_ID, | |
756 | .driver_data = (kernel_ulong_t)&sdhci_via, | |
757 | }, | |
758 | ||
29229052 XS |
759 | { |
760 | .vendor = PCI_VENDOR_ID_INTEL, | |
f9ee3eab AC |
761 | .device = PCI_DEVICE_ID_INTEL_MRST_SD0, |
762 | .subvendor = PCI_ANY_ID, | |
763 | .subdevice = PCI_ANY_ID, | |
764 | .driver_data = (kernel_ulong_t)&sdhci_intel_mrst_hc0, | |
765 | }, | |
766 | ||
767 | { | |
768 | .vendor = PCI_VENDOR_ID_INTEL, | |
769 | .device = PCI_DEVICE_ID_INTEL_MRST_SD1, | |
770 | .subvendor = PCI_ANY_ID, | |
771 | .subdevice = PCI_ANY_ID, | |
35ac6f08 JP |
772 | .driver_data = (kernel_ulong_t)&sdhci_intel_mrst_hc1_hc2, |
773 | }, | |
774 | ||
775 | { | |
776 | .vendor = PCI_VENDOR_ID_INTEL, | |
777 | .device = PCI_DEVICE_ID_INTEL_MRST_SD2, | |
778 | .subvendor = PCI_ANY_ID, | |
779 | .subdevice = PCI_ANY_ID, | |
780 | .driver_data = (kernel_ulong_t)&sdhci_intel_mrst_hc1_hc2, | |
f9ee3eab AC |
781 | }, |
782 | ||
783 | { | |
784 | .vendor = PCI_VENDOR_ID_INTEL, | |
29229052 XS |
785 | .device = PCI_DEVICE_ID_INTEL_MFD_SD, |
786 | .subvendor = PCI_ANY_ID, | |
787 | .subdevice = PCI_ANY_ID, | |
788 | .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sd, | |
789 | }, | |
790 | ||
791 | { | |
792 | .vendor = PCI_VENDOR_ID_INTEL, | |
793 | .device = PCI_DEVICE_ID_INTEL_MFD_SDIO1, | |
794 | .subvendor = PCI_ANY_ID, | |
795 | .subdevice = PCI_ANY_ID, | |
0d013bcf | 796 | .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sdio, |
29229052 XS |
797 | }, |
798 | ||
799 | { | |
800 | .vendor = PCI_VENDOR_ID_INTEL, | |
801 | .device = PCI_DEVICE_ID_INTEL_MFD_SDIO2, | |
802 | .subvendor = PCI_ANY_ID, | |
803 | .subdevice = PCI_ANY_ID, | |
0d013bcf | 804 | .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sdio, |
29229052 XS |
805 | }, |
806 | ||
807 | { | |
808 | .vendor = PCI_VENDOR_ID_INTEL, | |
809 | .device = PCI_DEVICE_ID_INTEL_MFD_EMMC0, | |
810 | .subvendor = PCI_ANY_ID, | |
811 | .subdevice = PCI_ANY_ID, | |
0d013bcf | 812 | .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc, |
29229052 XS |
813 | }, |
814 | ||
815 | { | |
816 | .vendor = PCI_VENDOR_ID_INTEL, | |
817 | .device = PCI_DEVICE_ID_INTEL_MFD_EMMC1, | |
818 | .subvendor = PCI_ANY_ID, | |
819 | .subdevice = PCI_ANY_ID, | |
0d013bcf | 820 | .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc, |
29229052 XS |
821 | }, |
822 | ||
26daa1ed JL |
823 | { |
824 | .vendor = PCI_VENDOR_ID_O2, | |
825 | .device = PCI_DEVICE_ID_O2_8120, | |
826 | .subvendor = PCI_ANY_ID, | |
827 | .subdevice = PCI_ANY_ID, | |
828 | .driver_data = (kernel_ulong_t)&sdhci_o2, | |
829 | }, | |
830 | ||
831 | { | |
832 | .vendor = PCI_VENDOR_ID_O2, | |
833 | .device = PCI_DEVICE_ID_O2_8220, | |
834 | .subvendor = PCI_ANY_ID, | |
835 | .subdevice = PCI_ANY_ID, | |
836 | .driver_data = (kernel_ulong_t)&sdhci_o2, | |
837 | }, | |
838 | ||
839 | { | |
840 | .vendor = PCI_VENDOR_ID_O2, | |
841 | .device = PCI_DEVICE_ID_O2_8221, | |
842 | .subvendor = PCI_ANY_ID, | |
843 | .subdevice = PCI_ANY_ID, | |
844 | .driver_data = (kernel_ulong_t)&sdhci_o2, | |
845 | }, | |
846 | ||
847 | { | |
848 | .vendor = PCI_VENDOR_ID_O2, | |
849 | .device = PCI_DEVICE_ID_O2_8320, | |
850 | .subvendor = PCI_ANY_ID, | |
851 | .subdevice = PCI_ANY_ID, | |
852 | .driver_data = (kernel_ulong_t)&sdhci_o2, | |
853 | }, | |
854 | ||
855 | { | |
856 | .vendor = PCI_VENDOR_ID_O2, | |
857 | .device = PCI_DEVICE_ID_O2_8321, | |
858 | .subvendor = PCI_ANY_ID, | |
859 | .subdevice = PCI_ANY_ID, | |
860 | .driver_data = (kernel_ulong_t)&sdhci_o2, | |
861 | }, | |
862 | ||
b8c86fc5 PO |
863 | { /* Generic SD host controller */ |
864 | PCI_DEVICE_CLASS((PCI_CLASS_SYSTEM_SDHCI << 8), 0xFFFF00) | |
865 | }, | |
866 | ||
867 | { /* end: all zeroes */ }, | |
868 | }; | |
869 | ||
870 | MODULE_DEVICE_TABLE(pci, pci_ids); | |
871 | ||
b8c86fc5 PO |
872 | /*****************************************************************************\ |
873 | * * | |
874 | * SDHCI core callbacks * | |
875 | * * | |
876 | \*****************************************************************************/ | |
877 | ||
878 | static int sdhci_pci_enable_dma(struct sdhci_host *host) | |
879 | { | |
880 | struct sdhci_pci_slot *slot; | |
881 | struct pci_dev *pdev; | |
882 | int ret; | |
883 | ||
884 | slot = sdhci_priv(host); | |
885 | pdev = slot->chip->pdev; | |
886 | ||
887 | if (((pdev->class & 0xFFFF00) == (PCI_CLASS_SYSTEM_SDHCI << 8)) && | |
888 | ((pdev->class & 0x0000FF) != PCI_SDHCI_IFDMA) && | |
a13abc7b | 889 | (host->flags & SDHCI_USE_SDMA)) { |
b8c86fc5 PO |
890 | dev_warn(&pdev->dev, "Will use DMA mode even though HW " |
891 | "doesn't fully claim to support it.\n"); | |
892 | } | |
893 | ||
284901a9 | 894 | ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); |
b8c86fc5 PO |
895 | if (ret) |
896 | return ret; | |
897 | ||
898 | pci_set_master(pdev); | |
899 | ||
900 | return 0; | |
901 | } | |
902 | ||
68077b02 ML |
903 | static int sdhci_pci_8bit_width(struct sdhci_host *host, int width) |
904 | { | |
905 | u8 ctrl; | |
906 | ||
907 | ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); | |
908 | ||
909 | switch (width) { | |
910 | case MMC_BUS_WIDTH_8: | |
911 | ctrl |= SDHCI_CTRL_8BITBUS; | |
912 | ctrl &= ~SDHCI_CTRL_4BITBUS; | |
913 | break; | |
914 | case MMC_BUS_WIDTH_4: | |
915 | ctrl |= SDHCI_CTRL_4BITBUS; | |
916 | ctrl &= ~SDHCI_CTRL_8BITBUS; | |
917 | break; | |
918 | default: | |
919 | ctrl &= ~(SDHCI_CTRL_8BITBUS | SDHCI_CTRL_4BITBUS); | |
920 | break; | |
921 | } | |
922 | ||
923 | sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); | |
924 | ||
925 | return 0; | |
926 | } | |
927 | ||
0f201655 AH |
928 | static void sdhci_pci_hw_reset(struct sdhci_host *host) |
929 | { | |
930 | struct sdhci_pci_slot *slot = sdhci_priv(host); | |
931 | int rst_n_gpio = slot->rst_n_gpio; | |
932 | ||
933 | if (!gpio_is_valid(rst_n_gpio)) | |
934 | return; | |
935 | gpio_set_value_cansleep(rst_n_gpio, 0); | |
936 | /* For eMMC, minimum is 1us but give it 10us for good measure */ | |
937 | udelay(10); | |
938 | gpio_set_value_cansleep(rst_n_gpio, 1); | |
939 | /* For eMMC, minimum is 200us but give it 300us for good measure */ | |
940 | usleep_range(300, 1000); | |
941 | } | |
942 | ||
b8c86fc5 PO |
943 | static struct sdhci_ops sdhci_pci_ops = { |
944 | .enable_dma = sdhci_pci_enable_dma, | |
68077b02 | 945 | .platform_8bit_width = sdhci_pci_8bit_width, |
0f201655 | 946 | .hw_reset = sdhci_pci_hw_reset, |
b8c86fc5 PO |
947 | }; |
948 | ||
949 | /*****************************************************************************\ | |
950 | * * | |
951 | * Suspend/resume * | |
952 | * * | |
953 | \*****************************************************************************/ | |
954 | ||
955 | #ifdef CONFIG_PM | |
956 | ||
29495aa0 | 957 | static int sdhci_pci_suspend(struct device *dev) |
b8c86fc5 | 958 | { |
29495aa0 | 959 | struct pci_dev *pdev = to_pci_dev(dev); |
b8c86fc5 PO |
960 | struct sdhci_pci_chip *chip; |
961 | struct sdhci_pci_slot *slot; | |
5f619704 | 962 | mmc_pm_flag_t slot_pm_flags; |
2f4cbb3d | 963 | mmc_pm_flag_t pm_flags = 0; |
b8c86fc5 PO |
964 | int i, ret; |
965 | ||
966 | chip = pci_get_drvdata(pdev); | |
967 | if (!chip) | |
968 | return 0; | |
969 | ||
b177bc91 | 970 | for (i = 0; i < chip->num_slots; i++) { |
b8c86fc5 PO |
971 | slot = chip->slots[i]; |
972 | if (!slot) | |
973 | continue; | |
974 | ||
29495aa0 | 975 | ret = sdhci_suspend_host(slot->host); |
b8c86fc5 | 976 | |
b678b91f AL |
977 | if (ret) |
978 | goto err_pci_suspend; | |
2f4cbb3d | 979 | |
5f619704 DD |
980 | slot_pm_flags = slot->host->mmc->pm_flags; |
981 | if (slot_pm_flags & MMC_PM_WAKE_SDIO_IRQ) | |
982 | sdhci_enable_irq_wakeups(slot->host); | |
983 | ||
984 | pm_flags |= slot_pm_flags; | |
b8c86fc5 PO |
985 | } |
986 | ||
4489428a | 987 | if (chip->fixes && chip->fixes->suspend) { |
29495aa0 | 988 | ret = chip->fixes->suspend(chip); |
b678b91f AL |
989 | if (ret) |
990 | goto err_pci_suspend; | |
4489428a PO |
991 | } |
992 | ||
b8c86fc5 | 993 | pci_save_state(pdev); |
2f4cbb3d | 994 | if (pm_flags & MMC_PM_KEEP_POWER) { |
5f619704 DD |
995 | if (pm_flags & MMC_PM_WAKE_SDIO_IRQ) { |
996 | pci_pme_active(pdev, true); | |
2f4cbb3d | 997 | pci_enable_wake(pdev, PCI_D3hot, 1); |
5f619704 | 998 | } |
2f4cbb3d NP |
999 | pci_set_power_state(pdev, PCI_D3hot); |
1000 | } else { | |
29495aa0 | 1001 | pci_enable_wake(pdev, PCI_D3hot, 0); |
2f4cbb3d | 1002 | pci_disable_device(pdev); |
29495aa0 | 1003 | pci_set_power_state(pdev, PCI_D3hot); |
2f4cbb3d | 1004 | } |
b8c86fc5 PO |
1005 | |
1006 | return 0; | |
b678b91f AL |
1007 | |
1008 | err_pci_suspend: | |
1009 | while (--i >= 0) | |
1010 | sdhci_resume_host(chip->slots[i]->host); | |
1011 | return ret; | |
b8c86fc5 PO |
1012 | } |
1013 | ||
29495aa0 | 1014 | static int sdhci_pci_resume(struct device *dev) |
b8c86fc5 | 1015 | { |
29495aa0 | 1016 | struct pci_dev *pdev = to_pci_dev(dev); |
b8c86fc5 PO |
1017 | struct sdhci_pci_chip *chip; |
1018 | struct sdhci_pci_slot *slot; | |
1019 | int i, ret; | |
1020 | ||
1021 | chip = pci_get_drvdata(pdev); | |
1022 | if (!chip) | |
1023 | return 0; | |
1024 | ||
1025 | pci_set_power_state(pdev, PCI_D0); | |
1026 | pci_restore_state(pdev); | |
1027 | ret = pci_enable_device(pdev); | |
1028 | if (ret) | |
1029 | return ret; | |
1030 | ||
45211e21 PO |
1031 | if (chip->fixes && chip->fixes->resume) { |
1032 | ret = chip->fixes->resume(chip); | |
1033 | if (ret) | |
1034 | return ret; | |
1035 | } | |
1036 | ||
b177bc91 | 1037 | for (i = 0; i < chip->num_slots; i++) { |
b8c86fc5 PO |
1038 | slot = chip->slots[i]; |
1039 | if (!slot) | |
1040 | continue; | |
1041 | ||
1042 | ret = sdhci_resume_host(slot->host); | |
1043 | if (ret) | |
1044 | return ret; | |
1045 | } | |
1046 | ||
1047 | return 0; | |
1048 | } | |
1049 | ||
1050 | #else /* CONFIG_PM */ | |
1051 | ||
1052 | #define sdhci_pci_suspend NULL | |
1053 | #define sdhci_pci_resume NULL | |
1054 | ||
1055 | #endif /* CONFIG_PM */ | |
1056 | ||
66fd8ad5 AH |
1057 | #ifdef CONFIG_PM_RUNTIME |
1058 | ||
1059 | static int sdhci_pci_runtime_suspend(struct device *dev) | |
1060 | { | |
1061 | struct pci_dev *pdev = container_of(dev, struct pci_dev, dev); | |
1062 | struct sdhci_pci_chip *chip; | |
1063 | struct sdhci_pci_slot *slot; | |
66fd8ad5 AH |
1064 | int i, ret; |
1065 | ||
1066 | chip = pci_get_drvdata(pdev); | |
1067 | if (!chip) | |
1068 | return 0; | |
1069 | ||
1070 | for (i = 0; i < chip->num_slots; i++) { | |
1071 | slot = chip->slots[i]; | |
1072 | if (!slot) | |
1073 | continue; | |
1074 | ||
1075 | ret = sdhci_runtime_suspend_host(slot->host); | |
1076 | ||
b678b91f AL |
1077 | if (ret) |
1078 | goto err_pci_runtime_suspend; | |
66fd8ad5 AH |
1079 | } |
1080 | ||
1081 | if (chip->fixes && chip->fixes->suspend) { | |
29495aa0 | 1082 | ret = chip->fixes->suspend(chip); |
b678b91f AL |
1083 | if (ret) |
1084 | goto err_pci_runtime_suspend; | |
66fd8ad5 AH |
1085 | } |
1086 | ||
1087 | return 0; | |
b678b91f AL |
1088 | |
1089 | err_pci_runtime_suspend: | |
1090 | while (--i >= 0) | |
1091 | sdhci_runtime_resume_host(chip->slots[i]->host); | |
1092 | return ret; | |
66fd8ad5 AH |
1093 | } |
1094 | ||
1095 | static int sdhci_pci_runtime_resume(struct device *dev) | |
1096 | { | |
1097 | struct pci_dev *pdev = container_of(dev, struct pci_dev, dev); | |
1098 | struct sdhci_pci_chip *chip; | |
1099 | struct sdhci_pci_slot *slot; | |
1100 | int i, ret; | |
1101 | ||
1102 | chip = pci_get_drvdata(pdev); | |
1103 | if (!chip) | |
1104 | return 0; | |
1105 | ||
1106 | if (chip->fixes && chip->fixes->resume) { | |
1107 | ret = chip->fixes->resume(chip); | |
1108 | if (ret) | |
1109 | return ret; | |
1110 | } | |
1111 | ||
1112 | for (i = 0; i < chip->num_slots; i++) { | |
1113 | slot = chip->slots[i]; | |
1114 | if (!slot) | |
1115 | continue; | |
1116 | ||
1117 | ret = sdhci_runtime_resume_host(slot->host); | |
1118 | if (ret) | |
1119 | return ret; | |
1120 | } | |
1121 | ||
1122 | return 0; | |
1123 | } | |
1124 | ||
1125 | static int sdhci_pci_runtime_idle(struct device *dev) | |
1126 | { | |
1127 | return 0; | |
1128 | } | |
1129 | ||
1130 | #else | |
1131 | ||
1132 | #define sdhci_pci_runtime_suspend NULL | |
1133 | #define sdhci_pci_runtime_resume NULL | |
1134 | #define sdhci_pci_runtime_idle NULL | |
1135 | ||
1136 | #endif | |
1137 | ||
1138 | static const struct dev_pm_ops sdhci_pci_pm_ops = { | |
29495aa0 ML |
1139 | .suspend = sdhci_pci_suspend, |
1140 | .resume = sdhci_pci_resume, | |
66fd8ad5 AH |
1141 | .runtime_suspend = sdhci_pci_runtime_suspend, |
1142 | .runtime_resume = sdhci_pci_runtime_resume, | |
1143 | .runtime_idle = sdhci_pci_runtime_idle, | |
1144 | }; | |
1145 | ||
b8c86fc5 PO |
1146 | /*****************************************************************************\ |
1147 | * * | |
1148 | * Device probing/removal * | |
1149 | * * | |
1150 | \*****************************************************************************/ | |
1151 | ||
1152 | static struct sdhci_pci_slot * __devinit sdhci_pci_probe_slot( | |
52c506f0 AH |
1153 | struct pci_dev *pdev, struct sdhci_pci_chip *chip, int first_bar, |
1154 | int slotno) | |
b8c86fc5 PO |
1155 | { |
1156 | struct sdhci_pci_slot *slot; | |
1157 | struct sdhci_host *host; | |
52c506f0 | 1158 | int ret, bar = first_bar + slotno; |
b8c86fc5 PO |
1159 | |
1160 | if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) { | |
1161 | dev_err(&pdev->dev, "BAR %d is not iomem. Aborting.\n", bar); | |
1162 | return ERR_PTR(-ENODEV); | |
1163 | } | |
1164 | ||
1165 | if (pci_resource_len(pdev, bar) != 0x100) { | |
1166 | dev_err(&pdev->dev, "Invalid iomem size. You may " | |
1167 | "experience problems.\n"); | |
1168 | } | |
1169 | ||
1170 | if ((pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) { | |
1171 | dev_err(&pdev->dev, "Vendor specific interface. Aborting.\n"); | |
1172 | return ERR_PTR(-ENODEV); | |
1173 | } | |
1174 | ||
1175 | if ((pdev->class & 0x0000FF) > PCI_SDHCI_IFVENDOR) { | |
1176 | dev_err(&pdev->dev, "Unknown interface. Aborting.\n"); | |
1177 | return ERR_PTR(-ENODEV); | |
1178 | } | |
1179 | ||
1180 | host = sdhci_alloc_host(&pdev->dev, sizeof(struct sdhci_pci_slot)); | |
1181 | if (IS_ERR(host)) { | |
c60a32cd | 1182 | dev_err(&pdev->dev, "cannot allocate host\n"); |
dc0fd7b5 | 1183 | return ERR_CAST(host); |
b8c86fc5 PO |
1184 | } |
1185 | ||
1186 | slot = sdhci_priv(host); | |
1187 | ||
1188 | slot->chip = chip; | |
1189 | slot->host = host; | |
1190 | slot->pci_bar = bar; | |
0f201655 | 1191 | slot->rst_n_gpio = -EINVAL; |
c5e027a4 | 1192 | slot->cd_gpio = -EINVAL; |
b8c86fc5 | 1193 | |
52c506f0 AH |
1194 | /* Retrieve platform data if there is any */ |
1195 | if (*sdhci_pci_get_data) | |
1196 | slot->data = sdhci_pci_get_data(pdev, slotno); | |
1197 | ||
1198 | if (slot->data) { | |
1199 | if (slot->data->setup) { | |
1200 | ret = slot->data->setup(slot->data); | |
1201 | if (ret) { | |
1202 | dev_err(&pdev->dev, "platform setup failed\n"); | |
1203 | goto free; | |
1204 | } | |
1205 | } | |
c5e027a4 AH |
1206 | slot->rst_n_gpio = slot->data->rst_n_gpio; |
1207 | slot->cd_gpio = slot->data->cd_gpio; | |
52c506f0 AH |
1208 | } |
1209 | ||
b8c86fc5 PO |
1210 | host->hw_name = "PCI"; |
1211 | host->ops = &sdhci_pci_ops; | |
1212 | host->quirks = chip->quirks; | |
f3c55a7b | 1213 | host->quirks2 = chip->quirks2; |
b8c86fc5 PO |
1214 | |
1215 | host->irq = pdev->irq; | |
1216 | ||
1217 | ret = pci_request_region(pdev, bar, mmc_hostname(host->mmc)); | |
1218 | if (ret) { | |
1219 | dev_err(&pdev->dev, "cannot request region\n"); | |
52c506f0 | 1220 | goto cleanup; |
b8c86fc5 PO |
1221 | } |
1222 | ||
092f82ed | 1223 | host->ioaddr = pci_ioremap_bar(pdev, bar); |
b8c86fc5 PO |
1224 | if (!host->ioaddr) { |
1225 | dev_err(&pdev->dev, "failed to remap registers\n"); | |
9fdcdbb0 | 1226 | ret = -ENOMEM; |
b8c86fc5 PO |
1227 | goto release; |
1228 | } | |
1229 | ||
4489428a PO |
1230 | if (chip->fixes && chip->fixes->probe_slot) { |
1231 | ret = chip->fixes->probe_slot(slot); | |
1232 | if (ret) | |
1233 | goto unmap; | |
1234 | } | |
1235 | ||
c5e027a4 AH |
1236 | if (gpio_is_valid(slot->rst_n_gpio)) { |
1237 | if (!gpio_request(slot->rst_n_gpio, "eMMC_reset")) { | |
1238 | gpio_direction_output(slot->rst_n_gpio, 1); | |
1239 | slot->host->mmc->caps |= MMC_CAP_HW_RESET; | |
1240 | } else { | |
1241 | dev_warn(&pdev->dev, "failed to request rst_n_gpio\n"); | |
1242 | slot->rst_n_gpio = -EINVAL; | |
1243 | } | |
1244 | } | |
1245 | ||
2f4cbb3d NP |
1246 | host->mmc->pm_caps = MMC_PM_KEEP_POWER | MMC_PM_WAKE_SDIO_IRQ; |
1247 | ||
b8c86fc5 PO |
1248 | ret = sdhci_add_host(host); |
1249 | if (ret) | |
4489428a | 1250 | goto remove; |
b8c86fc5 | 1251 | |
c5e027a4 AH |
1252 | sdhci_pci_add_own_cd(slot); |
1253 | ||
b8c86fc5 PO |
1254 | return slot; |
1255 | ||
4489428a | 1256 | remove: |
c5e027a4 AH |
1257 | if (gpio_is_valid(slot->rst_n_gpio)) |
1258 | gpio_free(slot->rst_n_gpio); | |
1259 | ||
4489428a | 1260 | if (chip->fixes && chip->fixes->remove_slot) |
1e72859e | 1261 | chip->fixes->remove_slot(slot, 0); |
4489428a | 1262 | |
b8c86fc5 PO |
1263 | unmap: |
1264 | iounmap(host->ioaddr); | |
1265 | ||
1266 | release: | |
1267 | pci_release_region(pdev, bar); | |
c60a32cd | 1268 | |
52c506f0 AH |
1269 | cleanup: |
1270 | if (slot->data && slot->data->cleanup) | |
1271 | slot->data->cleanup(slot->data); | |
1272 | ||
c60a32cd | 1273 | free: |
b8c86fc5 PO |
1274 | sdhci_free_host(host); |
1275 | ||
1276 | return ERR_PTR(ret); | |
1277 | } | |
1278 | ||
1279 | static void sdhci_pci_remove_slot(struct sdhci_pci_slot *slot) | |
1280 | { | |
1e72859e PO |
1281 | int dead; |
1282 | u32 scratch; | |
1283 | ||
c5e027a4 AH |
1284 | sdhci_pci_remove_own_cd(slot); |
1285 | ||
1e72859e PO |
1286 | dead = 0; |
1287 | scratch = readl(slot->host->ioaddr + SDHCI_INT_STATUS); | |
1288 | if (scratch == (u32)-1) | |
1289 | dead = 1; | |
1290 | ||
1291 | sdhci_remove_host(slot->host, dead); | |
4489428a | 1292 | |
c5e027a4 AH |
1293 | if (gpio_is_valid(slot->rst_n_gpio)) |
1294 | gpio_free(slot->rst_n_gpio); | |
1295 | ||
4489428a | 1296 | if (slot->chip->fixes && slot->chip->fixes->remove_slot) |
1e72859e | 1297 | slot->chip->fixes->remove_slot(slot, dead); |
4489428a | 1298 | |
52c506f0 AH |
1299 | if (slot->data && slot->data->cleanup) |
1300 | slot->data->cleanup(slot->data); | |
1301 | ||
b8c86fc5 | 1302 | pci_release_region(slot->chip->pdev, slot->pci_bar); |
4489428a | 1303 | |
b8c86fc5 PO |
1304 | sdhci_free_host(slot->host); |
1305 | } | |
1306 | ||
66fd8ad5 AH |
1307 | static void __devinit sdhci_pci_runtime_pm_allow(struct device *dev) |
1308 | { | |
1309 | pm_runtime_put_noidle(dev); | |
1310 | pm_runtime_allow(dev); | |
1311 | pm_runtime_set_autosuspend_delay(dev, 50); | |
1312 | pm_runtime_use_autosuspend(dev); | |
1313 | pm_suspend_ignore_children(dev, 1); | |
1314 | } | |
1315 | ||
1316 | static void __devexit sdhci_pci_runtime_pm_forbid(struct device *dev) | |
1317 | { | |
1318 | pm_runtime_forbid(dev); | |
1319 | pm_runtime_get_noresume(dev); | |
1320 | } | |
1321 | ||
b8c86fc5 PO |
1322 | static int __devinit sdhci_pci_probe(struct pci_dev *pdev, |
1323 | const struct pci_device_id *ent) | |
1324 | { | |
1325 | struct sdhci_pci_chip *chip; | |
1326 | struct sdhci_pci_slot *slot; | |
1327 | ||
cf5e23e1 | 1328 | u8 slots, first_bar; |
b8c86fc5 PO |
1329 | int ret, i; |
1330 | ||
1331 | BUG_ON(pdev == NULL); | |
1332 | BUG_ON(ent == NULL); | |
1333 | ||
b8c86fc5 | 1334 | dev_info(&pdev->dev, "SDHCI controller found [%04x:%04x] (rev %x)\n", |
cf5e23e1 | 1335 | (int)pdev->vendor, (int)pdev->device, (int)pdev->revision); |
b8c86fc5 PO |
1336 | |
1337 | ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &slots); | |
1338 | if (ret) | |
1339 | return ret; | |
1340 | ||
1341 | slots = PCI_SLOT_INFO_SLOTS(slots) + 1; | |
1342 | dev_dbg(&pdev->dev, "found %d slot(s)\n", slots); | |
1343 | if (slots == 0) | |
1344 | return -ENODEV; | |
1345 | ||
1346 | BUG_ON(slots > MAX_SLOTS); | |
1347 | ||
1348 | ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &first_bar); | |
1349 | if (ret) | |
1350 | return ret; | |
1351 | ||
1352 | first_bar &= PCI_SLOT_INFO_FIRST_BAR_MASK; | |
1353 | ||
1354 | if (first_bar > 5) { | |
1355 | dev_err(&pdev->dev, "Invalid first BAR. Aborting.\n"); | |
1356 | return -ENODEV; | |
1357 | } | |
1358 | ||
1359 | ret = pci_enable_device(pdev); | |
1360 | if (ret) | |
1361 | return ret; | |
1362 | ||
1363 | chip = kzalloc(sizeof(struct sdhci_pci_chip), GFP_KERNEL); | |
1364 | if (!chip) { | |
1365 | ret = -ENOMEM; | |
1366 | goto err; | |
1367 | } | |
1368 | ||
1369 | chip->pdev = pdev; | |
b177bc91 | 1370 | chip->fixes = (const struct sdhci_pci_fixes *)ent->driver_data; |
c43fd774 | 1371 | if (chip->fixes) { |
22606405 | 1372 | chip->quirks = chip->fixes->quirks; |
f3c55a7b | 1373 | chip->quirks2 = chip->fixes->quirks2; |
c43fd774 AH |
1374 | chip->allow_runtime_pm = chip->fixes->allow_runtime_pm; |
1375 | } | |
b8c86fc5 PO |
1376 | chip->num_slots = slots; |
1377 | ||
1378 | pci_set_drvdata(pdev, chip); | |
1379 | ||
22606405 PO |
1380 | if (chip->fixes && chip->fixes->probe) { |
1381 | ret = chip->fixes->probe(chip); | |
1382 | if (ret) | |
1383 | goto free; | |
1384 | } | |
1385 | ||
225d85fe AC |
1386 | slots = chip->num_slots; /* Quirk may have changed this */ |
1387 | ||
e6039832 AS |
1388 | pci_enable_msi(pdev); |
1389 | ||
b177bc91 | 1390 | for (i = 0; i < slots; i++) { |
52c506f0 | 1391 | slot = sdhci_pci_probe_slot(pdev, chip, first_bar, i); |
b8c86fc5 | 1392 | if (IS_ERR(slot)) { |
b177bc91 | 1393 | for (i--; i >= 0; i--) |
b8c86fc5 PO |
1394 | sdhci_pci_remove_slot(chip->slots[i]); |
1395 | ret = PTR_ERR(slot); | |
1396 | goto free; | |
1397 | } | |
1398 | ||
1399 | chip->slots[i] = slot; | |
1400 | } | |
1401 | ||
c43fd774 AH |
1402 | if (chip->allow_runtime_pm) |
1403 | sdhci_pci_runtime_pm_allow(&pdev->dev); | |
66fd8ad5 | 1404 | |
b8c86fc5 PO |
1405 | return 0; |
1406 | ||
1407 | free: | |
e6039832 AS |
1408 | pci_disable_msi(pdev); |
1409 | ||
b8c86fc5 PO |
1410 | pci_set_drvdata(pdev, NULL); |
1411 | kfree(chip); | |
1412 | ||
1413 | err: | |
1414 | pci_disable_device(pdev); | |
1415 | return ret; | |
1416 | } | |
1417 | ||
1418 | static void __devexit sdhci_pci_remove(struct pci_dev *pdev) | |
1419 | { | |
1420 | int i; | |
1421 | struct sdhci_pci_chip *chip; | |
1422 | ||
1423 | chip = pci_get_drvdata(pdev); | |
1424 | ||
1425 | if (chip) { | |
c43fd774 AH |
1426 | if (chip->allow_runtime_pm) |
1427 | sdhci_pci_runtime_pm_forbid(&pdev->dev); | |
1428 | ||
b177bc91 | 1429 | for (i = 0; i < chip->num_slots; i++) |
b8c86fc5 PO |
1430 | sdhci_pci_remove_slot(chip->slots[i]); |
1431 | ||
e6039832 AS |
1432 | pci_disable_msi(pdev); |
1433 | ||
b8c86fc5 PO |
1434 | pci_set_drvdata(pdev, NULL); |
1435 | kfree(chip); | |
1436 | } | |
1437 | ||
1438 | pci_disable_device(pdev); | |
1439 | } | |
1440 | ||
1441 | static struct pci_driver sdhci_driver = { | |
b177bc91 | 1442 | .name = "sdhci-pci", |
b8c86fc5 | 1443 | .id_table = pci_ids, |
b177bc91 | 1444 | .probe = sdhci_pci_probe, |
b8c86fc5 | 1445 | .remove = __devexit_p(sdhci_pci_remove), |
66fd8ad5 AH |
1446 | .driver = { |
1447 | .pm = &sdhci_pci_pm_ops | |
1448 | }, | |
b8c86fc5 PO |
1449 | }; |
1450 | ||
1451 | /*****************************************************************************\ | |
1452 | * * | |
1453 | * Driver init/exit * | |
1454 | * * | |
1455 | \*****************************************************************************/ | |
1456 | ||
1457 | static int __init sdhci_drv_init(void) | |
1458 | { | |
1459 | return pci_register_driver(&sdhci_driver); | |
1460 | } | |
1461 | ||
1462 | static void __exit sdhci_drv_exit(void) | |
1463 | { | |
1464 | pci_unregister_driver(&sdhci_driver); | |
1465 | } | |
1466 | ||
1467 | module_init(sdhci_drv_init); | |
1468 | module_exit(sdhci_drv_exit); | |
1469 | ||
32710e8f | 1470 | MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>"); |
b8c86fc5 PO |
1471 | MODULE_DESCRIPTION("Secure Digital Host Controller Interface PCI driver"); |
1472 | MODULE_LICENSE("GPL"); |