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mmc: sdhci-pci: add runtime pm support
[mirror_ubuntu-zesty-kernel.git] / drivers / mmc / host / sdhci-pci.c
CommitLineData
b8c86fc5
PO		 1/* linux/drivers/mmc/host/sdhci-pci.c - SDHCI on PCI bus interface
2 *
3 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or (at
8 * your option) any later version.
9 *
10 * Thanks to the following companies for their support:
11 *
12 * - JMicron (hardware and technical support)
13 */
14
15#include <linux/delay.h>
16#include <linux/highmem.h>
88b47679 17#include <linux/module.h>
b8c86fc5
PO		 18#include <linux/pci.h>
19#include <linux/dma-mapping.h>
5a0e3ad6 20#include <linux/slab.h>
ccc92c23 21#include <linux/device.h>
b8c86fc5 22#include <linux/mmc/host.h>
b177bc91
AP		 23#include <linux/scatterlist.h>
24#include <linux/io.h>
0f201655
AH		 25#include <linux/gpio.h>
26#include <linux/sfi.h>
66fd8ad5 27#include <linux/pm_runtime.h>
b8c86fc5
PO		 28
29#include "sdhci.h"
30
31/*
32 * PCI registers
33 */
34
35#define PCI_SDHCI_IFPIO 0x00
36#define PCI_SDHCI_IFDMA 0x01
37#define PCI_SDHCI_IFVENDOR 0x02
38
39#define PCI_SLOT_INFO 0x40 /* 8 bits */
40#define PCI_SLOT_INFO_SLOTS(x) ((x >> 4) & 7)
41#define PCI_SLOT_INFO_FIRST_BAR_MASK 0x07
42
43#define MAX_SLOTS 8
44
22606405 45struct sdhci_pci_chip;
4489428a 46struct sdhci_pci_slot;
22606405
PO		 47
48struct sdhci_pci_fixes {
49 unsigned int quirks;
50
b177bc91 51 int (*probe) (struct sdhci_pci_chip *);
45211e21 52
b177bc91
AP		 53 int (*probe_slot) (struct sdhci_pci_slot *);
54 void (*remove_slot) (struct sdhci_pci_slot *, int);
4489428a 55
b177bc91 56 int (*suspend) (struct sdhci_pci_chip *,
4489428a 57 pm_message_t);
b177bc91 58 int (*resume) (struct sdhci_pci_chip *);
22606405
PO		 59};
60
61struct sdhci_pci_slot {
62 struct sdhci_pci_chip *chip;
63 struct sdhci_host *host;
b8c86fc5 64
22606405 65 int pci_bar;
0f201655 66 int rst_n_gpio;
66fd8ad5
AH		 67 int cd_gpio;
68 int cd_irq;
22606405
PO		 69};
70
71struct sdhci_pci_chip {
72 struct pci_dev *pdev;
73
74 unsigned int quirks;
75 const struct sdhci_pci_fixes *fixes;
76
77 int num_slots; /* Slots on controller */
78 struct sdhci_pci_slot *slots[MAX_SLOTS]; /* Pointers to host slots */
79};
80
81
82/*****************************************************************************\
83 * *
84 * Hardware specific quirk handling *
85 * *
86\*****************************************************************************/
87
88static int ricoh_probe(struct sdhci_pci_chip *chip)
89{
c99436fb
CB		 90 if (chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG ||
91 chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SONY)
22606405 92 chip->quirks |= SDHCI_QUIRK_NO_CARD_NO_RESET;
ccc92c23
ML		 93 return 0;
94}
95
96static int ricoh_mmc_probe_slot(struct sdhci_pci_slot *slot)
97{
98 slot->host->caps =
99 ((0x21 << SDHCI_TIMEOUT_CLK_SHIFT)
100 & SDHCI_TIMEOUT_CLK_MASK) |
22606405 101
ccc92c23
ML		 102 ((0x21 << SDHCI_CLOCK_BASE_SHIFT)
103 & SDHCI_CLOCK_BASE_MASK) |
104
105 SDHCI_TIMEOUT_CLK_UNIT |
106 SDHCI_CAN_VDD_330 |
107 SDHCI_CAN_DO_SDMA;
108 return 0;
109}
110
111static int ricoh_mmc_resume(struct sdhci_pci_chip *chip)
112{
113 /* Apply a delay to allow controller to settle */
114 /* Otherwise it becomes confused if card state changed
115 during suspend */
116 msleep(500);
22606405
PO		 117 return 0;
118}
119
120static const struct sdhci_pci_fixes sdhci_ricoh = {
121 .probe = ricoh_probe,
84938294
VK		 122 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR |
123 SDHCI_QUIRK_FORCE_DMA |
124 SDHCI_QUIRK_CLOCK_BEFORE_RESET,
22606405
PO		 125};
126
ccc92c23
ML		 127static const struct sdhci_pci_fixes sdhci_ricoh_mmc = {
128 .probe_slot = ricoh_mmc_probe_slot,
129 .resume = ricoh_mmc_resume,
130 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR |
131 SDHCI_QUIRK_CLOCK_BEFORE_RESET |
132 SDHCI_QUIRK_NO_CARD_NO_RESET |
133 SDHCI_QUIRK_MISSING_CAPS
134};
135
22606405
PO		 136static const struct sdhci_pci_fixes sdhci_ene_712 = {
137 .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE |
138 SDHCI_QUIRK_BROKEN_DMA,
139};
140
141static const struct sdhci_pci_fixes sdhci_ene_714 = {
142 .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE |
143 SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS |
144 SDHCI_QUIRK_BROKEN_DMA,
145};
146
147static const struct sdhci_pci_fixes sdhci_cafe = {
148 .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER |
a0874897 149 SDHCI_QUIRK_NO_BUSY_IRQ |
ee53ab5d 150 SDHCI_QUIRK_BROKEN_TIMEOUT_VAL,
22606405
PO		 151};
152
68077b02
ML		 153static int mrst_hc_probe_slot(struct sdhci_pci_slot *slot)
154{
155 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA;
156 return 0;
157}
158
f9ee3eab
AC		 159/*
160 * ADMA operation is disabled for Moorestown platform due to
161 * hardware bugs.
162 */
35ac6f08 163static int mrst_hc_probe(struct sdhci_pci_chip *chip)
f9ee3eab
AC		 164{
165 /*
35ac6f08
JP		 166 * slots number is fixed here for MRST as SDIO3/5 are never used and
167 * have hardware bugs.
f9ee3eab
AC		 168 */
169 chip->num_slots = 1;
170 return 0;
171}
172
0f201655
AH		 173/* Medfield eMMC hardware reset GPIOs */
174static int mfd_emmc0_rst_gpio = -EINVAL;
175static int mfd_emmc1_rst_gpio = -EINVAL;
176
177static int mfd_emmc_gpio_parse(struct sfi_table_header *table)
178{
179 struct sfi_table_simple *sb = (struct sfi_table_simple *)table;
180 struct sfi_gpio_table_entry *entry;
181 int i, num;
182
183 num = SFI_GET_NUM_ENTRIES(sb, struct sfi_gpio_table_entry);
184 entry = (struct sfi_gpio_table_entry *)sb->pentry;
185
186 for (i = 0; i < num; i++, entry++) {
187 if (!strncmp(entry->pin_name, "emmc0_rst", SFI_NAME_LEN))
188 mfd_emmc0_rst_gpio = entry->pin_no;
189 else if (!strncmp(entry->pin_name, "emmc1_rst", SFI_NAME_LEN))
190 mfd_emmc1_rst_gpio = entry->pin_no;
191 }
192
193 return 0;
194}
195
66fd8ad5
AH		 196#ifdef CONFIG_PM_RUNTIME
197
198static irqreturn_t mfd_sd_cd(int irq, void *dev_id)
199{
200 struct sdhci_pci_slot *slot = dev_id;
201 struct sdhci_host *host = slot->host;
202
203 mmc_detect_change(host->mmc, msecs_to_jiffies(200));
204 return IRQ_HANDLED;
205}
206
207#define MFLD_SD_CD_PIN 69
208
209static int mfd_sd_probe_slot(struct sdhci_pci_slot *slot)
210{
211 int err, irq, gpio = MFLD_SD_CD_PIN;
212
213 slot->cd_gpio = -EINVAL;
214 slot->cd_irq = -EINVAL;
215
216 err = gpio_request(gpio, "sd_cd");
217 if (err < 0)
218 goto out;
219
220 err = gpio_direction_input(gpio);
221 if (err < 0)
222 goto out_free;
223
224 irq = gpio_to_irq(gpio);
225 if (irq < 0)
226 goto out_free;
227
228 err = request_irq(irq, mfd_sd_cd, IRQF_TRIGGER_RISING |
229 IRQF_TRIGGER_FALLING, "sd_cd", slot);
230 if (err)
231 goto out_free;
232
233 slot->cd_gpio = gpio;
234 slot->cd_irq = irq;
235 slot->host->quirks2 |= SDHCI_QUIRK2_OWN_CARD_DETECTION;
236
237 return 0;
238
239out_free:
240 gpio_free(gpio);
241out:
242 dev_warn(&slot->chip->pdev->dev, "failed to setup card detect wake up\n");
243 return 0;
244}
245
246static void mfd_sd_remove_slot(struct sdhci_pci_slot *slot, int dead)
247{
248 if (slot->cd_irq >= 0)
249 free_irq(slot->cd_irq, slot);
250 gpio_free(slot->cd_gpio);
251}
252
253#else
254
255#define mfd_sd_probe_slot NULL
256#define mfd_sd_remove_slot NULL
257
258#endif
259
0d013bcf
AH		 260static int mfd_emmc_probe_slot(struct sdhci_pci_slot *slot)
261{
0f201655
AH		 262 const char *name = NULL;
263 int gpio = -EINVAL;
264
265 sfi_table_parse(SFI_SIG_GPIO, NULL, NULL, mfd_emmc_gpio_parse);
266
267 switch (slot->chip->pdev->device) {
268 case PCI_DEVICE_ID_INTEL_MFD_EMMC0:
269 gpio = mfd_emmc0_rst_gpio;
270 name = "eMMC0_reset";
271 break;
272 case PCI_DEVICE_ID_INTEL_MFD_EMMC1:
273 gpio = mfd_emmc1_rst_gpio;
274 name = "eMMC1_reset";
275 break;
276 }
277
278 if (!gpio_request(gpio, name)) {
279 gpio_direction_output(gpio, 1);
280 slot->rst_n_gpio = gpio;
281 slot->host->mmc->caps |= MMC_CAP_HW_RESET;
282 }
283
66fd8ad5 284 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE;
0f201655 285
f7c56ef2
AH		 286 slot->host->mmc->caps2 = MMC_CAP2_BOOTPART_NOACC;
287
0d013bcf
AH		 288 return 0;
289}
290
0f201655
AH		 291static void mfd_emmc_remove_slot(struct sdhci_pci_slot *slot, int dead)
292{
293 gpio_free(slot->rst_n_gpio);
294}
295
f9ee3eab
AC		 296static const struct sdhci_pci_fixes sdhci_intel_mrst_hc0 = {
297 .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT,
68077b02 298 .probe_slot = mrst_hc_probe_slot,
f9ee3eab
AC		 299};
300
35ac6f08 301static const struct sdhci_pci_fixes sdhci_intel_mrst_hc1_hc2 = {
f9ee3eab 302 .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT,
35ac6f08 303 .probe = mrst_hc_probe,
f9ee3eab
AC		 304};
305
29229052
XS		 306static const struct sdhci_pci_fixes sdhci_intel_mfd_sd = {
307 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
66fd8ad5
AH		 308 .probe_slot = mfd_sd_probe_slot,
309 .remove_slot = mfd_sd_remove_slot,
29229052
XS		 310};
311
0d013bcf
AH		 312static const struct sdhci_pci_fixes sdhci_intel_mfd_sdio = {
313 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
314};
315
316static const struct sdhci_pci_fixes sdhci_intel_mfd_emmc = {
29229052 317 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
0d013bcf 318 .probe_slot = mfd_emmc_probe_slot,
0f201655 319 .remove_slot = mfd_emmc_remove_slot,
29229052
XS		 320};
321
26daa1ed
JL		 322/* O2Micro extra registers */
323#define O2_SD_LOCK_WP 0xD3
324#define O2_SD_MULTI_VCC3V 0xEE
325#define O2_SD_CLKREQ 0xEC
326#define O2_SD_CAPS 0xE0
327#define O2_SD_ADMA1 0xE2
328#define O2_SD_ADMA2 0xE7
329#define O2_SD_INF_MOD 0xF1
330
331static int o2_probe(struct sdhci_pci_chip *chip)
332{
333 int ret;
334 u8 scratch;
335
336 switch (chip->pdev->device) {
337 case PCI_DEVICE_ID_O2_8220:
338 case PCI_DEVICE_ID_O2_8221:
339 case PCI_DEVICE_ID_O2_8320:
340 case PCI_DEVICE_ID_O2_8321:
341 /* This extra setup is required due to broken ADMA. */
342 ret = pci_read_config_byte(chip->pdev, O2_SD_LOCK_WP, &scratch);
343 if (ret)
344 return ret;
345 scratch &= 0x7f;
346 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
347
348 /* Set Multi 3 to VCC3V# */
349 pci_write_config_byte(chip->pdev, O2_SD_MULTI_VCC3V, 0x08);
350
351 /* Disable CLK_REQ# support after media DET */
352 ret = pci_read_config_byte(chip->pdev, O2_SD_CLKREQ, &scratch);
353 if (ret)
354 return ret;
355 scratch |= 0x20;
356 pci_write_config_byte(chip->pdev, O2_SD_CLKREQ, scratch);
357
358 /* Choose capabilities, enable SDMA. We have to write 0x01
359 * to the capabilities register first to unlock it.
360 */
361 ret = pci_read_config_byte(chip->pdev, O2_SD_CAPS, &scratch);
362 if (ret)
363 return ret;
364 scratch |= 0x01;
365 pci_write_config_byte(chip->pdev, O2_SD_CAPS, scratch);
366 pci_write_config_byte(chip->pdev, O2_SD_CAPS, 0x73);
367
368 /* Disable ADMA1/2 */
369 pci_write_config_byte(chip->pdev, O2_SD_ADMA1, 0x39);
370 pci_write_config_byte(chip->pdev, O2_SD_ADMA2, 0x08);
371
372 /* Disable the infinite transfer mode */
373 ret = pci_read_config_byte(chip->pdev, O2_SD_INF_MOD, &scratch);
374 if (ret)
375 return ret;
376 scratch |= 0x08;
377 pci_write_config_byte(chip->pdev, O2_SD_INF_MOD, scratch);
378
379 /* Lock WP */
380 ret = pci_read_config_byte(chip->pdev, O2_SD_LOCK_WP, &scratch);
381 if (ret)
382 return ret;
383 scratch |= 0x80;
384 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
385 }
386
387 return 0;
388}
389
45211e21
PO		 390static int jmicron_pmos(struct sdhci_pci_chip *chip, int on)
391{
392 u8 scratch;
393 int ret;
394
395 ret = pci_read_config_byte(chip->pdev, 0xAE, &scratch);
396 if (ret)
397 return ret;
398
399 /*
400 * Turn PMOS on [bit 0], set over current detection to 2.4 V
401 * [bit 1:2] and enable over current debouncing [bit 6].
402 */
403 if (on)
404 scratch |= 0x47;
405 else
406 scratch &= ~0x47;
407
408 ret = pci_write_config_byte(chip->pdev, 0xAE, scratch);
409 if (ret)
410 return ret;
411
412 return 0;
413}
414
415static int jmicron_probe(struct sdhci_pci_chip *chip)
416{
417 int ret;
8f230f45 418 u16 mmcdev = 0;
45211e21 419
93fc48c7
PO		 420 if (chip->pdev->revision == 0) {
421 chip->quirks |= SDHCI_QUIRK_32BIT_DMA_ADDR |
422 SDHCI_QUIRK_32BIT_DMA_SIZE |
2134a922 423 SDHCI_QUIRK_32BIT_ADMA_SIZE |
4a3cba32 424 SDHCI_QUIRK_RESET_AFTER_REQUEST |
86a6a874 425 SDHCI_QUIRK_BROKEN_SMALL_PIO;
93fc48c7
PO		 426 }
427
4489428a
PO		 428 /*
429 * JMicron chips can have two interfaces to the same hardware
430 * in order to work around limitations in Microsoft's driver.
431 * We need to make sure we only bind to one of them.
432 *
433 * This code assumes two things:
434 *
435 * 1. The PCI code adds subfunctions in order.
436 *
437 * 2. The MMC interface has a lower subfunction number
438 * than the SD interface.
439 */
8f230f45
TI		 440 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_SD)
441 mmcdev = PCI_DEVICE_ID_JMICRON_JMB38X_MMC;
442 else if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD)
443 mmcdev = PCI_DEVICE_ID_JMICRON_JMB388_ESD;
444
445 if (mmcdev) {
4489428a
PO		 446 struct pci_dev *sd_dev;
447
448 sd_dev = NULL;
449 while ((sd_dev = pci_get_device(PCI_VENDOR_ID_JMICRON,
8f230f45 450 mmcdev, sd_dev)) != NULL) {
4489428a
PO		 451 if ((PCI_SLOT(chip->pdev->devfn) ==
452 PCI_SLOT(sd_dev->devfn)) &&
453 (chip->pdev->bus == sd_dev->bus))
454 break;
455 }
456
457 if (sd_dev) {
458 pci_dev_put(sd_dev);
459 dev_info(&chip->pdev->dev, "Refusing to bind to "
460 "secondary interface.\n");
461 return -ENODEV;
462 }
463 }
464
45211e21
PO		 465 /*
466 * JMicron chips need a bit of a nudge to enable the power
467 * output pins.
468 */
469 ret = jmicron_pmos(chip, 1);
470 if (ret) {
471 dev_err(&chip->pdev->dev, "Failure enabling card power\n");
472 return ret;
473 }
474
82b0e23a
TI		 475 /* quirk for unsable RO-detection on JM388 chips */
476 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD ||
477 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD)
478 chip->quirks |= SDHCI_QUIRK_UNSTABLE_RO_DETECT;
479
45211e21
PO		 480 return 0;
481}
482
4489428a
PO		 483static void jmicron_enable_mmc(struct sdhci_host *host, int on)
484{
485 u8 scratch;
486
487 scratch = readb(host->ioaddr + 0xC0);
488
489 if (on)
490 scratch |= 0x01;
491 else
492 scratch &= ~0x01;
493
494 writeb(scratch, host->ioaddr + 0xC0);
495}
496
497static int jmicron_probe_slot(struct sdhci_pci_slot *slot)
498{
2134a922
PO		 499 if (slot->chip->pdev->revision == 0) {
500 u16 version;
501
502 version = readl(slot->host->ioaddr + SDHCI_HOST_VERSION);
503 version = (version & SDHCI_VENDOR_VER_MASK) >>
504 SDHCI_VENDOR_VER_SHIFT;
505
506 /*
507 * Older versions of the chip have lots of nasty glitches
508 * in the ADMA engine. It's best just to avoid it
509 * completely.
510 */
511 if (version < 0xAC)
512 slot->host->quirks |= SDHCI_QUIRK_BROKEN_ADMA;
513 }
514
8f230f45
TI		 515 /* JM388 MMC doesn't support 1.8V while SD supports it */
516 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) {
517 slot->host->ocr_avail_sd = MMC_VDD_32_33 | MMC_VDD_33_34 |
518 MMC_VDD_29_30 | MMC_VDD_30_31 |
519 MMC_VDD_165_195; /* allow 1.8V */
520 slot->host->ocr_avail_mmc = MMC_VDD_32_33 | MMC_VDD_33_34 |
521 MMC_VDD_29_30 | MMC_VDD_30_31; /* no 1.8V for MMC */
522 }
523
4489428a
PO		 524 /*
525 * The secondary interface requires a bit set to get the
526 * interrupts.
527 */
8f230f45
TI		 528 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
529 slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD)
4489428a
PO		 530 jmicron_enable_mmc(slot->host, 1);
531
d75c1084
TI		 532 slot->host->mmc->caps |= MMC_CAP_BUS_WIDTH_TEST;
533
4489428a
PO		 534 return 0;
535}
536
1e72859e 537static void jmicron_remove_slot(struct sdhci_pci_slot *slot, int dead)
4489428a 538{
1e72859e
PO		 539 if (dead)
540 return;
541
8f230f45
TI		 542 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
543 slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD)
4489428a
PO		 544 jmicron_enable_mmc(slot->host, 0);
545}
546
547static int jmicron_suspend(struct sdhci_pci_chip *chip, pm_message_t state)
548{
549 int i;
550
8f230f45
TI		 551 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
552 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) {
b177bc91 553 for (i = 0; i < chip->num_slots; i++)
4489428a
PO		 554 jmicron_enable_mmc(chip->slots[i]->host, 0);
555 }
556
557 return 0;
558}
559
45211e21
PO		 560static int jmicron_resume(struct sdhci_pci_chip *chip)
561{
4489428a
PO		 562 int ret, i;
563
8f230f45
TI		 564 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
565 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) {
b177bc91 566 for (i = 0; i < chip->num_slots; i++)
4489428a
PO		 567 jmicron_enable_mmc(chip->slots[i]->host, 1);
568 }
45211e21
PO		 569
570 ret = jmicron_pmos(chip, 1);
571 if (ret) {
572 dev_err(&chip->pdev->dev, "Failure enabling card power\n");
573 return ret;
574 }
575
576 return 0;
577}
578
26daa1ed
JL		 579static const struct sdhci_pci_fixes sdhci_o2 = {
580 .probe = o2_probe,
581};
582
22606405 583static const struct sdhci_pci_fixes sdhci_jmicron = {
45211e21
PO		 584 .probe = jmicron_probe,
585
4489428a
PO		 586 .probe_slot = jmicron_probe_slot,
587 .remove_slot = jmicron_remove_slot,
588
589 .suspend = jmicron_suspend,
45211e21 590 .resume = jmicron_resume,
22606405
PO		 591};
592
a7a6186c
NP		 593/* SysKonnect CardBus2SDIO extra registers */
594#define SYSKT_CTRL 0x200
595#define SYSKT_RDFIFO_STAT 0x204
596#define SYSKT_WRFIFO_STAT 0x208
597#define SYSKT_POWER_DATA 0x20c
598#define SYSKT_POWER_330 0xef
599#define SYSKT_POWER_300 0xf8
600#define SYSKT_POWER_184 0xcc
601#define SYSKT_POWER_CMD 0x20d
602#define SYSKT_POWER_START (1 << 7)
603#define SYSKT_POWER_STATUS 0x20e
604#define SYSKT_POWER_STATUS_OK (1 << 0)
605#define SYSKT_BOARD_REV 0x210
606#define SYSKT_CHIP_REV 0x211
607#define SYSKT_CONF_DATA 0x212
608#define SYSKT_CONF_DATA_1V8 (1 << 2)
609#define SYSKT_CONF_DATA_2V5 (1 << 1)
610#define SYSKT_CONF_DATA_3V3 (1 << 0)
611
612static int syskt_probe(struct sdhci_pci_chip *chip)
613{
614 if ((chip->pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) {
615 chip->pdev->class &= ~0x0000FF;
616 chip->pdev->class |= PCI_SDHCI_IFDMA;
617 }
618 return 0;
619}
620
621static int syskt_probe_slot(struct sdhci_pci_slot *slot)
622{
623 int tm, ps;
624
625 u8 board_rev = readb(slot->host->ioaddr + SYSKT_BOARD_REV);
626 u8 chip_rev = readb(slot->host->ioaddr + SYSKT_CHIP_REV);
627 dev_info(&slot->chip->pdev->dev, "SysKonnect CardBus2SDIO, "
628 "board rev %d.%d, chip rev %d.%d\n",
629 board_rev >> 4, board_rev & 0xf,
630 chip_rev >> 4, chip_rev & 0xf);
631 if (chip_rev >= 0x20)
632 slot->host->quirks |= SDHCI_QUIRK_FORCE_DMA;
633
634 writeb(SYSKT_POWER_330, slot->host->ioaddr + SYSKT_POWER_DATA);
635 writeb(SYSKT_POWER_START, slot->host->ioaddr + SYSKT_POWER_CMD);
636 udelay(50);
637 tm = 10; /* Wait max 1 ms */
638 do {
639 ps = readw(slot->host->ioaddr + SYSKT_POWER_STATUS);
640 if (ps & SYSKT_POWER_STATUS_OK)
641 break;
642 udelay(100);
643 } while (--tm);
644 if (!tm) {
645 dev_err(&slot->chip->pdev->dev,
646 "power regulator never stabilized");
647 writeb(0, slot->host->ioaddr + SYSKT_POWER_CMD);
648 return -ENODEV;
649 }
650
651 return 0;
652}
653
654static const struct sdhci_pci_fixes sdhci_syskt = {
655 .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER,
656 .probe = syskt_probe,
657 .probe_slot = syskt_probe_slot,
658};
659
557b0697
HW		 660static int via_probe(struct sdhci_pci_chip *chip)
661{
662 if (chip->pdev->revision == 0x10)
663 chip->quirks |= SDHCI_QUIRK_DELAY_AFTER_POWER;
664
665 return 0;
666}
667
668static const struct sdhci_pci_fixes sdhci_via = {
669 .probe = via_probe,
670};
671
22606405 672static const struct pci_device_id pci_ids[] __devinitdata = {
b8c86fc5
PO		 673 {
674 .vendor = PCI_VENDOR_ID_RICOH,
675 .device = PCI_DEVICE_ID_RICOH_R5C822,
22606405 676 .subvendor = PCI_ANY_ID,
b8c86fc5 677 .subdevice = PCI_ANY_ID,
22606405 678 .driver_data = (kernel_ulong_t)&sdhci_ricoh,
b8c86fc5
PO		 679 },
680
ccc92c23
ML		 681 {
682 .vendor = PCI_VENDOR_ID_RICOH,
683 .device = 0x843,
684 .subvendor = PCI_ANY_ID,
685 .subdevice = PCI_ANY_ID,
686 .driver_data = (kernel_ulong_t)&sdhci_ricoh_mmc,
687 },
688
568133eb
PC		 689 {
690 .vendor = PCI_VENDOR_ID_RICOH,
691 .device = 0xe822,
692 .subvendor = PCI_ANY_ID,
693 .subdevice = PCI_ANY_ID,
694 .driver_data = (kernel_ulong_t)&sdhci_ricoh_mmc,
695 },
696
5fd11c07
MI		 697 {
698 .vendor = PCI_VENDOR_ID_RICOH,
699 .device = 0xe823,
700 .subvendor = PCI_ANY_ID,
701 .subdevice = PCI_ANY_ID,
702 .driver_data = (kernel_ulong_t)&sdhci_ricoh_mmc,
703 },
704
b8c86fc5
PO		 705 {
706 .vendor = PCI_VENDOR_ID_ENE,
707 .device = PCI_DEVICE_ID_ENE_CB712_SD,
708 .subvendor = PCI_ANY_ID,
709 .subdevice = PCI_ANY_ID,
22606405 710 .driver_data = (kernel_ulong_t)&sdhci_ene_712,
b8c86fc5
PO		 711 },
712
713 {
714 .vendor = PCI_VENDOR_ID_ENE,
715 .device = PCI_DEVICE_ID_ENE_CB712_SD_2,
716 .subvendor = PCI_ANY_ID,
717 .subdevice = PCI_ANY_ID,
22606405 718 .driver_data = (kernel_ulong_t)&sdhci_ene_712,
b8c86fc5
PO		 719 },
720
721 {
722 .vendor = PCI_VENDOR_ID_ENE,
723 .device = PCI_DEVICE_ID_ENE_CB714_SD,
724 .subvendor = PCI_ANY_ID,
725 .subdevice = PCI_ANY_ID,
22606405 726 .driver_data = (kernel_ulong_t)&sdhci_ene_714,
b8c86fc5
PO		 727 },
728
729 {
730 .vendor = PCI_VENDOR_ID_ENE,
731 .device = PCI_DEVICE_ID_ENE_CB714_SD_2,
732 .subvendor = PCI_ANY_ID,
733 .subdevice = PCI_ANY_ID,
22606405 734 .driver_data = (kernel_ulong_t)&sdhci_ene_714,
b8c86fc5
PO		 735 },
736
737 {
738 .vendor = PCI_VENDOR_ID_MARVELL,
8c5eb880 739 .device = PCI_DEVICE_ID_MARVELL_88ALP01_SD,
b8c86fc5
PO		 740 .subvendor = PCI_ANY_ID,
741 .subdevice = PCI_ANY_ID,
22606405 742 .driver_data = (kernel_ulong_t)&sdhci_cafe,
b8c86fc5
PO		 743 },
744
745 {
746 .vendor = PCI_VENDOR_ID_JMICRON,
747 .device = PCI_DEVICE_ID_JMICRON_JMB38X_SD,
748 .subvendor = PCI_ANY_ID,
749 .subdevice = PCI_ANY_ID,
22606405 750 .driver_data = (kernel_ulong_t)&sdhci_jmicron,
b8c86fc5
PO		 751 },
752
4489428a
PO		 753 {
754 .vendor = PCI_VENDOR_ID_JMICRON,
755 .device = PCI_DEVICE_ID_JMICRON_JMB38X_MMC,
756 .subvendor = PCI_ANY_ID,
757 .subdevice = PCI_ANY_ID,
758 .driver_data = (kernel_ulong_t)&sdhci_jmicron,
8f230f45
TI		 759 },
760
761 {
762 .vendor = PCI_VENDOR_ID_JMICRON,
763 .device = PCI_DEVICE_ID_JMICRON_JMB388_SD,
764 .subvendor = PCI_ANY_ID,
765 .subdevice = PCI_ANY_ID,
766 .driver_data = (kernel_ulong_t)&sdhci_jmicron,
767 },
768
769 {
770 .vendor = PCI_VENDOR_ID_JMICRON,
771 .device = PCI_DEVICE_ID_JMICRON_JMB388_ESD,
772 .subvendor = PCI_ANY_ID,
773 .subdevice = PCI_ANY_ID,
774 .driver_data = (kernel_ulong_t)&sdhci_jmicron,
4489428a
PO		 775 },
776
a7a6186c
NP		 777 {
778 .vendor = PCI_VENDOR_ID_SYSKONNECT,
779 .device = 0x8000,
780 .subvendor = PCI_ANY_ID,
781 .subdevice = PCI_ANY_ID,
782 .driver_data = (kernel_ulong_t)&sdhci_syskt,
783 },
784
557b0697
HW		 785 {
786 .vendor = PCI_VENDOR_ID_VIA,
787 .device = 0x95d0,
788 .subvendor = PCI_ANY_ID,
789 .subdevice = PCI_ANY_ID,
790 .driver_data = (kernel_ulong_t)&sdhci_via,
791 },
792
29229052
XS		 793 {
794 .vendor = PCI_VENDOR_ID_INTEL,
f9ee3eab
AC		 795 .device = PCI_DEVICE_ID_INTEL_MRST_SD0,
796 .subvendor = PCI_ANY_ID,
797 .subdevice = PCI_ANY_ID,
798 .driver_data = (kernel_ulong_t)&sdhci_intel_mrst_hc0,
799 },
800
801 {
802 .vendor = PCI_VENDOR_ID_INTEL,
803 .device = PCI_DEVICE_ID_INTEL_MRST_SD1,
804 .subvendor = PCI_ANY_ID,
805 .subdevice = PCI_ANY_ID,
35ac6f08
JP		 806 .driver_data = (kernel_ulong_t)&sdhci_intel_mrst_hc1_hc2,
807 },
808
809 {
810 .vendor = PCI_VENDOR_ID_INTEL,
811 .device = PCI_DEVICE_ID_INTEL_MRST_SD2,
812 .subvendor = PCI_ANY_ID,
813 .subdevice = PCI_ANY_ID,
814 .driver_data = (kernel_ulong_t)&sdhci_intel_mrst_hc1_hc2,
f9ee3eab
AC		 815 },
816
817 {
818 .vendor = PCI_VENDOR_ID_INTEL,
29229052
XS		 819 .device = PCI_DEVICE_ID_INTEL_MFD_SD,
820 .subvendor = PCI_ANY_ID,
821 .subdevice = PCI_ANY_ID,
822 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sd,
823 },
824
825 {
826 .vendor = PCI_VENDOR_ID_INTEL,
827 .device = PCI_DEVICE_ID_INTEL_MFD_SDIO1,
828 .subvendor = PCI_ANY_ID,
829 .subdevice = PCI_ANY_ID,
0d013bcf 830 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sdio,
29229052
XS		 831 },
832
833 {
834 .vendor = PCI_VENDOR_ID_INTEL,
835 .device = PCI_DEVICE_ID_INTEL_MFD_SDIO2,
836 .subvendor = PCI_ANY_ID,
837 .subdevice = PCI_ANY_ID,
0d013bcf 838 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sdio,
29229052
XS		 839 },
840
841 {
842 .vendor = PCI_VENDOR_ID_INTEL,
843 .device = PCI_DEVICE_ID_INTEL_MFD_EMMC0,
844 .subvendor = PCI_ANY_ID,
845 .subdevice = PCI_ANY_ID,
0d013bcf 846 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc,
29229052
XS		 847 },
848
849 {
850 .vendor = PCI_VENDOR_ID_INTEL,
851 .device = PCI_DEVICE_ID_INTEL_MFD_EMMC1,
852 .subvendor = PCI_ANY_ID,
853 .subdevice = PCI_ANY_ID,
0d013bcf 854 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc,
29229052
XS		 855 },
856
26daa1ed
JL		 857 {
858 .vendor = PCI_VENDOR_ID_O2,
859 .device = PCI_DEVICE_ID_O2_8120,
860 .subvendor = PCI_ANY_ID,
861 .subdevice = PCI_ANY_ID,
862 .driver_data = (kernel_ulong_t)&sdhci_o2,
863 },
864
865 {
866 .vendor = PCI_VENDOR_ID_O2,
867 .device = PCI_DEVICE_ID_O2_8220,
868 .subvendor = PCI_ANY_ID,
869 .subdevice = PCI_ANY_ID,
870 .driver_data = (kernel_ulong_t)&sdhci_o2,
871 },
872
873 {
874 .vendor = PCI_VENDOR_ID_O2,
875 .device = PCI_DEVICE_ID_O2_8221,
876 .subvendor = PCI_ANY_ID,
877 .subdevice = PCI_ANY_ID,
878 .driver_data = (kernel_ulong_t)&sdhci_o2,
879 },
880
881 {
882 .vendor = PCI_VENDOR_ID_O2,
883 .device = PCI_DEVICE_ID_O2_8320,
884 .subvendor = PCI_ANY_ID,
885 .subdevice = PCI_ANY_ID,
886 .driver_data = (kernel_ulong_t)&sdhci_o2,
887 },
888
889 {
890 .vendor = PCI_VENDOR_ID_O2,
891 .device = PCI_DEVICE_ID_O2_8321,
892 .subvendor = PCI_ANY_ID,
893 .subdevice = PCI_ANY_ID,
894 .driver_data = (kernel_ulong_t)&sdhci_o2,
895 },
896
b8c86fc5
PO		 897 { /* Generic SD host controller */
898 PCI_DEVICE_CLASS((PCI_CLASS_SYSTEM_SDHCI << 8), 0xFFFF00)
899 },
900
901 { /* end: all zeroes */ },
902};
903
904MODULE_DEVICE_TABLE(pci, pci_ids);
905
b8c86fc5
PO		 906/*****************************************************************************\
907 * *
908 * SDHCI core callbacks *
909 * *
910\*****************************************************************************/
911
912static int sdhci_pci_enable_dma(struct sdhci_host *host)
913{
914 struct sdhci_pci_slot *slot;
915 struct pci_dev *pdev;
916 int ret;
917
918 slot = sdhci_priv(host);
919 pdev = slot->chip->pdev;
920
921 if (((pdev->class & 0xFFFF00) == (PCI_CLASS_SYSTEM_SDHCI << 8)) &&
922 ((pdev->class & 0x0000FF) != PCI_SDHCI_IFDMA) &&
a13abc7b 923 (host->flags & SDHCI_USE_SDMA)) {
b8c86fc5
PO		 924 dev_warn(&pdev->dev, "Will use DMA mode even though HW "
925 "doesn't fully claim to support it.\n");
926 }
927
284901a9 928 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
b8c86fc5
PO		 929 if (ret)
930 return ret;
931
932 pci_set_master(pdev);
933
934 return 0;
935}
936
68077b02
ML		 937static int sdhci_pci_8bit_width(struct sdhci_host *host, int width)
938{
939 u8 ctrl;
940
941 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
942
943 switch (width) {
944 case MMC_BUS_WIDTH_8:
945 ctrl |= SDHCI_CTRL_8BITBUS;
946 ctrl &= ~SDHCI_CTRL_4BITBUS;
947 break;
948 case MMC_BUS_WIDTH_4:
949 ctrl |= SDHCI_CTRL_4BITBUS;
950 ctrl &= ~SDHCI_CTRL_8BITBUS;
951 break;
952 default:
953 ctrl &= ~(SDHCI_CTRL_8BITBUS | SDHCI_CTRL_4BITBUS);
954 break;
955 }
956
957 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
958
959 return 0;
960}
961
0f201655
AH		 962static void sdhci_pci_hw_reset(struct sdhci_host *host)
963{
964 struct sdhci_pci_slot *slot = sdhci_priv(host);
965 int rst_n_gpio = slot->rst_n_gpio;
966
967 if (!gpio_is_valid(rst_n_gpio))
968 return;
969 gpio_set_value_cansleep(rst_n_gpio, 0);
970 /* For eMMC, minimum is 1us but give it 10us for good measure */
971 udelay(10);
972 gpio_set_value_cansleep(rst_n_gpio, 1);
973 /* For eMMC, minimum is 200us but give it 300us for good measure */
974 usleep_range(300, 1000);
975}
976
b8c86fc5
PO		 977static struct sdhci_ops sdhci_pci_ops = {
978 .enable_dma = sdhci_pci_enable_dma,
68077b02 979 .platform_8bit_width = sdhci_pci_8bit_width,
0f201655 980 .hw_reset = sdhci_pci_hw_reset,
b8c86fc5
PO		 981};
982
983/*****************************************************************************\
984 * *
985 * Suspend/resume *
986 * *
987\*****************************************************************************/
988
989#ifdef CONFIG_PM
990
b177bc91 991static int sdhci_pci_suspend(struct pci_dev *pdev, pm_message_t state)
b8c86fc5
PO		 992{
993 struct sdhci_pci_chip *chip;
994 struct sdhci_pci_slot *slot;
5f619704 995 mmc_pm_flag_t slot_pm_flags;
2f4cbb3d 996 mmc_pm_flag_t pm_flags = 0;
b8c86fc5
PO		 997 int i, ret;
998
999 chip = pci_get_drvdata(pdev);
1000 if (!chip)
1001 return 0;
1002
b177bc91 1003 for (i = 0; i < chip->num_slots; i++) {
b8c86fc5
PO		 1004 slot = chip->slots[i];
1005 if (!slot)
1006 continue;
1007
1008 ret = sdhci_suspend_host(slot->host, state);
1009
1010 if (ret) {
b177bc91 1011 for (i--; i >= 0; i--)
b8c86fc5
PO		 1012 sdhci_resume_host(chip->slots[i]->host);
1013 return ret;
1014 }
2f4cbb3d 1015
5f619704
DD		 1016 slot_pm_flags = slot->host->mmc->pm_flags;
1017 if (slot_pm_flags & MMC_PM_WAKE_SDIO_IRQ)
1018 sdhci_enable_irq_wakeups(slot->host);
1019
1020 pm_flags |= slot_pm_flags;
b8c86fc5
PO		 1021 }
1022
4489428a
PO		 1023 if (chip->fixes && chip->fixes->suspend) {
1024 ret = chip->fixes->suspend(chip, state);
1025 if (ret) {
b177bc91 1026 for (i = chip->num_slots - 1; i >= 0; i--)
4489428a
PO		 1027 sdhci_resume_host(chip->slots[i]->host);
1028 return ret;
1029 }
1030 }
1031
b8c86fc5 1032 pci_save_state(pdev);
2f4cbb3d 1033 if (pm_flags & MMC_PM_KEEP_POWER) {
5f619704
DD		 1034 if (pm_flags & MMC_PM_WAKE_SDIO_IRQ) {
1035 pci_pme_active(pdev, true);
2f4cbb3d 1036 pci_enable_wake(pdev, PCI_D3hot, 1);
5f619704 1037 }
2f4cbb3d
NP		 1038 pci_set_power_state(pdev, PCI_D3hot);
1039 } else {
1040 pci_enable_wake(pdev, pci_choose_state(pdev, state), 0);
1041 pci_disable_device(pdev);
1042 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1043 }
b8c86fc5
PO		 1044
1045 return 0;
1046}
1047
b177bc91 1048static int sdhci_pci_resume(struct pci_dev *pdev)
b8c86fc5
PO		 1049{
1050 struct sdhci_pci_chip *chip;
1051 struct sdhci_pci_slot *slot;
1052 int i, ret;
1053
1054 chip = pci_get_drvdata(pdev);
1055 if (!chip)
1056 return 0;
1057
1058 pci_set_power_state(pdev, PCI_D0);
1059 pci_restore_state(pdev);
1060 ret = pci_enable_device(pdev);
1061 if (ret)
1062 return ret;
1063
45211e21
PO		 1064 if (chip->fixes && chip->fixes->resume) {
1065 ret = chip->fixes->resume(chip);
1066 if (ret)
1067 return ret;
1068 }
1069
b177bc91 1070 for (i = 0; i < chip->num_slots; i++) {
b8c86fc5
PO		 1071 slot = chip->slots[i];
1072 if (!slot)
1073 continue;
1074
1075 ret = sdhci_resume_host(slot->host);
1076 if (ret)
1077 return ret;
1078 }
1079
1080 return 0;
1081}
1082
1083#else /* CONFIG_PM */
1084
1085#define sdhci_pci_suspend NULL
1086#define sdhci_pci_resume NULL
1087
1088#endif /* CONFIG_PM */
1089
66fd8ad5
AH		 1090#ifdef CONFIG_PM_RUNTIME
1091
1092static int sdhci_pci_runtime_suspend(struct device *dev)
1093{
1094 struct pci_dev *pdev = container_of(dev, struct pci_dev, dev);
1095 struct sdhci_pci_chip *chip;
1096 struct sdhci_pci_slot *slot;
1097 pm_message_t state = { .event = PM_EVENT_SUSPEND };
1098 int i, ret;
1099
1100 chip = pci_get_drvdata(pdev);
1101 if (!chip)
1102 return 0;
1103
1104 for (i = 0; i < chip->num_slots; i++) {
1105 slot = chip->slots[i];
1106 if (!slot)
1107 continue;
1108
1109 ret = sdhci_runtime_suspend_host(slot->host);
1110
1111 if (ret) {
1112 for (i--; i >= 0; i--)
1113 sdhci_runtime_resume_host(chip->slots[i]->host);
1114 return ret;
1115 }
1116 }
1117
1118 if (chip->fixes && chip->fixes->suspend) {
1119 ret = chip->fixes->suspend(chip, state);
1120 if (ret) {
1121 for (i = chip->num_slots - 1; i >= 0; i--)
1122 sdhci_runtime_resume_host(chip->slots[i]->host);
1123 return ret;
1124 }
1125 }
1126
1127 return 0;
1128}
1129
1130static int sdhci_pci_runtime_resume(struct device *dev)
1131{
1132 struct pci_dev *pdev = container_of(dev, struct pci_dev, dev);
1133 struct sdhci_pci_chip *chip;
1134 struct sdhci_pci_slot *slot;
1135 int i, ret;
1136
1137 chip = pci_get_drvdata(pdev);
1138 if (!chip)
1139 return 0;
1140
1141 if (chip->fixes && chip->fixes->resume) {
1142 ret = chip->fixes->resume(chip);
1143 if (ret)
1144 return ret;
1145 }
1146
1147 for (i = 0; i < chip->num_slots; i++) {
1148 slot = chip->slots[i];
1149 if (!slot)
1150 continue;
1151
1152 ret = sdhci_runtime_resume_host(slot->host);
1153 if (ret)
1154 return ret;
1155 }
1156
1157 return 0;
1158}
1159
1160static int sdhci_pci_runtime_idle(struct device *dev)
1161{
1162 return 0;
1163}
1164
1165#else
1166
1167#define sdhci_pci_runtime_suspend NULL
1168#define sdhci_pci_runtime_resume NULL
1169#define sdhci_pci_runtime_idle NULL
1170
1171#endif
1172
1173static const struct dev_pm_ops sdhci_pci_pm_ops = {
1174 .runtime_suspend = sdhci_pci_runtime_suspend,
1175 .runtime_resume = sdhci_pci_runtime_resume,
1176 .runtime_idle = sdhci_pci_runtime_idle,
1177};
1178
b8c86fc5
PO		 1179/*****************************************************************************\
1180 * *
1181 * Device probing/removal *
1182 * *
1183\*****************************************************************************/
1184
1185static struct sdhci_pci_slot * __devinit sdhci_pci_probe_slot(
1186 struct pci_dev *pdev, struct sdhci_pci_chip *chip, int bar)
1187{
1188 struct sdhci_pci_slot *slot;
1189 struct sdhci_host *host;
b8c86fc5
PO		 1190 int ret;
1191
1192 if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) {
1193 dev_err(&pdev->dev, "BAR %d is not iomem. Aborting.\n", bar);
1194 return ERR_PTR(-ENODEV);
1195 }
1196
1197 if (pci_resource_len(pdev, bar) != 0x100) {
1198 dev_err(&pdev->dev, "Invalid iomem size. You may "
1199 "experience problems.\n");
1200 }
1201
1202 if ((pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) {
1203 dev_err(&pdev->dev, "Vendor specific interface. Aborting.\n");
1204 return ERR_PTR(-ENODEV);
1205 }
1206
1207 if ((pdev->class & 0x0000FF) > PCI_SDHCI_IFVENDOR) {
1208 dev_err(&pdev->dev, "Unknown interface. Aborting.\n");
1209 return ERR_PTR(-ENODEV);
1210 }
1211
1212 host = sdhci_alloc_host(&pdev->dev, sizeof(struct sdhci_pci_slot));
1213 if (IS_ERR(host)) {
c60a32cd 1214 dev_err(&pdev->dev, "cannot allocate host\n");
dc0fd7b5 1215 return ERR_CAST(host);
b8c86fc5
PO		 1216 }
1217
1218 slot = sdhci_priv(host);
1219
1220 slot->chip = chip;
1221 slot->host = host;
1222 slot->pci_bar = bar;
0f201655 1223 slot->rst_n_gpio = -EINVAL;
b8c86fc5
PO		 1224
1225 host->hw_name = "PCI";
1226 host->ops = &sdhci_pci_ops;
1227 host->quirks = chip->quirks;
1228
1229 host->irq = pdev->irq;
1230
1231 ret = pci_request_region(pdev, bar, mmc_hostname(host->mmc));
1232 if (ret) {
1233 dev_err(&pdev->dev, "cannot request region\n");
c60a32cd 1234 goto free;
b8c86fc5
PO		 1235 }
1236
092f82ed 1237 host->ioaddr = pci_ioremap_bar(pdev, bar);
b8c86fc5
PO		 1238 if (!host->ioaddr) {
1239 dev_err(&pdev->dev, "failed to remap registers\n");
9fdcdbb0 1240 ret = -ENOMEM;
b8c86fc5
PO		 1241 goto release;
1242 }
1243
4489428a
PO		 1244 if (chip->fixes && chip->fixes->probe_slot) {
1245 ret = chip->fixes->probe_slot(slot);
1246 if (ret)
1247 goto unmap;
1248 }
1249
2f4cbb3d
NP		 1250 host->mmc->pm_caps = MMC_PM_KEEP_POWER | MMC_PM_WAKE_SDIO_IRQ;
1251
b8c86fc5
PO		 1252 ret = sdhci_add_host(host);
1253 if (ret)
4489428a 1254 goto remove;
b8c86fc5
PO		 1255
1256 return slot;
1257
4489428a
PO		 1258remove:
1259 if (chip->fixes && chip->fixes->remove_slot)
1e72859e 1260 chip->fixes->remove_slot(slot, 0);
4489428a 1261
b8c86fc5
PO		 1262unmap:
1263 iounmap(host->ioaddr);
1264
1265release:
1266 pci_release_region(pdev, bar);
c60a32cd
DC		 1267
1268free:
b8c86fc5
PO		 1269 sdhci_free_host(host);
1270
1271 return ERR_PTR(ret);
1272}
1273
1274static void sdhci_pci_remove_slot(struct sdhci_pci_slot *slot)
1275{
1e72859e
PO		 1276 int dead;
1277 u32 scratch;
1278
1279 dead = 0;
1280 scratch = readl(slot->host->ioaddr + SDHCI_INT_STATUS);
1281 if (scratch == (u32)-1)
1282 dead = 1;
1283
1284 sdhci_remove_host(slot->host, dead);
4489428a
PO		 1285
1286 if (slot->chip->fixes && slot->chip->fixes->remove_slot)
1e72859e 1287 slot->chip->fixes->remove_slot(slot, dead);
4489428a 1288
b8c86fc5 1289 pci_release_region(slot->chip->pdev, slot->pci_bar);
4489428a 1290
b8c86fc5
PO		 1291 sdhci_free_host(slot->host);
1292}
1293
66fd8ad5
AH		 1294static void __devinit sdhci_pci_runtime_pm_allow(struct device *dev)
1295{
1296 pm_runtime_put_noidle(dev);
1297 pm_runtime_allow(dev);
1298 pm_runtime_set_autosuspend_delay(dev, 50);
1299 pm_runtime_use_autosuspend(dev);
1300 pm_suspend_ignore_children(dev, 1);
1301}
1302
1303static void __devexit sdhci_pci_runtime_pm_forbid(struct device *dev)
1304{
1305 pm_runtime_forbid(dev);
1306 pm_runtime_get_noresume(dev);
1307}
1308
b8c86fc5
PO		 1309static int __devinit sdhci_pci_probe(struct pci_dev *pdev,
1310 const struct pci_device_id *ent)
1311{
1312 struct sdhci_pci_chip *chip;
1313 struct sdhci_pci_slot *slot;
1314
cf5e23e1 1315 u8 slots, first_bar;
b8c86fc5
PO		 1316 int ret, i;
1317
1318 BUG_ON(pdev == NULL);
1319 BUG_ON(ent == NULL);
1320
b8c86fc5 1321 dev_info(&pdev->dev, "SDHCI controller found [%04x:%04x] (rev %x)\n",
cf5e23e1 1322 (int)pdev->vendor, (int)pdev->device, (int)pdev->revision);
b8c86fc5
PO		 1323
1324 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &slots);
1325 if (ret)
1326 return ret;
1327
1328 slots = PCI_SLOT_INFO_SLOTS(slots) + 1;
1329 dev_dbg(&pdev->dev, "found %d slot(s)\n", slots);
1330 if (slots == 0)
1331 return -ENODEV;
1332
1333 BUG_ON(slots > MAX_SLOTS);
1334
1335 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &first_bar);
1336 if (ret)
1337 return ret;
1338
1339 first_bar &= PCI_SLOT_INFO_FIRST_BAR_MASK;
1340
1341 if (first_bar > 5) {
1342 dev_err(&pdev->dev, "Invalid first BAR. Aborting.\n");
1343 return -ENODEV;
1344 }
1345
1346 ret = pci_enable_device(pdev);
1347 if (ret)
1348 return ret;
1349
1350 chip = kzalloc(sizeof(struct sdhci_pci_chip), GFP_KERNEL);
1351 if (!chip) {
1352 ret = -ENOMEM;
1353 goto err;
1354 }
1355
1356 chip->pdev = pdev;
b177bc91 1357 chip->fixes = (const struct sdhci_pci_fixes *)ent->driver_data;
22606405
PO		 1358 if (chip->fixes)
1359 chip->quirks = chip->fixes->quirks;
b8c86fc5
PO		 1360 chip->num_slots = slots;
1361
1362 pci_set_drvdata(pdev, chip);
1363
22606405
PO		 1364 if (chip->fixes && chip->fixes->probe) {
1365 ret = chip->fixes->probe(chip);
1366 if (ret)
1367 goto free;
1368 }
1369
225d85fe
AC		 1370 slots = chip->num_slots; /* Quirk may have changed this */
1371
b177bc91 1372 for (i = 0; i < slots; i++) {
b8c86fc5
PO		 1373 slot = sdhci_pci_probe_slot(pdev, chip, first_bar + i);
1374 if (IS_ERR(slot)) {
b177bc91 1375 for (i--; i >= 0; i--)
b8c86fc5
PO		 1376 sdhci_pci_remove_slot(chip->slots[i]);
1377 ret = PTR_ERR(slot);
1378 goto free;
1379 }
1380
1381 chip->slots[i] = slot;
1382 }
1383
66fd8ad5
AH		 1384 sdhci_pci_runtime_pm_allow(&pdev->dev);
1385
b8c86fc5
PO		 1386 return 0;
1387
1388free:
1389 pci_set_drvdata(pdev, NULL);
1390 kfree(chip);
1391
1392err:
1393 pci_disable_device(pdev);
1394 return ret;
1395}
1396
1397static void __devexit sdhci_pci_remove(struct pci_dev *pdev)
1398{
1399 int i;
1400 struct sdhci_pci_chip *chip;
1401
66fd8ad5
AH		 1402 sdhci_pci_runtime_pm_forbid(&pdev->dev);
1403
b8c86fc5
PO		 1404 chip = pci_get_drvdata(pdev);
1405
1406 if (chip) {
b177bc91 1407 for (i = 0; i < chip->num_slots; i++)
b8c86fc5
PO		 1408 sdhci_pci_remove_slot(chip->slots[i]);
1409
1410 pci_set_drvdata(pdev, NULL);
1411 kfree(chip);
1412 }
1413
1414 pci_disable_device(pdev);
1415}
1416
1417static struct pci_driver sdhci_driver = {
b177bc91 1418 .name = "sdhci-pci",
b8c86fc5 1419 .id_table = pci_ids,
b177bc91 1420 .probe = sdhci_pci_probe,
b8c86fc5
PO		 1421 .remove = __devexit_p(sdhci_pci_remove),
1422 .suspend = sdhci_pci_suspend,
1423 .resume = sdhci_pci_resume,
66fd8ad5
AH		 1424 .driver = {
1425 .pm = &sdhci_pci_pm_ops
1426 },
b8c86fc5
PO		 1427};
1428
1429/*****************************************************************************\
1430 * *
1431 * Driver init/exit *
1432 * *
1433\*****************************************************************************/
1434
1435static int __init sdhci_drv_init(void)
1436{
1437 return pci_register_driver(&sdhci_driver);
1438}
1439
1440static void __exit sdhci_drv_exit(void)
1441{
1442 pci_unregister_driver(&sdhci_driver);
1443}
1444
1445module_init(sdhci_drv_init);
1446module_exit(sdhci_drv_exit);
1447
32710e8f 1448MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
b8c86fc5
PO		 1449MODULE_DESCRIPTION("Secure Digital Host Controller Interface PCI driver");
1450MODULE_LICENSE("GPL");
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