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b8c86fc5 PO |
1 | /* linux/drivers/mmc/host/sdhci-pci.c - SDHCI on PCI bus interface |
2 | * | |
3 | * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved. | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License as published by | |
7 | * the Free Software Foundation; either version 2 of the License, or (at | |
8 | * your option) any later version. | |
9 | * | |
10 | * Thanks to the following companies for their support: | |
11 | * | |
12 | * - JMicron (hardware and technical support) | |
13 | */ | |
14 | ||
15 | #include <linux/delay.h> | |
16 | #include <linux/highmem.h> | |
88b47679 | 17 | #include <linux/module.h> |
b8c86fc5 PO |
18 | #include <linux/pci.h> |
19 | #include <linux/dma-mapping.h> | |
5a0e3ad6 | 20 | #include <linux/slab.h> |
ccc92c23 | 21 | #include <linux/device.h> |
b8c86fc5 | 22 | #include <linux/mmc/host.h> |
b177bc91 AP |
23 | #include <linux/scatterlist.h> |
24 | #include <linux/io.h> | |
0f201655 | 25 | #include <linux/gpio.h> |
66fd8ad5 | 26 | #include <linux/pm_runtime.h> |
ff59c520 | 27 | #include <linux/mmc/slot-gpio.h> |
52c506f0 | 28 | #include <linux/mmc/sdhci-pci-data.h> |
b8c86fc5 PO |
29 | |
30 | #include "sdhci.h" | |
522624f9 | 31 | #include "sdhci-pci.h" |
01acf691 | 32 | #include "sdhci-pci-o2micro.h" |
22606405 PO |
33 | |
34 | /*****************************************************************************\ | |
35 | * * | |
36 | * Hardware specific quirk handling * | |
37 | * * | |
38 | \*****************************************************************************/ | |
39 | ||
40 | static int ricoh_probe(struct sdhci_pci_chip *chip) | |
41 | { | |
c99436fb CB |
42 | if (chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG || |
43 | chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SONY) | |
22606405 | 44 | chip->quirks |= SDHCI_QUIRK_NO_CARD_NO_RESET; |
ccc92c23 ML |
45 | return 0; |
46 | } | |
47 | ||
48 | static int ricoh_mmc_probe_slot(struct sdhci_pci_slot *slot) | |
49 | { | |
50 | slot->host->caps = | |
51 | ((0x21 << SDHCI_TIMEOUT_CLK_SHIFT) | |
52 | & SDHCI_TIMEOUT_CLK_MASK) | | |
22606405 | 53 | |
ccc92c23 ML |
54 | ((0x21 << SDHCI_CLOCK_BASE_SHIFT) |
55 | & SDHCI_CLOCK_BASE_MASK) | | |
56 | ||
57 | SDHCI_TIMEOUT_CLK_UNIT | | |
58 | SDHCI_CAN_VDD_330 | | |
1a1f1f04 | 59 | SDHCI_CAN_DO_HISPD | |
ccc92c23 ML |
60 | SDHCI_CAN_DO_SDMA; |
61 | return 0; | |
62 | } | |
63 | ||
64 | static int ricoh_mmc_resume(struct sdhci_pci_chip *chip) | |
65 | { | |
66 | /* Apply a delay to allow controller to settle */ | |
67 | /* Otherwise it becomes confused if card state changed | |
68 | during suspend */ | |
69 | msleep(500); | |
22606405 PO |
70 | return 0; |
71 | } | |
72 | ||
73 | static const struct sdhci_pci_fixes sdhci_ricoh = { | |
74 | .probe = ricoh_probe, | |
84938294 VK |
75 | .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR | |
76 | SDHCI_QUIRK_FORCE_DMA | | |
77 | SDHCI_QUIRK_CLOCK_BEFORE_RESET, | |
22606405 PO |
78 | }; |
79 | ||
ccc92c23 ML |
80 | static const struct sdhci_pci_fixes sdhci_ricoh_mmc = { |
81 | .probe_slot = ricoh_mmc_probe_slot, | |
82 | .resume = ricoh_mmc_resume, | |
83 | .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR | | |
84 | SDHCI_QUIRK_CLOCK_BEFORE_RESET | | |
85 | SDHCI_QUIRK_NO_CARD_NO_RESET | | |
86 | SDHCI_QUIRK_MISSING_CAPS | |
87 | }; | |
88 | ||
22606405 PO |
89 | static const struct sdhci_pci_fixes sdhci_ene_712 = { |
90 | .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE | | |
91 | SDHCI_QUIRK_BROKEN_DMA, | |
92 | }; | |
93 | ||
94 | static const struct sdhci_pci_fixes sdhci_ene_714 = { | |
95 | .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE | | |
96 | SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS | | |
97 | SDHCI_QUIRK_BROKEN_DMA, | |
98 | }; | |
99 | ||
100 | static const struct sdhci_pci_fixes sdhci_cafe = { | |
101 | .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER | | |
a0874897 | 102 | SDHCI_QUIRK_NO_BUSY_IRQ | |
55fc05b7 | 103 | SDHCI_QUIRK_BROKEN_CARD_DETECTION | |
ee53ab5d | 104 | SDHCI_QUIRK_BROKEN_TIMEOUT_VAL, |
22606405 PO |
105 | }; |
106 | ||
43e968ce DB |
107 | static const struct sdhci_pci_fixes sdhci_intel_qrk = { |
108 | .quirks = SDHCI_QUIRK_NO_HISPD_BIT, | |
109 | }; | |
110 | ||
68077b02 ML |
111 | static int mrst_hc_probe_slot(struct sdhci_pci_slot *slot) |
112 | { | |
113 | slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA; | |
114 | return 0; | |
115 | } | |
116 | ||
f9ee3eab AC |
117 | /* |
118 | * ADMA operation is disabled for Moorestown platform due to | |
119 | * hardware bugs. | |
120 | */ | |
35ac6f08 | 121 | static int mrst_hc_probe(struct sdhci_pci_chip *chip) |
f9ee3eab AC |
122 | { |
123 | /* | |
35ac6f08 JP |
124 | * slots number is fixed here for MRST as SDIO3/5 are never used and |
125 | * have hardware bugs. | |
f9ee3eab AC |
126 | */ |
127 | chip->num_slots = 1; | |
128 | return 0; | |
129 | } | |
130 | ||
296e0b03 AS |
131 | static int pch_hc_probe_slot(struct sdhci_pci_slot *slot) |
132 | { | |
133 | slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA; | |
134 | return 0; | |
135 | } | |
136 | ||
66fd8ad5 AH |
137 | #ifdef CONFIG_PM_RUNTIME |
138 | ||
c5e027a4 | 139 | static irqreturn_t sdhci_pci_sd_cd(int irq, void *dev_id) |
66fd8ad5 AH |
140 | { |
141 | struct sdhci_pci_slot *slot = dev_id; | |
142 | struct sdhci_host *host = slot->host; | |
143 | ||
144 | mmc_detect_change(host->mmc, msecs_to_jiffies(200)); | |
145 | return IRQ_HANDLED; | |
146 | } | |
147 | ||
c5e027a4 | 148 | static void sdhci_pci_add_own_cd(struct sdhci_pci_slot *slot) |
66fd8ad5 | 149 | { |
c5e027a4 | 150 | int err, irq, gpio = slot->cd_gpio; |
66fd8ad5 AH |
151 | |
152 | slot->cd_gpio = -EINVAL; | |
153 | slot->cd_irq = -EINVAL; | |
154 | ||
c5e027a4 AH |
155 | if (!gpio_is_valid(gpio)) |
156 | return; | |
157 | ||
66fd8ad5 AH |
158 | err = gpio_request(gpio, "sd_cd"); |
159 | if (err < 0) | |
160 | goto out; | |
161 | ||
162 | err = gpio_direction_input(gpio); | |
163 | if (err < 0) | |
164 | goto out_free; | |
165 | ||
166 | irq = gpio_to_irq(gpio); | |
167 | if (irq < 0) | |
168 | goto out_free; | |
169 | ||
c5e027a4 | 170 | err = request_irq(irq, sdhci_pci_sd_cd, IRQF_TRIGGER_RISING | |
66fd8ad5 AH |
171 | IRQF_TRIGGER_FALLING, "sd_cd", slot); |
172 | if (err) | |
173 | goto out_free; | |
174 | ||
175 | slot->cd_gpio = gpio; | |
176 | slot->cd_irq = irq; | |
66fd8ad5 | 177 | |
c5e027a4 | 178 | return; |
66fd8ad5 AH |
179 | |
180 | out_free: | |
181 | gpio_free(gpio); | |
182 | out: | |
183 | dev_warn(&slot->chip->pdev->dev, "failed to setup card detect wake up\n"); | |
66fd8ad5 AH |
184 | } |
185 | ||
c5e027a4 | 186 | static void sdhci_pci_remove_own_cd(struct sdhci_pci_slot *slot) |
66fd8ad5 AH |
187 | { |
188 | if (slot->cd_irq >= 0) | |
189 | free_irq(slot->cd_irq, slot); | |
c5e027a4 AH |
190 | if (gpio_is_valid(slot->cd_gpio)) |
191 | gpio_free(slot->cd_gpio); | |
66fd8ad5 AH |
192 | } |
193 | ||
194 | #else | |
195 | ||
c5e027a4 AH |
196 | static inline void sdhci_pci_add_own_cd(struct sdhci_pci_slot *slot) |
197 | { | |
198 | } | |
199 | ||
200 | static inline void sdhci_pci_remove_own_cd(struct sdhci_pci_slot *slot) | |
201 | { | |
202 | } | |
66fd8ad5 AH |
203 | |
204 | #endif | |
205 | ||
0d013bcf AH |
206 | static int mfd_emmc_probe_slot(struct sdhci_pci_slot *slot) |
207 | { | |
66fd8ad5 | 208 | slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE; |
da721cf7 AH |
209 | slot->host->mmc->caps2 |= MMC_CAP2_BOOTPART_NOACC | |
210 | MMC_CAP2_HC_ERASE_SZ; | |
0d013bcf AH |
211 | return 0; |
212 | } | |
213 | ||
93933508 AH |
214 | static int mfd_sdio_probe_slot(struct sdhci_pci_slot *slot) |
215 | { | |
012e4671 | 216 | slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE; |
93933508 AH |
217 | return 0; |
218 | } | |
219 | ||
f9ee3eab AC |
220 | static const struct sdhci_pci_fixes sdhci_intel_mrst_hc0 = { |
221 | .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT, | |
68077b02 | 222 | .probe_slot = mrst_hc_probe_slot, |
f9ee3eab AC |
223 | }; |
224 | ||
35ac6f08 | 225 | static const struct sdhci_pci_fixes sdhci_intel_mrst_hc1_hc2 = { |
f9ee3eab | 226 | .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT, |
35ac6f08 | 227 | .probe = mrst_hc_probe, |
f9ee3eab AC |
228 | }; |
229 | ||
29229052 XS |
230 | static const struct sdhci_pci_fixes sdhci_intel_mfd_sd = { |
231 | .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, | |
c43fd774 | 232 | .allow_runtime_pm = true, |
77a0122e | 233 | .own_cd_for_runtime_pm = true, |
29229052 XS |
234 | }; |
235 | ||
0d013bcf AH |
236 | static const struct sdhci_pci_fixes sdhci_intel_mfd_sdio = { |
237 | .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, | |
f3c55a7b | 238 | .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON, |
c43fd774 | 239 | .allow_runtime_pm = true, |
93933508 | 240 | .probe_slot = mfd_sdio_probe_slot, |
0d013bcf AH |
241 | }; |
242 | ||
243 | static const struct sdhci_pci_fixes sdhci_intel_mfd_emmc = { | |
29229052 | 244 | .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, |
c43fd774 | 245 | .allow_runtime_pm = true, |
0d013bcf | 246 | .probe_slot = mfd_emmc_probe_slot, |
29229052 XS |
247 | }; |
248 | ||
296e0b03 AS |
249 | static const struct sdhci_pci_fixes sdhci_intel_pch_sdio = { |
250 | .quirks = SDHCI_QUIRK_BROKEN_ADMA, | |
251 | .probe_slot = pch_hc_probe_slot, | |
252 | }; | |
253 | ||
c9faff6c AH |
254 | static void sdhci_pci_int_hw_reset(struct sdhci_host *host) |
255 | { | |
256 | u8 reg; | |
257 | ||
258 | reg = sdhci_readb(host, SDHCI_POWER_CONTROL); | |
259 | reg |= 0x10; | |
260 | sdhci_writeb(host, reg, SDHCI_POWER_CONTROL); | |
261 | /* For eMMC, minimum is 1us but give it 9us for good measure */ | |
262 | udelay(9); | |
263 | reg &= ~0x10; | |
264 | sdhci_writeb(host, reg, SDHCI_POWER_CONTROL); | |
265 | /* For eMMC, minimum is 200us but give it 300us for good measure */ | |
266 | usleep_range(300, 1000); | |
267 | } | |
268 | ||
728ef3d1 AH |
269 | static int byt_emmc_probe_slot(struct sdhci_pci_slot *slot) |
270 | { | |
c9faff6c | 271 | slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE | |
f25c3372 | 272 | MMC_CAP_HW_RESET | MMC_CAP_1_8V_DDR; |
728ef3d1 | 273 | slot->host->mmc->caps2 |= MMC_CAP2_HC_ERASE_SZ; |
c9faff6c | 274 | slot->hw_reset = sdhci_pci_int_hw_reset; |
a06586b6 AH |
275 | if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BSW_EMMC) |
276 | slot->host->timeout_clk = 1000; /* 1000 kHz i.e. 1 MHz */ | |
728ef3d1 AH |
277 | return 0; |
278 | } | |
279 | ||
280 | static int byt_sdio_probe_slot(struct sdhci_pci_slot *slot) | |
281 | { | |
282 | slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE; | |
283 | return 0; | |
284 | } | |
285 | ||
ff59c520 AH |
286 | static int byt_sd_probe_slot(struct sdhci_pci_slot *slot) |
287 | { | |
288 | slot->cd_con_id = NULL; | |
289 | slot->cd_idx = 0; | |
290 | slot->cd_override_level = true; | |
291 | return 0; | |
292 | } | |
293 | ||
728ef3d1 AH |
294 | static const struct sdhci_pci_fixes sdhci_intel_byt_emmc = { |
295 | .allow_runtime_pm = true, | |
296 | .probe_slot = byt_emmc_probe_slot, | |
db6e8cdf | 297 | .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, |
e58e4a0d AH |
298 | .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | |
299 | SDHCI_QUIRK2_STOP_WITH_TC, | |
728ef3d1 AH |
300 | }; |
301 | ||
302 | static const struct sdhci_pci_fixes sdhci_intel_byt_sdio = { | |
db6e8cdf | 303 | .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, |
b7574bad GY |
304 | .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON | |
305 | SDHCI_QUIRK2_PRESET_VALUE_BROKEN, | |
728ef3d1 AH |
306 | .allow_runtime_pm = true, |
307 | .probe_slot = byt_sdio_probe_slot, | |
308 | }; | |
309 | ||
310 | static const struct sdhci_pci_fixes sdhci_intel_byt_sd = { | |
db6e8cdf | 311 | .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, |
b7574bad | 312 | .quirks2 = SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON | |
e58e4a0d AH |
313 | SDHCI_QUIRK2_PRESET_VALUE_BROKEN | |
314 | SDHCI_QUIRK2_STOP_WITH_TC, | |
7396e318 | 315 | .allow_runtime_pm = true, |
77a0122e | 316 | .own_cd_for_runtime_pm = true, |
ff59c520 | 317 | .probe_slot = byt_sd_probe_slot, |
728ef3d1 AH |
318 | }; |
319 | ||
8776a165 DC |
320 | /* Define Host controllers for Intel Merrifield platform */ |
321 | #define INTEL_MRFL_EMMC_0 0 | |
322 | #define INTEL_MRFL_EMMC_1 1 | |
323 | ||
324 | static int intel_mrfl_mmc_probe_slot(struct sdhci_pci_slot *slot) | |
325 | { | |
326 | if ((PCI_FUNC(slot->chip->pdev->devfn) != INTEL_MRFL_EMMC_0) && | |
327 | (PCI_FUNC(slot->chip->pdev->devfn) != INTEL_MRFL_EMMC_1)) | |
328 | /* SD support is not ready yet */ | |
329 | return -ENODEV; | |
330 | ||
331 | slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE | | |
332 | MMC_CAP_1_8V_DDR; | |
333 | ||
334 | return 0; | |
335 | } | |
336 | ||
337 | static const struct sdhci_pci_fixes sdhci_intel_mrfl_mmc = { | |
338 | .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, | |
b7574bad GY |
339 | .quirks2 = SDHCI_QUIRK2_BROKEN_HS200 | |
340 | SDHCI_QUIRK2_PRESET_VALUE_BROKEN, | |
f1b55a55 | 341 | .allow_runtime_pm = true, |
8776a165 DC |
342 | .probe_slot = intel_mrfl_mmc_probe_slot, |
343 | }; | |
344 | ||
26daa1ed JL |
345 | /* O2Micro extra registers */ |
346 | #define O2_SD_LOCK_WP 0xD3 | |
347 | #define O2_SD_MULTI_VCC3V 0xEE | |
348 | #define O2_SD_CLKREQ 0xEC | |
349 | #define O2_SD_CAPS 0xE0 | |
350 | #define O2_SD_ADMA1 0xE2 | |
351 | #define O2_SD_ADMA2 0xE7 | |
352 | #define O2_SD_INF_MOD 0xF1 | |
353 | ||
45211e21 PO |
354 | static int jmicron_pmos(struct sdhci_pci_chip *chip, int on) |
355 | { | |
356 | u8 scratch; | |
357 | int ret; | |
358 | ||
359 | ret = pci_read_config_byte(chip->pdev, 0xAE, &scratch); | |
360 | if (ret) | |
361 | return ret; | |
362 | ||
363 | /* | |
364 | * Turn PMOS on [bit 0], set over current detection to 2.4 V | |
365 | * [bit 1:2] and enable over current debouncing [bit 6]. | |
366 | */ | |
367 | if (on) | |
368 | scratch |= 0x47; | |
369 | else | |
370 | scratch &= ~0x47; | |
371 | ||
372 | ret = pci_write_config_byte(chip->pdev, 0xAE, scratch); | |
373 | if (ret) | |
374 | return ret; | |
375 | ||
376 | return 0; | |
377 | } | |
378 | ||
379 | static int jmicron_probe(struct sdhci_pci_chip *chip) | |
380 | { | |
381 | int ret; | |
8f230f45 | 382 | u16 mmcdev = 0; |
45211e21 | 383 | |
93fc48c7 PO |
384 | if (chip->pdev->revision == 0) { |
385 | chip->quirks |= SDHCI_QUIRK_32BIT_DMA_ADDR | | |
386 | SDHCI_QUIRK_32BIT_DMA_SIZE | | |
2134a922 | 387 | SDHCI_QUIRK_32BIT_ADMA_SIZE | |
4a3cba32 | 388 | SDHCI_QUIRK_RESET_AFTER_REQUEST | |
86a6a874 | 389 | SDHCI_QUIRK_BROKEN_SMALL_PIO; |
93fc48c7 PO |
390 | } |
391 | ||
4489428a PO |
392 | /* |
393 | * JMicron chips can have two interfaces to the same hardware | |
394 | * in order to work around limitations in Microsoft's driver. | |
395 | * We need to make sure we only bind to one of them. | |
396 | * | |
397 | * This code assumes two things: | |
398 | * | |
399 | * 1. The PCI code adds subfunctions in order. | |
400 | * | |
401 | * 2. The MMC interface has a lower subfunction number | |
402 | * than the SD interface. | |
403 | */ | |
8f230f45 TI |
404 | if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_SD) |
405 | mmcdev = PCI_DEVICE_ID_JMICRON_JMB38X_MMC; | |
406 | else if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD) | |
407 | mmcdev = PCI_DEVICE_ID_JMICRON_JMB388_ESD; | |
408 | ||
409 | if (mmcdev) { | |
4489428a PO |
410 | struct pci_dev *sd_dev; |
411 | ||
412 | sd_dev = NULL; | |
413 | while ((sd_dev = pci_get_device(PCI_VENDOR_ID_JMICRON, | |
8f230f45 | 414 | mmcdev, sd_dev)) != NULL) { |
4489428a PO |
415 | if ((PCI_SLOT(chip->pdev->devfn) == |
416 | PCI_SLOT(sd_dev->devfn)) && | |
417 | (chip->pdev->bus == sd_dev->bus)) | |
418 | break; | |
419 | } | |
420 | ||
421 | if (sd_dev) { | |
422 | pci_dev_put(sd_dev); | |
423 | dev_info(&chip->pdev->dev, "Refusing to bind to " | |
424 | "secondary interface.\n"); | |
425 | return -ENODEV; | |
426 | } | |
427 | } | |
428 | ||
45211e21 PO |
429 | /* |
430 | * JMicron chips need a bit of a nudge to enable the power | |
431 | * output pins. | |
432 | */ | |
433 | ret = jmicron_pmos(chip, 1); | |
434 | if (ret) { | |
435 | dev_err(&chip->pdev->dev, "Failure enabling card power\n"); | |
436 | return ret; | |
437 | } | |
438 | ||
82b0e23a TI |
439 | /* quirk for unsable RO-detection on JM388 chips */ |
440 | if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD || | |
441 | chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) | |
442 | chip->quirks |= SDHCI_QUIRK_UNSTABLE_RO_DETECT; | |
443 | ||
45211e21 PO |
444 | return 0; |
445 | } | |
446 | ||
4489428a PO |
447 | static void jmicron_enable_mmc(struct sdhci_host *host, int on) |
448 | { | |
449 | u8 scratch; | |
450 | ||
451 | scratch = readb(host->ioaddr + 0xC0); | |
452 | ||
453 | if (on) | |
454 | scratch |= 0x01; | |
455 | else | |
456 | scratch &= ~0x01; | |
457 | ||
458 | writeb(scratch, host->ioaddr + 0xC0); | |
459 | } | |
460 | ||
461 | static int jmicron_probe_slot(struct sdhci_pci_slot *slot) | |
462 | { | |
2134a922 PO |
463 | if (slot->chip->pdev->revision == 0) { |
464 | u16 version; | |
465 | ||
466 | version = readl(slot->host->ioaddr + SDHCI_HOST_VERSION); | |
467 | version = (version & SDHCI_VENDOR_VER_MASK) >> | |
468 | SDHCI_VENDOR_VER_SHIFT; | |
469 | ||
470 | /* | |
471 | * Older versions of the chip have lots of nasty glitches | |
472 | * in the ADMA engine. It's best just to avoid it | |
473 | * completely. | |
474 | */ | |
475 | if (version < 0xAC) | |
476 | slot->host->quirks |= SDHCI_QUIRK_BROKEN_ADMA; | |
477 | } | |
478 | ||
8f230f45 TI |
479 | /* JM388 MMC doesn't support 1.8V while SD supports it */ |
480 | if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) { | |
481 | slot->host->ocr_avail_sd = MMC_VDD_32_33 | MMC_VDD_33_34 | | |
482 | MMC_VDD_29_30 | MMC_VDD_30_31 | | |
483 | MMC_VDD_165_195; /* allow 1.8V */ | |
484 | slot->host->ocr_avail_mmc = MMC_VDD_32_33 | MMC_VDD_33_34 | | |
485 | MMC_VDD_29_30 | MMC_VDD_30_31; /* no 1.8V for MMC */ | |
486 | } | |
487 | ||
4489428a PO |
488 | /* |
489 | * The secondary interface requires a bit set to get the | |
490 | * interrupts. | |
491 | */ | |
8f230f45 TI |
492 | if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || |
493 | slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) | |
4489428a PO |
494 | jmicron_enable_mmc(slot->host, 1); |
495 | ||
d75c1084 TI |
496 | slot->host->mmc->caps |= MMC_CAP_BUS_WIDTH_TEST; |
497 | ||
4489428a PO |
498 | return 0; |
499 | } | |
500 | ||
1e72859e | 501 | static void jmicron_remove_slot(struct sdhci_pci_slot *slot, int dead) |
4489428a | 502 | { |
1e72859e PO |
503 | if (dead) |
504 | return; | |
505 | ||
8f230f45 TI |
506 | if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || |
507 | slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) | |
4489428a PO |
508 | jmicron_enable_mmc(slot->host, 0); |
509 | } | |
510 | ||
29495aa0 | 511 | static int jmicron_suspend(struct sdhci_pci_chip *chip) |
4489428a PO |
512 | { |
513 | int i; | |
514 | ||
8f230f45 TI |
515 | if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || |
516 | chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) { | |
b177bc91 | 517 | for (i = 0; i < chip->num_slots; i++) |
4489428a PO |
518 | jmicron_enable_mmc(chip->slots[i]->host, 0); |
519 | } | |
520 | ||
521 | return 0; | |
522 | } | |
523 | ||
45211e21 PO |
524 | static int jmicron_resume(struct sdhci_pci_chip *chip) |
525 | { | |
4489428a PO |
526 | int ret, i; |
527 | ||
8f230f45 TI |
528 | if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || |
529 | chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) { | |
b177bc91 | 530 | for (i = 0; i < chip->num_slots; i++) |
4489428a PO |
531 | jmicron_enable_mmc(chip->slots[i]->host, 1); |
532 | } | |
45211e21 PO |
533 | |
534 | ret = jmicron_pmos(chip, 1); | |
535 | if (ret) { | |
536 | dev_err(&chip->pdev->dev, "Failure enabling card power\n"); | |
537 | return ret; | |
538 | } | |
539 | ||
540 | return 0; | |
541 | } | |
542 | ||
26daa1ed | 543 | static const struct sdhci_pci_fixes sdhci_o2 = { |
01acf691 AL |
544 | .probe = sdhci_pci_o2_probe, |
545 | .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, | |
546 | .probe_slot = sdhci_pci_o2_probe_slot, | |
547 | .resume = sdhci_pci_o2_resume, | |
26daa1ed JL |
548 | }; |
549 | ||
22606405 | 550 | static const struct sdhci_pci_fixes sdhci_jmicron = { |
45211e21 PO |
551 | .probe = jmicron_probe, |
552 | ||
4489428a PO |
553 | .probe_slot = jmicron_probe_slot, |
554 | .remove_slot = jmicron_remove_slot, | |
555 | ||
556 | .suspend = jmicron_suspend, | |
45211e21 | 557 | .resume = jmicron_resume, |
22606405 PO |
558 | }; |
559 | ||
a7a6186c NP |
560 | /* SysKonnect CardBus2SDIO extra registers */ |
561 | #define SYSKT_CTRL 0x200 | |
562 | #define SYSKT_RDFIFO_STAT 0x204 | |
563 | #define SYSKT_WRFIFO_STAT 0x208 | |
564 | #define SYSKT_POWER_DATA 0x20c | |
565 | #define SYSKT_POWER_330 0xef | |
566 | #define SYSKT_POWER_300 0xf8 | |
567 | #define SYSKT_POWER_184 0xcc | |
568 | #define SYSKT_POWER_CMD 0x20d | |
569 | #define SYSKT_POWER_START (1 << 7) | |
570 | #define SYSKT_POWER_STATUS 0x20e | |
571 | #define SYSKT_POWER_STATUS_OK (1 << 0) | |
572 | #define SYSKT_BOARD_REV 0x210 | |
573 | #define SYSKT_CHIP_REV 0x211 | |
574 | #define SYSKT_CONF_DATA 0x212 | |
575 | #define SYSKT_CONF_DATA_1V8 (1 << 2) | |
576 | #define SYSKT_CONF_DATA_2V5 (1 << 1) | |
577 | #define SYSKT_CONF_DATA_3V3 (1 << 0) | |
578 | ||
579 | static int syskt_probe(struct sdhci_pci_chip *chip) | |
580 | { | |
581 | if ((chip->pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) { | |
582 | chip->pdev->class &= ~0x0000FF; | |
583 | chip->pdev->class |= PCI_SDHCI_IFDMA; | |
584 | } | |
585 | return 0; | |
586 | } | |
587 | ||
588 | static int syskt_probe_slot(struct sdhci_pci_slot *slot) | |
589 | { | |
590 | int tm, ps; | |
591 | ||
592 | u8 board_rev = readb(slot->host->ioaddr + SYSKT_BOARD_REV); | |
593 | u8 chip_rev = readb(slot->host->ioaddr + SYSKT_CHIP_REV); | |
594 | dev_info(&slot->chip->pdev->dev, "SysKonnect CardBus2SDIO, " | |
595 | "board rev %d.%d, chip rev %d.%d\n", | |
596 | board_rev >> 4, board_rev & 0xf, | |
597 | chip_rev >> 4, chip_rev & 0xf); | |
598 | if (chip_rev >= 0x20) | |
599 | slot->host->quirks |= SDHCI_QUIRK_FORCE_DMA; | |
600 | ||
601 | writeb(SYSKT_POWER_330, slot->host->ioaddr + SYSKT_POWER_DATA); | |
602 | writeb(SYSKT_POWER_START, slot->host->ioaddr + SYSKT_POWER_CMD); | |
603 | udelay(50); | |
604 | tm = 10; /* Wait max 1 ms */ | |
605 | do { | |
606 | ps = readw(slot->host->ioaddr + SYSKT_POWER_STATUS); | |
607 | if (ps & SYSKT_POWER_STATUS_OK) | |
608 | break; | |
609 | udelay(100); | |
610 | } while (--tm); | |
611 | if (!tm) { | |
612 | dev_err(&slot->chip->pdev->dev, | |
613 | "power regulator never stabilized"); | |
614 | writeb(0, slot->host->ioaddr + SYSKT_POWER_CMD); | |
615 | return -ENODEV; | |
616 | } | |
617 | ||
618 | return 0; | |
619 | } | |
620 | ||
621 | static const struct sdhci_pci_fixes sdhci_syskt = { | |
622 | .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER, | |
623 | .probe = syskt_probe, | |
624 | .probe_slot = syskt_probe_slot, | |
625 | }; | |
626 | ||
557b0697 HW |
627 | static int via_probe(struct sdhci_pci_chip *chip) |
628 | { | |
629 | if (chip->pdev->revision == 0x10) | |
630 | chip->quirks |= SDHCI_QUIRK_DELAY_AFTER_POWER; | |
631 | ||
632 | return 0; | |
633 | } | |
634 | ||
635 | static const struct sdhci_pci_fixes sdhci_via = { | |
636 | .probe = via_probe, | |
637 | }; | |
638 | ||
9107ebbf MC |
639 | static int rtsx_probe_slot(struct sdhci_pci_slot *slot) |
640 | { | |
641 | slot->host->mmc->caps2 |= MMC_CAP2_HS200; | |
642 | return 0; | |
643 | } | |
644 | ||
645 | static const struct sdhci_pci_fixes sdhci_rtsx = { | |
646 | .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | | |
647 | SDHCI_QUIRK2_BROKEN_DDR50, | |
648 | .probe_slot = rtsx_probe_slot, | |
649 | }; | |
650 | ||
d44f88da VW |
651 | static int amd_probe(struct sdhci_pci_chip *chip) |
652 | { | |
653 | struct pci_dev *smbus_dev; | |
654 | ||
655 | smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD, | |
656 | PCI_DEVICE_ID_AMD_HUDSON2_SMBUS, NULL); | |
657 | ||
e765bfa2 | 658 | if (smbus_dev && (smbus_dev->revision < 0x51)) { |
d44f88da | 659 | chip->quirks2 |= SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD; |
e765bfa2 VW |
660 | chip->quirks2 |= SDHCI_QUIRK2_BROKEN_HS200; |
661 | } | |
d44f88da VW |
662 | |
663 | return 0; | |
664 | } | |
665 | ||
666 | static const struct sdhci_pci_fixes sdhci_amd = { | |
667 | .probe = amd_probe, | |
668 | }; | |
669 | ||
9647f84d | 670 | static const struct pci_device_id pci_ids[] = { |
b8c86fc5 PO |
671 | { |
672 | .vendor = PCI_VENDOR_ID_RICOH, | |
673 | .device = PCI_DEVICE_ID_RICOH_R5C822, | |
22606405 | 674 | .subvendor = PCI_ANY_ID, |
b8c86fc5 | 675 | .subdevice = PCI_ANY_ID, |
22606405 | 676 | .driver_data = (kernel_ulong_t)&sdhci_ricoh, |
b8c86fc5 PO |
677 | }, |
678 | ||
ccc92c23 ML |
679 | { |
680 | .vendor = PCI_VENDOR_ID_RICOH, | |
681 | .device = 0x843, | |
682 | .subvendor = PCI_ANY_ID, | |
683 | .subdevice = PCI_ANY_ID, | |
684 | .driver_data = (kernel_ulong_t)&sdhci_ricoh_mmc, | |
685 | }, | |
686 | ||
568133eb PC |
687 | { |
688 | .vendor = PCI_VENDOR_ID_RICOH, | |
689 | .device = 0xe822, | |
690 | .subvendor = PCI_ANY_ID, | |
691 | .subdevice = PCI_ANY_ID, | |
692 | .driver_data = (kernel_ulong_t)&sdhci_ricoh_mmc, | |
693 | }, | |
694 | ||
5fd11c07 MI |
695 | { |
696 | .vendor = PCI_VENDOR_ID_RICOH, | |
697 | .device = 0xe823, | |
698 | .subvendor = PCI_ANY_ID, | |
699 | .subdevice = PCI_ANY_ID, | |
700 | .driver_data = (kernel_ulong_t)&sdhci_ricoh_mmc, | |
701 | }, | |
702 | ||
b8c86fc5 PO |
703 | { |
704 | .vendor = PCI_VENDOR_ID_ENE, | |
705 | .device = PCI_DEVICE_ID_ENE_CB712_SD, | |
706 | .subvendor = PCI_ANY_ID, | |
707 | .subdevice = PCI_ANY_ID, | |
22606405 | 708 | .driver_data = (kernel_ulong_t)&sdhci_ene_712, |
b8c86fc5 PO |
709 | }, |
710 | ||
711 | { | |
712 | .vendor = PCI_VENDOR_ID_ENE, | |
713 | .device = PCI_DEVICE_ID_ENE_CB712_SD_2, | |
714 | .subvendor = PCI_ANY_ID, | |
715 | .subdevice = PCI_ANY_ID, | |
22606405 | 716 | .driver_data = (kernel_ulong_t)&sdhci_ene_712, |
b8c86fc5 PO |
717 | }, |
718 | ||
719 | { | |
720 | .vendor = PCI_VENDOR_ID_ENE, | |
721 | .device = PCI_DEVICE_ID_ENE_CB714_SD, | |
722 | .subvendor = PCI_ANY_ID, | |
723 | .subdevice = PCI_ANY_ID, | |
22606405 | 724 | .driver_data = (kernel_ulong_t)&sdhci_ene_714, |
b8c86fc5 PO |
725 | }, |
726 | ||
727 | { | |
728 | .vendor = PCI_VENDOR_ID_ENE, | |
729 | .device = PCI_DEVICE_ID_ENE_CB714_SD_2, | |
730 | .subvendor = PCI_ANY_ID, | |
731 | .subdevice = PCI_ANY_ID, | |
22606405 | 732 | .driver_data = (kernel_ulong_t)&sdhci_ene_714, |
b8c86fc5 PO |
733 | }, |
734 | ||
735 | { | |
736 | .vendor = PCI_VENDOR_ID_MARVELL, | |
8c5eb880 | 737 | .device = PCI_DEVICE_ID_MARVELL_88ALP01_SD, |
b8c86fc5 PO |
738 | .subvendor = PCI_ANY_ID, |
739 | .subdevice = PCI_ANY_ID, | |
22606405 | 740 | .driver_data = (kernel_ulong_t)&sdhci_cafe, |
b8c86fc5 PO |
741 | }, |
742 | ||
743 | { | |
744 | .vendor = PCI_VENDOR_ID_JMICRON, | |
745 | .device = PCI_DEVICE_ID_JMICRON_JMB38X_SD, | |
746 | .subvendor = PCI_ANY_ID, | |
747 | .subdevice = PCI_ANY_ID, | |
22606405 | 748 | .driver_data = (kernel_ulong_t)&sdhci_jmicron, |
b8c86fc5 PO |
749 | }, |
750 | ||
4489428a PO |
751 | { |
752 | .vendor = PCI_VENDOR_ID_JMICRON, | |
753 | .device = PCI_DEVICE_ID_JMICRON_JMB38X_MMC, | |
754 | .subvendor = PCI_ANY_ID, | |
755 | .subdevice = PCI_ANY_ID, | |
756 | .driver_data = (kernel_ulong_t)&sdhci_jmicron, | |
8f230f45 TI |
757 | }, |
758 | ||
759 | { | |
760 | .vendor = PCI_VENDOR_ID_JMICRON, | |
761 | .device = PCI_DEVICE_ID_JMICRON_JMB388_SD, | |
762 | .subvendor = PCI_ANY_ID, | |
763 | .subdevice = PCI_ANY_ID, | |
764 | .driver_data = (kernel_ulong_t)&sdhci_jmicron, | |
765 | }, | |
766 | ||
767 | { | |
768 | .vendor = PCI_VENDOR_ID_JMICRON, | |
769 | .device = PCI_DEVICE_ID_JMICRON_JMB388_ESD, | |
770 | .subvendor = PCI_ANY_ID, | |
771 | .subdevice = PCI_ANY_ID, | |
772 | .driver_data = (kernel_ulong_t)&sdhci_jmicron, | |
4489428a PO |
773 | }, |
774 | ||
a7a6186c NP |
775 | { |
776 | .vendor = PCI_VENDOR_ID_SYSKONNECT, | |
777 | .device = 0x8000, | |
778 | .subvendor = PCI_ANY_ID, | |
779 | .subdevice = PCI_ANY_ID, | |
780 | .driver_data = (kernel_ulong_t)&sdhci_syskt, | |
781 | }, | |
782 | ||
557b0697 HW |
783 | { |
784 | .vendor = PCI_VENDOR_ID_VIA, | |
785 | .device = 0x95d0, | |
786 | .subvendor = PCI_ANY_ID, | |
787 | .subdevice = PCI_ANY_ID, | |
788 | .driver_data = (kernel_ulong_t)&sdhci_via, | |
9107ebbf MC |
789 | }, |
790 | ||
791 | { | |
792 | .vendor = PCI_VENDOR_ID_REALTEK, | |
793 | .device = 0x5250, | |
794 | .subvendor = PCI_ANY_ID, | |
795 | .subdevice = PCI_ANY_ID, | |
796 | .driver_data = (kernel_ulong_t)&sdhci_rtsx, | |
557b0697 HW |
797 | }, |
798 | ||
43e968ce DB |
799 | { |
800 | .vendor = PCI_VENDOR_ID_INTEL, | |
801 | .device = PCI_DEVICE_ID_INTEL_QRK_SD, | |
802 | .subvendor = PCI_ANY_ID, | |
803 | .subdevice = PCI_ANY_ID, | |
804 | .driver_data = (kernel_ulong_t)&sdhci_intel_qrk, | |
805 | }, | |
806 | ||
29229052 XS |
807 | { |
808 | .vendor = PCI_VENDOR_ID_INTEL, | |
f9ee3eab AC |
809 | .device = PCI_DEVICE_ID_INTEL_MRST_SD0, |
810 | .subvendor = PCI_ANY_ID, | |
811 | .subdevice = PCI_ANY_ID, | |
812 | .driver_data = (kernel_ulong_t)&sdhci_intel_mrst_hc0, | |
813 | }, | |
814 | ||
815 | { | |
816 | .vendor = PCI_VENDOR_ID_INTEL, | |
817 | .device = PCI_DEVICE_ID_INTEL_MRST_SD1, | |
818 | .subvendor = PCI_ANY_ID, | |
819 | .subdevice = PCI_ANY_ID, | |
35ac6f08 JP |
820 | .driver_data = (kernel_ulong_t)&sdhci_intel_mrst_hc1_hc2, |
821 | }, | |
822 | ||
823 | { | |
824 | .vendor = PCI_VENDOR_ID_INTEL, | |
825 | .device = PCI_DEVICE_ID_INTEL_MRST_SD2, | |
826 | .subvendor = PCI_ANY_ID, | |
827 | .subdevice = PCI_ANY_ID, | |
828 | .driver_data = (kernel_ulong_t)&sdhci_intel_mrst_hc1_hc2, | |
f9ee3eab AC |
829 | }, |
830 | ||
831 | { | |
832 | .vendor = PCI_VENDOR_ID_INTEL, | |
29229052 XS |
833 | .device = PCI_DEVICE_ID_INTEL_MFD_SD, |
834 | .subvendor = PCI_ANY_ID, | |
835 | .subdevice = PCI_ANY_ID, | |
836 | .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sd, | |
837 | }, | |
838 | ||
839 | { | |
840 | .vendor = PCI_VENDOR_ID_INTEL, | |
841 | .device = PCI_DEVICE_ID_INTEL_MFD_SDIO1, | |
842 | .subvendor = PCI_ANY_ID, | |
843 | .subdevice = PCI_ANY_ID, | |
0d013bcf | 844 | .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sdio, |
29229052 XS |
845 | }, |
846 | ||
847 | { | |
848 | .vendor = PCI_VENDOR_ID_INTEL, | |
849 | .device = PCI_DEVICE_ID_INTEL_MFD_SDIO2, | |
850 | .subvendor = PCI_ANY_ID, | |
851 | .subdevice = PCI_ANY_ID, | |
0d013bcf | 852 | .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sdio, |
29229052 XS |
853 | }, |
854 | ||
855 | { | |
856 | .vendor = PCI_VENDOR_ID_INTEL, | |
857 | .device = PCI_DEVICE_ID_INTEL_MFD_EMMC0, | |
858 | .subvendor = PCI_ANY_ID, | |
859 | .subdevice = PCI_ANY_ID, | |
0d013bcf | 860 | .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc, |
29229052 XS |
861 | }, |
862 | ||
863 | { | |
864 | .vendor = PCI_VENDOR_ID_INTEL, | |
865 | .device = PCI_DEVICE_ID_INTEL_MFD_EMMC1, | |
866 | .subvendor = PCI_ANY_ID, | |
867 | .subdevice = PCI_ANY_ID, | |
0d013bcf | 868 | .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc, |
29229052 XS |
869 | }, |
870 | ||
296e0b03 AS |
871 | { |
872 | .vendor = PCI_VENDOR_ID_INTEL, | |
873 | .device = PCI_DEVICE_ID_INTEL_PCH_SDIO0, | |
874 | .subvendor = PCI_ANY_ID, | |
875 | .subdevice = PCI_ANY_ID, | |
876 | .driver_data = (kernel_ulong_t)&sdhci_intel_pch_sdio, | |
877 | }, | |
878 | ||
879 | { | |
880 | .vendor = PCI_VENDOR_ID_INTEL, | |
881 | .device = PCI_DEVICE_ID_INTEL_PCH_SDIO1, | |
882 | .subvendor = PCI_ANY_ID, | |
883 | .subdevice = PCI_ANY_ID, | |
884 | .driver_data = (kernel_ulong_t)&sdhci_intel_pch_sdio, | |
885 | }, | |
886 | ||
728ef3d1 AH |
887 | { |
888 | .vendor = PCI_VENDOR_ID_INTEL, | |
889 | .device = PCI_DEVICE_ID_INTEL_BYT_EMMC, | |
890 | .subvendor = PCI_ANY_ID, | |
891 | .subdevice = PCI_ANY_ID, | |
892 | .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc, | |
893 | }, | |
894 | ||
895 | { | |
896 | .vendor = PCI_VENDOR_ID_INTEL, | |
897 | .device = PCI_DEVICE_ID_INTEL_BYT_SDIO, | |
898 | .subvendor = PCI_ANY_ID, | |
899 | .subdevice = PCI_ANY_ID, | |
900 | .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio, | |
901 | }, | |
902 | ||
903 | { | |
904 | .vendor = PCI_VENDOR_ID_INTEL, | |
905 | .device = PCI_DEVICE_ID_INTEL_BYT_SD, | |
906 | .subvendor = PCI_ANY_ID, | |
907 | .subdevice = PCI_ANY_ID, | |
908 | .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd, | |
909 | }, | |
910 | ||
30d025c0 AH |
911 | { |
912 | .vendor = PCI_VENDOR_ID_INTEL, | |
913 | .device = PCI_DEVICE_ID_INTEL_BYT_EMMC2, | |
914 | .subvendor = PCI_ANY_ID, | |
915 | .subdevice = PCI_ANY_ID, | |
916 | .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc, | |
917 | }, | |
918 | ||
066173b6 AC |
919 | { |
920 | .vendor = PCI_VENDOR_ID_INTEL, | |
921 | .device = PCI_DEVICE_ID_INTEL_BSW_EMMC, | |
922 | .subvendor = PCI_ANY_ID, | |
923 | .subdevice = PCI_ANY_ID, | |
924 | .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc, | |
925 | }, | |
926 | ||
927 | { | |
928 | .vendor = PCI_VENDOR_ID_INTEL, | |
929 | .device = PCI_DEVICE_ID_INTEL_BSW_SDIO, | |
930 | .subvendor = PCI_ANY_ID, | |
931 | .subdevice = PCI_ANY_ID, | |
932 | .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio, | |
933 | }, | |
934 | ||
935 | { | |
936 | .vendor = PCI_VENDOR_ID_INTEL, | |
937 | .device = PCI_DEVICE_ID_INTEL_BSW_SD, | |
938 | .subvendor = PCI_ANY_ID, | |
939 | .subdevice = PCI_ANY_ID, | |
940 | .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd, | |
941 | }, | |
d052068a EE |
942 | |
943 | { | |
944 | .vendor = PCI_VENDOR_ID_INTEL, | |
945 | .device = PCI_DEVICE_ID_INTEL_CLV_SDIO0, | |
946 | .subvendor = PCI_ANY_ID, | |
947 | .subdevice = PCI_ANY_ID, | |
948 | .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sd, | |
949 | }, | |
950 | ||
951 | { | |
952 | .vendor = PCI_VENDOR_ID_INTEL, | |
953 | .device = PCI_DEVICE_ID_INTEL_CLV_SDIO1, | |
954 | .subvendor = PCI_ANY_ID, | |
955 | .subdevice = PCI_ANY_ID, | |
956 | .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sdio, | |
957 | }, | |
958 | ||
959 | { | |
960 | .vendor = PCI_VENDOR_ID_INTEL, | |
961 | .device = PCI_DEVICE_ID_INTEL_CLV_SDIO2, | |
962 | .subvendor = PCI_ANY_ID, | |
963 | .subdevice = PCI_ANY_ID, | |
964 | .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sdio, | |
965 | }, | |
966 | ||
967 | { | |
968 | .vendor = PCI_VENDOR_ID_INTEL, | |
969 | .device = PCI_DEVICE_ID_INTEL_CLV_EMMC0, | |
970 | .subvendor = PCI_ANY_ID, | |
971 | .subdevice = PCI_ANY_ID, | |
972 | .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc, | |
973 | }, | |
974 | ||
975 | { | |
976 | .vendor = PCI_VENDOR_ID_INTEL, | |
977 | .device = PCI_DEVICE_ID_INTEL_CLV_EMMC1, | |
978 | .subvendor = PCI_ANY_ID, | |
979 | .subdevice = PCI_ANY_ID, | |
980 | .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc, | |
981 | }, | |
982 | ||
8776a165 DC |
983 | { |
984 | .vendor = PCI_VENDOR_ID_INTEL, | |
985 | .device = PCI_DEVICE_ID_INTEL_MRFL_MMC, | |
986 | .subvendor = PCI_ANY_ID, | |
987 | .subdevice = PCI_ANY_ID, | |
988 | .driver_data = (kernel_ulong_t)&sdhci_intel_mrfl_mmc, | |
989 | }, | |
26daa1ed JL |
990 | { |
991 | .vendor = PCI_VENDOR_ID_O2, | |
992 | .device = PCI_DEVICE_ID_O2_8120, | |
993 | .subvendor = PCI_ANY_ID, | |
994 | .subdevice = PCI_ANY_ID, | |
995 | .driver_data = (kernel_ulong_t)&sdhci_o2, | |
996 | }, | |
997 | ||
998 | { | |
999 | .vendor = PCI_VENDOR_ID_O2, | |
1000 | .device = PCI_DEVICE_ID_O2_8220, | |
1001 | .subvendor = PCI_ANY_ID, | |
1002 | .subdevice = PCI_ANY_ID, | |
1003 | .driver_data = (kernel_ulong_t)&sdhci_o2, | |
1004 | }, | |
1005 | ||
1006 | { | |
1007 | .vendor = PCI_VENDOR_ID_O2, | |
1008 | .device = PCI_DEVICE_ID_O2_8221, | |
1009 | .subvendor = PCI_ANY_ID, | |
1010 | .subdevice = PCI_ANY_ID, | |
1011 | .driver_data = (kernel_ulong_t)&sdhci_o2, | |
1012 | }, | |
1013 | ||
1014 | { | |
1015 | .vendor = PCI_VENDOR_ID_O2, | |
1016 | .device = PCI_DEVICE_ID_O2_8320, | |
1017 | .subvendor = PCI_ANY_ID, | |
1018 | .subdevice = PCI_ANY_ID, | |
1019 | .driver_data = (kernel_ulong_t)&sdhci_o2, | |
1020 | }, | |
1021 | ||
1022 | { | |
1023 | .vendor = PCI_VENDOR_ID_O2, | |
1024 | .device = PCI_DEVICE_ID_O2_8321, | |
1025 | .subvendor = PCI_ANY_ID, | |
1026 | .subdevice = PCI_ANY_ID, | |
1027 | .driver_data = (kernel_ulong_t)&sdhci_o2, | |
1028 | }, | |
1029 | ||
01acf691 AL |
1030 | { |
1031 | .vendor = PCI_VENDOR_ID_O2, | |
1032 | .device = PCI_DEVICE_ID_O2_FUJIN2, | |
1033 | .subvendor = PCI_ANY_ID, | |
1034 | .subdevice = PCI_ANY_ID, | |
1035 | .driver_data = (kernel_ulong_t)&sdhci_o2, | |
1036 | }, | |
1037 | ||
1038 | { | |
1039 | .vendor = PCI_VENDOR_ID_O2, | |
1040 | .device = PCI_DEVICE_ID_O2_SDS0, | |
1041 | .subvendor = PCI_ANY_ID, | |
1042 | .subdevice = PCI_ANY_ID, | |
1043 | .driver_data = (kernel_ulong_t)&sdhci_o2, | |
1044 | }, | |
1045 | ||
1046 | { | |
1047 | .vendor = PCI_VENDOR_ID_O2, | |
1048 | .device = PCI_DEVICE_ID_O2_SDS1, | |
1049 | .subvendor = PCI_ANY_ID, | |
1050 | .subdevice = PCI_ANY_ID, | |
1051 | .driver_data = (kernel_ulong_t)&sdhci_o2, | |
1052 | }, | |
1053 | ||
1054 | { | |
1055 | .vendor = PCI_VENDOR_ID_O2, | |
1056 | .device = PCI_DEVICE_ID_O2_SEABIRD0, | |
1057 | .subvendor = PCI_ANY_ID, | |
1058 | .subdevice = PCI_ANY_ID, | |
1059 | .driver_data = (kernel_ulong_t)&sdhci_o2, | |
1060 | }, | |
1061 | ||
1062 | { | |
1063 | .vendor = PCI_VENDOR_ID_O2, | |
1064 | .device = PCI_DEVICE_ID_O2_SEABIRD1, | |
1065 | .subvendor = PCI_ANY_ID, | |
1066 | .subdevice = PCI_ANY_ID, | |
1067 | .driver_data = (kernel_ulong_t)&sdhci_o2, | |
1068 | }, | |
d44f88da VW |
1069 | { |
1070 | .vendor = PCI_VENDOR_ID_AMD, | |
1071 | .device = PCI_ANY_ID, | |
1072 | .class = PCI_CLASS_SYSTEM_SDHCI << 8, | |
1073 | .class_mask = 0xFFFF00, | |
1074 | .subvendor = PCI_ANY_ID, | |
1075 | .subdevice = PCI_ANY_ID, | |
1076 | .driver_data = (kernel_ulong_t)&sdhci_amd, | |
1077 | }, | |
b8c86fc5 PO |
1078 | { /* Generic SD host controller */ |
1079 | PCI_DEVICE_CLASS((PCI_CLASS_SYSTEM_SDHCI << 8), 0xFFFF00) | |
1080 | }, | |
1081 | ||
1082 | { /* end: all zeroes */ }, | |
1083 | }; | |
1084 | ||
1085 | MODULE_DEVICE_TABLE(pci, pci_ids); | |
1086 | ||
b8c86fc5 PO |
1087 | /*****************************************************************************\ |
1088 | * * | |
1089 | * SDHCI core callbacks * | |
1090 | * * | |
1091 | \*****************************************************************************/ | |
1092 | ||
1093 | static int sdhci_pci_enable_dma(struct sdhci_host *host) | |
1094 | { | |
1095 | struct sdhci_pci_slot *slot; | |
1096 | struct pci_dev *pdev; | |
3828ecaa | 1097 | int ret = -1; |
b8c86fc5 PO |
1098 | |
1099 | slot = sdhci_priv(host); | |
1100 | pdev = slot->chip->pdev; | |
1101 | ||
1102 | if (((pdev->class & 0xFFFF00) == (PCI_CLASS_SYSTEM_SDHCI << 8)) && | |
1103 | ((pdev->class & 0x0000FF) != PCI_SDHCI_IFDMA) && | |
a13abc7b | 1104 | (host->flags & SDHCI_USE_SDMA)) { |
b8c86fc5 PO |
1105 | dev_warn(&pdev->dev, "Will use DMA mode even though HW " |
1106 | "doesn't fully claim to support it.\n"); | |
1107 | } | |
1108 | ||
3828ecaa AH |
1109 | if (host->flags & SDHCI_USE_64_BIT_DMA) { |
1110 | if (host->quirks2 & SDHCI_QUIRK2_BROKEN_64_BIT_DMA) { | |
1111 | host->flags &= ~SDHCI_USE_64_BIT_DMA; | |
1112 | } else { | |
1113 | ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(64)); | |
1114 | if (ret) | |
1115 | dev_warn(&pdev->dev, "Failed to set 64-bit DMA mask\n"); | |
1116 | } | |
1117 | } | |
1118 | if (ret) | |
1119 | ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); | |
b8c86fc5 PO |
1120 | if (ret) |
1121 | return ret; | |
1122 | ||
1123 | pci_set_master(pdev); | |
1124 | ||
1125 | return 0; | |
1126 | } | |
1127 | ||
2317f56c | 1128 | static void sdhci_pci_set_bus_width(struct sdhci_host *host, int width) |
68077b02 ML |
1129 | { |
1130 | u8 ctrl; | |
1131 | ||
1132 | ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); | |
1133 | ||
1134 | switch (width) { | |
1135 | case MMC_BUS_WIDTH_8: | |
1136 | ctrl |= SDHCI_CTRL_8BITBUS; | |
1137 | ctrl &= ~SDHCI_CTRL_4BITBUS; | |
1138 | break; | |
1139 | case MMC_BUS_WIDTH_4: | |
1140 | ctrl |= SDHCI_CTRL_4BITBUS; | |
1141 | ctrl &= ~SDHCI_CTRL_8BITBUS; | |
1142 | break; | |
1143 | default: | |
1144 | ctrl &= ~(SDHCI_CTRL_8BITBUS | SDHCI_CTRL_4BITBUS); | |
1145 | break; | |
1146 | } | |
1147 | ||
1148 | sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); | |
68077b02 ML |
1149 | } |
1150 | ||
c9faff6c | 1151 | static void sdhci_pci_gpio_hw_reset(struct sdhci_host *host) |
0f201655 AH |
1152 | { |
1153 | struct sdhci_pci_slot *slot = sdhci_priv(host); | |
1154 | int rst_n_gpio = slot->rst_n_gpio; | |
1155 | ||
1156 | if (!gpio_is_valid(rst_n_gpio)) | |
1157 | return; | |
1158 | gpio_set_value_cansleep(rst_n_gpio, 0); | |
1159 | /* For eMMC, minimum is 1us but give it 10us for good measure */ | |
1160 | udelay(10); | |
1161 | gpio_set_value_cansleep(rst_n_gpio, 1); | |
1162 | /* For eMMC, minimum is 200us but give it 300us for good measure */ | |
1163 | usleep_range(300, 1000); | |
1164 | } | |
1165 | ||
c9faff6c AH |
1166 | static void sdhci_pci_hw_reset(struct sdhci_host *host) |
1167 | { | |
1168 | struct sdhci_pci_slot *slot = sdhci_priv(host); | |
1169 | ||
1170 | if (slot->hw_reset) | |
1171 | slot->hw_reset(host); | |
1172 | } | |
1173 | ||
c915568d | 1174 | static const struct sdhci_ops sdhci_pci_ops = { |
1771059c | 1175 | .set_clock = sdhci_set_clock, |
b8c86fc5 | 1176 | .enable_dma = sdhci_pci_enable_dma, |
2317f56c | 1177 | .set_bus_width = sdhci_pci_set_bus_width, |
03231f9b | 1178 | .reset = sdhci_reset, |
96d7b78c | 1179 | .set_uhs_signaling = sdhci_set_uhs_signaling, |
0f201655 | 1180 | .hw_reset = sdhci_pci_hw_reset, |
b8c86fc5 PO |
1181 | }; |
1182 | ||
1183 | /*****************************************************************************\ | |
1184 | * * | |
1185 | * Suspend/resume * | |
1186 | * * | |
1187 | \*****************************************************************************/ | |
1188 | ||
1189 | #ifdef CONFIG_PM | |
1190 | ||
29495aa0 | 1191 | static int sdhci_pci_suspend(struct device *dev) |
b8c86fc5 | 1192 | { |
29495aa0 | 1193 | struct pci_dev *pdev = to_pci_dev(dev); |
b8c86fc5 PO |
1194 | struct sdhci_pci_chip *chip; |
1195 | struct sdhci_pci_slot *slot; | |
5f619704 | 1196 | mmc_pm_flag_t slot_pm_flags; |
2f4cbb3d | 1197 | mmc_pm_flag_t pm_flags = 0; |
b8c86fc5 PO |
1198 | int i, ret; |
1199 | ||
1200 | chip = pci_get_drvdata(pdev); | |
1201 | if (!chip) | |
1202 | return 0; | |
1203 | ||
b177bc91 | 1204 | for (i = 0; i < chip->num_slots; i++) { |
b8c86fc5 PO |
1205 | slot = chip->slots[i]; |
1206 | if (!slot) | |
1207 | continue; | |
1208 | ||
29495aa0 | 1209 | ret = sdhci_suspend_host(slot->host); |
b8c86fc5 | 1210 | |
b678b91f AL |
1211 | if (ret) |
1212 | goto err_pci_suspend; | |
2f4cbb3d | 1213 | |
5f619704 DD |
1214 | slot_pm_flags = slot->host->mmc->pm_flags; |
1215 | if (slot_pm_flags & MMC_PM_WAKE_SDIO_IRQ) | |
1216 | sdhci_enable_irq_wakeups(slot->host); | |
1217 | ||
1218 | pm_flags |= slot_pm_flags; | |
b8c86fc5 PO |
1219 | } |
1220 | ||
4489428a | 1221 | if (chip->fixes && chip->fixes->suspend) { |
29495aa0 | 1222 | ret = chip->fixes->suspend(chip); |
b678b91f AL |
1223 | if (ret) |
1224 | goto err_pci_suspend; | |
4489428a PO |
1225 | } |
1226 | ||
2f4cbb3d | 1227 | if (pm_flags & MMC_PM_KEEP_POWER) { |
6b91f2d4 CD |
1228 | if (pm_flags & MMC_PM_WAKE_SDIO_IRQ) |
1229 | device_init_wakeup(dev, true); | |
1230 | else | |
1231 | device_init_wakeup(dev, false); | |
1232 | } else | |
1233 | device_init_wakeup(dev, false); | |
b8c86fc5 PO |
1234 | |
1235 | return 0; | |
b678b91f AL |
1236 | |
1237 | err_pci_suspend: | |
1238 | while (--i >= 0) | |
1239 | sdhci_resume_host(chip->slots[i]->host); | |
1240 | return ret; | |
b8c86fc5 PO |
1241 | } |
1242 | ||
29495aa0 | 1243 | static int sdhci_pci_resume(struct device *dev) |
b8c86fc5 | 1244 | { |
29495aa0 | 1245 | struct pci_dev *pdev = to_pci_dev(dev); |
b8c86fc5 PO |
1246 | struct sdhci_pci_chip *chip; |
1247 | struct sdhci_pci_slot *slot; | |
1248 | int i, ret; | |
1249 | ||
1250 | chip = pci_get_drvdata(pdev); | |
1251 | if (!chip) | |
1252 | return 0; | |
1253 | ||
45211e21 PO |
1254 | if (chip->fixes && chip->fixes->resume) { |
1255 | ret = chip->fixes->resume(chip); | |
1256 | if (ret) | |
1257 | return ret; | |
1258 | } | |
1259 | ||
b177bc91 | 1260 | for (i = 0; i < chip->num_slots; i++) { |
b8c86fc5 PO |
1261 | slot = chip->slots[i]; |
1262 | if (!slot) | |
1263 | continue; | |
1264 | ||
1265 | ret = sdhci_resume_host(slot->host); | |
1266 | if (ret) | |
1267 | return ret; | |
1268 | } | |
1269 | ||
1270 | return 0; | |
1271 | } | |
1272 | ||
1273 | #else /* CONFIG_PM */ | |
1274 | ||
1275 | #define sdhci_pci_suspend NULL | |
1276 | #define sdhci_pci_resume NULL | |
1277 | ||
1278 | #endif /* CONFIG_PM */ | |
1279 | ||
66fd8ad5 AH |
1280 | #ifdef CONFIG_PM_RUNTIME |
1281 | ||
1282 | static int sdhci_pci_runtime_suspend(struct device *dev) | |
1283 | { | |
1284 | struct pci_dev *pdev = container_of(dev, struct pci_dev, dev); | |
1285 | struct sdhci_pci_chip *chip; | |
1286 | struct sdhci_pci_slot *slot; | |
66fd8ad5 AH |
1287 | int i, ret; |
1288 | ||
1289 | chip = pci_get_drvdata(pdev); | |
1290 | if (!chip) | |
1291 | return 0; | |
1292 | ||
1293 | for (i = 0; i < chip->num_slots; i++) { | |
1294 | slot = chip->slots[i]; | |
1295 | if (!slot) | |
1296 | continue; | |
1297 | ||
1298 | ret = sdhci_runtime_suspend_host(slot->host); | |
1299 | ||
b678b91f AL |
1300 | if (ret) |
1301 | goto err_pci_runtime_suspend; | |
66fd8ad5 AH |
1302 | } |
1303 | ||
1304 | if (chip->fixes && chip->fixes->suspend) { | |
29495aa0 | 1305 | ret = chip->fixes->suspend(chip); |
b678b91f AL |
1306 | if (ret) |
1307 | goto err_pci_runtime_suspend; | |
66fd8ad5 AH |
1308 | } |
1309 | ||
1310 | return 0; | |
b678b91f AL |
1311 | |
1312 | err_pci_runtime_suspend: | |
1313 | while (--i >= 0) | |
1314 | sdhci_runtime_resume_host(chip->slots[i]->host); | |
1315 | return ret; | |
66fd8ad5 AH |
1316 | } |
1317 | ||
1318 | static int sdhci_pci_runtime_resume(struct device *dev) | |
1319 | { | |
1320 | struct pci_dev *pdev = container_of(dev, struct pci_dev, dev); | |
1321 | struct sdhci_pci_chip *chip; | |
1322 | struct sdhci_pci_slot *slot; | |
1323 | int i, ret; | |
1324 | ||
1325 | chip = pci_get_drvdata(pdev); | |
1326 | if (!chip) | |
1327 | return 0; | |
1328 | ||
1329 | if (chip->fixes && chip->fixes->resume) { | |
1330 | ret = chip->fixes->resume(chip); | |
1331 | if (ret) | |
1332 | return ret; | |
1333 | } | |
1334 | ||
1335 | for (i = 0; i < chip->num_slots; i++) { | |
1336 | slot = chip->slots[i]; | |
1337 | if (!slot) | |
1338 | continue; | |
1339 | ||
1340 | ret = sdhci_runtime_resume_host(slot->host); | |
1341 | if (ret) | |
1342 | return ret; | |
1343 | } | |
1344 | ||
1345 | return 0; | |
1346 | } | |
1347 | ||
1348 | static int sdhci_pci_runtime_idle(struct device *dev) | |
1349 | { | |
1350 | return 0; | |
1351 | } | |
1352 | ||
66fd8ad5 AH |
1353 | #endif |
1354 | ||
1355 | static const struct dev_pm_ops sdhci_pci_pm_ops = { | |
29495aa0 ML |
1356 | .suspend = sdhci_pci_suspend, |
1357 | .resume = sdhci_pci_resume, | |
f3a92b1a PG |
1358 | SET_RUNTIME_PM_OPS(sdhci_pci_runtime_suspend, |
1359 | sdhci_pci_runtime_resume, sdhci_pci_runtime_idle) | |
66fd8ad5 AH |
1360 | }; |
1361 | ||
b8c86fc5 PO |
1362 | /*****************************************************************************\ |
1363 | * * | |
1364 | * Device probing/removal * | |
1365 | * * | |
1366 | \*****************************************************************************/ | |
1367 | ||
c3be1efd | 1368 | static struct sdhci_pci_slot *sdhci_pci_probe_slot( |
52c506f0 AH |
1369 | struct pci_dev *pdev, struct sdhci_pci_chip *chip, int first_bar, |
1370 | int slotno) | |
b8c86fc5 PO |
1371 | { |
1372 | struct sdhci_pci_slot *slot; | |
1373 | struct sdhci_host *host; | |
52c506f0 | 1374 | int ret, bar = first_bar + slotno; |
b8c86fc5 PO |
1375 | |
1376 | if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) { | |
1377 | dev_err(&pdev->dev, "BAR %d is not iomem. Aborting.\n", bar); | |
1378 | return ERR_PTR(-ENODEV); | |
1379 | } | |
1380 | ||
90b3e6c5 | 1381 | if (pci_resource_len(pdev, bar) < 0x100) { |
b8c86fc5 PO |
1382 | dev_err(&pdev->dev, "Invalid iomem size. You may " |
1383 | "experience problems.\n"); | |
1384 | } | |
1385 | ||
1386 | if ((pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) { | |
1387 | dev_err(&pdev->dev, "Vendor specific interface. Aborting.\n"); | |
1388 | return ERR_PTR(-ENODEV); | |
1389 | } | |
1390 | ||
1391 | if ((pdev->class & 0x0000FF) > PCI_SDHCI_IFVENDOR) { | |
1392 | dev_err(&pdev->dev, "Unknown interface. Aborting.\n"); | |
1393 | return ERR_PTR(-ENODEV); | |
1394 | } | |
1395 | ||
1396 | host = sdhci_alloc_host(&pdev->dev, sizeof(struct sdhci_pci_slot)); | |
1397 | if (IS_ERR(host)) { | |
c60a32cd | 1398 | dev_err(&pdev->dev, "cannot allocate host\n"); |
dc0fd7b5 | 1399 | return ERR_CAST(host); |
b8c86fc5 PO |
1400 | } |
1401 | ||
1402 | slot = sdhci_priv(host); | |
1403 | ||
1404 | slot->chip = chip; | |
1405 | slot->host = host; | |
1406 | slot->pci_bar = bar; | |
0f201655 | 1407 | slot->rst_n_gpio = -EINVAL; |
c5e027a4 | 1408 | slot->cd_gpio = -EINVAL; |
ff59c520 | 1409 | slot->cd_idx = -1; |
b8c86fc5 | 1410 | |
52c506f0 AH |
1411 | /* Retrieve platform data if there is any */ |
1412 | if (*sdhci_pci_get_data) | |
1413 | slot->data = sdhci_pci_get_data(pdev, slotno); | |
1414 | ||
1415 | if (slot->data) { | |
1416 | if (slot->data->setup) { | |
1417 | ret = slot->data->setup(slot->data); | |
1418 | if (ret) { | |
1419 | dev_err(&pdev->dev, "platform setup failed\n"); | |
1420 | goto free; | |
1421 | } | |
1422 | } | |
c5e027a4 AH |
1423 | slot->rst_n_gpio = slot->data->rst_n_gpio; |
1424 | slot->cd_gpio = slot->data->cd_gpio; | |
52c506f0 AH |
1425 | } |
1426 | ||
b8c86fc5 PO |
1427 | host->hw_name = "PCI"; |
1428 | host->ops = &sdhci_pci_ops; | |
1429 | host->quirks = chip->quirks; | |
f3c55a7b | 1430 | host->quirks2 = chip->quirks2; |
b8c86fc5 PO |
1431 | |
1432 | host->irq = pdev->irq; | |
1433 | ||
1434 | ret = pci_request_region(pdev, bar, mmc_hostname(host->mmc)); | |
1435 | if (ret) { | |
1436 | dev_err(&pdev->dev, "cannot request region\n"); | |
52c506f0 | 1437 | goto cleanup; |
b8c86fc5 PO |
1438 | } |
1439 | ||
092f82ed | 1440 | host->ioaddr = pci_ioremap_bar(pdev, bar); |
b8c86fc5 PO |
1441 | if (!host->ioaddr) { |
1442 | dev_err(&pdev->dev, "failed to remap registers\n"); | |
9fdcdbb0 | 1443 | ret = -ENOMEM; |
b8c86fc5 PO |
1444 | goto release; |
1445 | } | |
1446 | ||
4489428a PO |
1447 | if (chip->fixes && chip->fixes->probe_slot) { |
1448 | ret = chip->fixes->probe_slot(slot); | |
1449 | if (ret) | |
1450 | goto unmap; | |
1451 | } | |
1452 | ||
c5e027a4 AH |
1453 | if (gpio_is_valid(slot->rst_n_gpio)) { |
1454 | if (!gpio_request(slot->rst_n_gpio, "eMMC_reset")) { | |
1455 | gpio_direction_output(slot->rst_n_gpio, 1); | |
1456 | slot->host->mmc->caps |= MMC_CAP_HW_RESET; | |
c9faff6c | 1457 | slot->hw_reset = sdhci_pci_gpio_hw_reset; |
c5e027a4 AH |
1458 | } else { |
1459 | dev_warn(&pdev->dev, "failed to request rst_n_gpio\n"); | |
1460 | slot->rst_n_gpio = -EINVAL; | |
1461 | } | |
1462 | } | |
1463 | ||
2f4cbb3d | 1464 | host->mmc->pm_caps = MMC_PM_KEEP_POWER | MMC_PM_WAKE_SDIO_IRQ; |
eed222ac | 1465 | host->mmc->slotno = slotno; |
a08b17be | 1466 | host->mmc->caps2 |= MMC_CAP2_NO_PRESCAN_POWERUP; |
2f4cbb3d | 1467 | |
ff59c520 AH |
1468 | if (slot->cd_idx >= 0 && |
1469 | mmc_gpiod_request_cd(host->mmc, slot->cd_con_id, slot->cd_idx, | |
1470 | slot->cd_override_level, 0, NULL)) { | |
1471 | dev_warn(&pdev->dev, "failed to setup card detect gpio\n"); | |
1472 | slot->cd_idx = -1; | |
1473 | } | |
1474 | ||
b8c86fc5 PO |
1475 | ret = sdhci_add_host(host); |
1476 | if (ret) | |
4489428a | 1477 | goto remove; |
b8c86fc5 | 1478 | |
c5e027a4 AH |
1479 | sdhci_pci_add_own_cd(slot); |
1480 | ||
77a0122e AH |
1481 | /* |
1482 | * Check if the chip needs a separate GPIO for card detect to wake up | |
1483 | * from runtime suspend. If it is not there, don't allow runtime PM. | |
1484 | * Note sdhci_pci_add_own_cd() sets slot->cd_gpio to -EINVAL on failure. | |
1485 | */ | |
945be38c | 1486 | if (chip->fixes && chip->fixes->own_cd_for_runtime_pm && |
ff59c520 | 1487 | !gpio_is_valid(slot->cd_gpio) && slot->cd_idx < 0) |
77a0122e AH |
1488 | chip->allow_runtime_pm = false; |
1489 | ||
b8c86fc5 PO |
1490 | return slot; |
1491 | ||
4489428a | 1492 | remove: |
c5e027a4 AH |
1493 | if (gpio_is_valid(slot->rst_n_gpio)) |
1494 | gpio_free(slot->rst_n_gpio); | |
1495 | ||
4489428a | 1496 | if (chip->fixes && chip->fixes->remove_slot) |
1e72859e | 1497 | chip->fixes->remove_slot(slot, 0); |
4489428a | 1498 | |
b8c86fc5 PO |
1499 | unmap: |
1500 | iounmap(host->ioaddr); | |
1501 | ||
1502 | release: | |
1503 | pci_release_region(pdev, bar); | |
c60a32cd | 1504 | |
52c506f0 AH |
1505 | cleanup: |
1506 | if (slot->data && slot->data->cleanup) | |
1507 | slot->data->cleanup(slot->data); | |
1508 | ||
c60a32cd | 1509 | free: |
b8c86fc5 PO |
1510 | sdhci_free_host(host); |
1511 | ||
1512 | return ERR_PTR(ret); | |
1513 | } | |
1514 | ||
1515 | static void sdhci_pci_remove_slot(struct sdhci_pci_slot *slot) | |
1516 | { | |
1e72859e PO |
1517 | int dead; |
1518 | u32 scratch; | |
1519 | ||
c5e027a4 AH |
1520 | sdhci_pci_remove_own_cd(slot); |
1521 | ||
1e72859e PO |
1522 | dead = 0; |
1523 | scratch = readl(slot->host->ioaddr + SDHCI_INT_STATUS); | |
1524 | if (scratch == (u32)-1) | |
1525 | dead = 1; | |
1526 | ||
1527 | sdhci_remove_host(slot->host, dead); | |
4489428a | 1528 | |
c5e027a4 AH |
1529 | if (gpio_is_valid(slot->rst_n_gpio)) |
1530 | gpio_free(slot->rst_n_gpio); | |
1531 | ||
4489428a | 1532 | if (slot->chip->fixes && slot->chip->fixes->remove_slot) |
1e72859e | 1533 | slot->chip->fixes->remove_slot(slot, dead); |
4489428a | 1534 | |
52c506f0 AH |
1535 | if (slot->data && slot->data->cleanup) |
1536 | slot->data->cleanup(slot->data); | |
1537 | ||
b8c86fc5 | 1538 | pci_release_region(slot->chip->pdev, slot->pci_bar); |
4489428a | 1539 | |
b8c86fc5 PO |
1540 | sdhci_free_host(slot->host); |
1541 | } | |
1542 | ||
c3be1efd | 1543 | static void sdhci_pci_runtime_pm_allow(struct device *dev) |
66fd8ad5 AH |
1544 | { |
1545 | pm_runtime_put_noidle(dev); | |
1546 | pm_runtime_allow(dev); | |
1547 | pm_runtime_set_autosuspend_delay(dev, 50); | |
1548 | pm_runtime_use_autosuspend(dev); | |
1549 | pm_suspend_ignore_children(dev, 1); | |
1550 | } | |
1551 | ||
6e0ee714 | 1552 | static void sdhci_pci_runtime_pm_forbid(struct device *dev) |
66fd8ad5 AH |
1553 | { |
1554 | pm_runtime_forbid(dev); | |
1555 | pm_runtime_get_noresume(dev); | |
1556 | } | |
1557 | ||
c3be1efd | 1558 | static int sdhci_pci_probe(struct pci_dev *pdev, |
b8c86fc5 PO |
1559 | const struct pci_device_id *ent) |
1560 | { | |
1561 | struct sdhci_pci_chip *chip; | |
1562 | struct sdhci_pci_slot *slot; | |
1563 | ||
cf5e23e1 | 1564 | u8 slots, first_bar; |
b8c86fc5 PO |
1565 | int ret, i; |
1566 | ||
1567 | BUG_ON(pdev == NULL); | |
1568 | BUG_ON(ent == NULL); | |
1569 | ||
b8c86fc5 | 1570 | dev_info(&pdev->dev, "SDHCI controller found [%04x:%04x] (rev %x)\n", |
cf5e23e1 | 1571 | (int)pdev->vendor, (int)pdev->device, (int)pdev->revision); |
b8c86fc5 PO |
1572 | |
1573 | ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &slots); | |
1574 | if (ret) | |
1575 | return ret; | |
1576 | ||
1577 | slots = PCI_SLOT_INFO_SLOTS(slots) + 1; | |
1578 | dev_dbg(&pdev->dev, "found %d slot(s)\n", slots); | |
1579 | if (slots == 0) | |
1580 | return -ENODEV; | |
1581 | ||
1582 | BUG_ON(slots > MAX_SLOTS); | |
1583 | ||
1584 | ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &first_bar); | |
1585 | if (ret) | |
1586 | return ret; | |
1587 | ||
1588 | first_bar &= PCI_SLOT_INFO_FIRST_BAR_MASK; | |
1589 | ||
1590 | if (first_bar > 5) { | |
1591 | dev_err(&pdev->dev, "Invalid first BAR. Aborting.\n"); | |
1592 | return -ENODEV; | |
1593 | } | |
1594 | ||
1595 | ret = pci_enable_device(pdev); | |
1596 | if (ret) | |
1597 | return ret; | |
1598 | ||
1599 | chip = kzalloc(sizeof(struct sdhci_pci_chip), GFP_KERNEL); | |
1600 | if (!chip) { | |
1601 | ret = -ENOMEM; | |
1602 | goto err; | |
1603 | } | |
1604 | ||
1605 | chip->pdev = pdev; | |
b177bc91 | 1606 | chip->fixes = (const struct sdhci_pci_fixes *)ent->driver_data; |
c43fd774 | 1607 | if (chip->fixes) { |
22606405 | 1608 | chip->quirks = chip->fixes->quirks; |
f3c55a7b | 1609 | chip->quirks2 = chip->fixes->quirks2; |
c43fd774 AH |
1610 | chip->allow_runtime_pm = chip->fixes->allow_runtime_pm; |
1611 | } | |
b8c86fc5 PO |
1612 | chip->num_slots = slots; |
1613 | ||
1614 | pci_set_drvdata(pdev, chip); | |
1615 | ||
22606405 PO |
1616 | if (chip->fixes && chip->fixes->probe) { |
1617 | ret = chip->fixes->probe(chip); | |
1618 | if (ret) | |
1619 | goto free; | |
1620 | } | |
1621 | ||
225d85fe AC |
1622 | slots = chip->num_slots; /* Quirk may have changed this */ |
1623 | ||
b177bc91 | 1624 | for (i = 0; i < slots; i++) { |
52c506f0 | 1625 | slot = sdhci_pci_probe_slot(pdev, chip, first_bar, i); |
b8c86fc5 | 1626 | if (IS_ERR(slot)) { |
b177bc91 | 1627 | for (i--; i >= 0; i--) |
b8c86fc5 PO |
1628 | sdhci_pci_remove_slot(chip->slots[i]); |
1629 | ret = PTR_ERR(slot); | |
1630 | goto free; | |
1631 | } | |
1632 | ||
1633 | chip->slots[i] = slot; | |
1634 | } | |
1635 | ||
c43fd774 AH |
1636 | if (chip->allow_runtime_pm) |
1637 | sdhci_pci_runtime_pm_allow(&pdev->dev); | |
66fd8ad5 | 1638 | |
b8c86fc5 PO |
1639 | return 0; |
1640 | ||
1641 | free: | |
1642 | pci_set_drvdata(pdev, NULL); | |
1643 | kfree(chip); | |
1644 | ||
1645 | err: | |
1646 | pci_disable_device(pdev); | |
1647 | return ret; | |
1648 | } | |
1649 | ||
6e0ee714 | 1650 | static void sdhci_pci_remove(struct pci_dev *pdev) |
b8c86fc5 PO |
1651 | { |
1652 | int i; | |
1653 | struct sdhci_pci_chip *chip; | |
1654 | ||
1655 | chip = pci_get_drvdata(pdev); | |
1656 | ||
1657 | if (chip) { | |
c43fd774 AH |
1658 | if (chip->allow_runtime_pm) |
1659 | sdhci_pci_runtime_pm_forbid(&pdev->dev); | |
1660 | ||
b177bc91 | 1661 | for (i = 0; i < chip->num_slots; i++) |
b8c86fc5 PO |
1662 | sdhci_pci_remove_slot(chip->slots[i]); |
1663 | ||
1664 | pci_set_drvdata(pdev, NULL); | |
1665 | kfree(chip); | |
1666 | } | |
1667 | ||
1668 | pci_disable_device(pdev); | |
1669 | } | |
1670 | ||
1671 | static struct pci_driver sdhci_driver = { | |
b177bc91 | 1672 | .name = "sdhci-pci", |
b8c86fc5 | 1673 | .id_table = pci_ids, |
b177bc91 | 1674 | .probe = sdhci_pci_probe, |
0433c143 | 1675 | .remove = sdhci_pci_remove, |
66fd8ad5 AH |
1676 | .driver = { |
1677 | .pm = &sdhci_pci_pm_ops | |
1678 | }, | |
b8c86fc5 PO |
1679 | }; |
1680 | ||
acc69646 | 1681 | module_pci_driver(sdhci_driver); |
b8c86fc5 | 1682 | |
32710e8f | 1683 | MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>"); |
b8c86fc5 PO |
1684 | MODULE_DESCRIPTION("Secure Digital Host Controller Interface PCI driver"); |
1685 | MODULE_LICENSE("GPL"); |