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522624f9 AL |
1 | #ifndef __SDHCI_PCI_H |
2 | #define __SDHCI_PCI_H | |
3 | ||
4 | /* | |
5 | * PCI device IDs | |
6 | */ | |
7 | ||
8 | #define PCI_DEVICE_ID_INTEL_PCH_SDIO0 0x8809 | |
9 | #define PCI_DEVICE_ID_INTEL_PCH_SDIO1 0x880a | |
10 | #define PCI_DEVICE_ID_INTEL_BYT_EMMC 0x0f14 | |
11 | #define PCI_DEVICE_ID_INTEL_BYT_SDIO 0x0f15 | |
12 | #define PCI_DEVICE_ID_INTEL_BYT_SD 0x0f16 | |
13 | #define PCI_DEVICE_ID_INTEL_BYT_EMMC2 0x0f50 | |
066173b6 AC |
14 | #define PCI_DEVICE_ID_INTEL_BSW_EMMC 0x2294 |
15 | #define PCI_DEVICE_ID_INTEL_BSW_SDIO 0x2295 | |
16 | #define PCI_DEVICE_ID_INTEL_BSW_SD 0x2296 | |
1f64cec2 | 17 | #define PCI_DEVICE_ID_INTEL_MRFLD_MMC 0x1190 |
522624f9 AL |
18 | #define PCI_DEVICE_ID_INTEL_CLV_SDIO0 0x08f9 |
19 | #define PCI_DEVICE_ID_INTEL_CLV_SDIO1 0x08fa | |
20 | #define PCI_DEVICE_ID_INTEL_CLV_SDIO2 0x08fb | |
21 | #define PCI_DEVICE_ID_INTEL_CLV_EMMC0 0x08e5 | |
22 | #define PCI_DEVICE_ID_INTEL_CLV_EMMC1 0x08e6 | |
43e968ce | 23 | #define PCI_DEVICE_ID_INTEL_QRK_SD 0x08A7 |
1f7f2652 AH |
24 | #define PCI_DEVICE_ID_INTEL_SPT_EMMC 0x9d2b |
25 | #define PCI_DEVICE_ID_INTEL_SPT_SDIO 0x9d2c | |
26 | #define PCI_DEVICE_ID_INTEL_SPT_SD 0x9d2d | |
06bf9c56 | 27 | #define PCI_DEVICE_ID_INTEL_DNV_EMMC 0x19db |
4fd4c065 AH |
28 | #define PCI_DEVICE_ID_INTEL_BXT_SD 0x0aca |
29 | #define PCI_DEVICE_ID_INTEL_BXT_EMMC 0x0acc | |
30 | #define PCI_DEVICE_ID_INTEL_BXT_SDIO 0x0ad0 | |
01d6b2a4 AH |
31 | #define PCI_DEVICE_ID_INTEL_BXTM_SD 0x1aca |
32 | #define PCI_DEVICE_ID_INTEL_BXTM_EMMC 0x1acc | |
33 | #define PCI_DEVICE_ID_INTEL_BXTM_SDIO 0x1ad0 | |
4fd4c065 AH |
34 | #define PCI_DEVICE_ID_INTEL_APL_SD 0x5aca |
35 | #define PCI_DEVICE_ID_INTEL_APL_EMMC 0x5acc | |
36 | #define PCI_DEVICE_ID_INTEL_APL_SDIO 0x5ad0 | |
522624f9 AL |
37 | |
38 | /* | |
39 | * PCI registers | |
40 | */ | |
41 | ||
42 | #define PCI_SDHCI_IFPIO 0x00 | |
43 | #define PCI_SDHCI_IFDMA 0x01 | |
44 | #define PCI_SDHCI_IFVENDOR 0x02 | |
45 | ||
46 | #define PCI_SLOT_INFO 0x40 /* 8 bits */ | |
47 | #define PCI_SLOT_INFO_SLOTS(x) ((x >> 4) & 7) | |
48 | #define PCI_SLOT_INFO_FIRST_BAR_MASK 0x07 | |
49 | ||
50 | #define MAX_SLOTS 8 | |
51 | ||
52 | struct sdhci_pci_chip; | |
53 | struct sdhci_pci_slot; | |
54 | ||
55 | struct sdhci_pci_fixes { | |
56 | unsigned int quirks; | |
57 | unsigned int quirks2; | |
58 | bool allow_runtime_pm; | |
77a0122e | 59 | bool own_cd_for_runtime_pm; |
522624f9 AL |
60 | |
61 | int (*probe) (struct sdhci_pci_chip *); | |
62 | ||
63 | int (*probe_slot) (struct sdhci_pci_slot *); | |
64 | void (*remove_slot) (struct sdhci_pci_slot *, int); | |
65 | ||
66 | int (*suspend) (struct sdhci_pci_chip *); | |
67 | int (*resume) (struct sdhci_pci_chip *); | |
6bc09063 AH |
68 | |
69 | const struct sdhci_ops *ops; | |
522624f9 AL |
70 | }; |
71 | ||
72 | struct sdhci_pci_slot { | |
73 | struct sdhci_pci_chip *chip; | |
74 | struct sdhci_host *host; | |
75 | struct sdhci_pci_data *data; | |
76 | ||
522624f9 AL |
77 | int rst_n_gpio; |
78 | int cd_gpio; | |
79 | int cd_irq; | |
80 | ||
ff59c520 AH |
81 | char *cd_con_id; |
82 | int cd_idx; | |
83 | bool cd_override_level; | |
84 | ||
522624f9 | 85 | void (*hw_reset)(struct sdhci_host *host); |
e1bfad6d AH |
86 | int (*select_drive_strength)(struct sdhci_host *host, |
87 | struct mmc_card *card, | |
88 | unsigned int max_dtr, int host_drv, | |
89 | int card_drv, int *drv_type); | |
522624f9 AL |
90 | }; |
91 | ||
92 | struct sdhci_pci_chip { | |
93 | struct pci_dev *pdev; | |
94 | ||
95 | unsigned int quirks; | |
96 | unsigned int quirks2; | |
97 | bool allow_runtime_pm; | |
98 | const struct sdhci_pci_fixes *fixes; | |
99 | ||
100 | int num_slots; /* Slots on controller */ | |
101 | struct sdhci_pci_slot *slots[MAX_SLOTS]; /* Pointers to host slots */ | |
102 | }; | |
103 | ||
104 | #endif /* __SDHCI_PCI_H */ |