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a702c8ab ZG |
1 | /* |
2 | * Copyright (C) 2010 Marvell International Ltd. | |
3 | * Zhangfei Gao <zhangfei.gao@marvell.com> | |
4 | * Kevin Wang <dwang4@marvell.com> | |
5 | * Mingwei Wang <mwwang@marvell.com> | |
6 | * Philip Rakity <prakity@marvell.com> | |
7 | * Mark Brown <markb@marvell.com> | |
8 | * | |
9 | * This software is licensed under the terms of the GNU General Public | |
10 | * License version 2, as published by the Free Software Foundation, and | |
11 | * may be copied, distributed, and modified under those terms. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | */ | |
19 | #include <linux/err.h> | |
20 | #include <linux/init.h> | |
21 | #include <linux/platform_device.h> | |
22 | #include <linux/clk.h> | |
23 | #include <linux/io.h> | |
24 | #include <linux/gpio.h> | |
25 | #include <linux/mmc/card.h> | |
26 | #include <linux/mmc/host.h> | |
8f63795c | 27 | #include <linux/mmc/slot-gpio.h> |
bfed345e | 28 | #include <linux/platform_data/pxa_sdhci.h> |
a702c8ab ZG |
29 | #include <linux/slab.h> |
30 | #include <linux/delay.h> | |
88b47679 | 31 | #include <linux/module.h> |
b650352d CB |
32 | #include <linux/of.h> |
33 | #include <linux/of_device.h> | |
8f63795c | 34 | #include <linux/of_gpio.h> |
bb691ae4 KL |
35 | #include <linux/pm.h> |
36 | #include <linux/pm_runtime.h> | |
5491ce3f | 37 | #include <linux/mbus.h> |
b650352d | 38 | |
a702c8ab ZG |
39 | #include "sdhci.h" |
40 | #include "sdhci-pltfm.h" | |
41 | ||
bb691ae4 KL |
42 | #define PXAV3_RPM_DELAY_MS 50 |
43 | ||
a702c8ab ZG |
44 | #define SD_CLOCK_BURST_SIZE_SETUP 0x10A |
45 | #define SDCLK_SEL 0x100 | |
46 | #define SDCLK_DELAY_SHIFT 9 | |
47 | #define SDCLK_DELAY_MASK 0x1f | |
48 | ||
49 | #define SD_CFG_FIFO_PARAM 0x100 | |
50 | #define SDCFG_GEN_PAD_CLK_ON (1<<6) | |
51 | #define SDCFG_GEN_PAD_CLK_CNT_MASK 0xFF | |
52 | #define SDCFG_GEN_PAD_CLK_CNT_SHIFT 24 | |
53 | ||
54 | #define SD_SPI_MODE 0x108 | |
55 | #define SD_CE_ATA_1 0x10C | |
56 | ||
57 | #define SD_CE_ATA_2 0x10E | |
58 | #define SDCE_MISC_INT (1<<2) | |
59 | #define SDCE_MISC_INT_EN (1<<1) | |
60 | ||
cc9571e8 | 61 | struct sdhci_pxa { |
8afdc9cc | 62 | struct clk *clk_core; |
8c96a7a3 | 63 | struct clk *clk_io; |
cc9571e8 | 64 | u8 power_mode; |
1140011e | 65 | void __iomem *sdio3_conf_reg; |
cc9571e8 SH |
66 | }; |
67 | ||
5491ce3f MW |
68 | /* |
69 | * These registers are relative to the second register region, for the | |
70 | * MBus bridge. | |
71 | */ | |
72 | #define SDHCI_WINDOW_CTRL(i) (0x80 + ((i) << 3)) | |
73 | #define SDHCI_WINDOW_BASE(i) (0x84 + ((i) << 3)) | |
74 | #define SDHCI_MAX_WIN_NUM 8 | |
75 | ||
1140011e MW |
76 | /* |
77 | * Fields below belong to SDIO3 Configuration Register (third register | |
78 | * region for the Armada 38x flavor) | |
79 | */ | |
80 | ||
81 | #define SDIO3_CONF_CLK_INV BIT(0) | |
82 | #define SDIO3_CONF_SD_FB_CLK BIT(2) | |
83 | ||
5491ce3f MW |
84 | static int mv_conf_mbus_windows(struct platform_device *pdev, |
85 | const struct mbus_dram_target_info *dram) | |
86 | { | |
87 | int i; | |
88 | void __iomem *regs; | |
89 | struct resource *res; | |
90 | ||
91 | if (!dram) { | |
92 | dev_err(&pdev->dev, "no mbus dram info\n"); | |
93 | return -EINVAL; | |
94 | } | |
95 | ||
96 | res = platform_get_resource(pdev, IORESOURCE_MEM, 1); | |
97 | if (!res) { | |
98 | dev_err(&pdev->dev, "cannot get mbus registers\n"); | |
99 | return -EINVAL; | |
100 | } | |
101 | ||
102 | regs = ioremap(res->start, resource_size(res)); | |
103 | if (!regs) { | |
104 | dev_err(&pdev->dev, "cannot map mbus registers\n"); | |
105 | return -ENOMEM; | |
106 | } | |
107 | ||
108 | for (i = 0; i < SDHCI_MAX_WIN_NUM; i++) { | |
109 | writel(0, regs + SDHCI_WINDOW_CTRL(i)); | |
110 | writel(0, regs + SDHCI_WINDOW_BASE(i)); | |
111 | } | |
112 | ||
113 | for (i = 0; i < dram->num_cs; i++) { | |
114 | const struct mbus_dram_window *cs = dram->cs + i; | |
115 | ||
116 | /* Write size, attributes and target id to control register */ | |
117 | writel(((cs->size - 1) & 0xffff0000) | | |
118 | (cs->mbus_attr << 8) | | |
119 | (dram->mbus_dram_target_id << 4) | 1, | |
120 | regs + SDHCI_WINDOW_CTRL(i)); | |
121 | /* Write base address to base register */ | |
122 | writel(cs->base, regs + SDHCI_WINDOW_BASE(i)); | |
123 | } | |
124 | ||
125 | iounmap(regs); | |
126 | ||
127 | return 0; | |
128 | } | |
129 | ||
a39128bc MW |
130 | static int armada_38x_quirks(struct platform_device *pdev, |
131 | struct sdhci_host *host) | |
d4b803c5 | 132 | { |
a39128bc | 133 | struct device_node *np = pdev->dev.of_node; |
1140011e MW |
134 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
135 | struct sdhci_pxa *pxa = pltfm_host->priv; | |
136 | struct resource *res; | |
a39128bc | 137 | |
5de76bfc | 138 | host->quirks &= ~SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN; |
d4b803c5 | 139 | host->quirks |= SDHCI_QUIRK_MISSING_CAPS; |
0ca33b4a RK |
140 | |
141 | host->caps = sdhci_readl(host, SDHCI_CAPABILITIES); | |
142 | host->caps1 = sdhci_readl(host, SDHCI_CAPABILITIES_1); | |
143 | ||
1140011e MW |
144 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, |
145 | "conf-sdio3"); | |
146 | if (res) { | |
147 | pxa->sdio3_conf_reg = devm_ioremap_resource(&pdev->dev, res); | |
148 | if (IS_ERR(pxa->sdio3_conf_reg)) | |
149 | return PTR_ERR(pxa->sdio3_conf_reg); | |
150 | } else { | |
151 | /* | |
152 | * According to erratum 'FE-2946959' both SDR50 and DDR50 | |
153 | * modes require specific clock adjustments in SDIO3 | |
154 | * Configuration register, if the adjustment is not done, | |
155 | * remove them from the capabilities. | |
156 | */ | |
1140011e MW |
157 | host->caps1 &= ~(SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_DDR50); |
158 | ||
159 | dev_warn(&pdev->dev, "conf-sdio3 register not found: disabling SDR50 and DDR50 modes.\nConsider updating your dtb\n"); | |
160 | } | |
a39128bc MW |
161 | |
162 | /* | |
163 | * According to erratum 'ERR-7878951' Armada 38x SDHCI | |
164 | * controller has different capabilities than the ones shown | |
165 | * in its registers | |
166 | */ | |
a39128bc MW |
167 | if (of_property_read_bool(np, "no-1-8-v")) { |
168 | host->caps &= ~SDHCI_CAN_VDD_180; | |
169 | host->mmc->caps &= ~MMC_CAP_1_8V_DDR; | |
170 | } else { | |
171 | host->caps &= ~SDHCI_CAN_VDD_330; | |
172 | } | |
173 | host->caps1 &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_USE_SDR50_TUNING); | |
174 | ||
d4b803c5 GC |
175 | return 0; |
176 | } | |
177 | ||
03231f9b | 178 | static void pxav3_reset(struct sdhci_host *host, u8 mask) |
a702c8ab ZG |
179 | { |
180 | struct platform_device *pdev = to_platform_device(mmc_dev(host->mmc)); | |
181 | struct sdhci_pxa_platdata *pdata = pdev->dev.platform_data; | |
182 | ||
03231f9b RK |
183 | sdhci_reset(host, mask); |
184 | ||
a702c8ab ZG |
185 | if (mask == SDHCI_RESET_ALL) { |
186 | /* | |
187 | * tune timing of read data/command when crc error happen | |
188 | * no performance impact | |
189 | */ | |
190 | if (pdata && 0 != pdata->clk_delay_cycles) { | |
191 | u16 tmp; | |
192 | ||
193 | tmp = readw(host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP); | |
194 | tmp |= (pdata->clk_delay_cycles & SDCLK_DELAY_MASK) | |
195 | << SDCLK_DELAY_SHIFT; | |
196 | tmp |= SDCLK_SEL; | |
197 | writew(tmp, host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP); | |
198 | } | |
199 | } | |
200 | } | |
201 | ||
202 | #define MAX_WAIT_COUNT 5 | |
203 | static void pxav3_gen_init_74_clocks(struct sdhci_host *host, u8 power_mode) | |
204 | { | |
205 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
206 | struct sdhci_pxa *pxa = pltfm_host->priv; | |
207 | u16 tmp; | |
208 | int count; | |
209 | ||
210 | if (pxa->power_mode == MMC_POWER_UP | |
211 | && power_mode == MMC_POWER_ON) { | |
212 | ||
213 | dev_dbg(mmc_dev(host->mmc), | |
214 | "%s: slot->power_mode = %d," | |
215 | "ios->power_mode = %d\n", | |
216 | __func__, | |
217 | pxa->power_mode, | |
218 | power_mode); | |
219 | ||
220 | /* set we want notice of when 74 clocks are sent */ | |
221 | tmp = readw(host->ioaddr + SD_CE_ATA_2); | |
222 | tmp |= SDCE_MISC_INT_EN; | |
223 | writew(tmp, host->ioaddr + SD_CE_ATA_2); | |
224 | ||
225 | /* start sending the 74 clocks */ | |
226 | tmp = readw(host->ioaddr + SD_CFG_FIFO_PARAM); | |
227 | tmp |= SDCFG_GEN_PAD_CLK_ON; | |
228 | writew(tmp, host->ioaddr + SD_CFG_FIFO_PARAM); | |
229 | ||
230 | /* slowest speed is about 100KHz or 10usec per clock */ | |
231 | udelay(740); | |
232 | count = 0; | |
233 | ||
234 | while (count++ < MAX_WAIT_COUNT) { | |
235 | if ((readw(host->ioaddr + SD_CE_ATA_2) | |
236 | & SDCE_MISC_INT) == 0) | |
237 | break; | |
238 | udelay(10); | |
239 | } | |
240 | ||
241 | if (count == MAX_WAIT_COUNT) | |
242 | dev_warn(mmc_dev(host->mmc), "74 clock interrupt not cleared\n"); | |
243 | ||
244 | /* clear the interrupt bit if posted */ | |
245 | tmp = readw(host->ioaddr + SD_CE_ATA_2); | |
246 | tmp |= SDCE_MISC_INT; | |
247 | writew(tmp, host->ioaddr + SD_CE_ATA_2); | |
248 | } | |
249 | pxa->power_mode = power_mode; | |
250 | } | |
251 | ||
13e64501 | 252 | static void pxav3_set_uhs_signaling(struct sdhci_host *host, unsigned int uhs) |
a702c8ab | 253 | { |
1140011e MW |
254 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
255 | struct sdhci_pxa *pxa = pltfm_host->priv; | |
a702c8ab ZG |
256 | u16 ctrl_2; |
257 | ||
258 | /* | |
259 | * Set V18_EN -- UHS modes do not work without this. | |
260 | * does not change signaling voltage | |
261 | */ | |
262 | ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); | |
263 | ||
264 | /* Select Bus Speed Mode for host */ | |
265 | ctrl_2 &= ~SDHCI_CTRL_UHS_MASK; | |
266 | switch (uhs) { | |
267 | case MMC_TIMING_UHS_SDR12: | |
268 | ctrl_2 |= SDHCI_CTRL_UHS_SDR12; | |
269 | break; | |
270 | case MMC_TIMING_UHS_SDR25: | |
271 | ctrl_2 |= SDHCI_CTRL_UHS_SDR25; | |
272 | break; | |
273 | case MMC_TIMING_UHS_SDR50: | |
274 | ctrl_2 |= SDHCI_CTRL_UHS_SDR50 | SDHCI_CTRL_VDD_180; | |
275 | break; | |
276 | case MMC_TIMING_UHS_SDR104: | |
277 | ctrl_2 |= SDHCI_CTRL_UHS_SDR104 | SDHCI_CTRL_VDD_180; | |
278 | break; | |
668e84b2 | 279 | case MMC_TIMING_MMC_DDR52: |
a702c8ab ZG |
280 | case MMC_TIMING_UHS_DDR50: |
281 | ctrl_2 |= SDHCI_CTRL_UHS_DDR50 | SDHCI_CTRL_VDD_180; | |
282 | break; | |
283 | } | |
284 | ||
1140011e MW |
285 | /* |
286 | * Update SDIO3 Configuration register according to erratum | |
287 | * FE-2946959 | |
288 | */ | |
289 | if (pxa->sdio3_conf_reg) { | |
290 | u8 reg_val = readb(pxa->sdio3_conf_reg); | |
291 | ||
292 | if (uhs == MMC_TIMING_UHS_SDR50 || | |
293 | uhs == MMC_TIMING_UHS_DDR50) { | |
294 | reg_val &= ~SDIO3_CONF_CLK_INV; | |
295 | reg_val |= SDIO3_CONF_SD_FB_CLK; | |
fa796414 NH |
296 | } else if (uhs == MMC_TIMING_MMC_HS) { |
297 | reg_val &= ~SDIO3_CONF_CLK_INV; | |
298 | reg_val &= ~SDIO3_CONF_SD_FB_CLK; | |
1140011e MW |
299 | } else { |
300 | reg_val |= SDIO3_CONF_CLK_INV; | |
301 | reg_val &= ~SDIO3_CONF_SD_FB_CLK; | |
302 | } | |
303 | writeb(reg_val, pxa->sdio3_conf_reg); | |
304 | } | |
305 | ||
a702c8ab ZG |
306 | sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); |
307 | dev_dbg(mmc_dev(host->mmc), | |
308 | "%s uhs = %d, ctrl_2 = %04X\n", | |
309 | __func__, uhs, ctrl_2); | |
a702c8ab ZG |
310 | } |
311 | ||
c915568d | 312 | static const struct sdhci_ops pxav3_sdhci_ops = { |
1771059c | 313 | .set_clock = sdhci_set_clock, |
a702c8ab | 314 | .platform_send_init_74_clocks = pxav3_gen_init_74_clocks, |
d005d943 | 315 | .get_max_clock = sdhci_pltfm_clk_get_max_clock, |
2317f56c | 316 | .set_bus_width = sdhci_set_bus_width, |
03231f9b | 317 | .reset = pxav3_reset, |
b3153765 | 318 | .set_uhs_signaling = pxav3_set_uhs_signaling, |
a702c8ab ZG |
319 | }; |
320 | ||
73b7afb9 | 321 | static struct sdhci_pltfm_data sdhci_pxav3_pdata = { |
e065162a | 322 | .quirks = SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
73b7afb9 KL |
323 | | SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC |
324 | | SDHCI_QUIRK_32BIT_ADMA_SIZE | |
325 | | SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, | |
326 | .ops = &pxav3_sdhci_ops, | |
327 | }; | |
328 | ||
b650352d CB |
329 | #ifdef CONFIG_OF |
330 | static const struct of_device_id sdhci_pxav3_of_match[] = { | |
331 | { | |
332 | .compatible = "mrvl,pxav3-mmc", | |
333 | }, | |
5491ce3f MW |
334 | { |
335 | .compatible = "marvell,armada-380-sdhci", | |
336 | }, | |
b650352d CB |
337 | {}, |
338 | }; | |
339 | MODULE_DEVICE_TABLE(of, sdhci_pxav3_of_match); | |
340 | ||
341 | static struct sdhci_pxa_platdata *pxav3_get_mmc_pdata(struct device *dev) | |
342 | { | |
343 | struct sdhci_pxa_platdata *pdata; | |
344 | struct device_node *np = dev->of_node; | |
b650352d CB |
345 | u32 clk_delay_cycles; |
346 | ||
347 | pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL); | |
348 | if (!pdata) | |
349 | return NULL; | |
350 | ||
14460dba JZ |
351 | if (!of_property_read_u32(np, "mrvl,clk-delay-cycles", |
352 | &clk_delay_cycles)) | |
b650352d CB |
353 | pdata->clk_delay_cycles = clk_delay_cycles; |
354 | ||
355 | return pdata; | |
356 | } | |
357 | #else | |
358 | static inline struct sdhci_pxa_platdata *pxav3_get_mmc_pdata(struct device *dev) | |
359 | { | |
360 | return NULL; | |
361 | } | |
362 | #endif | |
363 | ||
c3be1efd | 364 | static int sdhci_pxav3_probe(struct platform_device *pdev) |
a702c8ab ZG |
365 | { |
366 | struct sdhci_pltfm_host *pltfm_host; | |
367 | struct sdhci_pxa_platdata *pdata = pdev->dev.platform_data; | |
368 | struct device *dev = &pdev->dev; | |
5491ce3f | 369 | struct device_node *np = pdev->dev.of_node; |
a702c8ab ZG |
370 | struct sdhci_host *host = NULL; |
371 | struct sdhci_pxa *pxa = NULL; | |
b650352d | 372 | const struct of_device_id *match; |
a702c8ab | 373 | int ret; |
a702c8ab | 374 | |
3df5b281 | 375 | pxa = devm_kzalloc(&pdev->dev, sizeof(struct sdhci_pxa), GFP_KERNEL); |
a702c8ab ZG |
376 | if (!pxa) |
377 | return -ENOMEM; | |
378 | ||
0e748234 | 379 | host = sdhci_pltfm_init(pdev, &sdhci_pxav3_pdata, 0); |
3df5b281 | 380 | if (IS_ERR(host)) |
a702c8ab | 381 | return PTR_ERR(host); |
5491ce3f | 382 | |
a702c8ab ZG |
383 | pltfm_host = sdhci_priv(host); |
384 | pltfm_host->priv = pxa; | |
385 | ||
01ae1070 SH |
386 | pxa->clk_io = devm_clk_get(dev, "io"); |
387 | if (IS_ERR(pxa->clk_io)) | |
388 | pxa->clk_io = devm_clk_get(dev, NULL); | |
8c96a7a3 | 389 | if (IS_ERR(pxa->clk_io)) { |
a702c8ab | 390 | dev_err(dev, "failed to get io clock\n"); |
8c96a7a3 | 391 | ret = PTR_ERR(pxa->clk_io); |
a702c8ab ZG |
392 | goto err_clk_get; |
393 | } | |
8c96a7a3 SH |
394 | pltfm_host->clk = pxa->clk_io; |
395 | clk_prepare_enable(pxa->clk_io); | |
a702c8ab | 396 | |
8afdc9cc SH |
397 | pxa->clk_core = devm_clk_get(dev, "core"); |
398 | if (!IS_ERR(pxa->clk_core)) | |
399 | clk_prepare_enable(pxa->clk_core); | |
400 | ||
a39128bc MW |
401 | /* enable 1/8V DDR capable */ |
402 | host->mmc->caps |= MMC_CAP_1_8V_DDR; | |
403 | ||
aa8165f9 | 404 | if (of_device_is_compatible(np, "marvell,armada-380-sdhci")) { |
a39128bc | 405 | ret = armada_38x_quirks(pdev, host); |
d4b803c5 | 406 | if (ret < 0) |
2162d9f4 | 407 | goto err_mbus_win; |
aa8165f9 TP |
408 | ret = mv_conf_mbus_windows(pdev, mv_mbus_dram_info()); |
409 | if (ret < 0) | |
410 | goto err_mbus_win; | |
411 | } | |
412 | ||
b650352d | 413 | match = of_match_device(of_match_ptr(sdhci_pxav3_of_match), &pdev->dev); |
943647f6 | 414 | if (match) { |
d2cf6071 SB |
415 | ret = mmc_of_parse(host->mmc); |
416 | if (ret) | |
417 | goto err_of_parse; | |
943647f6 | 418 | sdhci_get_of_property(pdev); |
b650352d | 419 | pdata = pxav3_get_mmc_pdata(dev); |
9cd76049 | 420 | pdev->dev.platform_data = pdata; |
943647f6 | 421 | } else if (pdata) { |
c844a46f KL |
422 | /* on-chip device */ |
423 | if (pdata->flags & PXA_FLAG_CARD_PERMANENT) | |
a702c8ab | 424 | host->mmc->caps |= MMC_CAP_NONREMOVABLE; |
a702c8ab ZG |
425 | |
426 | /* If slot design supports 8 bit data, indicate this to MMC. */ | |
427 | if (pdata->flags & PXA_FLAG_SD_8_BIT_CAPABLE_SLOT) | |
428 | host->mmc->caps |= MMC_CAP_8_BIT_DATA; | |
429 | ||
430 | if (pdata->quirks) | |
431 | host->quirks |= pdata->quirks; | |
7c52d7bb KL |
432 | if (pdata->quirks2) |
433 | host->quirks2 |= pdata->quirks2; | |
a702c8ab ZG |
434 | if (pdata->host_caps) |
435 | host->mmc->caps |= pdata->host_caps; | |
8f63795c CB |
436 | if (pdata->host_caps2) |
437 | host->mmc->caps2 |= pdata->host_caps2; | |
a702c8ab ZG |
438 | if (pdata->pm_caps) |
439 | host->mmc->pm_caps |= pdata->pm_caps; | |
8f63795c CB |
440 | |
441 | if (gpio_is_valid(pdata->ext_cd_gpio)) { | |
214fc309 LP |
442 | ret = mmc_gpio_request_cd(host->mmc, pdata->ext_cd_gpio, |
443 | 0); | |
8f63795c CB |
444 | if (ret) { |
445 | dev_err(mmc_dev(host->mmc), | |
446 | "failed to allocate card detect gpio\n"); | |
447 | goto err_cd_req; | |
448 | } | |
449 | } | |
a702c8ab ZG |
450 | } |
451 | ||
62cf983a JZ |
452 | pm_runtime_get_noresume(&pdev->dev); |
453 | pm_runtime_set_active(&pdev->dev); | |
bb691ae4 KL |
454 | pm_runtime_set_autosuspend_delay(&pdev->dev, PXAV3_RPM_DELAY_MS); |
455 | pm_runtime_use_autosuspend(&pdev->dev); | |
62cf983a | 456 | pm_runtime_enable(&pdev->dev); |
bb691ae4 | 457 | pm_suspend_ignore_children(&pdev->dev, 1); |
bb691ae4 | 458 | |
a702c8ab ZG |
459 | ret = sdhci_add_host(host); |
460 | if (ret) { | |
461 | dev_err(&pdev->dev, "failed to add host\n"); | |
462 | goto err_add_host; | |
463 | } | |
464 | ||
465 | platform_set_drvdata(pdev, host); | |
466 | ||
83dc9fec | 467 | if (host->mmc->pm_caps & MMC_PM_WAKE_SDIO_IRQ) |
740b7a44 | 468 | device_init_wakeup(&pdev->dev, 1); |
740b7a44 | 469 | |
bb691ae4 KL |
470 | pm_runtime_put_autosuspend(&pdev->dev); |
471 | ||
a702c8ab ZG |
472 | return 0; |
473 | ||
474 | err_add_host: | |
0dcaa249 | 475 | pm_runtime_disable(&pdev->dev); |
62cf983a | 476 | pm_runtime_put_noidle(&pdev->dev); |
87d2163d XW |
477 | err_of_parse: |
478 | err_cd_req: | |
aa8165f9 | 479 | err_mbus_win: |
8c96a7a3 | 480 | clk_disable_unprepare(pxa->clk_io); |
c25d9e1b | 481 | clk_disable_unprepare(pxa->clk_core); |
a702c8ab ZG |
482 | err_clk_get: |
483 | sdhci_pltfm_free(pdev); | |
a702c8ab ZG |
484 | return ret; |
485 | } | |
486 | ||
6e0ee714 | 487 | static int sdhci_pxav3_remove(struct platform_device *pdev) |
a702c8ab ZG |
488 | { |
489 | struct sdhci_host *host = platform_get_drvdata(pdev); | |
490 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
8c96a7a3 | 491 | struct sdhci_pxa *pxa = pltfm_host->priv; |
a702c8ab | 492 | |
bb691ae4 | 493 | pm_runtime_get_sync(&pdev->dev); |
bb691ae4 | 494 | pm_runtime_disable(&pdev->dev); |
20f1f2d7 JZ |
495 | pm_runtime_put_noidle(&pdev->dev); |
496 | ||
497 | sdhci_remove_host(host, 1); | |
a702c8ab | 498 | |
8c96a7a3 | 499 | clk_disable_unprepare(pxa->clk_io); |
c25d9e1b | 500 | clk_disable_unprepare(pxa->clk_core); |
8f63795c | 501 | |
a702c8ab | 502 | sdhci_pltfm_free(pdev); |
a702c8ab | 503 | |
a702c8ab ZG |
504 | return 0; |
505 | } | |
506 | ||
bb691ae4 KL |
507 | #ifdef CONFIG_PM_SLEEP |
508 | static int sdhci_pxav3_suspend(struct device *dev) | |
509 | { | |
510 | int ret; | |
511 | struct sdhci_host *host = dev_get_drvdata(dev); | |
512 | ||
513 | pm_runtime_get_sync(dev); | |
514 | ret = sdhci_suspend_host(host); | |
515 | pm_runtime_mark_last_busy(dev); | |
516 | pm_runtime_put_autosuspend(dev); | |
517 | ||
518 | return ret; | |
519 | } | |
520 | ||
521 | static int sdhci_pxav3_resume(struct device *dev) | |
522 | { | |
523 | int ret; | |
524 | struct sdhci_host *host = dev_get_drvdata(dev); | |
525 | ||
526 | pm_runtime_get_sync(dev); | |
527 | ret = sdhci_resume_host(host); | |
528 | pm_runtime_mark_last_busy(dev); | |
529 | pm_runtime_put_autosuspend(dev); | |
530 | ||
531 | return ret; | |
532 | } | |
533 | #endif | |
534 | ||
162d6f98 | 535 | #ifdef CONFIG_PM |
bb691ae4 KL |
536 | static int sdhci_pxav3_runtime_suspend(struct device *dev) |
537 | { | |
538 | struct sdhci_host *host = dev_get_drvdata(dev); | |
539 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
8c96a7a3 | 540 | struct sdhci_pxa *pxa = pltfm_host->priv; |
3bb10f60 | 541 | int ret; |
bb691ae4 | 542 | |
3bb10f60 JZ |
543 | ret = sdhci_runtime_suspend_host(host); |
544 | if (ret) | |
545 | return ret; | |
bb691ae4 | 546 | |
8c96a7a3 | 547 | clk_disable_unprepare(pxa->clk_io); |
8afdc9cc SH |
548 | if (!IS_ERR(pxa->clk_core)) |
549 | clk_disable_unprepare(pxa->clk_core); | |
bb691ae4 KL |
550 | |
551 | return 0; | |
552 | } | |
553 | ||
554 | static int sdhci_pxav3_runtime_resume(struct device *dev) | |
555 | { | |
556 | struct sdhci_host *host = dev_get_drvdata(dev); | |
557 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
8c96a7a3 | 558 | struct sdhci_pxa *pxa = pltfm_host->priv; |
bb691ae4 | 559 | |
8c96a7a3 | 560 | clk_prepare_enable(pxa->clk_io); |
8afdc9cc SH |
561 | if (!IS_ERR(pxa->clk_core)) |
562 | clk_prepare_enable(pxa->clk_core); | |
bb691ae4 | 563 | |
3bb10f60 | 564 | return sdhci_runtime_resume_host(host); |
bb691ae4 KL |
565 | } |
566 | #endif | |
567 | ||
568 | #ifdef CONFIG_PM | |
569 | static const struct dev_pm_ops sdhci_pxav3_pmops = { | |
570 | SET_SYSTEM_SLEEP_PM_OPS(sdhci_pxav3_suspend, sdhci_pxav3_resume) | |
571 | SET_RUNTIME_PM_OPS(sdhci_pxav3_runtime_suspend, | |
572 | sdhci_pxav3_runtime_resume, NULL) | |
573 | }; | |
574 | ||
575 | #define SDHCI_PXAV3_PMOPS (&sdhci_pxav3_pmops) | |
576 | ||
577 | #else | |
578 | #define SDHCI_PXAV3_PMOPS NULL | |
579 | #endif | |
580 | ||
a702c8ab ZG |
581 | static struct platform_driver sdhci_pxav3_driver = { |
582 | .driver = { | |
583 | .name = "sdhci-pxav3", | |
59d22309 | 584 | .of_match_table = of_match_ptr(sdhci_pxav3_of_match), |
bb691ae4 | 585 | .pm = SDHCI_PXAV3_PMOPS, |
a702c8ab ZG |
586 | }, |
587 | .probe = sdhci_pxav3_probe, | |
0433c143 | 588 | .remove = sdhci_pxav3_remove, |
a702c8ab | 589 | }; |
a702c8ab | 590 | |
d1f81a64 | 591 | module_platform_driver(sdhci_pxav3_driver); |
a702c8ab ZG |
592 | |
593 | MODULE_DESCRIPTION("SDHCI driver for pxav3"); | |
594 | MODULE_AUTHOR("Marvell International Ltd."); | |
595 | MODULE_LICENSE("GPL v2"); | |
596 |