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a702c8ab ZG |
1 | /* |
2 | * Copyright (C) 2010 Marvell International Ltd. | |
3 | * Zhangfei Gao <zhangfei.gao@marvell.com> | |
4 | * Kevin Wang <dwang4@marvell.com> | |
5 | * Mingwei Wang <mwwang@marvell.com> | |
6 | * Philip Rakity <prakity@marvell.com> | |
7 | * Mark Brown <markb@marvell.com> | |
8 | * | |
9 | * This software is licensed under the terms of the GNU General Public | |
10 | * License version 2, as published by the Free Software Foundation, and | |
11 | * may be copied, distributed, and modified under those terms. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | */ | |
19 | #include <linux/err.h> | |
20 | #include <linux/init.h> | |
21 | #include <linux/platform_device.h> | |
22 | #include <linux/clk.h> | |
23 | #include <linux/io.h> | |
24 | #include <linux/gpio.h> | |
25 | #include <linux/mmc/card.h> | |
26 | #include <linux/mmc/host.h> | |
8f63795c | 27 | #include <linux/mmc/slot-gpio.h> |
bfed345e | 28 | #include <linux/platform_data/pxa_sdhci.h> |
a702c8ab ZG |
29 | #include <linux/slab.h> |
30 | #include <linux/delay.h> | |
88b47679 | 31 | #include <linux/module.h> |
b650352d CB |
32 | #include <linux/of.h> |
33 | #include <linux/of_device.h> | |
8f63795c | 34 | #include <linux/of_gpio.h> |
bb691ae4 KL |
35 | #include <linux/pm.h> |
36 | #include <linux/pm_runtime.h> | |
b650352d | 37 | |
a702c8ab ZG |
38 | #include "sdhci.h" |
39 | #include "sdhci-pltfm.h" | |
40 | ||
bb691ae4 KL |
41 | #define PXAV3_RPM_DELAY_MS 50 |
42 | ||
a702c8ab ZG |
43 | #define SD_CLOCK_BURST_SIZE_SETUP 0x10A |
44 | #define SDCLK_SEL 0x100 | |
45 | #define SDCLK_DELAY_SHIFT 9 | |
46 | #define SDCLK_DELAY_MASK 0x1f | |
47 | ||
48 | #define SD_CFG_FIFO_PARAM 0x100 | |
49 | #define SDCFG_GEN_PAD_CLK_ON (1<<6) | |
50 | #define SDCFG_GEN_PAD_CLK_CNT_MASK 0xFF | |
51 | #define SDCFG_GEN_PAD_CLK_CNT_SHIFT 24 | |
52 | ||
53 | #define SD_SPI_MODE 0x108 | |
54 | #define SD_CE_ATA_1 0x10C | |
55 | ||
56 | #define SD_CE_ATA_2 0x10E | |
57 | #define SDCE_MISC_INT (1<<2) | |
58 | #define SDCE_MISC_INT_EN (1<<1) | |
59 | ||
60 | static void pxav3_set_private_registers(struct sdhci_host *host, u8 mask) | |
61 | { | |
62 | struct platform_device *pdev = to_platform_device(mmc_dev(host->mmc)); | |
63 | struct sdhci_pxa_platdata *pdata = pdev->dev.platform_data; | |
64 | ||
65 | if (mask == SDHCI_RESET_ALL) { | |
66 | /* | |
67 | * tune timing of read data/command when crc error happen | |
68 | * no performance impact | |
69 | */ | |
70 | if (pdata && 0 != pdata->clk_delay_cycles) { | |
71 | u16 tmp; | |
72 | ||
73 | tmp = readw(host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP); | |
74 | tmp |= (pdata->clk_delay_cycles & SDCLK_DELAY_MASK) | |
75 | << SDCLK_DELAY_SHIFT; | |
76 | tmp |= SDCLK_SEL; | |
77 | writew(tmp, host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP); | |
78 | } | |
79 | } | |
80 | } | |
81 | ||
82 | #define MAX_WAIT_COUNT 5 | |
83 | static void pxav3_gen_init_74_clocks(struct sdhci_host *host, u8 power_mode) | |
84 | { | |
85 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
86 | struct sdhci_pxa *pxa = pltfm_host->priv; | |
87 | u16 tmp; | |
88 | int count; | |
89 | ||
90 | if (pxa->power_mode == MMC_POWER_UP | |
91 | && power_mode == MMC_POWER_ON) { | |
92 | ||
93 | dev_dbg(mmc_dev(host->mmc), | |
94 | "%s: slot->power_mode = %d," | |
95 | "ios->power_mode = %d\n", | |
96 | __func__, | |
97 | pxa->power_mode, | |
98 | power_mode); | |
99 | ||
100 | /* set we want notice of when 74 clocks are sent */ | |
101 | tmp = readw(host->ioaddr + SD_CE_ATA_2); | |
102 | tmp |= SDCE_MISC_INT_EN; | |
103 | writew(tmp, host->ioaddr + SD_CE_ATA_2); | |
104 | ||
105 | /* start sending the 74 clocks */ | |
106 | tmp = readw(host->ioaddr + SD_CFG_FIFO_PARAM); | |
107 | tmp |= SDCFG_GEN_PAD_CLK_ON; | |
108 | writew(tmp, host->ioaddr + SD_CFG_FIFO_PARAM); | |
109 | ||
110 | /* slowest speed is about 100KHz or 10usec per clock */ | |
111 | udelay(740); | |
112 | count = 0; | |
113 | ||
114 | while (count++ < MAX_WAIT_COUNT) { | |
115 | if ((readw(host->ioaddr + SD_CE_ATA_2) | |
116 | & SDCE_MISC_INT) == 0) | |
117 | break; | |
118 | udelay(10); | |
119 | } | |
120 | ||
121 | if (count == MAX_WAIT_COUNT) | |
122 | dev_warn(mmc_dev(host->mmc), "74 clock interrupt not cleared\n"); | |
123 | ||
124 | /* clear the interrupt bit if posted */ | |
125 | tmp = readw(host->ioaddr + SD_CE_ATA_2); | |
126 | tmp |= SDCE_MISC_INT; | |
127 | writew(tmp, host->ioaddr + SD_CE_ATA_2); | |
128 | } | |
129 | pxa->power_mode = power_mode; | |
130 | } | |
131 | ||
132 | static int pxav3_set_uhs_signaling(struct sdhci_host *host, unsigned int uhs) | |
133 | { | |
134 | u16 ctrl_2; | |
135 | ||
136 | /* | |
137 | * Set V18_EN -- UHS modes do not work without this. | |
138 | * does not change signaling voltage | |
139 | */ | |
140 | ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); | |
141 | ||
142 | /* Select Bus Speed Mode for host */ | |
143 | ctrl_2 &= ~SDHCI_CTRL_UHS_MASK; | |
144 | switch (uhs) { | |
145 | case MMC_TIMING_UHS_SDR12: | |
146 | ctrl_2 |= SDHCI_CTRL_UHS_SDR12; | |
147 | break; | |
148 | case MMC_TIMING_UHS_SDR25: | |
149 | ctrl_2 |= SDHCI_CTRL_UHS_SDR25; | |
150 | break; | |
151 | case MMC_TIMING_UHS_SDR50: | |
152 | ctrl_2 |= SDHCI_CTRL_UHS_SDR50 | SDHCI_CTRL_VDD_180; | |
153 | break; | |
154 | case MMC_TIMING_UHS_SDR104: | |
155 | ctrl_2 |= SDHCI_CTRL_UHS_SDR104 | SDHCI_CTRL_VDD_180; | |
156 | break; | |
157 | case MMC_TIMING_UHS_DDR50: | |
158 | ctrl_2 |= SDHCI_CTRL_UHS_DDR50 | SDHCI_CTRL_VDD_180; | |
159 | break; | |
160 | } | |
161 | ||
162 | sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); | |
163 | dev_dbg(mmc_dev(host->mmc), | |
164 | "%s uhs = %d, ctrl_2 = %04X\n", | |
165 | __func__, uhs, ctrl_2); | |
166 | ||
167 | return 0; | |
168 | } | |
169 | ||
c915568d | 170 | static const struct sdhci_ops pxav3_sdhci_ops = { |
a702c8ab ZG |
171 | .platform_reset_exit = pxav3_set_private_registers, |
172 | .set_uhs_signaling = pxav3_set_uhs_signaling, | |
173 | .platform_send_init_74_clocks = pxav3_gen_init_74_clocks, | |
d005d943 | 174 | .get_max_clock = sdhci_pltfm_clk_get_max_clock, |
a702c8ab ZG |
175 | }; |
176 | ||
73b7afb9 KL |
177 | static struct sdhci_pltfm_data sdhci_pxav3_pdata = { |
178 | .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | |
179 | | SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC | |
180 | | SDHCI_QUIRK_32BIT_ADMA_SIZE | |
181 | | SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, | |
182 | .ops = &pxav3_sdhci_ops, | |
183 | }; | |
184 | ||
b650352d CB |
185 | #ifdef CONFIG_OF |
186 | static const struct of_device_id sdhci_pxav3_of_match[] = { | |
187 | { | |
188 | .compatible = "mrvl,pxav3-mmc", | |
189 | }, | |
190 | {}, | |
191 | }; | |
192 | MODULE_DEVICE_TABLE(of, sdhci_pxav3_of_match); | |
193 | ||
194 | static struct sdhci_pxa_platdata *pxav3_get_mmc_pdata(struct device *dev) | |
195 | { | |
196 | struct sdhci_pxa_platdata *pdata; | |
197 | struct device_node *np = dev->of_node; | |
198 | u32 bus_width; | |
199 | u32 clk_delay_cycles; | |
8f63795c | 200 | enum of_gpio_flags gpio_flags; |
b650352d CB |
201 | |
202 | pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL); | |
203 | if (!pdata) | |
204 | return NULL; | |
205 | ||
206 | if (of_find_property(np, "non-removable", NULL)) | |
207 | pdata->flags |= PXA_FLAG_CARD_PERMANENT; | |
208 | ||
209 | of_property_read_u32(np, "bus-width", &bus_width); | |
210 | if (bus_width == 8) | |
211 | pdata->flags |= PXA_FLAG_SD_8_BIT_CAPABLE_SLOT; | |
212 | ||
213 | of_property_read_u32(np, "mrvl,clk-delay-cycles", &clk_delay_cycles); | |
214 | if (clk_delay_cycles > 0) | |
215 | pdata->clk_delay_cycles = clk_delay_cycles; | |
216 | ||
8f63795c CB |
217 | pdata->ext_cd_gpio = of_get_named_gpio_flags(np, "cd-gpios", 0, &gpio_flags); |
218 | if (gpio_flags != OF_GPIO_ACTIVE_LOW) | |
219 | pdata->host_caps2 |= MMC_CAP2_CD_ACTIVE_HIGH; | |
220 | ||
b650352d CB |
221 | return pdata; |
222 | } | |
223 | #else | |
224 | static inline struct sdhci_pxa_platdata *pxav3_get_mmc_pdata(struct device *dev) | |
225 | { | |
226 | return NULL; | |
227 | } | |
228 | #endif | |
229 | ||
c3be1efd | 230 | static int sdhci_pxav3_probe(struct platform_device *pdev) |
a702c8ab ZG |
231 | { |
232 | struct sdhci_pltfm_host *pltfm_host; | |
233 | struct sdhci_pxa_platdata *pdata = pdev->dev.platform_data; | |
234 | struct device *dev = &pdev->dev; | |
235 | struct sdhci_host *host = NULL; | |
236 | struct sdhci_pxa *pxa = NULL; | |
b650352d CB |
237 | const struct of_device_id *match; |
238 | ||
a702c8ab ZG |
239 | int ret; |
240 | struct clk *clk; | |
241 | ||
242 | pxa = kzalloc(sizeof(struct sdhci_pxa), GFP_KERNEL); | |
243 | if (!pxa) | |
244 | return -ENOMEM; | |
245 | ||
73b7afb9 | 246 | host = sdhci_pltfm_init(pdev, &sdhci_pxav3_pdata); |
a702c8ab ZG |
247 | if (IS_ERR(host)) { |
248 | kfree(pxa); | |
249 | return PTR_ERR(host); | |
250 | } | |
251 | pltfm_host = sdhci_priv(host); | |
252 | pltfm_host->priv = pxa; | |
253 | ||
164378ef | 254 | clk = clk_get(dev, NULL); |
a702c8ab ZG |
255 | if (IS_ERR(clk)) { |
256 | dev_err(dev, "failed to get io clock\n"); | |
257 | ret = PTR_ERR(clk); | |
258 | goto err_clk_get; | |
259 | } | |
260 | pltfm_host->clk = clk; | |
164378ef | 261 | clk_prepare_enable(clk); |
a702c8ab | 262 | |
a702c8ab ZG |
263 | /* enable 1/8V DDR capable */ |
264 | host->mmc->caps |= MMC_CAP_1_8V_DDR; | |
265 | ||
b650352d CB |
266 | match = of_match_device(of_match_ptr(sdhci_pxav3_of_match), &pdev->dev); |
267 | if (match) | |
268 | pdata = pxav3_get_mmc_pdata(dev); | |
269 | ||
a702c8ab ZG |
270 | if (pdata) { |
271 | if (pdata->flags & PXA_FLAG_CARD_PERMANENT) { | |
272 | /* on-chip device */ | |
273 | host->quirks |= SDHCI_QUIRK_BROKEN_CARD_DETECTION; | |
274 | host->mmc->caps |= MMC_CAP_NONREMOVABLE; | |
275 | } | |
276 | ||
277 | /* If slot design supports 8 bit data, indicate this to MMC. */ | |
278 | if (pdata->flags & PXA_FLAG_SD_8_BIT_CAPABLE_SLOT) | |
279 | host->mmc->caps |= MMC_CAP_8_BIT_DATA; | |
280 | ||
281 | if (pdata->quirks) | |
282 | host->quirks |= pdata->quirks; | |
7c52d7bb KL |
283 | if (pdata->quirks2) |
284 | host->quirks2 |= pdata->quirks2; | |
a702c8ab ZG |
285 | if (pdata->host_caps) |
286 | host->mmc->caps |= pdata->host_caps; | |
8f63795c CB |
287 | if (pdata->host_caps2) |
288 | host->mmc->caps2 |= pdata->host_caps2; | |
a702c8ab ZG |
289 | if (pdata->pm_caps) |
290 | host->mmc->pm_caps |= pdata->pm_caps; | |
8f63795c CB |
291 | |
292 | if (gpio_is_valid(pdata->ext_cd_gpio)) { | |
293 | ret = mmc_gpio_request_cd(host->mmc, pdata->ext_cd_gpio); | |
294 | if (ret) { | |
295 | dev_err(mmc_dev(host->mmc), | |
296 | "failed to allocate card detect gpio\n"); | |
297 | goto err_cd_req; | |
298 | } | |
299 | } | |
a702c8ab ZG |
300 | } |
301 | ||
f4f24ade CB |
302 | sdhci_get_of_property(pdev); |
303 | ||
bb691ae4 KL |
304 | pm_runtime_set_active(&pdev->dev); |
305 | pm_runtime_enable(&pdev->dev); | |
306 | pm_runtime_set_autosuspend_delay(&pdev->dev, PXAV3_RPM_DELAY_MS); | |
307 | pm_runtime_use_autosuspend(&pdev->dev); | |
308 | pm_suspend_ignore_children(&pdev->dev, 1); | |
309 | pm_runtime_get_noresume(&pdev->dev); | |
310 | ||
a702c8ab ZG |
311 | ret = sdhci_add_host(host); |
312 | if (ret) { | |
313 | dev_err(&pdev->dev, "failed to add host\n"); | |
bb691ae4 KL |
314 | pm_runtime_forbid(&pdev->dev); |
315 | pm_runtime_disable(&pdev->dev); | |
a702c8ab ZG |
316 | goto err_add_host; |
317 | } | |
318 | ||
319 | platform_set_drvdata(pdev, host); | |
320 | ||
740b7a44 KL |
321 | if (pdata->pm_caps & MMC_PM_KEEP_POWER) { |
322 | device_init_wakeup(&pdev->dev, 1); | |
323 | host->mmc->pm_flags |= MMC_PM_WAKE_SDIO_IRQ; | |
324 | } else { | |
325 | device_init_wakeup(&pdev->dev, 0); | |
326 | } | |
327 | ||
bb691ae4 KL |
328 | pm_runtime_put_autosuspend(&pdev->dev); |
329 | ||
a702c8ab ZG |
330 | return 0; |
331 | ||
332 | err_add_host: | |
164378ef | 333 | clk_disable_unprepare(clk); |
a702c8ab | 334 | clk_put(clk); |
8f63795c | 335 | err_cd_req: |
a702c8ab ZG |
336 | err_clk_get: |
337 | sdhci_pltfm_free(pdev); | |
338 | kfree(pxa); | |
339 | return ret; | |
340 | } | |
341 | ||
6e0ee714 | 342 | static int sdhci_pxav3_remove(struct platform_device *pdev) |
a702c8ab ZG |
343 | { |
344 | struct sdhci_host *host = platform_get_drvdata(pdev); | |
345 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
346 | struct sdhci_pxa *pxa = pltfm_host->priv; | |
347 | ||
bb691ae4 | 348 | pm_runtime_get_sync(&pdev->dev); |
a702c8ab | 349 | sdhci_remove_host(host, 1); |
bb691ae4 | 350 | pm_runtime_disable(&pdev->dev); |
a702c8ab | 351 | |
164378ef | 352 | clk_disable_unprepare(pltfm_host->clk); |
a702c8ab | 353 | clk_put(pltfm_host->clk); |
8f63795c | 354 | |
a702c8ab ZG |
355 | sdhci_pltfm_free(pdev); |
356 | kfree(pxa); | |
357 | ||
358 | platform_set_drvdata(pdev, NULL); | |
359 | ||
360 | return 0; | |
361 | } | |
362 | ||
bb691ae4 KL |
363 | #ifdef CONFIG_PM_SLEEP |
364 | static int sdhci_pxav3_suspend(struct device *dev) | |
365 | { | |
366 | int ret; | |
367 | struct sdhci_host *host = dev_get_drvdata(dev); | |
368 | ||
369 | pm_runtime_get_sync(dev); | |
370 | ret = sdhci_suspend_host(host); | |
371 | pm_runtime_mark_last_busy(dev); | |
372 | pm_runtime_put_autosuspend(dev); | |
373 | ||
374 | return ret; | |
375 | } | |
376 | ||
377 | static int sdhci_pxav3_resume(struct device *dev) | |
378 | { | |
379 | int ret; | |
380 | struct sdhci_host *host = dev_get_drvdata(dev); | |
381 | ||
382 | pm_runtime_get_sync(dev); | |
383 | ret = sdhci_resume_host(host); | |
384 | pm_runtime_mark_last_busy(dev); | |
385 | pm_runtime_put_autosuspend(dev); | |
386 | ||
387 | return ret; | |
388 | } | |
389 | #endif | |
390 | ||
391 | #ifdef CONFIG_PM_RUNTIME | |
392 | static int sdhci_pxav3_runtime_suspend(struct device *dev) | |
393 | { | |
394 | struct sdhci_host *host = dev_get_drvdata(dev); | |
395 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
396 | unsigned long flags; | |
397 | ||
398 | if (pltfm_host->clk) { | |
399 | spin_lock_irqsave(&host->lock, flags); | |
400 | host->runtime_suspended = true; | |
401 | spin_unlock_irqrestore(&host->lock, flags); | |
402 | ||
403 | clk_disable_unprepare(pltfm_host->clk); | |
404 | } | |
405 | ||
406 | return 0; | |
407 | } | |
408 | ||
409 | static int sdhci_pxav3_runtime_resume(struct device *dev) | |
410 | { | |
411 | struct sdhci_host *host = dev_get_drvdata(dev); | |
412 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
413 | unsigned long flags; | |
414 | ||
415 | if (pltfm_host->clk) { | |
416 | clk_prepare_enable(pltfm_host->clk); | |
417 | ||
418 | spin_lock_irqsave(&host->lock, flags); | |
419 | host->runtime_suspended = false; | |
420 | spin_unlock_irqrestore(&host->lock, flags); | |
421 | } | |
422 | ||
423 | return 0; | |
424 | } | |
425 | #endif | |
426 | ||
427 | #ifdef CONFIG_PM | |
428 | static const struct dev_pm_ops sdhci_pxav3_pmops = { | |
429 | SET_SYSTEM_SLEEP_PM_OPS(sdhci_pxav3_suspend, sdhci_pxav3_resume) | |
430 | SET_RUNTIME_PM_OPS(sdhci_pxav3_runtime_suspend, | |
431 | sdhci_pxav3_runtime_resume, NULL) | |
432 | }; | |
433 | ||
434 | #define SDHCI_PXAV3_PMOPS (&sdhci_pxav3_pmops) | |
435 | ||
436 | #else | |
437 | #define SDHCI_PXAV3_PMOPS NULL | |
438 | #endif | |
439 | ||
a702c8ab ZG |
440 | static struct platform_driver sdhci_pxav3_driver = { |
441 | .driver = { | |
442 | .name = "sdhci-pxav3", | |
b650352d CB |
443 | #ifdef CONFIG_OF |
444 | .of_match_table = sdhci_pxav3_of_match, | |
445 | #endif | |
a702c8ab | 446 | .owner = THIS_MODULE, |
bb691ae4 | 447 | .pm = SDHCI_PXAV3_PMOPS, |
a702c8ab ZG |
448 | }, |
449 | .probe = sdhci_pxav3_probe, | |
0433c143 | 450 | .remove = sdhci_pxav3_remove, |
a702c8ab | 451 | }; |
a702c8ab | 452 | |
d1f81a64 | 453 | module_platform_driver(sdhci_pxav3_driver); |
a702c8ab ZG |
454 | |
455 | MODULE_DESCRIPTION("SDHCI driver for pxav3"); | |
456 | MODULE_AUTHOR("Marvell International Ltd."); | |
457 | MODULE_LICENSE("GPL v2"); | |
458 |