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0d1bb41a BD |
1 | /* linux/drivers/mmc/host/sdhci-s3c.c |
2 | * | |
3 | * Copyright 2008 Openmoko Inc. | |
4 | * Copyright 2008 Simtec Electronics | |
5 | * Ben Dooks <ben@simtec.co.uk> | |
6 | * http://armlinux.simtec.co.uk/ | |
7 | * | |
8 | * SDHCI (HSMMC) support for Samsung SoC | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License version 2 as | |
12 | * published by the Free Software Foundation. | |
13 | */ | |
14 | ||
017210d1 | 15 | #include <linux/spinlock.h> |
0d1bb41a BD |
16 | #include <linux/delay.h> |
17 | #include <linux/dma-mapping.h> | |
18 | #include <linux/platform_device.h> | |
cc014f3e | 19 | #include <linux/platform_data/mmc-sdhci-s3c.h> |
5a0e3ad6 | 20 | #include <linux/slab.h> |
0d1bb41a BD |
21 | #include <linux/clk.h> |
22 | #include <linux/io.h> | |
17866e14 | 23 | #include <linux/gpio.h> |
55156d24 | 24 | #include <linux/module.h> |
d5e9c02c MB |
25 | #include <linux/of.h> |
26 | #include <linux/of_gpio.h> | |
27 | #include <linux/pm.h> | |
9f4e8151 | 28 | #include <linux/pm_runtime.h> |
0d1bb41a BD |
29 | |
30 | #include <linux/mmc/host.h> | |
31 | ||
0d1bb41a BD |
32 | #include "sdhci.h" |
33 | ||
34 | #define MAX_BUS_CLK (4) | |
35 | ||
57f83245 JC |
36 | #define S3C_SDHCI_CONTROL2 (0x80) |
37 | #define S3C_SDHCI_CONTROL3 (0x84) | |
38 | #define S3C64XX_SDHCI_CONTROL4 (0x8C) | |
39 | ||
e64aae82 JC |
40 | #define S3C64XX_SDHCI_CTRL2_ENSTAASYNCCLR BIT(31) |
41 | #define S3C64XX_SDHCI_CTRL2_ENCMDCNFMSK BIT(30) | |
42 | #define S3C_SDHCI_CTRL2_CDINVRXD3 BIT(29) | |
43 | #define S3C_SDHCI_CTRL2_SLCARDOUT BIT(28) | |
57f83245 JC |
44 | |
45 | #define S3C_SDHCI_CTRL2_FLTCLKSEL_MASK (0xf << 24) | |
46 | #define S3C_SDHCI_CTRL2_FLTCLKSEL_SHIFT (24) | |
47 | #define S3C_SDHCI_CTRL2_FLTCLKSEL(_x) ((_x) << 24) | |
48 | ||
49 | #define S3C_SDHCI_CTRL2_LVLDAT_MASK (0xff << 16) | |
50 | #define S3C_SDHCI_CTRL2_LVLDAT_SHIFT (16) | |
51 | #define S3C_SDHCI_CTRL2_LVLDAT(_x) ((_x) << 16) | |
52 | ||
e64aae82 JC |
53 | #define S3C_SDHCI_CTRL2_ENFBCLKTX BIT(15) |
54 | #define S3C_SDHCI_CTRL2_ENFBCLKRX BIT(14) | |
55 | #define S3C_SDHCI_CTRL2_SDCDSEL BIT(13) | |
56 | #define S3C_SDHCI_CTRL2_SDSIGPC BIT(12) | |
57 | #define S3C_SDHCI_CTRL2_ENBUSYCHKTXSTART BIT(11) | |
57f83245 JC |
58 | |
59 | #define S3C_SDHCI_CTRL2_DFCNT_MASK (0x3 << 9) | |
60 | #define S3C_SDHCI_CTRL2_DFCNT_SHIFT (9) | |
61 | #define S3C_SDHCI_CTRL2_DFCNT_NONE (0x0 << 9) | |
62 | #define S3C_SDHCI_CTRL2_DFCNT_4SDCLK (0x1 << 9) | |
63 | #define S3C_SDHCI_CTRL2_DFCNT_16SDCLK (0x2 << 9) | |
64 | #define S3C_SDHCI_CTRL2_DFCNT_64SDCLK (0x3 << 9) | |
65 | ||
e64aae82 JC |
66 | #define S3C_SDHCI_CTRL2_ENCLKOUTHOLD BIT(8) |
67 | #define S3C_SDHCI_CTRL2_RWAITMODE BIT(7) | |
68 | #define S3C_SDHCI_CTRL2_DISBUFRD BIT(6) | |
69 | ||
57f83245 JC |
70 | #define S3C_SDHCI_CTRL2_SELBASECLK_MASK (0x3 << 4) |
71 | #define S3C_SDHCI_CTRL2_SELBASECLK_SHIFT (4) | |
e64aae82 JC |
72 | #define S3C_SDHCI_CTRL2_PWRSYNC BIT(3) |
73 | #define S3C_SDHCI_CTRL2_ENCLKOUTMSKCON BIT(1) | |
74 | #define S3C_SDHCI_CTRL2_HWINITFIN BIT(0) | |
57f83245 | 75 | |
e64aae82 JC |
76 | #define S3C_SDHCI_CTRL3_FCSEL3 BIT(31) |
77 | #define S3C_SDHCI_CTRL3_FCSEL2 BIT(23) | |
78 | #define S3C_SDHCI_CTRL3_FCSEL1 BIT(15) | |
79 | #define S3C_SDHCI_CTRL3_FCSEL0 BIT(7) | |
57f83245 JC |
80 | |
81 | #define S3C_SDHCI_CTRL3_FIA3_MASK (0x7f << 24) | |
82 | #define S3C_SDHCI_CTRL3_FIA3_SHIFT (24) | |
83 | #define S3C_SDHCI_CTRL3_FIA3(_x) ((_x) << 24) | |
84 | ||
85 | #define S3C_SDHCI_CTRL3_FIA2_MASK (0x7f << 16) | |
86 | #define S3C_SDHCI_CTRL3_FIA2_SHIFT (16) | |
87 | #define S3C_SDHCI_CTRL3_FIA2(_x) ((_x) << 16) | |
88 | ||
89 | #define S3C_SDHCI_CTRL3_FIA1_MASK (0x7f << 8) | |
90 | #define S3C_SDHCI_CTRL3_FIA1_SHIFT (8) | |
91 | #define S3C_SDHCI_CTRL3_FIA1(_x) ((_x) << 8) | |
92 | ||
93 | #define S3C_SDHCI_CTRL3_FIA0_MASK (0x7f << 0) | |
94 | #define S3C_SDHCI_CTRL3_FIA0_SHIFT (0) | |
95 | #define S3C_SDHCI_CTRL3_FIA0(_x) ((_x) << 0) | |
96 | ||
97 | #define S3C64XX_SDHCI_CONTROL4_DRIVE_MASK (0x3 << 16) | |
98 | #define S3C64XX_SDHCI_CONTROL4_DRIVE_SHIFT (16) | |
99 | #define S3C64XX_SDHCI_CONTROL4_DRIVE_2mA (0x0 << 16) | |
100 | #define S3C64XX_SDHCI_CONTROL4_DRIVE_4mA (0x1 << 16) | |
101 | #define S3C64XX_SDHCI_CONTROL4_DRIVE_7mA (0x2 << 16) | |
102 | #define S3C64XX_SDHCI_CONTROL4_DRIVE_9mA (0x3 << 16) | |
103 | ||
104 | #define S3C64XX_SDHCI_CONTROL4_BUSY (1) | |
105 | ||
0d1bb41a BD |
106 | /** |
107 | * struct sdhci_s3c - S3C SDHCI instance | |
108 | * @host: The SDHCI host created | |
109 | * @pdev: The platform device we where created from. | |
110 | * @ioarea: The resource created when we claimed the IO area. | |
111 | * @pdata: The platform data for this controller. | |
112 | * @cur_clk: The index of the current bus clock. | |
113 | * @clk_io: The clock for the internal bus interface. | |
114 | * @clk_bus: The clocks that are available for the SD/MMC bus clock. | |
115 | */ | |
116 | struct sdhci_s3c { | |
117 | struct sdhci_host *host; | |
118 | struct platform_device *pdev; | |
119 | struct resource *ioarea; | |
120 | struct s3c_sdhci_platdata *pdata; | |
3ac147fa | 121 | int cur_clk; |
17866e14 MS |
122 | int ext_cd_irq; |
123 | int ext_cd_gpio; | |
0d1bb41a BD |
124 | |
125 | struct clk *clk_io; | |
126 | struct clk *clk_bus[MAX_BUS_CLK]; | |
6eb28bdc | 127 | unsigned long clk_rates[MAX_BUS_CLK]; |
1771059c RK |
128 | |
129 | bool no_divider; | |
0d1bb41a BD |
130 | }; |
131 | ||
3119936a TA |
132 | /** |
133 | * struct sdhci_s3c_driver_data - S3C SDHCI platform specific driver data | |
134 | * @sdhci_quirks: sdhci host specific quirks. | |
135 | * | |
136 | * Specifies platform specific configuration of sdhci controller. | |
137 | * Note: A structure for driver specific platform data is used for future | |
138 | * expansion of its usage. | |
139 | */ | |
140 | struct sdhci_s3c_drv_data { | |
141 | unsigned int sdhci_quirks; | |
1771059c | 142 | bool no_divider; |
3119936a TA |
143 | }; |
144 | ||
0d1bb41a BD |
145 | static inline struct sdhci_s3c *to_s3c(struct sdhci_host *host) |
146 | { | |
147 | return sdhci_priv(host); | |
148 | } | |
149 | ||
0d1bb41a BD |
150 | /** |
151 | * sdhci_s3c_get_max_clk - callback to get maximum clock frequency. | |
152 | * @host: The SDHCI host instance. | |
153 | * | |
154 | * Callback to return the maximum clock rate acheivable by the controller. | |
155 | */ | |
156 | static unsigned int sdhci_s3c_get_max_clk(struct sdhci_host *host) | |
157 | { | |
158 | struct sdhci_s3c *ourhost = to_s3c(host); | |
222a13c5 TF |
159 | unsigned long rate, max = 0; |
160 | int src; | |
0d1bb41a | 161 | |
222a13c5 TF |
162 | for (src = 0; src < MAX_BUS_CLK; src++) { |
163 | rate = ourhost->clk_rates[src]; | |
0d1bb41a BD |
164 | if (rate > max) |
165 | max = rate; | |
166 | } | |
167 | ||
168 | return max; | |
169 | } | |
170 | ||
0d1bb41a BD |
171 | /** |
172 | * sdhci_s3c_consider_clock - consider one the bus clocks for current setting | |
173 | * @ourhost: Our SDHCI instance. | |
174 | * @src: The source clock index. | |
175 | * @wanted: The clock frequency wanted. | |
176 | */ | |
177 | static unsigned int sdhci_s3c_consider_clock(struct sdhci_s3c *ourhost, | |
178 | unsigned int src, | |
179 | unsigned int wanted) | |
180 | { | |
181 | unsigned long rate; | |
182 | struct clk *clksrc = ourhost->clk_bus[src]; | |
8880a4a5 | 183 | int shift; |
0d1bb41a | 184 | |
8f4b78d9 | 185 | if (IS_ERR(clksrc)) |
0d1bb41a BD |
186 | return UINT_MAX; |
187 | ||
253e0a7c | 188 | /* |
3119936a TA |
189 | * If controller uses a non-standard clock division, find the best clock |
190 | * speed possible with selected clock source and skip the division. | |
253e0a7c | 191 | */ |
1771059c | 192 | if (ourhost->no_divider) { |
69be8522 | 193 | spin_unlock_irq(&ourhost->host->lock); |
253e0a7c | 194 | rate = clk_round_rate(clksrc, wanted); |
69be8522 | 195 | spin_lock_irq(&ourhost->host->lock); |
253e0a7c JS |
196 | return wanted - rate; |
197 | } | |
198 | ||
6eb28bdc | 199 | rate = ourhost->clk_rates[src]; |
0d1bb41a | 200 | |
22003000 | 201 | for (shift = 0; shift <= 8; ++shift) { |
8880a4a5 | 202 | if ((rate >> shift) <= wanted) |
0d1bb41a BD |
203 | break; |
204 | } | |
22003000 TF |
205 | |
206 | if (shift > 8) { | |
207 | dev_dbg(&ourhost->pdev->dev, | |
208 | "clk %d: rate %ld, min rate %lu > wanted %u\n", | |
209 | src, rate, rate / 256, wanted); | |
210 | return UINT_MAX; | |
211 | } | |
0d1bb41a BD |
212 | |
213 | dev_dbg(&ourhost->pdev->dev, "clk %d: rate %ld, want %d, got %ld\n", | |
8880a4a5 | 214 | src, rate, wanted, rate >> shift); |
0d1bb41a | 215 | |
8880a4a5 | 216 | return wanted - (rate >> shift); |
0d1bb41a BD |
217 | } |
218 | ||
219 | /** | |
220 | * sdhci_s3c_set_clock - callback on clock change | |
221 | * @host: The SDHCI host being changed | |
222 | * @clock: The clock rate being requested. | |
223 | * | |
224 | * When the card's clock is going to be changed, look at the new frequency | |
225 | * and find the best clock source to go with it. | |
226 | */ | |
227 | static void sdhci_s3c_set_clock(struct sdhci_host *host, unsigned int clock) | |
228 | { | |
229 | struct sdhci_s3c *ourhost = to_s3c(host); | |
230 | unsigned int best = UINT_MAX; | |
231 | unsigned int delta; | |
232 | int best_src = 0; | |
233 | int src; | |
234 | u32 ctrl; | |
235 | ||
1650d0c7 RK |
236 | host->mmc->actual_clock = 0; |
237 | ||
0d1bb41a | 238 | /* don't bother if the clock is going off. */ |
1771059c RK |
239 | if (clock == 0) { |
240 | sdhci_set_clock(host, clock); | |
0d1bb41a | 241 | return; |
1771059c | 242 | } |
0d1bb41a BD |
243 | |
244 | for (src = 0; src < MAX_BUS_CLK; src++) { | |
245 | delta = sdhci_s3c_consider_clock(ourhost, src, clock); | |
246 | if (delta < best) { | |
247 | best = delta; | |
248 | best_src = src; | |
249 | } | |
250 | } | |
251 | ||
252 | dev_dbg(&ourhost->pdev->dev, | |
253 | "selected source %d, clock %d, delta %d\n", | |
254 | best_src, clock, best); | |
255 | ||
256 | /* select the new clock source */ | |
0d1bb41a BD |
257 | if (ourhost->cur_clk != best_src) { |
258 | struct clk *clk = ourhost->clk_bus[best_src]; | |
259 | ||
0f310a05 | 260 | clk_prepare_enable(clk); |
3ac147fa TF |
261 | if (ourhost->cur_clk >= 0) |
262 | clk_disable_unprepare( | |
263 | ourhost->clk_bus[ourhost->cur_clk]); | |
0d1bb41a BD |
264 | |
265 | ourhost->cur_clk = best_src; | |
6eb28bdc | 266 | host->max_clk = ourhost->clk_rates[best_src]; |
0d1bb41a BD |
267 | } |
268 | ||
3ac147fa TF |
269 | /* turn clock off to card before changing clock source */ |
270 | writew(0, host->ioaddr + SDHCI_CLOCK_CONTROL); | |
271 | ||
272 | ctrl = readl(host->ioaddr + S3C_SDHCI_CONTROL2); | |
273 | ctrl &= ~S3C_SDHCI_CTRL2_SELBASECLK_MASK; | |
274 | ctrl |= best_src << S3C_SDHCI_CTRL2_SELBASECLK_SHIFT; | |
275 | writel(ctrl, host->ioaddr + S3C_SDHCI_CONTROL2); | |
276 | ||
6fe47179 TA |
277 | /* reprogram default hardware configuration */ |
278 | writel(S3C64XX_SDHCI_CONTROL4_DRIVE_9mA, | |
279 | host->ioaddr + S3C64XX_SDHCI_CONTROL4); | |
280 | ||
281 | ctrl = readl(host->ioaddr + S3C_SDHCI_CONTROL2); | |
282 | ctrl |= (S3C64XX_SDHCI_CTRL2_ENSTAASYNCCLR | | |
283 | S3C64XX_SDHCI_CTRL2_ENCMDCNFMSK | | |
284 | S3C_SDHCI_CTRL2_ENFBCLKRX | | |
285 | S3C_SDHCI_CTRL2_DFCNT_NONE | | |
286 | S3C_SDHCI_CTRL2_ENCLKOUTHOLD); | |
287 | writel(ctrl, host->ioaddr + S3C_SDHCI_CONTROL2); | |
288 | ||
289 | /* reconfigure the controller for new clock rate */ | |
290 | ctrl = (S3C_SDHCI_CTRL3_FCSEL1 | S3C_SDHCI_CTRL3_FCSEL0); | |
291 | if (clock < 25 * 1000000) | |
292 | ctrl |= (S3C_SDHCI_CTRL3_FCSEL3 | S3C_SDHCI_CTRL3_FCSEL2); | |
293 | writel(ctrl, host->ioaddr + S3C_SDHCI_CONTROL3); | |
1771059c RK |
294 | |
295 | sdhci_set_clock(host, clock); | |
0d1bb41a BD |
296 | } |
297 | ||
ce5f036b MS |
298 | /** |
299 | * sdhci_s3c_get_min_clock - callback to get minimal supported clock value | |
300 | * @host: The SDHCI host being queried | |
301 | * | |
302 | * To init mmc host properly a minimal clock value is needed. For high system | |
303 | * bus clock's values the standard formula gives values out of allowed range. | |
304 | * The clock still can be set to lower values, if clock source other then | |
305 | * system bus is selected. | |
306 | */ | |
307 | static unsigned int sdhci_s3c_get_min_clock(struct sdhci_host *host) | |
308 | { | |
309 | struct sdhci_s3c *ourhost = to_s3c(host); | |
222a13c5 | 310 | unsigned long rate, min = ULONG_MAX; |
ce5f036b MS |
311 | int src; |
312 | ||
313 | for (src = 0; src < MAX_BUS_CLK; src++) { | |
222a13c5 TF |
314 | rate = ourhost->clk_rates[src] / 256; |
315 | if (!rate) | |
ce5f036b | 316 | continue; |
222a13c5 TF |
317 | if (rate < min) |
318 | min = rate; | |
ce5f036b | 319 | } |
222a13c5 | 320 | |
ce5f036b MS |
321 | return min; |
322 | } | |
323 | ||
253e0a7c JS |
324 | /* sdhci_cmu_get_max_clk - callback to get maximum clock frequency.*/ |
325 | static unsigned int sdhci_cmu_get_max_clock(struct sdhci_host *host) | |
326 | { | |
327 | struct sdhci_s3c *ourhost = to_s3c(host); | |
222a13c5 TF |
328 | unsigned long rate, max = 0; |
329 | int src; | |
330 | ||
331 | for (src = 0; src < MAX_BUS_CLK; src++) { | |
332 | struct clk *clk; | |
333 | ||
334 | clk = ourhost->clk_bus[src]; | |
335 | if (IS_ERR(clk)) | |
336 | continue; | |
337 | ||
338 | rate = clk_round_rate(clk, ULONG_MAX); | |
339 | if (rate > max) | |
340 | max = rate; | |
341 | } | |
253e0a7c | 342 | |
222a13c5 | 343 | return max; |
253e0a7c JS |
344 | } |
345 | ||
346 | /* sdhci_cmu_get_min_clock - callback to get minimal supported clock value. */ | |
347 | static unsigned int sdhci_cmu_get_min_clock(struct sdhci_host *host) | |
348 | { | |
349 | struct sdhci_s3c *ourhost = to_s3c(host); | |
222a13c5 TF |
350 | unsigned long rate, min = ULONG_MAX; |
351 | int src; | |
253e0a7c | 352 | |
222a13c5 TF |
353 | for (src = 0; src < MAX_BUS_CLK; src++) { |
354 | struct clk *clk; | |
355 | ||
356 | clk = ourhost->clk_bus[src]; | |
357 | if (IS_ERR(clk)) | |
358 | continue; | |
359 | ||
360 | rate = clk_round_rate(clk, 0); | |
361 | if (rate < min) | |
362 | min = rate; | |
363 | } | |
364 | ||
365 | return min; | |
253e0a7c JS |
366 | } |
367 | ||
368 | /* sdhci_cmu_set_clock - callback on clock change.*/ | |
369 | static void sdhci_cmu_set_clock(struct sdhci_host *host, unsigned int clock) | |
370 | { | |
371 | struct sdhci_s3c *ourhost = to_s3c(host); | |
2ad0b249 | 372 | struct device *dev = &ourhost->pdev->dev; |
3119936a TA |
373 | unsigned long timeout; |
374 | u16 clk = 0; | |
cd0cfdd2 | 375 | int ret; |
253e0a7c | 376 | |
1650d0c7 RK |
377 | host->mmc->actual_clock = 0; |
378 | ||
7ef2a5e2 JC |
379 | /* If the clock is going off, set to 0 at clock control register */ |
380 | if (clock == 0) { | |
381 | sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL); | |
253e0a7c | 382 | return; |
7ef2a5e2 | 383 | } |
253e0a7c JS |
384 | |
385 | sdhci_s3c_set_clock(host, clock); | |
386 | ||
017210d1 PO |
387 | /* Reset SD Clock Enable */ |
388 | clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); | |
389 | clk &= ~SDHCI_CLOCK_CARD_EN; | |
390 | sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); | |
391 | ||
392 | spin_unlock_irq(&host->lock); | |
cd0cfdd2 | 393 | ret = clk_set_rate(ourhost->clk_bus[ourhost->cur_clk], clock); |
017210d1 | 394 | spin_lock_irq(&host->lock); |
cd0cfdd2 MB |
395 | if (ret != 0) { |
396 | dev_err(dev, "%s: failed to set clock rate %uHz\n", | |
397 | mmc_hostname(host->mmc), clock); | |
398 | return; | |
399 | } | |
253e0a7c | 400 | |
3119936a TA |
401 | clk = SDHCI_CLOCK_INT_EN; |
402 | sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); | |
403 | ||
404 | /* Wait max 20 ms */ | |
405 | timeout = 20; | |
406 | while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL)) | |
407 | & SDHCI_CLOCK_INT_STABLE)) { | |
408 | if (timeout == 0) { | |
2ad0b249 JH |
409 | dev_err(dev, "%s: Internal clock never stabilised.\n", |
410 | mmc_hostname(host->mmc)); | |
3119936a TA |
411 | return; |
412 | } | |
413 | timeout--; | |
414 | mdelay(1); | |
415 | } | |
416 | ||
417 | clk |= SDHCI_CLOCK_CARD_EN; | |
418 | sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); | |
253e0a7c JS |
419 | } |
420 | ||
548f07d2 | 421 | /** |
2317f56c | 422 | * sdhci_s3c_set_bus_width - support 8bit buswidth |
548f07d2 JC |
423 | * @host: The SDHCI host being queried |
424 | * @width: MMC_BUS_WIDTH_ macro for the bus width being requested | |
425 | * | |
426 | * We have 8-bit width support but is not a v3 controller. | |
7bc088d3 | 427 | * So we add platform_bus_width() and support 8bit width. |
548f07d2 | 428 | */ |
2317f56c | 429 | static void sdhci_s3c_set_bus_width(struct sdhci_host *host, int width) |
548f07d2 JC |
430 | { |
431 | u8 ctrl; | |
432 | ||
433 | ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); | |
434 | ||
435 | switch (width) { | |
436 | case MMC_BUS_WIDTH_8: | |
437 | ctrl |= SDHCI_CTRL_8BITBUS; | |
438 | ctrl &= ~SDHCI_CTRL_4BITBUS; | |
439 | break; | |
440 | case MMC_BUS_WIDTH_4: | |
441 | ctrl |= SDHCI_CTRL_4BITBUS; | |
442 | ctrl &= ~SDHCI_CTRL_8BITBUS; | |
443 | break; | |
444 | default: | |
49bb1e61 G |
445 | ctrl &= ~SDHCI_CTRL_4BITBUS; |
446 | ctrl &= ~SDHCI_CTRL_8BITBUS; | |
548f07d2 JC |
447 | break; |
448 | } | |
449 | ||
450 | sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); | |
548f07d2 JC |
451 | } |
452 | ||
0d1bb41a BD |
453 | static struct sdhci_ops sdhci_s3c_ops = { |
454 | .get_max_clock = sdhci_s3c_get_max_clk, | |
0d1bb41a | 455 | .set_clock = sdhci_s3c_set_clock, |
ce5f036b | 456 | .get_min_clock = sdhci_s3c_get_min_clock, |
2317f56c | 457 | .set_bus_width = sdhci_s3c_set_bus_width, |
03231f9b | 458 | .reset = sdhci_reset, |
96d7b78c | 459 | .set_uhs_signaling = sdhci_set_uhs_signaling, |
0d1bb41a BD |
460 | }; |
461 | ||
cd1b00eb | 462 | #ifdef CONFIG_OF |
c3be1efd | 463 | static int sdhci_s3c_parse_dt(struct device *dev, |
cd1b00eb TA |
464 | struct sdhci_host *host, struct s3c_sdhci_platdata *pdata) |
465 | { | |
466 | struct device_node *node = dev->of_node; | |
cd1b00eb | 467 | u32 max_width; |
cd1b00eb TA |
468 | |
469 | /* if the bus-width property is not specified, assume width as 1 */ | |
470 | if (of_property_read_u32(node, "bus-width", &max_width)) | |
471 | max_width = 1; | |
472 | pdata->max_width = max_width; | |
473 | ||
cd1b00eb | 474 | /* get the card detection method */ |
ab5023ef | 475 | if (of_get_property(node, "broken-cd", NULL)) { |
cd1b00eb | 476 | pdata->cd_type = S3C_SDHCI_CD_NONE; |
e19499ae | 477 | return 0; |
cd1b00eb TA |
478 | } |
479 | ||
ab5023ef | 480 | if (of_get_property(node, "non-removable", NULL)) { |
cd1b00eb | 481 | pdata->cd_type = S3C_SDHCI_CD_PERMANENT; |
e19499ae | 482 | return 0; |
cd1b00eb TA |
483 | } |
484 | ||
11bc9381 | 485 | if (of_get_named_gpio(node, "cd-gpios", 0)) |
b96efccb | 486 | return 0; |
cd1b00eb | 487 | |
e19499ae TA |
488 | /* assuming internal card detect that will be configured by pinctrl */ |
489 | pdata->cd_type = S3C_SDHCI_CD_INTERNAL; | |
cd1b00eb | 490 | return 0; |
cd1b00eb TA |
491 | } |
492 | #else | |
c3be1efd | 493 | static int sdhci_s3c_parse_dt(struct device *dev, |
cd1b00eb TA |
494 | struct sdhci_host *host, struct s3c_sdhci_platdata *pdata) |
495 | { | |
496 | return -EINVAL; | |
497 | } | |
498 | #endif | |
499 | ||
500 | static const struct of_device_id sdhci_s3c_dt_match[]; | |
501 | ||
3119936a TA |
502 | static inline struct sdhci_s3c_drv_data *sdhci_s3c_get_driver_data( |
503 | struct platform_device *pdev) | |
504 | { | |
cd1b00eb TA |
505 | #ifdef CONFIG_OF |
506 | if (pdev->dev.of_node) { | |
507 | const struct of_device_id *match; | |
508 | match = of_match_node(sdhci_s3c_dt_match, pdev->dev.of_node); | |
509 | return (struct sdhci_s3c_drv_data *)match->data; | |
510 | } | |
511 | #endif | |
3119936a TA |
512 | return (struct sdhci_s3c_drv_data *) |
513 | platform_get_device_id(pdev)->driver_data; | |
514 | } | |
515 | ||
c3be1efd | 516 | static int sdhci_s3c_probe(struct platform_device *pdev) |
0d1bb41a | 517 | { |
1d4dc338 | 518 | struct s3c_sdhci_platdata *pdata; |
3119936a | 519 | struct sdhci_s3c_drv_data *drv_data; |
0d1bb41a BD |
520 | struct device *dev = &pdev->dev; |
521 | struct sdhci_host *host; | |
522 | struct sdhci_s3c *sc; | |
523 | struct resource *res; | |
524 | int ret, irq, ptr, clks; | |
525 | ||
cd1b00eb | 526 | if (!pdev->dev.platform_data && !pdev->dev.of_node) { |
0d1bb41a BD |
527 | dev_err(dev, "no device data specified\n"); |
528 | return -ENOENT; | |
529 | } | |
530 | ||
531 | irq = platform_get_irq(pdev, 0); | |
532 | if (irq < 0) { | |
533 | dev_err(dev, "no irq specified\n"); | |
534 | return irq; | |
535 | } | |
536 | ||
0d1bb41a BD |
537 | host = sdhci_alloc_host(dev, sizeof(struct sdhci_s3c)); |
538 | if (IS_ERR(host)) { | |
539 | dev_err(dev, "sdhci_alloc_host() failed\n"); | |
540 | return PTR_ERR(host); | |
541 | } | |
cd1b00eb | 542 | sc = sdhci_priv(host); |
0d1bb41a | 543 | |
1d4dc338 TA |
544 | pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); |
545 | if (!pdata) { | |
546 | ret = -ENOMEM; | |
b1b8fea9 | 547 | goto err_pdata_io_clk; |
cd1b00eb TA |
548 | } |
549 | ||
550 | if (pdev->dev.of_node) { | |
551 | ret = sdhci_s3c_parse_dt(&pdev->dev, host, pdata); | |
552 | if (ret) | |
b1b8fea9 | 553 | goto err_pdata_io_clk; |
cd1b00eb TA |
554 | } else { |
555 | memcpy(pdata, pdev->dev.platform_data, sizeof(*pdata)); | |
556 | sc->ext_cd_gpio = -1; /* invalid gpio number */ | |
1d4dc338 | 557 | } |
1d4dc338 | 558 | |
3119936a | 559 | drv_data = sdhci_s3c_get_driver_data(pdev); |
0d1bb41a BD |
560 | |
561 | sc->host = host; | |
562 | sc->pdev = pdev; | |
563 | sc->pdata = pdata; | |
3ac147fa | 564 | sc->cur_clk = -1; |
0d1bb41a BD |
565 | |
566 | platform_set_drvdata(pdev, host); | |
567 | ||
3aaf7ba7 | 568 | sc->clk_io = devm_clk_get(dev, "hsmmc"); |
0d1bb41a BD |
569 | if (IS_ERR(sc->clk_io)) { |
570 | dev_err(dev, "failed to get io clock\n"); | |
571 | ret = PTR_ERR(sc->clk_io); | |
b1b8fea9 | 572 | goto err_pdata_io_clk; |
0d1bb41a BD |
573 | } |
574 | ||
575 | /* enable the local io clock and keep it running for the moment. */ | |
0f310a05 | 576 | clk_prepare_enable(sc->clk_io); |
0d1bb41a BD |
577 | |
578 | for (clks = 0, ptr = 0; ptr < MAX_BUS_CLK; ptr++) { | |
4346b6d9 | 579 | char name[14]; |
0d1bb41a | 580 | |
4346b6d9 | 581 | snprintf(name, 14, "mmc_busclk.%d", ptr); |
8f4b78d9 TF |
582 | sc->clk_bus[ptr] = devm_clk_get(dev, name); |
583 | if (IS_ERR(sc->clk_bus[ptr])) | |
0d1bb41a | 584 | continue; |
0d1bb41a BD |
585 | |
586 | clks++; | |
6eb28bdc TF |
587 | sc->clk_rates[ptr] = clk_get_rate(sc->clk_bus[ptr]); |
588 | ||
0d1bb41a | 589 | dev_info(dev, "clock source %d: %s (%ld Hz)\n", |
6eb28bdc | 590 | ptr, name, sc->clk_rates[ptr]); |
0d1bb41a BD |
591 | } |
592 | ||
593 | if (clks == 0) { | |
594 | dev_err(dev, "failed to find any bus clocks\n"); | |
595 | ret = -ENOENT; | |
596 | goto err_no_busclks; | |
597 | } | |
598 | ||
9bda6da7 | 599 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
a3e2cd7f TR |
600 | host->ioaddr = devm_ioremap_resource(&pdev->dev, res); |
601 | if (IS_ERR(host->ioaddr)) { | |
602 | ret = PTR_ERR(host->ioaddr); | |
0d1bb41a BD |
603 | goto err_req_regs; |
604 | } | |
605 | ||
606 | /* Ensure we have minimal gpio selected CMD/CLK/Detect */ | |
607 | if (pdata->cfg_gpio) | |
608 | pdata->cfg_gpio(pdev, pdata->max_width); | |
609 | ||
610 | host->hw_name = "samsung-hsmmc"; | |
611 | host->ops = &sdhci_s3c_ops; | |
612 | host->quirks = 0; | |
285e244f | 613 | host->quirks2 = 0; |
0d1bb41a BD |
614 | host->irq = irq; |
615 | ||
616 | /* Setup quirks for the controller */ | |
b2e75eff | 617 | host->quirks |= SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC; |
a1d56460 | 618 | host->quirks |= SDHCI_QUIRK_NO_HISPD_BIT; |
1771059c | 619 | if (drv_data) { |
3119936a | 620 | host->quirks |= drv_data->sdhci_quirks; |
1771059c RK |
621 | sc->no_divider = drv_data->no_divider; |
622 | } | |
0d1bb41a BD |
623 | |
624 | #ifndef CONFIG_MMC_SDHCI_S3C_DMA | |
625 | ||
626 | /* we currently see overruns on errors, so disable the SDMA | |
627 | * support as well. */ | |
628 | host->quirks |= SDHCI_QUIRK_BROKEN_DMA; | |
629 | ||
630 | #endif /* CONFIG_MMC_SDHCI_S3C_DMA */ | |
631 | ||
632 | /* It seems we do not get an DATA transfer complete on non-busy | |
633 | * transfers, not sure if this is a problem with this specific | |
634 | * SDHCI block, or a missing configuration that needs to be set. */ | |
635 | host->quirks |= SDHCI_QUIRK_NO_BUSY_IRQ; | |
636 | ||
732f0e31 KP |
637 | /* This host supports the Auto CMD12 */ |
638 | host->quirks |= SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12; | |
639 | ||
7199e2b6 JC |
640 | /* Samsung SoCs need BROKEN_ADMA_ZEROLEN_DESC */ |
641 | host->quirks |= SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC; | |
642 | ||
17866e14 MS |
643 | if (pdata->cd_type == S3C_SDHCI_CD_NONE || |
644 | pdata->cd_type == S3C_SDHCI_CD_PERMANENT) | |
645 | host->quirks |= SDHCI_QUIRK_BROKEN_CARD_DETECTION; | |
646 | ||
647 | if (pdata->cd_type == S3C_SDHCI_CD_PERMANENT) | |
648 | host->mmc->caps = MMC_CAP_NONREMOVABLE; | |
649 | ||
0d22c770 TA |
650 | switch (pdata->max_width) { |
651 | case 8: | |
652 | host->mmc->caps |= MMC_CAP_8_BIT_DATA; | |
653 | case 4: | |
654 | host->mmc->caps |= MMC_CAP_4_BIT_DATA; | |
655 | break; | |
656 | } | |
657 | ||
fa1773cc SL |
658 | if (pdata->pm_caps) |
659 | host->mmc->pm_caps |= pdata->pm_caps; | |
660 | ||
0d1bb41a BD |
661 | host->quirks |= (SDHCI_QUIRK_32BIT_DMA_ADDR | |
662 | SDHCI_QUIRK_32BIT_DMA_SIZE); | |
663 | ||
3fe42e07 HL |
664 | /* HSMMC on Samsung SoCs uses SDCLK as timeout clock */ |
665 | host->quirks |= SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK; | |
666 | ||
253e0a7c JS |
667 | /* |
668 | * If controller does not have internal clock divider, | |
669 | * we can use overriding functions instead of default. | |
670 | */ | |
1771059c | 671 | if (sc->no_divider) { |
253e0a7c JS |
672 | sdhci_s3c_ops.set_clock = sdhci_cmu_set_clock; |
673 | sdhci_s3c_ops.get_min_clock = sdhci_cmu_get_min_clock; | |
674 | sdhci_s3c_ops.get_max_clock = sdhci_cmu_get_max_clock; | |
675 | } | |
676 | ||
b3824f2c JS |
677 | /* It supports additional host capabilities if needed */ |
678 | if (pdata->host_caps) | |
679 | host->mmc->caps |= pdata->host_caps; | |
680 | ||
c1c4b66d JC |
681 | if (pdata->host_caps2) |
682 | host->mmc->caps2 |= pdata->host_caps2; | |
683 | ||
9f4e8151 MB |
684 | pm_runtime_enable(&pdev->dev); |
685 | pm_runtime_set_autosuspend_delay(&pdev->dev, 50); | |
686 | pm_runtime_use_autosuspend(&pdev->dev); | |
687 | pm_suspend_ignore_children(&pdev->dev, 1); | |
688 | ||
f8e3260c UH |
689 | ret = mmc_of_parse(host->mmc); |
690 | if (ret) | |
691 | goto err_req_regs; | |
11bc9381 | 692 | |
0d1bb41a BD |
693 | ret = sdhci_add_host(host); |
694 | if (ret) { | |
695 | dev_err(dev, "sdhci_add_host() failed\n"); | |
9bda6da7 | 696 | goto err_req_regs; |
0d1bb41a BD |
697 | } |
698 | ||
162d6f98 | 699 | #ifdef CONFIG_PM |
0aa55c23 SJ |
700 | if (pdata->cd_type != S3C_SDHCI_CD_INTERNAL) |
701 | clk_disable_unprepare(sc->clk_io); | |
2abeb5c5 | 702 | #endif |
0d1bb41a BD |
703 | return 0; |
704 | ||
0d1bb41a | 705 | err_req_regs: |
221414db BZ |
706 | pm_runtime_disable(&pdev->dev); |
707 | ||
0d1bb41a | 708 | err_no_busclks: |
0f310a05 | 709 | clk_disable_unprepare(sc->clk_io); |
0d1bb41a | 710 | |
b1b8fea9 | 711 | err_pdata_io_clk: |
0d1bb41a BD |
712 | sdhci_free_host(host); |
713 | ||
714 | return ret; | |
715 | } | |
716 | ||
6e0ee714 | 717 | static int sdhci_s3c_remove(struct platform_device *pdev) |
0d1bb41a | 718 | { |
9d51a6b2 MS |
719 | struct sdhci_host *host = platform_get_drvdata(pdev); |
720 | struct sdhci_s3c *sc = sdhci_priv(host); | |
17866e14 MS |
721 | |
722 | if (sc->ext_cd_irq) | |
723 | free_irq(sc->ext_cd_irq, sc); | |
724 | ||
162d6f98 | 725 | #ifdef CONFIG_PM |
11bc9381 | 726 | if (sc->pdata->cd_type != S3C_SDHCI_CD_INTERNAL) |
0aa55c23 | 727 | clk_prepare_enable(sc->clk_io); |
2abeb5c5 | 728 | #endif |
9d51a6b2 MS |
729 | sdhci_remove_host(host, 1); |
730 | ||
387a8cbd | 731 | pm_runtime_dont_use_autosuspend(&pdev->dev); |
9f4e8151 MB |
732 | pm_runtime_disable(&pdev->dev); |
733 | ||
0f310a05 | 734 | clk_disable_unprepare(sc->clk_io); |
9d51a6b2 | 735 | |
9d51a6b2 | 736 | sdhci_free_host(host); |
9d51a6b2 | 737 | |
0d1bb41a BD |
738 | return 0; |
739 | } | |
740 | ||
d5e9c02c | 741 | #ifdef CONFIG_PM_SLEEP |
29495aa0 | 742 | static int sdhci_s3c_suspend(struct device *dev) |
0d1bb41a | 743 | { |
29495aa0 | 744 | struct sdhci_host *host = dev_get_drvdata(dev); |
0d1bb41a | 745 | |
29495aa0 | 746 | return sdhci_suspend_host(host); |
0d1bb41a BD |
747 | } |
748 | ||
29495aa0 | 749 | static int sdhci_s3c_resume(struct device *dev) |
0d1bb41a | 750 | { |
29495aa0 | 751 | struct sdhci_host *host = dev_get_drvdata(dev); |
0d1bb41a | 752 | |
65d13516 | 753 | return sdhci_resume_host(host); |
0d1bb41a | 754 | } |
d5e9c02c | 755 | #endif |
0d1bb41a | 756 | |
162d6f98 | 757 | #ifdef CONFIG_PM |
9f4e8151 MB |
758 | static int sdhci_s3c_runtime_suspend(struct device *dev) |
759 | { | |
760 | struct sdhci_host *host = dev_get_drvdata(dev); | |
2abeb5c5 CK |
761 | struct sdhci_s3c *ourhost = to_s3c(host); |
762 | struct clk *busclk = ourhost->clk_io; | |
763 | int ret; | |
764 | ||
765 | ret = sdhci_runtime_suspend_host(host); | |
9f4e8151 | 766 | |
3ac147fa TF |
767 | if (ourhost->cur_clk >= 0) |
768 | clk_disable_unprepare(ourhost->clk_bus[ourhost->cur_clk]); | |
0f310a05 | 769 | clk_disable_unprepare(busclk); |
2abeb5c5 | 770 | return ret; |
9f4e8151 MB |
771 | } |
772 | ||
773 | static int sdhci_s3c_runtime_resume(struct device *dev) | |
774 | { | |
775 | struct sdhci_host *host = dev_get_drvdata(dev); | |
2abeb5c5 CK |
776 | struct sdhci_s3c *ourhost = to_s3c(host); |
777 | struct clk *busclk = ourhost->clk_io; | |
778 | int ret; | |
9f4e8151 | 779 | |
0f310a05 | 780 | clk_prepare_enable(busclk); |
3ac147fa TF |
781 | if (ourhost->cur_clk >= 0) |
782 | clk_prepare_enable(ourhost->clk_bus[ourhost->cur_clk]); | |
2abeb5c5 CK |
783 | ret = sdhci_runtime_resume_host(host); |
784 | return ret; | |
9f4e8151 MB |
785 | } |
786 | #endif | |
787 | ||
29495aa0 | 788 | static const struct dev_pm_ops sdhci_s3c_pmops = { |
d5e9c02c | 789 | SET_SYSTEM_SLEEP_PM_OPS(sdhci_s3c_suspend, sdhci_s3c_resume) |
9f4e8151 MB |
790 | SET_RUNTIME_PM_OPS(sdhci_s3c_runtime_suspend, sdhci_s3c_runtime_resume, |
791 | NULL) | |
29495aa0 ML |
792 | }; |
793 | ||
3119936a TA |
794 | #if defined(CONFIG_CPU_EXYNOS4210) || defined(CONFIG_SOC_EXYNOS4212) |
795 | static struct sdhci_s3c_drv_data exynos4_sdhci_drv_data = { | |
1771059c | 796 | .no_divider = true, |
3119936a TA |
797 | }; |
798 | #define EXYNOS4_SDHCI_DRV_DATA ((kernel_ulong_t)&exynos4_sdhci_drv_data) | |
799 | #else | |
800 | #define EXYNOS4_SDHCI_DRV_DATA ((kernel_ulong_t)NULL) | |
801 | #endif | |
802 | ||
4d0aa491 | 803 | static const struct platform_device_id sdhci_s3c_driver_ids[] = { |
3119936a TA |
804 | { |
805 | .name = "s3c-sdhci", | |
806 | .driver_data = (kernel_ulong_t)NULL, | |
807 | }, { | |
808 | .name = "exynos4-sdhci", | |
809 | .driver_data = EXYNOS4_SDHCI_DRV_DATA, | |
810 | }, | |
811 | { } | |
812 | }; | |
813 | MODULE_DEVICE_TABLE(platform, sdhci_s3c_driver_ids); | |
814 | ||
cd1b00eb TA |
815 | #ifdef CONFIG_OF |
816 | static const struct of_device_id sdhci_s3c_dt_match[] = { | |
817 | { .compatible = "samsung,s3c6410-sdhci", }, | |
818 | { .compatible = "samsung,exynos4210-sdhci", | |
819 | .data = (void *)EXYNOS4_SDHCI_DRV_DATA }, | |
820 | {}, | |
821 | }; | |
822 | MODULE_DEVICE_TABLE(of, sdhci_s3c_dt_match); | |
823 | #endif | |
824 | ||
0d1bb41a BD |
825 | static struct platform_driver sdhci_s3c_driver = { |
826 | .probe = sdhci_s3c_probe, | |
0433c143 | 827 | .remove = sdhci_s3c_remove, |
3119936a | 828 | .id_table = sdhci_s3c_driver_ids, |
0d1bb41a | 829 | .driver = { |
0d1bb41a | 830 | .name = "s3c-sdhci", |
cd1b00eb | 831 | .of_match_table = of_match_ptr(sdhci_s3c_dt_match), |
6b3a194b | 832 | .pm = &sdhci_s3c_pmops, |
0d1bb41a BD |
833 | }, |
834 | }; | |
835 | ||
d1f81a64 | 836 | module_platform_driver(sdhci_s3c_driver); |
0d1bb41a BD |
837 | |
838 | MODULE_DESCRIPTION("Samsung SDHCI (HSMMC) glue"); | |
839 | MODULE_AUTHOR("Ben Dooks, <ben@simtec.co.uk>"); | |
840 | MODULE_LICENSE("GPL v2"); | |
841 | MODULE_ALIAS("platform:s3c-sdhci"); |