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0d1bb41a BD |
1 | /* linux/drivers/mmc/host/sdhci-s3c.c |
2 | * | |
3 | * Copyright 2008 Openmoko Inc. | |
4 | * Copyright 2008 Simtec Electronics | |
5 | * Ben Dooks <ben@simtec.co.uk> | |
6 | * http://armlinux.simtec.co.uk/ | |
7 | * | |
8 | * SDHCI (HSMMC) support for Samsung SoC | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License version 2 as | |
12 | * published by the Free Software Foundation. | |
13 | */ | |
14 | ||
15 | #include <linux/delay.h> | |
16 | #include <linux/dma-mapping.h> | |
17 | #include <linux/platform_device.h> | |
cc014f3e | 18 | #include <linux/platform_data/mmc-sdhci-s3c.h> |
5a0e3ad6 | 19 | #include <linux/slab.h> |
0d1bb41a BD |
20 | #include <linux/clk.h> |
21 | #include <linux/io.h> | |
17866e14 | 22 | #include <linux/gpio.h> |
55156d24 | 23 | #include <linux/module.h> |
d5e9c02c MB |
24 | #include <linux/of.h> |
25 | #include <linux/of_gpio.h> | |
26 | #include <linux/pm.h> | |
9f4e8151 | 27 | #include <linux/pm_runtime.h> |
0d1bb41a BD |
28 | |
29 | #include <linux/mmc/host.h> | |
30 | ||
cc014f3e | 31 | #include "sdhci-s3c-regs.h" |
0d1bb41a BD |
32 | #include "sdhci.h" |
33 | ||
34 | #define MAX_BUS_CLK (4) | |
35 | ||
36 | /** | |
37 | * struct sdhci_s3c - S3C SDHCI instance | |
38 | * @host: The SDHCI host created | |
39 | * @pdev: The platform device we where created from. | |
40 | * @ioarea: The resource created when we claimed the IO area. | |
41 | * @pdata: The platform data for this controller. | |
42 | * @cur_clk: The index of the current bus clock. | |
43 | * @clk_io: The clock for the internal bus interface. | |
44 | * @clk_bus: The clocks that are available for the SD/MMC bus clock. | |
45 | */ | |
46 | struct sdhci_s3c { | |
47 | struct sdhci_host *host; | |
48 | struct platform_device *pdev; | |
49 | struct resource *ioarea; | |
50 | struct s3c_sdhci_platdata *pdata; | |
3ac147fa | 51 | int cur_clk; |
17866e14 MS |
52 | int ext_cd_irq; |
53 | int ext_cd_gpio; | |
0d1bb41a BD |
54 | |
55 | struct clk *clk_io; | |
56 | struct clk *clk_bus[MAX_BUS_CLK]; | |
6eb28bdc | 57 | unsigned long clk_rates[MAX_BUS_CLK]; |
1771059c RK |
58 | |
59 | bool no_divider; | |
0d1bb41a BD |
60 | }; |
61 | ||
3119936a TA |
62 | /** |
63 | * struct sdhci_s3c_driver_data - S3C SDHCI platform specific driver data | |
64 | * @sdhci_quirks: sdhci host specific quirks. | |
65 | * | |
66 | * Specifies platform specific configuration of sdhci controller. | |
67 | * Note: A structure for driver specific platform data is used for future | |
68 | * expansion of its usage. | |
69 | */ | |
70 | struct sdhci_s3c_drv_data { | |
71 | unsigned int sdhci_quirks; | |
1771059c | 72 | bool no_divider; |
3119936a TA |
73 | }; |
74 | ||
0d1bb41a BD |
75 | static inline struct sdhci_s3c *to_s3c(struct sdhci_host *host) |
76 | { | |
77 | return sdhci_priv(host); | |
78 | } | |
79 | ||
0d1bb41a BD |
80 | /** |
81 | * sdhci_s3c_get_max_clk - callback to get maximum clock frequency. | |
82 | * @host: The SDHCI host instance. | |
83 | * | |
84 | * Callback to return the maximum clock rate acheivable by the controller. | |
85 | */ | |
86 | static unsigned int sdhci_s3c_get_max_clk(struct sdhci_host *host) | |
87 | { | |
88 | struct sdhci_s3c *ourhost = to_s3c(host); | |
222a13c5 TF |
89 | unsigned long rate, max = 0; |
90 | int src; | |
0d1bb41a | 91 | |
222a13c5 TF |
92 | for (src = 0; src < MAX_BUS_CLK; src++) { |
93 | rate = ourhost->clk_rates[src]; | |
0d1bb41a BD |
94 | if (rate > max) |
95 | max = rate; | |
96 | } | |
97 | ||
98 | return max; | |
99 | } | |
100 | ||
0d1bb41a BD |
101 | /** |
102 | * sdhci_s3c_consider_clock - consider one the bus clocks for current setting | |
103 | * @ourhost: Our SDHCI instance. | |
104 | * @src: The source clock index. | |
105 | * @wanted: The clock frequency wanted. | |
106 | */ | |
107 | static unsigned int sdhci_s3c_consider_clock(struct sdhci_s3c *ourhost, | |
108 | unsigned int src, | |
109 | unsigned int wanted) | |
110 | { | |
111 | unsigned long rate; | |
112 | struct clk *clksrc = ourhost->clk_bus[src]; | |
8880a4a5 | 113 | int shift; |
0d1bb41a | 114 | |
8f4b78d9 | 115 | if (IS_ERR(clksrc)) |
0d1bb41a BD |
116 | return UINT_MAX; |
117 | ||
253e0a7c | 118 | /* |
3119936a TA |
119 | * If controller uses a non-standard clock division, find the best clock |
120 | * speed possible with selected clock source and skip the division. | |
253e0a7c | 121 | */ |
1771059c | 122 | if (ourhost->no_divider) { |
253e0a7c JS |
123 | rate = clk_round_rate(clksrc, wanted); |
124 | return wanted - rate; | |
125 | } | |
126 | ||
6eb28bdc | 127 | rate = ourhost->clk_rates[src]; |
0d1bb41a | 128 | |
22003000 | 129 | for (shift = 0; shift <= 8; ++shift) { |
8880a4a5 | 130 | if ((rate >> shift) <= wanted) |
0d1bb41a BD |
131 | break; |
132 | } | |
22003000 TF |
133 | |
134 | if (shift > 8) { | |
135 | dev_dbg(&ourhost->pdev->dev, | |
136 | "clk %d: rate %ld, min rate %lu > wanted %u\n", | |
137 | src, rate, rate / 256, wanted); | |
138 | return UINT_MAX; | |
139 | } | |
0d1bb41a BD |
140 | |
141 | dev_dbg(&ourhost->pdev->dev, "clk %d: rate %ld, want %d, got %ld\n", | |
8880a4a5 | 142 | src, rate, wanted, rate >> shift); |
0d1bb41a | 143 | |
8880a4a5 | 144 | return wanted - (rate >> shift); |
0d1bb41a BD |
145 | } |
146 | ||
147 | /** | |
148 | * sdhci_s3c_set_clock - callback on clock change | |
149 | * @host: The SDHCI host being changed | |
150 | * @clock: The clock rate being requested. | |
151 | * | |
152 | * When the card's clock is going to be changed, look at the new frequency | |
153 | * and find the best clock source to go with it. | |
154 | */ | |
155 | static void sdhci_s3c_set_clock(struct sdhci_host *host, unsigned int clock) | |
156 | { | |
157 | struct sdhci_s3c *ourhost = to_s3c(host); | |
158 | unsigned int best = UINT_MAX; | |
159 | unsigned int delta; | |
160 | int best_src = 0; | |
161 | int src; | |
162 | u32 ctrl; | |
163 | ||
1650d0c7 RK |
164 | host->mmc->actual_clock = 0; |
165 | ||
0d1bb41a | 166 | /* don't bother if the clock is going off. */ |
1771059c RK |
167 | if (clock == 0) { |
168 | sdhci_set_clock(host, clock); | |
0d1bb41a | 169 | return; |
1771059c | 170 | } |
0d1bb41a BD |
171 | |
172 | for (src = 0; src < MAX_BUS_CLK; src++) { | |
173 | delta = sdhci_s3c_consider_clock(ourhost, src, clock); | |
174 | if (delta < best) { | |
175 | best = delta; | |
176 | best_src = src; | |
177 | } | |
178 | } | |
179 | ||
180 | dev_dbg(&ourhost->pdev->dev, | |
181 | "selected source %d, clock %d, delta %d\n", | |
182 | best_src, clock, best); | |
183 | ||
184 | /* select the new clock source */ | |
0d1bb41a BD |
185 | if (ourhost->cur_clk != best_src) { |
186 | struct clk *clk = ourhost->clk_bus[best_src]; | |
187 | ||
0f310a05 | 188 | clk_prepare_enable(clk); |
3ac147fa TF |
189 | if (ourhost->cur_clk >= 0) |
190 | clk_disable_unprepare( | |
191 | ourhost->clk_bus[ourhost->cur_clk]); | |
0d1bb41a BD |
192 | |
193 | ourhost->cur_clk = best_src; | |
6eb28bdc | 194 | host->max_clk = ourhost->clk_rates[best_src]; |
0d1bb41a BD |
195 | } |
196 | ||
3ac147fa TF |
197 | /* turn clock off to card before changing clock source */ |
198 | writew(0, host->ioaddr + SDHCI_CLOCK_CONTROL); | |
199 | ||
200 | ctrl = readl(host->ioaddr + S3C_SDHCI_CONTROL2); | |
201 | ctrl &= ~S3C_SDHCI_CTRL2_SELBASECLK_MASK; | |
202 | ctrl |= best_src << S3C_SDHCI_CTRL2_SELBASECLK_SHIFT; | |
203 | writel(ctrl, host->ioaddr + S3C_SDHCI_CONTROL2); | |
204 | ||
6fe47179 TA |
205 | /* reprogram default hardware configuration */ |
206 | writel(S3C64XX_SDHCI_CONTROL4_DRIVE_9mA, | |
207 | host->ioaddr + S3C64XX_SDHCI_CONTROL4); | |
208 | ||
209 | ctrl = readl(host->ioaddr + S3C_SDHCI_CONTROL2); | |
210 | ctrl |= (S3C64XX_SDHCI_CTRL2_ENSTAASYNCCLR | | |
211 | S3C64XX_SDHCI_CTRL2_ENCMDCNFMSK | | |
212 | S3C_SDHCI_CTRL2_ENFBCLKRX | | |
213 | S3C_SDHCI_CTRL2_DFCNT_NONE | | |
214 | S3C_SDHCI_CTRL2_ENCLKOUTHOLD); | |
215 | writel(ctrl, host->ioaddr + S3C_SDHCI_CONTROL2); | |
216 | ||
217 | /* reconfigure the controller for new clock rate */ | |
218 | ctrl = (S3C_SDHCI_CTRL3_FCSEL1 | S3C_SDHCI_CTRL3_FCSEL0); | |
219 | if (clock < 25 * 1000000) | |
220 | ctrl |= (S3C_SDHCI_CTRL3_FCSEL3 | S3C_SDHCI_CTRL3_FCSEL2); | |
221 | writel(ctrl, host->ioaddr + S3C_SDHCI_CONTROL3); | |
1771059c RK |
222 | |
223 | sdhci_set_clock(host, clock); | |
0d1bb41a BD |
224 | } |
225 | ||
ce5f036b MS |
226 | /** |
227 | * sdhci_s3c_get_min_clock - callback to get minimal supported clock value | |
228 | * @host: The SDHCI host being queried | |
229 | * | |
230 | * To init mmc host properly a minimal clock value is needed. For high system | |
231 | * bus clock's values the standard formula gives values out of allowed range. | |
232 | * The clock still can be set to lower values, if clock source other then | |
233 | * system bus is selected. | |
234 | */ | |
235 | static unsigned int sdhci_s3c_get_min_clock(struct sdhci_host *host) | |
236 | { | |
237 | struct sdhci_s3c *ourhost = to_s3c(host); | |
222a13c5 | 238 | unsigned long rate, min = ULONG_MAX; |
ce5f036b MS |
239 | int src; |
240 | ||
241 | for (src = 0; src < MAX_BUS_CLK; src++) { | |
222a13c5 TF |
242 | rate = ourhost->clk_rates[src] / 256; |
243 | if (!rate) | |
ce5f036b | 244 | continue; |
222a13c5 TF |
245 | if (rate < min) |
246 | min = rate; | |
ce5f036b | 247 | } |
222a13c5 | 248 | |
ce5f036b MS |
249 | return min; |
250 | } | |
251 | ||
253e0a7c JS |
252 | /* sdhci_cmu_get_max_clk - callback to get maximum clock frequency.*/ |
253 | static unsigned int sdhci_cmu_get_max_clock(struct sdhci_host *host) | |
254 | { | |
255 | struct sdhci_s3c *ourhost = to_s3c(host); | |
222a13c5 TF |
256 | unsigned long rate, max = 0; |
257 | int src; | |
258 | ||
259 | for (src = 0; src < MAX_BUS_CLK; src++) { | |
260 | struct clk *clk; | |
261 | ||
262 | clk = ourhost->clk_bus[src]; | |
263 | if (IS_ERR(clk)) | |
264 | continue; | |
265 | ||
266 | rate = clk_round_rate(clk, ULONG_MAX); | |
267 | if (rate > max) | |
268 | max = rate; | |
269 | } | |
253e0a7c | 270 | |
222a13c5 | 271 | return max; |
253e0a7c JS |
272 | } |
273 | ||
274 | /* sdhci_cmu_get_min_clock - callback to get minimal supported clock value. */ | |
275 | static unsigned int sdhci_cmu_get_min_clock(struct sdhci_host *host) | |
276 | { | |
277 | struct sdhci_s3c *ourhost = to_s3c(host); | |
222a13c5 TF |
278 | unsigned long rate, min = ULONG_MAX; |
279 | int src; | |
253e0a7c | 280 | |
222a13c5 TF |
281 | for (src = 0; src < MAX_BUS_CLK; src++) { |
282 | struct clk *clk; | |
283 | ||
284 | clk = ourhost->clk_bus[src]; | |
285 | if (IS_ERR(clk)) | |
286 | continue; | |
287 | ||
288 | rate = clk_round_rate(clk, 0); | |
289 | if (rate < min) | |
290 | min = rate; | |
291 | } | |
292 | ||
293 | return min; | |
253e0a7c JS |
294 | } |
295 | ||
296 | /* sdhci_cmu_set_clock - callback on clock change.*/ | |
297 | static void sdhci_cmu_set_clock(struct sdhci_host *host, unsigned int clock) | |
298 | { | |
299 | struct sdhci_s3c *ourhost = to_s3c(host); | |
2ad0b249 | 300 | struct device *dev = &ourhost->pdev->dev; |
3119936a TA |
301 | unsigned long timeout; |
302 | u16 clk = 0; | |
253e0a7c | 303 | |
1650d0c7 RK |
304 | host->mmc->actual_clock = 0; |
305 | ||
7ef2a5e2 JC |
306 | /* If the clock is going off, set to 0 at clock control register */ |
307 | if (clock == 0) { | |
308 | sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL); | |
253e0a7c | 309 | return; |
7ef2a5e2 | 310 | } |
253e0a7c JS |
311 | |
312 | sdhci_s3c_set_clock(host, clock); | |
313 | ||
314 | clk_set_rate(ourhost->clk_bus[ourhost->cur_clk], clock); | |
315 | ||
3119936a TA |
316 | clk = SDHCI_CLOCK_INT_EN; |
317 | sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); | |
318 | ||
319 | /* Wait max 20 ms */ | |
320 | timeout = 20; | |
321 | while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL)) | |
322 | & SDHCI_CLOCK_INT_STABLE)) { | |
323 | if (timeout == 0) { | |
2ad0b249 JH |
324 | dev_err(dev, "%s: Internal clock never stabilised.\n", |
325 | mmc_hostname(host->mmc)); | |
3119936a TA |
326 | return; |
327 | } | |
328 | timeout--; | |
329 | mdelay(1); | |
330 | } | |
331 | ||
332 | clk |= SDHCI_CLOCK_CARD_EN; | |
333 | sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); | |
253e0a7c JS |
334 | } |
335 | ||
548f07d2 | 336 | /** |
2317f56c | 337 | * sdhci_s3c_set_bus_width - support 8bit buswidth |
548f07d2 JC |
338 | * @host: The SDHCI host being queried |
339 | * @width: MMC_BUS_WIDTH_ macro for the bus width being requested | |
340 | * | |
341 | * We have 8-bit width support but is not a v3 controller. | |
7bc088d3 | 342 | * So we add platform_bus_width() and support 8bit width. |
548f07d2 | 343 | */ |
2317f56c | 344 | static void sdhci_s3c_set_bus_width(struct sdhci_host *host, int width) |
548f07d2 JC |
345 | { |
346 | u8 ctrl; | |
347 | ||
348 | ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); | |
349 | ||
350 | switch (width) { | |
351 | case MMC_BUS_WIDTH_8: | |
352 | ctrl |= SDHCI_CTRL_8BITBUS; | |
353 | ctrl &= ~SDHCI_CTRL_4BITBUS; | |
354 | break; | |
355 | case MMC_BUS_WIDTH_4: | |
356 | ctrl |= SDHCI_CTRL_4BITBUS; | |
357 | ctrl &= ~SDHCI_CTRL_8BITBUS; | |
358 | break; | |
359 | default: | |
49bb1e61 G |
360 | ctrl &= ~SDHCI_CTRL_4BITBUS; |
361 | ctrl &= ~SDHCI_CTRL_8BITBUS; | |
548f07d2 JC |
362 | break; |
363 | } | |
364 | ||
365 | sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); | |
548f07d2 JC |
366 | } |
367 | ||
0d1bb41a BD |
368 | static struct sdhci_ops sdhci_s3c_ops = { |
369 | .get_max_clock = sdhci_s3c_get_max_clk, | |
0d1bb41a | 370 | .set_clock = sdhci_s3c_set_clock, |
ce5f036b | 371 | .get_min_clock = sdhci_s3c_get_min_clock, |
2317f56c | 372 | .set_bus_width = sdhci_s3c_set_bus_width, |
03231f9b | 373 | .reset = sdhci_reset, |
96d7b78c | 374 | .set_uhs_signaling = sdhci_set_uhs_signaling, |
0d1bb41a BD |
375 | }; |
376 | ||
cd1b00eb | 377 | #ifdef CONFIG_OF |
c3be1efd | 378 | static int sdhci_s3c_parse_dt(struct device *dev, |
cd1b00eb TA |
379 | struct sdhci_host *host, struct s3c_sdhci_platdata *pdata) |
380 | { | |
381 | struct device_node *node = dev->of_node; | |
cd1b00eb | 382 | u32 max_width; |
cd1b00eb TA |
383 | |
384 | /* if the bus-width property is not specified, assume width as 1 */ | |
385 | if (of_property_read_u32(node, "bus-width", &max_width)) | |
386 | max_width = 1; | |
387 | pdata->max_width = max_width; | |
388 | ||
cd1b00eb | 389 | /* get the card detection method */ |
ab5023ef | 390 | if (of_get_property(node, "broken-cd", NULL)) { |
cd1b00eb | 391 | pdata->cd_type = S3C_SDHCI_CD_NONE; |
e19499ae | 392 | return 0; |
cd1b00eb TA |
393 | } |
394 | ||
ab5023ef | 395 | if (of_get_property(node, "non-removable", NULL)) { |
cd1b00eb | 396 | pdata->cd_type = S3C_SDHCI_CD_PERMANENT; |
e19499ae | 397 | return 0; |
cd1b00eb TA |
398 | } |
399 | ||
11bc9381 | 400 | if (of_get_named_gpio(node, "cd-gpios", 0)) |
b96efccb | 401 | return 0; |
cd1b00eb | 402 | |
e19499ae TA |
403 | /* assuming internal card detect that will be configured by pinctrl */ |
404 | pdata->cd_type = S3C_SDHCI_CD_INTERNAL; | |
cd1b00eb | 405 | return 0; |
cd1b00eb TA |
406 | } |
407 | #else | |
c3be1efd | 408 | static int sdhci_s3c_parse_dt(struct device *dev, |
cd1b00eb TA |
409 | struct sdhci_host *host, struct s3c_sdhci_platdata *pdata) |
410 | { | |
411 | return -EINVAL; | |
412 | } | |
413 | #endif | |
414 | ||
415 | static const struct of_device_id sdhci_s3c_dt_match[]; | |
416 | ||
3119936a TA |
417 | static inline struct sdhci_s3c_drv_data *sdhci_s3c_get_driver_data( |
418 | struct platform_device *pdev) | |
419 | { | |
cd1b00eb TA |
420 | #ifdef CONFIG_OF |
421 | if (pdev->dev.of_node) { | |
422 | const struct of_device_id *match; | |
423 | match = of_match_node(sdhci_s3c_dt_match, pdev->dev.of_node); | |
424 | return (struct sdhci_s3c_drv_data *)match->data; | |
425 | } | |
426 | #endif | |
3119936a TA |
427 | return (struct sdhci_s3c_drv_data *) |
428 | platform_get_device_id(pdev)->driver_data; | |
429 | } | |
430 | ||
c3be1efd | 431 | static int sdhci_s3c_probe(struct platform_device *pdev) |
0d1bb41a | 432 | { |
1d4dc338 | 433 | struct s3c_sdhci_platdata *pdata; |
3119936a | 434 | struct sdhci_s3c_drv_data *drv_data; |
0d1bb41a BD |
435 | struct device *dev = &pdev->dev; |
436 | struct sdhci_host *host; | |
437 | struct sdhci_s3c *sc; | |
438 | struct resource *res; | |
439 | int ret, irq, ptr, clks; | |
440 | ||
cd1b00eb | 441 | if (!pdev->dev.platform_data && !pdev->dev.of_node) { |
0d1bb41a BD |
442 | dev_err(dev, "no device data specified\n"); |
443 | return -ENOENT; | |
444 | } | |
445 | ||
446 | irq = platform_get_irq(pdev, 0); | |
447 | if (irq < 0) { | |
448 | dev_err(dev, "no irq specified\n"); | |
449 | return irq; | |
450 | } | |
451 | ||
0d1bb41a BD |
452 | host = sdhci_alloc_host(dev, sizeof(struct sdhci_s3c)); |
453 | if (IS_ERR(host)) { | |
454 | dev_err(dev, "sdhci_alloc_host() failed\n"); | |
455 | return PTR_ERR(host); | |
456 | } | |
cd1b00eb | 457 | sc = sdhci_priv(host); |
0d1bb41a | 458 | |
1d4dc338 TA |
459 | pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); |
460 | if (!pdata) { | |
461 | ret = -ENOMEM; | |
b1b8fea9 | 462 | goto err_pdata_io_clk; |
cd1b00eb TA |
463 | } |
464 | ||
465 | if (pdev->dev.of_node) { | |
466 | ret = sdhci_s3c_parse_dt(&pdev->dev, host, pdata); | |
467 | if (ret) | |
b1b8fea9 | 468 | goto err_pdata_io_clk; |
cd1b00eb TA |
469 | } else { |
470 | memcpy(pdata, pdev->dev.platform_data, sizeof(*pdata)); | |
471 | sc->ext_cd_gpio = -1; /* invalid gpio number */ | |
1d4dc338 | 472 | } |
1d4dc338 | 473 | |
3119936a | 474 | drv_data = sdhci_s3c_get_driver_data(pdev); |
0d1bb41a BD |
475 | |
476 | sc->host = host; | |
477 | sc->pdev = pdev; | |
478 | sc->pdata = pdata; | |
3ac147fa | 479 | sc->cur_clk = -1; |
0d1bb41a BD |
480 | |
481 | platform_set_drvdata(pdev, host); | |
482 | ||
3aaf7ba7 | 483 | sc->clk_io = devm_clk_get(dev, "hsmmc"); |
0d1bb41a BD |
484 | if (IS_ERR(sc->clk_io)) { |
485 | dev_err(dev, "failed to get io clock\n"); | |
486 | ret = PTR_ERR(sc->clk_io); | |
b1b8fea9 | 487 | goto err_pdata_io_clk; |
0d1bb41a BD |
488 | } |
489 | ||
490 | /* enable the local io clock and keep it running for the moment. */ | |
0f310a05 | 491 | clk_prepare_enable(sc->clk_io); |
0d1bb41a BD |
492 | |
493 | for (clks = 0, ptr = 0; ptr < MAX_BUS_CLK; ptr++) { | |
4346b6d9 | 494 | char name[14]; |
0d1bb41a | 495 | |
4346b6d9 | 496 | snprintf(name, 14, "mmc_busclk.%d", ptr); |
8f4b78d9 TF |
497 | sc->clk_bus[ptr] = devm_clk_get(dev, name); |
498 | if (IS_ERR(sc->clk_bus[ptr])) | |
0d1bb41a | 499 | continue; |
0d1bb41a BD |
500 | |
501 | clks++; | |
6eb28bdc TF |
502 | sc->clk_rates[ptr] = clk_get_rate(sc->clk_bus[ptr]); |
503 | ||
0d1bb41a | 504 | dev_info(dev, "clock source %d: %s (%ld Hz)\n", |
6eb28bdc | 505 | ptr, name, sc->clk_rates[ptr]); |
0d1bb41a BD |
506 | } |
507 | ||
508 | if (clks == 0) { | |
509 | dev_err(dev, "failed to find any bus clocks\n"); | |
510 | ret = -ENOENT; | |
511 | goto err_no_busclks; | |
512 | } | |
513 | ||
9bda6da7 | 514 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
a3e2cd7f TR |
515 | host->ioaddr = devm_ioremap_resource(&pdev->dev, res); |
516 | if (IS_ERR(host->ioaddr)) { | |
517 | ret = PTR_ERR(host->ioaddr); | |
0d1bb41a BD |
518 | goto err_req_regs; |
519 | } | |
520 | ||
521 | /* Ensure we have minimal gpio selected CMD/CLK/Detect */ | |
522 | if (pdata->cfg_gpio) | |
523 | pdata->cfg_gpio(pdev, pdata->max_width); | |
524 | ||
525 | host->hw_name = "samsung-hsmmc"; | |
526 | host->ops = &sdhci_s3c_ops; | |
527 | host->quirks = 0; | |
285e244f | 528 | host->quirks2 = 0; |
0d1bb41a BD |
529 | host->irq = irq; |
530 | ||
531 | /* Setup quirks for the controller */ | |
b2e75eff | 532 | host->quirks |= SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC; |
a1d56460 | 533 | host->quirks |= SDHCI_QUIRK_NO_HISPD_BIT; |
1771059c | 534 | if (drv_data) { |
3119936a | 535 | host->quirks |= drv_data->sdhci_quirks; |
1771059c RK |
536 | sc->no_divider = drv_data->no_divider; |
537 | } | |
0d1bb41a BD |
538 | |
539 | #ifndef CONFIG_MMC_SDHCI_S3C_DMA | |
540 | ||
541 | /* we currently see overruns on errors, so disable the SDMA | |
542 | * support as well. */ | |
543 | host->quirks |= SDHCI_QUIRK_BROKEN_DMA; | |
544 | ||
545 | #endif /* CONFIG_MMC_SDHCI_S3C_DMA */ | |
546 | ||
547 | /* It seems we do not get an DATA transfer complete on non-busy | |
548 | * transfers, not sure if this is a problem with this specific | |
549 | * SDHCI block, or a missing configuration that needs to be set. */ | |
550 | host->quirks |= SDHCI_QUIRK_NO_BUSY_IRQ; | |
551 | ||
732f0e31 KP |
552 | /* This host supports the Auto CMD12 */ |
553 | host->quirks |= SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12; | |
554 | ||
7199e2b6 JC |
555 | /* Samsung SoCs need BROKEN_ADMA_ZEROLEN_DESC */ |
556 | host->quirks |= SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC; | |
557 | ||
17866e14 MS |
558 | if (pdata->cd_type == S3C_SDHCI_CD_NONE || |
559 | pdata->cd_type == S3C_SDHCI_CD_PERMANENT) | |
560 | host->quirks |= SDHCI_QUIRK_BROKEN_CARD_DETECTION; | |
561 | ||
562 | if (pdata->cd_type == S3C_SDHCI_CD_PERMANENT) | |
563 | host->mmc->caps = MMC_CAP_NONREMOVABLE; | |
564 | ||
0d22c770 TA |
565 | switch (pdata->max_width) { |
566 | case 8: | |
567 | host->mmc->caps |= MMC_CAP_8_BIT_DATA; | |
568 | case 4: | |
569 | host->mmc->caps |= MMC_CAP_4_BIT_DATA; | |
570 | break; | |
571 | } | |
572 | ||
fa1773cc SL |
573 | if (pdata->pm_caps) |
574 | host->mmc->pm_caps |= pdata->pm_caps; | |
575 | ||
0d1bb41a BD |
576 | host->quirks |= (SDHCI_QUIRK_32BIT_DMA_ADDR | |
577 | SDHCI_QUIRK_32BIT_DMA_SIZE); | |
578 | ||
3fe42e07 HL |
579 | /* HSMMC on Samsung SoCs uses SDCLK as timeout clock */ |
580 | host->quirks |= SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK; | |
581 | ||
253e0a7c JS |
582 | /* |
583 | * If controller does not have internal clock divider, | |
584 | * we can use overriding functions instead of default. | |
585 | */ | |
1771059c | 586 | if (sc->no_divider) { |
253e0a7c JS |
587 | sdhci_s3c_ops.set_clock = sdhci_cmu_set_clock; |
588 | sdhci_s3c_ops.get_min_clock = sdhci_cmu_get_min_clock; | |
589 | sdhci_s3c_ops.get_max_clock = sdhci_cmu_get_max_clock; | |
590 | } | |
591 | ||
b3824f2c JS |
592 | /* It supports additional host capabilities if needed */ |
593 | if (pdata->host_caps) | |
594 | host->mmc->caps |= pdata->host_caps; | |
595 | ||
c1c4b66d JC |
596 | if (pdata->host_caps2) |
597 | host->mmc->caps2 |= pdata->host_caps2; | |
598 | ||
9f4e8151 MB |
599 | pm_runtime_enable(&pdev->dev); |
600 | pm_runtime_set_autosuspend_delay(&pdev->dev, 50); | |
601 | pm_runtime_use_autosuspend(&pdev->dev); | |
602 | pm_suspend_ignore_children(&pdev->dev, 1); | |
603 | ||
11bc9381 JC |
604 | mmc_of_parse(host->mmc); |
605 | ||
0d1bb41a BD |
606 | ret = sdhci_add_host(host); |
607 | if (ret) { | |
608 | dev_err(dev, "sdhci_add_host() failed\n"); | |
9f4e8151 MB |
609 | pm_runtime_forbid(&pdev->dev); |
610 | pm_runtime_get_noresume(&pdev->dev); | |
9bda6da7 | 611 | goto err_req_regs; |
0d1bb41a BD |
612 | } |
613 | ||
2abeb5c5 | 614 | #ifdef CONFIG_PM_RUNTIME |
0aa55c23 SJ |
615 | if (pdata->cd_type != S3C_SDHCI_CD_INTERNAL) |
616 | clk_disable_unprepare(sc->clk_io); | |
2abeb5c5 | 617 | #endif |
0d1bb41a BD |
618 | return 0; |
619 | ||
0d1bb41a | 620 | err_req_regs: |
0d1bb41a | 621 | err_no_busclks: |
0f310a05 | 622 | clk_disable_unprepare(sc->clk_io); |
0d1bb41a | 623 | |
b1b8fea9 | 624 | err_pdata_io_clk: |
0d1bb41a BD |
625 | sdhci_free_host(host); |
626 | ||
627 | return ret; | |
628 | } | |
629 | ||
6e0ee714 | 630 | static int sdhci_s3c_remove(struct platform_device *pdev) |
0d1bb41a | 631 | { |
9d51a6b2 MS |
632 | struct sdhci_host *host = platform_get_drvdata(pdev); |
633 | struct sdhci_s3c *sc = sdhci_priv(host); | |
17866e14 MS |
634 | |
635 | if (sc->ext_cd_irq) | |
636 | free_irq(sc->ext_cd_irq, sc); | |
637 | ||
2abeb5c5 | 638 | #ifdef CONFIG_PM_RUNTIME |
11bc9381 | 639 | if (sc->pdata->cd_type != S3C_SDHCI_CD_INTERNAL) |
0aa55c23 | 640 | clk_prepare_enable(sc->clk_io); |
2abeb5c5 | 641 | #endif |
9d51a6b2 MS |
642 | sdhci_remove_host(host, 1); |
643 | ||
387a8cbd | 644 | pm_runtime_dont_use_autosuspend(&pdev->dev); |
9f4e8151 MB |
645 | pm_runtime_disable(&pdev->dev); |
646 | ||
0f310a05 | 647 | clk_disable_unprepare(sc->clk_io); |
9d51a6b2 | 648 | |
9d51a6b2 | 649 | sdhci_free_host(host); |
9d51a6b2 | 650 | |
0d1bb41a BD |
651 | return 0; |
652 | } | |
653 | ||
d5e9c02c | 654 | #ifdef CONFIG_PM_SLEEP |
29495aa0 | 655 | static int sdhci_s3c_suspend(struct device *dev) |
0d1bb41a | 656 | { |
29495aa0 | 657 | struct sdhci_host *host = dev_get_drvdata(dev); |
0d1bb41a | 658 | |
29495aa0 | 659 | return sdhci_suspend_host(host); |
0d1bb41a BD |
660 | } |
661 | ||
29495aa0 | 662 | static int sdhci_s3c_resume(struct device *dev) |
0d1bb41a | 663 | { |
29495aa0 | 664 | struct sdhci_host *host = dev_get_drvdata(dev); |
0d1bb41a | 665 | |
65d13516 | 666 | return sdhci_resume_host(host); |
0d1bb41a | 667 | } |
d5e9c02c | 668 | #endif |
0d1bb41a | 669 | |
9f4e8151 MB |
670 | #ifdef CONFIG_PM_RUNTIME |
671 | static int sdhci_s3c_runtime_suspend(struct device *dev) | |
672 | { | |
673 | struct sdhci_host *host = dev_get_drvdata(dev); | |
2abeb5c5 CK |
674 | struct sdhci_s3c *ourhost = to_s3c(host); |
675 | struct clk *busclk = ourhost->clk_io; | |
676 | int ret; | |
677 | ||
678 | ret = sdhci_runtime_suspend_host(host); | |
9f4e8151 | 679 | |
3ac147fa TF |
680 | if (ourhost->cur_clk >= 0) |
681 | clk_disable_unprepare(ourhost->clk_bus[ourhost->cur_clk]); | |
0f310a05 | 682 | clk_disable_unprepare(busclk); |
2abeb5c5 | 683 | return ret; |
9f4e8151 MB |
684 | } |
685 | ||
686 | static int sdhci_s3c_runtime_resume(struct device *dev) | |
687 | { | |
688 | struct sdhci_host *host = dev_get_drvdata(dev); | |
2abeb5c5 CK |
689 | struct sdhci_s3c *ourhost = to_s3c(host); |
690 | struct clk *busclk = ourhost->clk_io; | |
691 | int ret; | |
9f4e8151 | 692 | |
0f310a05 | 693 | clk_prepare_enable(busclk); |
3ac147fa TF |
694 | if (ourhost->cur_clk >= 0) |
695 | clk_prepare_enable(ourhost->clk_bus[ourhost->cur_clk]); | |
2abeb5c5 CK |
696 | ret = sdhci_runtime_resume_host(host); |
697 | return ret; | |
9f4e8151 MB |
698 | } |
699 | #endif | |
700 | ||
d5e9c02c | 701 | #ifdef CONFIG_PM |
29495aa0 | 702 | static const struct dev_pm_ops sdhci_s3c_pmops = { |
d5e9c02c | 703 | SET_SYSTEM_SLEEP_PM_OPS(sdhci_s3c_suspend, sdhci_s3c_resume) |
9f4e8151 MB |
704 | SET_RUNTIME_PM_OPS(sdhci_s3c_runtime_suspend, sdhci_s3c_runtime_resume, |
705 | NULL) | |
29495aa0 ML |
706 | }; |
707 | ||
708 | #define SDHCI_S3C_PMOPS (&sdhci_s3c_pmops) | |
709 | ||
0d1bb41a | 710 | #else |
29495aa0 | 711 | #define SDHCI_S3C_PMOPS NULL |
0d1bb41a BD |
712 | #endif |
713 | ||
3119936a TA |
714 | #if defined(CONFIG_CPU_EXYNOS4210) || defined(CONFIG_SOC_EXYNOS4212) |
715 | static struct sdhci_s3c_drv_data exynos4_sdhci_drv_data = { | |
1771059c | 716 | .no_divider = true, |
3119936a TA |
717 | }; |
718 | #define EXYNOS4_SDHCI_DRV_DATA ((kernel_ulong_t)&exynos4_sdhci_drv_data) | |
719 | #else | |
720 | #define EXYNOS4_SDHCI_DRV_DATA ((kernel_ulong_t)NULL) | |
721 | #endif | |
722 | ||
723 | static struct platform_device_id sdhci_s3c_driver_ids[] = { | |
724 | { | |
725 | .name = "s3c-sdhci", | |
726 | .driver_data = (kernel_ulong_t)NULL, | |
727 | }, { | |
728 | .name = "exynos4-sdhci", | |
729 | .driver_data = EXYNOS4_SDHCI_DRV_DATA, | |
730 | }, | |
731 | { } | |
732 | }; | |
733 | MODULE_DEVICE_TABLE(platform, sdhci_s3c_driver_ids); | |
734 | ||
cd1b00eb TA |
735 | #ifdef CONFIG_OF |
736 | static const struct of_device_id sdhci_s3c_dt_match[] = { | |
737 | { .compatible = "samsung,s3c6410-sdhci", }, | |
738 | { .compatible = "samsung,exynos4210-sdhci", | |
739 | .data = (void *)EXYNOS4_SDHCI_DRV_DATA }, | |
740 | {}, | |
741 | }; | |
742 | MODULE_DEVICE_TABLE(of, sdhci_s3c_dt_match); | |
743 | #endif | |
744 | ||
0d1bb41a BD |
745 | static struct platform_driver sdhci_s3c_driver = { |
746 | .probe = sdhci_s3c_probe, | |
0433c143 | 747 | .remove = sdhci_s3c_remove, |
3119936a | 748 | .id_table = sdhci_s3c_driver_ids, |
0d1bb41a BD |
749 | .driver = { |
750 | .owner = THIS_MODULE, | |
751 | .name = "s3c-sdhci", | |
cd1b00eb | 752 | .of_match_table = of_match_ptr(sdhci_s3c_dt_match), |
29495aa0 | 753 | .pm = SDHCI_S3C_PMOPS, |
0d1bb41a BD |
754 | }, |
755 | }; | |
756 | ||
d1f81a64 | 757 | module_platform_driver(sdhci_s3c_driver); |
0d1bb41a BD |
758 | |
759 | MODULE_DESCRIPTION("Samsung SDHCI (HSMMC) glue"); | |
760 | MODULE_AUTHOR("Ben Dooks, <ben@simtec.co.uk>"); | |
761 | MODULE_LICENSE("GPL v2"); | |
762 | MODULE_ALIAS("platform:s3c-sdhci"); |