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0d1bb41a BD |
1 | /* linux/drivers/mmc/host/sdhci-s3c.c |
2 | * | |
3 | * Copyright 2008 Openmoko Inc. | |
4 | * Copyright 2008 Simtec Electronics | |
5 | * Ben Dooks <ben@simtec.co.uk> | |
6 | * http://armlinux.simtec.co.uk/ | |
7 | * | |
8 | * SDHCI (HSMMC) support for Samsung SoC | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License version 2 as | |
12 | * published by the Free Software Foundation. | |
13 | */ | |
14 | ||
15 | #include <linux/delay.h> | |
16 | #include <linux/dma-mapping.h> | |
17 | #include <linux/platform_device.h> | |
cc014f3e | 18 | #include <linux/platform_data/mmc-sdhci-s3c.h> |
5a0e3ad6 | 19 | #include <linux/slab.h> |
0d1bb41a BD |
20 | #include <linux/clk.h> |
21 | #include <linux/io.h> | |
17866e14 | 22 | #include <linux/gpio.h> |
55156d24 | 23 | #include <linux/module.h> |
d5e9c02c MB |
24 | #include <linux/of.h> |
25 | #include <linux/of_gpio.h> | |
26 | #include <linux/pm.h> | |
9f4e8151 | 27 | #include <linux/pm_runtime.h> |
0d1bb41a BD |
28 | |
29 | #include <linux/mmc/host.h> | |
30 | ||
cc014f3e | 31 | #include "sdhci-s3c-regs.h" |
0d1bb41a BD |
32 | #include "sdhci.h" |
33 | ||
34 | #define MAX_BUS_CLK (4) | |
35 | ||
36 | /** | |
37 | * struct sdhci_s3c - S3C SDHCI instance | |
38 | * @host: The SDHCI host created | |
39 | * @pdev: The platform device we where created from. | |
40 | * @ioarea: The resource created when we claimed the IO area. | |
41 | * @pdata: The platform data for this controller. | |
42 | * @cur_clk: The index of the current bus clock. | |
43 | * @clk_io: The clock for the internal bus interface. | |
44 | * @clk_bus: The clocks that are available for the SD/MMC bus clock. | |
45 | */ | |
46 | struct sdhci_s3c { | |
47 | struct sdhci_host *host; | |
48 | struct platform_device *pdev; | |
49 | struct resource *ioarea; | |
50 | struct s3c_sdhci_platdata *pdata; | |
3ac147fa | 51 | int cur_clk; |
17866e14 MS |
52 | int ext_cd_irq; |
53 | int ext_cd_gpio; | |
0d1bb41a BD |
54 | |
55 | struct clk *clk_io; | |
56 | struct clk *clk_bus[MAX_BUS_CLK]; | |
6eb28bdc | 57 | unsigned long clk_rates[MAX_BUS_CLK]; |
0d1bb41a BD |
58 | }; |
59 | ||
3119936a TA |
60 | /** |
61 | * struct sdhci_s3c_driver_data - S3C SDHCI platform specific driver data | |
62 | * @sdhci_quirks: sdhci host specific quirks. | |
63 | * | |
64 | * Specifies platform specific configuration of sdhci controller. | |
65 | * Note: A structure for driver specific platform data is used for future | |
66 | * expansion of its usage. | |
67 | */ | |
68 | struct sdhci_s3c_drv_data { | |
69 | unsigned int sdhci_quirks; | |
70 | }; | |
71 | ||
0d1bb41a BD |
72 | static inline struct sdhci_s3c *to_s3c(struct sdhci_host *host) |
73 | { | |
74 | return sdhci_priv(host); | |
75 | } | |
76 | ||
0d1bb41a BD |
77 | /** |
78 | * sdhci_s3c_get_max_clk - callback to get maximum clock frequency. | |
79 | * @host: The SDHCI host instance. | |
80 | * | |
81 | * Callback to return the maximum clock rate acheivable by the controller. | |
82 | */ | |
83 | static unsigned int sdhci_s3c_get_max_clk(struct sdhci_host *host) | |
84 | { | |
85 | struct sdhci_s3c *ourhost = to_s3c(host); | |
222a13c5 TF |
86 | unsigned long rate, max = 0; |
87 | int src; | |
0d1bb41a | 88 | |
222a13c5 TF |
89 | for (src = 0; src < MAX_BUS_CLK; src++) { |
90 | rate = ourhost->clk_rates[src]; | |
0d1bb41a BD |
91 | if (rate > max) |
92 | max = rate; | |
93 | } | |
94 | ||
95 | return max; | |
96 | } | |
97 | ||
0d1bb41a BD |
98 | /** |
99 | * sdhci_s3c_consider_clock - consider one the bus clocks for current setting | |
100 | * @ourhost: Our SDHCI instance. | |
101 | * @src: The source clock index. | |
102 | * @wanted: The clock frequency wanted. | |
103 | */ | |
104 | static unsigned int sdhci_s3c_consider_clock(struct sdhci_s3c *ourhost, | |
105 | unsigned int src, | |
106 | unsigned int wanted) | |
107 | { | |
108 | unsigned long rate; | |
109 | struct clk *clksrc = ourhost->clk_bus[src]; | |
8880a4a5 | 110 | int shift; |
0d1bb41a | 111 | |
8f4b78d9 | 112 | if (IS_ERR(clksrc)) |
0d1bb41a BD |
113 | return UINT_MAX; |
114 | ||
253e0a7c | 115 | /* |
3119936a TA |
116 | * If controller uses a non-standard clock division, find the best clock |
117 | * speed possible with selected clock source and skip the division. | |
253e0a7c | 118 | */ |
3119936a | 119 | if (ourhost->host->quirks & SDHCI_QUIRK_NONSTANDARD_CLOCK) { |
253e0a7c JS |
120 | rate = clk_round_rate(clksrc, wanted); |
121 | return wanted - rate; | |
122 | } | |
123 | ||
6eb28bdc | 124 | rate = ourhost->clk_rates[src]; |
0d1bb41a | 125 | |
22003000 | 126 | for (shift = 0; shift <= 8; ++shift) { |
8880a4a5 | 127 | if ((rate >> shift) <= wanted) |
0d1bb41a BD |
128 | break; |
129 | } | |
22003000 TF |
130 | |
131 | if (shift > 8) { | |
132 | dev_dbg(&ourhost->pdev->dev, | |
133 | "clk %d: rate %ld, min rate %lu > wanted %u\n", | |
134 | src, rate, rate / 256, wanted); | |
135 | return UINT_MAX; | |
136 | } | |
0d1bb41a BD |
137 | |
138 | dev_dbg(&ourhost->pdev->dev, "clk %d: rate %ld, want %d, got %ld\n", | |
8880a4a5 | 139 | src, rate, wanted, rate >> shift); |
0d1bb41a | 140 | |
8880a4a5 | 141 | return wanted - (rate >> shift); |
0d1bb41a BD |
142 | } |
143 | ||
144 | /** | |
145 | * sdhci_s3c_set_clock - callback on clock change | |
146 | * @host: The SDHCI host being changed | |
147 | * @clock: The clock rate being requested. | |
148 | * | |
149 | * When the card's clock is going to be changed, look at the new frequency | |
150 | * and find the best clock source to go with it. | |
151 | */ | |
152 | static void sdhci_s3c_set_clock(struct sdhci_host *host, unsigned int clock) | |
153 | { | |
154 | struct sdhci_s3c *ourhost = to_s3c(host); | |
155 | unsigned int best = UINT_MAX; | |
156 | unsigned int delta; | |
157 | int best_src = 0; | |
158 | int src; | |
159 | u32 ctrl; | |
160 | ||
161 | /* don't bother if the clock is going off. */ | |
162 | if (clock == 0) | |
163 | return; | |
164 | ||
165 | for (src = 0; src < MAX_BUS_CLK; src++) { | |
166 | delta = sdhci_s3c_consider_clock(ourhost, src, clock); | |
167 | if (delta < best) { | |
168 | best = delta; | |
169 | best_src = src; | |
170 | } | |
171 | } | |
172 | ||
173 | dev_dbg(&ourhost->pdev->dev, | |
174 | "selected source %d, clock %d, delta %d\n", | |
175 | best_src, clock, best); | |
176 | ||
177 | /* select the new clock source */ | |
0d1bb41a BD |
178 | if (ourhost->cur_clk != best_src) { |
179 | struct clk *clk = ourhost->clk_bus[best_src]; | |
180 | ||
0f310a05 | 181 | clk_prepare_enable(clk); |
3ac147fa TF |
182 | if (ourhost->cur_clk >= 0) |
183 | clk_disable_unprepare( | |
184 | ourhost->clk_bus[ourhost->cur_clk]); | |
0d1bb41a BD |
185 | |
186 | ourhost->cur_clk = best_src; | |
6eb28bdc | 187 | host->max_clk = ourhost->clk_rates[best_src]; |
0d1bb41a BD |
188 | } |
189 | ||
3ac147fa TF |
190 | /* turn clock off to card before changing clock source */ |
191 | writew(0, host->ioaddr + SDHCI_CLOCK_CONTROL); | |
192 | ||
193 | ctrl = readl(host->ioaddr + S3C_SDHCI_CONTROL2); | |
194 | ctrl &= ~S3C_SDHCI_CTRL2_SELBASECLK_MASK; | |
195 | ctrl |= best_src << S3C_SDHCI_CTRL2_SELBASECLK_SHIFT; | |
196 | writel(ctrl, host->ioaddr + S3C_SDHCI_CONTROL2); | |
197 | ||
6fe47179 TA |
198 | /* reprogram default hardware configuration */ |
199 | writel(S3C64XX_SDHCI_CONTROL4_DRIVE_9mA, | |
200 | host->ioaddr + S3C64XX_SDHCI_CONTROL4); | |
201 | ||
202 | ctrl = readl(host->ioaddr + S3C_SDHCI_CONTROL2); | |
203 | ctrl |= (S3C64XX_SDHCI_CTRL2_ENSTAASYNCCLR | | |
204 | S3C64XX_SDHCI_CTRL2_ENCMDCNFMSK | | |
205 | S3C_SDHCI_CTRL2_ENFBCLKRX | | |
206 | S3C_SDHCI_CTRL2_DFCNT_NONE | | |
207 | S3C_SDHCI_CTRL2_ENCLKOUTHOLD); | |
208 | writel(ctrl, host->ioaddr + S3C_SDHCI_CONTROL2); | |
209 | ||
210 | /* reconfigure the controller for new clock rate */ | |
211 | ctrl = (S3C_SDHCI_CTRL3_FCSEL1 | S3C_SDHCI_CTRL3_FCSEL0); | |
212 | if (clock < 25 * 1000000) | |
213 | ctrl |= (S3C_SDHCI_CTRL3_FCSEL3 | S3C_SDHCI_CTRL3_FCSEL2); | |
214 | writel(ctrl, host->ioaddr + S3C_SDHCI_CONTROL3); | |
0d1bb41a BD |
215 | } |
216 | ||
ce5f036b MS |
217 | /** |
218 | * sdhci_s3c_get_min_clock - callback to get minimal supported clock value | |
219 | * @host: The SDHCI host being queried | |
220 | * | |
221 | * To init mmc host properly a minimal clock value is needed. For high system | |
222 | * bus clock's values the standard formula gives values out of allowed range. | |
223 | * The clock still can be set to lower values, if clock source other then | |
224 | * system bus is selected. | |
225 | */ | |
226 | static unsigned int sdhci_s3c_get_min_clock(struct sdhci_host *host) | |
227 | { | |
228 | struct sdhci_s3c *ourhost = to_s3c(host); | |
222a13c5 | 229 | unsigned long rate, min = ULONG_MAX; |
ce5f036b MS |
230 | int src; |
231 | ||
232 | for (src = 0; src < MAX_BUS_CLK; src++) { | |
222a13c5 TF |
233 | rate = ourhost->clk_rates[src] / 256; |
234 | if (!rate) | |
ce5f036b | 235 | continue; |
222a13c5 TF |
236 | if (rate < min) |
237 | min = rate; | |
ce5f036b | 238 | } |
222a13c5 | 239 | |
ce5f036b MS |
240 | return min; |
241 | } | |
242 | ||
253e0a7c JS |
243 | /* sdhci_cmu_get_max_clk - callback to get maximum clock frequency.*/ |
244 | static unsigned int sdhci_cmu_get_max_clock(struct sdhci_host *host) | |
245 | { | |
246 | struct sdhci_s3c *ourhost = to_s3c(host); | |
222a13c5 TF |
247 | unsigned long rate, max = 0; |
248 | int src; | |
249 | ||
250 | for (src = 0; src < MAX_BUS_CLK; src++) { | |
251 | struct clk *clk; | |
252 | ||
253 | clk = ourhost->clk_bus[src]; | |
254 | if (IS_ERR(clk)) | |
255 | continue; | |
256 | ||
257 | rate = clk_round_rate(clk, ULONG_MAX); | |
258 | if (rate > max) | |
259 | max = rate; | |
260 | } | |
253e0a7c | 261 | |
222a13c5 | 262 | return max; |
253e0a7c JS |
263 | } |
264 | ||
265 | /* sdhci_cmu_get_min_clock - callback to get minimal supported clock value. */ | |
266 | static unsigned int sdhci_cmu_get_min_clock(struct sdhci_host *host) | |
267 | { | |
268 | struct sdhci_s3c *ourhost = to_s3c(host); | |
222a13c5 TF |
269 | unsigned long rate, min = ULONG_MAX; |
270 | int src; | |
253e0a7c | 271 | |
222a13c5 TF |
272 | for (src = 0; src < MAX_BUS_CLK; src++) { |
273 | struct clk *clk; | |
274 | ||
275 | clk = ourhost->clk_bus[src]; | |
276 | if (IS_ERR(clk)) | |
277 | continue; | |
278 | ||
279 | rate = clk_round_rate(clk, 0); | |
280 | if (rate < min) | |
281 | min = rate; | |
282 | } | |
283 | ||
284 | return min; | |
253e0a7c JS |
285 | } |
286 | ||
287 | /* sdhci_cmu_set_clock - callback on clock change.*/ | |
288 | static void sdhci_cmu_set_clock(struct sdhci_host *host, unsigned int clock) | |
289 | { | |
290 | struct sdhci_s3c *ourhost = to_s3c(host); | |
2ad0b249 | 291 | struct device *dev = &ourhost->pdev->dev; |
3119936a TA |
292 | unsigned long timeout; |
293 | u16 clk = 0; | |
253e0a7c | 294 | |
7ef2a5e2 JC |
295 | /* If the clock is going off, set to 0 at clock control register */ |
296 | if (clock == 0) { | |
297 | sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL); | |
253e0a7c | 298 | return; |
7ef2a5e2 | 299 | } |
253e0a7c JS |
300 | |
301 | sdhci_s3c_set_clock(host, clock); | |
302 | ||
303 | clk_set_rate(ourhost->clk_bus[ourhost->cur_clk], clock); | |
304 | ||
3119936a TA |
305 | clk = SDHCI_CLOCK_INT_EN; |
306 | sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); | |
307 | ||
308 | /* Wait max 20 ms */ | |
309 | timeout = 20; | |
310 | while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL)) | |
311 | & SDHCI_CLOCK_INT_STABLE)) { | |
312 | if (timeout == 0) { | |
2ad0b249 JH |
313 | dev_err(dev, "%s: Internal clock never stabilised.\n", |
314 | mmc_hostname(host->mmc)); | |
3119936a TA |
315 | return; |
316 | } | |
317 | timeout--; | |
318 | mdelay(1); | |
319 | } | |
320 | ||
321 | clk |= SDHCI_CLOCK_CARD_EN; | |
322 | sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); | |
253e0a7c JS |
323 | } |
324 | ||
548f07d2 | 325 | /** |
2317f56c | 326 | * sdhci_s3c_set_bus_width - support 8bit buswidth |
548f07d2 JC |
327 | * @host: The SDHCI host being queried |
328 | * @width: MMC_BUS_WIDTH_ macro for the bus width being requested | |
329 | * | |
330 | * We have 8-bit width support but is not a v3 controller. | |
7bc088d3 | 331 | * So we add platform_bus_width() and support 8bit width. |
548f07d2 | 332 | */ |
2317f56c | 333 | static void sdhci_s3c_set_bus_width(struct sdhci_host *host, int width) |
548f07d2 JC |
334 | { |
335 | u8 ctrl; | |
336 | ||
337 | ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); | |
338 | ||
339 | switch (width) { | |
340 | case MMC_BUS_WIDTH_8: | |
341 | ctrl |= SDHCI_CTRL_8BITBUS; | |
342 | ctrl &= ~SDHCI_CTRL_4BITBUS; | |
343 | break; | |
344 | case MMC_BUS_WIDTH_4: | |
345 | ctrl |= SDHCI_CTRL_4BITBUS; | |
346 | ctrl &= ~SDHCI_CTRL_8BITBUS; | |
347 | break; | |
348 | default: | |
49bb1e61 G |
349 | ctrl &= ~SDHCI_CTRL_4BITBUS; |
350 | ctrl &= ~SDHCI_CTRL_8BITBUS; | |
548f07d2 JC |
351 | break; |
352 | } | |
353 | ||
354 | sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); | |
548f07d2 JC |
355 | } |
356 | ||
0d1bb41a BD |
357 | static struct sdhci_ops sdhci_s3c_ops = { |
358 | .get_max_clock = sdhci_s3c_get_max_clk, | |
0d1bb41a | 359 | .set_clock = sdhci_s3c_set_clock, |
ce5f036b | 360 | .get_min_clock = sdhci_s3c_get_min_clock, |
2317f56c | 361 | .set_bus_width = sdhci_s3c_set_bus_width, |
03231f9b | 362 | .reset = sdhci_reset, |
0d1bb41a BD |
363 | }; |
364 | ||
17866e14 MS |
365 | static void sdhci_s3c_notify_change(struct platform_device *dev, int state) |
366 | { | |
367 | struct sdhci_host *host = platform_get_drvdata(dev); | |
4577f77b | 368 | #ifdef CONFIG_PM_RUNTIME |
fe007c02 | 369 | struct sdhci_s3c *sc = sdhci_priv(host); |
4577f77b | 370 | #endif |
06fe577f MS |
371 | unsigned long flags; |
372 | ||
17866e14 | 373 | if (host) { |
06fe577f | 374 | spin_lock_irqsave(&host->lock, flags); |
17866e14 MS |
375 | if (state) { |
376 | dev_dbg(&dev->dev, "card inserted.\n"); | |
fe007c02 HS |
377 | #ifdef CONFIG_PM_RUNTIME |
378 | clk_prepare_enable(sc->clk_io); | |
379 | #endif | |
17866e14 MS |
380 | host->flags &= ~SDHCI_DEVICE_DEAD; |
381 | host->quirks |= SDHCI_QUIRK_BROKEN_CARD_DETECTION; | |
382 | } else { | |
383 | dev_dbg(&dev->dev, "card removed.\n"); | |
384 | host->flags |= SDHCI_DEVICE_DEAD; | |
385 | host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION; | |
fe007c02 HS |
386 | #ifdef CONFIG_PM_RUNTIME |
387 | clk_disable_unprepare(sc->clk_io); | |
388 | #endif | |
17866e14 | 389 | } |
f522886e | 390 | tasklet_schedule(&host->card_tasklet); |
06fe577f | 391 | spin_unlock_irqrestore(&host->lock, flags); |
17866e14 MS |
392 | } |
393 | } | |
394 | ||
395 | static irqreturn_t sdhci_s3c_gpio_card_detect_thread(int irq, void *dev_id) | |
396 | { | |
397 | struct sdhci_s3c *sc = dev_id; | |
398 | int status = gpio_get_value(sc->ext_cd_gpio); | |
399 | if (sc->pdata->ext_cd_gpio_invert) | |
400 | status = !status; | |
401 | sdhci_s3c_notify_change(sc->pdev, status); | |
402 | return IRQ_HANDLED; | |
403 | } | |
404 | ||
405 | static void sdhci_s3c_setup_card_detect_gpio(struct sdhci_s3c *sc) | |
406 | { | |
407 | struct s3c_sdhci_platdata *pdata = sc->pdata; | |
408 | struct device *dev = &sc->pdev->dev; | |
409 | ||
b1b8fea9 | 410 | if (devm_gpio_request(dev, pdata->ext_cd_gpio, "SDHCI EXT CD") == 0) { |
17866e14 MS |
411 | sc->ext_cd_gpio = pdata->ext_cd_gpio; |
412 | sc->ext_cd_irq = gpio_to_irq(pdata->ext_cd_gpio); | |
413 | if (sc->ext_cd_irq && | |
414 | request_threaded_irq(sc->ext_cd_irq, NULL, | |
415 | sdhci_s3c_gpio_card_detect_thread, | |
2ad0b249 JH |
416 | IRQF_TRIGGER_RISING | |
417 | IRQF_TRIGGER_FALLING | | |
418 | IRQF_ONESHOT, | |
17866e14 MS |
419 | dev_name(dev), sc) == 0) { |
420 | int status = gpio_get_value(sc->ext_cd_gpio); | |
421 | if (pdata->ext_cd_gpio_invert) | |
422 | status = !status; | |
423 | sdhci_s3c_notify_change(sc->pdev, status); | |
424 | } else { | |
425 | dev_warn(dev, "cannot request irq for card detect\n"); | |
426 | sc->ext_cd_irq = 0; | |
427 | } | |
428 | } else { | |
429 | dev_err(dev, "cannot request gpio for card detect\n"); | |
430 | } | |
431 | } | |
432 | ||
cd1b00eb | 433 | #ifdef CONFIG_OF |
c3be1efd | 434 | static int sdhci_s3c_parse_dt(struct device *dev, |
cd1b00eb TA |
435 | struct sdhci_host *host, struct s3c_sdhci_platdata *pdata) |
436 | { | |
437 | struct device_node *node = dev->of_node; | |
438 | struct sdhci_s3c *ourhost = to_s3c(host); | |
439 | u32 max_width; | |
e19499ae | 440 | int gpio; |
cd1b00eb TA |
441 | |
442 | /* if the bus-width property is not specified, assume width as 1 */ | |
443 | if (of_property_read_u32(node, "bus-width", &max_width)) | |
444 | max_width = 1; | |
445 | pdata->max_width = max_width; | |
446 | ||
cd1b00eb | 447 | /* get the card detection method */ |
ab5023ef | 448 | if (of_get_property(node, "broken-cd", NULL)) { |
cd1b00eb | 449 | pdata->cd_type = S3C_SDHCI_CD_NONE; |
e19499ae | 450 | return 0; |
cd1b00eb TA |
451 | } |
452 | ||
ab5023ef | 453 | if (of_get_property(node, "non-removable", NULL)) { |
cd1b00eb | 454 | pdata->cd_type = S3C_SDHCI_CD_PERMANENT; |
e19499ae | 455 | return 0; |
cd1b00eb TA |
456 | } |
457 | ||
458 | gpio = of_get_named_gpio(node, "cd-gpios", 0); | |
459 | if (gpio_is_valid(gpio)) { | |
460 | pdata->cd_type = S3C_SDHCI_CD_GPIO; | |
cd1b00eb TA |
461 | pdata->ext_cd_gpio = gpio; |
462 | ourhost->ext_cd_gpio = -1; | |
463 | if (of_get_property(node, "cd-inverted", NULL)) | |
464 | pdata->ext_cd_gpio_invert = 1; | |
b96efccb | 465 | return 0; |
e19499ae TA |
466 | } else if (gpio != -ENOENT) { |
467 | dev_err(dev, "invalid card detect gpio specified\n"); | |
468 | return -EINVAL; | |
cd1b00eb TA |
469 | } |
470 | ||
e19499ae TA |
471 | /* assuming internal card detect that will be configured by pinctrl */ |
472 | pdata->cd_type = S3C_SDHCI_CD_INTERNAL; | |
cd1b00eb | 473 | return 0; |
cd1b00eb TA |
474 | } |
475 | #else | |
c3be1efd | 476 | static int sdhci_s3c_parse_dt(struct device *dev, |
cd1b00eb TA |
477 | struct sdhci_host *host, struct s3c_sdhci_platdata *pdata) |
478 | { | |
479 | return -EINVAL; | |
480 | } | |
481 | #endif | |
482 | ||
483 | static const struct of_device_id sdhci_s3c_dt_match[]; | |
484 | ||
3119936a TA |
485 | static inline struct sdhci_s3c_drv_data *sdhci_s3c_get_driver_data( |
486 | struct platform_device *pdev) | |
487 | { | |
cd1b00eb TA |
488 | #ifdef CONFIG_OF |
489 | if (pdev->dev.of_node) { | |
490 | const struct of_device_id *match; | |
491 | match = of_match_node(sdhci_s3c_dt_match, pdev->dev.of_node); | |
492 | return (struct sdhci_s3c_drv_data *)match->data; | |
493 | } | |
494 | #endif | |
3119936a TA |
495 | return (struct sdhci_s3c_drv_data *) |
496 | platform_get_device_id(pdev)->driver_data; | |
497 | } | |
498 | ||
c3be1efd | 499 | static int sdhci_s3c_probe(struct platform_device *pdev) |
0d1bb41a | 500 | { |
1d4dc338 | 501 | struct s3c_sdhci_platdata *pdata; |
3119936a | 502 | struct sdhci_s3c_drv_data *drv_data; |
0d1bb41a BD |
503 | struct device *dev = &pdev->dev; |
504 | struct sdhci_host *host; | |
505 | struct sdhci_s3c *sc; | |
506 | struct resource *res; | |
507 | int ret, irq, ptr, clks; | |
508 | ||
cd1b00eb | 509 | if (!pdev->dev.platform_data && !pdev->dev.of_node) { |
0d1bb41a BD |
510 | dev_err(dev, "no device data specified\n"); |
511 | return -ENOENT; | |
512 | } | |
513 | ||
514 | irq = platform_get_irq(pdev, 0); | |
515 | if (irq < 0) { | |
516 | dev_err(dev, "no irq specified\n"); | |
517 | return irq; | |
518 | } | |
519 | ||
0d1bb41a BD |
520 | host = sdhci_alloc_host(dev, sizeof(struct sdhci_s3c)); |
521 | if (IS_ERR(host)) { | |
522 | dev_err(dev, "sdhci_alloc_host() failed\n"); | |
523 | return PTR_ERR(host); | |
524 | } | |
cd1b00eb | 525 | sc = sdhci_priv(host); |
0d1bb41a | 526 | |
1d4dc338 TA |
527 | pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); |
528 | if (!pdata) { | |
529 | ret = -ENOMEM; | |
b1b8fea9 | 530 | goto err_pdata_io_clk; |
cd1b00eb TA |
531 | } |
532 | ||
533 | if (pdev->dev.of_node) { | |
534 | ret = sdhci_s3c_parse_dt(&pdev->dev, host, pdata); | |
535 | if (ret) | |
b1b8fea9 | 536 | goto err_pdata_io_clk; |
cd1b00eb TA |
537 | } else { |
538 | memcpy(pdata, pdev->dev.platform_data, sizeof(*pdata)); | |
539 | sc->ext_cd_gpio = -1; /* invalid gpio number */ | |
1d4dc338 | 540 | } |
1d4dc338 | 541 | |
3119936a | 542 | drv_data = sdhci_s3c_get_driver_data(pdev); |
0d1bb41a BD |
543 | |
544 | sc->host = host; | |
545 | sc->pdev = pdev; | |
546 | sc->pdata = pdata; | |
3ac147fa | 547 | sc->cur_clk = -1; |
0d1bb41a BD |
548 | |
549 | platform_set_drvdata(pdev, host); | |
550 | ||
3aaf7ba7 | 551 | sc->clk_io = devm_clk_get(dev, "hsmmc"); |
0d1bb41a BD |
552 | if (IS_ERR(sc->clk_io)) { |
553 | dev_err(dev, "failed to get io clock\n"); | |
554 | ret = PTR_ERR(sc->clk_io); | |
b1b8fea9 | 555 | goto err_pdata_io_clk; |
0d1bb41a BD |
556 | } |
557 | ||
558 | /* enable the local io clock and keep it running for the moment. */ | |
0f310a05 | 559 | clk_prepare_enable(sc->clk_io); |
0d1bb41a BD |
560 | |
561 | for (clks = 0, ptr = 0; ptr < MAX_BUS_CLK; ptr++) { | |
4346b6d9 | 562 | char name[14]; |
0d1bb41a | 563 | |
4346b6d9 | 564 | snprintf(name, 14, "mmc_busclk.%d", ptr); |
8f4b78d9 TF |
565 | sc->clk_bus[ptr] = devm_clk_get(dev, name); |
566 | if (IS_ERR(sc->clk_bus[ptr])) | |
0d1bb41a | 567 | continue; |
0d1bb41a BD |
568 | |
569 | clks++; | |
6eb28bdc TF |
570 | sc->clk_rates[ptr] = clk_get_rate(sc->clk_bus[ptr]); |
571 | ||
0d1bb41a | 572 | dev_info(dev, "clock source %d: %s (%ld Hz)\n", |
6eb28bdc | 573 | ptr, name, sc->clk_rates[ptr]); |
0d1bb41a BD |
574 | } |
575 | ||
576 | if (clks == 0) { | |
577 | dev_err(dev, "failed to find any bus clocks\n"); | |
578 | ret = -ENOENT; | |
579 | goto err_no_busclks; | |
580 | } | |
581 | ||
9bda6da7 | 582 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
a3e2cd7f TR |
583 | host->ioaddr = devm_ioremap_resource(&pdev->dev, res); |
584 | if (IS_ERR(host->ioaddr)) { | |
585 | ret = PTR_ERR(host->ioaddr); | |
0d1bb41a BD |
586 | goto err_req_regs; |
587 | } | |
588 | ||
589 | /* Ensure we have minimal gpio selected CMD/CLK/Detect */ | |
590 | if (pdata->cfg_gpio) | |
591 | pdata->cfg_gpio(pdev, pdata->max_width); | |
592 | ||
593 | host->hw_name = "samsung-hsmmc"; | |
594 | host->ops = &sdhci_s3c_ops; | |
595 | host->quirks = 0; | |
285e244f | 596 | host->quirks2 = 0; |
0d1bb41a BD |
597 | host->irq = irq; |
598 | ||
599 | /* Setup quirks for the controller */ | |
b2e75eff | 600 | host->quirks |= SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC; |
a1d56460 | 601 | host->quirks |= SDHCI_QUIRK_NO_HISPD_BIT; |
3119936a TA |
602 | if (drv_data) |
603 | host->quirks |= drv_data->sdhci_quirks; | |
0d1bb41a BD |
604 | |
605 | #ifndef CONFIG_MMC_SDHCI_S3C_DMA | |
606 | ||
607 | /* we currently see overruns on errors, so disable the SDMA | |
608 | * support as well. */ | |
609 | host->quirks |= SDHCI_QUIRK_BROKEN_DMA; | |
610 | ||
611 | #endif /* CONFIG_MMC_SDHCI_S3C_DMA */ | |
612 | ||
613 | /* It seems we do not get an DATA transfer complete on non-busy | |
614 | * transfers, not sure if this is a problem with this specific | |
615 | * SDHCI block, or a missing configuration that needs to be set. */ | |
616 | host->quirks |= SDHCI_QUIRK_NO_BUSY_IRQ; | |
617 | ||
732f0e31 KP |
618 | /* This host supports the Auto CMD12 */ |
619 | host->quirks |= SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12; | |
620 | ||
7199e2b6 JC |
621 | /* Samsung SoCs need BROKEN_ADMA_ZEROLEN_DESC */ |
622 | host->quirks |= SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC; | |
623 | ||
17866e14 MS |
624 | if (pdata->cd_type == S3C_SDHCI_CD_NONE || |
625 | pdata->cd_type == S3C_SDHCI_CD_PERMANENT) | |
626 | host->quirks |= SDHCI_QUIRK_BROKEN_CARD_DETECTION; | |
627 | ||
628 | if (pdata->cd_type == S3C_SDHCI_CD_PERMANENT) | |
629 | host->mmc->caps = MMC_CAP_NONREMOVABLE; | |
630 | ||
0d22c770 TA |
631 | switch (pdata->max_width) { |
632 | case 8: | |
633 | host->mmc->caps |= MMC_CAP_8_BIT_DATA; | |
634 | case 4: | |
635 | host->mmc->caps |= MMC_CAP_4_BIT_DATA; | |
636 | break; | |
637 | } | |
638 | ||
fa1773cc SL |
639 | if (pdata->pm_caps) |
640 | host->mmc->pm_caps |= pdata->pm_caps; | |
641 | ||
0d1bb41a BD |
642 | host->quirks |= (SDHCI_QUIRK_32BIT_DMA_ADDR | |
643 | SDHCI_QUIRK_32BIT_DMA_SIZE); | |
644 | ||
3fe42e07 HL |
645 | /* HSMMC on Samsung SoCs uses SDCLK as timeout clock */ |
646 | host->quirks |= SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK; | |
647 | ||
253e0a7c JS |
648 | /* |
649 | * If controller does not have internal clock divider, | |
650 | * we can use overriding functions instead of default. | |
651 | */ | |
3119936a | 652 | if (host->quirks & SDHCI_QUIRK_NONSTANDARD_CLOCK) { |
253e0a7c JS |
653 | sdhci_s3c_ops.set_clock = sdhci_cmu_set_clock; |
654 | sdhci_s3c_ops.get_min_clock = sdhci_cmu_get_min_clock; | |
655 | sdhci_s3c_ops.get_max_clock = sdhci_cmu_get_max_clock; | |
656 | } | |
657 | ||
b3824f2c JS |
658 | /* It supports additional host capabilities if needed */ |
659 | if (pdata->host_caps) | |
660 | host->mmc->caps |= pdata->host_caps; | |
661 | ||
c1c4b66d JC |
662 | if (pdata->host_caps2) |
663 | host->mmc->caps2 |= pdata->host_caps2; | |
664 | ||
9f4e8151 MB |
665 | pm_runtime_enable(&pdev->dev); |
666 | pm_runtime_set_autosuspend_delay(&pdev->dev, 50); | |
667 | pm_runtime_use_autosuspend(&pdev->dev); | |
668 | pm_suspend_ignore_children(&pdev->dev, 1); | |
669 | ||
0d1bb41a BD |
670 | ret = sdhci_add_host(host); |
671 | if (ret) { | |
672 | dev_err(dev, "sdhci_add_host() failed\n"); | |
9f4e8151 MB |
673 | pm_runtime_forbid(&pdev->dev); |
674 | pm_runtime_get_noresume(&pdev->dev); | |
9bda6da7 | 675 | goto err_req_regs; |
0d1bb41a BD |
676 | } |
677 | ||
17866e14 MS |
678 | /* The following two methods of card detection might call |
679 | sdhci_s3c_notify_change() immediately, so they can be called | |
680 | only after sdhci_add_host(). Setup errors are ignored. */ | |
681 | if (pdata->cd_type == S3C_SDHCI_CD_EXTERNAL && pdata->ext_cd_init) | |
682 | pdata->ext_cd_init(&sdhci_s3c_notify_change); | |
683 | if (pdata->cd_type == S3C_SDHCI_CD_GPIO && | |
684 | gpio_is_valid(pdata->ext_cd_gpio)) | |
685 | sdhci_s3c_setup_card_detect_gpio(sc); | |
686 | ||
2abeb5c5 | 687 | #ifdef CONFIG_PM_RUNTIME |
0aa55c23 SJ |
688 | if (pdata->cd_type != S3C_SDHCI_CD_INTERNAL) |
689 | clk_disable_unprepare(sc->clk_io); | |
2abeb5c5 | 690 | #endif |
0d1bb41a BD |
691 | return 0; |
692 | ||
0d1bb41a | 693 | err_req_regs: |
0d1bb41a | 694 | err_no_busclks: |
0f310a05 | 695 | clk_disable_unprepare(sc->clk_io); |
0d1bb41a | 696 | |
b1b8fea9 | 697 | err_pdata_io_clk: |
0d1bb41a BD |
698 | sdhci_free_host(host); |
699 | ||
700 | return ret; | |
701 | } | |
702 | ||
6e0ee714 | 703 | static int sdhci_s3c_remove(struct platform_device *pdev) |
0d1bb41a | 704 | { |
9d51a6b2 MS |
705 | struct sdhci_host *host = platform_get_drvdata(pdev); |
706 | struct sdhci_s3c *sc = sdhci_priv(host); | |
cd1b00eb | 707 | struct s3c_sdhci_platdata *pdata = sc->pdata; |
9d51a6b2 | 708 | |
17866e14 MS |
709 | if (pdata->cd_type == S3C_SDHCI_CD_EXTERNAL && pdata->ext_cd_cleanup) |
710 | pdata->ext_cd_cleanup(&sdhci_s3c_notify_change); | |
711 | ||
712 | if (sc->ext_cd_irq) | |
713 | free_irq(sc->ext_cd_irq, sc); | |
714 | ||
2abeb5c5 | 715 | #ifdef CONFIG_PM_RUNTIME |
0aa55c23 SJ |
716 | if (pdata->cd_type != S3C_SDHCI_CD_INTERNAL) |
717 | clk_prepare_enable(sc->clk_io); | |
2abeb5c5 | 718 | #endif |
9d51a6b2 MS |
719 | sdhci_remove_host(host, 1); |
720 | ||
387a8cbd | 721 | pm_runtime_dont_use_autosuspend(&pdev->dev); |
9f4e8151 MB |
722 | pm_runtime_disable(&pdev->dev); |
723 | ||
0f310a05 | 724 | clk_disable_unprepare(sc->clk_io); |
9d51a6b2 | 725 | |
9d51a6b2 | 726 | sdhci_free_host(host); |
9d51a6b2 | 727 | |
0d1bb41a BD |
728 | return 0; |
729 | } | |
730 | ||
d5e9c02c | 731 | #ifdef CONFIG_PM_SLEEP |
29495aa0 | 732 | static int sdhci_s3c_suspend(struct device *dev) |
0d1bb41a | 733 | { |
29495aa0 | 734 | struct sdhci_host *host = dev_get_drvdata(dev); |
0d1bb41a | 735 | |
29495aa0 | 736 | return sdhci_suspend_host(host); |
0d1bb41a BD |
737 | } |
738 | ||
29495aa0 | 739 | static int sdhci_s3c_resume(struct device *dev) |
0d1bb41a | 740 | { |
29495aa0 | 741 | struct sdhci_host *host = dev_get_drvdata(dev); |
0d1bb41a | 742 | |
65d13516 | 743 | return sdhci_resume_host(host); |
0d1bb41a | 744 | } |
d5e9c02c | 745 | #endif |
0d1bb41a | 746 | |
9f4e8151 MB |
747 | #ifdef CONFIG_PM_RUNTIME |
748 | static int sdhci_s3c_runtime_suspend(struct device *dev) | |
749 | { | |
750 | struct sdhci_host *host = dev_get_drvdata(dev); | |
2abeb5c5 CK |
751 | struct sdhci_s3c *ourhost = to_s3c(host); |
752 | struct clk *busclk = ourhost->clk_io; | |
753 | int ret; | |
754 | ||
755 | ret = sdhci_runtime_suspend_host(host); | |
9f4e8151 | 756 | |
3ac147fa TF |
757 | if (ourhost->cur_clk >= 0) |
758 | clk_disable_unprepare(ourhost->clk_bus[ourhost->cur_clk]); | |
0f310a05 | 759 | clk_disable_unprepare(busclk); |
2abeb5c5 | 760 | return ret; |
9f4e8151 MB |
761 | } |
762 | ||
763 | static int sdhci_s3c_runtime_resume(struct device *dev) | |
764 | { | |
765 | struct sdhci_host *host = dev_get_drvdata(dev); | |
2abeb5c5 CK |
766 | struct sdhci_s3c *ourhost = to_s3c(host); |
767 | struct clk *busclk = ourhost->clk_io; | |
768 | int ret; | |
9f4e8151 | 769 | |
0f310a05 | 770 | clk_prepare_enable(busclk); |
3ac147fa TF |
771 | if (ourhost->cur_clk >= 0) |
772 | clk_prepare_enable(ourhost->clk_bus[ourhost->cur_clk]); | |
2abeb5c5 CK |
773 | ret = sdhci_runtime_resume_host(host); |
774 | return ret; | |
9f4e8151 MB |
775 | } |
776 | #endif | |
777 | ||
d5e9c02c | 778 | #ifdef CONFIG_PM |
29495aa0 | 779 | static const struct dev_pm_ops sdhci_s3c_pmops = { |
d5e9c02c | 780 | SET_SYSTEM_SLEEP_PM_OPS(sdhci_s3c_suspend, sdhci_s3c_resume) |
9f4e8151 MB |
781 | SET_RUNTIME_PM_OPS(sdhci_s3c_runtime_suspend, sdhci_s3c_runtime_resume, |
782 | NULL) | |
29495aa0 ML |
783 | }; |
784 | ||
785 | #define SDHCI_S3C_PMOPS (&sdhci_s3c_pmops) | |
786 | ||
0d1bb41a | 787 | #else |
29495aa0 | 788 | #define SDHCI_S3C_PMOPS NULL |
0d1bb41a BD |
789 | #endif |
790 | ||
3119936a TA |
791 | #if defined(CONFIG_CPU_EXYNOS4210) || defined(CONFIG_SOC_EXYNOS4212) |
792 | static struct sdhci_s3c_drv_data exynos4_sdhci_drv_data = { | |
793 | .sdhci_quirks = SDHCI_QUIRK_NONSTANDARD_CLOCK, | |
794 | }; | |
795 | #define EXYNOS4_SDHCI_DRV_DATA ((kernel_ulong_t)&exynos4_sdhci_drv_data) | |
796 | #else | |
797 | #define EXYNOS4_SDHCI_DRV_DATA ((kernel_ulong_t)NULL) | |
798 | #endif | |
799 | ||
800 | static struct platform_device_id sdhci_s3c_driver_ids[] = { | |
801 | { | |
802 | .name = "s3c-sdhci", | |
803 | .driver_data = (kernel_ulong_t)NULL, | |
804 | }, { | |
805 | .name = "exynos4-sdhci", | |
806 | .driver_data = EXYNOS4_SDHCI_DRV_DATA, | |
807 | }, | |
808 | { } | |
809 | }; | |
810 | MODULE_DEVICE_TABLE(platform, sdhci_s3c_driver_ids); | |
811 | ||
cd1b00eb TA |
812 | #ifdef CONFIG_OF |
813 | static const struct of_device_id sdhci_s3c_dt_match[] = { | |
814 | { .compatible = "samsung,s3c6410-sdhci", }, | |
815 | { .compatible = "samsung,exynos4210-sdhci", | |
816 | .data = (void *)EXYNOS4_SDHCI_DRV_DATA }, | |
817 | {}, | |
818 | }; | |
819 | MODULE_DEVICE_TABLE(of, sdhci_s3c_dt_match); | |
820 | #endif | |
821 | ||
0d1bb41a BD |
822 | static struct platform_driver sdhci_s3c_driver = { |
823 | .probe = sdhci_s3c_probe, | |
0433c143 | 824 | .remove = sdhci_s3c_remove, |
3119936a | 825 | .id_table = sdhci_s3c_driver_ids, |
0d1bb41a BD |
826 | .driver = { |
827 | .owner = THIS_MODULE, | |
828 | .name = "s3c-sdhci", | |
cd1b00eb | 829 | .of_match_table = of_match_ptr(sdhci_s3c_dt_match), |
29495aa0 | 830 | .pm = SDHCI_S3C_PMOPS, |
0d1bb41a BD |
831 | }, |
832 | }; | |
833 | ||
d1f81a64 | 834 | module_platform_driver(sdhci_s3c_driver); |
0d1bb41a BD |
835 | |
836 | MODULE_DESCRIPTION("Samsung SDHCI (HSMMC) glue"); | |
837 | MODULE_AUTHOR("Ben Dooks, <ben@simtec.co.uk>"); | |
838 | MODULE_LICENSE("GPL v2"); | |
839 | MODULE_ALIAS("platform:s3c-sdhci"); |