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0d1bb41a BD |
1 | /* linux/drivers/mmc/host/sdhci-s3c.c |
2 | * | |
3 | * Copyright 2008 Openmoko Inc. | |
4 | * Copyright 2008 Simtec Electronics | |
5 | * Ben Dooks <ben@simtec.co.uk> | |
6 | * http://armlinux.simtec.co.uk/ | |
7 | * | |
8 | * SDHCI (HSMMC) support for Samsung SoC | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License version 2 as | |
12 | * published by the Free Software Foundation. | |
13 | */ | |
14 | ||
15 | #include <linux/delay.h> | |
16 | #include <linux/dma-mapping.h> | |
17 | #include <linux/platform_device.h> | |
5a0e3ad6 | 18 | #include <linux/slab.h> |
0d1bb41a BD |
19 | #include <linux/clk.h> |
20 | #include <linux/io.h> | |
17866e14 | 21 | #include <linux/gpio.h> |
55156d24 | 22 | #include <linux/module.h> |
d5e9c02c MB |
23 | #include <linux/of.h> |
24 | #include <linux/of_gpio.h> | |
25 | #include <linux/pm.h> | |
9f4e8151 | 26 | #include <linux/pm_runtime.h> |
0d1bb41a BD |
27 | |
28 | #include <linux/mmc/host.h> | |
29 | ||
30 | #include <plat/sdhci.h> | |
31 | #include <plat/regs-sdhci.h> | |
32 | ||
33 | #include "sdhci.h" | |
34 | ||
35 | #define MAX_BUS_CLK (4) | |
36 | ||
cd1b00eb TA |
37 | /* Number of gpio's used is max data bus width + command and clock lines */ |
38 | #define NUM_GPIOS(x) (x + 2) | |
39 | ||
0d1bb41a BD |
40 | /** |
41 | * struct sdhci_s3c - S3C SDHCI instance | |
42 | * @host: The SDHCI host created | |
43 | * @pdev: The platform device we where created from. | |
44 | * @ioarea: The resource created when we claimed the IO area. | |
45 | * @pdata: The platform data for this controller. | |
46 | * @cur_clk: The index of the current bus clock. | |
cd1b00eb | 47 | * @gpios: List of gpio numbers parsed from device tree. |
0d1bb41a BD |
48 | * @clk_io: The clock for the internal bus interface. |
49 | * @clk_bus: The clocks that are available for the SD/MMC bus clock. | |
50 | */ | |
51 | struct sdhci_s3c { | |
52 | struct sdhci_host *host; | |
53 | struct platform_device *pdev; | |
54 | struct resource *ioarea; | |
55 | struct s3c_sdhci_platdata *pdata; | |
56 | unsigned int cur_clk; | |
17866e14 MS |
57 | int ext_cd_irq; |
58 | int ext_cd_gpio; | |
cd1b00eb | 59 | int *gpios; |
0d1bb41a BD |
60 | |
61 | struct clk *clk_io; | |
62 | struct clk *clk_bus[MAX_BUS_CLK]; | |
63 | }; | |
64 | ||
3119936a TA |
65 | /** |
66 | * struct sdhci_s3c_driver_data - S3C SDHCI platform specific driver data | |
67 | * @sdhci_quirks: sdhci host specific quirks. | |
68 | * | |
69 | * Specifies platform specific configuration of sdhci controller. | |
70 | * Note: A structure for driver specific platform data is used for future | |
71 | * expansion of its usage. | |
72 | */ | |
73 | struct sdhci_s3c_drv_data { | |
74 | unsigned int sdhci_quirks; | |
75 | }; | |
76 | ||
0d1bb41a BD |
77 | static inline struct sdhci_s3c *to_s3c(struct sdhci_host *host) |
78 | { | |
79 | return sdhci_priv(host); | |
80 | } | |
81 | ||
82 | /** | |
83 | * get_curclk - convert ctrl2 register to clock source number | |
84 | * @ctrl2: Control2 register value. | |
85 | */ | |
86 | static u32 get_curclk(u32 ctrl2) | |
87 | { | |
88 | ctrl2 &= S3C_SDHCI_CTRL2_SELBASECLK_MASK; | |
89 | ctrl2 >>= S3C_SDHCI_CTRL2_SELBASECLK_SHIFT; | |
90 | ||
91 | return ctrl2; | |
92 | } | |
93 | ||
94 | static void sdhci_s3c_check_sclk(struct sdhci_host *host) | |
95 | { | |
96 | struct sdhci_s3c *ourhost = to_s3c(host); | |
97 | u32 tmp = readl(host->ioaddr + S3C_SDHCI_CONTROL2); | |
98 | ||
99 | if (get_curclk(tmp) != ourhost->cur_clk) { | |
100 | dev_dbg(&ourhost->pdev->dev, "restored ctrl2 clock setting\n"); | |
101 | ||
102 | tmp &= ~S3C_SDHCI_CTRL2_SELBASECLK_MASK; | |
103 | tmp |= ourhost->cur_clk << S3C_SDHCI_CTRL2_SELBASECLK_SHIFT; | |
7003fecb | 104 | writel(tmp, host->ioaddr + S3C_SDHCI_CONTROL2); |
0d1bb41a BD |
105 | } |
106 | } | |
107 | ||
108 | /** | |
109 | * sdhci_s3c_get_max_clk - callback to get maximum clock frequency. | |
110 | * @host: The SDHCI host instance. | |
111 | * | |
112 | * Callback to return the maximum clock rate acheivable by the controller. | |
113 | */ | |
114 | static unsigned int sdhci_s3c_get_max_clk(struct sdhci_host *host) | |
115 | { | |
116 | struct sdhci_s3c *ourhost = to_s3c(host); | |
117 | struct clk *busclk; | |
118 | unsigned int rate, max; | |
119 | int clk; | |
120 | ||
121 | /* note, a reset will reset the clock source */ | |
122 | ||
123 | sdhci_s3c_check_sclk(host); | |
124 | ||
125 | for (max = 0, clk = 0; clk < MAX_BUS_CLK; clk++) { | |
126 | busclk = ourhost->clk_bus[clk]; | |
127 | if (!busclk) | |
128 | continue; | |
129 | ||
130 | rate = clk_get_rate(busclk); | |
131 | if (rate > max) | |
132 | max = rate; | |
133 | } | |
134 | ||
135 | return max; | |
136 | } | |
137 | ||
0d1bb41a BD |
138 | /** |
139 | * sdhci_s3c_consider_clock - consider one the bus clocks for current setting | |
140 | * @ourhost: Our SDHCI instance. | |
141 | * @src: The source clock index. | |
142 | * @wanted: The clock frequency wanted. | |
143 | */ | |
144 | static unsigned int sdhci_s3c_consider_clock(struct sdhci_s3c *ourhost, | |
145 | unsigned int src, | |
146 | unsigned int wanted) | |
147 | { | |
148 | unsigned long rate; | |
149 | struct clk *clksrc = ourhost->clk_bus[src]; | |
150 | int div; | |
151 | ||
152 | if (!clksrc) | |
153 | return UINT_MAX; | |
154 | ||
253e0a7c | 155 | /* |
3119936a TA |
156 | * If controller uses a non-standard clock division, find the best clock |
157 | * speed possible with selected clock source and skip the division. | |
253e0a7c | 158 | */ |
3119936a | 159 | if (ourhost->host->quirks & SDHCI_QUIRK_NONSTANDARD_CLOCK) { |
253e0a7c JS |
160 | rate = clk_round_rate(clksrc, wanted); |
161 | return wanted - rate; | |
162 | } | |
163 | ||
0d1bb41a BD |
164 | rate = clk_get_rate(clksrc); |
165 | ||
166 | for (div = 1; div < 256; div *= 2) { | |
167 | if ((rate / div) <= wanted) | |
168 | break; | |
169 | } | |
170 | ||
171 | dev_dbg(&ourhost->pdev->dev, "clk %d: rate %ld, want %d, got %ld\n", | |
172 | src, rate, wanted, rate / div); | |
173 | ||
2ad0b249 | 174 | return wanted - (rate / div); |
0d1bb41a BD |
175 | } |
176 | ||
177 | /** | |
178 | * sdhci_s3c_set_clock - callback on clock change | |
179 | * @host: The SDHCI host being changed | |
180 | * @clock: The clock rate being requested. | |
181 | * | |
182 | * When the card's clock is going to be changed, look at the new frequency | |
183 | * and find the best clock source to go with it. | |
184 | */ | |
185 | static void sdhci_s3c_set_clock(struct sdhci_host *host, unsigned int clock) | |
186 | { | |
187 | struct sdhci_s3c *ourhost = to_s3c(host); | |
188 | unsigned int best = UINT_MAX; | |
189 | unsigned int delta; | |
190 | int best_src = 0; | |
191 | int src; | |
192 | u32 ctrl; | |
193 | ||
194 | /* don't bother if the clock is going off. */ | |
195 | if (clock == 0) | |
196 | return; | |
197 | ||
198 | for (src = 0; src < MAX_BUS_CLK; src++) { | |
199 | delta = sdhci_s3c_consider_clock(ourhost, src, clock); | |
200 | if (delta < best) { | |
201 | best = delta; | |
202 | best_src = src; | |
203 | } | |
204 | } | |
205 | ||
206 | dev_dbg(&ourhost->pdev->dev, | |
207 | "selected source %d, clock %d, delta %d\n", | |
208 | best_src, clock, best); | |
209 | ||
210 | /* select the new clock source */ | |
0d1bb41a BD |
211 | if (ourhost->cur_clk != best_src) { |
212 | struct clk *clk = ourhost->clk_bus[best_src]; | |
213 | ||
e684c468 CK |
214 | clk_enable(clk); |
215 | clk_disable(ourhost->clk_bus[ourhost->cur_clk]); | |
216 | ||
0d1bb41a BD |
217 | /* turn clock off to card before changing clock source */ |
218 | writew(0, host->ioaddr + SDHCI_CLOCK_CONTROL); | |
219 | ||
220 | ourhost->cur_clk = best_src; | |
221 | host->max_clk = clk_get_rate(clk); | |
0d1bb41a BD |
222 | |
223 | ctrl = readl(host->ioaddr + S3C_SDHCI_CONTROL2); | |
224 | ctrl &= ~S3C_SDHCI_CTRL2_SELBASECLK_MASK; | |
225 | ctrl |= best_src << S3C_SDHCI_CTRL2_SELBASECLK_SHIFT; | |
226 | writel(ctrl, host->ioaddr + S3C_SDHCI_CONTROL2); | |
227 | } | |
228 | ||
6fe47179 TA |
229 | /* reprogram default hardware configuration */ |
230 | writel(S3C64XX_SDHCI_CONTROL4_DRIVE_9mA, | |
231 | host->ioaddr + S3C64XX_SDHCI_CONTROL4); | |
232 | ||
233 | ctrl = readl(host->ioaddr + S3C_SDHCI_CONTROL2); | |
234 | ctrl |= (S3C64XX_SDHCI_CTRL2_ENSTAASYNCCLR | | |
235 | S3C64XX_SDHCI_CTRL2_ENCMDCNFMSK | | |
236 | S3C_SDHCI_CTRL2_ENFBCLKRX | | |
237 | S3C_SDHCI_CTRL2_DFCNT_NONE | | |
238 | S3C_SDHCI_CTRL2_ENCLKOUTHOLD); | |
239 | writel(ctrl, host->ioaddr + S3C_SDHCI_CONTROL2); | |
240 | ||
241 | /* reconfigure the controller for new clock rate */ | |
242 | ctrl = (S3C_SDHCI_CTRL3_FCSEL1 | S3C_SDHCI_CTRL3_FCSEL0); | |
243 | if (clock < 25 * 1000000) | |
244 | ctrl |= (S3C_SDHCI_CTRL3_FCSEL3 | S3C_SDHCI_CTRL3_FCSEL2); | |
245 | writel(ctrl, host->ioaddr + S3C_SDHCI_CONTROL3); | |
0d1bb41a BD |
246 | } |
247 | ||
ce5f036b MS |
248 | /** |
249 | * sdhci_s3c_get_min_clock - callback to get minimal supported clock value | |
250 | * @host: The SDHCI host being queried | |
251 | * | |
252 | * To init mmc host properly a minimal clock value is needed. For high system | |
253 | * bus clock's values the standard formula gives values out of allowed range. | |
254 | * The clock still can be set to lower values, if clock source other then | |
255 | * system bus is selected. | |
256 | */ | |
257 | static unsigned int sdhci_s3c_get_min_clock(struct sdhci_host *host) | |
258 | { | |
259 | struct sdhci_s3c *ourhost = to_s3c(host); | |
260 | unsigned int delta, min = UINT_MAX; | |
261 | int src; | |
262 | ||
263 | for (src = 0; src < MAX_BUS_CLK; src++) { | |
264 | delta = sdhci_s3c_consider_clock(ourhost, src, 0); | |
265 | if (delta == UINT_MAX) | |
266 | continue; | |
267 | /* delta is a negative value in this case */ | |
268 | if (-delta < min) | |
269 | min = -delta; | |
270 | } | |
271 | return min; | |
272 | } | |
273 | ||
253e0a7c JS |
274 | /* sdhci_cmu_get_max_clk - callback to get maximum clock frequency.*/ |
275 | static unsigned int sdhci_cmu_get_max_clock(struct sdhci_host *host) | |
276 | { | |
277 | struct sdhci_s3c *ourhost = to_s3c(host); | |
278 | ||
279 | return clk_round_rate(ourhost->clk_bus[ourhost->cur_clk], UINT_MAX); | |
280 | } | |
281 | ||
282 | /* sdhci_cmu_get_min_clock - callback to get minimal supported clock value. */ | |
283 | static unsigned int sdhci_cmu_get_min_clock(struct sdhci_host *host) | |
284 | { | |
285 | struct sdhci_s3c *ourhost = to_s3c(host); | |
286 | ||
287 | /* | |
288 | * initial clock can be in the frequency range of | |
289 | * 100KHz-400KHz, so we set it as max value. | |
290 | */ | |
291 | return clk_round_rate(ourhost->clk_bus[ourhost->cur_clk], 400000); | |
292 | } | |
293 | ||
294 | /* sdhci_cmu_set_clock - callback on clock change.*/ | |
295 | static void sdhci_cmu_set_clock(struct sdhci_host *host, unsigned int clock) | |
296 | { | |
297 | struct sdhci_s3c *ourhost = to_s3c(host); | |
2ad0b249 | 298 | struct device *dev = &ourhost->pdev->dev; |
3119936a TA |
299 | unsigned long timeout; |
300 | u16 clk = 0; | |
253e0a7c JS |
301 | |
302 | /* don't bother if the clock is going off */ | |
303 | if (clock == 0) | |
304 | return; | |
305 | ||
306 | sdhci_s3c_set_clock(host, clock); | |
307 | ||
308 | clk_set_rate(ourhost->clk_bus[ourhost->cur_clk], clock); | |
309 | ||
310 | host->clock = clock; | |
3119936a TA |
311 | |
312 | clk = SDHCI_CLOCK_INT_EN; | |
313 | sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); | |
314 | ||
315 | /* Wait max 20 ms */ | |
316 | timeout = 20; | |
317 | while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL)) | |
318 | & SDHCI_CLOCK_INT_STABLE)) { | |
319 | if (timeout == 0) { | |
2ad0b249 JH |
320 | dev_err(dev, "%s: Internal clock never stabilised.\n", |
321 | mmc_hostname(host->mmc)); | |
3119936a TA |
322 | return; |
323 | } | |
324 | timeout--; | |
325 | mdelay(1); | |
326 | } | |
327 | ||
328 | clk |= SDHCI_CLOCK_CARD_EN; | |
329 | sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); | |
253e0a7c JS |
330 | } |
331 | ||
548f07d2 JC |
332 | /** |
333 | * sdhci_s3c_platform_8bit_width - support 8bit buswidth | |
334 | * @host: The SDHCI host being queried | |
335 | * @width: MMC_BUS_WIDTH_ macro for the bus width being requested | |
336 | * | |
337 | * We have 8-bit width support but is not a v3 controller. | |
338 | * So we add platform_8bit_width() and support 8bit width. | |
339 | */ | |
340 | static int sdhci_s3c_platform_8bit_width(struct sdhci_host *host, int width) | |
341 | { | |
342 | u8 ctrl; | |
343 | ||
344 | ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); | |
345 | ||
346 | switch (width) { | |
347 | case MMC_BUS_WIDTH_8: | |
348 | ctrl |= SDHCI_CTRL_8BITBUS; | |
349 | ctrl &= ~SDHCI_CTRL_4BITBUS; | |
350 | break; | |
351 | case MMC_BUS_WIDTH_4: | |
352 | ctrl |= SDHCI_CTRL_4BITBUS; | |
353 | ctrl &= ~SDHCI_CTRL_8BITBUS; | |
354 | break; | |
355 | default: | |
49bb1e61 G |
356 | ctrl &= ~SDHCI_CTRL_4BITBUS; |
357 | ctrl &= ~SDHCI_CTRL_8BITBUS; | |
548f07d2 JC |
358 | break; |
359 | } | |
360 | ||
361 | sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); | |
362 | ||
363 | return 0; | |
364 | } | |
365 | ||
0d1bb41a BD |
366 | static struct sdhci_ops sdhci_s3c_ops = { |
367 | .get_max_clock = sdhci_s3c_get_max_clk, | |
0d1bb41a | 368 | .set_clock = sdhci_s3c_set_clock, |
ce5f036b | 369 | .get_min_clock = sdhci_s3c_get_min_clock, |
548f07d2 | 370 | .platform_8bit_width = sdhci_s3c_platform_8bit_width, |
0d1bb41a BD |
371 | }; |
372 | ||
17866e14 MS |
373 | static void sdhci_s3c_notify_change(struct platform_device *dev, int state) |
374 | { | |
375 | struct sdhci_host *host = platform_get_drvdata(dev); | |
06fe577f MS |
376 | unsigned long flags; |
377 | ||
17866e14 | 378 | if (host) { |
06fe577f | 379 | spin_lock_irqsave(&host->lock, flags); |
17866e14 MS |
380 | if (state) { |
381 | dev_dbg(&dev->dev, "card inserted.\n"); | |
382 | host->flags &= ~SDHCI_DEVICE_DEAD; | |
383 | host->quirks |= SDHCI_QUIRK_BROKEN_CARD_DETECTION; | |
384 | } else { | |
385 | dev_dbg(&dev->dev, "card removed.\n"); | |
386 | host->flags |= SDHCI_DEVICE_DEAD; | |
387 | host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION; | |
388 | } | |
f522886e | 389 | tasklet_schedule(&host->card_tasklet); |
06fe577f | 390 | spin_unlock_irqrestore(&host->lock, flags); |
17866e14 MS |
391 | } |
392 | } | |
393 | ||
394 | static irqreturn_t sdhci_s3c_gpio_card_detect_thread(int irq, void *dev_id) | |
395 | { | |
396 | struct sdhci_s3c *sc = dev_id; | |
397 | int status = gpio_get_value(sc->ext_cd_gpio); | |
398 | if (sc->pdata->ext_cd_gpio_invert) | |
399 | status = !status; | |
400 | sdhci_s3c_notify_change(sc->pdev, status); | |
401 | return IRQ_HANDLED; | |
402 | } | |
403 | ||
404 | static void sdhci_s3c_setup_card_detect_gpio(struct sdhci_s3c *sc) | |
405 | { | |
406 | struct s3c_sdhci_platdata *pdata = sc->pdata; | |
407 | struct device *dev = &sc->pdev->dev; | |
408 | ||
409 | if (gpio_request(pdata->ext_cd_gpio, "SDHCI EXT CD") == 0) { | |
410 | sc->ext_cd_gpio = pdata->ext_cd_gpio; | |
411 | sc->ext_cd_irq = gpio_to_irq(pdata->ext_cd_gpio); | |
412 | if (sc->ext_cd_irq && | |
413 | request_threaded_irq(sc->ext_cd_irq, NULL, | |
414 | sdhci_s3c_gpio_card_detect_thread, | |
2ad0b249 JH |
415 | IRQF_TRIGGER_RISING | |
416 | IRQF_TRIGGER_FALLING | | |
417 | IRQF_ONESHOT, | |
17866e14 MS |
418 | dev_name(dev), sc) == 0) { |
419 | int status = gpio_get_value(sc->ext_cd_gpio); | |
420 | if (pdata->ext_cd_gpio_invert) | |
421 | status = !status; | |
422 | sdhci_s3c_notify_change(sc->pdev, status); | |
423 | } else { | |
424 | dev_warn(dev, "cannot request irq for card detect\n"); | |
425 | sc->ext_cd_irq = 0; | |
426 | } | |
427 | } else { | |
428 | dev_err(dev, "cannot request gpio for card detect\n"); | |
429 | } | |
430 | } | |
431 | ||
cd1b00eb TA |
432 | #ifdef CONFIG_OF |
433 | static int __devinit sdhci_s3c_parse_dt(struct device *dev, | |
434 | struct sdhci_host *host, struct s3c_sdhci_platdata *pdata) | |
435 | { | |
436 | struct device_node *node = dev->of_node; | |
437 | struct sdhci_s3c *ourhost = to_s3c(host); | |
438 | u32 max_width; | |
439 | int gpio, cnt, ret; | |
440 | ||
441 | /* if the bus-width property is not specified, assume width as 1 */ | |
442 | if (of_property_read_u32(node, "bus-width", &max_width)) | |
443 | max_width = 1; | |
444 | pdata->max_width = max_width; | |
445 | ||
446 | ourhost->gpios = devm_kzalloc(dev, NUM_GPIOS(pdata->max_width) * | |
447 | sizeof(int), GFP_KERNEL); | |
448 | if (!ourhost->gpios) | |
449 | return -ENOMEM; | |
450 | ||
451 | /* get the card detection method */ | |
452 | if (of_get_property(node, "broken-cd", 0)) { | |
453 | pdata->cd_type = S3C_SDHCI_CD_NONE; | |
454 | goto setup_bus; | |
455 | } | |
456 | ||
457 | if (of_get_property(node, "non-removable", 0)) { | |
458 | pdata->cd_type = S3C_SDHCI_CD_PERMANENT; | |
459 | goto setup_bus; | |
460 | } | |
461 | ||
462 | gpio = of_get_named_gpio(node, "cd-gpios", 0); | |
463 | if (gpio_is_valid(gpio)) { | |
464 | pdata->cd_type = S3C_SDHCI_CD_GPIO; | |
465 | goto found_cd; | |
466 | } else if (gpio != -ENOENT) { | |
467 | dev_err(dev, "invalid card detect gpio specified\n"); | |
468 | return -EINVAL; | |
469 | } | |
470 | ||
471 | gpio = of_get_named_gpio(node, "samsung,cd-pinmux-gpio", 0); | |
472 | if (gpio_is_valid(gpio)) { | |
473 | pdata->cd_type = S3C_SDHCI_CD_INTERNAL; | |
474 | goto found_cd; | |
475 | } else if (gpio != -ENOENT) { | |
476 | dev_err(dev, "invalid card detect gpio specified\n"); | |
477 | return -EINVAL; | |
478 | } | |
479 | ||
480 | dev_info(dev, "assuming no card detect line available\n"); | |
481 | pdata->cd_type = S3C_SDHCI_CD_NONE; | |
482 | ||
483 | found_cd: | |
484 | if (pdata->cd_type == S3C_SDHCI_CD_GPIO) { | |
485 | pdata->ext_cd_gpio = gpio; | |
486 | ourhost->ext_cd_gpio = -1; | |
487 | if (of_get_property(node, "cd-inverted", NULL)) | |
488 | pdata->ext_cd_gpio_invert = 1; | |
489 | } else if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) { | |
490 | ret = gpio_request(gpio, "sdhci-cd"); | |
491 | if (ret) { | |
492 | dev_err(dev, "card detect gpio request failed\n"); | |
493 | return -EINVAL; | |
494 | } | |
495 | ourhost->ext_cd_gpio = gpio; | |
496 | } | |
497 | ||
498 | setup_bus: | |
499 | /* get the gpios for command, clock and data lines */ | |
500 | for (cnt = 0; cnt < NUM_GPIOS(pdata->max_width); cnt++) { | |
501 | gpio = of_get_gpio(node, cnt); | |
502 | if (!gpio_is_valid(gpio)) { | |
503 | dev_err(dev, "invalid gpio[%d]\n", cnt); | |
504 | goto err_free_dt_cd_gpio; | |
505 | } | |
506 | ourhost->gpios[cnt] = gpio; | |
507 | } | |
508 | ||
509 | for (cnt = 0; cnt < NUM_GPIOS(pdata->max_width); cnt++) { | |
510 | ret = gpio_request(ourhost->gpios[cnt], "sdhci-gpio"); | |
511 | if (ret) { | |
512 | dev_err(dev, "gpio[%d] request failed\n", cnt); | |
513 | goto err_free_dt_gpios; | |
514 | } | |
515 | } | |
516 | ||
517 | return 0; | |
518 | ||
519 | err_free_dt_gpios: | |
520 | while (--cnt >= 0) | |
521 | gpio_free(ourhost->gpios[cnt]); | |
522 | err_free_dt_cd_gpio: | |
523 | if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) | |
524 | gpio_free(ourhost->ext_cd_gpio); | |
525 | return -EINVAL; | |
526 | } | |
527 | #else | |
528 | static int __devinit sdhci_s3c_parse_dt(struct device *dev, | |
529 | struct sdhci_host *host, struct s3c_sdhci_platdata *pdata) | |
530 | { | |
531 | return -EINVAL; | |
532 | } | |
533 | #endif | |
534 | ||
535 | static const struct of_device_id sdhci_s3c_dt_match[]; | |
536 | ||
3119936a TA |
537 | static inline struct sdhci_s3c_drv_data *sdhci_s3c_get_driver_data( |
538 | struct platform_device *pdev) | |
539 | { | |
cd1b00eb TA |
540 | #ifdef CONFIG_OF |
541 | if (pdev->dev.of_node) { | |
542 | const struct of_device_id *match; | |
543 | match = of_match_node(sdhci_s3c_dt_match, pdev->dev.of_node); | |
544 | return (struct sdhci_s3c_drv_data *)match->data; | |
545 | } | |
546 | #endif | |
3119936a TA |
547 | return (struct sdhci_s3c_drv_data *) |
548 | platform_get_device_id(pdev)->driver_data; | |
549 | } | |
550 | ||
0d1bb41a BD |
551 | static int __devinit sdhci_s3c_probe(struct platform_device *pdev) |
552 | { | |
1d4dc338 | 553 | struct s3c_sdhci_platdata *pdata; |
3119936a | 554 | struct sdhci_s3c_drv_data *drv_data; |
0d1bb41a BD |
555 | struct device *dev = &pdev->dev; |
556 | struct sdhci_host *host; | |
557 | struct sdhci_s3c *sc; | |
558 | struct resource *res; | |
559 | int ret, irq, ptr, clks; | |
560 | ||
cd1b00eb | 561 | if (!pdev->dev.platform_data && !pdev->dev.of_node) { |
0d1bb41a BD |
562 | dev_err(dev, "no device data specified\n"); |
563 | return -ENOENT; | |
564 | } | |
565 | ||
566 | irq = platform_get_irq(pdev, 0); | |
567 | if (irq < 0) { | |
568 | dev_err(dev, "no irq specified\n"); | |
569 | return irq; | |
570 | } | |
571 | ||
0d1bb41a BD |
572 | host = sdhci_alloc_host(dev, sizeof(struct sdhci_s3c)); |
573 | if (IS_ERR(host)) { | |
574 | dev_err(dev, "sdhci_alloc_host() failed\n"); | |
575 | return PTR_ERR(host); | |
576 | } | |
cd1b00eb | 577 | sc = sdhci_priv(host); |
0d1bb41a | 578 | |
1d4dc338 TA |
579 | pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); |
580 | if (!pdata) { | |
581 | ret = -ENOMEM; | |
cd1b00eb TA |
582 | goto err_pdata; |
583 | } | |
584 | ||
585 | if (pdev->dev.of_node) { | |
586 | ret = sdhci_s3c_parse_dt(&pdev->dev, host, pdata); | |
587 | if (ret) | |
588 | goto err_pdata; | |
589 | } else { | |
590 | memcpy(pdata, pdev->dev.platform_data, sizeof(*pdata)); | |
591 | sc->ext_cd_gpio = -1; /* invalid gpio number */ | |
1d4dc338 | 592 | } |
1d4dc338 | 593 | |
3119936a | 594 | drv_data = sdhci_s3c_get_driver_data(pdev); |
0d1bb41a BD |
595 | |
596 | sc->host = host; | |
597 | sc->pdev = pdev; | |
598 | sc->pdata = pdata; | |
599 | ||
600 | platform_set_drvdata(pdev, host); | |
601 | ||
602 | sc->clk_io = clk_get(dev, "hsmmc"); | |
603 | if (IS_ERR(sc->clk_io)) { | |
604 | dev_err(dev, "failed to get io clock\n"); | |
605 | ret = PTR_ERR(sc->clk_io); | |
606 | goto err_io_clk; | |
607 | } | |
608 | ||
609 | /* enable the local io clock and keep it running for the moment. */ | |
610 | clk_enable(sc->clk_io); | |
611 | ||
612 | for (clks = 0, ptr = 0; ptr < MAX_BUS_CLK; ptr++) { | |
613 | struct clk *clk; | |
4346b6d9 | 614 | char name[14]; |
0d1bb41a | 615 | |
4346b6d9 | 616 | snprintf(name, 14, "mmc_busclk.%d", ptr); |
0d1bb41a | 617 | clk = clk_get(dev, name); |
2ad0b249 | 618 | if (IS_ERR(clk)) |
0d1bb41a | 619 | continue; |
0d1bb41a BD |
620 | |
621 | clks++; | |
622 | sc->clk_bus[ptr] = clk; | |
253e0a7c JS |
623 | |
624 | /* | |
625 | * save current clock index to know which clock bus | |
626 | * is used later in overriding functions. | |
627 | */ | |
628 | sc->cur_clk = ptr; | |
629 | ||
0d1bb41a BD |
630 | dev_info(dev, "clock source %d: %s (%ld Hz)\n", |
631 | ptr, name, clk_get_rate(clk)); | |
632 | } | |
633 | ||
634 | if (clks == 0) { | |
635 | dev_err(dev, "failed to find any bus clocks\n"); | |
636 | ret = -ENOENT; | |
637 | goto err_no_busclks; | |
638 | } | |
639 | ||
2abeb5c5 | 640 | #ifndef CONFIG_PM_RUNTIME |
e684c468 | 641 | clk_enable(sc->clk_bus[sc->cur_clk]); |
2abeb5c5 | 642 | #endif |
e684c468 | 643 | |
9bda6da7 JL |
644 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
645 | host->ioaddr = devm_request_and_ioremap(&pdev->dev, res); | |
0d1bb41a BD |
646 | if (!host->ioaddr) { |
647 | dev_err(dev, "failed to map registers\n"); | |
648 | ret = -ENXIO; | |
649 | goto err_req_regs; | |
650 | } | |
651 | ||
652 | /* Ensure we have minimal gpio selected CMD/CLK/Detect */ | |
653 | if (pdata->cfg_gpio) | |
654 | pdata->cfg_gpio(pdev, pdata->max_width); | |
655 | ||
656 | host->hw_name = "samsung-hsmmc"; | |
657 | host->ops = &sdhci_s3c_ops; | |
658 | host->quirks = 0; | |
659 | host->irq = irq; | |
660 | ||
661 | /* Setup quirks for the controller */ | |
b2e75eff | 662 | host->quirks |= SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC; |
a1d56460 | 663 | host->quirks |= SDHCI_QUIRK_NO_HISPD_BIT; |
3119936a TA |
664 | if (drv_data) |
665 | host->quirks |= drv_data->sdhci_quirks; | |
0d1bb41a BD |
666 | |
667 | #ifndef CONFIG_MMC_SDHCI_S3C_DMA | |
668 | ||
669 | /* we currently see overruns on errors, so disable the SDMA | |
670 | * support as well. */ | |
671 | host->quirks |= SDHCI_QUIRK_BROKEN_DMA; | |
672 | ||
673 | #endif /* CONFIG_MMC_SDHCI_S3C_DMA */ | |
674 | ||
675 | /* It seems we do not get an DATA transfer complete on non-busy | |
676 | * transfers, not sure if this is a problem with this specific | |
677 | * SDHCI block, or a missing configuration that needs to be set. */ | |
678 | host->quirks |= SDHCI_QUIRK_NO_BUSY_IRQ; | |
679 | ||
732f0e31 KP |
680 | /* This host supports the Auto CMD12 */ |
681 | host->quirks |= SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12; | |
682 | ||
7199e2b6 JC |
683 | /* Samsung SoCs need BROKEN_ADMA_ZEROLEN_DESC */ |
684 | host->quirks |= SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC; | |
685 | ||
17866e14 MS |
686 | if (pdata->cd_type == S3C_SDHCI_CD_NONE || |
687 | pdata->cd_type == S3C_SDHCI_CD_PERMANENT) | |
688 | host->quirks |= SDHCI_QUIRK_BROKEN_CARD_DETECTION; | |
689 | ||
690 | if (pdata->cd_type == S3C_SDHCI_CD_PERMANENT) | |
691 | host->mmc->caps = MMC_CAP_NONREMOVABLE; | |
692 | ||
0d22c770 TA |
693 | switch (pdata->max_width) { |
694 | case 8: | |
695 | host->mmc->caps |= MMC_CAP_8_BIT_DATA; | |
696 | case 4: | |
697 | host->mmc->caps |= MMC_CAP_4_BIT_DATA; | |
698 | break; | |
699 | } | |
700 | ||
fa1773cc SL |
701 | if (pdata->pm_caps) |
702 | host->mmc->pm_caps |= pdata->pm_caps; | |
703 | ||
0d1bb41a BD |
704 | host->quirks |= (SDHCI_QUIRK_32BIT_DMA_ADDR | |
705 | SDHCI_QUIRK_32BIT_DMA_SIZE); | |
706 | ||
3fe42e07 HL |
707 | /* HSMMC on Samsung SoCs uses SDCLK as timeout clock */ |
708 | host->quirks |= SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK; | |
709 | ||
253e0a7c JS |
710 | /* |
711 | * If controller does not have internal clock divider, | |
712 | * we can use overriding functions instead of default. | |
713 | */ | |
3119936a | 714 | if (host->quirks & SDHCI_QUIRK_NONSTANDARD_CLOCK) { |
253e0a7c JS |
715 | sdhci_s3c_ops.set_clock = sdhci_cmu_set_clock; |
716 | sdhci_s3c_ops.get_min_clock = sdhci_cmu_get_min_clock; | |
717 | sdhci_s3c_ops.get_max_clock = sdhci_cmu_get_max_clock; | |
718 | } | |
719 | ||
b3824f2c JS |
720 | /* It supports additional host capabilities if needed */ |
721 | if (pdata->host_caps) | |
722 | host->mmc->caps |= pdata->host_caps; | |
723 | ||
c1c4b66d JC |
724 | if (pdata->host_caps2) |
725 | host->mmc->caps2 |= pdata->host_caps2; | |
726 | ||
9f4e8151 MB |
727 | pm_runtime_enable(&pdev->dev); |
728 | pm_runtime_set_autosuspend_delay(&pdev->dev, 50); | |
729 | pm_runtime_use_autosuspend(&pdev->dev); | |
730 | pm_suspend_ignore_children(&pdev->dev, 1); | |
731 | ||
0d1bb41a BD |
732 | ret = sdhci_add_host(host); |
733 | if (ret) { | |
734 | dev_err(dev, "sdhci_add_host() failed\n"); | |
9f4e8151 MB |
735 | pm_runtime_forbid(&pdev->dev); |
736 | pm_runtime_get_noresume(&pdev->dev); | |
9bda6da7 | 737 | goto err_req_regs; |
0d1bb41a BD |
738 | } |
739 | ||
17866e14 MS |
740 | /* The following two methods of card detection might call |
741 | sdhci_s3c_notify_change() immediately, so they can be called | |
742 | only after sdhci_add_host(). Setup errors are ignored. */ | |
743 | if (pdata->cd_type == S3C_SDHCI_CD_EXTERNAL && pdata->ext_cd_init) | |
744 | pdata->ext_cd_init(&sdhci_s3c_notify_change); | |
745 | if (pdata->cd_type == S3C_SDHCI_CD_GPIO && | |
746 | gpio_is_valid(pdata->ext_cd_gpio)) | |
747 | sdhci_s3c_setup_card_detect_gpio(sc); | |
748 | ||
2abeb5c5 CK |
749 | #ifdef CONFIG_PM_RUNTIME |
750 | clk_disable(sc->clk_io); | |
751 | #endif | |
0d1bb41a BD |
752 | return 0; |
753 | ||
0d1bb41a | 754 | err_req_regs: |
2abeb5c5 | 755 | #ifndef CONFIG_PM_RUNTIME |
e684c468 | 756 | clk_disable(sc->clk_bus[sc->cur_clk]); |
2abeb5c5 | 757 | #endif |
0d1bb41a | 758 | for (ptr = 0; ptr < MAX_BUS_CLK; ptr++) { |
326adda5 | 759 | if (sc->clk_bus[ptr]) { |
326adda5 JC |
760 | clk_put(sc->clk_bus[ptr]); |
761 | } | |
0d1bb41a BD |
762 | } |
763 | ||
764 | err_no_busclks: | |
765 | clk_disable(sc->clk_io); | |
766 | clk_put(sc->clk_io); | |
767 | ||
768 | err_io_clk: | |
cd1b00eb TA |
769 | for (ptr = 0; ptr < NUM_GPIOS(sc->pdata->max_width); ptr++) |
770 | gpio_free(sc->gpios[ptr]); | |
771 | if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) | |
772 | gpio_free(sc->ext_cd_gpio); | |
773 | ||
774 | err_pdata: | |
0d1bb41a BD |
775 | sdhci_free_host(host); |
776 | ||
777 | return ret; | |
778 | } | |
779 | ||
780 | static int __devexit sdhci_s3c_remove(struct platform_device *pdev) | |
781 | { | |
9d51a6b2 MS |
782 | struct sdhci_host *host = platform_get_drvdata(pdev); |
783 | struct sdhci_s3c *sc = sdhci_priv(host); | |
cd1b00eb | 784 | struct s3c_sdhci_platdata *pdata = sc->pdata; |
9d51a6b2 MS |
785 | int ptr; |
786 | ||
17866e14 MS |
787 | if (pdata->cd_type == S3C_SDHCI_CD_EXTERNAL && pdata->ext_cd_cleanup) |
788 | pdata->ext_cd_cleanup(&sdhci_s3c_notify_change); | |
789 | ||
790 | if (sc->ext_cd_irq) | |
791 | free_irq(sc->ext_cd_irq, sc); | |
792 | ||
793 | if (gpio_is_valid(sc->ext_cd_gpio)) | |
794 | gpio_free(sc->ext_cd_gpio); | |
795 | ||
2abeb5c5 CK |
796 | #ifdef CONFIG_PM_RUNTIME |
797 | clk_enable(sc->clk_io); | |
798 | #endif | |
9d51a6b2 MS |
799 | sdhci_remove_host(host, 1); |
800 | ||
387a8cbd | 801 | pm_runtime_dont_use_autosuspend(&pdev->dev); |
9f4e8151 MB |
802 | pm_runtime_disable(&pdev->dev); |
803 | ||
2abeb5c5 | 804 | #ifndef CONFIG_PM_RUNTIME |
e684c468 | 805 | clk_disable(sc->clk_bus[sc->cur_clk]); |
2abeb5c5 | 806 | #endif |
5feb54a1 | 807 | for (ptr = 0; ptr < MAX_BUS_CLK; ptr++) { |
9320f7cb | 808 | if (sc->clk_bus[ptr]) { |
9320f7cb MS |
809 | clk_put(sc->clk_bus[ptr]); |
810 | } | |
9d51a6b2 MS |
811 | } |
812 | clk_disable(sc->clk_io); | |
813 | clk_put(sc->clk_io); | |
814 | ||
cd1b00eb TA |
815 | if (pdev->dev.of_node) { |
816 | for (ptr = 0; ptr < NUM_GPIOS(sc->pdata->max_width); ptr++) | |
817 | gpio_free(sc->gpios[ptr]); | |
818 | } | |
819 | ||
9d51a6b2 MS |
820 | sdhci_free_host(host); |
821 | platform_set_drvdata(pdev, NULL); | |
822 | ||
0d1bb41a BD |
823 | return 0; |
824 | } | |
825 | ||
d5e9c02c | 826 | #ifdef CONFIG_PM_SLEEP |
29495aa0 | 827 | static int sdhci_s3c_suspend(struct device *dev) |
0d1bb41a | 828 | { |
29495aa0 | 829 | struct sdhci_host *host = dev_get_drvdata(dev); |
0d1bb41a | 830 | |
29495aa0 | 831 | return sdhci_suspend_host(host); |
0d1bb41a BD |
832 | } |
833 | ||
29495aa0 | 834 | static int sdhci_s3c_resume(struct device *dev) |
0d1bb41a | 835 | { |
29495aa0 | 836 | struct sdhci_host *host = dev_get_drvdata(dev); |
0d1bb41a | 837 | |
65d13516 | 838 | return sdhci_resume_host(host); |
0d1bb41a | 839 | } |
d5e9c02c | 840 | #endif |
0d1bb41a | 841 | |
9f4e8151 MB |
842 | #ifdef CONFIG_PM_RUNTIME |
843 | static int sdhci_s3c_runtime_suspend(struct device *dev) | |
844 | { | |
845 | struct sdhci_host *host = dev_get_drvdata(dev); | |
2abeb5c5 CK |
846 | struct sdhci_s3c *ourhost = to_s3c(host); |
847 | struct clk *busclk = ourhost->clk_io; | |
848 | int ret; | |
849 | ||
850 | ret = sdhci_runtime_suspend_host(host); | |
9f4e8151 | 851 | |
2abeb5c5 CK |
852 | clk_disable(ourhost->clk_bus[ourhost->cur_clk]); |
853 | clk_disable(busclk); | |
854 | return ret; | |
9f4e8151 MB |
855 | } |
856 | ||
857 | static int sdhci_s3c_runtime_resume(struct device *dev) | |
858 | { | |
859 | struct sdhci_host *host = dev_get_drvdata(dev); | |
2abeb5c5 CK |
860 | struct sdhci_s3c *ourhost = to_s3c(host); |
861 | struct clk *busclk = ourhost->clk_io; | |
862 | int ret; | |
9f4e8151 | 863 | |
2abeb5c5 CK |
864 | clk_enable(busclk); |
865 | clk_enable(ourhost->clk_bus[ourhost->cur_clk]); | |
866 | ret = sdhci_runtime_resume_host(host); | |
867 | return ret; | |
9f4e8151 MB |
868 | } |
869 | #endif | |
870 | ||
d5e9c02c | 871 | #ifdef CONFIG_PM |
29495aa0 | 872 | static const struct dev_pm_ops sdhci_s3c_pmops = { |
d5e9c02c | 873 | SET_SYSTEM_SLEEP_PM_OPS(sdhci_s3c_suspend, sdhci_s3c_resume) |
9f4e8151 MB |
874 | SET_RUNTIME_PM_OPS(sdhci_s3c_runtime_suspend, sdhci_s3c_runtime_resume, |
875 | NULL) | |
29495aa0 ML |
876 | }; |
877 | ||
878 | #define SDHCI_S3C_PMOPS (&sdhci_s3c_pmops) | |
879 | ||
0d1bb41a | 880 | #else |
29495aa0 | 881 | #define SDHCI_S3C_PMOPS NULL |
0d1bb41a BD |
882 | #endif |
883 | ||
3119936a TA |
884 | #if defined(CONFIG_CPU_EXYNOS4210) || defined(CONFIG_SOC_EXYNOS4212) |
885 | static struct sdhci_s3c_drv_data exynos4_sdhci_drv_data = { | |
886 | .sdhci_quirks = SDHCI_QUIRK_NONSTANDARD_CLOCK, | |
887 | }; | |
888 | #define EXYNOS4_SDHCI_DRV_DATA ((kernel_ulong_t)&exynos4_sdhci_drv_data) | |
889 | #else | |
890 | #define EXYNOS4_SDHCI_DRV_DATA ((kernel_ulong_t)NULL) | |
891 | #endif | |
892 | ||
893 | static struct platform_device_id sdhci_s3c_driver_ids[] = { | |
894 | { | |
895 | .name = "s3c-sdhci", | |
896 | .driver_data = (kernel_ulong_t)NULL, | |
897 | }, { | |
898 | .name = "exynos4-sdhci", | |
899 | .driver_data = EXYNOS4_SDHCI_DRV_DATA, | |
900 | }, | |
901 | { } | |
902 | }; | |
903 | MODULE_DEVICE_TABLE(platform, sdhci_s3c_driver_ids); | |
904 | ||
cd1b00eb TA |
905 | #ifdef CONFIG_OF |
906 | static const struct of_device_id sdhci_s3c_dt_match[] = { | |
907 | { .compatible = "samsung,s3c6410-sdhci", }, | |
908 | { .compatible = "samsung,exynos4210-sdhci", | |
909 | .data = (void *)EXYNOS4_SDHCI_DRV_DATA }, | |
910 | {}, | |
911 | }; | |
912 | MODULE_DEVICE_TABLE(of, sdhci_s3c_dt_match); | |
913 | #endif | |
914 | ||
0d1bb41a BD |
915 | static struct platform_driver sdhci_s3c_driver = { |
916 | .probe = sdhci_s3c_probe, | |
917 | .remove = __devexit_p(sdhci_s3c_remove), | |
3119936a | 918 | .id_table = sdhci_s3c_driver_ids, |
0d1bb41a BD |
919 | .driver = { |
920 | .owner = THIS_MODULE, | |
921 | .name = "s3c-sdhci", | |
cd1b00eb | 922 | .of_match_table = of_match_ptr(sdhci_s3c_dt_match), |
29495aa0 | 923 | .pm = SDHCI_S3C_PMOPS, |
0d1bb41a BD |
924 | }, |
925 | }; | |
926 | ||
d1f81a64 | 927 | module_platform_driver(sdhci_s3c_driver); |
0d1bb41a BD |
928 | |
929 | MODULE_DESCRIPTION("Samsung SDHCI (HSMMC) glue"); | |
930 | MODULE_AUTHOR("Ben Dooks, <ben@simtec.co.uk>"); | |
931 | MODULE_LICENSE("GPL v2"); | |
932 | MODULE_ALIAS("platform:s3c-sdhci"); |