[mirror_ubuntu-bionic-kernel.git] / drivers / mmc / host / sdhci-tegra.c

/*
 * Copyright (C) 2010 Google, Inc.
 *
 * This software is licensed under the terms of the GNU General Public
 * License version 2, as published by the Free Software Foundation, and
 * may be copied, distributed, and modified under those terms.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 */

#include <linux/err.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/mmc/card.h>
#include <linux/mmc/host.h>
#include <linux/mmc/mmc.h>
#include <linux/mmc/slot-gpio.h>
#include <linux/gpio/consumer.h>

#include "sdhci-pltfm.h"

/* Tegra SDHOST controller vendor register definitions */
#define SDHCI_TEGRA_VENDOR_CLOCK_CTRL			0x100
#define SDHCI_CLOCK_CTRL_TAP_MASK			0x00ff0000
#define SDHCI_CLOCK_CTRL_TAP_SHIFT			16
#define SDHCI_CLOCK_CTRL_SDR50_TUNING_OVERRIDE		BIT(5)
#define SDHCI_CLOCK_CTRL_PADPIPE_CLKEN_OVERRIDE		BIT(3)
#define SDHCI_CLOCK_CTRL_SPI_MODE_CLKEN_OVERRIDE	BIT(2)

#define SDHCI_TEGRA_VENDOR_MISC_CTRL		0x120
#define SDHCI_MISC_CTRL_ENABLE_SDR104		0x8
#define SDHCI_MISC_CTRL_ENABLE_SDR50		0x10
#define SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300	0x20
#define SDHCI_MISC_CTRL_ENABLE_DDR50		0x200

#define NVQUIRK_FORCE_SDHCI_SPEC_200	BIT(0)
#define NVQUIRK_ENABLE_BLOCK_GAP_DET	BIT(1)
#define NVQUIRK_ENABLE_SDHCI_SPEC_300	BIT(2)
#define NVQUIRK_DISABLE_SDR50		BIT(3)
#define NVQUIRK_DISABLE_SDR104		BIT(4)
#define NVQUIRK_DISABLE_DDR50		BIT(5)

struct sdhci_tegra_soc_data {
	const struct sdhci_pltfm_data *pdata;
	u32 nvquirks;
};

struct sdhci_tegra {
	const struct sdhci_tegra_soc_data *soc_data;
	struct gpio_desc *power_gpio;
	bool ddr_signaling;
};

static u16 tegra_sdhci_readw(struct sdhci_host *host, int reg)
{
	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
	struct sdhci_tegra *tegra_host = pltfm_host->priv;
	const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data;

	if (unlikely((soc_data->nvquirks & NVQUIRK_FORCE_SDHCI_SPEC_200) &&
			(reg == SDHCI_HOST_VERSION))) {
		/* Erratum: Version register is invalid in HW. */
		return SDHCI_SPEC_200;
	}

	return readw(host->ioaddr + reg);
}

static void tegra_sdhci_writew(struct sdhci_host *host, u16 val, int reg)
{
	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);

	switch (reg) {
	case SDHCI_TRANSFER_MODE:
		/*
		 * Postpone this write, we must do it together with a
		 * command write that is down below.
		 */
		pltfm_host->xfer_mode_shadow = val;
		return;
	case SDHCI_COMMAND:
		writel((val << 16) | pltfm_host->xfer_mode_shadow,
			host->ioaddr + SDHCI_TRANSFER_MODE);
		return;
	}

	writew(val, host->ioaddr + reg);
}

static void tegra_sdhci_writel(struct sdhci_host *host, u32 val, int reg)
{
	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
	struct sdhci_tegra *tegra_host = pltfm_host->priv;
	const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data;

	/* Seems like we're getting spurious timeout and crc errors, so
	 * disable signalling of them. In case of real errors software
	 * timers should take care of eventually detecting them.
	 */
	if (unlikely(reg == SDHCI_SIGNAL_ENABLE))
		val &= ~(SDHCI_INT_TIMEOUT|SDHCI_INT_CRC);

	writel(val, host->ioaddr + reg);

	if (unlikely((soc_data->nvquirks & NVQUIRK_ENABLE_BLOCK_GAP_DET) &&
			(reg == SDHCI_INT_ENABLE))) {
		/* Erratum: Must enable block gap interrupt detection */
		u8 gap_ctrl = readb(host->ioaddr + SDHCI_BLOCK_GAP_CONTROL);
		if (val & SDHCI_INT_CARD_INT)
			gap_ctrl |= 0x8;
		else
			gap_ctrl &= ~0x8;
		writeb(gap_ctrl, host->ioaddr + SDHCI_BLOCK_GAP_CONTROL);
	}
}

static unsigned int tegra_sdhci_get_ro(struct sdhci_host *host)
{
	return mmc_gpio_get_ro(host->mmc);
}

static void tegra_sdhci_reset(struct sdhci_host *host, u8 mask)
{
	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
	struct sdhci_tegra *tegra_host = pltfm_host->priv;
	const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data;
	u32 misc_ctrl, clk_ctrl;

	sdhci_reset(host, mask);

	if (!(mask & SDHCI_RESET_ALL))
		return;

	misc_ctrl = sdhci_readw(host, SDHCI_TEGRA_VENDOR_MISC_CTRL);
	/* Erratum: Enable SDHCI spec v3.00 support */
	if (soc_data->nvquirks & NVQUIRK_ENABLE_SDHCI_SPEC_300)
		misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300;
	/* Don't advertise UHS modes which aren't supported yet */
	if (soc_data->nvquirks & NVQUIRK_DISABLE_SDR50)
		misc_ctrl &= ~SDHCI_MISC_CTRL_ENABLE_SDR50;
	if (soc_data->nvquirks & NVQUIRK_DISABLE_DDR50)
		misc_ctrl &= ~SDHCI_MISC_CTRL_ENABLE_DDR50;
	if (soc_data->nvquirks & NVQUIRK_DISABLE_SDR104)
		misc_ctrl &= ~SDHCI_MISC_CTRL_ENABLE_SDR104;
	sdhci_writew(host, misc_ctrl, SDHCI_TEGRA_VENDOR_MISC_CTRL);

	clk_ctrl = sdhci_readl(host, SDHCI_TEGRA_VENDOR_CLOCK_CTRL);
	clk_ctrl &= ~SDHCI_CLOCK_CTRL_SPI_MODE_CLKEN_OVERRIDE;
	if (!(soc_data->nvquirks & NVQUIRK_DISABLE_SDR50))
		clk_ctrl |= SDHCI_CLOCK_CTRL_SDR50_TUNING_OVERRIDE;
	sdhci_writel(host, clk_ctrl, SDHCI_TEGRA_VENDOR_CLOCK_CTRL);

	tegra_host->ddr_signaling = false;
}

static void tegra_sdhci_set_bus_width(struct sdhci_host *host, int bus_width)
{
	u32 ctrl;

	ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
	if ((host->mmc->caps & MMC_CAP_8_BIT_DATA) &&
	    (bus_width == MMC_BUS_WIDTH_8)) {
		ctrl &= ~SDHCI_CTRL_4BITBUS;
		ctrl |= SDHCI_CTRL_8BITBUS;
	} else {
		ctrl &= ~SDHCI_CTRL_8BITBUS;
		if (bus_width == MMC_BUS_WIDTH_4)
			ctrl |= SDHCI_CTRL_4BITBUS;
		else
			ctrl &= ~SDHCI_CTRL_4BITBUS;
	}
	sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
}

static void tegra_sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
{
	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
	struct sdhci_tegra *tegra_host = pltfm_host->priv;
	unsigned long host_clk;

	if (!clock)
		return;

	host_clk = tegra_host->ddr_signaling ? clock * 2 : clock;
	clk_set_rate(pltfm_host->clk, host_clk);
	host->max_clk = clk_get_rate(pltfm_host->clk);

	return sdhci_set_clock(host, clock);
}

static void tegra_sdhci_set_uhs_signaling(struct sdhci_host *host,
					  unsigned timing)
{
	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
	struct sdhci_tegra *tegra_host = pltfm_host->priv;

	if (timing == MMC_TIMING_UHS_DDR50)
		tegra_host->ddr_signaling = true;

	return sdhci_set_uhs_signaling(host, timing);
}

static unsigned int tegra_sdhci_get_max_clock(struct sdhci_host *host)
{
	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);

	/*
	 * DDR modes require the host to run at double the card frequency, so
	 * the maximum rate we can support is half of the module input clock.
	 */
	return clk_round_rate(pltfm_host->clk, UINT_MAX) / 2;
}

static void tegra_sdhci_set_tap(struct sdhci_host *host, unsigned int tap)
{
	u32 reg;

	reg = sdhci_readl(host, SDHCI_TEGRA_VENDOR_CLOCK_CTRL);
	reg &= ~SDHCI_CLOCK_CTRL_TAP_MASK;
	reg |= tap << SDHCI_CLOCK_CTRL_TAP_SHIFT;
	sdhci_writel(host, reg, SDHCI_TEGRA_VENDOR_CLOCK_CTRL);
}

static int tegra_sdhci_execute_tuning(struct sdhci_host *host, u32 opcode)
{
	unsigned int min, max;

	/*
	 * Start search for minimum tap value at 10, as smaller values are
	 * may wrongly be reported as working but fail at higher speeds,
	 * according to the TRM.
	 */
	min = 10;
	while (min < 255) {
		tegra_sdhci_set_tap(host, min);
		if (!mmc_send_tuning(host->mmc, opcode, NULL))
			break;
		min++;
	}

	/* Find the maximum tap value that still passes. */
	max = min + 1;
	while (max < 255) {
		tegra_sdhci_set_tap(host, max);
		if (mmc_send_tuning(host->mmc, opcode, NULL)) {
			max--;
			break;
		}
		max++;
	}

	/* The TRM states the ideal tap value is at 75% in the passing range. */
	tegra_sdhci_set_tap(host, min + ((max - min) * 3 / 4));

	return mmc_send_tuning(host->mmc, opcode, NULL);
}

static const struct sdhci_ops tegra_sdhci_ops = {
	.get_ro     = tegra_sdhci_get_ro,
	.read_w     = tegra_sdhci_readw,
	.write_l    = tegra_sdhci_writel,
	.set_clock  = tegra_sdhci_set_clock,
	.set_bus_width = tegra_sdhci_set_bus_width,
	.reset      = tegra_sdhci_reset,
	.platform_execute_tuning = tegra_sdhci_execute_tuning,
	.set_uhs_signaling = tegra_sdhci_set_uhs_signaling,
	.get_max_clock = tegra_sdhci_get_max_clock,
};

static const struct sdhci_pltfm_data sdhci_tegra20_pdata = {
	.quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL |
		  SDHCI_QUIRK_SINGLE_POWER_WRITE |
		  SDHCI_QUIRK_NO_HISPD_BIT |
		  SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC |
		  SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
	.ops  = &tegra_sdhci_ops,
};

static const struct sdhci_tegra_soc_data soc_data_tegra20 = {
	.pdata = &sdhci_tegra20_pdata,
	.nvquirks = NVQUIRK_FORCE_SDHCI_SPEC_200 |
		    NVQUIRK_ENABLE_BLOCK_GAP_DET,
};

static const struct sdhci_pltfm_data sdhci_tegra30_pdata = {
	.quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL |
		  SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
		  SDHCI_QUIRK_SINGLE_POWER_WRITE |
		  SDHCI_QUIRK_NO_HISPD_BIT |
		  SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC |
		  SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
	.quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
	.ops  = &tegra_sdhci_ops,
};

static const struct sdhci_tegra_soc_data soc_data_tegra30 = {
	.pdata = &sdhci_tegra30_pdata,
	.nvquirks = NVQUIRK_ENABLE_SDHCI_SPEC_300 |
		    NVQUIRK_DISABLE_SDR50 |
		    NVQUIRK_DISABLE_SDR104,
};

static const struct sdhci_ops tegra114_sdhci_ops = {
	.get_ro     = tegra_sdhci_get_ro,
	.read_w     = tegra_sdhci_readw,
	.write_w    = tegra_sdhci_writew,
	.write_l    = tegra_sdhci_writel,
	.set_clock  = tegra_sdhci_set_clock,
	.set_bus_width = tegra_sdhci_set_bus_width,
	.reset      = tegra_sdhci_reset,
	.platform_execute_tuning = tegra_sdhci_execute_tuning,
	.set_uhs_signaling = tegra_sdhci_set_uhs_signaling,
	.get_max_clock = tegra_sdhci_get_max_clock,
};

static const struct sdhci_pltfm_data sdhci_tegra114_pdata = {
	.quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL |
		  SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
		  SDHCI_QUIRK_SINGLE_POWER_WRITE |
		  SDHCI_QUIRK_NO_HISPD_BIT |
		  SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC |
		  SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
	.quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
	.ops  = &tegra114_sdhci_ops,
};

static const struct sdhci_tegra_soc_data soc_data_tegra114 = {
	.pdata = &sdhci_tegra114_pdata,
	.nvquirks = NVQUIRK_DISABLE_SDR50 |
		    NVQUIRK_DISABLE_DDR50 |
		    NVQUIRK_DISABLE_SDR104,
};

static const struct sdhci_pltfm_data sdhci_tegra210_pdata = {
	.quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL |
		  SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
		  SDHCI_QUIRK_SINGLE_POWER_WRITE |
		  SDHCI_QUIRK_NO_HISPD_BIT |
		  SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC |
		  SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
	.quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
	.ops  = &tegra114_sdhci_ops,
};

static const struct sdhci_tegra_soc_data soc_data_tegra210 = {
	.pdata = &sdhci_tegra210_pdata,
	.nvquirks = NVQUIRK_DISABLE_SDR50 |
		    NVQUIRK_DISABLE_DDR50 |
		    NVQUIRK_DISABLE_SDR104,
};

static const struct of_device_id sdhci_tegra_dt_match[] = {
	{ .compatible = "nvidia,tegra210-sdhci", .data = &soc_data_tegra210 },
	{ .compatible = "nvidia,tegra124-sdhci", .data = &soc_data_tegra114 },
	{ .compatible = "nvidia,tegra114-sdhci", .data = &soc_data_tegra114 },
	{ .compatible = "nvidia,tegra30-sdhci", .data = &soc_data_tegra30 },
	{ .compatible = "nvidia,tegra20-sdhci", .data = &soc_data_tegra20 },
	{}
};
MODULE_DEVICE_TABLE(of, sdhci_tegra_dt_match);

static int sdhci_tegra_probe(struct platform_device *pdev)
{
	const struct of_device_id *match;
	const struct sdhci_tegra_soc_data *soc_data;
	struct sdhci_host *host;
	struct sdhci_pltfm_host *pltfm_host;
	struct sdhci_tegra *tegra_host;
	struct clk *clk;
	int rc;

	match = of_match_device(sdhci_tegra_dt_match, &pdev->dev);
	if (!match)
		return -EINVAL;
	soc_data = match->data;

	host = sdhci_pltfm_init(pdev, soc_data->pdata, 0);
	if (IS_ERR(host))
		return PTR_ERR(host);
	pltfm_host = sdhci_priv(host);

	tegra_host = devm_kzalloc(&pdev->dev, sizeof(*tegra_host), GFP_KERNEL);
	if (!tegra_host) {
		dev_err(mmc_dev(host->mmc), "failed to allocate tegra_host\n");
		rc = -ENOMEM;
		goto err_alloc_tegra_host;
	}
	tegra_host->ddr_signaling = false;
	tegra_host->soc_data = soc_data;
	pltfm_host->priv = tegra_host;

	rc = mmc_of_parse(host->mmc);
	if (rc)
		goto err_parse_dt;

	if (!(tegra_host->soc_data->nvquirks & NVQUIRK_DISABLE_DDR50))
		host->mmc->caps |= MMC_CAP_1_8V_DDR;

	tegra_host->power_gpio = devm_gpiod_get_optional(&pdev->dev, "power",
							 GPIOD_OUT_HIGH);
	if (IS_ERR(tegra_host->power_gpio)) {
		rc = PTR_ERR(tegra_host->power_gpio);
		goto err_power_req;
	}

	clk = devm_clk_get(mmc_dev(host->mmc), NULL);
	if (IS_ERR(clk)) {
		dev_err(mmc_dev(host->mmc), "clk err\n");
		rc = PTR_ERR(clk);
		goto err_clk_get;
	}
	clk_prepare_enable(clk);
	pltfm_host->clk = clk;

	rc = sdhci_add_host(host);
	if (rc)
		goto err_add_host;

	return 0;

err_add_host:
	clk_disable_unprepare(pltfm_host->clk);
err_clk_get:
err_power_req:
err_parse_dt:
err_alloc_tegra_host:
	sdhci_pltfm_free(pdev);
	return rc;
}

static struct platform_driver sdhci_tegra_driver = {
	.driver		= {
		.name	= "sdhci-tegra",
		.of_match_table = sdhci_tegra_dt_match,
		.pm	= SDHCI_PLTFM_PMOPS,
	},
	.probe		= sdhci_tegra_probe,
	.remove		= sdhci_pltfm_unregister,
};

module_platform_driver(sdhci_tegra_driver);

MODULE_DESCRIPTION("SDHCI driver for Tegra");
MODULE_AUTHOR("Google, Inc.");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
03d2bfc8 OJ	1	/*
	2	* Copyright (C) 2010 Google, Inc.
	3	*
	4	* This software is licensed under the terms of the GNU General Public
	5	* License version 2, as published by the Free Software Foundation, and
	6	* may be copied, distributed, and modified under those terms.
	7	*
	8	* This program is distributed in the hope that it will be useful,
	9	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	10	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	11	* GNU General Public License for more details.
	12	*
	13	*/
	14
	15	#include <linux/err.h>
96547f5d	16	#include <linux/module.h>
03d2bfc8 OJ	17	#include <linux/init.h>
	18	#include <linux/platform_device.h>
	19	#include <linux/clk.h>
	20	#include <linux/io.h>
55cd65e4	21	#include <linux/of.h>
3e44a1a7	22	#include <linux/of_device.h>
03d2bfc8 OJ	23	#include <linux/mmc/card.h>
03d2bfc8 OJ	24	#include <linux/mmc/host.h>
c3c2384c	25	#include <linux/mmc/mmc.h>
0aacd23f	26	#include <linux/mmc/slot-gpio.h>
2391b340	27	#include <linux/gpio/consumer.h>
03d2bfc8	28
03d2bfc8 OJ	29	#include "sdhci-pltfm.h"
03d2bfc8 OJ	30
ca5879d3	31	/* Tegra SDHOST controller vendor register definitions */
74cd42bc	32	#define SDHCI_TEGRA_VENDOR_CLOCK_CTRL 0x100
c3c2384c LS	33	#define SDHCI_CLOCK_CTRL_TAP_MASK 0x00ff0000
	34	#define SDHCI_CLOCK_CTRL_TAP_SHIFT 16
	35	#define SDHCI_CLOCK_CTRL_SDR50_TUNING_OVERRIDE BIT(5)
74cd42bc LS	36	#define SDHCI_CLOCK_CTRL_PADPIPE_CLKEN_OVERRIDE BIT(3)
	37	#define SDHCI_CLOCK_CTRL_SPI_MODE_CLKEN_OVERRIDE BIT(2)
	38
ca5879d3	39	#define SDHCI_TEGRA_VENDOR_MISC_CTRL 0x120
3145351a AB	40	#define SDHCI_MISC_CTRL_ENABLE_SDR104 0x8
3145351a AB	41	#define SDHCI_MISC_CTRL_ENABLE_SDR50 0x10
ca5879d3	42	#define SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300 0x20
3145351a	43	#define SDHCI_MISC_CTRL_ENABLE_DDR50 0x200
ca5879d3	44
3e44a1a7 SW	45	#define NVQUIRK_FORCE_SDHCI_SPEC_200 BIT(0)
3e44a1a7 SW	46	#define NVQUIRK_ENABLE_BLOCK_GAP_DET BIT(1)
ca5879d3	47	#define NVQUIRK_ENABLE_SDHCI_SPEC_300 BIT(2)
3145351a AB	48	#define NVQUIRK_DISABLE_SDR50 BIT(3)
	49	#define NVQUIRK_DISABLE_SDR104 BIT(4)
	50	#define NVQUIRK_DISABLE_DDR50 BIT(5)
3e44a1a7 SW	51
3e44a1a7 SW	52	struct sdhci_tegra_soc_data {
1db5eebf	53	const struct sdhci_pltfm_data *pdata;
3e44a1a7 SW	54	u32 nvquirks;
	55	};
	56
	57	struct sdhci_tegra {
3e44a1a7	58	const struct sdhci_tegra_soc_data *soc_data;
2391b340	59	struct gpio_desc *power_gpio;
a8e326a9	60	bool ddr_signaling;
3e44a1a7 SW	61	};
3e44a1a7 SW	62
03d2bfc8 OJ	63	static u16 tegra_sdhci_readw(struct sdhci_host *host, int reg)
03d2bfc8 OJ	64	{
3e44a1a7 SW	65	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
	66	struct sdhci_tegra *tegra_host = pltfm_host->priv;
	67	const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data;
	68
	69	if (unlikely((soc_data->nvquirks & NVQUIRK_FORCE_SDHCI_SPEC_200) &&
	70	(reg == SDHCI_HOST_VERSION))) {
03d2bfc8 OJ	71	/* Erratum: Version register is invalid in HW. */
	72	return SDHCI_SPEC_200;
	73	}
	74
	75	return readw(host->ioaddr + reg);
	76	}
	77
352ee868 PK	78	static void tegra_sdhci_writew(struct sdhci_host *host, u16 val, int reg)
	79	{
	80	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
352ee868	81
01df7ecd RK	82	switch (reg) {
	83	case SDHCI_TRANSFER_MODE:
	84	/*
	85	* Postpone this write, we must do it together with a
	86	* command write that is down below.
	87	*/
	88	pltfm_host->xfer_mode_shadow = val;
	89	return;
	90	case SDHCI_COMMAND:
	91	writel((val << 16) \| pltfm_host->xfer_mode_shadow,
	92	host->ioaddr + SDHCI_TRANSFER_MODE);
	93	return;
352ee868 PK	94	}
	95
	96	writew(val, host->ioaddr + reg);
	97	}
	98
03d2bfc8 OJ	99	static void tegra_sdhci_writel(struct sdhci_host *host, u32 val, int reg)
03d2bfc8 OJ	100	{
3e44a1a7 SW	101	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
	102	struct sdhci_tegra *tegra_host = pltfm_host->priv;
	103	const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data;
	104
03d2bfc8 OJ	105	/* Seems like we're getting spurious timeout and crc errors, so
	106	* disable signalling of them. In case of real errors software
	107	* timers should take care of eventually detecting them.
	108	*/
	109	if (unlikely(reg == SDHCI_SIGNAL_ENABLE))
	110	val &= ~(SDHCI_INT_TIMEOUT\|SDHCI_INT_CRC);
	111
	112	writel(val, host->ioaddr + reg);
	113
3e44a1a7 SW	114	if (unlikely((soc_data->nvquirks & NVQUIRK_ENABLE_BLOCK_GAP_DET) &&
3e44a1a7 SW	115	(reg == SDHCI_INT_ENABLE))) {
03d2bfc8 OJ	116	/* Erratum: Must enable block gap interrupt detection */
	117	u8 gap_ctrl = readb(host->ioaddr + SDHCI_BLOCK_GAP_CONTROL);
	118	if (val & SDHCI_INT_CARD_INT)
	119	gap_ctrl \|= 0x8;
	120	else
	121	gap_ctrl &= ~0x8;
	122	writeb(gap_ctrl, host->ioaddr + SDHCI_BLOCK_GAP_CONTROL);
	123	}
	124	}
	125
3e44a1a7	126	static unsigned int tegra_sdhci_get_ro(struct sdhci_host *host)
03d2bfc8	127	{
0aacd23f	128	return mmc_gpio_get_ro(host->mmc);
03d2bfc8 OJ	129	}
03d2bfc8 OJ	130
03231f9b	131	static void tegra_sdhci_reset(struct sdhci_host *host, u8 mask)
ca5879d3 PK	132	{
	133	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
	134	struct sdhci_tegra *tegra_host = pltfm_host->priv;
	135	const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data;
74cd42bc	136	u32 misc_ctrl, clk_ctrl;
ca5879d3	137
03231f9b RK	138	sdhci_reset(host, mask);
03231f9b RK	139
ca5879d3 PK	140	if (!(mask & SDHCI_RESET_ALL))
	141	return;
	142
3145351a	143	misc_ctrl = sdhci_readw(host, SDHCI_TEGRA_VENDOR_MISC_CTRL);
ca5879d3	144	/* Erratum: Enable SDHCI spec v3.00 support */
3145351a	145	if (soc_data->nvquirks & NVQUIRK_ENABLE_SDHCI_SPEC_300)
ca5879d3	146	misc_ctrl \|= SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300;
3145351a AB	147	/* Don't advertise UHS modes which aren't supported yet */
	148	if (soc_data->nvquirks & NVQUIRK_DISABLE_SDR50)
	149	misc_ctrl &= ~SDHCI_MISC_CTRL_ENABLE_SDR50;
	150	if (soc_data->nvquirks & NVQUIRK_DISABLE_DDR50)
	151	misc_ctrl &= ~SDHCI_MISC_CTRL_ENABLE_DDR50;
	152	if (soc_data->nvquirks & NVQUIRK_DISABLE_SDR104)
	153	misc_ctrl &= ~SDHCI_MISC_CTRL_ENABLE_SDR104;
	154	sdhci_writew(host, misc_ctrl, SDHCI_TEGRA_VENDOR_MISC_CTRL);
a8e326a9	155
74cd42bc LS	156	clk_ctrl = sdhci_readl(host, SDHCI_TEGRA_VENDOR_CLOCK_CTRL);
74cd42bc LS	157	clk_ctrl &= ~SDHCI_CLOCK_CTRL_SPI_MODE_CLKEN_OVERRIDE;
c3c2384c LS	158	if (!(soc_data->nvquirks & NVQUIRK_DISABLE_SDR50))
c3c2384c LS	159	clk_ctrl \|= SDHCI_CLOCK_CTRL_SDR50_TUNING_OVERRIDE;
74cd42bc LS	160	sdhci_writel(host, clk_ctrl, SDHCI_TEGRA_VENDOR_CLOCK_CTRL);
74cd42bc LS	161
a8e326a9	162	tegra_host->ddr_signaling = false;
ca5879d3 PK	163	}
ca5879d3 PK	164
2317f56c	165	static void tegra_sdhci_set_bus_width(struct sdhci_host *host, int bus_width)
03d2bfc8	166	{
03d2bfc8 OJ	167	u32 ctrl;
03d2bfc8 OJ	168
03d2bfc8	169	ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
0aacd23f JL	170	if ((host->mmc->caps & MMC_CAP_8_BIT_DATA) &&
0aacd23f JL	171	(bus_width == MMC_BUS_WIDTH_8)) {
03d2bfc8 OJ	172	ctrl &= ~SDHCI_CTRL_4BITBUS;
	173	ctrl \|= SDHCI_CTRL_8BITBUS;
	174	} else {
	175	ctrl &= ~SDHCI_CTRL_8BITBUS;
	176	if (bus_width == MMC_BUS_WIDTH_4)
	177	ctrl \|= SDHCI_CTRL_4BITBUS;
	178	else
	179	ctrl &= ~SDHCI_CTRL_4BITBUS;
	180	}
	181	sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
03d2bfc8 OJ	182	}
03d2bfc8 OJ	183
a8e326a9 LS	184	static void tegra_sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
	185	{
	186	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
	187	struct sdhci_tegra *tegra_host = pltfm_host->priv;
	188	unsigned long host_clk;
	189
	190	if (!clock)
	191	return;
	192
	193	host_clk = tegra_host->ddr_signaling ? clock * 2 : clock;
	194	clk_set_rate(pltfm_host->clk, host_clk);
	195	host->max_clk = clk_get_rate(pltfm_host->clk);
	196
	197	return sdhci_set_clock(host, clock);
	198	}
	199
	200	static void tegra_sdhci_set_uhs_signaling(struct sdhci_host *host,
	201	unsigned timing)
	202	{
	203	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
	204	struct sdhci_tegra *tegra_host = pltfm_host->priv;
	205
	206	if (timing == MMC_TIMING_UHS_DDR50)
	207	tegra_host->ddr_signaling = true;
	208
	209	return sdhci_set_uhs_signaling(host, timing);
	210	}
	211
	212	static unsigned int tegra_sdhci_get_max_clock(struct sdhci_host *host)
	213	{
	214	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
	215
	216	/*
	217	* DDR modes require the host to run at double the card frequency, so
	218	* the maximum rate we can support is half of the module input clock.
	219	*/
	220	return clk_round_rate(pltfm_host->clk, UINT_MAX) / 2;
	221	}
	222
c3c2384c LS	223	static void tegra_sdhci_set_tap(struct sdhci_host *host, unsigned int tap)
	224	{
	225	u32 reg;
	226
	227	reg = sdhci_readl(host, SDHCI_TEGRA_VENDOR_CLOCK_CTRL);
	228	reg &= ~SDHCI_CLOCK_CTRL_TAP_MASK;
	229	reg \|= tap << SDHCI_CLOCK_CTRL_TAP_SHIFT;
	230	sdhci_writel(host, reg, SDHCI_TEGRA_VENDOR_CLOCK_CTRL);
	231	}
	232
	233	static int tegra_sdhci_execute_tuning(struct sdhci_host *host, u32 opcode)
	234	{
	235	unsigned int min, max;
	236
	237	/*
	238	* Start search for minimum tap value at 10, as smaller values are
	239	* may wrongly be reported as working but fail at higher speeds,
	240	* according to the TRM.
	241	*/
	242	min = 10;
	243	while (min < 255) {
	244	tegra_sdhci_set_tap(host, min);
	245	if (!mmc_send_tuning(host->mmc, opcode, NULL))
	246	break;
	247	min++;
	248	}
	249
	250	/* Find the maximum tap value that still passes. */
	251	max = min + 1;
	252	while (max < 255) {
	253	tegra_sdhci_set_tap(host, max);
	254	if (mmc_send_tuning(host->mmc, opcode, NULL)) {
	255	max--;
	256	break;
	257	}
	258	max++;
	259	}
	260
	261	/* The TRM states the ideal tap value is at 75% in the passing range. */
	262	tegra_sdhci_set_tap(host, min + ((max - min) * 3 / 4));
	263
	264	return mmc_send_tuning(host->mmc, opcode, NULL);
	265	}
	266
c915568d	267	static const struct sdhci_ops tegra_sdhci_ops = {
85d6509d	268	.get_ro = tegra_sdhci_get_ro,
85d6509d SG	269	.read_w = tegra_sdhci_readw,
85d6509d SG	270	.write_l = tegra_sdhci_writel,
a8e326a9	271	.set_clock = tegra_sdhci_set_clock,
2317f56c	272	.set_bus_width = tegra_sdhci_set_bus_width,
03231f9b	273	.reset = tegra_sdhci_reset,
c3c2384c	274	.platform_execute_tuning = tegra_sdhci_execute_tuning,
a8e326a9 LS	275	.set_uhs_signaling = tegra_sdhci_set_uhs_signaling,
a8e326a9 LS	276	.get_max_clock = tegra_sdhci_get_max_clock,
85d6509d SG	277	};
85d6509d SG	278
1db5eebf	279	static const struct sdhci_pltfm_data sdhci_tegra20_pdata = {
3e44a1a7 SW	280	.quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL \|
	281	SDHCI_QUIRK_SINGLE_POWER_WRITE \|
	282	SDHCI_QUIRK_NO_HISPD_BIT \|
f9260355 AB	283	SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC \|
f9260355 AB	284	SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
3e44a1a7 SW	285	.ops = &tegra_sdhci_ops,
	286	};
	287
d49d19c2	288	static const struct sdhci_tegra_soc_data soc_data_tegra20 = {
3e44a1a7 SW	289	.pdata = &sdhci_tegra20_pdata,
	290	.nvquirks = NVQUIRK_FORCE_SDHCI_SPEC_200 \|
	291	NVQUIRK_ENABLE_BLOCK_GAP_DET,
	292	};
3e44a1a7	293
1db5eebf	294	static const struct sdhci_pltfm_data sdhci_tegra30_pdata = {
85d6509d	295	.quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL \|
3e44a1a7	296	SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK \|
85d6509d SG	297	SDHCI_QUIRK_SINGLE_POWER_WRITE \|
85d6509d SG	298	SDHCI_QUIRK_NO_HISPD_BIT \|
f9260355 AB	299	SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC \|
f9260355 AB	300	SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
a8e326a9	301	.quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
85d6509d SG	302	.ops = &tegra_sdhci_ops,
85d6509d SG	303	};
03d2bfc8	304
d49d19c2	305	static const struct sdhci_tegra_soc_data soc_data_tegra30 = {
3e44a1a7	306	.pdata = &sdhci_tegra30_pdata,
3145351a AB	307	.nvquirks = NVQUIRK_ENABLE_SDHCI_SPEC_300 \|
	308	NVQUIRK_DISABLE_SDR50 \|
	309	NVQUIRK_DISABLE_SDR104,
3e44a1a7	310	};
3e44a1a7	311
01df7ecd RK	312	static const struct sdhci_ops tegra114_sdhci_ops = {
	313	.get_ro = tegra_sdhci_get_ro,
	314	.read_w = tegra_sdhci_readw,
	315	.write_w = tegra_sdhci_writew,
	316	.write_l = tegra_sdhci_writel,
a8e326a9	317	.set_clock = tegra_sdhci_set_clock,
01df7ecd RK	318	.set_bus_width = tegra_sdhci_set_bus_width,
01df7ecd RK	319	.reset = tegra_sdhci_reset,
c3c2384c	320	.platform_execute_tuning = tegra_sdhci_execute_tuning,
a8e326a9 LS	321	.set_uhs_signaling = tegra_sdhci_set_uhs_signaling,
a8e326a9 LS	322	.get_max_clock = tegra_sdhci_get_max_clock,
01df7ecd RK	323	};
01df7ecd RK	324
1db5eebf	325	static const struct sdhci_pltfm_data sdhci_tegra114_pdata = {
5ebf2552 RK	326	.quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL \|
	327	SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK \|
	328	SDHCI_QUIRK_SINGLE_POWER_WRITE \|
	329	SDHCI_QUIRK_NO_HISPD_BIT \|
f9260355 AB	330	SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC \|
f9260355 AB	331	SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
a8e326a9	332	.quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
01df7ecd	333	.ops = &tegra114_sdhci_ops,
5ebf2552 RK	334	};
5ebf2552 RK	335
d49d19c2	336	static const struct sdhci_tegra_soc_data soc_data_tegra114 = {
5ebf2552	337	.pdata = &sdhci_tegra114_pdata,
3145351a AB	338	.nvquirks = NVQUIRK_DISABLE_SDR50 \|
3145351a AB	339	NVQUIRK_DISABLE_DDR50 \|
01df7ecd	340	NVQUIRK_DISABLE_SDR104,
5ebf2552 RK	341	};
5ebf2552 RK	342
b5a84ecf TR	343	static const struct sdhci_pltfm_data sdhci_tegra210_pdata = {
	344	.quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL \|
	345	SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK \|
	346	SDHCI_QUIRK_SINGLE_POWER_WRITE \|
	347	SDHCI_QUIRK_NO_HISPD_BIT \|
a8e326a9 LS	348	SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC \|
	349	SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
	350	.quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
b5a84ecf TR	351	.ops = &tegra114_sdhci_ops,
	352	};
	353
	354	static const struct sdhci_tegra_soc_data soc_data_tegra210 = {
	355	.pdata = &sdhci_tegra210_pdata,
	356	.nvquirks = NVQUIRK_DISABLE_SDR50 \|
	357	NVQUIRK_DISABLE_DDR50 \|
	358	NVQUIRK_DISABLE_SDR104,
	359	};
	360
498d83e7	361	static const struct of_device_id sdhci_tegra_dt_match[] = {
b5a84ecf	362	{ .compatible = "nvidia,tegra210-sdhci", .data = &soc_data_tegra210 },
67debea3	363	{ .compatible = "nvidia,tegra124-sdhci", .data = &soc_data_tegra114 },
5ebf2552	364	{ .compatible = "nvidia,tegra114-sdhci", .data = &soc_data_tegra114 },
3e44a1a7	365	{ .compatible = "nvidia,tegra30-sdhci", .data = &soc_data_tegra30 },
3e44a1a7	366	{ .compatible = "nvidia,tegra20-sdhci", .data = &soc_data_tegra20 },
275173b2 GL	367	{}
275173b2 GL	368	};
e4404fab	369	MODULE_DEVICE_TABLE(of, sdhci_tegra_dt_match);
275173b2	370
c3be1efd	371	static int sdhci_tegra_probe(struct platform_device *pdev)
03d2bfc8	372	{
3e44a1a7 SW	373	const struct of_device_id *match;
	374	const struct sdhci_tegra_soc_data *soc_data;
	375	struct sdhci_host *host;
85d6509d	376	struct sdhci_pltfm_host *pltfm_host;
3e44a1a7	377	struct sdhci_tegra *tegra_host;
03d2bfc8 OJ	378	struct clk *clk;
	379	int rc;
	380
3e44a1a7	381	match = of_match_device(sdhci_tegra_dt_match, &pdev->dev);
b37f9d98 JL	382	if (!match)
	383	return -EINVAL;
	384	soc_data = match->data;
3e44a1a7	385
0e748234	386	host = sdhci_pltfm_init(pdev, soc_data->pdata, 0);
85d6509d SG	387	if (IS_ERR(host))
85d6509d SG	388	return PTR_ERR(host);
85d6509d SG	389	pltfm_host = sdhci_priv(host);
85d6509d SG	390
3e44a1a7 SW	391	tegra_host = devm_kzalloc(&pdev->dev, sizeof(*tegra_host), GFP_KERNEL);
	392	if (!tegra_host) {
	393	dev_err(mmc_dev(host->mmc), "failed to allocate tegra_host\n");
	394	rc = -ENOMEM;
0e786102	395	goto err_alloc_tegra_host;
3e44a1a7	396	}
a8e326a9	397	tegra_host->ddr_signaling = false;
3e44a1a7	398	tegra_host->soc_data = soc_data;
3e44a1a7	399	pltfm_host->priv = tegra_host;
275173b2	400
2391b340	401	rc = mmc_of_parse(host->mmc);
47caa84f SB	402	if (rc)
47caa84f SB	403	goto err_parse_dt;
0e786102	404
c3c2384c LS	405	if (!(tegra_host->soc_data->nvquirks & NVQUIRK_DISABLE_DDR50))
	406	host->mmc->caps \|= MMC_CAP_1_8V_DDR;
	407
2391b340 MJ	408	tegra_host->power_gpio = devm_gpiod_get_optional(&pdev->dev, "power",
	409	GPIOD_OUT_HIGH);
	410	if (IS_ERR(tegra_host->power_gpio)) {
	411	rc = PTR_ERR(tegra_host->power_gpio);
	412	goto err_power_req;
03d2bfc8 OJ	413	}
03d2bfc8 OJ	414
e4f79d9c	415	clk = devm_clk_get(mmc_dev(host->mmc), NULL);
03d2bfc8 OJ	416	if (IS_ERR(clk)) {
	417	dev_err(mmc_dev(host->mmc), "clk err\n");
	418	rc = PTR_ERR(clk);
85d6509d	419	goto err_clk_get;
03d2bfc8	420	}
1e674bc6	421	clk_prepare_enable(clk);
03d2bfc8 OJ	422	pltfm_host->clk = clk;
03d2bfc8 OJ	423
85d6509d SG	424	rc = sdhci_add_host(host);
	425	if (rc)
	426	goto err_add_host;
	427
03d2bfc8 OJ	428	return 0;
03d2bfc8 OJ	429
85d6509d	430	err_add_host:
1e674bc6	431	clk_disable_unprepare(pltfm_host->clk);
85d6509d	432	err_clk_get:
85d6509d	433	err_power_req:
47caa84f	434	err_parse_dt:
0e786102	435	err_alloc_tegra_host:
85d6509d	436	sdhci_pltfm_free(pdev);
03d2bfc8 OJ	437	return rc;
	438	}
	439
85d6509d SG	440	static struct platform_driver sdhci_tegra_driver = {
	441	.driver = {
	442	.name = "sdhci-tegra",
275173b2	443	.of_match_table = sdhci_tegra_dt_match,
29495aa0	444	.pm = SDHCI_PLTFM_PMOPS,
85d6509d SG	445	},
85d6509d SG	446	.probe = sdhci_tegra_probe,
caebcae9	447	.remove = sdhci_pltfm_unregister,
03d2bfc8 OJ	448	};
03d2bfc8 OJ	449
d1f81a64	450	module_platform_driver(sdhci_tegra_driver);
85d6509d SG	451
85d6509d SG	452	MODULE_DESCRIPTION("SDHCI driver for Tegra");
3e44a1a7	453	MODULE_AUTHOR("Google, Inc.");
85d6509d	454	MODULE_LICENSE("GPL v2");