]>
Commit | Line | Data |
---|---|---|
06c8b667 HZ |
1 | /* |
2 | * PHY support for Xenon SDHC | |
3 | * | |
4 | * Copyright (C) 2016 Marvell, All Rights Reserved. | |
5 | * | |
6 | * Author: Hu Ziji <huziji@marvell.com> | |
7 | * Date: 2016-8-24 | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or | |
10 | * modify it under the terms of the GNU General Public License as | |
11 | * published by the Free Software Foundation version 2. | |
12 | */ | |
13 | ||
14 | #include <linux/slab.h> | |
15 | #include <linux/delay.h> | |
16 | #include <linux/ktime.h> | |
17 | #include <linux/of_address.h> | |
18 | ||
19 | #include "sdhci-pltfm.h" | |
20 | #include "sdhci-xenon.h" | |
21 | ||
22 | /* Register base for eMMC PHY 5.0 Version */ | |
23 | #define XENON_EMMC_5_0_PHY_REG_BASE 0x0160 | |
24 | /* Register base for eMMC PHY 5.1 Version */ | |
25 | #define XENON_EMMC_PHY_REG_BASE 0x0170 | |
26 | ||
27 | #define XENON_EMMC_PHY_TIMING_ADJUST XENON_EMMC_PHY_REG_BASE | |
28 | #define XENON_EMMC_5_0_PHY_TIMING_ADJUST XENON_EMMC_5_0_PHY_REG_BASE | |
29 | #define XENON_TIMING_ADJUST_SLOW_MODE BIT(29) | |
30 | #define XENON_TIMING_ADJUST_SDIO_MODE BIT(28) | |
31 | #define XENON_SAMPL_INV_QSP_PHASE_SELECT BIT(18) | |
32 | #define XENON_SAMPL_INV_QSP_PHASE_SELECT_SHIFT 18 | |
33 | #define XENON_PHY_INITIALIZAION BIT(31) | |
34 | #define XENON_WAIT_CYCLE_BEFORE_USING_MASK 0xF | |
35 | #define XENON_WAIT_CYCLE_BEFORE_USING_SHIFT 12 | |
36 | #define XENON_FC_SYNC_EN_DURATION_MASK 0xF | |
37 | #define XENON_FC_SYNC_EN_DURATION_SHIFT 8 | |
38 | #define XENON_FC_SYNC_RST_EN_DURATION_MASK 0xF | |
39 | #define XENON_FC_SYNC_RST_EN_DURATION_SHIFT 4 | |
40 | #define XENON_FC_SYNC_RST_DURATION_MASK 0xF | |
41 | #define XENON_FC_SYNC_RST_DURATION_SHIFT 0 | |
42 | ||
43 | #define XENON_EMMC_PHY_FUNC_CONTROL (XENON_EMMC_PHY_REG_BASE + 0x4) | |
44 | #define XENON_EMMC_5_0_PHY_FUNC_CONTROL \ | |
45 | (XENON_EMMC_5_0_PHY_REG_BASE + 0x4) | |
46 | #define XENON_ASYNC_DDRMODE_MASK BIT(23) | |
47 | #define XENON_ASYNC_DDRMODE_SHIFT 23 | |
48 | #define XENON_CMD_DDR_MODE BIT(16) | |
49 | #define XENON_DQ_DDR_MODE_SHIFT 8 | |
50 | #define XENON_DQ_DDR_MODE_MASK 0xFF | |
51 | #define XENON_DQ_ASYNC_MODE BIT(4) | |
52 | ||
53 | #define XENON_EMMC_PHY_PAD_CONTROL (XENON_EMMC_PHY_REG_BASE + 0x8) | |
54 | #define XENON_EMMC_5_0_PHY_PAD_CONTROL \ | |
55 | (XENON_EMMC_5_0_PHY_REG_BASE + 0x8) | |
56 | #define XENON_REC_EN_SHIFT 24 | |
57 | #define XENON_REC_EN_MASK 0xF | |
58 | #define XENON_FC_DQ_RECEN BIT(24) | |
59 | #define XENON_FC_CMD_RECEN BIT(25) | |
60 | #define XENON_FC_QSP_RECEN BIT(26) | |
61 | #define XENON_FC_QSN_RECEN BIT(27) | |
62 | #define XENON_OEN_QSN BIT(28) | |
63 | #define XENON_AUTO_RECEN_CTRL BIT(30) | |
64 | #define XENON_FC_ALL_CMOS_RECEIVER 0xF000 | |
65 | ||
66 | #define XENON_EMMC5_FC_QSP_PD BIT(18) | |
67 | #define XENON_EMMC5_FC_QSP_PU BIT(22) | |
68 | #define XENON_EMMC5_FC_CMD_PD BIT(17) | |
69 | #define XENON_EMMC5_FC_CMD_PU BIT(21) | |
70 | #define XENON_EMMC5_FC_DQ_PD BIT(16) | |
71 | #define XENON_EMMC5_FC_DQ_PU BIT(20) | |
72 | ||
73 | #define XENON_EMMC_PHY_PAD_CONTROL1 (XENON_EMMC_PHY_REG_BASE + 0xC) | |
74 | #define XENON_EMMC5_1_FC_QSP_PD BIT(9) | |
75 | #define XENON_EMMC5_1_FC_QSP_PU BIT(25) | |
76 | #define XENON_EMMC5_1_FC_CMD_PD BIT(8) | |
77 | #define XENON_EMMC5_1_FC_CMD_PU BIT(24) | |
78 | #define XENON_EMMC5_1_FC_DQ_PD 0xFF | |
79 | #define XENON_EMMC5_1_FC_DQ_PU (0xFF << 16) | |
80 | ||
81 | #define XENON_EMMC_PHY_PAD_CONTROL2 (XENON_EMMC_PHY_REG_BASE + 0x10) | |
82 | #define XENON_EMMC_5_0_PHY_PAD_CONTROL2 \ | |
83 | (XENON_EMMC_5_0_PHY_REG_BASE + 0xC) | |
84 | #define XENON_ZNR_MASK 0x1F | |
85 | #define XENON_ZNR_SHIFT 8 | |
86 | #define XENON_ZPR_MASK 0x1F | |
87 | /* Preferred ZNR and ZPR value vary between different boards. | |
88 | * The specific ZNR and ZPR value should be defined here | |
89 | * according to board actual timing. | |
90 | */ | |
91 | #define XENON_ZNR_DEF_VALUE 0xF | |
92 | #define XENON_ZPR_DEF_VALUE 0xF | |
93 | ||
94 | #define XENON_EMMC_PHY_DLL_CONTROL (XENON_EMMC_PHY_REG_BASE + 0x14) | |
95 | #define XENON_EMMC_5_0_PHY_DLL_CONTROL \ | |
96 | (XENON_EMMC_5_0_PHY_REG_BASE + 0x10) | |
97 | #define XENON_DLL_ENABLE BIT(31) | |
98 | #define XENON_DLL_UPDATE_STROBE_5_0 BIT(30) | |
99 | #define XENON_DLL_REFCLK_SEL BIT(30) | |
100 | #define XENON_DLL_UPDATE BIT(23) | |
101 | #define XENON_DLL_PHSEL1_SHIFT 24 | |
102 | #define XENON_DLL_PHSEL0_SHIFT 16 | |
103 | #define XENON_DLL_PHASE_MASK 0x3F | |
104 | #define XENON_DLL_PHASE_90_DEGREE 0x1F | |
105 | #define XENON_DLL_FAST_LOCK BIT(5) | |
106 | #define XENON_DLL_GAIN2X BIT(3) | |
107 | #define XENON_DLL_BYPASS_EN BIT(0) | |
108 | ||
109 | #define XENON_EMMC_5_0_PHY_LOGIC_TIMING_ADJUST \ | |
110 | (XENON_EMMC_5_0_PHY_REG_BASE + 0x14) | |
a04b9b47 | 111 | #define XENON_EMMC_5_0_PHY_LOGIC_TIMING_VALUE 0x5A54 |
06c8b667 HZ |
112 | #define XENON_EMMC_PHY_LOGIC_TIMING_ADJUST (XENON_EMMC_PHY_REG_BASE + 0x18) |
113 | #define XENON_LOGIC_TIMING_VALUE 0x00AA8977 | |
114 | ||
115 | /* | |
116 | * List offset of PHY registers and some special register values | |
117 | * in eMMC PHY 5.0 or eMMC PHY 5.1 | |
118 | */ | |
119 | struct xenon_emmc_phy_regs { | |
120 | /* Offset of Timing Adjust register */ | |
121 | u16 timing_adj; | |
122 | /* Offset of Func Control register */ | |
123 | u16 func_ctrl; | |
124 | /* Offset of Pad Control register */ | |
125 | u16 pad_ctrl; | |
126 | /* Offset of Pad Control register 2 */ | |
127 | u16 pad_ctrl2; | |
128 | /* Offset of DLL Control register */ | |
129 | u16 dll_ctrl; | |
130 | /* Offset of Logic Timing Adjust register */ | |
131 | u16 logic_timing_adj; | |
132 | /* DLL Update Enable bit */ | |
133 | u32 dll_update; | |
a04b9b47 HZ |
134 | /* value in Logic Timing Adjustment register */ |
135 | u32 logic_timing_val; | |
06c8b667 HZ |
136 | }; |
137 | ||
138 | static const char * const phy_types[] = { | |
139 | "emmc 5.0 phy", | |
140 | "emmc 5.1 phy" | |
141 | }; | |
142 | ||
143 | enum xenon_phy_type_enum { | |
144 | EMMC_5_0_PHY, | |
145 | EMMC_5_1_PHY, | |
146 | NR_PHY_TYPES | |
147 | }; | |
148 | ||
298269c6 HZ |
149 | enum soc_pad_ctrl_type { |
150 | SOC_PAD_SD, | |
151 | SOC_PAD_FIXED_1_8V, | |
152 | }; | |
153 | ||
154 | struct soc_pad_ctrl { | |
155 | /* Register address of SoC PHY PAD ctrl */ | |
156 | void __iomem *reg; | |
157 | /* SoC PHY PAD ctrl type */ | |
158 | enum soc_pad_ctrl_type pad_type; | |
159 | /* SoC specific operation to set SoC PHY PAD */ | |
160 | void (*set_soc_pad)(struct sdhci_host *host, | |
161 | unsigned char signal_voltage); | |
162 | }; | |
163 | ||
06c8b667 HZ |
164 | static struct xenon_emmc_phy_regs xenon_emmc_5_0_phy_regs = { |
165 | .timing_adj = XENON_EMMC_5_0_PHY_TIMING_ADJUST, | |
166 | .func_ctrl = XENON_EMMC_5_0_PHY_FUNC_CONTROL, | |
167 | .pad_ctrl = XENON_EMMC_5_0_PHY_PAD_CONTROL, | |
168 | .pad_ctrl2 = XENON_EMMC_5_0_PHY_PAD_CONTROL2, | |
169 | .dll_ctrl = XENON_EMMC_5_0_PHY_DLL_CONTROL, | |
170 | .logic_timing_adj = XENON_EMMC_5_0_PHY_LOGIC_TIMING_ADJUST, | |
171 | .dll_update = XENON_DLL_UPDATE_STROBE_5_0, | |
a04b9b47 | 172 | .logic_timing_val = XENON_EMMC_5_0_PHY_LOGIC_TIMING_VALUE, |
06c8b667 HZ |
173 | }; |
174 | ||
175 | static struct xenon_emmc_phy_regs xenon_emmc_5_1_phy_regs = { | |
176 | .timing_adj = XENON_EMMC_PHY_TIMING_ADJUST, | |
177 | .func_ctrl = XENON_EMMC_PHY_FUNC_CONTROL, | |
178 | .pad_ctrl = XENON_EMMC_PHY_PAD_CONTROL, | |
179 | .pad_ctrl2 = XENON_EMMC_PHY_PAD_CONTROL2, | |
180 | .dll_ctrl = XENON_EMMC_PHY_DLL_CONTROL, | |
181 | .logic_timing_adj = XENON_EMMC_PHY_LOGIC_TIMING_ADJUST, | |
182 | .dll_update = XENON_DLL_UPDATE, | |
a04b9b47 | 183 | .logic_timing_val = XENON_LOGIC_TIMING_VALUE, |
06c8b667 HZ |
184 | }; |
185 | ||
186 | /* | |
187 | * eMMC PHY configuration and operations | |
188 | */ | |
189 | struct xenon_emmc_phy_params { | |
190 | bool slow_mode; | |
191 | ||
192 | u8 znr; | |
193 | u8 zpr; | |
194 | ||
195 | /* Nr of consecutive Sampling Points of a Valid Sampling Window */ | |
196 | u8 nr_tun_times; | |
197 | /* Divider for calculating Tuning Step */ | |
198 | u8 tun_step_divider; | |
298269c6 HZ |
199 | |
200 | struct soc_pad_ctrl pad_ctrl; | |
06c8b667 HZ |
201 | }; |
202 | ||
203 | static int xenon_alloc_emmc_phy(struct sdhci_host *host) | |
204 | { | |
205 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
206 | struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host); | |
207 | struct xenon_emmc_phy_params *params; | |
208 | ||
209 | params = devm_kzalloc(mmc_dev(host->mmc), sizeof(*params), GFP_KERNEL); | |
210 | if (!params) | |
211 | return -ENOMEM; | |
212 | ||
213 | priv->phy_params = params; | |
214 | if (priv->phy_type == EMMC_5_0_PHY) | |
215 | priv->emmc_phy_regs = &xenon_emmc_5_0_phy_regs; | |
216 | else | |
217 | priv->emmc_phy_regs = &xenon_emmc_5_1_phy_regs; | |
218 | ||
219 | return 0; | |
220 | } | |
221 | ||
222 | /* | |
223 | * eMMC 5.0/5.1 PHY init/re-init. | |
224 | * eMMC PHY init should be executed after: | |
225 | * 1. SDCLK frequency changes. | |
226 | * 2. SDCLK is stopped and re-enabled. | |
227 | * 3. config in emmc_phy_regs->timing_adj and emmc_phy_regs->func_ctrl | |
228 | * are changed | |
229 | */ | |
230 | static int xenon_emmc_phy_init(struct sdhci_host *host) | |
231 | { | |
232 | u32 reg; | |
233 | u32 wait, clock; | |
234 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
235 | struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host); | |
236 | struct xenon_emmc_phy_regs *phy_regs = priv->emmc_phy_regs; | |
237 | ||
238 | reg = sdhci_readl(host, phy_regs->timing_adj); | |
239 | reg |= XENON_PHY_INITIALIZAION; | |
240 | sdhci_writel(host, reg, phy_regs->timing_adj); | |
241 | ||
242 | /* Add duration of FC_SYNC_RST */ | |
243 | wait = ((reg >> XENON_FC_SYNC_RST_DURATION_SHIFT) & | |
244 | XENON_FC_SYNC_RST_DURATION_MASK); | |
245 | /* Add interval between FC_SYNC_EN and FC_SYNC_RST */ | |
246 | wait += ((reg >> XENON_FC_SYNC_RST_EN_DURATION_SHIFT) & | |
247 | XENON_FC_SYNC_RST_EN_DURATION_MASK); | |
248 | /* Add duration of asserting FC_SYNC_EN */ | |
249 | wait += ((reg >> XENON_FC_SYNC_EN_DURATION_SHIFT) & | |
250 | XENON_FC_SYNC_EN_DURATION_MASK); | |
251 | /* Add duration of waiting for PHY */ | |
252 | wait += ((reg >> XENON_WAIT_CYCLE_BEFORE_USING_SHIFT) & | |
253 | XENON_WAIT_CYCLE_BEFORE_USING_MASK); | |
254 | /* 4 additional bus clock and 4 AXI bus clock are required */ | |
255 | wait += 8; | |
256 | wait <<= 20; | |
257 | ||
258 | clock = host->clock; | |
259 | if (!clock) | |
260 | /* Use the possibly slowest bus frequency value */ | |
261 | clock = XENON_LOWEST_SDCLK_FREQ; | |
262 | /* get the wait time */ | |
263 | wait /= clock; | |
264 | wait++; | |
265 | /* wait for host eMMC PHY init completes */ | |
266 | udelay(wait); | |
267 | ||
268 | reg = sdhci_readl(host, phy_regs->timing_adj); | |
269 | reg &= XENON_PHY_INITIALIZAION; | |
270 | if (reg) { | |
271 | dev_err(mmc_dev(host->mmc), "eMMC PHY init cannot complete after %d us\n", | |
272 | wait); | |
273 | return -ETIMEDOUT; | |
274 | } | |
275 | ||
276 | return 0; | |
277 | } | |
278 | ||
298269c6 HZ |
279 | #define ARMADA_3700_SOC_PAD_1_8V 0x1 |
280 | #define ARMADA_3700_SOC_PAD_3_3V 0x0 | |
281 | ||
282 | static void armada_3700_soc_pad_voltage_set(struct sdhci_host *host, | |
283 | unsigned char signal_voltage) | |
284 | { | |
285 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
286 | struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host); | |
287 | struct xenon_emmc_phy_params *params = priv->phy_params; | |
288 | ||
289 | if (params->pad_ctrl.pad_type == SOC_PAD_FIXED_1_8V) { | |
290 | writel(ARMADA_3700_SOC_PAD_1_8V, params->pad_ctrl.reg); | |
291 | } else if (params->pad_ctrl.pad_type == SOC_PAD_SD) { | |
292 | if (signal_voltage == MMC_SIGNAL_VOLTAGE_180) | |
293 | writel(ARMADA_3700_SOC_PAD_1_8V, params->pad_ctrl.reg); | |
294 | else if (signal_voltage == MMC_SIGNAL_VOLTAGE_330) | |
295 | writel(ARMADA_3700_SOC_PAD_3_3V, params->pad_ctrl.reg); | |
296 | } | |
297 | } | |
298 | ||
299 | /* | |
300 | * Set SoC PHY voltage PAD control register, | |
301 | * according to the operation voltage on PAD. | |
302 | * The detailed operation depends on SoC implementation. | |
303 | */ | |
304 | static void xenon_emmc_phy_set_soc_pad(struct sdhci_host *host, | |
305 | unsigned char signal_voltage) | |
306 | { | |
307 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
308 | struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host); | |
309 | struct xenon_emmc_phy_params *params = priv->phy_params; | |
310 | ||
311 | if (!params->pad_ctrl.reg) | |
312 | return; | |
313 | ||
314 | if (params->pad_ctrl.set_soc_pad) | |
315 | params->pad_ctrl.set_soc_pad(host, signal_voltage); | |
316 | } | |
317 | ||
06c8b667 HZ |
318 | /* |
319 | * Enable eMMC PHY HW DLL | |
320 | * DLL should be enabled and stable before HS200/SDR104 tuning, | |
321 | * and before HS400 data strobe setting. | |
322 | */ | |
323 | static int xenon_emmc_phy_enable_dll(struct sdhci_host *host) | |
324 | { | |
325 | u32 reg; | |
326 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
327 | struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host); | |
328 | struct xenon_emmc_phy_regs *phy_regs = priv->emmc_phy_regs; | |
329 | ktime_t timeout; | |
330 | ||
331 | if (WARN_ON(host->clock <= MMC_HIGH_52_MAX_DTR)) | |
332 | return -EINVAL; | |
333 | ||
334 | reg = sdhci_readl(host, phy_regs->dll_ctrl); | |
335 | if (reg & XENON_DLL_ENABLE) | |
336 | return 0; | |
337 | ||
338 | /* Enable DLL */ | |
339 | reg = sdhci_readl(host, phy_regs->dll_ctrl); | |
340 | reg |= (XENON_DLL_ENABLE | XENON_DLL_FAST_LOCK); | |
341 | ||
342 | /* | |
343 | * Set Phase as 90 degree, which is most common value. | |
344 | * Might set another value if necessary. | |
345 | * The granularity is 1 degree. | |
346 | */ | |
347 | reg &= ~((XENON_DLL_PHASE_MASK << XENON_DLL_PHSEL0_SHIFT) | | |
348 | (XENON_DLL_PHASE_MASK << XENON_DLL_PHSEL1_SHIFT)); | |
349 | reg |= ((XENON_DLL_PHASE_90_DEGREE << XENON_DLL_PHSEL0_SHIFT) | | |
350 | (XENON_DLL_PHASE_90_DEGREE << XENON_DLL_PHSEL1_SHIFT)); | |
351 | ||
352 | reg &= ~XENON_DLL_BYPASS_EN; | |
353 | reg |= phy_regs->dll_update; | |
354 | if (priv->phy_type == EMMC_5_1_PHY) | |
355 | reg &= ~XENON_DLL_REFCLK_SEL; | |
356 | sdhci_writel(host, reg, phy_regs->dll_ctrl); | |
357 | ||
358 | /* Wait max 32 ms */ | |
359 | timeout = ktime_add_ms(ktime_get(), 32); | |
360 | while (!(sdhci_readw(host, XENON_SLOT_EXT_PRESENT_STATE) & | |
361 | XENON_DLL_LOCK_STATE)) { | |
362 | if (ktime_after(ktime_get(), timeout)) { | |
363 | dev_err(mmc_dev(host->mmc), "Wait for DLL Lock time-out\n"); | |
364 | return -ETIMEDOUT; | |
365 | } | |
366 | udelay(100); | |
367 | } | |
368 | return 0; | |
369 | } | |
370 | ||
371 | /* | |
372 | * Config to eMMC PHY to prepare for tuning. | |
373 | * Enable HW DLL and set the TUNING_STEP | |
374 | */ | |
375 | static int xenon_emmc_phy_config_tuning(struct sdhci_host *host) | |
376 | { | |
377 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
378 | struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host); | |
379 | struct xenon_emmc_phy_params *params = priv->phy_params; | |
380 | u32 reg, tuning_step; | |
381 | int ret; | |
382 | ||
383 | if (host->clock <= MMC_HIGH_52_MAX_DTR) | |
384 | return -EINVAL; | |
385 | ||
386 | ret = xenon_emmc_phy_enable_dll(host); | |
387 | if (ret) | |
388 | return ret; | |
389 | ||
390 | /* Achieve TUNING_STEP with HW DLL help */ | |
391 | reg = sdhci_readl(host, XENON_SLOT_DLL_CUR_DLY_VAL); | |
392 | tuning_step = reg / params->tun_step_divider; | |
393 | if (unlikely(tuning_step > XENON_TUNING_STEP_MASK)) { | |
394 | dev_warn(mmc_dev(host->mmc), | |
395 | "HS200 TUNING_STEP %d is larger than MAX value\n", | |
396 | tuning_step); | |
397 | tuning_step = XENON_TUNING_STEP_MASK; | |
398 | } | |
399 | ||
400 | /* Set TUNING_STEP for later tuning */ | |
401 | reg = sdhci_readl(host, XENON_SLOT_OP_STATUS_CTRL); | |
402 | reg &= ~(XENON_TUN_CONSECUTIVE_TIMES_MASK << | |
403 | XENON_TUN_CONSECUTIVE_TIMES_SHIFT); | |
404 | reg |= (params->nr_tun_times << XENON_TUN_CONSECUTIVE_TIMES_SHIFT); | |
405 | reg &= ~(XENON_TUNING_STEP_MASK << XENON_TUNING_STEP_SHIFT); | |
406 | reg |= (tuning_step << XENON_TUNING_STEP_SHIFT); | |
407 | sdhci_writel(host, reg, XENON_SLOT_OP_STATUS_CTRL); | |
408 | ||
409 | return 0; | |
410 | } | |
411 | ||
412 | static void xenon_emmc_phy_disable_data_strobe(struct sdhci_host *host) | |
413 | { | |
414 | u32 reg; | |
415 | ||
416 | /* Disable SDHC Data Strobe */ | |
417 | reg = sdhci_readl(host, XENON_SLOT_EMMC_CTRL); | |
418 | reg &= ~XENON_ENABLE_DATA_STROBE; | |
419 | sdhci_writel(host, reg, XENON_SLOT_EMMC_CTRL); | |
420 | } | |
421 | ||
422 | /* Set HS400 Data Strobe */ | |
423 | static void xenon_emmc_phy_strobe_delay_adj(struct sdhci_host *host) | |
424 | { | |
425 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
426 | struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host); | |
427 | u32 reg; | |
428 | ||
429 | if (WARN_ON(host->timing != MMC_TIMING_MMC_HS400)) | |
430 | return; | |
431 | ||
432 | if (host->clock <= MMC_HIGH_52_MAX_DTR) | |
433 | return; | |
434 | ||
435 | dev_dbg(mmc_dev(host->mmc), "starts HS400 strobe delay adjustment\n"); | |
436 | ||
437 | xenon_emmc_phy_enable_dll(host); | |
438 | ||
439 | /* Enable SDHC Data Strobe */ | |
440 | reg = sdhci_readl(host, XENON_SLOT_EMMC_CTRL); | |
441 | reg |= XENON_ENABLE_DATA_STROBE; | |
442 | sdhci_writel(host, reg, XENON_SLOT_EMMC_CTRL); | |
443 | ||
444 | /* Set Data Strobe Pull down */ | |
445 | if (priv->phy_type == EMMC_5_0_PHY) { | |
446 | reg = sdhci_readl(host, XENON_EMMC_5_0_PHY_PAD_CONTROL); | |
447 | reg |= XENON_EMMC5_FC_QSP_PD; | |
448 | reg &= ~XENON_EMMC5_FC_QSP_PU; | |
449 | sdhci_writel(host, reg, XENON_EMMC_5_0_PHY_PAD_CONTROL); | |
450 | } else { | |
451 | reg = sdhci_readl(host, XENON_EMMC_PHY_PAD_CONTROL1); | |
452 | reg |= XENON_EMMC5_1_FC_QSP_PD; | |
453 | reg &= ~XENON_EMMC5_1_FC_QSP_PU; | |
454 | sdhci_writel(host, reg, XENON_EMMC_PHY_PAD_CONTROL1); | |
455 | } | |
456 | } | |
457 | ||
458 | /* | |
459 | * If eMMC PHY Slow Mode is required in lower speed mode (SDCLK < 55MHz) | |
460 | * in SDR mode, enable Slow Mode to bypass eMMC PHY. | |
461 | * SDIO slower SDR mode also requires Slow Mode. | |
462 | * | |
463 | * If Slow Mode is enabled, return true. | |
464 | * Otherwise, return false. | |
465 | */ | |
466 | static bool xenon_emmc_phy_slow_mode(struct sdhci_host *host, | |
467 | unsigned char timing) | |
468 | { | |
469 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
470 | struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host); | |
471 | struct xenon_emmc_phy_params *params = priv->phy_params; | |
472 | struct xenon_emmc_phy_regs *phy_regs = priv->emmc_phy_regs; | |
473 | u32 reg; | |
474 | int ret; | |
475 | ||
476 | if (host->clock > MMC_HIGH_52_MAX_DTR) | |
477 | return false; | |
478 | ||
479 | reg = sdhci_readl(host, phy_regs->timing_adj); | |
480 | /* When in slower SDR mode, enable Slow Mode for SDIO | |
481 | * or when Slow Mode flag is set | |
482 | */ | |
483 | switch (timing) { | |
484 | case MMC_TIMING_LEGACY: | |
485 | /* | |
486 | * If Slow Mode is required, enable Slow Mode by default | |
487 | * in early init phase to avoid any potential issue. | |
488 | */ | |
489 | if (params->slow_mode) { | |
490 | reg |= XENON_TIMING_ADJUST_SLOW_MODE; | |
491 | ret = true; | |
492 | } else { | |
493 | reg &= ~XENON_TIMING_ADJUST_SLOW_MODE; | |
494 | ret = false; | |
495 | } | |
496 | break; | |
497 | case MMC_TIMING_UHS_SDR25: | |
498 | case MMC_TIMING_UHS_SDR12: | |
499 | case MMC_TIMING_SD_HS: | |
500 | case MMC_TIMING_MMC_HS: | |
501 | if ((priv->init_card_type == MMC_TYPE_SDIO) || | |
502 | params->slow_mode) { | |
503 | reg |= XENON_TIMING_ADJUST_SLOW_MODE; | |
504 | ret = true; | |
505 | break; | |
506 | } | |
507 | default: | |
508 | reg &= ~XENON_TIMING_ADJUST_SLOW_MODE; | |
509 | ret = false; | |
510 | } | |
511 | ||
512 | sdhci_writel(host, reg, phy_regs->timing_adj); | |
513 | return ret; | |
514 | } | |
515 | ||
516 | /* | |
517 | * Set-up eMMC 5.0/5.1 PHY. | |
518 | * Specific configuration depends on the current speed mode in use. | |
519 | */ | |
520 | static void xenon_emmc_phy_set(struct sdhci_host *host, | |
521 | unsigned char timing) | |
522 | { | |
523 | u32 reg; | |
524 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
525 | struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host); | |
526 | struct xenon_emmc_phy_params *params = priv->phy_params; | |
527 | struct xenon_emmc_phy_regs *phy_regs = priv->emmc_phy_regs; | |
528 | ||
529 | dev_dbg(mmc_dev(host->mmc), "eMMC PHY setting starts\n"); | |
530 | ||
531 | /* Setup pad, set bit[28] and bits[26:24] */ | |
532 | reg = sdhci_readl(host, phy_regs->pad_ctrl); | |
533 | reg |= (XENON_FC_DQ_RECEN | XENON_FC_CMD_RECEN | | |
534 | XENON_FC_QSP_RECEN | XENON_OEN_QSN); | |
535 | /* All FC_XX_RECEIVCE should be set as CMOS Type */ | |
536 | reg |= XENON_FC_ALL_CMOS_RECEIVER; | |
537 | sdhci_writel(host, reg, phy_regs->pad_ctrl); | |
538 | ||
539 | /* Set CMD and DQ Pull Up */ | |
540 | if (priv->phy_type == EMMC_5_0_PHY) { | |
541 | reg = sdhci_readl(host, XENON_EMMC_5_0_PHY_PAD_CONTROL); | |
542 | reg |= (XENON_EMMC5_FC_CMD_PU | XENON_EMMC5_FC_DQ_PU); | |
543 | reg &= ~(XENON_EMMC5_FC_CMD_PD | XENON_EMMC5_FC_DQ_PD); | |
544 | sdhci_writel(host, reg, XENON_EMMC_5_0_PHY_PAD_CONTROL); | |
545 | } else { | |
546 | reg = sdhci_readl(host, XENON_EMMC_PHY_PAD_CONTROL1); | |
547 | reg |= (XENON_EMMC5_1_FC_CMD_PU | XENON_EMMC5_1_FC_DQ_PU); | |
548 | reg &= ~(XENON_EMMC5_1_FC_CMD_PD | XENON_EMMC5_1_FC_DQ_PD); | |
549 | sdhci_writel(host, reg, XENON_EMMC_PHY_PAD_CONTROL1); | |
550 | } | |
551 | ||
552 | if (timing == MMC_TIMING_LEGACY) { | |
553 | xenon_emmc_phy_slow_mode(host, timing); | |
554 | goto phy_init; | |
555 | } | |
556 | ||
557 | /* | |
558 | * If SDIO card, set SDIO Mode | |
559 | * Otherwise, clear SDIO Mode | |
560 | */ | |
561 | reg = sdhci_readl(host, phy_regs->timing_adj); | |
562 | if (priv->init_card_type == MMC_TYPE_SDIO) | |
563 | reg |= XENON_TIMING_ADJUST_SDIO_MODE; | |
564 | else | |
565 | reg &= ~XENON_TIMING_ADJUST_SDIO_MODE; | |
566 | sdhci_writel(host, reg, phy_regs->timing_adj); | |
567 | ||
568 | if (xenon_emmc_phy_slow_mode(host, timing)) | |
569 | goto phy_init; | |
570 | ||
571 | /* | |
572 | * Set preferred ZNR and ZPR value | |
573 | * The ZNR and ZPR value vary between different boards. | |
574 | * Define them both in sdhci-xenon-emmc-phy.h. | |
575 | */ | |
576 | reg = sdhci_readl(host, phy_regs->pad_ctrl2); | |
577 | reg &= ~((XENON_ZNR_MASK << XENON_ZNR_SHIFT) | XENON_ZPR_MASK); | |
578 | reg |= ((params->znr << XENON_ZNR_SHIFT) | params->zpr); | |
579 | sdhci_writel(host, reg, phy_regs->pad_ctrl2); | |
580 | ||
581 | /* | |
582 | * When setting EMMC_PHY_FUNC_CONTROL register, | |
583 | * SD clock should be disabled | |
584 | */ | |
585 | reg = sdhci_readl(host, SDHCI_CLOCK_CONTROL); | |
586 | reg &= ~SDHCI_CLOCK_CARD_EN; | |
587 | sdhci_writew(host, reg, SDHCI_CLOCK_CONTROL); | |
588 | ||
589 | reg = sdhci_readl(host, phy_regs->func_ctrl); | |
590 | switch (timing) { | |
591 | case MMC_TIMING_MMC_HS400: | |
592 | reg |= (XENON_DQ_DDR_MODE_MASK << XENON_DQ_DDR_MODE_SHIFT) | | |
593 | XENON_CMD_DDR_MODE; | |
594 | reg &= ~XENON_DQ_ASYNC_MODE; | |
595 | break; | |
596 | case MMC_TIMING_UHS_DDR50: | |
597 | case MMC_TIMING_MMC_DDR52: | |
598 | reg |= (XENON_DQ_DDR_MODE_MASK << XENON_DQ_DDR_MODE_SHIFT) | | |
599 | XENON_CMD_DDR_MODE | XENON_DQ_ASYNC_MODE; | |
600 | break; | |
601 | default: | |
602 | reg &= ~((XENON_DQ_DDR_MODE_MASK << XENON_DQ_DDR_MODE_SHIFT) | | |
603 | XENON_CMD_DDR_MODE); | |
604 | reg |= XENON_DQ_ASYNC_MODE; | |
605 | } | |
606 | sdhci_writel(host, reg, phy_regs->func_ctrl); | |
607 | ||
608 | /* Enable bus clock */ | |
609 | reg = sdhci_readl(host, SDHCI_CLOCK_CONTROL); | |
610 | reg |= SDHCI_CLOCK_CARD_EN; | |
611 | sdhci_writew(host, reg, SDHCI_CLOCK_CONTROL); | |
612 | ||
613 | if (timing == MMC_TIMING_MMC_HS400) | |
614 | /* Hardware team recommend a value for HS400 */ | |
a04b9b47 | 615 | sdhci_writel(host, phy_regs->logic_timing_val, |
06c8b667 HZ |
616 | phy_regs->logic_timing_adj); |
617 | else | |
618 | xenon_emmc_phy_disable_data_strobe(host); | |
619 | ||
620 | phy_init: | |
621 | xenon_emmc_phy_init(host); | |
622 | ||
623 | dev_dbg(mmc_dev(host->mmc), "eMMC PHY setting completes\n"); | |
624 | } | |
625 | ||
298269c6 HZ |
626 | static int get_dt_pad_ctrl_data(struct sdhci_host *host, |
627 | struct device_node *np, | |
628 | struct xenon_emmc_phy_params *params) | |
629 | { | |
630 | int ret = 0; | |
631 | const char *name; | |
632 | struct resource iomem; | |
633 | ||
634 | if (of_device_is_compatible(np, "marvell,armada-3700-sdhci")) | |
635 | params->pad_ctrl.set_soc_pad = armada_3700_soc_pad_voltage_set; | |
636 | else | |
637 | return 0; | |
638 | ||
639 | if (of_address_to_resource(np, 1, &iomem)) { | |
640 | dev_err(mmc_dev(host->mmc), "Unable to find SoC PAD ctrl register address for %s\n", | |
641 | np->name); | |
642 | return -EINVAL; | |
643 | } | |
644 | ||
645 | params->pad_ctrl.reg = devm_ioremap_resource(mmc_dev(host->mmc), | |
646 | &iomem); | |
e6e267b0 | 647 | if (IS_ERR(params->pad_ctrl.reg)) |
298269c6 | 648 | return PTR_ERR(params->pad_ctrl.reg); |
298269c6 HZ |
649 | |
650 | ret = of_property_read_string(np, "marvell,pad-type", &name); | |
651 | if (ret) { | |
652 | dev_err(mmc_dev(host->mmc), "Unable to determine SoC PHY PAD ctrl type\n"); | |
653 | return ret; | |
654 | } | |
655 | if (!strcmp(name, "sd")) { | |
656 | params->pad_ctrl.pad_type = SOC_PAD_SD; | |
657 | } else if (!strcmp(name, "fixed-1-8v")) { | |
658 | params->pad_ctrl.pad_type = SOC_PAD_FIXED_1_8V; | |
659 | } else { | |
660 | dev_err(mmc_dev(host->mmc), "Unsupported SoC PHY PAD ctrl type %s\n", | |
661 | name); | |
662 | return -EINVAL; | |
663 | } | |
664 | ||
665 | return ret; | |
666 | } | |
667 | ||
06c8b667 HZ |
668 | static int xenon_emmc_phy_parse_param_dt(struct sdhci_host *host, |
669 | struct device_node *np, | |
670 | struct xenon_emmc_phy_params *params) | |
671 | { | |
672 | u32 value; | |
673 | ||
674 | params->slow_mode = false; | |
675 | if (of_property_read_bool(np, "marvell,xenon-phy-slow-mode")) | |
676 | params->slow_mode = true; | |
677 | ||
678 | params->znr = XENON_ZNR_DEF_VALUE; | |
679 | if (!of_property_read_u32(np, "marvell,xenon-phy-znr", &value)) | |
680 | params->znr = value & XENON_ZNR_MASK; | |
681 | ||
682 | params->zpr = XENON_ZPR_DEF_VALUE; | |
683 | if (!of_property_read_u32(np, "marvell,xenon-phy-zpr", &value)) | |
684 | params->zpr = value & XENON_ZPR_MASK; | |
685 | ||
686 | params->nr_tun_times = XENON_TUN_CONSECUTIVE_TIMES; | |
687 | if (!of_property_read_u32(np, "marvell,xenon-phy-nr-success-tun", | |
688 | &value)) | |
689 | params->nr_tun_times = value & XENON_TUN_CONSECUTIVE_TIMES_MASK; | |
690 | ||
691 | params->tun_step_divider = XENON_TUNING_STEP_DIVIDER; | |
692 | if (!of_property_read_u32(np, "marvell,xenon-phy-tun-step-divider", | |
693 | &value)) | |
694 | params->tun_step_divider = value & 0xFF; | |
695 | ||
298269c6 HZ |
696 | return get_dt_pad_ctrl_data(host, np, params); |
697 | } | |
698 | ||
699 | /* Set SoC PHY Voltage PAD */ | |
700 | void xenon_soc_pad_ctrl(struct sdhci_host *host, | |
701 | unsigned char signal_voltage) | |
702 | { | |
703 | xenon_emmc_phy_set_soc_pad(host, signal_voltage); | |
06c8b667 HZ |
704 | } |
705 | ||
706 | /* | |
707 | * Setting PHY when card is working in High Speed Mode. | |
708 | * HS400 set data strobe line. | |
709 | * HS200/SDR104 set tuning config to prepare for tuning. | |
710 | */ | |
711 | static int xenon_hs_delay_adj(struct sdhci_host *host) | |
712 | { | |
713 | int ret = 0; | |
714 | ||
715 | if (WARN_ON(host->clock <= XENON_DEFAULT_SDCLK_FREQ)) | |
716 | return -EINVAL; | |
717 | ||
718 | switch (host->timing) { | |
719 | case MMC_TIMING_MMC_HS400: | |
720 | xenon_emmc_phy_strobe_delay_adj(host); | |
721 | return 0; | |
722 | case MMC_TIMING_MMC_HS200: | |
723 | case MMC_TIMING_UHS_SDR104: | |
724 | return xenon_emmc_phy_config_tuning(host); | |
725 | case MMC_TIMING_MMC_DDR52: | |
726 | case MMC_TIMING_UHS_DDR50: | |
727 | /* | |
728 | * DDR Mode requires driver to scan Sampling Fixed Delay Line, | |
729 | * to find out a perfect operation sampling point. | |
730 | * It is hard to implement such a scan in host driver | |
731 | * since initiating commands by host driver is not safe. | |
732 | * Thus so far just keep PHY Sampling Fixed Delay in | |
733 | * default value of DDR mode. | |
734 | * | |
735 | * If any timing issue occurs in DDR mode on Marvell products, | |
736 | * please contact maintainer for internal support in Marvell. | |
737 | */ | |
738 | dev_warn_once(mmc_dev(host->mmc), "Timing issue might occur in DDR mode\n"); | |
739 | return 0; | |
740 | } | |
741 | ||
742 | return ret; | |
743 | } | |
744 | ||
745 | /* | |
746 | * Adjust PHY setting. | |
747 | * PHY setting should be adjusted when SDCLK frequency, Bus Width | |
748 | * or Speed Mode is changed. | |
749 | * Additional config are required when card is working in High Speed mode, | |
750 | * after leaving Legacy Mode. | |
751 | */ | |
752 | int xenon_phy_adj(struct sdhci_host *host, struct mmc_ios *ios) | |
753 | { | |
754 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
755 | struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host); | |
756 | int ret = 0; | |
757 | ||
758 | if (!host->clock) { | |
759 | priv->clock = 0; | |
760 | return 0; | |
761 | } | |
762 | ||
763 | /* | |
764 | * The timing, frequency or bus width is changed, | |
765 | * better to set eMMC PHY based on current setting | |
766 | * and adjust Xenon SDHC delay. | |
767 | */ | |
768 | if ((host->clock == priv->clock) && | |
769 | (ios->bus_width == priv->bus_width) && | |
770 | (ios->timing == priv->timing)) | |
771 | return 0; | |
772 | ||
773 | xenon_emmc_phy_set(host, ios->timing); | |
774 | ||
775 | /* Update the record */ | |
776 | priv->bus_width = ios->bus_width; | |
777 | ||
778 | priv->timing = ios->timing; | |
779 | priv->clock = host->clock; | |
780 | ||
781 | /* Legacy mode is a special case */ | |
782 | if (ios->timing == MMC_TIMING_LEGACY) | |
783 | return 0; | |
784 | ||
785 | if (host->clock > XENON_DEFAULT_SDCLK_FREQ) | |
786 | ret = xenon_hs_delay_adj(host); | |
787 | return ret; | |
788 | } | |
789 | ||
06c8b667 HZ |
790 | static int xenon_add_phy(struct device_node *np, struct sdhci_host *host, |
791 | const char *phy_name) | |
792 | { | |
793 | struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); | |
794 | struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host); | |
795 | int i, ret; | |
796 | ||
797 | for (i = 0; i < NR_PHY_TYPES; i++) { | |
798 | if (!strcmp(phy_name, phy_types[i])) { | |
799 | priv->phy_type = i; | |
800 | break; | |
801 | } | |
802 | } | |
803 | if (i == NR_PHY_TYPES) { | |
804 | dev_err(mmc_dev(host->mmc), | |
805 | "Unable to determine PHY name %s. Use default eMMC 5.1 PHY\n", | |
806 | phy_name); | |
807 | priv->phy_type = EMMC_5_1_PHY; | |
808 | } | |
809 | ||
810 | ret = xenon_alloc_emmc_phy(host); | |
811 | if (ret) | |
812 | return ret; | |
813 | ||
bae3dee0 | 814 | return xenon_emmc_phy_parse_param_dt(host, np, priv->phy_params); |
06c8b667 HZ |
815 | } |
816 | ||
817 | int xenon_phy_parse_dt(struct device_node *np, struct sdhci_host *host) | |
818 | { | |
819 | const char *phy_type = NULL; | |
820 | ||
821 | if (!of_property_read_string(np, "marvell,xenon-phy-type", &phy_type)) | |
822 | return xenon_add_phy(np, host, phy_type); | |
823 | ||
824 | return xenon_add_phy(np, host, "emmc 5.1 phy"); | |
825 | } |