]> git.proxmox.com Git - mirror_ubuntu-artful-kernel.git/blame - drivers/mmc/host/sdhci.c
projects / mirror_ubuntu-artful-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
mmc: sdio: Fix to support any block size optimally
[mirror_ubuntu-artful-kernel.git] / drivers / mmc / host / sdhci.c
CommitLineData
d129bceb 1/*
70f10482 2 * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
d129bceb 3 *
b69c9058 4 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
d129bceb
PO		 5 *
6 * This program is free software; you can redistribute it and/or modify
643f720c
PO		 7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or (at
9 * your option) any later version.
84c46a53
PO		 10 *
11 * Thanks to the following companies for their support:
12 *
13 * - JMicron (hardware and technical support)
d129bceb
PO		 14 */
15
d129bceb
PO		 16#include <linux/delay.h>
17#include <linux/highmem.h>
b8c86fc5 18#include <linux/io.h>
88b47679 19#include <linux/module.h>
d129bceb 20#include <linux/dma-mapping.h>
5a0e3ad6 21#include <linux/slab.h>
11763609 22#include <linux/scatterlist.h>
9bea3c85 23#include <linux/regulator/consumer.h>
66fd8ad5 24#include <linux/pm_runtime.h>
d129bceb 25
2f730fec
PO		 26#include <linux/leds.h>
27
22113efd 28#include <linux/mmc/mmc.h>
d129bceb 29#include <linux/mmc/host.h>
d129bceb 30
d129bceb
PO		 31#include "sdhci.h"
32
33#define DRIVER_NAME "sdhci"
d129bceb 34
d129bceb 35#define DBG(f, x...) \
c6563178 36 pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
d129bceb 37
f9134319
PO		 38#if defined(CONFIG_LEDS_CLASS) || (defined(CONFIG_LEDS_CLASS_MODULE) && \
39 defined(CONFIG_MMC_SDHCI_MODULE))
40#define SDHCI_USE_LEDS_CLASS
41#endif
42
b513ea25
AN		 43#define MAX_TUNING_LOOP 40
44
df673b22 45static unsigned int debug_quirks = 0;
66fd8ad5 46static unsigned int debug_quirks2;
67435274 47
d129bceb
PO		 48static void sdhci_finish_data(struct sdhci_host *);
49
50static void sdhci_send_command(struct sdhci_host *, struct mmc_command *);
51static void sdhci_finish_command(struct sdhci_host *);
cf2b5eea
AN		 52static int sdhci_execute_tuning(struct mmc_host *mmc);
53static void sdhci_tuning_timer(unsigned long data);
d129bceb 54
66fd8ad5
AH		 55#ifdef CONFIG_PM_RUNTIME
56static int sdhci_runtime_pm_get(struct sdhci_host *host);
57static int sdhci_runtime_pm_put(struct sdhci_host *host);
58#else
59static inline int sdhci_runtime_pm_get(struct sdhci_host *host)
60{
61 return 0;
62}
63static inline int sdhci_runtime_pm_put(struct sdhci_host *host)
64{
65 return 0;
66}
67#endif
68
d129bceb
PO		 69static void sdhci_dumpregs(struct sdhci_host *host)
70{
a3c76eb9 71 pr_debug(DRIVER_NAME ": =========== REGISTER DUMP (%s)===========\n",
412ab659 72 mmc_hostname(host->mmc));
d129bceb 73
a3c76eb9 74 pr_debug(DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n",
4e4141a5
AV		 75 sdhci_readl(host, SDHCI_DMA_ADDRESS),
76 sdhci_readw(host, SDHCI_HOST_VERSION));
a3c76eb9 77 pr_debug(DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n",
4e4141a5
AV		 78 sdhci_readw(host, SDHCI_BLOCK_SIZE),
79 sdhci_readw(host, SDHCI_BLOCK_COUNT));
a3c76eb9 80 pr_debug(DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
4e4141a5
AV		 81 sdhci_readl(host, SDHCI_ARGUMENT),
82 sdhci_readw(host, SDHCI_TRANSFER_MODE));
a3c76eb9 83 pr_debug(DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n",
4e4141a5
AV		 84 sdhci_readl(host, SDHCI_PRESENT_STATE),
85 sdhci_readb(host, SDHCI_HOST_CONTROL));
a3c76eb9 86 pr_debug(DRIVER_NAME ": Power: 0x%08x | Blk gap: 0x%08x\n",
4e4141a5
AV		 87 sdhci_readb(host, SDHCI_POWER_CONTROL),
88 sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL));
a3c76eb9 89 pr_debug(DRIVER_NAME ": Wake-up: 0x%08x | Clock: 0x%08x\n",
4e4141a5
AV		 90 sdhci_readb(host, SDHCI_WAKE_UP_CONTROL),
91 sdhci_readw(host, SDHCI_CLOCK_CONTROL));
a3c76eb9 92 pr_debug(DRIVER_NAME ": Timeout: 0x%08x | Int stat: 0x%08x\n",
4e4141a5
AV		 93 sdhci_readb(host, SDHCI_TIMEOUT_CONTROL),
94 sdhci_readl(host, SDHCI_INT_STATUS));
a3c76eb9 95 pr_debug(DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
4e4141a5
AV		 96 sdhci_readl(host, SDHCI_INT_ENABLE),
97 sdhci_readl(host, SDHCI_SIGNAL_ENABLE));
a3c76eb9 98 pr_debug(DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
4e4141a5
AV		 99 sdhci_readw(host, SDHCI_ACMD12_ERR),
100 sdhci_readw(host, SDHCI_SLOT_INT_STATUS));
a3c76eb9 101 pr_debug(DRIVER_NAME ": Caps: 0x%08x | Caps_1: 0x%08x\n",
4e4141a5 102 sdhci_readl(host, SDHCI_CAPABILITIES),
e8120ad1 103 sdhci_readl(host, SDHCI_CAPABILITIES_1));
a3c76eb9 104 pr_debug(DRIVER_NAME ": Cmd: 0x%08x | Max curr: 0x%08x\n",
e8120ad1 105 sdhci_readw(host, SDHCI_COMMAND),
4e4141a5 106 sdhci_readl(host, SDHCI_MAX_CURRENT));
a3c76eb9 107 pr_debug(DRIVER_NAME ": Host ctl2: 0x%08x\n",
f2119df6 108 sdhci_readw(host, SDHCI_HOST_CONTROL2));
d129bceb 109
be3f4ae0 110 if (host->flags & SDHCI_USE_ADMA)
a3c76eb9 111 pr_debug(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n",
be3f4ae0
BD		 112 readl(host->ioaddr + SDHCI_ADMA_ERROR),
113 readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
114
a3c76eb9 115 pr_debug(DRIVER_NAME ": ===========================================\n");
d129bceb
PO		 116}
117
118/*****************************************************************************\
119 * *
120 * Low level functions *
121 * *
122\*****************************************************************************/
123
7260cf5e
AV		 124static void sdhci_clear_set_irqs(struct sdhci_host *host, u32 clear, u32 set)
125{
126 u32 ier;
127
128 ier = sdhci_readl(host, SDHCI_INT_ENABLE);
129 ier &= ~clear;
130 ier |= set;
131 sdhci_writel(host, ier, SDHCI_INT_ENABLE);
132 sdhci_writel(host, ier, SDHCI_SIGNAL_ENABLE);
133}
134
135static void sdhci_unmask_irqs(struct sdhci_host *host, u32 irqs)
136{
137 sdhci_clear_set_irqs(host, 0, irqs);
138}
139
140static void sdhci_mask_irqs(struct sdhci_host *host, u32 irqs)
141{
142 sdhci_clear_set_irqs(host, irqs, 0);
143}
144
145static void sdhci_set_card_detection(struct sdhci_host *host, bool enable)
146{
d25928d1 147 u32 present, irqs;
7260cf5e 148
68d1fb7e
AV		 149 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
150 return;
151
66fd8ad5
AH		 152 if (host->quirks2 & SDHCI_QUIRK2_OWN_CARD_DETECTION)
153 return;
154
d25928d1
SG		 155 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
156 SDHCI_CARD_PRESENT;
157 irqs = present ? SDHCI_INT_CARD_REMOVE : SDHCI_INT_CARD_INSERT;
158
7260cf5e
AV		 159 if (enable)
160 sdhci_unmask_irqs(host, irqs);
161 else
162 sdhci_mask_irqs(host, irqs);
163}
164
165static void sdhci_enable_card_detection(struct sdhci_host *host)
166{
167 sdhci_set_card_detection(host, true);
168}
169
170static void sdhci_disable_card_detection(struct sdhci_host *host)
171{
172 sdhci_set_card_detection(host, false);
173}
174
d129bceb
PO		 175static void sdhci_reset(struct sdhci_host *host, u8 mask)
176{
e16514d8 177 unsigned long timeout;
063a9dbb 178 u32 uninitialized_var(ier);
e16514d8 179
b8c86fc5 180 if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
4e4141a5 181 if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) &
8a4da143
PO		 182 SDHCI_CARD_PRESENT))
183 return;
184 }
185
063a9dbb
AV		 186 if (host->quirks & SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET)
187 ier = sdhci_readl(host, SDHCI_INT_ENABLE);
188
393c1a34
PR		 189 if (host->ops->platform_reset_enter)
190 host->ops->platform_reset_enter(host, mask);
191
4e4141a5 192 sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
d129bceb 193
e16514d8 194 if (mask & SDHCI_RESET_ALL)
d129bceb
PO		 195 host->clock = 0;
196
e16514d8
PO		 197 /* Wait max 100 ms */
198 timeout = 100;
199
200 /* hw clears the bit when it's done */
4e4141a5 201 while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
e16514d8 202 if (timeout == 0) {
a3c76eb9 203 pr_err("%s: Reset 0x%x never completed.\n",
e16514d8
PO		 204 mmc_hostname(host->mmc), (int)mask);
205 sdhci_dumpregs(host);
206 return;
207 }
208 timeout--;
209 mdelay(1);
d129bceb 210 }
063a9dbb 211
393c1a34
PR		 212 if (host->ops->platform_reset_exit)
213 host->ops->platform_reset_exit(host, mask);
214
063a9dbb
AV		 215 if (host->quirks & SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET)
216 sdhci_clear_set_irqs(host, SDHCI_INT_ALL_MASK, ier);
d129bceb
PO		 217}
218
2f4cbb3d
NP		 219static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios);
220
221static void sdhci_init(struct sdhci_host *host, int soft)
d129bceb 222{
2f4cbb3d
NP		 223 if (soft)
224 sdhci_reset(host, SDHCI_RESET_CMD|SDHCI_RESET_DATA);
225 else
226 sdhci_reset(host, SDHCI_RESET_ALL);
d129bceb 227
7260cf5e
AV		 228 sdhci_clear_set_irqs(host, SDHCI_INT_ALL_MASK,
229 SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
3192a28f
PO		 230 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX |
231 SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT |
6aa943ab 232 SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE);
2f4cbb3d
NP		 233
234 if (soft) {
235 /* force clock reconfiguration */
236 host->clock = 0;
237 sdhci_set_ios(host->mmc, &host->mmc->ios);
238 }
7260cf5e 239}
d129bceb 240
7260cf5e
AV		 241static void sdhci_reinit(struct sdhci_host *host)
242{
2f4cbb3d 243 sdhci_init(host, 0);
7260cf5e 244 sdhci_enable_card_detection(host);
d129bceb
PO		 245}
246
247static void sdhci_activate_led(struct sdhci_host *host)
248{
249 u8 ctrl;
250
4e4141a5 251 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
d129bceb 252 ctrl |= SDHCI_CTRL_LED;
4e4141a5 253 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d129bceb
PO		 254}
255
256static void sdhci_deactivate_led(struct sdhci_host *host)
257{
258 u8 ctrl;
259
4e4141a5 260 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
d129bceb 261 ctrl &= ~SDHCI_CTRL_LED;
4e4141a5 262 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d129bceb
PO		 263}
264
f9134319 265#ifdef SDHCI_USE_LEDS_CLASS
2f730fec
PO		 266static void sdhci_led_control(struct led_classdev *led,
267 enum led_brightness brightness)
268{
269 struct sdhci_host *host = container_of(led, struct sdhci_host, led);
270 unsigned long flags;
271
272 spin_lock_irqsave(&host->lock, flags);
273
66fd8ad5
AH		 274 if (host->runtime_suspended)
275 goto out;
276
2f730fec
PO		 277 if (brightness == LED_OFF)
278 sdhci_deactivate_led(host);
279 else
280 sdhci_activate_led(host);
66fd8ad5 281out:
2f730fec
PO		 282 spin_unlock_irqrestore(&host->lock, flags);
283}
284#endif
285
d129bceb
PO		 286/*****************************************************************************\
287 * *
288 * Core functions *
289 * *
290\*****************************************************************************/
291
a406f5a3 292static void sdhci_read_block_pio(struct sdhci_host *host)
d129bceb 293{
7659150c
PO		 294 unsigned long flags;
295 size_t blksize, len, chunk;
7244b85b 296 u32 uninitialized_var(scratch);
7659150c 297 u8 *buf;
d129bceb 298
a406f5a3 299 DBG("PIO reading\n");
d129bceb 300
a406f5a3 301 blksize = host->data->blksz;
7659150c 302 chunk = 0;
d129bceb 303
7659150c 304 local_irq_save(flags);
d129bceb 305
a406f5a3 306 while (blksize) {
7659150c
PO		 307 if (!sg_miter_next(&host->sg_miter))
308 BUG();
d129bceb 309
7659150c 310 len = min(host->sg_miter.length, blksize);
d129bceb 311
7659150c
PO		 312 blksize -= len;
313 host->sg_miter.consumed = len;
14d836e7 314
7659150c 315 buf = host->sg_miter.addr;
d129bceb 316
7659150c
PO		 317 while (len) {
318 if (chunk == 0) {
4e4141a5 319 scratch = sdhci_readl(host, SDHCI_BUFFER);
7659150c 320 chunk = 4;
a406f5a3 321 }
7659150c
PO		 322
323 *buf = scratch & 0xFF;
324
325 buf++;
326 scratch >>= 8;
327 chunk--;
328 len--;
d129bceb 329 }
a406f5a3 330 }
7659150c
PO		 331
332 sg_miter_stop(&host->sg_miter);
333
334 local_irq_restore(flags);
a406f5a3 335}
d129bceb 336
a406f5a3
PO		 337static void sdhci_write_block_pio(struct sdhci_host *host)
338{
7659150c
PO		 339 unsigned long flags;
340 size_t blksize, len, chunk;
341 u32 scratch;
342 u8 *buf;
d129bceb 343
a406f5a3
PO		 344 DBG("PIO writing\n");
345
346 blksize = host->data->blksz;
7659150c
PO		 347 chunk = 0;
348 scratch = 0;
d129bceb 349
7659150c 350 local_irq_save(flags);
d129bceb 351
a406f5a3 352 while (blksize) {
7659150c
PO		 353 if (!sg_miter_next(&host->sg_miter))
354 BUG();
a406f5a3 355
7659150c
PO		 356 len = min(host->sg_miter.length, blksize);
357
358 blksize -= len;
359 host->sg_miter.consumed = len;
360
361 buf = host->sg_miter.addr;
d129bceb 362
7659150c
PO		 363 while (len) {
364 scratch |= (u32)*buf << (chunk * 8);
365
366 buf++;
367 chunk++;
368 len--;
369
370 if ((chunk == 4) || ((len == 0) && (blksize == 0))) {
4e4141a5 371 sdhci_writel(host, scratch, SDHCI_BUFFER);
7659150c
PO		 372 chunk = 0;
373 scratch = 0;
d129bceb 374 }
d129bceb
PO		 375 }
376 }
7659150c
PO		 377
378 sg_miter_stop(&host->sg_miter);
379
380 local_irq_restore(flags);
a406f5a3
PO		 381}
382
383static void sdhci_transfer_pio(struct sdhci_host *host)
384{
385 u32 mask;
386
387 BUG_ON(!host->data);
388
7659150c 389 if (host->blocks == 0)
a406f5a3
PO		 390 return;
391
392 if (host->data->flags & MMC_DATA_READ)
393 mask = SDHCI_DATA_AVAILABLE;
394 else
395 mask = SDHCI_SPACE_AVAILABLE;
396
4a3cba32
PO		 397 /*
398 * Some controllers (JMicron JMB38x) mess up the buffer bits
399 * for transfers < 4 bytes. As long as it is just one block,
400 * we can ignore the bits.
401 */
402 if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) &&
403 (host->data->blocks == 1))
404 mask = ~0;
405
4e4141a5 406 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
3e3bf207
AV		 407 if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY)
408 udelay(100);
409
a406f5a3
PO		 410 if (host->data->flags & MMC_DATA_READ)
411 sdhci_read_block_pio(host);
412 else
413 sdhci_write_block_pio(host);
d129bceb 414
7659150c
PO		 415 host->blocks--;
416 if (host->blocks == 0)
a406f5a3 417 break;
a406f5a3 418 }
d129bceb 419
a406f5a3 420 DBG("PIO transfer complete.\n");
d129bceb
PO		 421}
422
2134a922
PO		 423static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags)
424{
425 local_irq_save(*flags);
426 return kmap_atomic(sg_page(sg), KM_BIO_SRC_IRQ) + sg->offset;
427}
428
429static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags)
430{
431 kunmap_atomic(buffer, KM_BIO_SRC_IRQ);
432 local_irq_restore(*flags);
433}
434
118cd17d
BD		 435static void sdhci_set_adma_desc(u8 *desc, u32 addr, int len, unsigned cmd)
436{
9e506f35
BD		 437 __le32 *dataddr = (__le32 __force *)(desc + 4);
438 __le16 *cmdlen = (__le16 __force *)desc;
118cd17d 439
9e506f35
BD		 440 /* SDHCI specification says ADMA descriptors should be 4 byte
441 * aligned, so using 16 or 32bit operations should be safe. */
118cd17d 442
9e506f35
BD		 443 cmdlen[0] = cpu_to_le16(cmd);
444 cmdlen[1] = cpu_to_le16(len);
445
446 dataddr[0] = cpu_to_le32(addr);
118cd17d
BD		 447}
448
8f1934ce 449static int sdhci_adma_table_pre(struct sdhci_host *host,
2134a922
PO		 450 struct mmc_data *data)
451{
452 int direction;
453
454 u8 *desc;
455 u8 *align;
456 dma_addr_t addr;
457 dma_addr_t align_addr;
458 int len, offset;
459
460 struct scatterlist *sg;
461 int i;
462 char *buffer;
463 unsigned long flags;
464
465 /*
466 * The spec does not specify endianness of descriptor table.
467 * We currently guess that it is LE.
468 */
469
470 if (data->flags & MMC_DATA_READ)
471 direction = DMA_FROM_DEVICE;
472 else
473 direction = DMA_TO_DEVICE;
474
475 /*
476 * The ADMA descriptor table is mapped further down as we
477 * need to fill it with data first.
478 */
479
480 host->align_addr = dma_map_single(mmc_dev(host->mmc),
481 host->align_buffer, 128 * 4, direction);
8d8bb39b 482 if (dma_mapping_error(mmc_dev(host->mmc), host->align_addr))
8f1934ce 483 goto fail;
2134a922
PO		 484 BUG_ON(host->align_addr & 0x3);
485
486 host->sg_count = dma_map_sg(mmc_dev(host->mmc),
487 data->sg, data->sg_len, direction);
8f1934ce
PO		 488 if (host->sg_count == 0)
489 goto unmap_align;
2134a922
PO		 490
491 desc = host->adma_desc;
492 align = host->align_buffer;
493
494 align_addr = host->align_addr;
495
496 for_each_sg(data->sg, sg, host->sg_count, i) {
497 addr = sg_dma_address(sg);
498 len = sg_dma_len(sg);
499
500 /*
501 * The SDHCI specification states that ADMA
502 * addresses must be 32-bit aligned. If they
503 * aren't, then we use a bounce buffer for
504 * the (up to three) bytes that screw up the
505 * alignment.
506 */
507 offset = (4 - (addr & 0x3)) & 0x3;
508 if (offset) {
509 if (data->flags & MMC_DATA_WRITE) {
510 buffer = sdhci_kmap_atomic(sg, &flags);
6cefd05f 511 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3));
2134a922
PO		 512 memcpy(align, buffer, offset);
513 sdhci_kunmap_atomic(buffer, &flags);
514 }
515
118cd17d
BD		 516 /* tran, valid */
517 sdhci_set_adma_desc(desc, align_addr, offset, 0x21);
2134a922
PO		 518
519 BUG_ON(offset > 65536);
520
2134a922
PO		 521 align += 4;
522 align_addr += 4;
523
524 desc += 8;
525
526 addr += offset;
527 len -= offset;
528 }
529
2134a922
PO		 530 BUG_ON(len > 65536);
531
118cd17d
BD		 532 /* tran, valid */
533 sdhci_set_adma_desc(desc, addr, len, 0x21);
2134a922
PO		 534 desc += 8;
535
536 /*
537 * If this triggers then we have a calculation bug
538 * somewhere. :/
539 */
540 WARN_ON((desc - host->adma_desc) > (128 * 2 + 1) * 4);
541 }
542
70764a90
TA		 543 if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) {
544 /*
545 * Mark the last descriptor as the terminating descriptor
546 */
547 if (desc != host->adma_desc) {
548 desc -= 8;
549 desc[0] |= 0x2; /* end */
550 }
551 } else {
552 /*
553 * Add a terminating entry.
554 */
2134a922 555
70764a90
TA		 556 /* nop, end, valid */
557 sdhci_set_adma_desc(desc, 0, 0, 0x3);
558 }
2134a922
PO		 559
560 /*
561 * Resync align buffer as we might have changed it.
562 */
563 if (data->flags & MMC_DATA_WRITE) {
564 dma_sync_single_for_device(mmc_dev(host->mmc),
565 host->align_addr, 128 * 4, direction);
566 }
567
568 host->adma_addr = dma_map_single(mmc_dev(host->mmc),
569 host->adma_desc, (128 * 2 + 1) * 4, DMA_TO_DEVICE);
980167b7 570 if (dma_mapping_error(mmc_dev(host->mmc), host->adma_addr))
8f1934ce 571 goto unmap_entries;
2134a922 572 BUG_ON(host->adma_addr & 0x3);
8f1934ce
PO		 573
574 return 0;
575
576unmap_entries:
577 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
578 data->sg_len, direction);
579unmap_align:
580 dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
581 128 * 4, direction);
582fail:
583 return -EINVAL;
2134a922
PO		 584}
585
586static void sdhci_adma_table_post(struct sdhci_host *host,
587 struct mmc_data *data)
588{
589 int direction;
590
591 struct scatterlist *sg;
592 int i, size;
593 u8 *align;
594 char *buffer;
595 unsigned long flags;
596
597 if (data->flags & MMC_DATA_READ)
598 direction = DMA_FROM_DEVICE;
599 else
600 direction = DMA_TO_DEVICE;
601
602 dma_unmap_single(mmc_dev(host->mmc), host->adma_addr,
603 (128 * 2 + 1) * 4, DMA_TO_DEVICE);
604
605 dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
606 128 * 4, direction);
607
608 if (data->flags & MMC_DATA_READ) {
609 dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
610 data->sg_len, direction);
611
612 align = host->align_buffer;
613
614 for_each_sg(data->sg, sg, host->sg_count, i) {
615 if (sg_dma_address(sg) & 0x3) {
616 size = 4 - (sg_dma_address(sg) & 0x3);
617
618 buffer = sdhci_kmap_atomic(sg, &flags);
6cefd05f 619 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3));
2134a922
PO		 620 memcpy(buffer, align, size);
621 sdhci_kunmap_atomic(buffer, &flags);
622
623 align += 4;
624 }
625 }
626 }
627
628 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
629 data->sg_len, direction);
630}
631
a3c7778f 632static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd)
d129bceb 633{
1c8cde92 634 u8 count;
a3c7778f 635 struct mmc_data *data = cmd->data;
1c8cde92 636 unsigned target_timeout, current_timeout;
d129bceb 637
ee53ab5d
PO		 638 /*
639 * If the host controller provides us with an incorrect timeout
640 * value, just skip the check and use 0xE. The hardware may take
641 * longer to time out, but that's much better than having a too-short
642 * timeout value.
643 */
11a2f1b7 644 if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL)
ee53ab5d 645 return 0xE;
e538fbe8 646
a3c7778f
AW		 647 /* Unspecified timeout, assume max */
648 if (!data && !cmd->cmd_timeout_ms)
649 return 0xE;
d129bceb 650
a3c7778f
AW		 651 /* timeout in us */
652 if (!data)
653 target_timeout = cmd->cmd_timeout_ms * 1000;
78a2ca27
AS		 654 else {
655 target_timeout = data->timeout_ns / 1000;
656 if (host->clock)
657 target_timeout += data->timeout_clks / host->clock;
658 }
81b39802 659
1c8cde92
PO		 660 /*
661 * Figure out needed cycles.
662 * We do this in steps in order to fit inside a 32 bit int.
663 * The first step is the minimum timeout, which will have a
664 * minimum resolution of 6 bits:
665 * (1) 2^13*1000 > 2^22,
666 * (2) host->timeout_clk < 2^16
667 * =>
668 * (1) / (2) > 2^6
669 */
670 count = 0;
671 current_timeout = (1 << 13) * 1000 / host->timeout_clk;
672 while (current_timeout < target_timeout) {
673 count++;
674 current_timeout <<= 1;
675 if (count >= 0xF)
676 break;
677 }
678
679 if (count >= 0xF) {
a3c76eb9 680 pr_warning("%s: Too large timeout requested for CMD%d!\n",
a3c7778f 681 mmc_hostname(host->mmc), cmd->opcode);
1c8cde92
PO		 682 count = 0xE;
683 }
684
ee53ab5d
PO		 685 return count;
686}
687
6aa943ab
AV		 688static void sdhci_set_transfer_irqs(struct sdhci_host *host)
689{
690 u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL;
691 u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR;
692
693 if (host->flags & SDHCI_REQ_USE_DMA)
694 sdhci_clear_set_irqs(host, pio_irqs, dma_irqs);
695 else
696 sdhci_clear_set_irqs(host, dma_irqs, pio_irqs);
697}
698
a3c7778f 699static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd)
ee53ab5d
PO		 700{
701 u8 count;
2134a922 702 u8 ctrl;
a3c7778f 703 struct mmc_data *data = cmd->data;
8f1934ce 704 int ret;
ee53ab5d
PO		 705
706 WARN_ON(host->data);
707
a3c7778f
AW		 708 if (data || (cmd->flags & MMC_RSP_BUSY)) {
709 count = sdhci_calc_timeout(host, cmd);
710 sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
711 }
712
713 if (!data)
ee53ab5d
PO		 714 return;
715
716 /* Sanity checks */
717 BUG_ON(data->blksz * data->blocks > 524288);
718 BUG_ON(data->blksz > host->mmc->max_blk_size);
719 BUG_ON(data->blocks > 65535);
720
721 host->data = data;
722 host->data_early = 0;
f6a03cbf 723 host->data->bytes_xfered = 0;
ee53ab5d 724
a13abc7b 725 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))
c9fddbc4
PO		 726 host->flags |= SDHCI_REQ_USE_DMA;
727
2134a922
PO		 728 /*
729 * FIXME: This doesn't account for merging when mapping the
730 * scatterlist.
731 */
732 if (host->flags & SDHCI_REQ_USE_DMA) {
733 int broken, i;
734 struct scatterlist *sg;
735
736 broken = 0;
737 if (host->flags & SDHCI_USE_ADMA) {
738 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
739 broken = 1;
740 } else {
741 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE)
742 broken = 1;
743 }
744
745 if (unlikely(broken)) {
746 for_each_sg(data->sg, sg, data->sg_len, i) {
747 if (sg->length & 0x3) {
748 DBG("Reverting to PIO because of "
749 "transfer size (%d)\n",
750 sg->length);
751 host->flags &= ~SDHCI_REQ_USE_DMA;
752 break;
753 }
754 }
755 }
c9fddbc4
PO		 756 }
757
758 /*
759 * The assumption here being that alignment is the same after
760 * translation to device address space.
761 */
2134a922
PO		 762 if (host->flags & SDHCI_REQ_USE_DMA) {
763 int broken, i;
764 struct scatterlist *sg;
765
766 broken = 0;
767 if (host->flags & SDHCI_USE_ADMA) {
768 /*
769 * As we use 3 byte chunks to work around
770 * alignment problems, we need to check this
771 * quirk.
772 */
773 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
774 broken = 1;
775 } else {
776 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR)
777 broken = 1;
778 }
779
780 if (unlikely(broken)) {
781 for_each_sg(data->sg, sg, data->sg_len, i) {
782 if (sg->offset & 0x3) {
783 DBG("Reverting to PIO because of "
784 "bad alignment\n");
785 host->flags &= ~SDHCI_REQ_USE_DMA;
786 break;
787 }
788 }
789 }
790 }
791
8f1934ce
PO		 792 if (host->flags & SDHCI_REQ_USE_DMA) {
793 if (host->flags & SDHCI_USE_ADMA) {
794 ret = sdhci_adma_table_pre(host, data);
795 if (ret) {
796 /*
797 * This only happens when someone fed
798 * us an invalid request.
799 */
800 WARN_ON(1);
ebd6d357 801 host->flags &= ~SDHCI_REQ_USE_DMA;
8f1934ce 802 } else {
4e4141a5
AV		 803 sdhci_writel(host, host->adma_addr,
804 SDHCI_ADMA_ADDRESS);
8f1934ce
PO		 805 }
806 } else {
c8b3e02e 807 int sg_cnt;
8f1934ce 808
c8b3e02e 809 sg_cnt = dma_map_sg(mmc_dev(host->mmc),
8f1934ce
PO		 810 data->sg, data->sg_len,
811 (data->flags & MMC_DATA_READ) ?
812 DMA_FROM_DEVICE :
813 DMA_TO_DEVICE);
c8b3e02e 814 if (sg_cnt == 0) {
8f1934ce
PO		 815 /*
816 * This only happens when someone fed
817 * us an invalid request.
818 */
819 WARN_ON(1);
ebd6d357 820 host->flags &= ~SDHCI_REQ_USE_DMA;
8f1934ce 821 } else {
719a61b4 822 WARN_ON(sg_cnt != 1);
4e4141a5
AV		 823 sdhci_writel(host, sg_dma_address(data->sg),
824 SDHCI_DMA_ADDRESS);
8f1934ce
PO		 825 }
826 }
827 }
828
2134a922
PO		 829 /*
830 * Always adjust the DMA selection as some controllers
831 * (e.g. JMicron) can't do PIO properly when the selection
832 * is ADMA.
833 */
834 if (host->version >= SDHCI_SPEC_200) {
4e4141a5 835 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
2134a922
PO		 836 ctrl &= ~SDHCI_CTRL_DMA_MASK;
837 if ((host->flags & SDHCI_REQ_USE_DMA) &&
838 (host->flags & SDHCI_USE_ADMA))
839 ctrl |= SDHCI_CTRL_ADMA32;
840 else
841 ctrl |= SDHCI_CTRL_SDMA;
4e4141a5 842 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
c9fddbc4
PO		 843 }
844
8f1934ce 845 if (!(host->flags & SDHCI_REQ_USE_DMA)) {
da60a91d
SAS		 846 int flags;
847
848 flags = SG_MITER_ATOMIC;
849 if (host->data->flags & MMC_DATA_READ)
850 flags |= SG_MITER_TO_SG;
851 else
852 flags |= SG_MITER_FROM_SG;
853 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
7659150c 854 host->blocks = data->blocks;
d129bceb 855 }
c7fa9963 856
6aa943ab
AV		 857 sdhci_set_transfer_irqs(host);
858
f6a03cbf
MV		 859 /* Set the DMA boundary value and block size */
860 sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
861 data->blksz), SDHCI_BLOCK_SIZE);
4e4141a5 862 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
c7fa9963
PO		 863}
864
865static void sdhci_set_transfer_mode(struct sdhci_host *host,
e89d456f 866 struct mmc_command *cmd)
c7fa9963
PO		 867{
868 u16 mode;
e89d456f 869 struct mmc_data *data = cmd->data;
c7fa9963 870
c7fa9963
PO		 871 if (data == NULL)
872 return;
873
e538fbe8
PO		 874 WARN_ON(!host->data);
875
c7fa9963 876 mode = SDHCI_TRNS_BLK_CNT_EN;
e89d456f
AW		 877 if (mmc_op_multi(cmd->opcode) || data->blocks > 1) {
878 mode |= SDHCI_TRNS_MULTI;
879 /*
880 * If we are sending CMD23, CMD12 never gets sent
881 * on successful completion (so no Auto-CMD12).
882 */
883 if (!host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD12))
884 mode |= SDHCI_TRNS_AUTO_CMD12;
8edf6371
AW		 885 else if (host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) {
886 mode |= SDHCI_TRNS_AUTO_CMD23;
887 sdhci_writel(host, host->mrq->sbc->arg, SDHCI_ARGUMENT2);
888 }
c4512f79 889 }
8edf6371 890
c7fa9963
PO		 891 if (data->flags & MMC_DATA_READ)
892 mode |= SDHCI_TRNS_READ;
c9fddbc4 893 if (host->flags & SDHCI_REQ_USE_DMA)
c7fa9963
PO		 894 mode |= SDHCI_TRNS_DMA;
895
4e4141a5 896 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
d129bceb
PO		 897}
898
899static void sdhci_finish_data(struct sdhci_host *host)
900{
901 struct mmc_data *data;
d129bceb
PO		 902
903 BUG_ON(!host->data);
904
905 data = host->data;
906 host->data = NULL;
907
c9fddbc4 908 if (host->flags & SDHCI_REQ_USE_DMA) {
2134a922
PO		 909 if (host->flags & SDHCI_USE_ADMA)
910 sdhci_adma_table_post(host, data);
911 else {
912 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
913 data->sg_len, (data->flags & MMC_DATA_READ) ?
914 DMA_FROM_DEVICE : DMA_TO_DEVICE);
915 }
d129bceb
PO		 916 }
917
918 /*
c9b74c5b
PO		 919 * The specification states that the block count register must
920 * be updated, but it does not specify at what point in the
921 * data flow. That makes the register entirely useless to read
922 * back so we have to assume that nothing made it to the card
923 * in the event of an error.
d129bceb 924 */
c9b74c5b
PO		 925 if (data->error)
926 data->bytes_xfered = 0;
d129bceb 927 else
c9b74c5b 928 data->bytes_xfered = data->blksz * data->blocks;
d129bceb 929
e89d456f
AW		 930 /*
931 * Need to send CMD12 if -
932 * a) open-ended multiblock transfer (no CMD23)
933 * b) error in multiblock transfer
934 */
935 if (data->stop &&
936 (data->error ||
937 !host->mrq->sbc)) {
938
d129bceb
PO		 939 /*
940 * The controller needs a reset of internal state machines
941 * upon error conditions.
942 */
17b0429d 943 if (data->error) {
d129bceb
PO		 944 sdhci_reset(host, SDHCI_RESET_CMD);
945 sdhci_reset(host, SDHCI_RESET_DATA);
946 }
947
948 sdhci_send_command(host, data->stop);
949 } else
950 tasklet_schedule(&host->finish_tasklet);
951}
952
953static void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
954{
955 int flags;
fd2208d7 956 u32 mask;
7cb2c76f 957 unsigned long timeout;
d129bceb
PO		 958
959 WARN_ON(host->cmd);
960
d129bceb 961 /* Wait max 10 ms */
7cb2c76f 962 timeout = 10;
fd2208d7
PO		 963
964 mask = SDHCI_CMD_INHIBIT;
965 if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
966 mask |= SDHCI_DATA_INHIBIT;
967
968 /* We shouldn't wait for data inihibit for stop commands, even
969 though they might use busy signaling */
970 if (host->mrq->data && (cmd == host->mrq->data->stop))
971 mask &= ~SDHCI_DATA_INHIBIT;
972
4e4141a5 973 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
7cb2c76f 974 if (timeout == 0) {
a3c76eb9 975 pr_err("%s: Controller never released "
acf1da45 976 "inhibit bit(s).\n", mmc_hostname(host->mmc));
d129bceb 977 sdhci_dumpregs(host);
17b0429d 978 cmd->error = -EIO;
d129bceb
PO		 979 tasklet_schedule(&host->finish_tasklet);
980 return;
981 }
7cb2c76f
PO		 982 timeout--;
983 mdelay(1);
984 }
d129bceb
PO		 985
986 mod_timer(&host->timer, jiffies + 10 * HZ);
987
988 host->cmd = cmd;
989
a3c7778f 990 sdhci_prepare_data(host, cmd);
d129bceb 991
4e4141a5 992 sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT);
d129bceb 993
e89d456f 994 sdhci_set_transfer_mode(host, cmd);
c7fa9963 995
d129bceb 996 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
a3c76eb9 997 pr_err("%s: Unsupported response type!\n",
d129bceb 998 mmc_hostname(host->mmc));
17b0429d 999 cmd->error = -EINVAL;
d129bceb
PO		 1000 tasklet_schedule(&host->finish_tasklet);
1001 return;
1002 }
1003
1004 if (!(cmd->flags & MMC_RSP_PRESENT))
1005 flags = SDHCI_CMD_RESP_NONE;
1006 else if (cmd->flags & MMC_RSP_136)
1007 flags = SDHCI_CMD_RESP_LONG;
1008 else if (cmd->flags & MMC_RSP_BUSY)
1009 flags = SDHCI_CMD_RESP_SHORT_BUSY;
1010 else
1011 flags = SDHCI_CMD_RESP_SHORT;
1012
1013 if (cmd->flags & MMC_RSP_CRC)
1014 flags |= SDHCI_CMD_CRC;
1015 if (cmd->flags & MMC_RSP_OPCODE)
1016 flags |= SDHCI_CMD_INDEX;
b513ea25
AN		 1017
1018 /* CMD19 is special in that the Data Present Select should be set */
1019 if (cmd->data || (cmd->opcode == MMC_SEND_TUNING_BLOCK))
d129bceb
PO		 1020 flags |= SDHCI_CMD_DATA;
1021
4e4141a5 1022 sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND);
d129bceb
PO		 1023}
1024
1025static void sdhci_finish_command(struct sdhci_host *host)
1026{
1027 int i;
1028
1029 BUG_ON(host->cmd == NULL);
1030
1031 if (host->cmd->flags & MMC_RSP_PRESENT) {
1032 if (host->cmd->flags & MMC_RSP_136) {
1033 /* CRC is stripped so we need to do some shifting. */
1034 for (i = 0;i < 4;i++) {
4e4141a5 1035 host->cmd->resp[i] = sdhci_readl(host,
d129bceb
PO		 1036 SDHCI_RESPONSE + (3-i)*4) << 8;
1037 if (i != 3)
1038 host->cmd->resp[i] |=
4e4141a5 1039 sdhci_readb(host,
d129bceb
PO		 1040 SDHCI_RESPONSE + (3-i)*4-1);
1041 }
1042 } else {
4e4141a5 1043 host->cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE);
d129bceb
PO		 1044 }
1045 }
1046
17b0429d 1047 host->cmd->error = 0;
d129bceb 1048
e89d456f
AW		 1049 /* Finished CMD23, now send actual command. */
1050 if (host->cmd == host->mrq->sbc) {
1051 host->cmd = NULL;
1052 sdhci_send_command(host, host->mrq->cmd);
1053 } else {
e538fbe8 1054
e89d456f
AW		 1055 /* Processed actual command. */
1056 if (host->data && host->data_early)
1057 sdhci_finish_data(host);
d129bceb 1058
e89d456f
AW		 1059 if (!host->cmd->data)
1060 tasklet_schedule(&host->finish_tasklet);
1061
1062 host->cmd = NULL;
1063 }
d129bceb
PO		 1064}
1065
1066static void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
1067{
c3ed3877
AN		 1068 int div = 0; /* Initialized for compiler warning */
1069 u16 clk = 0;
7cb2c76f 1070 unsigned long timeout;
d129bceb
PO		 1071
1072 if (clock == host->clock)
1073 return;
1074
8114634c
AV		 1075 if (host->ops->set_clock) {
1076 host->ops->set_clock(host, clock);
1077 if (host->quirks & SDHCI_QUIRK_NONSTANDARD_CLOCK)
1078 return;
1079 }
1080
4e4141a5 1081 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
d129bceb
PO		 1082
1083 if (clock == 0)
1084 goto out;
1085
85105c53 1086 if (host->version >= SDHCI_SPEC_300) {
c3ed3877
AN		 1087 /*
1088 * Check if the Host Controller supports Programmable Clock
1089 * Mode.
1090 */
1091 if (host->clk_mul) {
1092 u16 ctrl;
1093
1094 /*
1095 * We need to figure out whether the Host Driver needs
1096 * to select Programmable Clock Mode, or the value can
1097 * be set automatically by the Host Controller based on
1098 * the Preset Value registers.
1099 */
1100 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1101 if (!(ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
1102 for (div = 1; div <= 1024; div++) {
1103 if (((host->max_clk * host->clk_mul) /
1104 div) <= clock)
1105 break;
1106 }
1107 /*
1108 * Set Programmable Clock Mode in the Clock
1109 * Control register.
1110 */
1111 clk = SDHCI_PROG_CLOCK_MODE;
1112 div--;
1113 }
1114 } else {
1115 /* Version 3.00 divisors must be a multiple of 2. */
1116 if (host->max_clk <= clock)
1117 div = 1;
1118 else {
1119 for (div = 2; div < SDHCI_MAX_DIV_SPEC_300;
1120 div += 2) {
1121 if ((host->max_clk / div) <= clock)
1122 break;
1123 }
85105c53 1124 }
c3ed3877 1125 div >>= 1;
85105c53
ZG		 1126 }
1127 } else {
1128 /* Version 2.00 divisors must be a power of 2. */
0397526d 1129 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
85105c53
ZG		 1130 if ((host->max_clk / div) <= clock)
1131 break;
1132 }
c3ed3877 1133 div >>= 1;
d129bceb 1134 }
d129bceb 1135
c3ed3877 1136 clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
85105c53
ZG		 1137 clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
1138 << SDHCI_DIVIDER_HI_SHIFT;
d129bceb 1139 clk |= SDHCI_CLOCK_INT_EN;
4e4141a5 1140 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
d129bceb 1141
27f6cb16
CB		 1142 /* Wait max 20 ms */
1143 timeout = 20;
4e4141a5 1144 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
7cb2c76f
PO		 1145 & SDHCI_CLOCK_INT_STABLE)) {
1146 if (timeout == 0) {
a3c76eb9 1147 pr_err("%s: Internal clock never "
acf1da45 1148 "stabilised.\n", mmc_hostname(host->mmc));
d129bceb
PO		 1149 sdhci_dumpregs(host);
1150 return;
1151 }
7cb2c76f
PO		 1152 timeout--;
1153 mdelay(1);
1154 }
d129bceb
PO		 1155
1156 clk |= SDHCI_CLOCK_CARD_EN;
4e4141a5 1157 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
d129bceb
PO		 1158
1159out:
1160 host->clock = clock;
1161}
1162
146ad66e
PO		 1163static void sdhci_set_power(struct sdhci_host *host, unsigned short power)
1164{
8364248a 1165 u8 pwr = 0;
146ad66e 1166
8364248a 1167 if (power != (unsigned short)-1) {
ae628903
PO		 1168 switch (1 << power) {
1169 case MMC_VDD_165_195:
1170 pwr = SDHCI_POWER_180;
1171 break;
1172 case MMC_VDD_29_30:
1173 case MMC_VDD_30_31:
1174 pwr = SDHCI_POWER_300;
1175 break;
1176 case MMC_VDD_32_33:
1177 case MMC_VDD_33_34:
1178 pwr = SDHCI_POWER_330;
1179 break;
1180 default:
1181 BUG();
1182 }
1183 }
1184
1185 if (host->pwr == pwr)
146ad66e
PO		 1186 return;
1187
ae628903
PO		 1188 host->pwr = pwr;
1189
1190 if (pwr == 0) {
4e4141a5 1191 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
ae628903 1192 return;
9e9dc5f2
DS		 1193 }
1194
1195 /*
1196 * Spec says that we should clear the power reg before setting
1197 * a new value. Some controllers don't seem to like this though.
1198 */
b8c86fc5 1199 if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
4e4141a5 1200 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
146ad66e 1201
e08c1694 1202 /*
c71f6512 1203 * At least the Marvell CaFe chip gets confused if we set the voltage
e08c1694
AS		 1204 * and set turn on power at the same time, so set the voltage first.
1205 */
11a2f1b7 1206 if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
ae628903 1207 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
e08c1694 1208
ae628903 1209 pwr |= SDHCI_POWER_ON;
146ad66e 1210
ae628903 1211 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
557b0697
HW		 1212
1213 /*
1214 * Some controllers need an extra 10ms delay of 10ms before they
1215 * can apply clock after applying power
1216 */
11a2f1b7 1217 if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER)
557b0697 1218 mdelay(10);
146ad66e
PO		 1219}
1220
d129bceb
PO		 1221/*****************************************************************************\
1222 * *
1223 * MMC callbacks *
1224 * *
1225\*****************************************************************************/
1226
1227static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1228{
1229 struct sdhci_host *host;
68d1fb7e 1230 bool present;
d129bceb
PO		 1231 unsigned long flags;
1232
1233 host = mmc_priv(mmc);
1234
66fd8ad5
AH		 1235 sdhci_runtime_pm_get(host);
1236
d129bceb
PO		 1237 spin_lock_irqsave(&host->lock, flags);
1238
1239 WARN_ON(host->mrq != NULL);
1240
f9134319 1241#ifndef SDHCI_USE_LEDS_CLASS
d129bceb 1242 sdhci_activate_led(host);
2f730fec 1243#endif
e89d456f
AW		 1244
1245 /*
1246 * Ensure we don't send the STOP for non-SET_BLOCK_COUNTED
1247 * requests if Auto-CMD12 is enabled.
1248 */
1249 if (!mrq->sbc && (host->flags & SDHCI_AUTO_CMD12)) {
c4512f79
JH		 1250 if (mrq->stop) {
1251 mrq->data->stop = NULL;
1252 mrq->stop = NULL;
1253 }
1254 }
d129bceb
PO		 1255
1256 host->mrq = mrq;
1257
68d1fb7e
AV		 1258 /* If polling, assume that the card is always present. */
1259 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
1260 present = true;
1261 else
1262 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
1263 SDHCI_CARD_PRESENT;
1264
1265 if (!present || host->flags & SDHCI_DEVICE_DEAD) {
17b0429d 1266 host->mrq->cmd->error = -ENOMEDIUM;
d129bceb 1267 tasklet_schedule(&host->finish_tasklet);
cf2b5eea
AN		 1268 } else {
1269 u32 present_state;
1270
1271 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
1272 /*
1273 * Check if the re-tuning timer has already expired and there
1274 * is no on-going data transfer. If so, we need to execute
1275 * tuning procedure before sending command.
1276 */
1277 if ((host->flags & SDHCI_NEEDS_RETUNING) &&
1278 !(present_state & (SDHCI_DOING_WRITE | SDHCI_DOING_READ))) {
1279 spin_unlock_irqrestore(&host->lock, flags);
1280 sdhci_execute_tuning(mmc);
1281 spin_lock_irqsave(&host->lock, flags);
1282
1283 /* Restore original mmc_request structure */
1284 host->mrq = mrq;
1285 }
1286
8edf6371 1287 if (mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23))
e89d456f
AW		 1288 sdhci_send_command(host, mrq->sbc);
1289 else
1290 sdhci_send_command(host, mrq->cmd);
cf2b5eea 1291 }
d129bceb 1292
5f25a66f 1293 mmiowb();
d129bceb
PO		 1294 spin_unlock_irqrestore(&host->lock, flags);
1295}
1296
66fd8ad5 1297static void sdhci_do_set_ios(struct sdhci_host *host, struct mmc_ios *ios)
d129bceb 1298{
d129bceb
PO		 1299 unsigned long flags;
1300 u8 ctrl;
1301
d129bceb
PO		 1302 spin_lock_irqsave(&host->lock, flags);
1303
1e72859e
PO		 1304 if (host->flags & SDHCI_DEVICE_DEAD)
1305 goto out;
1306
d129bceb
PO		 1307 /*
1308 * Reset the chip on each power off.
1309 * Should clear out any weird states.
1310 */
1311 if (ios->power_mode == MMC_POWER_OFF) {
4e4141a5 1312 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
7260cf5e 1313 sdhci_reinit(host);
d129bceb
PO		 1314 }
1315
1316 sdhci_set_clock(host, ios->clock);
1317
1318 if (ios->power_mode == MMC_POWER_OFF)
146ad66e 1319 sdhci_set_power(host, -1);
d129bceb 1320 else
146ad66e 1321 sdhci_set_power(host, ios->vdd);
d129bceb 1322
643a81ff
PR		 1323 if (host->ops->platform_send_init_74_clocks)
1324 host->ops->platform_send_init_74_clocks(host, ios->power_mode);
1325
15ec4461
PR		 1326 /*
1327 * If your platform has 8-bit width support but is not a v3 controller,
1328 * or if it requires special setup code, you should implement that in
1329 * platform_8bit_width().
1330 */
1331 if (host->ops->platform_8bit_width)
1332 host->ops->platform_8bit_width(host, ios->bus_width);
1333 else {
1334 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1335 if (ios->bus_width == MMC_BUS_WIDTH_8) {
1336 ctrl &= ~SDHCI_CTRL_4BITBUS;
1337 if (host->version >= SDHCI_SPEC_300)
1338 ctrl |= SDHCI_CTRL_8BITBUS;
1339 } else {
1340 if (host->version >= SDHCI_SPEC_300)
1341 ctrl &= ~SDHCI_CTRL_8BITBUS;
1342 if (ios->bus_width == MMC_BUS_WIDTH_4)
1343 ctrl |= SDHCI_CTRL_4BITBUS;
1344 else
1345 ctrl &= ~SDHCI_CTRL_4BITBUS;
1346 }
1347 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1348 }
ae6d6c92 1349
15ec4461 1350 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
cd9277c0 1351
3ab9c8da
PR		 1352 if ((ios->timing == MMC_TIMING_SD_HS ||
1353 ios->timing == MMC_TIMING_MMC_HS)
1354 && !(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT))
cd9277c0
PO		 1355 ctrl |= SDHCI_CTRL_HISPD;
1356 else
1357 ctrl &= ~SDHCI_CTRL_HISPD;
1358
d6d50a15 1359 if (host->version >= SDHCI_SPEC_300) {
49c468fc
AN		 1360 u16 clk, ctrl_2;
1361 unsigned int clock;
1362
1363 /* In case of UHS-I modes, set High Speed Enable */
1364 if ((ios->timing == MMC_TIMING_UHS_SDR50) ||
1365 (ios->timing == MMC_TIMING_UHS_SDR104) ||
1366 (ios->timing == MMC_TIMING_UHS_DDR50) ||
1367 (ios->timing == MMC_TIMING_UHS_SDR25) ||
1368 (ios->timing == MMC_TIMING_UHS_SDR12))
1369 ctrl |= SDHCI_CTRL_HISPD;
d6d50a15
AN		 1370
1371 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1372 if (!(ctrl_2 & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
758535c4 1373 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d6d50a15
AN		 1374 /*
1375 * We only need to set Driver Strength if the
1376 * preset value enable is not set.
1377 */
1378 ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK;
1379 if (ios->drv_type == MMC_SET_DRIVER_TYPE_A)
1380 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A;
1381 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C)
1382 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C;
1383
1384 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
758535c4
AN		 1385 } else {
1386 /*
1387 * According to SDHC Spec v3.00, if the Preset Value
1388 * Enable in the Host Control 2 register is set, we
1389 * need to reset SD Clock Enable before changing High
1390 * Speed Enable to avoid generating clock gliches.
1391 */
758535c4
AN		 1392
1393 /* Reset SD Clock Enable */
1394 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1395 clk &= ~SDHCI_CLOCK_CARD_EN;
1396 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1397
1398 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1399
1400 /* Re-enable SD Clock */
1401 clock = host->clock;
1402 host->clock = 0;
1403 sdhci_set_clock(host, clock);
d6d50a15 1404 }
49c468fc 1405
49c468fc
AN		 1406
1407 /* Reset SD Clock Enable */
1408 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1409 clk &= ~SDHCI_CLOCK_CARD_EN;
1410 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1411
6322cdd0
PR		 1412 if (host->ops->set_uhs_signaling)
1413 host->ops->set_uhs_signaling(host, ios->timing);
1414 else {
1415 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1416 /* Select Bus Speed Mode for host */
1417 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
1418 if (ios->timing == MMC_TIMING_UHS_SDR12)
1419 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
1420 else if (ios->timing == MMC_TIMING_UHS_SDR25)
1421 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
1422 else if (ios->timing == MMC_TIMING_UHS_SDR50)
1423 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
1424 else if (ios->timing == MMC_TIMING_UHS_SDR104)
1425 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
1426 else if (ios->timing == MMC_TIMING_UHS_DDR50)
1427 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
1428 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1429 }
49c468fc
AN		 1430
1431 /* Re-enable SD Clock */
1432 clock = host->clock;
1433 host->clock = 0;
1434 sdhci_set_clock(host, clock);
758535c4
AN		 1435 } else
1436 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d6d50a15 1437
b8352260
LD		 1438 /*
1439 * Some (ENE) controllers go apeshit on some ios operation,
1440 * signalling timeout and CRC errors even on CMD0. Resetting
1441 * it on each ios seems to solve the problem.
1442 */
b8c86fc5 1443 if(host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
b8352260
LD		 1444 sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
1445
1e72859e 1446out:
5f25a66f 1447 mmiowb();
d129bceb
PO		 1448 spin_unlock_irqrestore(&host->lock, flags);
1449}
1450
66fd8ad5
AH		 1451static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1452{
1453 struct sdhci_host *host = mmc_priv(mmc);
1454
1455 sdhci_runtime_pm_get(host);
1456 sdhci_do_set_ios(host, ios);
1457 sdhci_runtime_pm_put(host);
1458}
1459
1460static int sdhci_check_ro(struct sdhci_host *host)
d129bceb 1461{
d129bceb 1462 unsigned long flags;
2dfb579c 1463 int is_readonly;
d129bceb 1464
d129bceb
PO		 1465 spin_lock_irqsave(&host->lock, flags);
1466
1e72859e 1467 if (host->flags & SDHCI_DEVICE_DEAD)
2dfb579c
WS		 1468 is_readonly = 0;
1469 else if (host->ops->get_ro)
1470 is_readonly = host->ops->get_ro(host);
1e72859e 1471 else
2dfb579c
WS		 1472 is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE)
1473 & SDHCI_WRITE_PROTECT);
d129bceb
PO		 1474
1475 spin_unlock_irqrestore(&host->lock, flags);
1476
2dfb579c
WS		 1477 /* This quirk needs to be replaced by a callback-function later */
1478 return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ?
1479 !is_readonly : is_readonly;
d129bceb
PO		 1480}
1481
82b0e23a
TI		 1482#define SAMPLE_COUNT 5
1483
66fd8ad5 1484static int sdhci_do_get_ro(struct sdhci_host *host)
82b0e23a 1485{
82b0e23a
TI		 1486 int i, ro_count;
1487
82b0e23a 1488 if (!(host->quirks & SDHCI_QUIRK_UNSTABLE_RO_DETECT))
66fd8ad5 1489 return sdhci_check_ro(host);
82b0e23a
TI		 1490
1491 ro_count = 0;
1492 for (i = 0; i < SAMPLE_COUNT; i++) {
66fd8ad5 1493 if (sdhci_check_ro(host)) {
82b0e23a
TI		 1494 if (++ro_count > SAMPLE_COUNT / 2)
1495 return 1;
1496 }
1497 msleep(30);
1498 }
1499 return 0;
1500}
1501
20758b66
AH		 1502static void sdhci_hw_reset(struct mmc_host *mmc)
1503{
1504 struct sdhci_host *host = mmc_priv(mmc);
1505
1506 if (host->ops && host->ops->hw_reset)
1507 host->ops->hw_reset(host);
1508}
1509
66fd8ad5 1510static int sdhci_get_ro(struct mmc_host *mmc)
f75979b7 1511{
66fd8ad5
AH		 1512 struct sdhci_host *host = mmc_priv(mmc);
1513 int ret;
f75979b7 1514
66fd8ad5
AH		 1515 sdhci_runtime_pm_get(host);
1516 ret = sdhci_do_get_ro(host);
1517 sdhci_runtime_pm_put(host);
1518 return ret;
1519}
f75979b7 1520
66fd8ad5
AH		 1521static void sdhci_enable_sdio_irq_nolock(struct sdhci_host *host, int enable)
1522{
1e72859e
PO		 1523 if (host->flags & SDHCI_DEVICE_DEAD)
1524 goto out;
1525
66fd8ad5
AH		 1526 if (enable)
1527 host->flags |= SDHCI_SDIO_IRQ_ENABLED;
1528 else
1529 host->flags &= ~SDHCI_SDIO_IRQ_ENABLED;
1530
1531 /* SDIO IRQ will be enabled as appropriate in runtime resume */
1532 if (host->runtime_suspended)
1533 goto out;
1534
f75979b7 1535 if (enable)
7260cf5e
AV		 1536 sdhci_unmask_irqs(host, SDHCI_INT_CARD_INT);
1537 else
1538 sdhci_mask_irqs(host, SDHCI_INT_CARD_INT);
1e72859e 1539out:
f75979b7 1540 mmiowb();
66fd8ad5
AH		 1541}
1542
1543static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1544{
1545 struct sdhci_host *host = mmc_priv(mmc);
1546 unsigned long flags;
f75979b7 1547
66fd8ad5
AH		 1548 spin_lock_irqsave(&host->lock, flags);
1549 sdhci_enable_sdio_irq_nolock(host, enable);
f75979b7
PO		 1550 spin_unlock_irqrestore(&host->lock, flags);
1551}
1552
66fd8ad5
AH		 1553static int sdhci_do_start_signal_voltage_switch(struct sdhci_host *host,
1554 struct mmc_ios *ios)
f2119df6 1555{
f2119df6
AN		 1556 u8 pwr;
1557 u16 clk, ctrl;
1558 u32 present_state;
1559
f2119df6
AN		 1560 /*
1561 * Signal Voltage Switching is only applicable for Host Controllers
1562 * v3.00 and above.
1563 */
1564 if (host->version < SDHCI_SPEC_300)
1565 return 0;
1566
1567 /*
1568 * We first check whether the request is to set signalling voltage
1569 * to 3.3V. If so, we change the voltage to 3.3V and return quickly.
1570 */
1571 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1572 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) {
1573 /* Set 1.8V Signal Enable in the Host Control2 register to 0 */
1574 ctrl &= ~SDHCI_CTRL_VDD_180;
1575 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1576
1577 /* Wait for 5ms */
1578 usleep_range(5000, 5500);
1579
1580 /* 3.3V regulator output should be stable within 5 ms */
1581 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1582 if (!(ctrl & SDHCI_CTRL_VDD_180))
1583 return 0;
1584 else {
a3c76eb9 1585 pr_info(DRIVER_NAME ": Switching to 3.3V "
f2119df6
AN		 1586 "signalling voltage failed\n");
1587 return -EIO;
1588 }
1589 } else if (!(ctrl & SDHCI_CTRL_VDD_180) &&
1590 (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180)) {
1591 /* Stop SDCLK */
1592 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1593 clk &= ~SDHCI_CLOCK_CARD_EN;
1594 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1595
1596 /* Check whether DAT[3:0] is 0000 */
1597 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
1598 if (!((present_state & SDHCI_DATA_LVL_MASK) >>
1599 SDHCI_DATA_LVL_SHIFT)) {
1600 /*
1601 * Enable 1.8V Signal Enable in the Host Control2
1602 * register
1603 */
1604 ctrl |= SDHCI_CTRL_VDD_180;
1605 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1606
1607 /* Wait for 5ms */
1608 usleep_range(5000, 5500);
1609
1610 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1611 if (ctrl & SDHCI_CTRL_VDD_180) {
1612 /* Provide SDCLK again and wait for 1ms*/
1613 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1614 clk |= SDHCI_CLOCK_CARD_EN;
1615 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1616 usleep_range(1000, 1500);
1617
1618 /*
1619 * If DAT[3:0] level is 1111b, then the card
1620 * was successfully switched to 1.8V signaling.
1621 */
1622 present_state = sdhci_readl(host,
1623 SDHCI_PRESENT_STATE);
1624 if ((present_state & SDHCI_DATA_LVL_MASK) ==
1625 SDHCI_DATA_LVL_MASK)
1626 return 0;
1627 }
1628 }
1629
1630 /*
1631 * If we are here, that means the switch to 1.8V signaling
1632 * failed. We power cycle the card, and retry initialization
1633 * sequence by setting S18R to 0.
1634 */
1635 pwr = sdhci_readb(host, SDHCI_POWER_CONTROL);
1636 pwr &= ~SDHCI_POWER_ON;
1637 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1638
1639 /* Wait for 1ms as per the spec */
1640 usleep_range(1000, 1500);
1641 pwr |= SDHCI_POWER_ON;
1642 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1643
a3c76eb9 1644 pr_info(DRIVER_NAME ": Switching to 1.8V signalling "
f2119df6
AN		 1645 "voltage failed, retrying with S18R set to 0\n");
1646 return -EAGAIN;
1647 } else
1648 /* No signal voltage switch required */
1649 return 0;
1650}
1651
66fd8ad5
AH		 1652static int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
1653 struct mmc_ios *ios)
1654{
1655 struct sdhci_host *host = mmc_priv(mmc);
1656 int err;
1657
1658 if (host->version < SDHCI_SPEC_300)
1659 return 0;
1660 sdhci_runtime_pm_get(host);
1661 err = sdhci_do_start_signal_voltage_switch(host, ios);
1662 sdhci_runtime_pm_put(host);
1663 return err;
1664}
1665
b513ea25
AN		 1666static int sdhci_execute_tuning(struct mmc_host *mmc)
1667{
1668 struct sdhci_host *host;
1669 u16 ctrl;
1670 u32 ier;
1671 int tuning_loop_counter = MAX_TUNING_LOOP;
1672 unsigned long timeout;
1673 int err = 0;
1674
1675 host = mmc_priv(mmc);
1676
66fd8ad5 1677 sdhci_runtime_pm_get(host);
b513ea25
AN		 1678 disable_irq(host->irq);
1679 spin_lock(&host->lock);
1680
1681 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1682
1683 /*
1684 * Host Controller needs tuning only in case of SDR104 mode
1685 * and for SDR50 mode when Use Tuning for SDR50 is set in
1686 * Capabilities register.
1687 */
1688 if (((ctrl & SDHCI_CTRL_UHS_MASK) == SDHCI_CTRL_UHS_SDR104) ||
1689 (((ctrl & SDHCI_CTRL_UHS_MASK) == SDHCI_CTRL_UHS_SDR50) &&
1690 (host->flags & SDHCI_SDR50_NEEDS_TUNING)))
1691 ctrl |= SDHCI_CTRL_EXEC_TUNING;
1692 else {
1693 spin_unlock(&host->lock);
1694 enable_irq(host->irq);
66fd8ad5 1695 sdhci_runtime_pm_put(host);
b513ea25
AN		 1696 return 0;
1697 }
1698
1699 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1700
1701 /*
1702 * As per the Host Controller spec v3.00, tuning command
1703 * generates Buffer Read Ready interrupt, so enable that.
1704 *
1705 * Note: The spec clearly says that when tuning sequence
1706 * is being performed, the controller does not generate
1707 * interrupts other than Buffer Read Ready interrupt. But
1708 * to make sure we don't hit a controller bug, we _only_
1709 * enable Buffer Read Ready interrupt here.
1710 */
1711 ier = sdhci_readl(host, SDHCI_INT_ENABLE);
1712 sdhci_clear_set_irqs(host, ier, SDHCI_INT_DATA_AVAIL);
1713
1714 /*
1715 * Issue CMD19 repeatedly till Execute Tuning is set to 0 or the number
1716 * of loops reaches 40 times or a timeout of 150ms occurs.
1717 */
1718 timeout = 150;
1719 do {
1720 struct mmc_command cmd = {0};
66fd8ad5 1721 struct mmc_request mrq = {NULL};
b513ea25
AN		 1722
1723 if (!tuning_loop_counter && !timeout)
1724 break;
1725
1726 cmd.opcode = MMC_SEND_TUNING_BLOCK;
1727 cmd.arg = 0;
1728 cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
1729 cmd.retries = 0;
1730 cmd.data = NULL;
1731 cmd.error = 0;
1732
1733 mrq.cmd = &cmd;
1734 host->mrq = &mrq;
1735
1736 /*
1737 * In response to CMD19, the card sends 64 bytes of tuning
1738 * block to the Host Controller. So we set the block size
1739 * to 64 here.
1740 */
1741 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64), SDHCI_BLOCK_SIZE);
1742
1743 /*
1744 * The tuning block is sent by the card to the host controller.
1745 * So we set the TRNS_READ bit in the Transfer Mode register.
1746 * This also takes care of setting DMA Enable and Multi Block
1747 * Select in the same register to 0.
1748 */
1749 sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
1750
1751 sdhci_send_command(host, &cmd);
1752
1753 host->cmd = NULL;
1754 host->mrq = NULL;
1755
1756 spin_unlock(&host->lock);
1757 enable_irq(host->irq);
1758
1759 /* Wait for Buffer Read Ready interrupt */
1760 wait_event_interruptible_timeout(host->buf_ready_int,
1761 (host->tuning_done == 1),
1762 msecs_to_jiffies(50));
1763 disable_irq(host->irq);
1764 spin_lock(&host->lock);
1765
1766 if (!host->tuning_done) {
a3c76eb9 1767 pr_info(DRIVER_NAME ": Timeout waiting for "
b513ea25
AN		 1768 "Buffer Read Ready interrupt during tuning "
1769 "procedure, falling back to fixed sampling "
1770 "clock\n");
1771 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1772 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
1773 ctrl &= ~SDHCI_CTRL_EXEC_TUNING;
1774 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1775
1776 err = -EIO;
1777 goto out;
1778 }
1779
1780 host->tuning_done = 0;
1781
1782 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1783 tuning_loop_counter--;
1784 timeout--;
1785 mdelay(1);
1786 } while (ctrl & SDHCI_CTRL_EXEC_TUNING);
1787
1788 /*
1789 * The Host Driver has exhausted the maximum number of loops allowed,
1790 * so use fixed sampling frequency.
1791 */
1792 if (!tuning_loop_counter || !timeout) {
1793 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
1794 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1795 } else {
1796 if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) {
a3c76eb9 1797 pr_info(DRIVER_NAME ": Tuning procedure"
b513ea25
AN		 1798 " failed, falling back to fixed sampling"
1799 " clock\n");
1800 err = -EIO;
1801 }
1802 }
1803
1804out:
cf2b5eea
AN		 1805 /*
1806 * If this is the very first time we are here, we start the retuning
1807 * timer. Since only during the first time, SDHCI_NEEDS_RETUNING
1808 * flag won't be set, we check this condition before actually starting
1809 * the timer.
1810 */
1811 if (!(host->flags & SDHCI_NEEDS_RETUNING) && host->tuning_count &&
1812 (host->tuning_mode == SDHCI_TUNING_MODE_1)) {
1813 mod_timer(&host->tuning_timer, jiffies +
1814 host->tuning_count * HZ);
1815 /* Tuning mode 1 limits the maximum data length to 4MB */
1816 mmc->max_blk_count = (4 * 1024 * 1024) / mmc->max_blk_size;
1817 } else {
1818 host->flags &= ~SDHCI_NEEDS_RETUNING;
1819 /* Reload the new initial value for timer */
1820 if (host->tuning_mode == SDHCI_TUNING_MODE_1)
1821 mod_timer(&host->tuning_timer, jiffies +
1822 host->tuning_count * HZ);
1823 }
1824
1825 /*
1826 * In case tuning fails, host controllers which support re-tuning can
1827 * try tuning again at a later time, when the re-tuning timer expires.
1828 * So for these controllers, we return 0. Since there might be other
1829 * controllers who do not have this capability, we return error for
1830 * them.
1831 */
1832 if (err && host->tuning_count &&
1833 host->tuning_mode == SDHCI_TUNING_MODE_1)
1834 err = 0;
1835
b513ea25
AN		 1836 sdhci_clear_set_irqs(host, SDHCI_INT_DATA_AVAIL, ier);
1837 spin_unlock(&host->lock);
1838 enable_irq(host->irq);
66fd8ad5 1839 sdhci_runtime_pm_put(host);
b513ea25
AN		 1840
1841 return err;
1842}
1843
66fd8ad5 1844static void sdhci_do_enable_preset_value(struct sdhci_host *host, bool enable)
4d55c5a1 1845{
4d55c5a1
AN		 1846 u16 ctrl;
1847 unsigned long flags;
1848
4d55c5a1
AN		 1849 /* Host Controller v3.00 defines preset value registers */
1850 if (host->version < SDHCI_SPEC_300)
1851 return;
1852
1853 spin_lock_irqsave(&host->lock, flags);
1854
1855 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1856
1857 /*
1858 * We only enable or disable Preset Value if they are not already
1859 * enabled or disabled respectively. Otherwise, we bail out.
1860 */
1861 if (enable && !(ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
1862 ctrl |= SDHCI_CTRL_PRESET_VAL_ENABLE;
1863 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
66fd8ad5 1864 host->flags |= SDHCI_PV_ENABLED;
4d55c5a1
AN		 1865 } else if (!enable && (ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
1866 ctrl &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
1867 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
66fd8ad5 1868 host->flags &= ~SDHCI_PV_ENABLED;
4d55c5a1
AN		 1869 }
1870
1871 spin_unlock_irqrestore(&host->lock, flags);
1872}
1873
66fd8ad5
AH		 1874static void sdhci_enable_preset_value(struct mmc_host *mmc, bool enable)
1875{
1876 struct sdhci_host *host = mmc_priv(mmc);
1877
1878 sdhci_runtime_pm_get(host);
1879 sdhci_do_enable_preset_value(host, enable);
1880 sdhci_runtime_pm_put(host);
1881}
1882
ab7aefd0 1883static const struct mmc_host_ops sdhci_ops = {
d129bceb
PO		 1884 .request = sdhci_request,
1885 .set_ios = sdhci_set_ios,
1886 .get_ro = sdhci_get_ro,
20758b66 1887 .hw_reset = sdhci_hw_reset,
f75979b7 1888 .enable_sdio_irq = sdhci_enable_sdio_irq,
f2119df6 1889 .start_signal_voltage_switch = sdhci_start_signal_voltage_switch,
b513ea25 1890 .execute_tuning = sdhci_execute_tuning,
4d55c5a1 1891 .enable_preset_value = sdhci_enable_preset_value,
d129bceb
PO		 1892};
1893
1894/*****************************************************************************\
1895 * *
1896 * Tasklets *
1897 * *
1898\*****************************************************************************/
1899
1900static void sdhci_tasklet_card(unsigned long param)
1901{
1902 struct sdhci_host *host;
1903 unsigned long flags;
1904
1905 host = (struct sdhci_host*)param;
1906
1907 spin_lock_irqsave(&host->lock, flags);
1908
66fd8ad5
AH		 1909 /* Check host->mrq first in case we are runtime suspended */
1910 if (host->mrq &&
1911 !(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) {
a3c76eb9 1912 pr_err("%s: Card removed during transfer!\n",
66fd8ad5 1913 mmc_hostname(host->mmc));
a3c76eb9 1914 pr_err("%s: Resetting controller.\n",
66fd8ad5 1915 mmc_hostname(host->mmc));
d129bceb 1916
66fd8ad5
AH		 1917 sdhci_reset(host, SDHCI_RESET_CMD);
1918 sdhci_reset(host, SDHCI_RESET_DATA);
d129bceb 1919
66fd8ad5
AH		 1920 host->mrq->cmd->error = -ENOMEDIUM;
1921 tasklet_schedule(&host->finish_tasklet);
d129bceb
PO		 1922 }
1923
1924 spin_unlock_irqrestore(&host->lock, flags);
1925
04cf585d 1926 mmc_detect_change(host->mmc, msecs_to_jiffies(200));
d129bceb
PO		 1927}
1928
1929static void sdhci_tasklet_finish(unsigned long param)
1930{
1931 struct sdhci_host *host;
1932 unsigned long flags;
1933 struct mmc_request *mrq;
1934
1935 host = (struct sdhci_host*)param;
1936
66fd8ad5
AH		 1937 spin_lock_irqsave(&host->lock, flags);
1938
0c9c99a7
CB		 1939 /*
1940 * If this tasklet gets rescheduled while running, it will
1941 * be run again afterwards but without any active request.
1942 */
66fd8ad5
AH		 1943 if (!host->mrq) {
1944 spin_unlock_irqrestore(&host->lock, flags);
0c9c99a7 1945 return;
66fd8ad5 1946 }
d129bceb
PO		 1947
1948 del_timer(&host->timer);
1949
1950 mrq = host->mrq;
1951
d129bceb
PO		 1952 /*
1953 * The controller needs a reset of internal state machines
1954 * upon error conditions.
1955 */
1e72859e 1956 if (!(host->flags & SDHCI_DEVICE_DEAD) &&
b7b4d342 1957 ((mrq->cmd && mrq->cmd->error) ||
1e72859e
PO		 1958 (mrq->data && (mrq->data->error ||
1959 (mrq->data->stop && mrq->data->stop->error))) ||
1960 (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) {
645289dc
PO		 1961
1962 /* Some controllers need this kick or reset won't work here */
b8c86fc5 1963 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET) {
645289dc
PO		 1964 unsigned int clock;
1965
1966 /* This is to force an update */
1967 clock = host->clock;
1968 host->clock = 0;
1969 sdhci_set_clock(host, clock);
1970 }
1971
1972 /* Spec says we should do both at the same time, but Ricoh
1973 controllers do not like that. */
d129bceb
PO		 1974 sdhci_reset(host, SDHCI_RESET_CMD);
1975 sdhci_reset(host, SDHCI_RESET_DATA);
1976 }
1977
1978 host->mrq = NULL;
1979 host->cmd = NULL;
1980 host->data = NULL;
1981
f9134319 1982#ifndef SDHCI_USE_LEDS_CLASS
d129bceb 1983 sdhci_deactivate_led(host);
2f730fec 1984#endif
d129bceb 1985
5f25a66f 1986 mmiowb();
d129bceb
PO		 1987 spin_unlock_irqrestore(&host->lock, flags);
1988
1989 mmc_request_done(host->mmc, mrq);
66fd8ad5 1990 sdhci_runtime_pm_put(host);
d129bceb
PO		 1991}
1992
1993static void sdhci_timeout_timer(unsigned long data)
1994{
1995 struct sdhci_host *host;
1996 unsigned long flags;
1997
1998 host = (struct sdhci_host*)data;
1999
2000 spin_lock_irqsave(&host->lock, flags);
2001
2002 if (host->mrq) {
a3c76eb9 2003 pr_err("%s: Timeout waiting for hardware "
acf1da45 2004 "interrupt.\n", mmc_hostname(host->mmc));
d129bceb
PO		 2005 sdhci_dumpregs(host);
2006
2007 if (host->data) {
17b0429d 2008 host->data->error = -ETIMEDOUT;
d129bceb
PO		 2009 sdhci_finish_data(host);
2010 } else {
2011 if (host->cmd)
17b0429d 2012 host->cmd->error = -ETIMEDOUT;
d129bceb 2013 else
17b0429d 2014 host->mrq->cmd->error = -ETIMEDOUT;
d129bceb
PO		 2015
2016 tasklet_schedule(&host->finish_tasklet);
2017 }
2018 }
2019
5f25a66f 2020 mmiowb();
d129bceb
PO		 2021 spin_unlock_irqrestore(&host->lock, flags);
2022}
2023
cf2b5eea
AN		 2024static void sdhci_tuning_timer(unsigned long data)
2025{
2026 struct sdhci_host *host;
2027 unsigned long flags;
2028
2029 host = (struct sdhci_host *)data;
2030
2031 spin_lock_irqsave(&host->lock, flags);
2032
2033 host->flags |= SDHCI_NEEDS_RETUNING;
2034
2035 spin_unlock_irqrestore(&host->lock, flags);
2036}
2037
d129bceb
PO		 2038/*****************************************************************************\
2039 * *
2040 * Interrupt handling *
2041 * *
2042\*****************************************************************************/
2043
2044static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask)
2045{
2046 BUG_ON(intmask == 0);
2047
2048 if (!host->cmd) {
a3c76eb9 2049 pr_err("%s: Got command interrupt 0x%08x even "
b67ac3f3
PO		 2050 "though no command operation was in progress.\n",
2051 mmc_hostname(host->mmc), (unsigned)intmask);
d129bceb
PO		 2052 sdhci_dumpregs(host);
2053 return;
2054 }
2055
43b58b36 2056 if (intmask & SDHCI_INT_TIMEOUT)
17b0429d
PO		 2057 host->cmd->error = -ETIMEDOUT;
2058 else if (intmask & (SDHCI_INT_CRC | SDHCI_INT_END_BIT |
2059 SDHCI_INT_INDEX))
2060 host->cmd->error = -EILSEQ;
43b58b36 2061
e809517f 2062 if (host->cmd->error) {
d129bceb 2063 tasklet_schedule(&host->finish_tasklet);
e809517f
PO		 2064 return;
2065 }
2066
2067 /*
2068 * The host can send and interrupt when the busy state has
2069 * ended, allowing us to wait without wasting CPU cycles.
2070 * Unfortunately this is overloaded on the "data complete"
2071 * interrupt, so we need to take some care when handling
2072 * it.
2073 *
2074 * Note: The 1.0 specification is a bit ambiguous about this
2075 * feature so there might be some problems with older
2076 * controllers.
2077 */
2078 if (host->cmd->flags & MMC_RSP_BUSY) {
2079 if (host->cmd->data)
2080 DBG("Cannot wait for busy signal when also "
2081 "doing a data transfer");
f945405c 2082 else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ))
e809517f 2083 return;
f945405c
BD		 2084
2085 /* The controller does not support the end-of-busy IRQ,
2086 * fall through and take the SDHCI_INT_RESPONSE */
e809517f
PO		 2087 }
2088
2089 if (intmask & SDHCI_INT_RESPONSE)
43b58b36 2090 sdhci_finish_command(host);
d129bceb
PO		 2091}
2092
0957c333 2093#ifdef CONFIG_MMC_DEBUG
6882a8c0
BD		 2094static void sdhci_show_adma_error(struct sdhci_host *host)
2095{
2096 const char *name = mmc_hostname(host->mmc);
2097 u8 *desc = host->adma_desc;
2098 __le32 *dma;
2099 __le16 *len;
2100 u8 attr;
2101
2102 sdhci_dumpregs(host);
2103
2104 while (true) {
2105 dma = (__le32 *)(desc + 4);
2106 len = (__le16 *)(desc + 2);
2107 attr = *desc;
2108
2109 DBG("%s: %p: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n",
2110 name, desc, le32_to_cpu(*dma), le16_to_cpu(*len), attr);
2111
2112 desc += 8;
2113
2114 if (attr & 2)
2115 break;
2116 }
2117}
2118#else
2119static void sdhci_show_adma_error(struct sdhci_host *host) { }
2120#endif
2121
d129bceb
PO		 2122static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
2123{
2124 BUG_ON(intmask == 0);
2125
b513ea25
AN		 2126 /* CMD19 generates _only_ Buffer Read Ready interrupt */
2127 if (intmask & SDHCI_INT_DATA_AVAIL) {
2128 if (SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND)) ==
2129 MMC_SEND_TUNING_BLOCK) {
2130 host->tuning_done = 1;
2131 wake_up(&host->buf_ready_int);
2132 return;
2133 }
2134 }
2135
d129bceb
PO		 2136 if (!host->data) {
2137 /*
e809517f
PO		 2138 * The "data complete" interrupt is also used to
2139 * indicate that a busy state has ended. See comment
2140 * above in sdhci_cmd_irq().
d129bceb 2141 */
e809517f
PO		 2142 if (host->cmd && (host->cmd->flags & MMC_RSP_BUSY)) {
2143 if (intmask & SDHCI_INT_DATA_END) {
2144 sdhci_finish_command(host);
2145 return;
2146 }
2147 }
d129bceb 2148
a3c76eb9 2149 pr_err("%s: Got data interrupt 0x%08x even "
b67ac3f3
PO		 2150 "though no data operation was in progress.\n",
2151 mmc_hostname(host->mmc), (unsigned)intmask);
d129bceb
PO		 2152 sdhci_dumpregs(host);
2153
2154 return;
2155 }
2156
2157 if (intmask & SDHCI_INT_DATA_TIMEOUT)
17b0429d 2158 host->data->error = -ETIMEDOUT;
22113efd
AL		 2159 else if (intmask & SDHCI_INT_DATA_END_BIT)
2160 host->data->error = -EILSEQ;
2161 else if ((intmask & SDHCI_INT_DATA_CRC) &&
2162 SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))
2163 != MMC_BUS_TEST_R)
17b0429d 2164 host->data->error = -EILSEQ;
6882a8c0 2165 else if (intmask & SDHCI_INT_ADMA_ERROR) {
a3c76eb9 2166 pr_err("%s: ADMA error\n", mmc_hostname(host->mmc));
6882a8c0 2167 sdhci_show_adma_error(host);
2134a922 2168 host->data->error = -EIO;
6882a8c0 2169 }
d129bceb 2170
17b0429d 2171 if (host->data->error)
d129bceb
PO		 2172 sdhci_finish_data(host);
2173 else {
a406f5a3 2174 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
d129bceb
PO		 2175 sdhci_transfer_pio(host);
2176
6ba736a1
PO		 2177 /*
2178 * We currently don't do anything fancy with DMA
2179 * boundaries, but as we can't disable the feature
2180 * we need to at least restart the transfer.
f6a03cbf
MV		 2181 *
2182 * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS)
2183 * should return a valid address to continue from, but as
2184 * some controllers are faulty, don't trust them.
6ba736a1 2185 */
f6a03cbf
MV		 2186 if (intmask & SDHCI_INT_DMA_END) {
2187 u32 dmastart, dmanow;
2188 dmastart = sg_dma_address(host->data->sg);
2189 dmanow = dmastart + host->data->bytes_xfered;
2190 /*
2191 * Force update to the next DMA block boundary.
2192 */
2193 dmanow = (dmanow &
2194 ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) +
2195 SDHCI_DEFAULT_BOUNDARY_SIZE;
2196 host->data->bytes_xfered = dmanow - dmastart;
2197 DBG("%s: DMA base 0x%08x, transferred 0x%06x bytes,"
2198 " next 0x%08x\n",
2199 mmc_hostname(host->mmc), dmastart,
2200 host->data->bytes_xfered, dmanow);
2201 sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS);
2202 }
6ba736a1 2203
e538fbe8
PO		 2204 if (intmask & SDHCI_INT_DATA_END) {
2205 if (host->cmd) {
2206 /*
2207 * Data managed to finish before the
2208 * command completed. Make sure we do
2209 * things in the proper order.
2210 */
2211 host->data_early = 1;
2212 } else {
2213 sdhci_finish_data(host);
2214 }
2215 }
d129bceb
PO		 2216 }
2217}
2218
7d12e780 2219static irqreturn_t sdhci_irq(int irq, void *dev_id)
d129bceb
PO		 2220{
2221 irqreturn_t result;
66fd8ad5 2222 struct sdhci_host *host = dev_id;
d129bceb 2223 u32 intmask;
f75979b7 2224 int cardint = 0;
d129bceb
PO		 2225
2226 spin_lock(&host->lock);
2227
66fd8ad5
AH		 2228 if (host->runtime_suspended) {
2229 spin_unlock(&host->lock);
a3c76eb9 2230 pr_warning("%s: got irq while runtime suspended\n",
66fd8ad5
AH		 2231 mmc_hostname(host->mmc));
2232 return IRQ_HANDLED;
2233 }
2234
4e4141a5 2235 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
d129bceb 2236
62df67a5 2237 if (!intmask || intmask == 0xffffffff) {
d129bceb
PO		 2238 result = IRQ_NONE;
2239 goto out;
2240 }
2241
b69c9058
PO		 2242 DBG("*** %s got interrupt: 0x%08x\n",
2243 mmc_hostname(host->mmc), intmask);
d129bceb 2244
3192a28f 2245 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
d25928d1
SG		 2246 u32 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
2247 SDHCI_CARD_PRESENT;
2248
2249 /*
2250 * There is a observation on i.mx esdhc. INSERT bit will be
2251 * immediately set again when it gets cleared, if a card is
2252 * inserted. We have to mask the irq to prevent interrupt
2253 * storm which will freeze the system. And the REMOVE gets
2254 * the same situation.
2255 *
2256 * More testing are needed here to ensure it works for other
2257 * platforms though.
2258 */
2259 sdhci_mask_irqs(host, present ? SDHCI_INT_CARD_INSERT :
2260 SDHCI_INT_CARD_REMOVE);
2261 sdhci_unmask_irqs(host, present ? SDHCI_INT_CARD_REMOVE :
2262 SDHCI_INT_CARD_INSERT);
2263
4e4141a5 2264 sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT |
d25928d1
SG		 2265 SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS);
2266 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE);
d129bceb 2267 tasklet_schedule(&host->card_tasklet);
3192a28f 2268 }
d129bceb 2269
3192a28f 2270 if (intmask & SDHCI_INT_CMD_MASK) {
4e4141a5
AV		 2271 sdhci_writel(host, intmask & SDHCI_INT_CMD_MASK,
2272 SDHCI_INT_STATUS);
3192a28f 2273 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK);
d129bceb
PO		 2274 }
2275
2276 if (intmask & SDHCI_INT_DATA_MASK) {
4e4141a5
AV		 2277 sdhci_writel(host, intmask & SDHCI_INT_DATA_MASK,
2278 SDHCI_INT_STATUS);
3192a28f 2279 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
d129bceb
PO		 2280 }
2281
2282 intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK);
2283
964f9ce2
PO		 2284 intmask &= ~SDHCI_INT_ERROR;
2285
d129bceb 2286 if (intmask & SDHCI_INT_BUS_POWER) {
a3c76eb9 2287 pr_err("%s: Card is consuming too much power!\n",
d129bceb 2288 mmc_hostname(host->mmc));
4e4141a5 2289 sdhci_writel(host, SDHCI_INT_BUS_POWER, SDHCI_INT_STATUS);
d129bceb
PO		 2290 }
2291
9d26a5d3 2292 intmask &= ~SDHCI_INT_BUS_POWER;
3192a28f 2293
f75979b7
PO		 2294 if (intmask & SDHCI_INT_CARD_INT)
2295 cardint = 1;
2296
2297 intmask &= ~SDHCI_INT_CARD_INT;
2298
3192a28f 2299 if (intmask) {
a3c76eb9 2300 pr_err("%s: Unexpected interrupt 0x%08x.\n",
3192a28f 2301 mmc_hostname(host->mmc), intmask);
d129bceb
PO		 2302 sdhci_dumpregs(host);
2303
4e4141a5 2304 sdhci_writel(host, intmask, SDHCI_INT_STATUS);
3192a28f 2305 }
d129bceb
PO		 2306
2307 result = IRQ_HANDLED;
2308
5f25a66f 2309 mmiowb();
d129bceb
PO		 2310out:
2311 spin_unlock(&host->lock);
2312
f75979b7
PO		 2313 /*
2314 * We have to delay this as it calls back into the driver.
2315 */
2316 if (cardint)
2317 mmc_signal_sdio_irq(host->mmc);
2318
d129bceb
PO		 2319 return result;
2320}
2321
2322/*****************************************************************************\
2323 * *
2324 * Suspend/resume *
2325 * *
2326\*****************************************************************************/
2327
2328#ifdef CONFIG_PM
2329
29495aa0 2330int sdhci_suspend_host(struct sdhci_host *host)
d129bceb 2331{
b8c86fc5 2332 int ret;
a715dfc7 2333
7260cf5e
AV		 2334 sdhci_disable_card_detection(host);
2335
cf2b5eea
AN		 2336 /* Disable tuning since we are suspending */
2337 if (host->version >= SDHCI_SPEC_300 && host->tuning_count &&
2338 host->tuning_mode == SDHCI_TUNING_MODE_1) {
2339 host->flags &= ~SDHCI_NEEDS_RETUNING;
2340 mod_timer(&host->tuning_timer, jiffies +
2341 host->tuning_count * HZ);
2342 }
2343
1a13f8fa 2344 ret = mmc_suspend_host(host->mmc);
b8c86fc5
PO		 2345 if (ret)
2346 return ret;
a715dfc7 2347
b8c86fc5 2348 free_irq(host->irq, host);
d129bceb 2349
9bea3c85
MS		 2350 if (host->vmmc)
2351 ret = regulator_disable(host->vmmc);
2352
2353 return ret;
d129bceb
PO		 2354}
2355
b8c86fc5 2356EXPORT_SYMBOL_GPL(sdhci_suspend_host);
d129bceb 2357
b8c86fc5
PO		 2358int sdhci_resume_host(struct sdhci_host *host)
2359{
2360 int ret;
d129bceb 2361
9bea3c85
MS		 2362 if (host->vmmc) {
2363 int ret = regulator_enable(host->vmmc);
2364 if (ret)
2365 return ret;
2366 }
2367
a13abc7b 2368 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
b8c86fc5
PO		 2369 if (host->ops->enable_dma)
2370 host->ops->enable_dma(host);
2371 }
d129bceb 2372
b8c86fc5
PO		 2373 ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
2374 mmc_hostname(host->mmc), host);
df1c4b7b
PO		 2375 if (ret)
2376 return ret;
d129bceb 2377
2f4cbb3d 2378 sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER));
b8c86fc5
PO		 2379 mmiowb();
2380
2381 ret = mmc_resume_host(host->mmc);
7260cf5e
AV		 2382 sdhci_enable_card_detection(host);
2383
cf2b5eea
AN		 2384 /* Set the re-tuning expiration flag */
2385 if ((host->version >= SDHCI_SPEC_300) && host->tuning_count &&
2386 (host->tuning_mode == SDHCI_TUNING_MODE_1))
2387 host->flags |= SDHCI_NEEDS_RETUNING;
2388
2f4cbb3d 2389 return ret;
d129bceb
PO		 2390}
2391
b8c86fc5 2392EXPORT_SYMBOL_GPL(sdhci_resume_host);
d129bceb 2393
5f619704
DD		 2394void sdhci_enable_irq_wakeups(struct sdhci_host *host)
2395{
2396 u8 val;
2397 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2398 val |= SDHCI_WAKE_ON_INT;
2399 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2400}
2401
2402EXPORT_SYMBOL_GPL(sdhci_enable_irq_wakeups);
2403
d129bceb
PO		 2404#endif /* CONFIG_PM */
2405
66fd8ad5
AH		 2406#ifdef CONFIG_PM_RUNTIME
2407
2408static int sdhci_runtime_pm_get(struct sdhci_host *host)
2409{
2410 return pm_runtime_get_sync(host->mmc->parent);
2411}
2412
2413static int sdhci_runtime_pm_put(struct sdhci_host *host)
2414{
2415 pm_runtime_mark_last_busy(host->mmc->parent);
2416 return pm_runtime_put_autosuspend(host->mmc->parent);
2417}
2418
2419int sdhci_runtime_suspend_host(struct sdhci_host *host)
2420{
2421 unsigned long flags;
2422 int ret = 0;
2423
2424 /* Disable tuning since we are suspending */
2425 if (host->version >= SDHCI_SPEC_300 &&
2426 host->tuning_mode == SDHCI_TUNING_MODE_1) {
2427 del_timer_sync(&host->tuning_timer);
2428 host->flags &= ~SDHCI_NEEDS_RETUNING;
2429 }
2430
2431 spin_lock_irqsave(&host->lock, flags);
2432 sdhci_mask_irqs(host, SDHCI_INT_ALL_MASK);
2433 spin_unlock_irqrestore(&host->lock, flags);
2434
2435 synchronize_irq(host->irq);
2436
2437 spin_lock_irqsave(&host->lock, flags);
2438 host->runtime_suspended = true;
2439 spin_unlock_irqrestore(&host->lock, flags);
2440
2441 return ret;
2442}
2443EXPORT_SYMBOL_GPL(sdhci_runtime_suspend_host);
2444
2445int sdhci_runtime_resume_host(struct sdhci_host *host)
2446{
2447 unsigned long flags;
2448 int ret = 0, host_flags = host->flags;
2449
2450 if (host_flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2451 if (host->ops->enable_dma)
2452 host->ops->enable_dma(host);
2453 }
2454
2455 sdhci_init(host, 0);
2456
2457 /* Force clock and power re-program */
2458 host->pwr = 0;
2459 host->clock = 0;
2460 sdhci_do_set_ios(host, &host->mmc->ios);
2461
2462 sdhci_do_start_signal_voltage_switch(host, &host->mmc->ios);
2463 if (host_flags & SDHCI_PV_ENABLED)
2464 sdhci_do_enable_preset_value(host, true);
2465
2466 /* Set the re-tuning expiration flag */
2467 if ((host->version >= SDHCI_SPEC_300) && host->tuning_count &&
2468 (host->tuning_mode == SDHCI_TUNING_MODE_1))
2469 host->flags |= SDHCI_NEEDS_RETUNING;
2470
2471 spin_lock_irqsave(&host->lock, flags);
2472
2473 host->runtime_suspended = false;
2474
2475 /* Enable SDIO IRQ */
2476 if ((host->flags & SDHCI_SDIO_IRQ_ENABLED))
2477 sdhci_enable_sdio_irq_nolock(host, true);
2478
2479 /* Enable Card Detection */
2480 sdhci_enable_card_detection(host);
2481
2482 spin_unlock_irqrestore(&host->lock, flags);
2483
2484 return ret;
2485}
2486EXPORT_SYMBOL_GPL(sdhci_runtime_resume_host);
2487
2488#endif
2489
d129bceb
PO		 2490/*****************************************************************************\
2491 * *
b8c86fc5 2492 * Device allocation/registration *
d129bceb
PO		 2493 * *
2494\*****************************************************************************/
2495
b8c86fc5
PO		 2496struct sdhci_host *sdhci_alloc_host(struct device *dev,
2497 size_t priv_size)
d129bceb 2498{
d129bceb
PO		 2499 struct mmc_host *mmc;
2500 struct sdhci_host *host;
2501
b8c86fc5 2502 WARN_ON(dev == NULL);
d129bceb 2503
b8c86fc5 2504 mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev);
d129bceb 2505 if (!mmc)
b8c86fc5 2506 return ERR_PTR(-ENOMEM);
d129bceb
PO		 2507
2508 host = mmc_priv(mmc);
2509 host->mmc = mmc;
2510
b8c86fc5
PO		 2511 return host;
2512}
8a4da143 2513
b8c86fc5 2514EXPORT_SYMBOL_GPL(sdhci_alloc_host);
d129bceb 2515
b8c86fc5
PO		 2516int sdhci_add_host(struct sdhci_host *host)
2517{
2518 struct mmc_host *mmc;
f2119df6
AN		 2519 u32 caps[2];
2520 u32 max_current_caps;
2521 unsigned int ocr_avail;
b8c86fc5 2522 int ret;
d129bceb 2523
b8c86fc5
PO		 2524 WARN_ON(host == NULL);
2525 if (host == NULL)
2526 return -EINVAL;
d129bceb 2527
b8c86fc5 2528 mmc = host->mmc;
d129bceb 2529
b8c86fc5
PO		 2530 if (debug_quirks)
2531 host->quirks = debug_quirks;
66fd8ad5
AH		 2532 if (debug_quirks2)
2533 host->quirks2 = debug_quirks2;
d129bceb 2534
d96649ed
PO		 2535 sdhci_reset(host, SDHCI_RESET_ALL);
2536
4e4141a5 2537 host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
2134a922
PO		 2538 host->version = (host->version & SDHCI_SPEC_VER_MASK)
2539 >> SDHCI_SPEC_VER_SHIFT;
85105c53 2540 if (host->version > SDHCI_SPEC_300) {
a3c76eb9 2541 pr_err("%s: Unknown controller version (%d). "
b69c9058 2542 "You may experience problems.\n", mmc_hostname(mmc),
2134a922 2543 host->version);
4a965505
PO		 2544 }
2545
f2119df6 2546 caps[0] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ? host->caps :
ccc92c23 2547 sdhci_readl(host, SDHCI_CAPABILITIES);
d129bceb 2548
f2119df6
AN		 2549 caps[1] = (host->version >= SDHCI_SPEC_300) ?
2550 sdhci_readl(host, SDHCI_CAPABILITIES_1) : 0;
2551
b8c86fc5 2552 if (host->quirks & SDHCI_QUIRK_FORCE_DMA)
a13abc7b 2553 host->flags |= SDHCI_USE_SDMA;
f2119df6 2554 else if (!(caps[0] & SDHCI_CAN_DO_SDMA))
a13abc7b 2555 DBG("Controller doesn't have SDMA capability\n");
67435274 2556 else
a13abc7b 2557 host->flags |= SDHCI_USE_SDMA;
d129bceb 2558
b8c86fc5 2559 if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
a13abc7b 2560 (host->flags & SDHCI_USE_SDMA)) {
cee687ce 2561 DBG("Disabling DMA as it is marked broken\n");
a13abc7b 2562 host->flags &= ~SDHCI_USE_SDMA;
7c168e3d
FT		 2563 }
2564
f2119df6
AN		 2565 if ((host->version >= SDHCI_SPEC_200) &&
2566 (caps[0] & SDHCI_CAN_DO_ADMA2))
a13abc7b 2567 host->flags |= SDHCI_USE_ADMA;
2134a922
PO		 2568
2569 if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) &&
2570 (host->flags & SDHCI_USE_ADMA)) {
2571 DBG("Disabling ADMA as it is marked broken\n");
2572 host->flags &= ~SDHCI_USE_ADMA;
2573 }
2574
a13abc7b 2575 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
b8c86fc5
PO		 2576 if (host->ops->enable_dma) {
2577 if (host->ops->enable_dma(host)) {
a3c76eb9 2578 pr_warning("%s: No suitable DMA "
b8c86fc5
PO		 2579 "available. Falling back to PIO.\n",
2580 mmc_hostname(mmc));
a13abc7b
RR		 2581 host->flags &=
2582 ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
b8c86fc5 2583 }
d129bceb
PO		 2584 }
2585 }
2586
2134a922
PO		 2587 if (host->flags & SDHCI_USE_ADMA) {
2588 /*
2589 * We need to allocate descriptors for all sg entries
2590 * (128) and potentially one alignment transfer for
2591 * each of those entries.
2592 */
2593 host->adma_desc = kmalloc((128 * 2 + 1) * 4, GFP_KERNEL);
2594 host->align_buffer = kmalloc(128 * 4, GFP_KERNEL);
2595 if (!host->adma_desc || !host->align_buffer) {
2596 kfree(host->adma_desc);
2597 kfree(host->align_buffer);
a3c76eb9 2598 pr_warning("%s: Unable to allocate ADMA "
2134a922
PO		 2599 "buffers. Falling back to standard DMA.\n",
2600 mmc_hostname(mmc));
2601 host->flags &= ~SDHCI_USE_ADMA;
2602 }
2603 }
2604
7659150c
PO		 2605 /*
2606 * If we use DMA, then it's up to the caller to set the DMA
2607 * mask, but PIO does not need the hw shim so we set a new
2608 * mask here in that case.
2609 */
a13abc7b 2610 if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) {
7659150c
PO		 2611 host->dma_mask = DMA_BIT_MASK(64);
2612 mmc_dev(host->mmc)->dma_mask = &host->dma_mask;
2613 }
d129bceb 2614
c4687d5f 2615 if (host->version >= SDHCI_SPEC_300)
f2119df6 2616 host->max_clk = (caps[0] & SDHCI_CLOCK_V3_BASE_MASK)
c4687d5f
ZG		 2617 >> SDHCI_CLOCK_BASE_SHIFT;
2618 else
f2119df6 2619 host->max_clk = (caps[0] & SDHCI_CLOCK_BASE_MASK)
c4687d5f
ZG		 2620 >> SDHCI_CLOCK_BASE_SHIFT;
2621
4240ff0a 2622 host->max_clk *= 1000000;
f27f47ef
AV		 2623 if (host->max_clk == 0 || host->quirks &
2624 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) {
4240ff0a 2625 if (!host->ops->get_max_clock) {
a3c76eb9 2626 pr_err("%s: Hardware doesn't specify base clock "
4240ff0a
BD		 2627 "frequency.\n", mmc_hostname(mmc));
2628 return -ENODEV;
2629 }
2630 host->max_clk = host->ops->get_max_clock(host);
8ef1a143 2631 }
d129bceb 2632
c3ed3877
AN		 2633 /*
2634 * In case of Host Controller v3.00, find out whether clock
2635 * multiplier is supported.
2636 */
2637 host->clk_mul = (caps[1] & SDHCI_CLOCK_MUL_MASK) >>
2638 SDHCI_CLOCK_MUL_SHIFT;
2639
2640 /*
2641 * In case the value in Clock Multiplier is 0, then programmable
2642 * clock mode is not supported, otherwise the actual clock
2643 * multiplier is one more than the value of Clock Multiplier
2644 * in the Capabilities Register.
2645 */
2646 if (host->clk_mul)
2647 host->clk_mul += 1;
2648
d129bceb
PO		 2649 /*
2650 * Set host parameters.
2651 */
2652 mmc->ops = &sdhci_ops;
c3ed3877 2653 mmc->f_max = host->max_clk;
ce5f036b 2654 if (host->ops->get_min_clock)
a9e58f25 2655 mmc->f_min = host->ops->get_min_clock(host);
c3ed3877
AN		 2656 else if (host->version >= SDHCI_SPEC_300) {
2657 if (host->clk_mul) {
2658 mmc->f_min = (host->max_clk * host->clk_mul) / 1024;
2659 mmc->f_max = host->max_clk * host->clk_mul;
2660 } else
2661 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300;
2662 } else
0397526d 2663 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200;
15ec4461 2664
272308ca
AS		 2665 host->timeout_clk =
2666 (caps[0] & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT;
2667 if (host->timeout_clk == 0) {
2668 if (host->ops->get_timeout_clock) {
2669 host->timeout_clk = host->ops->get_timeout_clock(host);
2670 } else if (!(host->quirks &
2671 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) {
a3c76eb9 2672 pr_err("%s: Hardware doesn't specify timeout clock "
272308ca
AS		 2673 "frequency.\n", mmc_hostname(mmc));
2674 return -ENODEV;
2675 }
2676 }
2677 if (caps[0] & SDHCI_TIMEOUT_CLK_UNIT)
2678 host->timeout_clk *= 1000;
2679
2680 if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)
65be3fef 2681 host->timeout_clk = mmc->f_max / 1000;
272308ca 2682
65be3fef 2683 mmc->max_discard_to = (1 << 27) / host->timeout_clk;
58d1246d 2684
e89d456f
AW		 2685 mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_ERASE | MMC_CAP_CMD23;
2686
2687 if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12)
2688 host->flags |= SDHCI_AUTO_CMD12;
5fe23c7f 2689
8edf6371 2690 /* Auto-CMD23 stuff only works in ADMA or PIO. */
4f3d3e9b 2691 if ((host->version >= SDHCI_SPEC_300) &&
8edf6371 2692 ((host->flags & SDHCI_USE_ADMA) ||
4f3d3e9b 2693 !(host->flags & SDHCI_USE_SDMA))) {
8edf6371
AW		 2694 host->flags |= SDHCI_AUTO_CMD23;
2695 DBG("%s: Auto-CMD23 available\n", mmc_hostname(mmc));
2696 } else {
2697 DBG("%s: Auto-CMD23 unavailable\n", mmc_hostname(mmc));
2698 }
2699
15ec4461
PR		 2700 /*
2701 * A controller may support 8-bit width, but the board itself
2702 * might not have the pins brought out. Boards that support
2703 * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in
2704 * their platform code before calling sdhci_add_host(), and we
2705 * won't assume 8-bit width for hosts without that CAP.
2706 */
5fe23c7f 2707 if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA))
15ec4461 2708 mmc->caps |= MMC_CAP_4_BIT_DATA;
d129bceb 2709
f2119df6 2710 if (caps[0] & SDHCI_CAN_DO_HISPD)
a29e7e18 2711 mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
cd9277c0 2712
176d1ed4
JC		 2713 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) &&
2714 mmc_card_is_removable(mmc))
68d1fb7e
AV		 2715 mmc->caps |= MMC_CAP_NEEDS_POLL;
2716
f2119df6
AN		 2717 /* UHS-I mode(s) supported by the host controller. */
2718 if (host->version >= SDHCI_SPEC_300)
2719 mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;
2720
2721 /* SDR104 supports also implies SDR50 support */
2722 if (caps[1] & SDHCI_SUPPORT_SDR104)
2723 mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50;
2724 else if (caps[1] & SDHCI_SUPPORT_SDR50)
2725 mmc->caps |= MMC_CAP_UHS_SDR50;
2726
2727 if (caps[1] & SDHCI_SUPPORT_DDR50)
2728 mmc->caps |= MMC_CAP_UHS_DDR50;
2729
b513ea25
AN		 2730 /* Does the host needs tuning for SDR50? */
2731 if (caps[1] & SDHCI_USE_SDR50_TUNING)
2732 host->flags |= SDHCI_SDR50_NEEDS_TUNING;
2733
d6d50a15
AN		 2734 /* Driver Type(s) (A, C, D) supported by the host */
2735 if (caps[1] & SDHCI_DRIVER_TYPE_A)
2736 mmc->caps |= MMC_CAP_DRIVER_TYPE_A;
2737 if (caps[1] & SDHCI_DRIVER_TYPE_C)
2738 mmc->caps |= MMC_CAP_DRIVER_TYPE_C;
2739 if (caps[1] & SDHCI_DRIVER_TYPE_D)
2740 mmc->caps |= MMC_CAP_DRIVER_TYPE_D;
2741
bec8726a
G		 2742 /*
2743 * If Power Off Notify capability is enabled by the host,
2744 * set notify to short power off notify timeout value.
2745 */
2746 if (mmc->caps2 & MMC_CAP2_POWEROFF_NOTIFY)
2747 mmc->power_notify_type = MMC_HOST_PW_NOTIFY_SHORT;
2748 else
2749 mmc->power_notify_type = MMC_HOST_PW_NOTIFY_NONE;
2750
cf2b5eea
AN		 2751 /* Initial value for re-tuning timer count */
2752 host->tuning_count = (caps[1] & SDHCI_RETUNING_TIMER_COUNT_MASK) >>
2753 SDHCI_RETUNING_TIMER_COUNT_SHIFT;
2754
2755 /*
2756 * In case Re-tuning Timer is not disabled, the actual value of
2757 * re-tuning timer will be 2 ^ (n - 1).
2758 */
2759 if (host->tuning_count)
2760 host->tuning_count = 1 << (host->tuning_count - 1);
2761
2762 /* Re-tuning mode supported by the Host Controller */
2763 host->tuning_mode = (caps[1] & SDHCI_RETUNING_MODE_MASK) >>
2764 SDHCI_RETUNING_MODE_SHIFT;
2765
8f230f45 2766 ocr_avail = 0;
f2119df6
AN		 2767 /*
2768 * According to SD Host Controller spec v3.00, if the Host System
2769 * can afford more than 150mA, Host Driver should set XPC to 1. Also
2770 * the value is meaningful only if Voltage Support in the Capabilities
2771 * register is set. The actual current value is 4 times the register
2772 * value.
2773 */
2774 max_current_caps = sdhci_readl(host, SDHCI_MAX_CURRENT);
2775
2776 if (caps[0] & SDHCI_CAN_VDD_330) {
2777 int max_current_330;
2778
8f230f45 2779 ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34;
f2119df6
AN		 2780
2781 max_current_330 = ((max_current_caps &
2782 SDHCI_MAX_CURRENT_330_MASK) >>
2783 SDHCI_MAX_CURRENT_330_SHIFT) *
2784 SDHCI_MAX_CURRENT_MULTIPLIER;
2785
2786 if (max_current_330 > 150)
2787 mmc->caps |= MMC_CAP_SET_XPC_330;
2788 }
2789 if (caps[0] & SDHCI_CAN_VDD_300) {
2790 int max_current_300;
2791
8f230f45 2792 ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31;
f2119df6
AN		 2793
2794 max_current_300 = ((max_current_caps &
2795 SDHCI_MAX_CURRENT_300_MASK) >>
2796 SDHCI_MAX_CURRENT_300_SHIFT) *
2797 SDHCI_MAX_CURRENT_MULTIPLIER;
2798
2799 if (max_current_300 > 150)
2800 mmc->caps |= MMC_CAP_SET_XPC_300;
2801 }
2802 if (caps[0] & SDHCI_CAN_VDD_180) {
2803 int max_current_180;
2804
8f230f45
TI		 2805 ocr_avail |= MMC_VDD_165_195;
2806
f2119df6
AN		 2807 max_current_180 = ((max_current_caps &
2808 SDHCI_MAX_CURRENT_180_MASK) >>
2809 SDHCI_MAX_CURRENT_180_SHIFT) *
2810 SDHCI_MAX_CURRENT_MULTIPLIER;
2811
2812 if (max_current_180 > 150)
2813 mmc->caps |= MMC_CAP_SET_XPC_180;
5371c927
AN		 2814
2815 /* Maximum current capabilities of the host at 1.8V */
2816 if (max_current_180 >= 800)
2817 mmc->caps |= MMC_CAP_MAX_CURRENT_800;
2818 else if (max_current_180 >= 600)
2819 mmc->caps |= MMC_CAP_MAX_CURRENT_600;
2820 else if (max_current_180 >= 400)
2821 mmc->caps |= MMC_CAP_MAX_CURRENT_400;
2822 else
2823 mmc->caps |= MMC_CAP_MAX_CURRENT_200;
f2119df6
AN		 2824 }
2825
8f230f45
TI		 2826 mmc->ocr_avail = ocr_avail;
2827 mmc->ocr_avail_sdio = ocr_avail;
2828 if (host->ocr_avail_sdio)
2829 mmc->ocr_avail_sdio &= host->ocr_avail_sdio;
2830 mmc->ocr_avail_sd = ocr_avail;
2831 if (host->ocr_avail_sd)
2832 mmc->ocr_avail_sd &= host->ocr_avail_sd;
2833 else /* normal SD controllers don't support 1.8V */
2834 mmc->ocr_avail_sd &= ~MMC_VDD_165_195;
2835 mmc->ocr_avail_mmc = ocr_avail;
2836 if (host->ocr_avail_mmc)
2837 mmc->ocr_avail_mmc &= host->ocr_avail_mmc;
146ad66e
PO		 2838
2839 if (mmc->ocr_avail == 0) {
a3c76eb9 2840 pr_err("%s: Hardware doesn't report any "
b69c9058 2841 "support voltages.\n", mmc_hostname(mmc));
b8c86fc5 2842 return -ENODEV;
146ad66e
PO		 2843 }
2844
d129bceb
PO		 2845 spin_lock_init(&host->lock);
2846
2847 /*
2134a922
PO		 2848 * Maximum number of segments. Depends on if the hardware
2849 * can do scatter/gather or not.
d129bceb 2850 */
2134a922 2851 if (host->flags & SDHCI_USE_ADMA)
a36274e0 2852 mmc->max_segs = 128;
a13abc7b 2853 else if (host->flags & SDHCI_USE_SDMA)
a36274e0 2854 mmc->max_segs = 1;
2134a922 2855 else /* PIO */
a36274e0 2856 mmc->max_segs = 128;
d129bceb
PO		 2857
2858 /*
bab76961 2859 * Maximum number of sectors in one transfer. Limited by DMA boundary
55db890a 2860 * size (512KiB).
d129bceb 2861 */
55db890a 2862 mmc->max_req_size = 524288;
d129bceb
PO		 2863
2864 /*
2865 * Maximum segment size. Could be one segment with the maximum number
2134a922
PO		 2866 * of bytes. When doing hardware scatter/gather, each entry cannot
2867 * be larger than 64 KiB though.
d129bceb 2868 */
30652aa3
OJ		 2869 if (host->flags & SDHCI_USE_ADMA) {
2870 if (host->quirks & SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC)
2871 mmc->max_seg_size = 65535;
2872 else
2873 mmc->max_seg_size = 65536;
2874 } else {
2134a922 2875 mmc->max_seg_size = mmc->max_req_size;
30652aa3 2876 }
d129bceb 2877
fe4a3c7a
PO		 2878 /*
2879 * Maximum block size. This varies from controller to controller and
2880 * is specified in the capabilities register.
2881 */
0633f654
AV		 2882 if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) {
2883 mmc->max_blk_size = 2;
2884 } else {
f2119df6 2885 mmc->max_blk_size = (caps[0] & SDHCI_MAX_BLOCK_MASK) >>
0633f654
AV		 2886 SDHCI_MAX_BLOCK_SHIFT;
2887 if (mmc->max_blk_size >= 3) {
a3c76eb9 2888 pr_warning("%s: Invalid maximum block size, "
0633f654
AV		 2889 "assuming 512 bytes\n", mmc_hostname(mmc));
2890 mmc->max_blk_size = 0;
2891 }
2892 }
2893
2894 mmc->max_blk_size = 512 << mmc->max_blk_size;
fe4a3c7a 2895
55db890a
PO		 2896 /*
2897 * Maximum block count.
2898 */
1388eefd 2899 mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
55db890a 2900
d129bceb
PO		 2901 /*
2902 * Init tasklets.
2903 */
2904 tasklet_init(&host->card_tasklet,
2905 sdhci_tasklet_card, (unsigned long)host);
2906 tasklet_init(&host->finish_tasklet,
2907 sdhci_tasklet_finish, (unsigned long)host);
2908
e4cad1b5 2909 setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host);
d129bceb 2910
cf2b5eea 2911 if (host->version >= SDHCI_SPEC_300) {
b513ea25
AN		 2912 init_waitqueue_head(&host->buf_ready_int);
2913
cf2b5eea
AN		 2914 /* Initialize re-tuning timer */
2915 init_timer(&host->tuning_timer);
2916 host->tuning_timer.data = (unsigned long)host;
2917 host->tuning_timer.function = sdhci_tuning_timer;
2918 }
2919
dace1453 2920 ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
b69c9058 2921 mmc_hostname(mmc), host);
d129bceb 2922 if (ret)
8ef1a143 2923 goto untasklet;
d129bceb 2924
9bea3c85
MS		 2925 host->vmmc = regulator_get(mmc_dev(mmc), "vmmc");
2926 if (IS_ERR(host->vmmc)) {
a3c76eb9 2927 pr_info("%s: no vmmc regulator found\n", mmc_hostname(mmc));
9bea3c85
MS		 2928 host->vmmc = NULL;
2929 } else {
2930 regulator_enable(host->vmmc);
2931 }
2932
2f4cbb3d 2933 sdhci_init(host, 0);
d129bceb
PO		 2934
2935#ifdef CONFIG_MMC_DEBUG
2936 sdhci_dumpregs(host);
2937#endif
2938
f9134319 2939#ifdef SDHCI_USE_LEDS_CLASS
5dbace0c
HS		 2940 snprintf(host->led_name, sizeof(host->led_name),
2941 "%s::", mmc_hostname(mmc));
2942 host->led.name = host->led_name;
2f730fec
PO		 2943 host->led.brightness = LED_OFF;
2944 host->led.default_trigger = mmc_hostname(mmc);
2945 host->led.brightness_set = sdhci_led_control;
2946
b8c86fc5 2947 ret = led_classdev_register(mmc_dev(mmc), &host->led);
2f730fec
PO		 2948 if (ret)
2949 goto reset;
2950#endif
2951
5f25a66f
PO		 2952 mmiowb();
2953
d129bceb
PO		 2954 mmc_add_host(mmc);
2955
a3c76eb9 2956 pr_info("%s: SDHCI controller on %s [%s] using %s\n",
d1b26863 2957 mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)),
a13abc7b
RR		 2958 (host->flags & SDHCI_USE_ADMA) ? "ADMA" :
2959 (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO");
d129bceb 2960
7260cf5e
AV		 2961 sdhci_enable_card_detection(host);
2962
d129bceb
PO		 2963 return 0;
2964
f9134319 2965#ifdef SDHCI_USE_LEDS_CLASS
2f730fec
PO		 2966reset:
2967 sdhci_reset(host, SDHCI_RESET_ALL);
2968 free_irq(host->irq, host);
2969#endif
8ef1a143 2970untasklet:
d129bceb
PO		 2971 tasklet_kill(&host->card_tasklet);
2972 tasklet_kill(&host->finish_tasklet);
d129bceb
PO		 2973
2974 return ret;
2975}
2976
b8c86fc5 2977EXPORT_SYMBOL_GPL(sdhci_add_host);
d129bceb 2978
1e72859e 2979void sdhci_remove_host(struct sdhci_host *host, int dead)
b8c86fc5 2980{
1e72859e
PO		 2981 unsigned long flags;
2982
2983 if (dead) {
2984 spin_lock_irqsave(&host->lock, flags);
2985
2986 host->flags |= SDHCI_DEVICE_DEAD;
2987
2988 if (host->mrq) {
a3c76eb9 2989 pr_err("%s: Controller removed during "
1e72859e
PO		 2990 " transfer!\n", mmc_hostname(host->mmc));
2991
2992 host->mrq->cmd->error = -ENOMEDIUM;
2993 tasklet_schedule(&host->finish_tasklet);
2994 }
2995
2996 spin_unlock_irqrestore(&host->lock, flags);
2997 }
2998
7260cf5e
AV		 2999 sdhci_disable_card_detection(host);
3000
b8c86fc5 3001 mmc_remove_host(host->mmc);
d129bceb 3002
f9134319 3003#ifdef SDHCI_USE_LEDS_CLASS
2f730fec
PO		 3004 led_classdev_unregister(&host->led);
3005#endif
3006
1e72859e
PO		 3007 if (!dead)
3008 sdhci_reset(host, SDHCI_RESET_ALL);
d129bceb
PO		 3009
3010 free_irq(host->irq, host);
3011
3012 del_timer_sync(&host->timer);
cf2b5eea
AN		 3013 if (host->version >= SDHCI_SPEC_300)
3014 del_timer_sync(&host->tuning_timer);
d129bceb
PO		 3015
3016 tasklet_kill(&host->card_tasklet);
3017 tasklet_kill(&host->finish_tasklet);
2134a922 3018
9bea3c85
MS		 3019 if (host->vmmc) {
3020 regulator_disable(host->vmmc);
3021 regulator_put(host->vmmc);
3022 }
3023
2134a922
PO		 3024 kfree(host->adma_desc);
3025 kfree(host->align_buffer);
3026
3027 host->adma_desc = NULL;
3028 host->align_buffer = NULL;
d129bceb
PO		 3029}
3030
b8c86fc5 3031EXPORT_SYMBOL_GPL(sdhci_remove_host);
d129bceb 3032
b8c86fc5 3033void sdhci_free_host(struct sdhci_host *host)
d129bceb 3034{
b8c86fc5 3035 mmc_free_host(host->mmc);
d129bceb
PO		 3036}
3037
b8c86fc5 3038EXPORT_SYMBOL_GPL(sdhci_free_host);
d129bceb
PO		 3039
3040/*****************************************************************************\
3041 * *
3042 * Driver init/exit *
3043 * *
3044\*****************************************************************************/
3045
3046static int __init sdhci_drv_init(void)
3047{
a3c76eb9 3048 pr_info(DRIVER_NAME
52fbf9c9 3049 ": Secure Digital Host Controller Interface driver\n");
a3c76eb9 3050 pr_info(DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
d129bceb 3051
b8c86fc5 3052 return 0;
d129bceb
PO		 3053}
3054
3055static void __exit sdhci_drv_exit(void)
3056{
d129bceb
PO		 3057}
3058
3059module_init(sdhci_drv_init);
3060module_exit(sdhci_drv_exit);
3061
df673b22 3062module_param(debug_quirks, uint, 0444);
66fd8ad5 3063module_param(debug_quirks2, uint, 0444);
67435274 3064
32710e8f 3065MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
b8c86fc5 3066MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver");
d129bceb 3067MODULE_LICENSE("GPL");
67435274 3068
df673b22 3069MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");
66fd8ad5 3070MODULE_PARM_DESC(debug_quirks2, "Force certain other quirks.");
Ubuntu Artful kernel mirror