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mmc: sdhci: Factor out sdhci_needs_reset()
[mirror_ubuntu-artful-kernel.git] / drivers / mmc / host / sdhci.c
CommitLineData
d129bceb 1/*
70f10482 2 * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
d129bceb 3 *
b69c9058 4 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
d129bceb
PO		 5 *
6 * This program is free software; you can redistribute it and/or modify
643f720c
PO		 7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or (at
9 * your option) any later version.
84c46a53
PO		 10 *
11 * Thanks to the following companies for their support:
12 *
13 * - JMicron (hardware and technical support)
d129bceb
PO		 14 */
15
d129bceb
PO		 16#include <linux/delay.h>
17#include <linux/highmem.h>
b8c86fc5 18#include <linux/io.h>
88b47679 19#include <linux/module.h>
d129bceb 20#include <linux/dma-mapping.h>
5a0e3ad6 21#include <linux/slab.h>
11763609 22#include <linux/scatterlist.h>
9bea3c85 23#include <linux/regulator/consumer.h>
66fd8ad5 24#include <linux/pm_runtime.h>
d129bceb 25
2f730fec
PO		 26#include <linux/leds.h>
27
22113efd 28#include <linux/mmc/mmc.h>
d129bceb 29#include <linux/mmc/host.h>
473b095a 30#include <linux/mmc/card.h>
85cc1c33 31#include <linux/mmc/sdio.h>
bec9d4e5 32#include <linux/mmc/slot-gpio.h>
d129bceb 33
d129bceb
PO		 34#include "sdhci.h"
35
36#define DRIVER_NAME "sdhci"
d129bceb 37
d129bceb 38#define DBG(f, x...) \
c6563178 39 pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
d129bceb 40
b513ea25
AN		 41#define MAX_TUNING_LOOP 40
42
df673b22 43static unsigned int debug_quirks = 0;
66fd8ad5 44static unsigned int debug_quirks2;
67435274 45
d129bceb
PO		 46static void sdhci_finish_data(struct sdhci_host *);
47
52983382 48static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable);
d129bceb
PO		 49
50static void sdhci_dumpregs(struct sdhci_host *host)
51{
a7c53671
CD		 52 pr_err(DRIVER_NAME ": =========== REGISTER DUMP (%s)===========\n",
53 mmc_hostname(host->mmc));
d129bceb 54
a7c53671
CD		 55 pr_err(DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n",
56 sdhci_readl(host, SDHCI_DMA_ADDRESS),
57 sdhci_readw(host, SDHCI_HOST_VERSION));
58 pr_err(DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n",
59 sdhci_readw(host, SDHCI_BLOCK_SIZE),
60 sdhci_readw(host, SDHCI_BLOCK_COUNT));
61 pr_err(DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
62 sdhci_readl(host, SDHCI_ARGUMENT),
63 sdhci_readw(host, SDHCI_TRANSFER_MODE));
64 pr_err(DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n",
65 sdhci_readl(host, SDHCI_PRESENT_STATE),
66 sdhci_readb(host, SDHCI_HOST_CONTROL));
67 pr_err(DRIVER_NAME ": Power: 0x%08x | Blk gap: 0x%08x\n",
68 sdhci_readb(host, SDHCI_POWER_CONTROL),
69 sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL));
70 pr_err(DRIVER_NAME ": Wake-up: 0x%08x | Clock: 0x%08x\n",
71 sdhci_readb(host, SDHCI_WAKE_UP_CONTROL),
72 sdhci_readw(host, SDHCI_CLOCK_CONTROL));
73 pr_err(DRIVER_NAME ": Timeout: 0x%08x | Int stat: 0x%08x\n",
74 sdhci_readb(host, SDHCI_TIMEOUT_CONTROL),
75 sdhci_readl(host, SDHCI_INT_STATUS));
76 pr_err(DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
77 sdhci_readl(host, SDHCI_INT_ENABLE),
78 sdhci_readl(host, SDHCI_SIGNAL_ENABLE));
79 pr_err(DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
80 sdhci_readw(host, SDHCI_ACMD12_ERR),
81 sdhci_readw(host, SDHCI_SLOT_INT_STATUS));
82 pr_err(DRIVER_NAME ": Caps: 0x%08x | Caps_1: 0x%08x\n",
83 sdhci_readl(host, SDHCI_CAPABILITIES),
84 sdhci_readl(host, SDHCI_CAPABILITIES_1));
85 pr_err(DRIVER_NAME ": Cmd: 0x%08x | Max curr: 0x%08x\n",
86 sdhci_readw(host, SDHCI_COMMAND),
87 sdhci_readl(host, SDHCI_MAX_CURRENT));
88 pr_err(DRIVER_NAME ": Host ctl2: 0x%08x\n",
89 sdhci_readw(host, SDHCI_HOST_CONTROL2));
d129bceb 90
e57a5f61
AH		 91 if (host->flags & SDHCI_USE_ADMA) {
92 if (host->flags & SDHCI_USE_64_BIT_DMA)
a7c53671
CD		 93 pr_err(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x%08x\n",
94 readl(host->ioaddr + SDHCI_ADMA_ERROR),
95 readl(host->ioaddr + SDHCI_ADMA_ADDRESS_HI),
96 readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
e57a5f61 97 else
a7c53671
CD		 98 pr_err(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n",
99 readl(host->ioaddr + SDHCI_ADMA_ERROR),
100 readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
e57a5f61 101 }
be3f4ae0 102
a7c53671 103 pr_err(DRIVER_NAME ": ===========================================\n");
d129bceb
PO		 104}
105
106/*****************************************************************************\
107 * *
108 * Low level functions *
109 * *
110\*****************************************************************************/
111
7260cf5e
AV		 112static void sdhci_set_card_detection(struct sdhci_host *host, bool enable)
113{
5b4f1f6c 114 u32 present;
7260cf5e 115
c79396c1 116 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) ||
860951c5 117 !mmc_card_is_removable(host->mmc))
66fd8ad5
AH		 118 return;
119
5b4f1f6c
RK		 120 if (enable) {
121 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
122 SDHCI_CARD_PRESENT;
d25928d1 123
5b4f1f6c
RK		 124 host->ier |= present ? SDHCI_INT_CARD_REMOVE :
125 SDHCI_INT_CARD_INSERT;
126 } else {
127 host->ier &= ~(SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT);
128 }
b537f94c
RK		 129
130 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
131 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
7260cf5e
AV		 132}
133
134static void sdhci_enable_card_detection(struct sdhci_host *host)
135{
136 sdhci_set_card_detection(host, true);
137}
138
139static void sdhci_disable_card_detection(struct sdhci_host *host)
140{
141 sdhci_set_card_detection(host, false);
142}
143
02d0b685
UH		 144static void sdhci_runtime_pm_bus_on(struct sdhci_host *host)
145{
146 if (host->bus_on)
147 return;
148 host->bus_on = true;
149 pm_runtime_get_noresume(host->mmc->parent);
150}
151
152static void sdhci_runtime_pm_bus_off(struct sdhci_host *host)
153{
154 if (!host->bus_on)
155 return;
156 host->bus_on = false;
157 pm_runtime_put_noidle(host->mmc->parent);
158}
159
03231f9b 160void sdhci_reset(struct sdhci_host *host, u8 mask)
d129bceb 161{
e16514d8 162 unsigned long timeout;
393c1a34 163
4e4141a5 164 sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
d129bceb 165
f0710a55 166 if (mask & SDHCI_RESET_ALL) {
d129bceb 167 host->clock = 0;
f0710a55
AH		 168 /* Reset-all turns off SD Bus Power */
169 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
170 sdhci_runtime_pm_bus_off(host);
171 }
d129bceb 172
e16514d8
PO		 173 /* Wait max 100 ms */
174 timeout = 100;
175
176 /* hw clears the bit when it's done */
4e4141a5 177 while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
e16514d8 178 if (timeout == 0) {
a3c76eb9 179 pr_err("%s: Reset 0x%x never completed.\n",
e16514d8
PO		 180 mmc_hostname(host->mmc), (int)mask);
181 sdhci_dumpregs(host);
182 return;
183 }
184 timeout--;
185 mdelay(1);
d129bceb 186 }
03231f9b
RK		 187}
188EXPORT_SYMBOL_GPL(sdhci_reset);
189
190static void sdhci_do_reset(struct sdhci_host *host, u8 mask)
191{
192 if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
d3940f27
AH		 193 struct mmc_host *mmc = host->mmc;
194
195 if (!mmc->ops->get_cd(mmc))
03231f9b
RK		 196 return;
197 }
063a9dbb 198
03231f9b 199 host->ops->reset(host, mask);
393c1a34 200
da91a8f9
RK		 201 if (mask & SDHCI_RESET_ALL) {
202 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
203 if (host->ops->enable_dma)
204 host->ops->enable_dma(host);
205 }
206
207 /* Resetting the controller clears many */
208 host->preset_enabled = false;
3abc1e80 209 }
d129bceb
PO		 210}
211
2f4cbb3d 212static void sdhci_init(struct sdhci_host *host, int soft)
d129bceb 213{
d3940f27
AH		 214 struct mmc_host *mmc = host->mmc;
215
2f4cbb3d 216 if (soft)
03231f9b 217 sdhci_do_reset(host, SDHCI_RESET_CMD|SDHCI_RESET_DATA);
2f4cbb3d 218 else
03231f9b 219 sdhci_do_reset(host, SDHCI_RESET_ALL);
d129bceb 220
b537f94c
RK		 221 host->ier = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
222 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT |
223 SDHCI_INT_INDEX | SDHCI_INT_END_BIT | SDHCI_INT_CRC |
224 SDHCI_INT_TIMEOUT | SDHCI_INT_DATA_END |
225 SDHCI_INT_RESPONSE;
226
227 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
228 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2f4cbb3d
NP		 229
230 if (soft) {
231 /* force clock reconfiguration */
232 host->clock = 0;
d3940f27 233 mmc->ops->set_ios(mmc, &mmc->ios);
2f4cbb3d 234 }
7260cf5e 235}
d129bceb 236
7260cf5e
AV		 237static void sdhci_reinit(struct sdhci_host *host)
238{
2f4cbb3d 239 sdhci_init(host, 0);
7260cf5e 240 sdhci_enable_card_detection(host);
d129bceb
PO		 241}
242
061d17a6 243static void __sdhci_led_activate(struct sdhci_host *host)
d129bceb
PO		 244{
245 u8 ctrl;
246
4e4141a5 247 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
d129bceb 248 ctrl |= SDHCI_CTRL_LED;
4e4141a5 249 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d129bceb
PO		 250}
251
061d17a6 252static void __sdhci_led_deactivate(struct sdhci_host *host)
d129bceb
PO		 253{
254 u8 ctrl;
255
4e4141a5 256 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
d129bceb 257 ctrl &= ~SDHCI_CTRL_LED;
4e4141a5 258 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d129bceb
PO		 259}
260
4f78230f 261#if IS_REACHABLE(CONFIG_LEDS_CLASS)
2f730fec 262static void sdhci_led_control(struct led_classdev *led,
061d17a6 263 enum led_brightness brightness)
2f730fec
PO		 264{
265 struct sdhci_host *host = container_of(led, struct sdhci_host, led);
266 unsigned long flags;
267
268 spin_lock_irqsave(&host->lock, flags);
269
66fd8ad5
AH		 270 if (host->runtime_suspended)
271 goto out;
272
2f730fec 273 if (brightness == LED_OFF)
061d17a6 274 __sdhci_led_deactivate(host);
2f730fec 275 else
061d17a6 276 __sdhci_led_activate(host);
66fd8ad5 277out:
2f730fec
PO		 278 spin_unlock_irqrestore(&host->lock, flags);
279}
061d17a6
AH		 280
281static int sdhci_led_register(struct sdhci_host *host)
282{
283 struct mmc_host *mmc = host->mmc;
284
285 snprintf(host->led_name, sizeof(host->led_name),
286 "%s::", mmc_hostname(mmc));
287
288 host->led.name = host->led_name;
289 host->led.brightness = LED_OFF;
290 host->led.default_trigger = mmc_hostname(mmc);
291 host->led.brightness_set = sdhci_led_control;
292
293 return led_classdev_register(mmc_dev(mmc), &host->led);
294}
295
296static void sdhci_led_unregister(struct sdhci_host *host)
297{
298 led_classdev_unregister(&host->led);
299}
300
301static inline void sdhci_led_activate(struct sdhci_host *host)
302{
303}
304
305static inline void sdhci_led_deactivate(struct sdhci_host *host)
306{
307}
308
309#else
310
311static inline int sdhci_led_register(struct sdhci_host *host)
312{
313 return 0;
314}
315
316static inline void sdhci_led_unregister(struct sdhci_host *host)
317{
318}
319
320static inline void sdhci_led_activate(struct sdhci_host *host)
321{
322 __sdhci_led_activate(host);
323}
324
325static inline void sdhci_led_deactivate(struct sdhci_host *host)
326{
327 __sdhci_led_deactivate(host);
328}
329
2f730fec
PO		 330#endif
331
d129bceb
PO		 332/*****************************************************************************\
333 * *
334 * Core functions *
335 * *
336\*****************************************************************************/
337
a406f5a3 338static void sdhci_read_block_pio(struct sdhci_host *host)
d129bceb 339{
7659150c
PO		 340 unsigned long flags;
341 size_t blksize, len, chunk;
7244b85b 342 u32 uninitialized_var(scratch);
7659150c 343 u8 *buf;
d129bceb 344
a406f5a3 345 DBG("PIO reading\n");
d129bceb 346
a406f5a3 347 blksize = host->data->blksz;
7659150c 348 chunk = 0;
d129bceb 349
7659150c 350 local_irq_save(flags);
d129bceb 351
a406f5a3 352 while (blksize) {
bf3a35ac 353 BUG_ON(!sg_miter_next(&host->sg_miter));
d129bceb 354
7659150c 355 len = min(host->sg_miter.length, blksize);
d129bceb 356
7659150c
PO		 357 blksize -= len;
358 host->sg_miter.consumed = len;
14d836e7 359
7659150c 360 buf = host->sg_miter.addr;
d129bceb 361
7659150c
PO		 362 while (len) {
363 if (chunk == 0) {
4e4141a5 364 scratch = sdhci_readl(host, SDHCI_BUFFER);
7659150c 365 chunk = 4;
a406f5a3 366 }
7659150c
PO		 367
368 *buf = scratch & 0xFF;
369
370 buf++;
371 scratch >>= 8;
372 chunk--;
373 len--;
d129bceb 374 }
a406f5a3 375 }
7659150c
PO		 376
377 sg_miter_stop(&host->sg_miter);
378
379 local_irq_restore(flags);
a406f5a3 380}
d129bceb 381
a406f5a3
PO		 382static void sdhci_write_block_pio(struct sdhci_host *host)
383{
7659150c
PO		 384 unsigned long flags;
385 size_t blksize, len, chunk;
386 u32 scratch;
387 u8 *buf;
d129bceb 388
a406f5a3
PO		 389 DBG("PIO writing\n");
390
391 blksize = host->data->blksz;
7659150c
PO		 392 chunk = 0;
393 scratch = 0;
d129bceb 394
7659150c 395 local_irq_save(flags);
d129bceb 396
a406f5a3 397 while (blksize) {
bf3a35ac 398 BUG_ON(!sg_miter_next(&host->sg_miter));
a406f5a3 399
7659150c
PO		 400 len = min(host->sg_miter.length, blksize);
401
402 blksize -= len;
403 host->sg_miter.consumed = len;
404
405 buf = host->sg_miter.addr;
d129bceb 406
7659150c
PO		 407 while (len) {
408 scratch |= (u32)*buf << (chunk * 8);
409
410 buf++;
411 chunk++;
412 len--;
413
414 if ((chunk == 4) || ((len == 0) && (blksize == 0))) {
4e4141a5 415 sdhci_writel(host, scratch, SDHCI_BUFFER);
7659150c
PO		 416 chunk = 0;
417 scratch = 0;
d129bceb 418 }
d129bceb
PO		 419 }
420 }
7659150c
PO		 421
422 sg_miter_stop(&host->sg_miter);
423
424 local_irq_restore(flags);
a406f5a3
PO		 425}
426
427static void sdhci_transfer_pio(struct sdhci_host *host)
428{
429 u32 mask;
430
7659150c 431 if (host->blocks == 0)
a406f5a3
PO		 432 return;
433
434 if (host->data->flags & MMC_DATA_READ)
435 mask = SDHCI_DATA_AVAILABLE;
436 else
437 mask = SDHCI_SPACE_AVAILABLE;
438
4a3cba32
PO		 439 /*
440 * Some controllers (JMicron JMB38x) mess up the buffer bits
441 * for transfers < 4 bytes. As long as it is just one block,
442 * we can ignore the bits.
443 */
444 if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) &&
445 (host->data->blocks == 1))
446 mask = ~0;
447
4e4141a5 448 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
3e3bf207
AV		 449 if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY)
450 udelay(100);
451
a406f5a3
PO		 452 if (host->data->flags & MMC_DATA_READ)
453 sdhci_read_block_pio(host);
454 else
455 sdhci_write_block_pio(host);
d129bceb 456
7659150c
PO		 457 host->blocks--;
458 if (host->blocks == 0)
a406f5a3 459 break;
a406f5a3 460 }
d129bceb 461
a406f5a3 462 DBG("PIO transfer complete.\n");
d129bceb
PO		 463}
464
48857d9b 465static int sdhci_pre_dma_transfer(struct sdhci_host *host,
c0999b72 466 struct mmc_data *data, int cookie)
48857d9b
RK		 467{
468 int sg_count;
469
94538e51
RK		 470 /*
471 * If the data buffers are already mapped, return the previous
472 * dma_map_sg() result.
473 */
474 if (data->host_cookie == COOKIE_PRE_MAPPED)
48857d9b 475 return data->sg_count;
48857d9b
RK		 476
477 sg_count = dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
478 data->flags & MMC_DATA_WRITE ?
479 DMA_TO_DEVICE : DMA_FROM_DEVICE);
480
481 if (sg_count == 0)
482 return -ENOSPC;
483
484 data->sg_count = sg_count;
c0999b72 485 data->host_cookie = cookie;
48857d9b
RK		 486
487 return sg_count;
488}
489
2134a922
PO		 490static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags)
491{
492 local_irq_save(*flags);
482fce99 493 return kmap_atomic(sg_page(sg)) + sg->offset;
2134a922
PO		 494}
495
496static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags)
497{
482fce99 498 kunmap_atomic(buffer);
2134a922
PO		 499 local_irq_restore(*flags);
500}
501
e57a5f61
AH		 502static void sdhci_adma_write_desc(struct sdhci_host *host, void *desc,
503 dma_addr_t addr, int len, unsigned cmd)
118cd17d 504{
e57a5f61 505 struct sdhci_adma2_64_desc *dma_desc = desc;
118cd17d 506
e57a5f61 507 /* 32-bit and 64-bit descriptors have these members in same position */
0545230f
AH		 508 dma_desc->cmd = cpu_to_le16(cmd);
509 dma_desc->len = cpu_to_le16(len);
e57a5f61
AH		 510 dma_desc->addr_lo = cpu_to_le32((u32)addr);
511
512 if (host->flags & SDHCI_USE_64_BIT_DMA)
513 dma_desc->addr_hi = cpu_to_le32((u64)addr >> 32);
118cd17d
BD		 514}
515
b5ffa674
AH		 516static void sdhci_adma_mark_end(void *desc)
517{
e57a5f61 518 struct sdhci_adma2_64_desc *dma_desc = desc;
b5ffa674 519
e57a5f61 520 /* 32-bit and 64-bit descriptors have 'cmd' in same position */
0545230f 521 dma_desc->cmd |= cpu_to_le16(ADMA2_END);
b5ffa674
AH		 522}
523
60c64762
RK		 524static void sdhci_adma_table_pre(struct sdhci_host *host,
525 struct mmc_data *data, int sg_count)
2134a922 526{
2134a922 527 struct scatterlist *sg;
2134a922 528 unsigned long flags;
acc3ad13
RK		 529 dma_addr_t addr, align_addr;
530 void *desc, *align;
531 char *buffer;
532 int len, offset, i;
2134a922
PO		 533
534 /*
535 * The spec does not specify endianness of descriptor table.
536 * We currently guess that it is LE.
537 */
538
60c64762 539 host->sg_count = sg_count;
2134a922 540
4efaa6fb 541 desc = host->adma_table;
2134a922
PO		 542 align = host->align_buffer;
543
544 align_addr = host->align_addr;
545
546 for_each_sg(data->sg, sg, host->sg_count, i) {
547 addr = sg_dma_address(sg);
548 len = sg_dma_len(sg);
549
550 /*
acc3ad13
RK		 551 * The SDHCI specification states that ADMA addresses must
552 * be 32-bit aligned. If they aren't, then we use a bounce
553 * buffer for the (up to three) bytes that screw up the
2134a922
PO		 554 * alignment.
555 */
04a5ae6f
AH		 556 offset = (SDHCI_ADMA2_ALIGN - (addr & SDHCI_ADMA2_MASK)) &
557 SDHCI_ADMA2_MASK;
2134a922
PO		 558 if (offset) {
559 if (data->flags & MMC_DATA_WRITE) {
560 buffer = sdhci_kmap_atomic(sg, &flags);
561 memcpy(align, buffer, offset);
562 sdhci_kunmap_atomic(buffer, &flags);
563 }
564
118cd17d 565 /* tran, valid */
e57a5f61 566 sdhci_adma_write_desc(host, desc, align_addr, offset,
739d46dc 567 ADMA2_TRAN_VALID);
2134a922
PO		 568
569 BUG_ON(offset > 65536);
570
04a5ae6f
AH		 571 align += SDHCI_ADMA2_ALIGN;
572 align_addr += SDHCI_ADMA2_ALIGN;
2134a922 573
76fe379a 574 desc += host->desc_sz;
2134a922
PO		 575
576 addr += offset;
577 len -= offset;
578 }
579
2134a922
PO		 580 BUG_ON(len > 65536);
581
347ea32d
AH		 582 if (len) {
583 /* tran, valid */
584 sdhci_adma_write_desc(host, desc, addr, len,
585 ADMA2_TRAN_VALID);
586 desc += host->desc_sz;
587 }
2134a922
PO		 588
589 /*
590 * If this triggers then we have a calculation bug
591 * somewhere. :/
592 */
76fe379a 593 WARN_ON((desc - host->adma_table) >= host->adma_table_sz);
2134a922
PO		 594 }
595
70764a90 596 if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) {
acc3ad13 597 /* Mark the last descriptor as the terminating descriptor */
4efaa6fb 598 if (desc != host->adma_table) {
76fe379a 599 desc -= host->desc_sz;
b5ffa674 600 sdhci_adma_mark_end(desc);
70764a90
TA		 601 }
602 } else {
acc3ad13 603 /* Add a terminating entry - nop, end, valid */
e57a5f61 604 sdhci_adma_write_desc(host, desc, 0, 0, ADMA2_NOP_END_VALID);
70764a90 605 }
2134a922
PO		 606}
607
608static void sdhci_adma_table_post(struct sdhci_host *host,
609 struct mmc_data *data)
610{
2134a922
PO		 611 struct scatterlist *sg;
612 int i, size;
1c3d5f6d 613 void *align;
2134a922
PO		 614 char *buffer;
615 unsigned long flags;
616
47fa9613
RK		 617 if (data->flags & MMC_DATA_READ) {
618 bool has_unaligned = false;
de0b65a7 619
47fa9613
RK		 620 /* Do a quick scan of the SG list for any unaligned mappings */
621 for_each_sg(data->sg, sg, host->sg_count, i)
622 if (sg_dma_address(sg) & SDHCI_ADMA2_MASK) {
623 has_unaligned = true;
624 break;
625 }
2134a922 626
47fa9613
RK		 627 if (has_unaligned) {
628 dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
f55c98f7 629 data->sg_len, DMA_FROM_DEVICE);
2134a922 630
47fa9613 631 align = host->align_buffer;
2134a922 632
47fa9613
RK		 633 for_each_sg(data->sg, sg, host->sg_count, i) {
634 if (sg_dma_address(sg) & SDHCI_ADMA2_MASK) {
635 size = SDHCI_ADMA2_ALIGN -
636 (sg_dma_address(sg) & SDHCI_ADMA2_MASK);
637
638 buffer = sdhci_kmap_atomic(sg, &flags);
639 memcpy(buffer, align, size);
640 sdhci_kunmap_atomic(buffer, &flags);
2134a922 641
47fa9613
RK		 642 align += SDHCI_ADMA2_ALIGN;
643 }
2134a922
PO		 644 }
645 }
646 }
2134a922
PO		 647}
648
a3c7778f 649static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd)
d129bceb 650{
1c8cde92 651 u8 count;
a3c7778f 652 struct mmc_data *data = cmd->data;
1c8cde92 653 unsigned target_timeout, current_timeout;
d129bceb 654
ee53ab5d
PO		 655 /*
656 * If the host controller provides us with an incorrect timeout
657 * value, just skip the check and use 0xE. The hardware may take
658 * longer to time out, but that's much better than having a too-short
659 * timeout value.
660 */
11a2f1b7 661 if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL)
ee53ab5d 662 return 0xE;
e538fbe8 663
a3c7778f 664 /* Unspecified timeout, assume max */
1d4d7744 665 if (!data && !cmd->busy_timeout)
a3c7778f 666 return 0xE;
d129bceb 667
a3c7778f
AW		 668 /* timeout in us */
669 if (!data)
1d4d7744 670 target_timeout = cmd->busy_timeout * 1000;
78a2ca27 671 else {
fafcfda9 672 target_timeout = DIV_ROUND_UP(data->timeout_ns, 1000);
7f05538a
RK		 673 if (host->clock && data->timeout_clks) {
674 unsigned long long val;
675
676 /*
677 * data->timeout_clks is in units of clock cycles.
678 * host->clock is in Hz. target_timeout is in us.
679 * Hence, us = 1000000 * cycles / Hz. Round up.
680 */
681 val = 1000000 * data->timeout_clks;
682 if (do_div(val, host->clock))
683 target_timeout++;
684 target_timeout += val;
685 }
78a2ca27 686 }
81b39802 687
1c8cde92
PO		 688 /*
689 * Figure out needed cycles.
690 * We do this in steps in order to fit inside a 32 bit int.
691 * The first step is the minimum timeout, which will have a
692 * minimum resolution of 6 bits:
693 * (1) 2^13*1000 > 2^22,
694 * (2) host->timeout_clk < 2^16
695 * =>
696 * (1) / (2) > 2^6
697 */
698 count = 0;
699 current_timeout = (1 << 13) * 1000 / host->timeout_clk;
700 while (current_timeout < target_timeout) {
701 count++;
702 current_timeout <<= 1;
703 if (count >= 0xF)
704 break;
705 }
706
707 if (count >= 0xF) {
09eeff52
CB		 708 DBG("%s: Too large timeout 0x%x requested for CMD%d!\n",
709 mmc_hostname(host->mmc), count, cmd->opcode);
1c8cde92
PO		 710 count = 0xE;
711 }
712
ee53ab5d
PO		 713 return count;
714}
715
6aa943ab
AV		 716static void sdhci_set_transfer_irqs(struct sdhci_host *host)
717{
718 u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL;
719 u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR;
720
721 if (host->flags & SDHCI_REQ_USE_DMA)
b537f94c 722 host->ier = (host->ier & ~pio_irqs) | dma_irqs;
6aa943ab 723 else
b537f94c
RK		 724 host->ier = (host->ier & ~dma_irqs) | pio_irqs;
725
726 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
727 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
6aa943ab
AV		 728}
729
b45e668a 730static void sdhci_set_timeout(struct sdhci_host *host, struct mmc_command *cmd)
ee53ab5d
PO		 731{
732 u8 count;
b45e668a
AD		 733
734 if (host->ops->set_timeout) {
735 host->ops->set_timeout(host, cmd);
736 } else {
737 count = sdhci_calc_timeout(host, cmd);
738 sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
739 }
740}
741
742static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd)
743{
2134a922 744 u8 ctrl;
a3c7778f 745 struct mmc_data *data = cmd->data;
ee53ab5d 746
b45e668a
AD		 747 if (data || (cmd->flags & MMC_RSP_BUSY))
748 sdhci_set_timeout(host, cmd);
a3c7778f
AW		 749
750 if (!data)
ee53ab5d
PO		 751 return;
752
43dea098
AH		 753 WARN_ON(host->data);
754
ee53ab5d
PO		 755 /* Sanity checks */
756 BUG_ON(data->blksz * data->blocks > 524288);
757 BUG_ON(data->blksz > host->mmc->max_blk_size);
758 BUG_ON(data->blocks > 65535);
759
760 host->data = data;
761 host->data_early = 0;
f6a03cbf 762 host->data->bytes_xfered = 0;
ee53ab5d 763
fce14421 764 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2134a922 765 struct scatterlist *sg;
df953925 766 unsigned int length_mask, offset_mask;
a0eaf0f9 767 int i;
2134a922 768
fce14421
RK		 769 host->flags |= SDHCI_REQ_USE_DMA;
770
771 /*
772 * FIXME: This doesn't account for merging when mapping the
773 * scatterlist.
774 *
775 * The assumption here being that alignment and lengths are
776 * the same after DMA mapping to device address space.
777 */
a0eaf0f9 778 length_mask = 0;
df953925 779 offset_mask = 0;
2134a922 780 if (host->flags & SDHCI_USE_ADMA) {
df953925 781 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE) {
a0eaf0f9 782 length_mask = 3;
df953925
RK		 783 /*
784 * As we use up to 3 byte chunks to work
785 * around alignment problems, we need to
786 * check the offset as well.
787 */
788 offset_mask = 3;
789 }
2134a922
PO		 790 } else {
791 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE)
a0eaf0f9 792 length_mask = 3;
df953925
RK		 793 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR)
794 offset_mask = 3;
2134a922
PO		 795 }
796
df953925 797 if (unlikely(length_mask | offset_mask)) {
2134a922 798 for_each_sg(data->sg, sg, data->sg_len, i) {
a0eaf0f9 799 if (sg->length & length_mask) {
2e4456f0 800 DBG("Reverting to PIO because of transfer size (%d)\n",
a0eaf0f9 801 sg->length);
2134a922
PO		 802 host->flags &= ~SDHCI_REQ_USE_DMA;
803 break;
804 }
a0eaf0f9 805 if (sg->offset & offset_mask) {
2e4456f0 806 DBG("Reverting to PIO because of bad alignment\n");
2134a922
PO		 807 host->flags &= ~SDHCI_REQ_USE_DMA;
808 break;
809 }
810 }
811 }
812 }
813
8f1934ce 814 if (host->flags & SDHCI_REQ_USE_DMA) {
c0999b72 815 int sg_cnt = sdhci_pre_dma_transfer(host, data, COOKIE_MAPPED);
60c64762
RK		 816
817 if (sg_cnt <= 0) {
818 /*
819 * This only happens when someone fed
820 * us an invalid request.
821 */
822 WARN_ON(1);
823 host->flags &= ~SDHCI_REQ_USE_DMA;
824 } else if (host->flags & SDHCI_USE_ADMA) {
825 sdhci_adma_table_pre(host, data, sg_cnt);
826
827 sdhci_writel(host, host->adma_addr, SDHCI_ADMA_ADDRESS);
828 if (host->flags & SDHCI_USE_64_BIT_DMA)
829 sdhci_writel(host,
830 (u64)host->adma_addr >> 32,
831 SDHCI_ADMA_ADDRESS_HI);
8f1934ce 832 } else {
60c64762
RK		 833 WARN_ON(sg_cnt != 1);
834 sdhci_writel(host, sg_dma_address(data->sg),
835 SDHCI_DMA_ADDRESS);
8f1934ce
PO		 836 }
837 }
838
2134a922
PO		 839 /*
840 * Always adjust the DMA selection as some controllers
841 * (e.g. JMicron) can't do PIO properly when the selection
842 * is ADMA.
843 */
844 if (host->version >= SDHCI_SPEC_200) {
4e4141a5 845 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
2134a922
PO		 846 ctrl &= ~SDHCI_CTRL_DMA_MASK;
847 if ((host->flags & SDHCI_REQ_USE_DMA) &&
e57a5f61
AH		 848 (host->flags & SDHCI_USE_ADMA)) {
849 if (host->flags & SDHCI_USE_64_BIT_DMA)
850 ctrl |= SDHCI_CTRL_ADMA64;
851 else
852 ctrl |= SDHCI_CTRL_ADMA32;
853 } else {
2134a922 854 ctrl |= SDHCI_CTRL_SDMA;
e57a5f61 855 }
4e4141a5 856 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
c9fddbc4
PO		 857 }
858
8f1934ce 859 if (!(host->flags & SDHCI_REQ_USE_DMA)) {
da60a91d
SAS		 860 int flags;
861
862 flags = SG_MITER_ATOMIC;
863 if (host->data->flags & MMC_DATA_READ)
864 flags |= SG_MITER_TO_SG;
865 else
866 flags |= SG_MITER_FROM_SG;
867 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
7659150c 868 host->blocks = data->blocks;
d129bceb 869 }
c7fa9963 870
6aa943ab
AV		 871 sdhci_set_transfer_irqs(host);
872
f6a03cbf
MV		 873 /* Set the DMA boundary value and block size */
874 sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
875 data->blksz), SDHCI_BLOCK_SIZE);
4e4141a5 876 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
c7fa9963
PO		 877}
878
879static void sdhci_set_transfer_mode(struct sdhci_host *host,
e89d456f 880 struct mmc_command *cmd)
c7fa9963 881{
d3fc5d71 882 u16 mode = 0;
e89d456f 883 struct mmc_data *data = cmd->data;
c7fa9963 884
2b558c13 885 if (data == NULL) {
9b8ffea6
VW		 886 if (host->quirks2 &
887 SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD) {
888 sdhci_writew(host, 0x0, SDHCI_TRANSFER_MODE);
889 } else {
2b558c13 890 /* clear Auto CMD settings for no data CMDs */
9b8ffea6
VW		 891 mode = sdhci_readw(host, SDHCI_TRANSFER_MODE);
892 sdhci_writew(host, mode & ~(SDHCI_TRNS_AUTO_CMD12 |
2b558c13 893 SDHCI_TRNS_AUTO_CMD23), SDHCI_TRANSFER_MODE);
9b8ffea6 894 }
c7fa9963 895 return;
2b558c13 896 }
c7fa9963 897
e538fbe8
PO		 898 WARN_ON(!host->data);
899
d3fc5d71
VY		 900 if (!(host->quirks2 & SDHCI_QUIRK2_SUPPORT_SINGLE))
901 mode = SDHCI_TRNS_BLK_CNT_EN;
902
e89d456f 903 if (mmc_op_multi(cmd->opcode) || data->blocks > 1) {
d3fc5d71 904 mode = SDHCI_TRNS_BLK_CNT_EN | SDHCI_TRNS_MULTI;
e89d456f
AW		 905 /*
906 * If we are sending CMD23, CMD12 never gets sent
907 * on successful completion (so no Auto-CMD12).
908 */
a4c73aba 909 if (!cmd->mrq->sbc && (host->flags & SDHCI_AUTO_CMD12) &&
85cc1c33 910 (cmd->opcode != SD_IO_RW_EXTENDED))
e89d456f 911 mode |= SDHCI_TRNS_AUTO_CMD12;
a4c73aba 912 else if (cmd->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) {
8edf6371 913 mode |= SDHCI_TRNS_AUTO_CMD23;
a4c73aba 914 sdhci_writel(host, cmd->mrq->sbc->arg, SDHCI_ARGUMENT2);
8edf6371 915 }
c4512f79 916 }
8edf6371 917
c7fa9963
PO		 918 if (data->flags & MMC_DATA_READ)
919 mode |= SDHCI_TRNS_READ;
c9fddbc4 920 if (host->flags & SDHCI_REQ_USE_DMA)
c7fa9963
PO		 921 mode |= SDHCI_TRNS_DMA;
922
4e4141a5 923 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
d129bceb
PO		 924}
925
0cc563ce
AH		 926static bool sdhci_needs_reset(struct sdhci_host *host, struct mmc_request *mrq)
927{
928 return (!(host->flags & SDHCI_DEVICE_DEAD) &&
929 ((mrq->cmd && mrq->cmd->error) ||
930 (mrq->sbc && mrq->sbc->error) ||
931 (mrq->data && ((mrq->data->error && !mrq->data->stop) ||
932 (mrq->data->stop && mrq->data->stop->error))) ||
933 (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST)));
934}
935
a6d3bdd5
AH		 936static void sdhci_finish_mrq(struct sdhci_host *host, struct mmc_request *mrq)
937{
938 tasklet_schedule(&host->finish_tasklet);
939}
940
d129bceb
PO		 941static void sdhci_finish_data(struct sdhci_host *host)
942{
943 struct mmc_data *data;
d129bceb 944
d129bceb
PO		 945 data = host->data;
946 host->data = NULL;
7c89a3d9 947 host->data_cmd = NULL;
d129bceb 948
add8913d
RK		 949 if ((host->flags & (SDHCI_REQ_USE_DMA | SDHCI_USE_ADMA)) ==
950 (SDHCI_REQ_USE_DMA | SDHCI_USE_ADMA))
951 sdhci_adma_table_post(host, data);
d129bceb
PO		 952
953 /*
c9b74c5b
PO		 954 * The specification states that the block count register must
955 * be updated, but it does not specify at what point in the
956 * data flow. That makes the register entirely useless to read
957 * back so we have to assume that nothing made it to the card
958 * in the event of an error.
d129bceb 959 */
c9b74c5b
PO		 960 if (data->error)
961 data->bytes_xfered = 0;
d129bceb 962 else
c9b74c5b 963 data->bytes_xfered = data->blksz * data->blocks;
d129bceb 964
e89d456f
AW		 965 /*
966 * Need to send CMD12 if -
967 * a) open-ended multiblock transfer (no CMD23)
968 * b) error in multiblock transfer
969 */
970 if (data->stop &&
971 (data->error ||
a4c73aba 972 !data->mrq->sbc)) {
e89d456f 973
d129bceb
PO		 974 /*
975 * The controller needs a reset of internal state machines
976 * upon error conditions.
977 */
17b0429d 978 if (data->error) {
03231f9b
RK		 979 sdhci_do_reset(host, SDHCI_RESET_CMD);
980 sdhci_do_reset(host, SDHCI_RESET_DATA);
d129bceb
PO		 981 }
982
983 sdhci_send_command(host, data->stop);
a6d3bdd5
AH		 984 } else {
985 sdhci_finish_mrq(host, data->mrq);
986 }
d129bceb
PO		 987}
988
c0e55129 989void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
d129bceb
PO		 990{
991 int flags;
fd2208d7 992 u32 mask;
7cb2c76f 993 unsigned long timeout;
d129bceb
PO		 994
995 WARN_ON(host->cmd);
996
96776200
RK		 997 /* Initially, a command has no error */
998 cmd->error = 0;
999
d129bceb 1000 /* Wait max 10 ms */
7cb2c76f 1001 timeout = 10;
fd2208d7
PO		 1002
1003 mask = SDHCI_CMD_INHIBIT;
1004 if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
1005 mask |= SDHCI_DATA_INHIBIT;
1006
1007 /* We shouldn't wait for data inihibit for stop commands, even
1008 though they might use busy signaling */
a4c73aba 1009 if (cmd->mrq->data && (cmd == cmd->mrq->data->stop))
fd2208d7
PO		 1010 mask &= ~SDHCI_DATA_INHIBIT;
1011
4e4141a5 1012 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
7cb2c76f 1013 if (timeout == 0) {
2e4456f0
MV		 1014 pr_err("%s: Controller never released inhibit bit(s).\n",
1015 mmc_hostname(host->mmc));
d129bceb 1016 sdhci_dumpregs(host);
17b0429d 1017 cmd->error = -EIO;
a6d3bdd5 1018 sdhci_finish_mrq(host, cmd->mrq);
d129bceb
PO		 1019 return;
1020 }
7cb2c76f
PO		 1021 timeout--;
1022 mdelay(1);
1023 }
d129bceb 1024
3e1a6892 1025 timeout = jiffies;
1d4d7744
UH		 1026 if (!cmd->data && cmd->busy_timeout > 9000)
1027 timeout += DIV_ROUND_UP(cmd->busy_timeout, 1000) * HZ + HZ;
3e1a6892
AH		 1028 else
1029 timeout += 10 * HZ;
1030 mod_timer(&host->timer, timeout);
d129bceb
PO		 1031
1032 host->cmd = cmd;
7c89a3d9
AH		 1033 if (cmd->data || cmd->flags & MMC_RSP_BUSY) {
1034 WARN_ON(host->data_cmd);
1035 host->data_cmd = cmd;
1036 }
d129bceb 1037
a3c7778f 1038 sdhci_prepare_data(host, cmd);
d129bceb 1039
4e4141a5 1040 sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT);
d129bceb 1041
e89d456f 1042 sdhci_set_transfer_mode(host, cmd);
c7fa9963 1043
d129bceb 1044 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
a3c76eb9 1045 pr_err("%s: Unsupported response type!\n",
d129bceb 1046 mmc_hostname(host->mmc));
17b0429d 1047 cmd->error = -EINVAL;
a6d3bdd5 1048 sdhci_finish_mrq(host, cmd->mrq);
d129bceb
PO		 1049 return;
1050 }
1051
1052 if (!(cmd->flags & MMC_RSP_PRESENT))
1053 flags = SDHCI_CMD_RESP_NONE;
1054 else if (cmd->flags & MMC_RSP_136)
1055 flags = SDHCI_CMD_RESP_LONG;
1056 else if (cmd->flags & MMC_RSP_BUSY)
1057 flags = SDHCI_CMD_RESP_SHORT_BUSY;
1058 else
1059 flags = SDHCI_CMD_RESP_SHORT;
1060
1061 if (cmd->flags & MMC_RSP_CRC)
1062 flags |= SDHCI_CMD_CRC;
1063 if (cmd->flags & MMC_RSP_OPCODE)
1064 flags |= SDHCI_CMD_INDEX;
b513ea25
AN		 1065
1066 /* CMD19 is special in that the Data Present Select should be set */
069c9f14
G		 1067 if (cmd->data || cmd->opcode == MMC_SEND_TUNING_BLOCK ||
1068 cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200)
d129bceb
PO		 1069 flags |= SDHCI_CMD_DATA;
1070
4e4141a5 1071 sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND);
d129bceb 1072}
c0e55129 1073EXPORT_SYMBOL_GPL(sdhci_send_command);
d129bceb
PO		 1074
1075static void sdhci_finish_command(struct sdhci_host *host)
1076{
e0a5640a 1077 struct mmc_command *cmd = host->cmd;
d129bceb
PO		 1078 int i;
1079
e0a5640a
AH		 1080 host->cmd = NULL;
1081
1082 if (cmd->flags & MMC_RSP_PRESENT) {
1083 if (cmd->flags & MMC_RSP_136) {
d129bceb
PO		 1084 /* CRC is stripped so we need to do some shifting. */
1085 for (i = 0;i < 4;i++) {
e0a5640a 1086 cmd->resp[i] = sdhci_readl(host,
d129bceb
PO		 1087 SDHCI_RESPONSE + (3-i)*4) << 8;
1088 if (i != 3)
e0a5640a 1089 cmd->resp[i] |=
4e4141a5 1090 sdhci_readb(host,
d129bceb
PO		 1091 SDHCI_RESPONSE + (3-i)*4-1);
1092 }
1093 } else {
e0a5640a 1094 cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE);
d129bceb
PO		 1095 }
1096 }
1097
6bde8681
AH		 1098 /*
1099 * The host can send and interrupt when the busy state has
1100 * ended, allowing us to wait without wasting CPU cycles.
1101 * The busy signal uses DAT0 so this is similar to waiting
1102 * for data to complete.
1103 *
1104 * Note: The 1.0 specification is a bit ambiguous about this
1105 * feature so there might be some problems with older
1106 * controllers.
1107 */
e0a5640a
AH		 1108 if (cmd->flags & MMC_RSP_BUSY) {
1109 if (cmd->data) {
6bde8681
AH		 1110 DBG("Cannot wait for busy signal when also doing a data transfer");
1111 } else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ) &&
ea968023
AH		 1112 cmd == host->data_cmd) {
1113 /* Command complete before busy is ended */
6bde8681
AH		 1114 return;
1115 }
1116 }
1117
e89d456f 1118 /* Finished CMD23, now send actual command. */
a4c73aba
AH		 1119 if (cmd == cmd->mrq->sbc) {
1120 sdhci_send_command(host, cmd->mrq->cmd);
e89d456f 1121 } else {
e538fbe8 1122
e89d456f
AW		 1123 /* Processed actual command. */
1124 if (host->data && host->data_early)
1125 sdhci_finish_data(host);
d129bceb 1126
e0a5640a 1127 if (!cmd->data)
a6d3bdd5 1128 sdhci_finish_mrq(host, cmd->mrq);
e89d456f 1129 }
d129bceb
PO		 1130}
1131
52983382
KL		 1132static u16 sdhci_get_preset_value(struct sdhci_host *host)
1133{
d975f121 1134 u16 preset = 0;
52983382 1135
d975f121
RK		 1136 switch (host->timing) {
1137 case MMC_TIMING_UHS_SDR12:
52983382
KL		 1138 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1139 break;
d975f121 1140 case MMC_TIMING_UHS_SDR25:
52983382
KL		 1141 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR25);
1142 break;
d975f121 1143 case MMC_TIMING_UHS_SDR50:
52983382
KL		 1144 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR50);
1145 break;
d975f121
RK		 1146 case MMC_TIMING_UHS_SDR104:
1147 case MMC_TIMING_MMC_HS200:
52983382
KL		 1148 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR104);
1149 break;
d975f121 1150 case MMC_TIMING_UHS_DDR50:
0dafa60e 1151 case MMC_TIMING_MMC_DDR52:
52983382
KL		 1152 preset = sdhci_readw(host, SDHCI_PRESET_FOR_DDR50);
1153 break;
e9fb05d5
AH		 1154 case MMC_TIMING_MMC_HS400:
1155 preset = sdhci_readw(host, SDHCI_PRESET_FOR_HS400);
1156 break;
52983382
KL		 1157 default:
1158 pr_warn("%s: Invalid UHS-I mode selected\n",
1159 mmc_hostname(host->mmc));
1160 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1161 break;
1162 }
1163 return preset;
1164}
1165
fb9ee047
LD		 1166u16 sdhci_calc_clk(struct sdhci_host *host, unsigned int clock,
1167 unsigned int *actual_clock)
d129bceb 1168{
c3ed3877 1169 int div = 0; /* Initialized for compiler warning */
df16219f 1170 int real_div = div, clk_mul = 1;
c3ed3877 1171 u16 clk = 0;
5497159c 1172 bool switch_base_clk = false;
d129bceb 1173
85105c53 1174 if (host->version >= SDHCI_SPEC_300) {
da91a8f9 1175 if (host->preset_enabled) {
52983382
KL		 1176 u16 pre_val;
1177
1178 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1179 pre_val = sdhci_get_preset_value(host);
1180 div = (pre_val & SDHCI_PRESET_SDCLK_FREQ_MASK)
1181 >> SDHCI_PRESET_SDCLK_FREQ_SHIFT;
1182 if (host->clk_mul &&
1183 (pre_val & SDHCI_PRESET_CLKGEN_SEL_MASK)) {
1184 clk = SDHCI_PROG_CLOCK_MODE;
1185 real_div = div + 1;
1186 clk_mul = host->clk_mul;
1187 } else {
1188 real_div = max_t(int, 1, div << 1);
1189 }
1190 goto clock_set;
1191 }
1192
c3ed3877
AN		 1193 /*
1194 * Check if the Host Controller supports Programmable Clock
1195 * Mode.
1196 */
1197 if (host->clk_mul) {
52983382
KL		 1198 for (div = 1; div <= 1024; div++) {
1199 if ((host->max_clk * host->clk_mul / div)
1200 <= clock)
1201 break;
1202 }
5497159c 1203 if ((host->max_clk * host->clk_mul / div) <= clock) {
1204 /*
1205 * Set Programmable Clock Mode in the Clock
1206 * Control register.
1207 */
1208 clk = SDHCI_PROG_CLOCK_MODE;
1209 real_div = div;
1210 clk_mul = host->clk_mul;
1211 div--;
1212 } else {
1213 /*
1214 * Divisor can be too small to reach clock
1215 * speed requirement. Then use the base clock.
1216 */
1217 switch_base_clk = true;
1218 }
1219 }
1220
1221 if (!host->clk_mul || switch_base_clk) {
c3ed3877
AN		 1222 /* Version 3.00 divisors must be a multiple of 2. */
1223 if (host->max_clk <= clock)
1224 div = 1;
1225 else {
1226 for (div = 2; div < SDHCI_MAX_DIV_SPEC_300;
1227 div += 2) {
1228 if ((host->max_clk / div) <= clock)
1229 break;
1230 }
85105c53 1231 }
df16219f 1232 real_div = div;
c3ed3877 1233 div >>= 1;
d1955c3a
SG		 1234 if ((host->quirks2 & SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN)
1235 && !div && host->max_clk <= 25000000)
1236 div = 1;
85105c53
ZG		 1237 }
1238 } else {
1239 /* Version 2.00 divisors must be a power of 2. */
0397526d 1240 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
85105c53
ZG		 1241 if ((host->max_clk / div) <= clock)
1242 break;
1243 }
df16219f 1244 real_div = div;
c3ed3877 1245 div >>= 1;
d129bceb 1246 }
d129bceb 1247
52983382 1248clock_set:
03d6f5ff 1249 if (real_div)
fb9ee047 1250 *actual_clock = (host->max_clk * clk_mul) / real_div;
c3ed3877 1251 clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
85105c53
ZG		 1252 clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
1253 << SDHCI_DIVIDER_HI_SHIFT;
fb9ee047
LD		 1254
1255 return clk;
1256}
1257EXPORT_SYMBOL_GPL(sdhci_calc_clk);
1258
1259void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
1260{
1261 u16 clk;
1262 unsigned long timeout;
1263
1264 host->mmc->actual_clock = 0;
1265
1266 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
fb9ee047
LD		 1267
1268 if (clock == 0)
1269 return;
1270
1271 clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock);
1272
d129bceb 1273 clk |= SDHCI_CLOCK_INT_EN;
4e4141a5 1274 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
d129bceb 1275
27f6cb16
CB		 1276 /* Wait max 20 ms */
1277 timeout = 20;
4e4141a5 1278 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
7cb2c76f
PO		 1279 & SDHCI_CLOCK_INT_STABLE)) {
1280 if (timeout == 0) {
2e4456f0
MV		 1281 pr_err("%s: Internal clock never stabilised.\n",
1282 mmc_hostname(host->mmc));
d129bceb
PO		 1283 sdhci_dumpregs(host);
1284 return;
1285 }
7cb2c76f
PO		 1286 timeout--;
1287 mdelay(1);
1288 }
d129bceb
PO		 1289
1290 clk |= SDHCI_CLOCK_CARD_EN;
4e4141a5 1291 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
d129bceb 1292}
1771059c 1293EXPORT_SYMBOL_GPL(sdhci_set_clock);
d129bceb 1294
1dceb041
AH		 1295static void sdhci_set_power_reg(struct sdhci_host *host, unsigned char mode,
1296 unsigned short vdd)
146ad66e 1297{
3a48edc4 1298 struct mmc_host *mmc = host->mmc;
1dceb041
AH		 1299
1300 spin_unlock_irq(&host->lock);
1301 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd);
1302 spin_lock_irq(&host->lock);
1303
1304 if (mode != MMC_POWER_OFF)
1305 sdhci_writeb(host, SDHCI_POWER_ON, SDHCI_POWER_CONTROL);
1306 else
1307 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1308}
1309
1310void sdhci_set_power(struct sdhci_host *host, unsigned char mode,
1311 unsigned short vdd)
1312{
8364248a 1313 u8 pwr = 0;
146ad66e 1314
24fbb3ca
RK		 1315 if (mode != MMC_POWER_OFF) {
1316 switch (1 << vdd) {
ae628903
PO		 1317 case MMC_VDD_165_195:
1318 pwr = SDHCI_POWER_180;
1319 break;
1320 case MMC_VDD_29_30:
1321 case MMC_VDD_30_31:
1322 pwr = SDHCI_POWER_300;
1323 break;
1324 case MMC_VDD_32_33:
1325 case MMC_VDD_33_34:
1326 pwr = SDHCI_POWER_330;
1327 break;
1328 default:
9d5de93f
AH		 1329 WARN(1, "%s: Invalid vdd %#x\n",
1330 mmc_hostname(host->mmc), vdd);
1331 break;
ae628903
PO		 1332 }
1333 }
1334
1335 if (host->pwr == pwr)
e921a8b6 1336 return;
146ad66e 1337
ae628903
PO		 1338 host->pwr = pwr;
1339
1340 if (pwr == 0) {
4e4141a5 1341 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
f0710a55
AH		 1342 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
1343 sdhci_runtime_pm_bus_off(host);
e921a8b6
RK		 1344 } else {
1345 /*
1346 * Spec says that we should clear the power reg before setting
1347 * a new value. Some controllers don't seem to like this though.
1348 */
1349 if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
1350 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
146ad66e 1351
e921a8b6
RK		 1352 /*
1353 * At least the Marvell CaFe chip gets confused if we set the
1354 * voltage and set turn on power at the same time, so set the
1355 * voltage first.
1356 */
1357 if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
1358 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
e08c1694 1359
e921a8b6 1360 pwr |= SDHCI_POWER_ON;
146ad66e 1361
e921a8b6 1362 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
557b0697 1363
e921a8b6
RK		 1364 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
1365 sdhci_runtime_pm_bus_on(host);
f0710a55 1366
e921a8b6
RK		 1367 /*
1368 * Some controllers need an extra 10ms delay of 10ms before
1369 * they can apply clock after applying power
1370 */
1371 if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER)
1372 mdelay(10);
1373 }
1dceb041
AH		 1374}
1375EXPORT_SYMBOL_GPL(sdhci_set_power);
918f4cbd 1376
1dceb041
AH		 1377static void __sdhci_set_power(struct sdhci_host *host, unsigned char mode,
1378 unsigned short vdd)
1379{
1380 struct mmc_host *mmc = host->mmc;
1381
1382 if (host->ops->set_power)
1383 host->ops->set_power(host, mode, vdd);
1384 else if (!IS_ERR(mmc->supply.vmmc))
1385 sdhci_set_power_reg(host, mode, vdd);
1386 else
1387 sdhci_set_power(host, mode, vdd);
146ad66e
PO		 1388}
1389
d129bceb
PO		 1390/*****************************************************************************\
1391 * *
1392 * MMC callbacks *
1393 * *
1394\*****************************************************************************/
1395
1396static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1397{
1398 struct sdhci_host *host;
505a8680 1399 int present;
d129bceb
PO		 1400 unsigned long flags;
1401
1402 host = mmc_priv(mmc);
1403
04e079cf 1404 /* Firstly check card presence */
8d28b7a7 1405 present = mmc->ops->get_cd(mmc);
2836766a 1406
d129bceb
PO		 1407 spin_lock_irqsave(&host->lock, flags);
1408
1409 WARN_ON(host->mrq != NULL);
1410
061d17a6 1411 sdhci_led_activate(host);
e89d456f
AW		 1412
1413 /*
1414 * Ensure we don't send the STOP for non-SET_BLOCK_COUNTED
1415 * requests if Auto-CMD12 is enabled.
1416 */
1417 if (!mrq->sbc && (host->flags & SDHCI_AUTO_CMD12)) {
c4512f79
JH		 1418 if (mrq->stop) {
1419 mrq->data->stop = NULL;
1420 mrq->stop = NULL;
1421 }
1422 }
d129bceb
PO		 1423
1424 host->mrq = mrq;
1425
68d1fb7e 1426 if (!present || host->flags & SDHCI_DEVICE_DEAD) {
a4c73aba 1427 mrq->cmd->error = -ENOMEDIUM;
a6d3bdd5 1428 sdhci_finish_mrq(host, mrq);
cf2b5eea 1429 } else {
8edf6371 1430 if (mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23))
e89d456f
AW		 1431 sdhci_send_command(host, mrq->sbc);
1432 else
1433 sdhci_send_command(host, mrq->cmd);
cf2b5eea 1434 }
d129bceb 1435
5f25a66f 1436 mmiowb();
d129bceb
PO		 1437 spin_unlock_irqrestore(&host->lock, flags);
1438}
1439
2317f56c
RK		 1440void sdhci_set_bus_width(struct sdhci_host *host, int width)
1441{
1442 u8 ctrl;
1443
1444 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1445 if (width == MMC_BUS_WIDTH_8) {
1446 ctrl &= ~SDHCI_CTRL_4BITBUS;
1447 if (host->version >= SDHCI_SPEC_300)
1448 ctrl |= SDHCI_CTRL_8BITBUS;
1449 } else {
1450 if (host->version >= SDHCI_SPEC_300)
1451 ctrl &= ~SDHCI_CTRL_8BITBUS;
1452 if (width == MMC_BUS_WIDTH_4)
1453 ctrl |= SDHCI_CTRL_4BITBUS;
1454 else
1455 ctrl &= ~SDHCI_CTRL_4BITBUS;
1456 }
1457 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1458}
1459EXPORT_SYMBOL_GPL(sdhci_set_bus_width);
1460
96d7b78c
RK		 1461void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing)
1462{
1463 u16 ctrl_2;
1464
1465 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1466 /* Select Bus Speed Mode for host */
1467 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
1468 if ((timing == MMC_TIMING_MMC_HS200) ||
1469 (timing == MMC_TIMING_UHS_SDR104))
1470 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
1471 else if (timing == MMC_TIMING_UHS_SDR12)
1472 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
1473 else if (timing == MMC_TIMING_UHS_SDR25)
1474 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
1475 else if (timing == MMC_TIMING_UHS_SDR50)
1476 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
1477 else if ((timing == MMC_TIMING_UHS_DDR50) ||
1478 (timing == MMC_TIMING_MMC_DDR52))
1479 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
e9fb05d5
AH		 1480 else if (timing == MMC_TIMING_MMC_HS400)
1481 ctrl_2 |= SDHCI_CTRL_HS400; /* Non-standard */
96d7b78c
RK		 1482 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1483}
1484EXPORT_SYMBOL_GPL(sdhci_set_uhs_signaling);
1485
ded97e0b 1486static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
d129bceb 1487{
ded97e0b 1488 struct sdhci_host *host = mmc_priv(mmc);
d129bceb
PO		 1489 unsigned long flags;
1490 u8 ctrl;
1491
d129bceb
PO		 1492 spin_lock_irqsave(&host->lock, flags);
1493
ceb6143b
AH		 1494 if (host->flags & SDHCI_DEVICE_DEAD) {
1495 spin_unlock_irqrestore(&host->lock, flags);
3a48edc4
TK		 1496 if (!IS_ERR(mmc->supply.vmmc) &&
1497 ios->power_mode == MMC_POWER_OFF)
4e743f1f 1498 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
ceb6143b
AH		 1499 return;
1500 }
1e72859e 1501
d129bceb
PO		 1502 /*
1503 * Reset the chip on each power off.
1504 * Should clear out any weird states.
1505 */
1506 if (ios->power_mode == MMC_POWER_OFF) {
4e4141a5 1507 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
7260cf5e 1508 sdhci_reinit(host);
d129bceb
PO		 1509 }
1510
52983382 1511 if (host->version >= SDHCI_SPEC_300 &&
372c4634
DA		 1512 (ios->power_mode == MMC_POWER_UP) &&
1513 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN))
52983382
KL		 1514 sdhci_enable_preset_value(host, false);
1515
373073ef 1516 if (!ios->clock || ios->clock != host->clock) {
1771059c 1517 host->ops->set_clock(host, ios->clock);
373073ef 1518 host->clock = ios->clock;
03d6f5ff
AD		 1519
1520 if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK &&
1521 host->clock) {
1522 host->timeout_clk = host->mmc->actual_clock ?
1523 host->mmc->actual_clock / 1000 :
1524 host->clock / 1000;
1525 host->mmc->max_busy_timeout =
1526 host->ops->get_max_timeout_count ?
1527 host->ops->get_max_timeout_count(host) :
1528 1 << 27;
1529 host->mmc->max_busy_timeout /= host->timeout_clk;
1530 }
373073ef 1531 }
d129bceb 1532
1dceb041 1533 __sdhci_set_power(host, ios->power_mode, ios->vdd);
d129bceb 1534
643a81ff
PR		 1535 if (host->ops->platform_send_init_74_clocks)
1536 host->ops->platform_send_init_74_clocks(host, ios->power_mode);
1537
2317f56c 1538 host->ops->set_bus_width(host, ios->bus_width);
ae6d6c92 1539
15ec4461 1540 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
cd9277c0 1541
3ab9c8da
PR		 1542 if ((ios->timing == MMC_TIMING_SD_HS ||
1543 ios->timing == MMC_TIMING_MMC_HS)
1544 && !(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT))
cd9277c0
PO		 1545 ctrl |= SDHCI_CTRL_HISPD;
1546 else
1547 ctrl &= ~SDHCI_CTRL_HISPD;
1548
d6d50a15 1549 if (host->version >= SDHCI_SPEC_300) {
49c468fc 1550 u16 clk, ctrl_2;
49c468fc
AN		 1551
1552 /* In case of UHS-I modes, set High Speed Enable */
e9fb05d5
AH		 1553 if ((ios->timing == MMC_TIMING_MMC_HS400) ||
1554 (ios->timing == MMC_TIMING_MMC_HS200) ||
bb8175a8 1555 (ios->timing == MMC_TIMING_MMC_DDR52) ||
069c9f14 1556 (ios->timing == MMC_TIMING_UHS_SDR50) ||
49c468fc
AN		 1557 (ios->timing == MMC_TIMING_UHS_SDR104) ||
1558 (ios->timing == MMC_TIMING_UHS_DDR50) ||
dd8df17f 1559 (ios->timing == MMC_TIMING_UHS_SDR25))
49c468fc 1560 ctrl |= SDHCI_CTRL_HISPD;
d6d50a15 1561
da91a8f9 1562 if (!host->preset_enabled) {
758535c4 1563 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d6d50a15
AN		 1564 /*
1565 * We only need to set Driver Strength if the
1566 * preset value enable is not set.
1567 */
da91a8f9 1568 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
d6d50a15
AN		 1569 ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK;
1570 if (ios->drv_type == MMC_SET_DRIVER_TYPE_A)
1571 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A;
43e943a0
PG		 1572 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_B)
1573 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_B;
d6d50a15
AN		 1574 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C)
1575 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C;
43e943a0
PG		 1576 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_D)
1577 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_D;
1578 else {
2e4456f0
MV		 1579 pr_warn("%s: invalid driver type, default to driver type B\n",
1580 mmc_hostname(mmc));
43e943a0
PG		 1581 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_B;
1582 }
d6d50a15
AN		 1583
1584 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
758535c4
AN		 1585 } else {
1586 /*
1587 * According to SDHC Spec v3.00, if the Preset Value
1588 * Enable in the Host Control 2 register is set, we
1589 * need to reset SD Clock Enable before changing High
1590 * Speed Enable to avoid generating clock gliches.
1591 */
758535c4
AN		 1592
1593 /* Reset SD Clock Enable */
1594 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1595 clk &= ~SDHCI_CLOCK_CARD_EN;
1596 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1597
1598 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1599
1600 /* Re-enable SD Clock */
1771059c 1601 host->ops->set_clock(host, host->clock);
d6d50a15 1602 }
49c468fc 1603
49c468fc
AN		 1604 /* Reset SD Clock Enable */
1605 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1606 clk &= ~SDHCI_CLOCK_CARD_EN;
1607 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1608
96d7b78c 1609 host->ops->set_uhs_signaling(host, ios->timing);
d975f121 1610 host->timing = ios->timing;
49c468fc 1611
52983382
KL		 1612 if (!(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN) &&
1613 ((ios->timing == MMC_TIMING_UHS_SDR12) ||
1614 (ios->timing == MMC_TIMING_UHS_SDR25) ||
1615 (ios->timing == MMC_TIMING_UHS_SDR50) ||
1616 (ios->timing == MMC_TIMING_UHS_SDR104) ||
0dafa60e
JZ		 1617 (ios->timing == MMC_TIMING_UHS_DDR50) ||
1618 (ios->timing == MMC_TIMING_MMC_DDR52))) {
52983382
KL		 1619 u16 preset;
1620
1621 sdhci_enable_preset_value(host, true);
1622 preset = sdhci_get_preset_value(host);
1623 ios->drv_type = (preset & SDHCI_PRESET_DRV_MASK)
1624 >> SDHCI_PRESET_DRV_SHIFT;
1625 }
1626
49c468fc 1627 /* Re-enable SD Clock */
1771059c 1628 host->ops->set_clock(host, host->clock);
758535c4
AN		 1629 } else
1630 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d6d50a15 1631
b8352260
LD		 1632 /*
1633 * Some (ENE) controllers go apeshit on some ios operation,
1634 * signalling timeout and CRC errors even on CMD0. Resetting
1635 * it on each ios seems to solve the problem.
1636 */
c63705e1 1637 if (host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
03231f9b 1638 sdhci_do_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
b8352260 1639
5f25a66f 1640 mmiowb();
d129bceb
PO		 1641 spin_unlock_irqrestore(&host->lock, flags);
1642}
1643
ded97e0b 1644static int sdhci_get_cd(struct mmc_host *mmc)
66fd8ad5
AH		 1645{
1646 struct sdhci_host *host = mmc_priv(mmc);
ded97e0b 1647 int gpio_cd = mmc_gpio_get_cd(mmc);
94144a46
KL		 1648
1649 if (host->flags & SDHCI_DEVICE_DEAD)
1650 return 0;
1651
88af5655 1652 /* If nonremovable, assume that the card is always present. */
860951c5 1653 if (!mmc_card_is_removable(host->mmc))
94144a46
KL		 1654 return 1;
1655
88af5655
II		 1656 /*
1657 * Try slot gpio detect, if defined it take precedence
1658 * over build in controller functionality
1659 */
287980e4 1660 if (gpio_cd >= 0)
94144a46
KL		 1661 return !!gpio_cd;
1662
88af5655
II		 1663 /* If polling, assume that the card is always present. */
1664 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
1665 return 1;
1666
94144a46
KL		 1667 /* Host native card detect */
1668 return !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
1669}
1670
66fd8ad5 1671static int sdhci_check_ro(struct sdhci_host *host)
d129bceb 1672{
d129bceb 1673 unsigned long flags;
2dfb579c 1674 int is_readonly;
d129bceb 1675
d129bceb
PO		 1676 spin_lock_irqsave(&host->lock, flags);
1677
1e72859e 1678 if (host->flags & SDHCI_DEVICE_DEAD)
2dfb579c
WS		 1679 is_readonly = 0;
1680 else if (host->ops->get_ro)
1681 is_readonly = host->ops->get_ro(host);
1e72859e 1682 else
2dfb579c
WS		 1683 is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE)
1684 & SDHCI_WRITE_PROTECT);
d129bceb
PO		 1685
1686 spin_unlock_irqrestore(&host->lock, flags);
1687
2dfb579c
WS		 1688 /* This quirk needs to be replaced by a callback-function later */
1689 return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ?
1690 !is_readonly : is_readonly;
d129bceb
PO		 1691}
1692
82b0e23a
TI		 1693#define SAMPLE_COUNT 5
1694
ded97e0b 1695static int sdhci_get_ro(struct mmc_host *mmc)
82b0e23a 1696{
ded97e0b 1697 struct sdhci_host *host = mmc_priv(mmc);
82b0e23a
TI		 1698 int i, ro_count;
1699
82b0e23a 1700 if (!(host->quirks & SDHCI_QUIRK_UNSTABLE_RO_DETECT))
66fd8ad5 1701 return sdhci_check_ro(host);
82b0e23a
TI		 1702
1703 ro_count = 0;
1704 for (i = 0; i < SAMPLE_COUNT; i++) {
66fd8ad5 1705 if (sdhci_check_ro(host)) {
82b0e23a
TI		 1706 if (++ro_count > SAMPLE_COUNT / 2)
1707 return 1;
1708 }
1709 msleep(30);
1710 }
1711 return 0;
1712}
1713
20758b66
AH		 1714static void sdhci_hw_reset(struct mmc_host *mmc)
1715{
1716 struct sdhci_host *host = mmc_priv(mmc);
1717
1718 if (host->ops && host->ops->hw_reset)
1719 host->ops->hw_reset(host);
1720}
1721
66fd8ad5
AH		 1722static void sdhci_enable_sdio_irq_nolock(struct sdhci_host *host, int enable)
1723{
be138554 1724 if (!(host->flags & SDHCI_DEVICE_DEAD)) {
ef104333 1725 if (enable)
b537f94c 1726 host->ier |= SDHCI_INT_CARD_INT;
ef104333 1727 else
b537f94c
RK		 1728 host->ier &= ~SDHCI_INT_CARD_INT;
1729
1730 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
1731 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
ef104333
RK		 1732 mmiowb();
1733 }
66fd8ad5
AH		 1734}
1735
1736static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1737{
1738 struct sdhci_host *host = mmc_priv(mmc);
1739 unsigned long flags;
f75979b7 1740
66fd8ad5 1741 spin_lock_irqsave(&host->lock, flags);
ef104333
RK		 1742 if (enable)
1743 host->flags |= SDHCI_SDIO_IRQ_ENABLED;
1744 else
1745 host->flags &= ~SDHCI_SDIO_IRQ_ENABLED;
1746
66fd8ad5 1747 sdhci_enable_sdio_irq_nolock(host, enable);
f75979b7
PO		 1748 spin_unlock_irqrestore(&host->lock, flags);
1749}
1750
ded97e0b
DA		 1751static int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
1752 struct mmc_ios *ios)
f2119df6 1753{
ded97e0b 1754 struct sdhci_host *host = mmc_priv(mmc);
20b92a30 1755 u16 ctrl;
6231f3de 1756 int ret;
f2119df6 1757
20b92a30
KL		 1758 /*
1759 * Signal Voltage Switching is only applicable for Host Controllers
1760 * v3.00 and above.
1761 */
1762 if (host->version < SDHCI_SPEC_300)
1763 return 0;
6231f3de 1764
f2119df6 1765 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
f2119df6 1766
21f5998f 1767 switch (ios->signal_voltage) {
20b92a30 1768 case MMC_SIGNAL_VOLTAGE_330:
8cb851a4
AH		 1769 if (!(host->flags & SDHCI_SIGNALING_330))
1770 return -EINVAL;
20b92a30
KL		 1771 /* Set 1.8V Signal Enable in the Host Control2 register to 0 */
1772 ctrl &= ~SDHCI_CTRL_VDD_180;
1773 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
f2119df6 1774
3a48edc4
TK		 1775 if (!IS_ERR(mmc->supply.vqmmc)) {
1776 ret = regulator_set_voltage(mmc->supply.vqmmc, 2700000,
1777 3600000);
20b92a30 1778 if (ret) {
6606110d
JP		 1779 pr_warn("%s: Switching to 3.3V signalling voltage failed\n",
1780 mmc_hostname(mmc));
20b92a30
KL		 1781 return -EIO;
1782 }
1783 }
1784 /* Wait for 5ms */
1785 usleep_range(5000, 5500);
f2119df6 1786
20b92a30
KL		 1787 /* 3.3V regulator output should be stable within 5 ms */
1788 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1789 if (!(ctrl & SDHCI_CTRL_VDD_180))
1790 return 0;
6231f3de 1791
6606110d
JP		 1792 pr_warn("%s: 3.3V regulator output did not became stable\n",
1793 mmc_hostname(mmc));
20b92a30
KL		 1794
1795 return -EAGAIN;
1796 case MMC_SIGNAL_VOLTAGE_180:
8cb851a4
AH		 1797 if (!(host->flags & SDHCI_SIGNALING_180))
1798 return -EINVAL;
3a48edc4
TK		 1799 if (!IS_ERR(mmc->supply.vqmmc)) {
1800 ret = regulator_set_voltage(mmc->supply.vqmmc,
20b92a30
KL		 1801 1700000, 1950000);
1802 if (ret) {
6606110d
JP		 1803 pr_warn("%s: Switching to 1.8V signalling voltage failed\n",
1804 mmc_hostname(mmc));
20b92a30
KL		 1805 return -EIO;
1806 }
1807 }
6231f3de 1808
6231f3de
PR		 1809 /*
1810 * Enable 1.8V Signal Enable in the Host Control2
1811 * register
1812 */
20b92a30
KL		 1813 ctrl |= SDHCI_CTRL_VDD_180;
1814 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
6231f3de 1815
9d967a61
VY		 1816 /* Some controller need to do more when switching */
1817 if (host->ops->voltage_switch)
1818 host->ops->voltage_switch(host);
1819
20b92a30
KL		 1820 /* 1.8V regulator output should be stable within 5 ms */
1821 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1822 if (ctrl & SDHCI_CTRL_VDD_180)
1823 return 0;
f2119df6 1824
6606110d
JP		 1825 pr_warn("%s: 1.8V regulator output did not became stable\n",
1826 mmc_hostname(mmc));
f2119df6 1827
20b92a30
KL		 1828 return -EAGAIN;
1829 case MMC_SIGNAL_VOLTAGE_120:
8cb851a4
AH		 1830 if (!(host->flags & SDHCI_SIGNALING_120))
1831 return -EINVAL;
3a48edc4
TK		 1832 if (!IS_ERR(mmc->supply.vqmmc)) {
1833 ret = regulator_set_voltage(mmc->supply.vqmmc, 1100000,
1834 1300000);
20b92a30 1835 if (ret) {
6606110d
JP		 1836 pr_warn("%s: Switching to 1.2V signalling voltage failed\n",
1837 mmc_hostname(mmc));
20b92a30 1838 return -EIO;
f2119df6
AN		 1839 }
1840 }
6231f3de 1841 return 0;
20b92a30 1842 default:
f2119df6
AN		 1843 /* No signal voltage switch required */
1844 return 0;
20b92a30 1845 }
f2119df6
AN		 1846}
1847
20b92a30
KL		 1848static int sdhci_card_busy(struct mmc_host *mmc)
1849{
1850 struct sdhci_host *host = mmc_priv(mmc);
1851 u32 present_state;
1852
e613cc47 1853 /* Check whether DAT[0] is 0 */
20b92a30 1854 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
20b92a30 1855
e613cc47 1856 return !(present_state & SDHCI_DATA_0_LVL_MASK);
20b92a30
KL		 1857}
1858
b5540ce1
AH		 1859static int sdhci_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios)
1860{
1861 struct sdhci_host *host = mmc_priv(mmc);
1862 unsigned long flags;
1863
1864 spin_lock_irqsave(&host->lock, flags);
1865 host->flags |= SDHCI_HS400_TUNING;
1866 spin_unlock_irqrestore(&host->lock, flags);
1867
1868 return 0;
1869}
1870
069c9f14 1871static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode)
b513ea25 1872{
4b6f37d3 1873 struct sdhci_host *host = mmc_priv(mmc);
b513ea25 1874 u16 ctrl;
b513ea25 1875 int tuning_loop_counter = MAX_TUNING_LOOP;
b513ea25 1876 int err = 0;
2b35bd83 1877 unsigned long flags;
38e40bf5 1878 unsigned int tuning_count = 0;
b5540ce1 1879 bool hs400_tuning;
b513ea25 1880
2b35bd83 1881 spin_lock_irqsave(&host->lock, flags);
b513ea25 1882
b5540ce1
AH		 1883 hs400_tuning = host->flags & SDHCI_HS400_TUNING;
1884 host->flags &= ~SDHCI_HS400_TUNING;
1885
38e40bf5
AH		 1886 if (host->tuning_mode == SDHCI_TUNING_MODE_1)
1887 tuning_count = host->tuning_count;
1888
b513ea25 1889 /*
9faac7b9
WY		 1890 * The Host Controller needs tuning in case of SDR104 and DDR50
1891 * mode, and for SDR50 mode when Use Tuning for SDR50 is set in
1892 * the Capabilities register.
069c9f14
G		 1893 * If the Host Controller supports the HS200 mode then the
1894 * tuning function has to be executed.
b513ea25 1895 */
4b6f37d3 1896 switch (host->timing) {
b5540ce1 1897 /* HS400 tuning is done in HS200 mode */
e9fb05d5 1898 case MMC_TIMING_MMC_HS400:
b5540ce1
AH		 1899 err = -EINVAL;
1900 goto out_unlock;
1901
4b6f37d3 1902 case MMC_TIMING_MMC_HS200:
b5540ce1
AH		 1903 /*
1904 * Periodic re-tuning for HS400 is not expected to be needed, so
1905 * disable it here.
1906 */
1907 if (hs400_tuning)
1908 tuning_count = 0;
1909 break;
1910
4b6f37d3 1911 case MMC_TIMING_UHS_SDR104:
9faac7b9 1912 case MMC_TIMING_UHS_DDR50:
4b6f37d3
RK		 1913 break;
1914
1915 case MMC_TIMING_UHS_SDR50:
4228b213 1916 if (host->flags & SDHCI_SDR50_NEEDS_TUNING)
4b6f37d3
RK		 1917 break;
1918 /* FALLTHROUGH */
1919
1920 default:
d519c863 1921 goto out_unlock;
b513ea25
AN		 1922 }
1923
45251812 1924 if (host->ops->platform_execute_tuning) {
2b35bd83 1925 spin_unlock_irqrestore(&host->lock, flags);
45251812 1926 err = host->ops->platform_execute_tuning(host, opcode);
45251812
DA		 1927 return err;
1928 }
1929
4b6f37d3
RK		 1930 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1931 ctrl |= SDHCI_CTRL_EXEC_TUNING;
67d0d04a
VY		 1932 if (host->quirks2 & SDHCI_QUIRK2_TUNING_WORK_AROUND)
1933 ctrl |= SDHCI_CTRL_TUNED_CLK;
b513ea25
AN		 1934 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1935
1936 /*
1937 * As per the Host Controller spec v3.00, tuning command
1938 * generates Buffer Read Ready interrupt, so enable that.
1939 *
1940 * Note: The spec clearly says that when tuning sequence
1941 * is being performed, the controller does not generate
1942 * interrupts other than Buffer Read Ready interrupt. But
1943 * to make sure we don't hit a controller bug, we _only_
1944 * enable Buffer Read Ready interrupt here.
1945 */
b537f94c
RK		 1946 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE);
1947 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE);
b513ea25
AN		 1948
1949 /*
1950 * Issue CMD19 repeatedly till Execute Tuning is set to 0 or the number
1473bdd5 1951 * of loops reaches 40 times.
b513ea25 1952 */
b513ea25
AN		 1953 do {
1954 struct mmc_command cmd = {0};
66fd8ad5 1955 struct mmc_request mrq = {NULL};
b513ea25 1956
069c9f14 1957 cmd.opcode = opcode;
b513ea25
AN		 1958 cmd.arg = 0;
1959 cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
1960 cmd.retries = 0;
1961 cmd.data = NULL;
1962 cmd.error = 0;
1963
7ce45e95
AC		 1964 if (tuning_loop_counter-- == 0)
1965 break;
1966
b513ea25
AN		 1967 mrq.cmd = &cmd;
1968 host->mrq = &mrq;
1969
1970 /*
1971 * In response to CMD19, the card sends 64 bytes of tuning
1972 * block to the Host Controller. So we set the block size
1973 * to 64 here.
1974 */
069c9f14
G		 1975 if (cmd.opcode == MMC_SEND_TUNING_BLOCK_HS200) {
1976 if (mmc->ios.bus_width == MMC_BUS_WIDTH_8)
1977 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 128),
1978 SDHCI_BLOCK_SIZE);
1979 else if (mmc->ios.bus_width == MMC_BUS_WIDTH_4)
1980 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
1981 SDHCI_BLOCK_SIZE);
1982 } else {
1983 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
1984 SDHCI_BLOCK_SIZE);
1985 }
b513ea25
AN		 1986
1987 /*
1988 * The tuning block is sent by the card to the host controller.
1989 * So we set the TRNS_READ bit in the Transfer Mode register.
1990 * This also takes care of setting DMA Enable and Multi Block
1991 * Select in the same register to 0.
1992 */
1993 sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
1994
1995 sdhci_send_command(host, &cmd);
1996
1997 host->cmd = NULL;
1998 host->mrq = NULL;
1999
2b35bd83 2000 spin_unlock_irqrestore(&host->lock, flags);
b513ea25
AN		 2001 /* Wait for Buffer Read Ready interrupt */
2002 wait_event_interruptible_timeout(host->buf_ready_int,
2003 (host->tuning_done == 1),
2004 msecs_to_jiffies(50));
2b35bd83 2005 spin_lock_irqsave(&host->lock, flags);
b513ea25
AN		 2006
2007 if (!host->tuning_done) {
2e4456f0 2008 pr_info(DRIVER_NAME ": Timeout waiting for Buffer Read Ready interrupt during tuning procedure, falling back to fixed sampling clock\n");
b513ea25
AN		 2009 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2010 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
2011 ctrl &= ~SDHCI_CTRL_EXEC_TUNING;
2012 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2013
2014 err = -EIO;
2015 goto out;
2016 }
2017
2018 host->tuning_done = 0;
2019
2020 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
197160d5
NS		 2021
2022 /* eMMC spec does not require a delay between tuning cycles */
2023 if (opcode == MMC_SEND_TUNING_BLOCK)
2024 mdelay(1);
b513ea25
AN		 2025 } while (ctrl & SDHCI_CTRL_EXEC_TUNING);
2026
2027 /*
2028 * The Host Driver has exhausted the maximum number of loops allowed,
2029 * so use fixed sampling frequency.
2030 */
7ce45e95 2031 if (tuning_loop_counter < 0) {
b513ea25
AN		 2032 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
2033 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
7ce45e95
AC		 2034 }
2035 if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) {
2e4456f0 2036 pr_info(DRIVER_NAME ": Tuning procedure failed, falling back to fixed sampling clock\n");
114f2bf6 2037 err = -EIO;
b513ea25
AN		 2038 }
2039
2040out:
38e40bf5 2041 if (tuning_count) {
66c39dfc
AH		 2042 /*
2043 * In case tuning fails, host controllers which support
2044 * re-tuning can try tuning again at a later time, when the
2045 * re-tuning timer expires. So for these controllers, we
2046 * return 0. Since there might be other controllers who do not
2047 * have this capability, we return error for them.
2048 */
2049 err = 0;
cf2b5eea
AN		 2050 }
2051
66c39dfc 2052 host->mmc->retune_period = err ? 0 : tuning_count;
cf2b5eea 2053
b537f94c
RK		 2054 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2055 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
d519c863 2056out_unlock:
2b35bd83 2057 spin_unlock_irqrestore(&host->lock, flags);
b513ea25
AN		 2058 return err;
2059}
2060
cb849648
AH		 2061static int sdhci_select_drive_strength(struct mmc_card *card,
2062 unsigned int max_dtr, int host_drv,
2063 int card_drv, int *drv_type)
2064{
2065 struct sdhci_host *host = mmc_priv(card->host);
2066
2067 if (!host->ops->select_drive_strength)
2068 return 0;
2069
2070 return host->ops->select_drive_strength(host, card, max_dtr, host_drv,
2071 card_drv, drv_type);
2072}
52983382
KL		 2073
2074static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable)
4d55c5a1 2075{
4d55c5a1
AN		 2076 /* Host Controller v3.00 defines preset value registers */
2077 if (host->version < SDHCI_SPEC_300)
2078 return;
2079
4d55c5a1
AN		 2080 /*
2081 * We only enable or disable Preset Value if they are not already
2082 * enabled or disabled respectively. Otherwise, we bail out.
2083 */
da91a8f9
RK		 2084 if (host->preset_enabled != enable) {
2085 u16 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2086
2087 if (enable)
2088 ctrl |= SDHCI_CTRL_PRESET_VAL_ENABLE;
2089 else
2090 ctrl &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
2091
4d55c5a1 2092 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
da91a8f9
RK		 2093
2094 if (enable)
2095 host->flags |= SDHCI_PV_ENABLED;
2096 else
2097 host->flags &= ~SDHCI_PV_ENABLED;
2098
2099 host->preset_enabled = enable;
4d55c5a1 2100 }
66fd8ad5
AH		 2101}
2102
348487cb
HC		 2103static void sdhci_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
2104 int err)
2105{
2106 struct sdhci_host *host = mmc_priv(mmc);
2107 struct mmc_data *data = mrq->data;
2108
f48f039c 2109 if (data->host_cookie != COOKIE_UNMAPPED)
771a3dc2
RK		 2110 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
2111 data->flags & MMC_DATA_WRITE ?
2112 DMA_TO_DEVICE : DMA_FROM_DEVICE);
2113
2114 data->host_cookie = COOKIE_UNMAPPED;
348487cb
HC		 2115}
2116
348487cb
HC		 2117static void sdhci_pre_req(struct mmc_host *mmc, struct mmc_request *mrq,
2118 bool is_first_req)
2119{
2120 struct sdhci_host *host = mmc_priv(mmc);
2121
d31911b9 2122 mrq->data->host_cookie = COOKIE_UNMAPPED;
348487cb
HC		 2123
2124 if (host->flags & SDHCI_REQ_USE_DMA)
94538e51 2125 sdhci_pre_dma_transfer(host, mrq->data, COOKIE_PRE_MAPPED);
348487cb
HC		 2126}
2127
71e69211 2128static void sdhci_card_event(struct mmc_host *mmc)
d129bceb 2129{
71e69211 2130 struct sdhci_host *host = mmc_priv(mmc);
d129bceb 2131 unsigned long flags;
2836766a 2132 int present;
d129bceb 2133
722e1280
CD		 2134 /* First check if client has provided their own card event */
2135 if (host->ops->card_event)
2136 host->ops->card_event(host);
2137
d3940f27 2138 present = mmc->ops->get_cd(mmc);
2836766a 2139
d129bceb
PO		 2140 spin_lock_irqsave(&host->lock, flags);
2141
66fd8ad5 2142 /* Check host->mrq first in case we are runtime suspended */
2836766a 2143 if (host->mrq && !present) {
a3c76eb9 2144 pr_err("%s: Card removed during transfer!\n",
66fd8ad5 2145 mmc_hostname(host->mmc));
a3c76eb9 2146 pr_err("%s: Resetting controller.\n",
66fd8ad5 2147 mmc_hostname(host->mmc));
d129bceb 2148
03231f9b
RK		 2149 sdhci_do_reset(host, SDHCI_RESET_CMD);
2150 sdhci_do_reset(host, SDHCI_RESET_DATA);
d129bceb 2151
66fd8ad5 2152 host->mrq->cmd->error = -ENOMEDIUM;
a6d3bdd5 2153 sdhci_finish_mrq(host, host->mrq);
d129bceb
PO		 2154 }
2155
2156 spin_unlock_irqrestore(&host->lock, flags);
71e69211
GL		 2157}
2158
2159static const struct mmc_host_ops sdhci_ops = {
2160 .request = sdhci_request,
348487cb
HC		 2161 .post_req = sdhci_post_req,
2162 .pre_req = sdhci_pre_req,
71e69211 2163 .set_ios = sdhci_set_ios,
94144a46 2164 .get_cd = sdhci_get_cd,
71e69211
GL		 2165 .get_ro = sdhci_get_ro,
2166 .hw_reset = sdhci_hw_reset,
2167 .enable_sdio_irq = sdhci_enable_sdio_irq,
2168 .start_signal_voltage_switch = sdhci_start_signal_voltage_switch,
b5540ce1 2169 .prepare_hs400_tuning = sdhci_prepare_hs400_tuning,
71e69211 2170 .execute_tuning = sdhci_execute_tuning,
cb849648 2171 .select_drive_strength = sdhci_select_drive_strength,
71e69211 2172 .card_event = sdhci_card_event,
20b92a30 2173 .card_busy = sdhci_card_busy,
71e69211
GL		 2174};
2175
2176/*****************************************************************************\
2177 * *
2178 * Tasklets *
2179 * *
2180\*****************************************************************************/
2181
d129bceb
PO		 2182static void sdhci_tasklet_finish(unsigned long param)
2183{
2184 struct sdhci_host *host;
2185 unsigned long flags;
2186 struct mmc_request *mrq;
2187
2188 host = (struct sdhci_host*)param;
2189
66fd8ad5
AH		 2190 spin_lock_irqsave(&host->lock, flags);
2191
0c9c99a7
CB		 2192 /*
2193 * If this tasklet gets rescheduled while running, it will
2194 * be run again afterwards but without any active request.
2195 */
66fd8ad5
AH		 2196 if (!host->mrq) {
2197 spin_unlock_irqrestore(&host->lock, flags);
0c9c99a7 2198 return;
66fd8ad5 2199 }
d129bceb
PO		 2200
2201 del_timer(&host->timer);
2202
2203 mrq = host->mrq;
2204
054cedff
RK		 2205 /*
2206 * Always unmap the data buffers if they were mapped by
2207 * sdhci_prepare_data() whenever we finish with a request.
2208 * This avoids leaking DMA mappings on error.
2209 */
2210 if (host->flags & SDHCI_REQ_USE_DMA) {
2211 struct mmc_data *data = mrq->data;
2212
2213 if (data && data->host_cookie == COOKIE_MAPPED) {
2214 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
2215 (data->flags & MMC_DATA_READ) ?
2216 DMA_FROM_DEVICE : DMA_TO_DEVICE);
2217 data->host_cookie = COOKIE_UNMAPPED;
2218 }
2219 }
2220
d129bceb
PO		 2221 /*
2222 * The controller needs a reset of internal state machines
2223 * upon error conditions.
2224 */
0cc563ce 2225 if (sdhci_needs_reset(host, mrq)) {
645289dc 2226 /* Some controllers need this kick or reset won't work here */
8213af3b 2227 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)
645289dc 2228 /* This is to force an update */
1771059c 2229 host->ops->set_clock(host, host->clock);
645289dc
PO		 2230
2231 /* Spec says we should do both at the same time, but Ricoh
2232 controllers do not like that. */
03231f9b
RK		 2233 sdhci_do_reset(host, SDHCI_RESET_CMD);
2234 sdhci_do_reset(host, SDHCI_RESET_DATA);
d129bceb
PO		 2235 }
2236
2237 host->mrq = NULL;
2238 host->cmd = NULL;
2239 host->data = NULL;
7c89a3d9 2240 host->data_cmd = NULL;
d129bceb 2241
061d17a6 2242 sdhci_led_deactivate(host);
d129bceb 2243
5f25a66f 2244 mmiowb();
d129bceb
PO		 2245 spin_unlock_irqrestore(&host->lock, flags);
2246
2247 mmc_request_done(host->mmc, mrq);
2248}
2249
2250static void sdhci_timeout_timer(unsigned long data)
2251{
2252 struct sdhci_host *host;
2253 unsigned long flags;
2254
2255 host = (struct sdhci_host*)data;
2256
2257 spin_lock_irqsave(&host->lock, flags);
2258
2259 if (host->mrq) {
2e4456f0
MV		 2260 pr_err("%s: Timeout waiting for hardware interrupt.\n",
2261 mmc_hostname(host->mmc));
d129bceb
PO		 2262 sdhci_dumpregs(host);
2263
2264 if (host->data) {
17b0429d 2265 host->data->error = -ETIMEDOUT;
d129bceb
PO		 2266 sdhci_finish_data(host);
2267 } else {
2268 if (host->cmd)
17b0429d 2269 host->cmd->error = -ETIMEDOUT;
d129bceb 2270 else
17b0429d 2271 host->mrq->cmd->error = -ETIMEDOUT;
d129bceb 2272
a6d3bdd5 2273 sdhci_finish_mrq(host, host->mrq);
d129bceb
PO		 2274 }
2275 }
2276
5f25a66f 2277 mmiowb();
d129bceb
PO		 2278 spin_unlock_irqrestore(&host->lock, flags);
2279}
2280
2281/*****************************************************************************\
2282 * *
2283 * Interrupt handling *
2284 * *
2285\*****************************************************************************/
2286
61541397 2287static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask, u32 *mask)
d129bceb 2288{
d129bceb 2289 if (!host->cmd) {
2e4456f0
MV		 2290 pr_err("%s: Got command interrupt 0x%08x even though no command operation was in progress.\n",
2291 mmc_hostname(host->mmc), (unsigned)intmask);
d129bceb
PO		 2292 sdhci_dumpregs(host);
2293 return;
2294 }
2295
ec014cba
RK		 2296 if (intmask & (SDHCI_INT_TIMEOUT | SDHCI_INT_CRC |
2297 SDHCI_INT_END_BIT | SDHCI_INT_INDEX)) {
2298 if (intmask & SDHCI_INT_TIMEOUT)
2299 host->cmd->error = -ETIMEDOUT;
2300 else
2301 host->cmd->error = -EILSEQ;
43b58b36 2302
71fcbda0
RK		 2303 /*
2304 * If this command initiates a data phase and a response
2305 * CRC error is signalled, the card can start transferring
2306 * data - the card may have received the command without
2307 * error. We must not terminate the mmc_request early.
2308 *
2309 * If the card did not receive the command or returned an
2310 * error which prevented it sending data, the data phase
2311 * will time out.
2312 */
2313 if (host->cmd->data &&
2314 (intmask & (SDHCI_INT_CRC | SDHCI_INT_TIMEOUT)) ==
2315 SDHCI_INT_CRC) {
2316 host->cmd = NULL;
2317 return;
2318 }
2319
a6d3bdd5 2320 sdhci_finish_mrq(host, host->cmd->mrq);
e809517f
PO		 2321 return;
2322 }
2323
6bde8681
AH		 2324 if ((host->quirks2 & SDHCI_QUIRK2_STOP_WITH_TC) &&
2325 !(host->cmd->flags & MMC_RSP_BUSY) && !host->data &&
2326 host->cmd->opcode == MMC_STOP_TRANSMISSION)
61541397 2327 *mask &= ~SDHCI_INT_DATA_END;
e809517f
PO		 2328
2329 if (intmask & SDHCI_INT_RESPONSE)
43b58b36 2330 sdhci_finish_command(host);
d129bceb
PO		 2331}
2332
0957c333 2333#ifdef CONFIG_MMC_DEBUG
08621b18 2334static void sdhci_adma_show_error(struct sdhci_host *host)
6882a8c0
BD		 2335{
2336 const char *name = mmc_hostname(host->mmc);
1c3d5f6d 2337 void *desc = host->adma_table;
6882a8c0
BD		 2338
2339 sdhci_dumpregs(host);
2340
2341 while (true) {
e57a5f61
AH		 2342 struct sdhci_adma2_64_desc *dma_desc = desc;
2343
2344 if (host->flags & SDHCI_USE_64_BIT_DMA)
2345 DBG("%s: %p: DMA 0x%08x%08x, LEN 0x%04x, Attr=0x%02x\n",
2346 name, desc, le32_to_cpu(dma_desc->addr_hi),
2347 le32_to_cpu(dma_desc->addr_lo),
2348 le16_to_cpu(dma_desc->len),
2349 le16_to_cpu(dma_desc->cmd));
2350 else
2351 DBG("%s: %p: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n",
2352 name, desc, le32_to_cpu(dma_desc->addr_lo),
2353 le16_to_cpu(dma_desc->len),
2354 le16_to_cpu(dma_desc->cmd));
6882a8c0 2355
76fe379a 2356 desc += host->desc_sz;
6882a8c0 2357
0545230f 2358 if (dma_desc->cmd & cpu_to_le16(ADMA2_END))
6882a8c0
BD		 2359 break;
2360 }
2361}
2362#else
08621b18 2363static void sdhci_adma_show_error(struct sdhci_host *host) { }
6882a8c0
BD		 2364#endif
2365
d129bceb
PO		 2366static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
2367{
069c9f14 2368 u32 command;
d129bceb 2369
b513ea25
AN		 2370 /* CMD19 generates _only_ Buffer Read Ready interrupt */
2371 if (intmask & SDHCI_INT_DATA_AVAIL) {
069c9f14
G		 2372 command = SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND));
2373 if (command == MMC_SEND_TUNING_BLOCK ||
2374 command == MMC_SEND_TUNING_BLOCK_HS200) {
b513ea25
AN		 2375 host->tuning_done = 1;
2376 wake_up(&host->buf_ready_int);
2377 return;
2378 }
2379 }
2380
d129bceb 2381 if (!host->data) {
7c89a3d9
AH		 2382 struct mmc_command *data_cmd = host->data_cmd;
2383
2384 if (data_cmd)
2385 host->data_cmd = NULL;
2386
d129bceb 2387 /*
e809517f
PO		 2388 * The "data complete" interrupt is also used to
2389 * indicate that a busy state has ended. See comment
2390 * above in sdhci_cmd_irq().
d129bceb 2391 */
7c89a3d9 2392 if (data_cmd && (data_cmd->flags & MMC_RSP_BUSY)) {
c5abd5e8 2393 if (intmask & SDHCI_INT_DATA_TIMEOUT) {
7c89a3d9 2394 data_cmd->error = -ETIMEDOUT;
a6d3bdd5 2395 sdhci_finish_mrq(host, data_cmd->mrq);
c5abd5e8
MC		 2396 return;
2397 }
e809517f 2398 if (intmask & SDHCI_INT_DATA_END) {
e99783a4
CM		 2399 /*
2400 * Some cards handle busy-end interrupt
2401 * before the command completed, so make
2402 * sure we do things in the proper order.
2403 */
ea968023
AH		 2404 if (host->cmd == data_cmd)
2405 return;
2406
a6d3bdd5 2407 sdhci_finish_mrq(host, data_cmd->mrq);
e809517f
PO		 2408 return;
2409 }
2410 }
d129bceb 2411
2e4456f0
MV		 2412 pr_err("%s: Got data interrupt 0x%08x even though no data operation was in progress.\n",
2413 mmc_hostname(host->mmc), (unsigned)intmask);
d129bceb
PO		 2414 sdhci_dumpregs(host);
2415
2416 return;
2417 }
2418
2419 if (intmask & SDHCI_INT_DATA_TIMEOUT)
17b0429d 2420 host->data->error = -ETIMEDOUT;
22113efd
AL		 2421 else if (intmask & SDHCI_INT_DATA_END_BIT)
2422 host->data->error = -EILSEQ;
2423 else if ((intmask & SDHCI_INT_DATA_CRC) &&
2424 SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))
2425 != MMC_BUS_TEST_R)
17b0429d 2426 host->data->error = -EILSEQ;
6882a8c0 2427 else if (intmask & SDHCI_INT_ADMA_ERROR) {
a3c76eb9 2428 pr_err("%s: ADMA error\n", mmc_hostname(host->mmc));
08621b18 2429 sdhci_adma_show_error(host);
2134a922 2430 host->data->error = -EIO;
a4071fbb
HZ		 2431 if (host->ops->adma_workaround)
2432 host->ops->adma_workaround(host, intmask);
6882a8c0 2433 }
d129bceb 2434
17b0429d 2435 if (host->data->error)
d129bceb
PO		 2436 sdhci_finish_data(host);
2437 else {
a406f5a3 2438 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
d129bceb
PO		 2439 sdhci_transfer_pio(host);
2440
6ba736a1
PO		 2441 /*
2442 * We currently don't do anything fancy with DMA
2443 * boundaries, but as we can't disable the feature
2444 * we need to at least restart the transfer.
f6a03cbf
MV		 2445 *
2446 * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS)
2447 * should return a valid address to continue from, but as
2448 * some controllers are faulty, don't trust them.
6ba736a1 2449 */
f6a03cbf
MV		 2450 if (intmask & SDHCI_INT_DMA_END) {
2451 u32 dmastart, dmanow;
2452 dmastart = sg_dma_address(host->data->sg);
2453 dmanow = dmastart + host->data->bytes_xfered;
2454 /*
2455 * Force update to the next DMA block boundary.
2456 */
2457 dmanow = (dmanow &
2458 ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) +
2459 SDHCI_DEFAULT_BOUNDARY_SIZE;
2460 host->data->bytes_xfered = dmanow - dmastart;
2461 DBG("%s: DMA base 0x%08x, transferred 0x%06x bytes,"
2462 " next 0x%08x\n",
2463 mmc_hostname(host->mmc), dmastart,
2464 host->data->bytes_xfered, dmanow);
2465 sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS);
2466 }
6ba736a1 2467
e538fbe8 2468 if (intmask & SDHCI_INT_DATA_END) {
7c89a3d9 2469 if (host->cmd == host->data_cmd) {
e538fbe8
PO		 2470 /*
2471 * Data managed to finish before the
2472 * command completed. Make sure we do
2473 * things in the proper order.
2474 */
2475 host->data_early = 1;
2476 } else {
2477 sdhci_finish_data(host);
2478 }
2479 }
d129bceb
PO		 2480 }
2481}
2482
7d12e780 2483static irqreturn_t sdhci_irq(int irq, void *dev_id)
d129bceb 2484{
781e989c 2485 irqreturn_t result = IRQ_NONE;
66fd8ad5 2486 struct sdhci_host *host = dev_id;
41005003 2487 u32 intmask, mask, unexpected = 0;
781e989c 2488 int max_loops = 16;
d129bceb
PO		 2489
2490 spin_lock(&host->lock);
2491
be138554 2492 if (host->runtime_suspended && !sdhci_sdio_irq_enabled(host)) {
66fd8ad5 2493 spin_unlock(&host->lock);
655bca76 2494 return IRQ_NONE;
66fd8ad5
AH		 2495 }
2496
4e4141a5 2497 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
62df67a5 2498 if (!intmask || intmask == 0xffffffff) {
d129bceb
PO		 2499 result = IRQ_NONE;
2500 goto out;
2501 }
2502
41005003
RK		 2503 do {
2504 /* Clear selected interrupts. */
2505 mask = intmask & (SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
2506 SDHCI_INT_BUS_POWER);
2507 sdhci_writel(host, mask, SDHCI_INT_STATUS);
d129bceb 2508
41005003
RK		 2509 DBG("*** %s got interrupt: 0x%08x\n",
2510 mmc_hostname(host->mmc), intmask);
d129bceb 2511
41005003
RK		 2512 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
2513 u32 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
2514 SDHCI_CARD_PRESENT;
d129bceb 2515
41005003
RK		 2516 /*
2517 * There is a observation on i.mx esdhc. INSERT
2518 * bit will be immediately set again when it gets
2519 * cleared, if a card is inserted. We have to mask
2520 * the irq to prevent interrupt storm which will
2521 * freeze the system. And the REMOVE gets the
2522 * same situation.
2523 *
2524 * More testing are needed here to ensure it works
2525 * for other platforms though.
2526 */
b537f94c
RK		 2527 host->ier &= ~(SDHCI_INT_CARD_INSERT |
2528 SDHCI_INT_CARD_REMOVE);
2529 host->ier |= present ? SDHCI_INT_CARD_REMOVE :
2530 SDHCI_INT_CARD_INSERT;
2531 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2532 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
41005003
RK		 2533
2534 sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT |
2535 SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS);
3560db8e
RK		 2536
2537 host->thread_isr |= intmask & (SDHCI_INT_CARD_INSERT |
2538 SDHCI_INT_CARD_REMOVE);
2539 result = IRQ_WAKE_THREAD;
41005003 2540 }
d129bceb 2541
41005003 2542 if (intmask & SDHCI_INT_CMD_MASK)
61541397
AH		 2543 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK,
2544 &intmask);
964f9ce2 2545
41005003
RK		 2546 if (intmask & SDHCI_INT_DATA_MASK)
2547 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
d129bceb 2548
41005003
RK		 2549 if (intmask & SDHCI_INT_BUS_POWER)
2550 pr_err("%s: Card is consuming too much power!\n",
2551 mmc_hostname(host->mmc));
3192a28f 2552
781e989c
RK		 2553 if (intmask & SDHCI_INT_CARD_INT) {
2554 sdhci_enable_sdio_irq_nolock(host, false);
2555 host->thread_isr |= SDHCI_INT_CARD_INT;
2556 result = IRQ_WAKE_THREAD;
2557 }
f75979b7 2558
41005003
RK		 2559 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE |
2560 SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
2561 SDHCI_INT_ERROR | SDHCI_INT_BUS_POWER |
2562 SDHCI_INT_CARD_INT);
f75979b7 2563
41005003
RK		 2564 if (intmask) {
2565 unexpected |= intmask;
2566 sdhci_writel(host, intmask, SDHCI_INT_STATUS);
2567 }
d129bceb 2568
781e989c
RK		 2569 if (result == IRQ_NONE)
2570 result = IRQ_HANDLED;
d129bceb 2571
41005003 2572 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
41005003 2573 } while (intmask && --max_loops);
d129bceb
PO		 2574out:
2575 spin_unlock(&host->lock);
2576
6379b237
AS		 2577 if (unexpected) {
2578 pr_err("%s: Unexpected interrupt 0x%08x.\n",
2579 mmc_hostname(host->mmc), unexpected);
2580 sdhci_dumpregs(host);
2581 }
f75979b7 2582
d129bceb
PO		 2583 return result;
2584}
2585
781e989c
RK		 2586static irqreturn_t sdhci_thread_irq(int irq, void *dev_id)
2587{
2588 struct sdhci_host *host = dev_id;
2589 unsigned long flags;
2590 u32 isr;
2591
2592 spin_lock_irqsave(&host->lock, flags);
2593 isr = host->thread_isr;
2594 host->thread_isr = 0;
2595 spin_unlock_irqrestore(&host->lock, flags);
2596
3560db8e 2597 if (isr & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
d3940f27
AH		 2598 struct mmc_host *mmc = host->mmc;
2599
2600 mmc->ops->card_event(mmc);
2601 mmc_detect_change(mmc, msecs_to_jiffies(200));
3560db8e
RK		 2602 }
2603
781e989c
RK		 2604 if (isr & SDHCI_INT_CARD_INT) {
2605 sdio_run_irqs(host->mmc);
2606
2607 spin_lock_irqsave(&host->lock, flags);
2608 if (host->flags & SDHCI_SDIO_IRQ_ENABLED)
2609 sdhci_enable_sdio_irq_nolock(host, true);
2610 spin_unlock_irqrestore(&host->lock, flags);
2611 }
2612
2613 return isr ? IRQ_HANDLED : IRQ_NONE;
2614}
2615
d129bceb
PO		 2616/*****************************************************************************\
2617 * *
2618 * Suspend/resume *
2619 * *
2620\*****************************************************************************/
2621
2622#ifdef CONFIG_PM
84d62605
LD		 2623/*
2624 * To enable wakeup events, the corresponding events have to be enabled in
2625 * the Interrupt Status Enable register too. See 'Table 1-6: Wakeup Signal
2626 * Table' in the SD Host Controller Standard Specification.
2627 * It is useless to restore SDHCI_INT_ENABLE state in
2628 * sdhci_disable_irq_wakeups() since it will be set by
2629 * sdhci_enable_card_detection() or sdhci_init().
2630 */
ad080d79
KL		 2631void sdhci_enable_irq_wakeups(struct sdhci_host *host)
2632{
2633 u8 val;
2634 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
2635 | SDHCI_WAKE_ON_INT;
84d62605
LD		 2636 u32 irq_val = SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE |
2637 SDHCI_INT_CARD_INT;
ad080d79
KL		 2638
2639 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2640 val |= mask ;
2641 /* Avoid fake wake up */
84d62605 2642 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) {
ad080d79 2643 val &= ~(SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE);
84d62605
LD		 2644 irq_val &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE);
2645 }
ad080d79 2646 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
84d62605 2647 sdhci_writel(host, irq_val, SDHCI_INT_ENABLE);
ad080d79
KL		 2648}
2649EXPORT_SYMBOL_GPL(sdhci_enable_irq_wakeups);
2650
0b10f478 2651static void sdhci_disable_irq_wakeups(struct sdhci_host *host)
ad080d79
KL		 2652{
2653 u8 val;
2654 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
2655 | SDHCI_WAKE_ON_INT;
2656
2657 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2658 val &= ~mask;
2659 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2660}
d129bceb 2661
29495aa0 2662int sdhci_suspend_host(struct sdhci_host *host)
d129bceb 2663{
7260cf5e
AV		 2664 sdhci_disable_card_detection(host);
2665
66c39dfc
AH		 2666 mmc_retune_timer_stop(host->mmc);
2667 mmc_retune_needed(host->mmc);
cf2b5eea 2668
ad080d79 2669 if (!device_may_wakeup(mmc_dev(host->mmc))) {
b537f94c
RK		 2670 host->ier = 0;
2671 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
2672 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
ad080d79
KL		 2673 free_irq(host->irq, host);
2674 } else {
2675 sdhci_enable_irq_wakeups(host);
2676 enable_irq_wake(host->irq);
2677 }
4ee14ec6 2678 return 0;
d129bceb
PO		 2679}
2680
b8c86fc5 2681EXPORT_SYMBOL_GPL(sdhci_suspend_host);
d129bceb 2682
b8c86fc5
PO		 2683int sdhci_resume_host(struct sdhci_host *host)
2684{
d3940f27 2685 struct mmc_host *mmc = host->mmc;
4ee14ec6 2686 int ret = 0;
d129bceb 2687
a13abc7b 2688 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
b8c86fc5
PO		 2689 if (host->ops->enable_dma)
2690 host->ops->enable_dma(host);
2691 }
d129bceb 2692
6308d290
AH		 2693 if ((host->mmc->pm_flags & MMC_PM_KEEP_POWER) &&
2694 (host->quirks2 & SDHCI_QUIRK2_HOST_OFF_CARD_ON)) {
2695 /* Card keeps power but host controller does not */
2696 sdhci_init(host, 0);
2697 host->pwr = 0;
2698 host->clock = 0;
d3940f27 2699 mmc->ops->set_ios(mmc, &mmc->ios);
6308d290
AH		 2700 } else {
2701 sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER));
2702 mmiowb();
2703 }
b8c86fc5 2704
14a7b416
HC		 2705 if (!device_may_wakeup(mmc_dev(host->mmc))) {
2706 ret = request_threaded_irq(host->irq, sdhci_irq,
2707 sdhci_thread_irq, IRQF_SHARED,
2708 mmc_hostname(host->mmc), host);
2709 if (ret)
2710 return ret;
2711 } else {
2712 sdhci_disable_irq_wakeups(host);
2713 disable_irq_wake(host->irq);
2714 }
2715
7260cf5e
AV		 2716 sdhci_enable_card_detection(host);
2717
2f4cbb3d 2718 return ret;
d129bceb
PO		 2719}
2720
b8c86fc5 2721EXPORT_SYMBOL_GPL(sdhci_resume_host);
66fd8ad5 2722
66fd8ad5
AH		 2723int sdhci_runtime_suspend_host(struct sdhci_host *host)
2724{
2725 unsigned long flags;
66fd8ad5 2726
66c39dfc
AH		 2727 mmc_retune_timer_stop(host->mmc);
2728 mmc_retune_needed(host->mmc);
66fd8ad5
AH		 2729
2730 spin_lock_irqsave(&host->lock, flags);
b537f94c
RK		 2731 host->ier &= SDHCI_INT_CARD_INT;
2732 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2733 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
66fd8ad5
AH		 2734 spin_unlock_irqrestore(&host->lock, flags);
2735
781e989c 2736 synchronize_hardirq(host->irq);
66fd8ad5
AH		 2737
2738 spin_lock_irqsave(&host->lock, flags);
2739 host->runtime_suspended = true;
2740 spin_unlock_irqrestore(&host->lock, flags);
2741
8a125bad 2742 return 0;
66fd8ad5
AH		 2743}
2744EXPORT_SYMBOL_GPL(sdhci_runtime_suspend_host);
2745
2746int sdhci_runtime_resume_host(struct sdhci_host *host)
2747{
d3940f27 2748 struct mmc_host *mmc = host->mmc;
66fd8ad5 2749 unsigned long flags;
8a125bad 2750 int host_flags = host->flags;
66fd8ad5
AH		 2751
2752 if (host_flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2753 if (host->ops->enable_dma)
2754 host->ops->enable_dma(host);
2755 }
2756
2757 sdhci_init(host, 0);
2758
2759 /* Force clock and power re-program */
2760 host->pwr = 0;
2761 host->clock = 0;
d3940f27
AH		 2762 mmc->ops->start_signal_voltage_switch(mmc, &mmc->ios);
2763 mmc->ops->set_ios(mmc, &mmc->ios);
66fd8ad5 2764
52983382
KL		 2765 if ((host_flags & SDHCI_PV_ENABLED) &&
2766 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN)) {
2767 spin_lock_irqsave(&host->lock, flags);
2768 sdhci_enable_preset_value(host, true);
2769 spin_unlock_irqrestore(&host->lock, flags);
2770 }
66fd8ad5 2771
66fd8ad5
AH		 2772 spin_lock_irqsave(&host->lock, flags);
2773
2774 host->runtime_suspended = false;
2775
2776 /* Enable SDIO IRQ */
ef104333 2777 if (host->flags & SDHCI_SDIO_IRQ_ENABLED)
66fd8ad5
AH		 2778 sdhci_enable_sdio_irq_nolock(host, true);
2779
2780 /* Enable Card Detection */
2781 sdhci_enable_card_detection(host);
2782
2783 spin_unlock_irqrestore(&host->lock, flags);
2784
8a125bad 2785 return 0;
66fd8ad5
AH		 2786}
2787EXPORT_SYMBOL_GPL(sdhci_runtime_resume_host);
2788
162d6f98 2789#endif /* CONFIG_PM */
66fd8ad5 2790
d129bceb
PO		 2791/*****************************************************************************\
2792 * *
b8c86fc5 2793 * Device allocation/registration *
d129bceb
PO		 2794 * *
2795\*****************************************************************************/
2796
b8c86fc5
PO		 2797struct sdhci_host *sdhci_alloc_host(struct device *dev,
2798 size_t priv_size)
d129bceb 2799{
d129bceb
PO		 2800 struct mmc_host *mmc;
2801 struct sdhci_host *host;
2802
b8c86fc5 2803 WARN_ON(dev == NULL);
d129bceb 2804
b8c86fc5 2805 mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev);
d129bceb 2806 if (!mmc)
b8c86fc5 2807 return ERR_PTR(-ENOMEM);
d129bceb
PO		 2808
2809 host = mmc_priv(mmc);
2810 host->mmc = mmc;
bf60e592
AH		 2811 host->mmc_host_ops = sdhci_ops;
2812 mmc->ops = &host->mmc_host_ops;
d129bceb 2813
8cb851a4
AH		 2814 host->flags = SDHCI_SIGNALING_330;
2815
b8c86fc5
PO		 2816 return host;
2817}
8a4da143 2818
b8c86fc5 2819EXPORT_SYMBOL_GPL(sdhci_alloc_host);
d129bceb 2820
7b91369b
AC		 2821static int sdhci_set_dma_mask(struct sdhci_host *host)
2822{
2823 struct mmc_host *mmc = host->mmc;
2824 struct device *dev = mmc_dev(mmc);
2825 int ret = -EINVAL;
2826
2827 if (host->quirks2 & SDHCI_QUIRK2_BROKEN_64_BIT_DMA)
2828 host->flags &= ~SDHCI_USE_64_BIT_DMA;
2829
2830 /* Try 64-bit mask if hardware is capable of it */
2831 if (host->flags & SDHCI_USE_64_BIT_DMA) {
2832 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64));
2833 if (ret) {
2834 pr_warn("%s: Failed to set 64-bit DMA mask.\n",
2835 mmc_hostname(mmc));
2836 host->flags &= ~SDHCI_USE_64_BIT_DMA;
2837 }
2838 }
2839
2840 /* 32-bit mask as default & fallback */
2841 if (ret) {
2842 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32));
2843 if (ret)
2844 pr_warn("%s: Failed to set 32-bit DMA mask.\n",
2845 mmc_hostname(mmc));
2846 }
2847
2848 return ret;
2849}
2850
6132a3bf
AH		 2851void __sdhci_read_caps(struct sdhci_host *host, u16 *ver, u32 *caps, u32 *caps1)
2852{
2853 u16 v;
2854
2855 if (host->read_caps)
2856 return;
2857
2858 host->read_caps = true;
2859
2860 if (debug_quirks)
2861 host->quirks = debug_quirks;
2862
2863 if (debug_quirks2)
2864 host->quirks2 = debug_quirks2;
2865
2866 sdhci_do_reset(host, SDHCI_RESET_ALL);
2867
2868 v = ver ? *ver : sdhci_readw(host, SDHCI_HOST_VERSION);
2869 host->version = (v & SDHCI_SPEC_VER_MASK) >> SDHCI_SPEC_VER_SHIFT;
2870
2871 if (host->quirks & SDHCI_QUIRK_MISSING_CAPS)
2872 return;
2873
2874 host->caps = caps ? *caps : sdhci_readl(host, SDHCI_CAPABILITIES);
2875
2876 if (host->version < SDHCI_SPEC_300)
2877 return;
2878
2879 host->caps1 = caps1 ? *caps1 : sdhci_readl(host, SDHCI_CAPABILITIES_1);
2880}
2881EXPORT_SYMBOL_GPL(__sdhci_read_caps);
2882
52f5336d 2883int sdhci_setup_host(struct sdhci_host *host)
b8c86fc5
PO		 2884{
2885 struct mmc_host *mmc;
f2119df6
AN		 2886 u32 max_current_caps;
2887 unsigned int ocr_avail;
f5fa92e5 2888 unsigned int override_timeout_clk;
59241757 2889 u32 max_clk;
b8c86fc5 2890 int ret;
d129bceb 2891
b8c86fc5
PO		 2892 WARN_ON(host == NULL);
2893 if (host == NULL)
2894 return -EINVAL;
d129bceb 2895
b8c86fc5 2896 mmc = host->mmc;
d129bceb 2897
6132a3bf 2898 sdhci_read_caps(host);
d129bceb 2899
f5fa92e5
AH		 2900 override_timeout_clk = host->timeout_clk;
2901
85105c53 2902 if (host->version > SDHCI_SPEC_300) {
2e4456f0
MV		 2903 pr_err("%s: Unknown controller version (%d). You may experience problems.\n",
2904 mmc_hostname(mmc), host->version);
4a965505
PO		 2905 }
2906
b8c86fc5 2907 if (host->quirks & SDHCI_QUIRK_FORCE_DMA)
a13abc7b 2908 host->flags |= SDHCI_USE_SDMA;
28da3589 2909 else if (!(host->caps & SDHCI_CAN_DO_SDMA))
a13abc7b 2910 DBG("Controller doesn't have SDMA capability\n");
67435274 2911 else
a13abc7b 2912 host->flags |= SDHCI_USE_SDMA;
d129bceb 2913
b8c86fc5 2914 if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
a13abc7b 2915 (host->flags & SDHCI_USE_SDMA)) {
cee687ce 2916 DBG("Disabling DMA as it is marked broken\n");
a13abc7b 2917 host->flags &= ~SDHCI_USE_SDMA;
7c168e3d
FT		 2918 }
2919
f2119df6 2920 if ((host->version >= SDHCI_SPEC_200) &&
28da3589 2921 (host->caps & SDHCI_CAN_DO_ADMA2))
a13abc7b 2922 host->flags |= SDHCI_USE_ADMA;
2134a922
PO		 2923
2924 if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) &&
2925 (host->flags & SDHCI_USE_ADMA)) {
2926 DBG("Disabling ADMA as it is marked broken\n");
2927 host->flags &= ~SDHCI_USE_ADMA;
2928 }
2929
e57a5f61
AH		 2930 /*
2931 * It is assumed that a 64-bit capable device has set a 64-bit DMA mask
2932 * and *must* do 64-bit DMA. A driver has the opportunity to change
2933 * that during the first call to ->enable_dma(). Similarly
2934 * SDHCI_QUIRK2_BROKEN_64_BIT_DMA must be left to the drivers to
2935 * implement.
2936 */
28da3589 2937 if (host->caps & SDHCI_CAN_64BIT)
e57a5f61
AH		 2938 host->flags |= SDHCI_USE_64_BIT_DMA;
2939
a13abc7b 2940 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
7b91369b
AC		 2941 ret = sdhci_set_dma_mask(host);
2942
2943 if (!ret && host->ops->enable_dma)
2944 ret = host->ops->enable_dma(host);
2945
2946 if (ret) {
2947 pr_warn("%s: No suitable DMA available - falling back to PIO\n",
2948 mmc_hostname(mmc));
2949 host->flags &= ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
2950
2951 ret = 0;
d129bceb
PO		 2952 }
2953 }
2954
e57a5f61
AH		 2955 /* SDMA does not support 64-bit DMA */
2956 if (host->flags & SDHCI_USE_64_BIT_DMA)
2957 host->flags &= ~SDHCI_USE_SDMA;
2958
2134a922 2959 if (host->flags & SDHCI_USE_ADMA) {
e66e61cb
RK		 2960 dma_addr_t dma;
2961 void *buf;
2962
2134a922 2963 /*
76fe379a
AH		 2964 * The DMA descriptor table size is calculated as the maximum
2965 * number of segments times 2, to allow for an alignment
2966 * descriptor for each segment, plus 1 for a nop end descriptor,
2967 * all multipled by the descriptor size.
2134a922 2968 */
e57a5f61
AH		 2969 if (host->flags & SDHCI_USE_64_BIT_DMA) {
2970 host->adma_table_sz = (SDHCI_MAX_SEGS * 2 + 1) *
2971 SDHCI_ADMA2_64_DESC_SZ;
e57a5f61 2972 host->desc_sz = SDHCI_ADMA2_64_DESC_SZ;
e57a5f61
AH		 2973 } else {
2974 host->adma_table_sz = (SDHCI_MAX_SEGS * 2 + 1) *
2975 SDHCI_ADMA2_32_DESC_SZ;
e57a5f61 2976 host->desc_sz = SDHCI_ADMA2_32_DESC_SZ;
e57a5f61 2977 }
e66e61cb 2978
04a5ae6f 2979 host->align_buffer_sz = SDHCI_MAX_SEGS * SDHCI_ADMA2_ALIGN;
e66e61cb
RK		 2980 buf = dma_alloc_coherent(mmc_dev(mmc), host->align_buffer_sz +
2981 host->adma_table_sz, &dma, GFP_KERNEL);
2982 if (!buf) {
6606110d 2983 pr_warn("%s: Unable to allocate ADMA buffers - falling back to standard DMA\n",
2134a922
PO		 2984 mmc_hostname(mmc));
2985 host->flags &= ~SDHCI_USE_ADMA;
e66e61cb
RK		 2986 } else if ((dma + host->align_buffer_sz) &
2987 (SDHCI_ADMA2_DESC_ALIGN - 1)) {
6606110d
JP		 2988 pr_warn("%s: unable to allocate aligned ADMA descriptor\n",
2989 mmc_hostname(mmc));
d1e49f77 2990 host->flags &= ~SDHCI_USE_ADMA;
e66e61cb
RK		 2991 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
2992 host->adma_table_sz, buf, dma);
2993 } else {
2994 host->align_buffer = buf;
2995 host->align_addr = dma;
edd63fcc 2996
e66e61cb
RK		 2997 host->adma_table = buf + host->align_buffer_sz;
2998 host->adma_addr = dma + host->align_buffer_sz;
2999 }
2134a922
PO		 3000 }
3001
7659150c
PO		 3002 /*
3003 * If we use DMA, then it's up to the caller to set the DMA
3004 * mask, but PIO does not need the hw shim so we set a new
3005 * mask here in that case.
3006 */
a13abc7b 3007 if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) {
7659150c 3008 host->dma_mask = DMA_BIT_MASK(64);
4e743f1f 3009 mmc_dev(mmc)->dma_mask = &host->dma_mask;
7659150c 3010 }
d129bceb 3011
c4687d5f 3012 if (host->version >= SDHCI_SPEC_300)
28da3589 3013 host->max_clk = (host->caps & SDHCI_CLOCK_V3_BASE_MASK)
c4687d5f
ZG		 3014 >> SDHCI_CLOCK_BASE_SHIFT;
3015 else
28da3589 3016 host->max_clk = (host->caps & SDHCI_CLOCK_BASE_MASK)
c4687d5f
ZG		 3017 >> SDHCI_CLOCK_BASE_SHIFT;
3018
4240ff0a 3019 host->max_clk *= 1000000;
f27f47ef
AV		 3020 if (host->max_clk == 0 || host->quirks &
3021 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) {
4240ff0a 3022 if (!host->ops->get_max_clock) {
2e4456f0
MV		 3023 pr_err("%s: Hardware doesn't specify base clock frequency.\n",
3024 mmc_hostname(mmc));
eb5c20de
AH		 3025 ret = -ENODEV;
3026 goto undma;
4240ff0a
BD		 3027 }
3028 host->max_clk = host->ops->get_max_clock(host);
8ef1a143 3029 }
d129bceb 3030
c3ed3877
AN		 3031 /*
3032 * In case of Host Controller v3.00, find out whether clock
3033 * multiplier is supported.
3034 */
28da3589 3035 host->clk_mul = (host->caps1 & SDHCI_CLOCK_MUL_MASK) >>
c3ed3877
AN		 3036 SDHCI_CLOCK_MUL_SHIFT;
3037
3038 /*
3039 * In case the value in Clock Multiplier is 0, then programmable
3040 * clock mode is not supported, otherwise the actual clock
3041 * multiplier is one more than the value of Clock Multiplier
3042 * in the Capabilities Register.
3043 */
3044 if (host->clk_mul)
3045 host->clk_mul += 1;
3046
d129bceb
PO		 3047 /*
3048 * Set host parameters.
3049 */
59241757
DA		 3050 max_clk = host->max_clk;
3051
ce5f036b 3052 if (host->ops->get_min_clock)
a9e58f25 3053 mmc->f_min = host->ops->get_min_clock(host);
c3ed3877
AN		 3054 else if (host->version >= SDHCI_SPEC_300) {
3055 if (host->clk_mul) {
3056 mmc->f_min = (host->max_clk * host->clk_mul) / 1024;
59241757 3057 max_clk = host->max_clk * host->clk_mul;
c3ed3877
AN		 3058 } else
3059 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300;
3060 } else
0397526d 3061 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200;
15ec4461 3062
d310ae49 3063 if (!mmc->f_max || mmc->f_max > max_clk)
59241757
DA		 3064 mmc->f_max = max_clk;
3065
28aab053 3066 if (!(host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) {
28da3589 3067 host->timeout_clk = (host->caps & SDHCI_TIMEOUT_CLK_MASK) >>
28aab053
AD		 3068 SDHCI_TIMEOUT_CLK_SHIFT;
3069 if (host->timeout_clk == 0) {
3070 if (host->ops->get_timeout_clock) {
3071 host->timeout_clk =
3072 host->ops->get_timeout_clock(host);
3073 } else {
3074 pr_err("%s: Hardware doesn't specify timeout clock frequency.\n",
3075 mmc_hostname(mmc));
eb5c20de
AH		 3076 ret = -ENODEV;
3077 goto undma;
28aab053 3078 }
272308ca 3079 }
272308ca 3080
28da3589 3081 if (host->caps & SDHCI_TIMEOUT_CLK_UNIT)
28aab053 3082 host->timeout_clk *= 1000;
272308ca 3083
99513624
AH		 3084 if (override_timeout_clk)
3085 host->timeout_clk = override_timeout_clk;
3086
28aab053 3087 mmc->max_busy_timeout = host->ops->get_max_timeout_count ?
a6ff5aeb 3088 host->ops->get_max_timeout_count(host) : 1 << 27;
28aab053
AD		 3089 mmc->max_busy_timeout /= host->timeout_clk;
3090 }
58d1246d 3091
e89d456f 3092 mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_ERASE | MMC_CAP_CMD23;
781e989c 3093 mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD;
e89d456f
AW		 3094
3095 if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12)
3096 host->flags |= SDHCI_AUTO_CMD12;
5fe23c7f 3097
8edf6371 3098 /* Auto-CMD23 stuff only works in ADMA or PIO. */
4f3d3e9b 3099 if ((host->version >= SDHCI_SPEC_300) &&
8edf6371 3100 ((host->flags & SDHCI_USE_ADMA) ||
3bfa6f03
SB		 3101 !(host->flags & SDHCI_USE_SDMA)) &&
3102 !(host->quirks2 & SDHCI_QUIRK2_ACMD23_BROKEN)) {
8edf6371
AW		 3103 host->flags |= SDHCI_AUTO_CMD23;
3104 DBG("%s: Auto-CMD23 available\n", mmc_hostname(mmc));
3105 } else {
3106 DBG("%s: Auto-CMD23 unavailable\n", mmc_hostname(mmc));
3107 }
3108
15ec4461
PR		 3109 /*
3110 * A controller may support 8-bit width, but the board itself
3111 * might not have the pins brought out. Boards that support
3112 * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in
3113 * their platform code before calling sdhci_add_host(), and we
3114 * won't assume 8-bit width for hosts without that CAP.
3115 */
5fe23c7f 3116 if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA))
15ec4461 3117 mmc->caps |= MMC_CAP_4_BIT_DATA;
d129bceb 3118
63ef5d8c
JH		 3119 if (host->quirks2 & SDHCI_QUIRK2_HOST_NO_CMD23)
3120 mmc->caps &= ~MMC_CAP_CMD23;
3121
28da3589 3122 if (host->caps & SDHCI_CAN_DO_HISPD)
a29e7e18 3123 mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
cd9277c0 3124
176d1ed4 3125 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) &&
860951c5 3126 mmc_card_is_removable(mmc) &&
287980e4 3127 mmc_gpio_get_cd(host->mmc) < 0)
68d1fb7e
AV		 3128 mmc->caps |= MMC_CAP_NEEDS_POLL;
3129
3a48edc4 3130 /* If there are external regulators, get them */
eb5c20de
AH		 3131 ret = mmc_regulator_get_supply(mmc);
3132 if (ret == -EPROBE_DEFER)
3133 goto undma;
3a48edc4 3134
6231f3de 3135 /* If vqmmc regulator and no 1.8V signalling, then there's no UHS */
3a48edc4
TK		 3136 if (!IS_ERR(mmc->supply.vqmmc)) {
3137 ret = regulator_enable(mmc->supply.vqmmc);
3138 if (!regulator_is_supported_voltage(mmc->supply.vqmmc, 1700000,
3139 1950000))
28da3589
AH		 3140 host->caps1 &= ~(SDHCI_SUPPORT_SDR104 |
3141 SDHCI_SUPPORT_SDR50 |
3142 SDHCI_SUPPORT_DDR50);
a3361aba
CB		 3143 if (ret) {
3144 pr_warn("%s: Failed to enable vqmmc regulator: %d\n",
3145 mmc_hostname(mmc), ret);
4bb74313 3146 mmc->supply.vqmmc = ERR_PTR(-EINVAL);
a3361aba 3147 }
8363c374 3148 }
6231f3de 3149
28da3589
AH		 3150 if (host->quirks2 & SDHCI_QUIRK2_NO_1_8_V) {
3151 host->caps1 &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
3152 SDHCI_SUPPORT_DDR50);
3153 }
6a66180a 3154
4188bba0 3155 /* Any UHS-I mode in caps implies SDR12 and SDR25 support. */
28da3589
AH		 3156 if (host->caps1 & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
3157 SDHCI_SUPPORT_DDR50))
f2119df6
AN		 3158 mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;
3159
3160 /* SDR104 supports also implies SDR50 support */
28da3589 3161 if (host->caps1 & SDHCI_SUPPORT_SDR104) {
f2119df6 3162 mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50;
156e14b1
GC		 3163 /* SD3.0: SDR104 is supported so (for eMMC) the caps2
3164 * field can be promoted to support HS200.
3165 */
549c0b18 3166 if (!(host->quirks2 & SDHCI_QUIRK2_BROKEN_HS200))
13868bf2 3167 mmc->caps2 |= MMC_CAP2_HS200;
28da3589 3168 } else if (host->caps1 & SDHCI_SUPPORT_SDR50) {
f2119df6 3169 mmc->caps |= MMC_CAP_UHS_SDR50;
28da3589 3170 }
f2119df6 3171
e9fb05d5 3172 if (host->quirks2 & SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 &&
28da3589 3173 (host->caps1 & SDHCI_SUPPORT_HS400))
e9fb05d5
AH		 3174 mmc->caps2 |= MMC_CAP2_HS400;
3175
549c0b18
AH		 3176 if ((mmc->caps2 & MMC_CAP2_HSX00_1_2V) &&
3177 (IS_ERR(mmc->supply.vqmmc) ||
3178 !regulator_is_supported_voltage(mmc->supply.vqmmc, 1100000,
3179 1300000)))
3180 mmc->caps2 &= ~MMC_CAP2_HSX00_1_2V;
3181
28da3589
AH		 3182 if ((host->caps1 & SDHCI_SUPPORT_DDR50) &&
3183 !(host->quirks2 & SDHCI_QUIRK2_BROKEN_DDR50))
f2119df6
AN		 3184 mmc->caps |= MMC_CAP_UHS_DDR50;
3185
069c9f14 3186 /* Does the host need tuning for SDR50? */
28da3589 3187 if (host->caps1 & SDHCI_USE_SDR50_TUNING)
b513ea25
AN		 3188 host->flags |= SDHCI_SDR50_NEEDS_TUNING;
3189
d6d50a15 3190 /* Driver Type(s) (A, C, D) supported by the host */
28da3589 3191 if (host->caps1 & SDHCI_DRIVER_TYPE_A)
d6d50a15 3192 mmc->caps |= MMC_CAP_DRIVER_TYPE_A;
28da3589 3193 if (host->caps1 & SDHCI_DRIVER_TYPE_C)
d6d50a15 3194 mmc->caps |= MMC_CAP_DRIVER_TYPE_C;
28da3589 3195 if (host->caps1 & SDHCI_DRIVER_TYPE_D)
d6d50a15
AN		 3196 mmc->caps |= MMC_CAP_DRIVER_TYPE_D;
3197
cf2b5eea 3198 /* Initial value for re-tuning timer count */
28da3589
AH		 3199 host->tuning_count = (host->caps1 & SDHCI_RETUNING_TIMER_COUNT_MASK) >>
3200 SDHCI_RETUNING_TIMER_COUNT_SHIFT;
cf2b5eea
AN		 3201
3202 /*
3203 * In case Re-tuning Timer is not disabled, the actual value of
3204 * re-tuning timer will be 2 ^ (n - 1).
3205 */
3206 if (host->tuning_count)
3207 host->tuning_count = 1 << (host->tuning_count - 1);
3208
3209 /* Re-tuning mode supported by the Host Controller */
28da3589 3210 host->tuning_mode = (host->caps1 & SDHCI_RETUNING_MODE_MASK) >>
cf2b5eea
AN		 3211 SDHCI_RETUNING_MODE_SHIFT;
3212
8f230f45 3213 ocr_avail = 0;
bad37e1a 3214
f2119df6
AN		 3215 /*
3216 * According to SD Host Controller spec v3.00, if the Host System
3217 * can afford more than 150mA, Host Driver should set XPC to 1. Also
3218 * the value is meaningful only if Voltage Support in the Capabilities
3219 * register is set. The actual current value is 4 times the register
3220 * value.
3221 */
3222 max_current_caps = sdhci_readl(host, SDHCI_MAX_CURRENT);
3a48edc4 3223 if (!max_current_caps && !IS_ERR(mmc->supply.vmmc)) {
ae906037 3224 int curr = regulator_get_current_limit(mmc->supply.vmmc);
bad37e1a
PR		 3225 if (curr > 0) {
3226
3227 /* convert to SDHCI_MAX_CURRENT format */
3228 curr = curr/1000; /* convert to mA */
3229 curr = curr/SDHCI_MAX_CURRENT_MULTIPLIER;
3230
3231 curr = min_t(u32, curr, SDHCI_MAX_CURRENT_LIMIT);
3232 max_current_caps =
3233 (curr << SDHCI_MAX_CURRENT_330_SHIFT) |
3234 (curr << SDHCI_MAX_CURRENT_300_SHIFT) |
3235 (curr << SDHCI_MAX_CURRENT_180_SHIFT);
3236 }
3237 }
f2119df6 3238
28da3589 3239 if (host->caps & SDHCI_CAN_VDD_330) {
8f230f45 3240 ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34;
f2119df6 3241
55c4665e 3242 mmc->max_current_330 = ((max_current_caps &
f2119df6
AN		 3243 SDHCI_MAX_CURRENT_330_MASK) >>
3244 SDHCI_MAX_CURRENT_330_SHIFT) *
3245 SDHCI_MAX_CURRENT_MULTIPLIER;
f2119df6 3246 }
28da3589 3247 if (host->caps & SDHCI_CAN_VDD_300) {
8f230f45 3248 ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31;
f2119df6 3249
55c4665e 3250 mmc->max_current_300 = ((max_current_caps &
f2119df6
AN		 3251 SDHCI_MAX_CURRENT_300_MASK) >>
3252 SDHCI_MAX_CURRENT_300_SHIFT) *
3253 SDHCI_MAX_CURRENT_MULTIPLIER;
f2119df6 3254 }
28da3589 3255 if (host->caps & SDHCI_CAN_VDD_180) {
8f230f45
TI		 3256 ocr_avail |= MMC_VDD_165_195;
3257
55c4665e 3258 mmc->max_current_180 = ((max_current_caps &
f2119df6
AN		 3259 SDHCI_MAX_CURRENT_180_MASK) >>
3260 SDHCI_MAX_CURRENT_180_SHIFT) *
3261 SDHCI_MAX_CURRENT_MULTIPLIER;
f2119df6
AN		 3262 }
3263
5fd26c7e
UH		 3264 /* If OCR set by host, use it instead. */
3265 if (host->ocr_mask)
3266 ocr_avail = host->ocr_mask;
3267
3268 /* If OCR set by external regulators, give it highest prio. */
3a48edc4 3269 if (mmc->ocr_avail)
52221610 3270 ocr_avail = mmc->ocr_avail;
3a48edc4 3271
8f230f45
TI		 3272 mmc->ocr_avail = ocr_avail;
3273 mmc->ocr_avail_sdio = ocr_avail;
3274 if (host->ocr_avail_sdio)
3275 mmc->ocr_avail_sdio &= host->ocr_avail_sdio;
3276 mmc->ocr_avail_sd = ocr_avail;
3277 if (host->ocr_avail_sd)
3278 mmc->ocr_avail_sd &= host->ocr_avail_sd;
3279 else /* normal SD controllers don't support 1.8V */
3280 mmc->ocr_avail_sd &= ~MMC_VDD_165_195;
3281 mmc->ocr_avail_mmc = ocr_avail;
3282 if (host->ocr_avail_mmc)
3283 mmc->ocr_avail_mmc &= host->ocr_avail_mmc;
146ad66e
PO		 3284
3285 if (mmc->ocr_avail == 0) {
2e4456f0
MV		 3286 pr_err("%s: Hardware doesn't report any support voltages.\n",
3287 mmc_hostname(mmc));
eb5c20de
AH		 3288 ret = -ENODEV;
3289 goto unreg;
146ad66e
PO		 3290 }
3291
8cb851a4
AH		 3292 if ((mmc->caps & (MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 |
3293 MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_SDR104 |
3294 MMC_CAP_UHS_DDR50 | MMC_CAP_1_8V_DDR)) ||
3295 (mmc->caps2 & (MMC_CAP2_HS200_1_8V_SDR | MMC_CAP2_HS400_1_8V)))
3296 host->flags |= SDHCI_SIGNALING_180;
3297
3298 if (mmc->caps2 & MMC_CAP2_HSX00_1_2V)
3299 host->flags |= SDHCI_SIGNALING_120;
3300
d129bceb
PO		 3301 spin_lock_init(&host->lock);
3302
3303 /*
2134a922
PO		 3304 * Maximum number of segments. Depends on if the hardware
3305 * can do scatter/gather or not.
d129bceb 3306 */
2134a922 3307 if (host->flags & SDHCI_USE_ADMA)
4fb213f8 3308 mmc->max_segs = SDHCI_MAX_SEGS;
a13abc7b 3309 else if (host->flags & SDHCI_USE_SDMA)
a36274e0 3310 mmc->max_segs = 1;
2134a922 3311 else /* PIO */
4fb213f8 3312 mmc->max_segs = SDHCI_MAX_SEGS;
d129bceb
PO		 3313
3314 /*
ac00531d
AH		 3315 * Maximum number of sectors in one transfer. Limited by SDMA boundary
3316 * size (512KiB). Note some tuning modes impose a 4MiB limit, but this
3317 * is less anyway.
d129bceb 3318 */
55db890a 3319 mmc->max_req_size = 524288;
d129bceb
PO		 3320
3321 /*
3322 * Maximum segment size. Could be one segment with the maximum number
2134a922
PO		 3323 * of bytes. When doing hardware scatter/gather, each entry cannot
3324 * be larger than 64 KiB though.
d129bceb 3325 */
30652aa3
OJ		 3326 if (host->flags & SDHCI_USE_ADMA) {
3327 if (host->quirks & SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC)
3328 mmc->max_seg_size = 65535;
3329 else
3330 mmc->max_seg_size = 65536;
3331 } else {
2134a922 3332 mmc->max_seg_size = mmc->max_req_size;
30652aa3 3333 }
d129bceb 3334
fe4a3c7a
PO		 3335 /*
3336 * Maximum block size. This varies from controller to controller and
3337 * is specified in the capabilities register.
3338 */
0633f654
AV		 3339 if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) {
3340 mmc->max_blk_size = 2;
3341 } else {
28da3589 3342 mmc->max_blk_size = (host->caps & SDHCI_MAX_BLOCK_MASK) >>
0633f654
AV		 3343 SDHCI_MAX_BLOCK_SHIFT;
3344 if (mmc->max_blk_size >= 3) {
6606110d
JP		 3345 pr_warn("%s: Invalid maximum block size, assuming 512 bytes\n",
3346 mmc_hostname(mmc));
0633f654
AV		 3347 mmc->max_blk_size = 0;
3348 }
3349 }
3350
3351 mmc->max_blk_size = 512 << mmc->max_blk_size;
fe4a3c7a 3352
55db890a
PO		 3353 /*
3354 * Maximum block count.
3355 */
1388eefd 3356 mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
55db890a 3357
52f5336d
AH		 3358 return 0;
3359
3360unreg:
3361 if (!IS_ERR(mmc->supply.vqmmc))
3362 regulator_disable(mmc->supply.vqmmc);
3363undma:
3364 if (host->align_buffer)
3365 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
3366 host->adma_table_sz, host->align_buffer,
3367 host->align_addr);
3368 host->adma_table = NULL;
3369 host->align_buffer = NULL;
3370
3371 return ret;
3372}
3373EXPORT_SYMBOL_GPL(sdhci_setup_host);
3374
3375int __sdhci_add_host(struct sdhci_host *host)
3376{
3377 struct mmc_host *mmc = host->mmc;
3378 int ret;
3379
d129bceb
PO		 3380 /*
3381 * Init tasklets.
3382 */
d129bceb
PO		 3383 tasklet_init(&host->finish_tasklet,
3384 sdhci_tasklet_finish, (unsigned long)host);
3385
e4cad1b5 3386 setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host);
d129bceb 3387
250fb7b4 3388 init_waitqueue_head(&host->buf_ready_int);
b513ea25 3389
2af502ca
SG		 3390 sdhci_init(host, 0);
3391
781e989c
RK		 3392 ret = request_threaded_irq(host->irq, sdhci_irq, sdhci_thread_irq,
3393 IRQF_SHARED, mmc_hostname(mmc), host);
0fc81ee3
MB		 3394 if (ret) {
3395 pr_err("%s: Failed to request IRQ %d: %d\n",
3396 mmc_hostname(mmc), host->irq, ret);
8ef1a143 3397 goto untasklet;
0fc81ee3 3398 }
d129bceb 3399
d129bceb
PO		 3400#ifdef CONFIG_MMC_DEBUG
3401 sdhci_dumpregs(host);
3402#endif
3403
061d17a6 3404 ret = sdhci_led_register(host);
0fc81ee3
MB		 3405 if (ret) {
3406 pr_err("%s: Failed to register LED device: %d\n",
3407 mmc_hostname(mmc), ret);
eb5c20de 3408 goto unirq;
0fc81ee3 3409 }
2f730fec 3410
5f25a66f
PO		 3411 mmiowb();
3412
eb5c20de
AH		 3413 ret = mmc_add_host(mmc);
3414 if (ret)
3415 goto unled;
d129bceb 3416
a3c76eb9 3417 pr_info("%s: SDHCI controller on %s [%s] using %s\n",
d1b26863 3418 mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)),
e57a5f61
AH		 3419 (host->flags & SDHCI_USE_ADMA) ?
3420 (host->flags & SDHCI_USE_64_BIT_DMA) ? "ADMA 64-bit" : "ADMA" :
a13abc7b 3421 (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO");
d129bceb 3422
7260cf5e
AV		 3423 sdhci_enable_card_detection(host);
3424
d129bceb
PO		 3425 return 0;
3426
eb5c20de 3427unled:
061d17a6 3428 sdhci_led_unregister(host);
eb5c20de 3429unirq:
03231f9b 3430 sdhci_do_reset(host, SDHCI_RESET_ALL);
b537f94c
RK		 3431 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
3432 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
2f730fec 3433 free_irq(host->irq, host);
8ef1a143 3434untasklet:
d129bceb 3435 tasklet_kill(&host->finish_tasklet);
52f5336d 3436
eb5c20de
AH		 3437 if (!IS_ERR(mmc->supply.vqmmc))
3438 regulator_disable(mmc->supply.vqmmc);
52f5336d 3439
eb5c20de
AH		 3440 if (host->align_buffer)
3441 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
3442 host->adma_table_sz, host->align_buffer,
3443 host->align_addr);
3444 host->adma_table = NULL;
3445 host->align_buffer = NULL;
d129bceb
PO		 3446
3447 return ret;
3448}
52f5336d
AH		 3449EXPORT_SYMBOL_GPL(__sdhci_add_host);
3450
3451int sdhci_add_host(struct sdhci_host *host)
3452{
3453 int ret;
3454
3455 ret = sdhci_setup_host(host);
3456 if (ret)
3457 return ret;
d129bceb 3458
52f5336d
AH		 3459 return __sdhci_add_host(host);
3460}
b8c86fc5 3461EXPORT_SYMBOL_GPL(sdhci_add_host);
d129bceb 3462
1e72859e 3463void sdhci_remove_host(struct sdhci_host *host, int dead)
b8c86fc5 3464{
3a48edc4 3465 struct mmc_host *mmc = host->mmc;
1e72859e
PO		 3466 unsigned long flags;
3467
3468 if (dead) {
3469 spin_lock_irqsave(&host->lock, flags);
3470
3471 host->flags |= SDHCI_DEVICE_DEAD;
3472
3473 if (host->mrq) {
a3c76eb9 3474 pr_err("%s: Controller removed during "
4e743f1f 3475 " transfer!\n", mmc_hostname(mmc));
1e72859e
PO		 3476
3477 host->mrq->cmd->error = -ENOMEDIUM;
a6d3bdd5 3478 sdhci_finish_mrq(host, host->mrq);
1e72859e
PO		 3479 }
3480
3481 spin_unlock_irqrestore(&host->lock, flags);
3482 }
3483
7260cf5e
AV		 3484 sdhci_disable_card_detection(host);
3485
4e743f1f 3486 mmc_remove_host(mmc);
d129bceb 3487
061d17a6 3488 sdhci_led_unregister(host);
2f730fec 3489
1e72859e 3490 if (!dead)
03231f9b 3491 sdhci_do_reset(host, SDHCI_RESET_ALL);
d129bceb 3492
b537f94c
RK		 3493 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
3494 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
d129bceb
PO		 3495 free_irq(host->irq, host);
3496
3497 del_timer_sync(&host->timer);
3498
d129bceb 3499 tasklet_kill(&host->finish_tasklet);
2134a922 3500
3a48edc4
TK		 3501 if (!IS_ERR(mmc->supply.vqmmc))
3502 regulator_disable(mmc->supply.vqmmc);
6231f3de 3503
edd63fcc 3504 if (host->align_buffer)
e66e61cb
RK		 3505 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
3506 host->adma_table_sz, host->align_buffer,
3507 host->align_addr);
2134a922 3508
4efaa6fb 3509 host->adma_table = NULL;
2134a922 3510 host->align_buffer = NULL;
d129bceb
PO		 3511}
3512
b8c86fc5 3513EXPORT_SYMBOL_GPL(sdhci_remove_host);
d129bceb 3514
b8c86fc5 3515void sdhci_free_host(struct sdhci_host *host)
d129bceb 3516{
b8c86fc5 3517 mmc_free_host(host->mmc);
d129bceb
PO		 3518}
3519
b8c86fc5 3520EXPORT_SYMBOL_GPL(sdhci_free_host);
d129bceb
PO		 3521
3522/*****************************************************************************\
3523 * *
3524 * Driver init/exit *
3525 * *
3526\*****************************************************************************/
3527
3528static int __init sdhci_drv_init(void)
3529{
a3c76eb9 3530 pr_info(DRIVER_NAME
52fbf9c9 3531 ": Secure Digital Host Controller Interface driver\n");
a3c76eb9 3532 pr_info(DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
d129bceb 3533
b8c86fc5 3534 return 0;
d129bceb
PO		 3535}
3536
3537static void __exit sdhci_drv_exit(void)
3538{
d129bceb
PO		 3539}
3540
3541module_init(sdhci_drv_init);
3542module_exit(sdhci_drv_exit);
3543
df673b22 3544module_param(debug_quirks, uint, 0444);
66fd8ad5 3545module_param(debug_quirks2, uint, 0444);
67435274 3546
32710e8f 3547MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
b8c86fc5 3548MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver");
d129bceb 3549MODULE_LICENSE("GPL");
67435274 3550
df673b22 3551MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");
66fd8ad5 3552MODULE_PARM_DESC(debug_quirks2, "Force certain other quirks.");
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