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mmc: sdhci: Remove redundant ADMA page boundary warnings
[mirror_ubuntu-artful-kernel.git] / drivers / mmc / host / sdhci.c
CommitLineData
d129bceb 1/*
70f10482 2 * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
d129bceb 3 *
b69c9058 4 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
d129bceb
PO		 5 *
6 * This program is free software; you can redistribute it and/or modify
643f720c
PO		 7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or (at
9 * your option) any later version.
84c46a53
PO		 10 *
11 * Thanks to the following companies for their support:
12 *
13 * - JMicron (hardware and technical support)
d129bceb
PO		 14 */
15
d129bceb
PO		 16#include <linux/delay.h>
17#include <linux/highmem.h>
b8c86fc5 18#include <linux/io.h>
88b47679 19#include <linux/module.h>
d129bceb 20#include <linux/dma-mapping.h>
5a0e3ad6 21#include <linux/slab.h>
11763609 22#include <linux/scatterlist.h>
9bea3c85 23#include <linux/regulator/consumer.h>
66fd8ad5 24#include <linux/pm_runtime.h>
d129bceb 25
2f730fec
PO		 26#include <linux/leds.h>
27
22113efd 28#include <linux/mmc/mmc.h>
d129bceb 29#include <linux/mmc/host.h>
473b095a 30#include <linux/mmc/card.h>
bec9d4e5 31#include <linux/mmc/slot-gpio.h>
d129bceb 32
d129bceb
PO		 33#include "sdhci.h"
34
35#define DRIVER_NAME "sdhci"
d129bceb 36
d129bceb 37#define DBG(f, x...) \
c6563178 38 pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
d129bceb 39
f9134319
PO		 40#if defined(CONFIG_LEDS_CLASS) || (defined(CONFIG_LEDS_CLASS_MODULE) && \
41 defined(CONFIG_MMC_SDHCI_MODULE))
42#define SDHCI_USE_LEDS_CLASS
43#endif
44
b513ea25
AN		 45#define MAX_TUNING_LOOP 40
46
df673b22 47static unsigned int debug_quirks = 0;
66fd8ad5 48static unsigned int debug_quirks2;
67435274 49
d129bceb
PO		 50static void sdhci_finish_data(struct sdhci_host *);
51
d129bceb 52static void sdhci_finish_command(struct sdhci_host *);
069c9f14 53static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode);
cf2b5eea 54static void sdhci_tuning_timer(unsigned long data);
52983382 55static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable);
d129bceb 56
162d6f98 57#ifdef CONFIG_PM
66fd8ad5
AH		 58static int sdhci_runtime_pm_get(struct sdhci_host *host);
59static int sdhci_runtime_pm_put(struct sdhci_host *host);
f0710a55
AH		 60static void sdhci_runtime_pm_bus_on(struct sdhci_host *host);
61static void sdhci_runtime_pm_bus_off(struct sdhci_host *host);
66fd8ad5
AH		 62#else
63static inline int sdhci_runtime_pm_get(struct sdhci_host *host)
64{
65 return 0;
66}
67static inline int sdhci_runtime_pm_put(struct sdhci_host *host)
68{
69 return 0;
70}
f0710a55
AH		 71static void sdhci_runtime_pm_bus_on(struct sdhci_host *host)
72{
73}
74static void sdhci_runtime_pm_bus_off(struct sdhci_host *host)
75{
76}
66fd8ad5
AH		 77#endif
78
d129bceb
PO		 79static void sdhci_dumpregs(struct sdhci_host *host)
80{
a3c76eb9 81 pr_debug(DRIVER_NAME ": =========== REGISTER DUMP (%s)===========\n",
412ab659 82 mmc_hostname(host->mmc));
d129bceb 83
a3c76eb9 84 pr_debug(DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n",
4e4141a5
AV		 85 sdhci_readl(host, SDHCI_DMA_ADDRESS),
86 sdhci_readw(host, SDHCI_HOST_VERSION));
a3c76eb9 87 pr_debug(DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n",
4e4141a5
AV		 88 sdhci_readw(host, SDHCI_BLOCK_SIZE),
89 sdhci_readw(host, SDHCI_BLOCK_COUNT));
a3c76eb9 90 pr_debug(DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
4e4141a5
AV		 91 sdhci_readl(host, SDHCI_ARGUMENT),
92 sdhci_readw(host, SDHCI_TRANSFER_MODE));
a3c76eb9 93 pr_debug(DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n",
4e4141a5
AV		 94 sdhci_readl(host, SDHCI_PRESENT_STATE),
95 sdhci_readb(host, SDHCI_HOST_CONTROL));
a3c76eb9 96 pr_debug(DRIVER_NAME ": Power: 0x%08x | Blk gap: 0x%08x\n",
4e4141a5
AV		 97 sdhci_readb(host, SDHCI_POWER_CONTROL),
98 sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL));
a3c76eb9 99 pr_debug(DRIVER_NAME ": Wake-up: 0x%08x | Clock: 0x%08x\n",
4e4141a5
AV		 100 sdhci_readb(host, SDHCI_WAKE_UP_CONTROL),
101 sdhci_readw(host, SDHCI_CLOCK_CONTROL));
a3c76eb9 102 pr_debug(DRIVER_NAME ": Timeout: 0x%08x | Int stat: 0x%08x\n",
4e4141a5
AV		 103 sdhci_readb(host, SDHCI_TIMEOUT_CONTROL),
104 sdhci_readl(host, SDHCI_INT_STATUS));
a3c76eb9 105 pr_debug(DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
4e4141a5
AV		 106 sdhci_readl(host, SDHCI_INT_ENABLE),
107 sdhci_readl(host, SDHCI_SIGNAL_ENABLE));
a3c76eb9 108 pr_debug(DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
4e4141a5
AV		 109 sdhci_readw(host, SDHCI_ACMD12_ERR),
110 sdhci_readw(host, SDHCI_SLOT_INT_STATUS));
a3c76eb9 111 pr_debug(DRIVER_NAME ": Caps: 0x%08x | Caps_1: 0x%08x\n",
4e4141a5 112 sdhci_readl(host, SDHCI_CAPABILITIES),
e8120ad1 113 sdhci_readl(host, SDHCI_CAPABILITIES_1));
a3c76eb9 114 pr_debug(DRIVER_NAME ": Cmd: 0x%08x | Max curr: 0x%08x\n",
e8120ad1 115 sdhci_readw(host, SDHCI_COMMAND),
4e4141a5 116 sdhci_readl(host, SDHCI_MAX_CURRENT));
a3c76eb9 117 pr_debug(DRIVER_NAME ": Host ctl2: 0x%08x\n",
f2119df6 118 sdhci_readw(host, SDHCI_HOST_CONTROL2));
d129bceb 119
e57a5f61
AH		 120 if (host->flags & SDHCI_USE_ADMA) {
121 if (host->flags & SDHCI_USE_64_BIT_DMA)
122 pr_debug(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x%08x\n",
123 readl(host->ioaddr + SDHCI_ADMA_ERROR),
124 readl(host->ioaddr + SDHCI_ADMA_ADDRESS_HI),
125 readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
126 else
127 pr_debug(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n",
128 readl(host->ioaddr + SDHCI_ADMA_ERROR),
129 readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
130 }
be3f4ae0 131
a3c76eb9 132 pr_debug(DRIVER_NAME ": ===========================================\n");
d129bceb
PO		 133}
134
135/*****************************************************************************\
136 * *
137 * Low level functions *
138 * *
139\*****************************************************************************/
140
7260cf5e
AV		 141static void sdhci_set_card_detection(struct sdhci_host *host, bool enable)
142{
5b4f1f6c 143 u32 present;
7260cf5e 144
c79396c1 145 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) ||
87b87a3f 146 (host->mmc->caps & MMC_CAP_NONREMOVABLE))
66fd8ad5
AH		 147 return;
148
5b4f1f6c
RK		 149 if (enable) {
150 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
151 SDHCI_CARD_PRESENT;
d25928d1 152
5b4f1f6c
RK		 153 host->ier |= present ? SDHCI_INT_CARD_REMOVE :
154 SDHCI_INT_CARD_INSERT;
155 } else {
156 host->ier &= ~(SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT);
157 }
b537f94c
RK		 158
159 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
160 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
7260cf5e
AV		 161}
162
163static void sdhci_enable_card_detection(struct sdhci_host *host)
164{
165 sdhci_set_card_detection(host, true);
166}
167
168static void sdhci_disable_card_detection(struct sdhci_host *host)
169{
170 sdhci_set_card_detection(host, false);
171}
172
03231f9b 173void sdhci_reset(struct sdhci_host *host, u8 mask)
d129bceb 174{
e16514d8 175 unsigned long timeout;
393c1a34 176
4e4141a5 177 sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
d129bceb 178
f0710a55 179 if (mask & SDHCI_RESET_ALL) {
d129bceb 180 host->clock = 0;
f0710a55
AH		 181 /* Reset-all turns off SD Bus Power */
182 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
183 sdhci_runtime_pm_bus_off(host);
184 }
d129bceb 185
e16514d8
PO		 186 /* Wait max 100 ms */
187 timeout = 100;
188
189 /* hw clears the bit when it's done */
4e4141a5 190 while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
e16514d8 191 if (timeout == 0) {
a3c76eb9 192 pr_err("%s: Reset 0x%x never completed.\n",
e16514d8
PO		 193 mmc_hostname(host->mmc), (int)mask);
194 sdhci_dumpregs(host);
195 return;
196 }
197 timeout--;
198 mdelay(1);
d129bceb 199 }
03231f9b
RK		 200}
201EXPORT_SYMBOL_GPL(sdhci_reset);
202
203static void sdhci_do_reset(struct sdhci_host *host, u8 mask)
204{
205 if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
206 if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) &
207 SDHCI_CARD_PRESENT))
208 return;
209 }
063a9dbb 210
03231f9b 211 host->ops->reset(host, mask);
393c1a34 212
da91a8f9
RK		 213 if (mask & SDHCI_RESET_ALL) {
214 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
215 if (host->ops->enable_dma)
216 host->ops->enable_dma(host);
217 }
218
219 /* Resetting the controller clears many */
220 host->preset_enabled = false;
3abc1e80 221 }
d129bceb
PO		 222}
223
2f4cbb3d
NP		 224static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios);
225
226static void sdhci_init(struct sdhci_host *host, int soft)
d129bceb 227{
2f4cbb3d 228 if (soft)
03231f9b 229 sdhci_do_reset(host, SDHCI_RESET_CMD|SDHCI_RESET_DATA);
2f4cbb3d 230 else
03231f9b 231 sdhci_do_reset(host, SDHCI_RESET_ALL);
d129bceb 232
b537f94c
RK		 233 host->ier = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
234 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT |
235 SDHCI_INT_INDEX | SDHCI_INT_END_BIT | SDHCI_INT_CRC |
236 SDHCI_INT_TIMEOUT | SDHCI_INT_DATA_END |
237 SDHCI_INT_RESPONSE;
238
239 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
240 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2f4cbb3d
NP		 241
242 if (soft) {
243 /* force clock reconfiguration */
244 host->clock = 0;
245 sdhci_set_ios(host->mmc, &host->mmc->ios);
246 }
7260cf5e 247}
d129bceb 248
7260cf5e
AV		 249static void sdhci_reinit(struct sdhci_host *host)
250{
2f4cbb3d 251 sdhci_init(host, 0);
b67c6b41
AL		 252 /*
253 * Retuning stuffs are affected by different cards inserted and only
254 * applicable to UHS-I cards. So reset these fields to their initial
255 * value when card is removed.
256 */
973905fe
AL		 257 if (host->flags & SDHCI_USING_RETUNING_TIMER) {
258 host->flags &= ~SDHCI_USING_RETUNING_TIMER;
259
b67c6b41
AL		 260 del_timer_sync(&host->tuning_timer);
261 host->flags &= ~SDHCI_NEEDS_RETUNING;
b67c6b41 262 }
7260cf5e 263 sdhci_enable_card_detection(host);
d129bceb
PO		 264}
265
266static void sdhci_activate_led(struct sdhci_host *host)
267{
268 u8 ctrl;
269
4e4141a5 270 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
d129bceb 271 ctrl |= SDHCI_CTRL_LED;
4e4141a5 272 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d129bceb
PO		 273}
274
275static void sdhci_deactivate_led(struct sdhci_host *host)
276{
277 u8 ctrl;
278
4e4141a5 279 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
d129bceb 280 ctrl &= ~SDHCI_CTRL_LED;
4e4141a5 281 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d129bceb
PO		 282}
283
f9134319 284#ifdef SDHCI_USE_LEDS_CLASS
2f730fec
PO		 285static void sdhci_led_control(struct led_classdev *led,
286 enum led_brightness brightness)
287{
288 struct sdhci_host *host = container_of(led, struct sdhci_host, led);
289 unsigned long flags;
290
291 spin_lock_irqsave(&host->lock, flags);
292
66fd8ad5
AH		 293 if (host->runtime_suspended)
294 goto out;
295
2f730fec
PO		 296 if (brightness == LED_OFF)
297 sdhci_deactivate_led(host);
298 else
299 sdhci_activate_led(host);
66fd8ad5 300out:
2f730fec
PO		 301 spin_unlock_irqrestore(&host->lock, flags);
302}
303#endif
304
d129bceb
PO		 305/*****************************************************************************\
306 * *
307 * Core functions *
308 * *
309\*****************************************************************************/
310
a406f5a3 311static void sdhci_read_block_pio(struct sdhci_host *host)
d129bceb 312{
7659150c
PO		 313 unsigned long flags;
314 size_t blksize, len, chunk;
7244b85b 315 u32 uninitialized_var(scratch);
7659150c 316 u8 *buf;
d129bceb 317
a406f5a3 318 DBG("PIO reading\n");
d129bceb 319
a406f5a3 320 blksize = host->data->blksz;
7659150c 321 chunk = 0;
d129bceb 322
7659150c 323 local_irq_save(flags);
d129bceb 324
a406f5a3 325 while (blksize) {
7659150c
PO		 326 if (!sg_miter_next(&host->sg_miter))
327 BUG();
d129bceb 328
7659150c 329 len = min(host->sg_miter.length, blksize);
d129bceb 330
7659150c
PO		 331 blksize -= len;
332 host->sg_miter.consumed = len;
14d836e7 333
7659150c 334 buf = host->sg_miter.addr;
d129bceb 335
7659150c
PO		 336 while (len) {
337 if (chunk == 0) {
4e4141a5 338 scratch = sdhci_readl(host, SDHCI_BUFFER);
7659150c 339 chunk = 4;
a406f5a3 340 }
7659150c
PO		 341
342 *buf = scratch & 0xFF;
343
344 buf++;
345 scratch >>= 8;
346 chunk--;
347 len--;
d129bceb 348 }
a406f5a3 349 }
7659150c
PO		 350
351 sg_miter_stop(&host->sg_miter);
352
353 local_irq_restore(flags);
a406f5a3 354}
d129bceb 355
a406f5a3
PO		 356static void sdhci_write_block_pio(struct sdhci_host *host)
357{
7659150c
PO		 358 unsigned long flags;
359 size_t blksize, len, chunk;
360 u32 scratch;
361 u8 *buf;
d129bceb 362
a406f5a3
PO		 363 DBG("PIO writing\n");
364
365 blksize = host->data->blksz;
7659150c
PO		 366 chunk = 0;
367 scratch = 0;
d129bceb 368
7659150c 369 local_irq_save(flags);
d129bceb 370
a406f5a3 371 while (blksize) {
7659150c
PO		 372 if (!sg_miter_next(&host->sg_miter))
373 BUG();
a406f5a3 374
7659150c
PO		 375 len = min(host->sg_miter.length, blksize);
376
377 blksize -= len;
378 host->sg_miter.consumed = len;
379
380 buf = host->sg_miter.addr;
d129bceb 381
7659150c
PO		 382 while (len) {
383 scratch |= (u32)*buf << (chunk * 8);
384
385 buf++;
386 chunk++;
387 len--;
388
389 if ((chunk == 4) || ((len == 0) && (blksize == 0))) {
4e4141a5 390 sdhci_writel(host, scratch, SDHCI_BUFFER);
7659150c
PO		 391 chunk = 0;
392 scratch = 0;
d129bceb 393 }
d129bceb
PO		 394 }
395 }
7659150c
PO		 396
397 sg_miter_stop(&host->sg_miter);
398
399 local_irq_restore(flags);
a406f5a3
PO		 400}
401
402static void sdhci_transfer_pio(struct sdhci_host *host)
403{
404 u32 mask;
405
406 BUG_ON(!host->data);
407
7659150c 408 if (host->blocks == 0)
a406f5a3
PO		 409 return;
410
411 if (host->data->flags & MMC_DATA_READ)
412 mask = SDHCI_DATA_AVAILABLE;
413 else
414 mask = SDHCI_SPACE_AVAILABLE;
415
4a3cba32
PO		 416 /*
417 * Some controllers (JMicron JMB38x) mess up the buffer bits
418 * for transfers < 4 bytes. As long as it is just one block,
419 * we can ignore the bits.
420 */
421 if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) &&
422 (host->data->blocks == 1))
423 mask = ~0;
424
4e4141a5 425 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
3e3bf207
AV		 426 if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY)
427 udelay(100);
428
a406f5a3
PO		 429 if (host->data->flags & MMC_DATA_READ)
430 sdhci_read_block_pio(host);
431 else
432 sdhci_write_block_pio(host);
d129bceb 433
7659150c
PO		 434 host->blocks--;
435 if (host->blocks == 0)
a406f5a3 436 break;
a406f5a3 437 }
d129bceb 438
a406f5a3 439 DBG("PIO transfer complete.\n");
d129bceb
PO		 440}
441
2134a922
PO		 442static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags)
443{
444 local_irq_save(*flags);
482fce99 445 return kmap_atomic(sg_page(sg)) + sg->offset;
2134a922
PO		 446}
447
448static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags)
449{
482fce99 450 kunmap_atomic(buffer);
2134a922
PO		 451 local_irq_restore(*flags);
452}
453
e57a5f61
AH		 454static void sdhci_adma_write_desc(struct sdhci_host *host, void *desc,
455 dma_addr_t addr, int len, unsigned cmd)
118cd17d 456{
e57a5f61 457 struct sdhci_adma2_64_desc *dma_desc = desc;
118cd17d 458
e57a5f61 459 /* 32-bit and 64-bit descriptors have these members in same position */
0545230f
AH		 460 dma_desc->cmd = cpu_to_le16(cmd);
461 dma_desc->len = cpu_to_le16(len);
e57a5f61
AH		 462 dma_desc->addr_lo = cpu_to_le32((u32)addr);
463
464 if (host->flags & SDHCI_USE_64_BIT_DMA)
465 dma_desc->addr_hi = cpu_to_le32((u64)addr >> 32);
118cd17d
BD		 466}
467
b5ffa674
AH		 468static void sdhci_adma_mark_end(void *desc)
469{
e57a5f61 470 struct sdhci_adma2_64_desc *dma_desc = desc;
b5ffa674 471
e57a5f61 472 /* 32-bit and 64-bit descriptors have 'cmd' in same position */
0545230f 473 dma_desc->cmd |= cpu_to_le16(ADMA2_END);
b5ffa674
AH		 474}
475
8f1934ce 476static int sdhci_adma_table_pre(struct sdhci_host *host,
2134a922
PO		 477 struct mmc_data *data)
478{
479 int direction;
480
1c3d5f6d
AH		 481 void *desc;
482 void *align;
2134a922
PO		 483 dma_addr_t addr;
484 dma_addr_t align_addr;
485 int len, offset;
486
487 struct scatterlist *sg;
488 int i;
489 char *buffer;
490 unsigned long flags;
491
492 /*
493 * The spec does not specify endianness of descriptor table.
494 * We currently guess that it is LE.
495 */
496
497 if (data->flags & MMC_DATA_READ)
498 direction = DMA_FROM_DEVICE;
499 else
500 direction = DMA_TO_DEVICE;
501
2134a922 502 host->align_addr = dma_map_single(mmc_dev(host->mmc),
76fe379a 503 host->align_buffer, host->align_buffer_sz, direction);
8d8bb39b 504 if (dma_mapping_error(mmc_dev(host->mmc), host->align_addr))
8f1934ce 505 goto fail;
76fe379a 506 BUG_ON(host->align_addr & host->align_mask);
2134a922
PO		 507
508 host->sg_count = dma_map_sg(mmc_dev(host->mmc),
509 data->sg, data->sg_len, direction);
8f1934ce
PO		 510 if (host->sg_count == 0)
511 goto unmap_align;
2134a922 512
4efaa6fb 513 desc = host->adma_table;
2134a922
PO		 514 align = host->align_buffer;
515
516 align_addr = host->align_addr;
517
518 for_each_sg(data->sg, sg, host->sg_count, i) {
519 addr = sg_dma_address(sg);
520 len = sg_dma_len(sg);
521
522 /*
523 * The SDHCI specification states that ADMA
524 * addresses must be 32-bit aligned. If they
525 * aren't, then we use a bounce buffer for
526 * the (up to three) bytes that screw up the
527 * alignment.
528 */
76fe379a
AH		 529 offset = (host->align_sz - (addr & host->align_mask)) &
530 host->align_mask;
2134a922
PO		 531 if (offset) {
532 if (data->flags & MMC_DATA_WRITE) {
533 buffer = sdhci_kmap_atomic(sg, &flags);
534 memcpy(align, buffer, offset);
535 sdhci_kunmap_atomic(buffer, &flags);
536 }
537
118cd17d 538 /* tran, valid */
e57a5f61 539 sdhci_adma_write_desc(host, desc, align_addr, offset,
739d46dc 540 ADMA2_TRAN_VALID);
2134a922
PO		 541
542 BUG_ON(offset > 65536);
543
76fe379a
AH		 544 align += host->align_sz;
545 align_addr += host->align_sz;
2134a922 546
76fe379a 547 desc += host->desc_sz;
2134a922
PO		 548
549 addr += offset;
550 len -= offset;
551 }
552
2134a922
PO		 553 BUG_ON(len > 65536);
554
118cd17d 555 /* tran, valid */
e57a5f61 556 sdhci_adma_write_desc(host, desc, addr, len, ADMA2_TRAN_VALID);
76fe379a 557 desc += host->desc_sz;
2134a922
PO		 558
559 /*
560 * If this triggers then we have a calculation bug
561 * somewhere. :/
562 */
76fe379a 563 WARN_ON((desc - host->adma_table) >= host->adma_table_sz);
2134a922
PO		 564 }
565
70764a90
TA		 566 if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) {
567 /*
568 * Mark the last descriptor as the terminating descriptor
569 */
4efaa6fb 570 if (desc != host->adma_table) {
76fe379a 571 desc -= host->desc_sz;
b5ffa674 572 sdhci_adma_mark_end(desc);
70764a90
TA		 573 }
574 } else {
575 /*
576 * Add a terminating entry.
577 */
2134a922 578
70764a90 579 /* nop, end, valid */
e57a5f61 580 sdhci_adma_write_desc(host, desc, 0, 0, ADMA2_NOP_END_VALID);
70764a90 581 }
2134a922
PO		 582
583 /*
584 * Resync align buffer as we might have changed it.
585 */
586 if (data->flags & MMC_DATA_WRITE) {
587 dma_sync_single_for_device(mmc_dev(host->mmc),
76fe379a 588 host->align_addr, host->align_buffer_sz, direction);
2134a922
PO		 589 }
590
8f1934ce
PO		 591 return 0;
592
8f1934ce
PO		 593unmap_align:
594 dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
76fe379a 595 host->align_buffer_sz, direction);
8f1934ce
PO		 596fail:
597 return -EINVAL;
2134a922
PO		 598}
599
600static void sdhci_adma_table_post(struct sdhci_host *host,
601 struct mmc_data *data)
602{
603 int direction;
604
605 struct scatterlist *sg;
606 int i, size;
1c3d5f6d 607 void *align;
2134a922
PO		 608 char *buffer;
609 unsigned long flags;
de0b65a7 610 bool has_unaligned;
2134a922
PO		 611
612 if (data->flags & MMC_DATA_READ)
613 direction = DMA_FROM_DEVICE;
614 else
615 direction = DMA_TO_DEVICE;
616
2134a922 617 dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
76fe379a 618 host->align_buffer_sz, direction);
2134a922 619
de0b65a7
RK		 620 /* Do a quick scan of the SG list for any unaligned mappings */
621 has_unaligned = false;
622 for_each_sg(data->sg, sg, host->sg_count, i)
76fe379a 623 if (sg_dma_address(sg) & host->align_mask) {
de0b65a7
RK		 624 has_unaligned = true;
625 break;
626 }
627
628 if (has_unaligned && data->flags & MMC_DATA_READ) {
2134a922
PO		 629 dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
630 data->sg_len, direction);
631
632 align = host->align_buffer;
633
634 for_each_sg(data->sg, sg, host->sg_count, i) {
76fe379a
AH		 635 if (sg_dma_address(sg) & host->align_mask) {
636 size = host->align_sz -
637 (sg_dma_address(sg) & host->align_mask);
2134a922
PO		 638
639 buffer = sdhci_kmap_atomic(sg, &flags);
640 memcpy(buffer, align, size);
641 sdhci_kunmap_atomic(buffer, &flags);
642
76fe379a 643 align += host->align_sz;
2134a922
PO		 644 }
645 }
646 }
647
648 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
649 data->sg_len, direction);
650}
651
a3c7778f 652static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd)
d129bceb 653{
1c8cde92 654 u8 count;
a3c7778f 655 struct mmc_data *data = cmd->data;
1c8cde92 656 unsigned target_timeout, current_timeout;
d129bceb 657
ee53ab5d
PO		 658 /*
659 * If the host controller provides us with an incorrect timeout
660 * value, just skip the check and use 0xE. The hardware may take
661 * longer to time out, but that's much better than having a too-short
662 * timeout value.
663 */
11a2f1b7 664 if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL)
ee53ab5d 665 return 0xE;
e538fbe8 666
a3c7778f 667 /* Unspecified timeout, assume max */
1d4d7744 668 if (!data && !cmd->busy_timeout)
a3c7778f 669 return 0xE;
d129bceb 670
a3c7778f
AW		 671 /* timeout in us */
672 if (!data)
1d4d7744 673 target_timeout = cmd->busy_timeout * 1000;
78a2ca27
AS		 674 else {
675 target_timeout = data->timeout_ns / 1000;
676 if (host->clock)
677 target_timeout += data->timeout_clks / host->clock;
678 }
81b39802 679
1c8cde92
PO		 680 /*
681 * Figure out needed cycles.
682 * We do this in steps in order to fit inside a 32 bit int.
683 * The first step is the minimum timeout, which will have a
684 * minimum resolution of 6 bits:
685 * (1) 2^13*1000 > 2^22,
686 * (2) host->timeout_clk < 2^16
687 * =>
688 * (1) / (2) > 2^6
689 */
690 count = 0;
691 current_timeout = (1 << 13) * 1000 / host->timeout_clk;
692 while (current_timeout < target_timeout) {
693 count++;
694 current_timeout <<= 1;
695 if (count >= 0xF)
696 break;
697 }
698
699 if (count >= 0xF) {
09eeff52
CB		 700 DBG("%s: Too large timeout 0x%x requested for CMD%d!\n",
701 mmc_hostname(host->mmc), count, cmd->opcode);
1c8cde92
PO		 702 count = 0xE;
703 }
704
ee53ab5d
PO		 705 return count;
706}
707
6aa943ab
AV		 708static void sdhci_set_transfer_irqs(struct sdhci_host *host)
709{
710 u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL;
711 u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR;
712
713 if (host->flags & SDHCI_REQ_USE_DMA)
b537f94c 714 host->ier = (host->ier & ~pio_irqs) | dma_irqs;
6aa943ab 715 else
b537f94c
RK		 716 host->ier = (host->ier & ~dma_irqs) | pio_irqs;
717
718 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
719 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
6aa943ab
AV		 720}
721
b45e668a 722static void sdhci_set_timeout(struct sdhci_host *host, struct mmc_command *cmd)
ee53ab5d
PO		 723{
724 u8 count;
b45e668a
AD		 725
726 if (host->ops->set_timeout) {
727 host->ops->set_timeout(host, cmd);
728 } else {
729 count = sdhci_calc_timeout(host, cmd);
730 sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
731 }
732}
733
734static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd)
735{
2134a922 736 u8 ctrl;
a3c7778f 737 struct mmc_data *data = cmd->data;
8f1934ce 738 int ret;
ee53ab5d
PO		 739
740 WARN_ON(host->data);
741
b45e668a
AD		 742 if (data || (cmd->flags & MMC_RSP_BUSY))
743 sdhci_set_timeout(host, cmd);
a3c7778f
AW		 744
745 if (!data)
ee53ab5d
PO		 746 return;
747
748 /* Sanity checks */
749 BUG_ON(data->blksz * data->blocks > 524288);
750 BUG_ON(data->blksz > host->mmc->max_blk_size);
751 BUG_ON(data->blocks > 65535);
752
753 host->data = data;
754 host->data_early = 0;
f6a03cbf 755 host->data->bytes_xfered = 0;
ee53ab5d 756
a13abc7b 757 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))
c9fddbc4
PO		 758 host->flags |= SDHCI_REQ_USE_DMA;
759
2134a922
PO		 760 /*
761 * FIXME: This doesn't account for merging when mapping the
762 * scatterlist.
763 */
764 if (host->flags & SDHCI_REQ_USE_DMA) {
765 int broken, i;
766 struct scatterlist *sg;
767
768 broken = 0;
769 if (host->flags & SDHCI_USE_ADMA) {
770 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
771 broken = 1;
772 } else {
773 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE)
774 broken = 1;
775 }
776
777 if (unlikely(broken)) {
778 for_each_sg(data->sg, sg, data->sg_len, i) {
779 if (sg->length & 0x3) {
780 DBG("Reverting to PIO because of "
781 "transfer size (%d)\n",
782 sg->length);
783 host->flags &= ~SDHCI_REQ_USE_DMA;
784 break;
785 }
786 }
787 }
c9fddbc4
PO		 788 }
789
790 /*
791 * The assumption here being that alignment is the same after
792 * translation to device address space.
793 */
2134a922
PO		 794 if (host->flags & SDHCI_REQ_USE_DMA) {
795 int broken, i;
796 struct scatterlist *sg;
797
798 broken = 0;
799 if (host->flags & SDHCI_USE_ADMA) {
800 /*
801 * As we use 3 byte chunks to work around
802 * alignment problems, we need to check this
803 * quirk.
804 */
805 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
806 broken = 1;
807 } else {
808 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR)
809 broken = 1;
810 }
811
812 if (unlikely(broken)) {
813 for_each_sg(data->sg, sg, data->sg_len, i) {
814 if (sg->offset & 0x3) {
815 DBG("Reverting to PIO because of "
816 "bad alignment\n");
817 host->flags &= ~SDHCI_REQ_USE_DMA;
818 break;
819 }
820 }
821 }
822 }
823
8f1934ce
PO		 824 if (host->flags & SDHCI_REQ_USE_DMA) {
825 if (host->flags & SDHCI_USE_ADMA) {
826 ret = sdhci_adma_table_pre(host, data);
827 if (ret) {
828 /*
829 * This only happens when someone fed
830 * us an invalid request.
831 */
832 WARN_ON(1);
ebd6d357 833 host->flags &= ~SDHCI_REQ_USE_DMA;
8f1934ce 834 } else {
4e4141a5
AV		 835 sdhci_writel(host, host->adma_addr,
836 SDHCI_ADMA_ADDRESS);
e57a5f61
AH		 837 if (host->flags & SDHCI_USE_64_BIT_DMA)
838 sdhci_writel(host,
839 (u64)host->adma_addr >> 32,
840 SDHCI_ADMA_ADDRESS_HI);
8f1934ce
PO		 841 }
842 } else {
c8b3e02e 843 int sg_cnt;
8f1934ce 844
c8b3e02e 845 sg_cnt = dma_map_sg(mmc_dev(host->mmc),
8f1934ce
PO		 846 data->sg, data->sg_len,
847 (data->flags & MMC_DATA_READ) ?
848 DMA_FROM_DEVICE :
849 DMA_TO_DEVICE);
c8b3e02e 850 if (sg_cnt == 0) {
8f1934ce
PO		 851 /*
852 * This only happens when someone fed
853 * us an invalid request.
854 */
855 WARN_ON(1);
ebd6d357 856 host->flags &= ~SDHCI_REQ_USE_DMA;
8f1934ce 857 } else {
719a61b4 858 WARN_ON(sg_cnt != 1);
4e4141a5
AV		 859 sdhci_writel(host, sg_dma_address(data->sg),
860 SDHCI_DMA_ADDRESS);
8f1934ce
PO		 861 }
862 }
863 }
864
2134a922
PO		 865 /*
866 * Always adjust the DMA selection as some controllers
867 * (e.g. JMicron) can't do PIO properly when the selection
868 * is ADMA.
869 */
870 if (host->version >= SDHCI_SPEC_200) {
4e4141a5 871 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
2134a922
PO		 872 ctrl &= ~SDHCI_CTRL_DMA_MASK;
873 if ((host->flags & SDHCI_REQ_USE_DMA) &&
e57a5f61
AH		 874 (host->flags & SDHCI_USE_ADMA)) {
875 if (host->flags & SDHCI_USE_64_BIT_DMA)
876 ctrl |= SDHCI_CTRL_ADMA64;
877 else
878 ctrl |= SDHCI_CTRL_ADMA32;
879 } else {
2134a922 880 ctrl |= SDHCI_CTRL_SDMA;
e57a5f61 881 }
4e4141a5 882 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
c9fddbc4
PO		 883 }
884
8f1934ce 885 if (!(host->flags & SDHCI_REQ_USE_DMA)) {
da60a91d
SAS		 886 int flags;
887
888 flags = SG_MITER_ATOMIC;
889 if (host->data->flags & MMC_DATA_READ)
890 flags |= SG_MITER_TO_SG;
891 else
892 flags |= SG_MITER_FROM_SG;
893 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
7659150c 894 host->blocks = data->blocks;
d129bceb 895 }
c7fa9963 896
6aa943ab
AV		 897 sdhci_set_transfer_irqs(host);
898
f6a03cbf
MV		 899 /* Set the DMA boundary value and block size */
900 sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
901 data->blksz), SDHCI_BLOCK_SIZE);
4e4141a5 902 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
c7fa9963
PO		 903}
904
905static void sdhci_set_transfer_mode(struct sdhci_host *host,
e89d456f 906 struct mmc_command *cmd)
c7fa9963
PO		 907{
908 u16 mode;
e89d456f 909 struct mmc_data *data = cmd->data;
c7fa9963 910
2b558c13 911 if (data == NULL) {
9b8ffea6
VW		 912 if (host->quirks2 &
913 SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD) {
914 sdhci_writew(host, 0x0, SDHCI_TRANSFER_MODE);
915 } else {
2b558c13 916 /* clear Auto CMD settings for no data CMDs */
9b8ffea6
VW		 917 mode = sdhci_readw(host, SDHCI_TRANSFER_MODE);
918 sdhci_writew(host, mode & ~(SDHCI_TRNS_AUTO_CMD12 |
2b558c13 919 SDHCI_TRNS_AUTO_CMD23), SDHCI_TRANSFER_MODE);
9b8ffea6 920 }
c7fa9963 921 return;
2b558c13 922 }
c7fa9963 923
e538fbe8
PO		 924 WARN_ON(!host->data);
925
c7fa9963 926 mode = SDHCI_TRNS_BLK_CNT_EN;
e89d456f
AW		 927 if (mmc_op_multi(cmd->opcode) || data->blocks > 1) {
928 mode |= SDHCI_TRNS_MULTI;
929 /*
930 * If we are sending CMD23, CMD12 never gets sent
931 * on successful completion (so no Auto-CMD12).
932 */
933 if (!host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD12))
934 mode |= SDHCI_TRNS_AUTO_CMD12;
8edf6371
AW		 935 else if (host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) {
936 mode |= SDHCI_TRNS_AUTO_CMD23;
937 sdhci_writel(host, host->mrq->sbc->arg, SDHCI_ARGUMENT2);
938 }
c4512f79 939 }
8edf6371 940
c7fa9963
PO		 941 if (data->flags & MMC_DATA_READ)
942 mode |= SDHCI_TRNS_READ;
c9fddbc4 943 if (host->flags & SDHCI_REQ_USE_DMA)
c7fa9963
PO		 944 mode |= SDHCI_TRNS_DMA;
945
4e4141a5 946 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
d129bceb
PO		 947}
948
949static void sdhci_finish_data(struct sdhci_host *host)
950{
951 struct mmc_data *data;
d129bceb
PO		 952
953 BUG_ON(!host->data);
954
955 data = host->data;
956 host->data = NULL;
957
c9fddbc4 958 if (host->flags & SDHCI_REQ_USE_DMA) {
2134a922
PO		 959 if (host->flags & SDHCI_USE_ADMA)
960 sdhci_adma_table_post(host, data);
961 else {
962 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
963 data->sg_len, (data->flags & MMC_DATA_READ) ?
964 DMA_FROM_DEVICE : DMA_TO_DEVICE);
965 }
d129bceb
PO		 966 }
967
968 /*
c9b74c5b
PO		 969 * The specification states that the block count register must
970 * be updated, but it does not specify at what point in the
971 * data flow. That makes the register entirely useless to read
972 * back so we have to assume that nothing made it to the card
973 * in the event of an error.
d129bceb 974 */
c9b74c5b
PO		 975 if (data->error)
976 data->bytes_xfered = 0;
d129bceb 977 else
c9b74c5b 978 data->bytes_xfered = data->blksz * data->blocks;
d129bceb 979
e89d456f
AW		 980 /*
981 * Need to send CMD12 if -
982 * a) open-ended multiblock transfer (no CMD23)
983 * b) error in multiblock transfer
984 */
985 if (data->stop &&
986 (data->error ||
987 !host->mrq->sbc)) {
988
d129bceb
PO		 989 /*
990 * The controller needs a reset of internal state machines
991 * upon error conditions.
992 */
17b0429d 993 if (data->error) {
03231f9b
RK		 994 sdhci_do_reset(host, SDHCI_RESET_CMD);
995 sdhci_do_reset(host, SDHCI_RESET_DATA);
d129bceb
PO		 996 }
997
998 sdhci_send_command(host, data->stop);
999 } else
1000 tasklet_schedule(&host->finish_tasklet);
1001}
1002
c0e55129 1003void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
d129bceb
PO		 1004{
1005 int flags;
fd2208d7 1006 u32 mask;
7cb2c76f 1007 unsigned long timeout;
d129bceb
PO		 1008
1009 WARN_ON(host->cmd);
1010
d129bceb 1011 /* Wait max 10 ms */
7cb2c76f 1012 timeout = 10;
fd2208d7
PO		 1013
1014 mask = SDHCI_CMD_INHIBIT;
1015 if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
1016 mask |= SDHCI_DATA_INHIBIT;
1017
1018 /* We shouldn't wait for data inihibit for stop commands, even
1019 though they might use busy signaling */
1020 if (host->mrq->data && (cmd == host->mrq->data->stop))
1021 mask &= ~SDHCI_DATA_INHIBIT;
1022
4e4141a5 1023 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
7cb2c76f 1024 if (timeout == 0) {
a3c76eb9 1025 pr_err("%s: Controller never released "
acf1da45 1026 "inhibit bit(s).\n", mmc_hostname(host->mmc));
d129bceb 1027 sdhci_dumpregs(host);
17b0429d 1028 cmd->error = -EIO;
d129bceb
PO		 1029 tasklet_schedule(&host->finish_tasklet);
1030 return;
1031 }
7cb2c76f
PO		 1032 timeout--;
1033 mdelay(1);
1034 }
d129bceb 1035
3e1a6892 1036 timeout = jiffies;
1d4d7744
UH		 1037 if (!cmd->data && cmd->busy_timeout > 9000)
1038 timeout += DIV_ROUND_UP(cmd->busy_timeout, 1000) * HZ + HZ;
3e1a6892
AH		 1039 else
1040 timeout += 10 * HZ;
1041 mod_timer(&host->timer, timeout);
d129bceb
PO		 1042
1043 host->cmd = cmd;
e99783a4 1044 host->busy_handle = 0;
d129bceb 1045
a3c7778f 1046 sdhci_prepare_data(host, cmd);
d129bceb 1047
4e4141a5 1048 sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT);
d129bceb 1049
e89d456f 1050 sdhci_set_transfer_mode(host, cmd);
c7fa9963 1051
d129bceb 1052 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
a3c76eb9 1053 pr_err("%s: Unsupported response type!\n",
d129bceb 1054 mmc_hostname(host->mmc));
17b0429d 1055 cmd->error = -EINVAL;
d129bceb
PO		 1056 tasklet_schedule(&host->finish_tasklet);
1057 return;
1058 }
1059
1060 if (!(cmd->flags & MMC_RSP_PRESENT))
1061 flags = SDHCI_CMD_RESP_NONE;
1062 else if (cmd->flags & MMC_RSP_136)
1063 flags = SDHCI_CMD_RESP_LONG;
1064 else if (cmd->flags & MMC_RSP_BUSY)
1065 flags = SDHCI_CMD_RESP_SHORT_BUSY;
1066 else
1067 flags = SDHCI_CMD_RESP_SHORT;
1068
1069 if (cmd->flags & MMC_RSP_CRC)
1070 flags |= SDHCI_CMD_CRC;
1071 if (cmd->flags & MMC_RSP_OPCODE)
1072 flags |= SDHCI_CMD_INDEX;
b513ea25
AN		 1073
1074 /* CMD19 is special in that the Data Present Select should be set */
069c9f14
G		 1075 if (cmd->data || cmd->opcode == MMC_SEND_TUNING_BLOCK ||
1076 cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200)
d129bceb
PO		 1077 flags |= SDHCI_CMD_DATA;
1078
4e4141a5 1079 sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND);
d129bceb 1080}
c0e55129 1081EXPORT_SYMBOL_GPL(sdhci_send_command);
d129bceb
PO		 1082
1083static void sdhci_finish_command(struct sdhci_host *host)
1084{
1085 int i;
1086
1087 BUG_ON(host->cmd == NULL);
1088
1089 if (host->cmd->flags & MMC_RSP_PRESENT) {
1090 if (host->cmd->flags & MMC_RSP_136) {
1091 /* CRC is stripped so we need to do some shifting. */
1092 for (i = 0;i < 4;i++) {
4e4141a5 1093 host->cmd->resp[i] = sdhci_readl(host,
d129bceb
PO		 1094 SDHCI_RESPONSE + (3-i)*4) << 8;
1095 if (i != 3)
1096 host->cmd->resp[i] |=
4e4141a5 1097 sdhci_readb(host,
d129bceb
PO		 1098 SDHCI_RESPONSE + (3-i)*4-1);
1099 }
1100 } else {
4e4141a5 1101 host->cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE);
d129bceb
PO		 1102 }
1103 }
1104
17b0429d 1105 host->cmd->error = 0;
d129bceb 1106
e89d456f
AW		 1107 /* Finished CMD23, now send actual command. */
1108 if (host->cmd == host->mrq->sbc) {
1109 host->cmd = NULL;
1110 sdhci_send_command(host, host->mrq->cmd);
1111 } else {
e538fbe8 1112
e89d456f
AW		 1113 /* Processed actual command. */
1114 if (host->data && host->data_early)
1115 sdhci_finish_data(host);
d129bceb 1116
e89d456f
AW		 1117 if (!host->cmd->data)
1118 tasklet_schedule(&host->finish_tasklet);
1119
1120 host->cmd = NULL;
1121 }
d129bceb
PO		 1122}
1123
52983382
KL		 1124static u16 sdhci_get_preset_value(struct sdhci_host *host)
1125{
d975f121 1126 u16 preset = 0;
52983382 1127
d975f121
RK		 1128 switch (host->timing) {
1129 case MMC_TIMING_UHS_SDR12:
52983382
KL		 1130 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1131 break;
d975f121 1132 case MMC_TIMING_UHS_SDR25:
52983382
KL		 1133 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR25);
1134 break;
d975f121 1135 case MMC_TIMING_UHS_SDR50:
52983382
KL		 1136 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR50);
1137 break;
d975f121
RK		 1138 case MMC_TIMING_UHS_SDR104:
1139 case MMC_TIMING_MMC_HS200:
52983382
KL		 1140 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR104);
1141 break;
d975f121 1142 case MMC_TIMING_UHS_DDR50:
52983382
KL		 1143 preset = sdhci_readw(host, SDHCI_PRESET_FOR_DDR50);
1144 break;
e9fb05d5
AH		 1145 case MMC_TIMING_MMC_HS400:
1146 preset = sdhci_readw(host, SDHCI_PRESET_FOR_HS400);
1147 break;
52983382
KL		 1148 default:
1149 pr_warn("%s: Invalid UHS-I mode selected\n",
1150 mmc_hostname(host->mmc));
1151 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1152 break;
1153 }
1154 return preset;
1155}
1156
1771059c 1157void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
d129bceb 1158{
c3ed3877 1159 int div = 0; /* Initialized for compiler warning */
df16219f 1160 int real_div = div, clk_mul = 1;
c3ed3877 1161 u16 clk = 0;
7cb2c76f 1162 unsigned long timeout;
d129bceb 1163
1650d0c7
RK		 1164 host->mmc->actual_clock = 0;
1165
4e4141a5 1166 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
d129bceb
PO		 1167
1168 if (clock == 0)
373073ef 1169 return;
d129bceb 1170
85105c53 1171 if (host->version >= SDHCI_SPEC_300) {
da91a8f9 1172 if (host->preset_enabled) {
52983382
KL		 1173 u16 pre_val;
1174
1175 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1176 pre_val = sdhci_get_preset_value(host);
1177 div = (pre_val & SDHCI_PRESET_SDCLK_FREQ_MASK)
1178 >> SDHCI_PRESET_SDCLK_FREQ_SHIFT;
1179 if (host->clk_mul &&
1180 (pre_val & SDHCI_PRESET_CLKGEN_SEL_MASK)) {
1181 clk = SDHCI_PROG_CLOCK_MODE;
1182 real_div = div + 1;
1183 clk_mul = host->clk_mul;
1184 } else {
1185 real_div = max_t(int, 1, div << 1);
1186 }
1187 goto clock_set;
1188 }
1189
c3ed3877
AN		 1190 /*
1191 * Check if the Host Controller supports Programmable Clock
1192 * Mode.
1193 */
1194 if (host->clk_mul) {
52983382
KL		 1195 for (div = 1; div <= 1024; div++) {
1196 if ((host->max_clk * host->clk_mul / div)
1197 <= clock)
1198 break;
1199 }
c3ed3877 1200 /*
52983382
KL		 1201 * Set Programmable Clock Mode in the Clock
1202 * Control register.
c3ed3877 1203 */
52983382
KL		 1204 clk = SDHCI_PROG_CLOCK_MODE;
1205 real_div = div;
1206 clk_mul = host->clk_mul;
1207 div--;
c3ed3877
AN		 1208 } else {
1209 /* Version 3.00 divisors must be a multiple of 2. */
1210 if (host->max_clk <= clock)
1211 div = 1;
1212 else {
1213 for (div = 2; div < SDHCI_MAX_DIV_SPEC_300;
1214 div += 2) {
1215 if ((host->max_clk / div) <= clock)
1216 break;
1217 }
85105c53 1218 }
df16219f 1219 real_div = div;
c3ed3877 1220 div >>= 1;
85105c53
ZG		 1221 }
1222 } else {
1223 /* Version 2.00 divisors must be a power of 2. */
0397526d 1224 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
85105c53
ZG		 1225 if ((host->max_clk / div) <= clock)
1226 break;
1227 }
df16219f 1228 real_div = div;
c3ed3877 1229 div >>= 1;
d129bceb 1230 }
d129bceb 1231
52983382 1232clock_set:
03d6f5ff 1233 if (real_div)
df16219f 1234 host->mmc->actual_clock = (host->max_clk * clk_mul) / real_div;
c3ed3877 1235 clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
85105c53
ZG		 1236 clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
1237 << SDHCI_DIVIDER_HI_SHIFT;
d129bceb 1238 clk |= SDHCI_CLOCK_INT_EN;
4e4141a5 1239 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
d129bceb 1240
27f6cb16
CB		 1241 /* Wait max 20 ms */
1242 timeout = 20;
4e4141a5 1243 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
7cb2c76f
PO		 1244 & SDHCI_CLOCK_INT_STABLE)) {
1245 if (timeout == 0) {
a3c76eb9 1246 pr_err("%s: Internal clock never "
acf1da45 1247 "stabilised.\n", mmc_hostname(host->mmc));
d129bceb
PO		 1248 sdhci_dumpregs(host);
1249 return;
1250 }
7cb2c76f
PO		 1251 timeout--;
1252 mdelay(1);
1253 }
d129bceb
PO		 1254
1255 clk |= SDHCI_CLOCK_CARD_EN;
4e4141a5 1256 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
d129bceb 1257}
1771059c 1258EXPORT_SYMBOL_GPL(sdhci_set_clock);
d129bceb 1259
24fbb3ca
RK		 1260static void sdhci_set_power(struct sdhci_host *host, unsigned char mode,
1261 unsigned short vdd)
146ad66e 1262{
3a48edc4 1263 struct mmc_host *mmc = host->mmc;
8364248a 1264 u8 pwr = 0;
146ad66e 1265
52221610
TK		 1266 if (!IS_ERR(mmc->supply.vmmc)) {
1267 spin_unlock_irq(&host->lock);
4e743f1f 1268 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd);
52221610 1269 spin_lock_irq(&host->lock);
3cbc6123
TK		 1270
1271 if (mode != MMC_POWER_OFF)
1272 sdhci_writeb(host, SDHCI_POWER_ON, SDHCI_POWER_CONTROL);
1273 else
1274 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1275
52221610
TK		 1276 return;
1277 }
1278
24fbb3ca
RK		 1279 if (mode != MMC_POWER_OFF) {
1280 switch (1 << vdd) {
ae628903
PO		 1281 case MMC_VDD_165_195:
1282 pwr = SDHCI_POWER_180;
1283 break;
1284 case MMC_VDD_29_30:
1285 case MMC_VDD_30_31:
1286 pwr = SDHCI_POWER_300;
1287 break;
1288 case MMC_VDD_32_33:
1289 case MMC_VDD_33_34:
1290 pwr = SDHCI_POWER_330;
1291 break;
1292 default:
1293 BUG();
1294 }
1295 }
1296
1297 if (host->pwr == pwr)
e921a8b6 1298 return;
146ad66e 1299
ae628903
PO		 1300 host->pwr = pwr;
1301
1302 if (pwr == 0) {
4e4141a5 1303 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
f0710a55
AH		 1304 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
1305 sdhci_runtime_pm_bus_off(host);
24fbb3ca 1306 vdd = 0;
e921a8b6
RK		 1307 } else {
1308 /*
1309 * Spec says that we should clear the power reg before setting
1310 * a new value. Some controllers don't seem to like this though.
1311 */
1312 if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
1313 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
146ad66e 1314
e921a8b6
RK		 1315 /*
1316 * At least the Marvell CaFe chip gets confused if we set the
1317 * voltage and set turn on power at the same time, so set the
1318 * voltage first.
1319 */
1320 if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
1321 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
e08c1694 1322
e921a8b6 1323 pwr |= SDHCI_POWER_ON;
146ad66e 1324
e921a8b6 1325 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
557b0697 1326
e921a8b6
RK		 1327 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
1328 sdhci_runtime_pm_bus_on(host);
f0710a55 1329
e921a8b6
RK		 1330 /*
1331 * Some controllers need an extra 10ms delay of 10ms before
1332 * they can apply clock after applying power
1333 */
1334 if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER)
1335 mdelay(10);
1336 }
146ad66e
PO		 1337}
1338
d129bceb
PO		 1339/*****************************************************************************\
1340 * *
1341 * MMC callbacks *
1342 * *
1343\*****************************************************************************/
1344
1345static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1346{
1347 struct sdhci_host *host;
505a8680 1348 int present;
d129bceb 1349 unsigned long flags;
473b095a 1350 u32 tuning_opcode;
d129bceb
PO		 1351
1352 host = mmc_priv(mmc);
1353
66fd8ad5
AH		 1354 sdhci_runtime_pm_get(host);
1355
2836766a
KK		 1356 present = mmc_gpio_get_cd(host->mmc);
1357
d129bceb
PO		 1358 spin_lock_irqsave(&host->lock, flags);
1359
1360 WARN_ON(host->mrq != NULL);
1361
f9134319 1362#ifndef SDHCI_USE_LEDS_CLASS
d129bceb 1363 sdhci_activate_led(host);
2f730fec 1364#endif
e89d456f
AW		 1365
1366 /*
1367 * Ensure we don't send the STOP for non-SET_BLOCK_COUNTED
1368 * requests if Auto-CMD12 is enabled.
1369 */
1370 if (!mrq->sbc && (host->flags & SDHCI_AUTO_CMD12)) {
c4512f79
JH		 1371 if (mrq->stop) {
1372 mrq->data->stop = NULL;
1373 mrq->stop = NULL;
1374 }
1375 }
d129bceb
PO		 1376
1377 host->mrq = mrq;
1378
505a8680
SG		 1379 /*
1380 * Firstly check card presence from cd-gpio. The return could
1381 * be one of the following possibilities:
1382 * negative: cd-gpio is not available
1383 * zero: cd-gpio is used, and card is removed
1384 * one: cd-gpio is used, and card is present
1385 */
505a8680
SG		 1386 if (present < 0) {
1387 /* If polling, assume that the card is always present. */
1388 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
1389 present = 1;
1390 else
1391 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
1392 SDHCI_CARD_PRESENT;
bec9d4e5
GL		 1393 }
1394
68d1fb7e 1395 if (!present || host->flags & SDHCI_DEVICE_DEAD) {
17b0429d 1396 host->mrq->cmd->error = -ENOMEDIUM;
d129bceb 1397 tasklet_schedule(&host->finish_tasklet);
cf2b5eea
AN		 1398 } else {
1399 u32 present_state;
1400
1401 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
1402 /*
1403 * Check if the re-tuning timer has already expired and there
7756a96d
YS		 1404 * is no on-going data transfer and DAT0 is not busy. If so,
1405 * we need to execute tuning procedure before sending command.
cf2b5eea
AN		 1406 */
1407 if ((host->flags & SDHCI_NEEDS_RETUNING) &&
7756a96d
YS		 1408 !(present_state & (SDHCI_DOING_WRITE | SDHCI_DOING_READ)) &&
1409 (present_state & SDHCI_DATA_0_LVL_MASK)) {
14efd957
CB		 1410 if (mmc->card) {
1411 /* eMMC uses cmd21 but sd and sdio use cmd19 */
1412 tuning_opcode =
1413 mmc->card->type == MMC_TYPE_MMC ?
1414 MMC_SEND_TUNING_BLOCK_HS200 :
1415 MMC_SEND_TUNING_BLOCK;
63c21180
CL		 1416
1417 /* Here we need to set the host->mrq to NULL,
1418 * in case the pending finish_tasklet
1419 * finishes it incorrectly.
1420 */
1421 host->mrq = NULL;
1422
14efd957
CB		 1423 spin_unlock_irqrestore(&host->lock, flags);
1424 sdhci_execute_tuning(mmc, tuning_opcode);
1425 spin_lock_irqsave(&host->lock, flags);
1426
1427 /* Restore original mmc_request structure */
1428 host->mrq = mrq;
1429 }
cf2b5eea
AN		 1430 }
1431
8edf6371 1432 if (mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23))
e89d456f
AW		 1433 sdhci_send_command(host, mrq->sbc);
1434 else
1435 sdhci_send_command(host, mrq->cmd);
cf2b5eea 1436 }
d129bceb 1437
5f25a66f 1438 mmiowb();
d129bceb
PO		 1439 spin_unlock_irqrestore(&host->lock, flags);
1440}
1441
2317f56c
RK		 1442void sdhci_set_bus_width(struct sdhci_host *host, int width)
1443{
1444 u8 ctrl;
1445
1446 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1447 if (width == MMC_BUS_WIDTH_8) {
1448 ctrl &= ~SDHCI_CTRL_4BITBUS;
1449 if (host->version >= SDHCI_SPEC_300)
1450 ctrl |= SDHCI_CTRL_8BITBUS;
1451 } else {
1452 if (host->version >= SDHCI_SPEC_300)
1453 ctrl &= ~SDHCI_CTRL_8BITBUS;
1454 if (width == MMC_BUS_WIDTH_4)
1455 ctrl |= SDHCI_CTRL_4BITBUS;
1456 else
1457 ctrl &= ~SDHCI_CTRL_4BITBUS;
1458 }
1459 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1460}
1461EXPORT_SYMBOL_GPL(sdhci_set_bus_width);
1462
96d7b78c
RK		 1463void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing)
1464{
1465 u16 ctrl_2;
1466
1467 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1468 /* Select Bus Speed Mode for host */
1469 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
1470 if ((timing == MMC_TIMING_MMC_HS200) ||
1471 (timing == MMC_TIMING_UHS_SDR104))
1472 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
1473 else if (timing == MMC_TIMING_UHS_SDR12)
1474 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
1475 else if (timing == MMC_TIMING_UHS_SDR25)
1476 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
1477 else if (timing == MMC_TIMING_UHS_SDR50)
1478 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
1479 else if ((timing == MMC_TIMING_UHS_DDR50) ||
1480 (timing == MMC_TIMING_MMC_DDR52))
1481 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
e9fb05d5
AH		 1482 else if (timing == MMC_TIMING_MMC_HS400)
1483 ctrl_2 |= SDHCI_CTRL_HS400; /* Non-standard */
96d7b78c
RK		 1484 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1485}
1486EXPORT_SYMBOL_GPL(sdhci_set_uhs_signaling);
1487
66fd8ad5 1488static void sdhci_do_set_ios(struct sdhci_host *host, struct mmc_ios *ios)
d129bceb 1489{
d129bceb
PO		 1490 unsigned long flags;
1491 u8 ctrl;
3a48edc4 1492 struct mmc_host *mmc = host->mmc;
d129bceb 1493
d129bceb
PO		 1494 spin_lock_irqsave(&host->lock, flags);
1495
ceb6143b
AH		 1496 if (host->flags & SDHCI_DEVICE_DEAD) {
1497 spin_unlock_irqrestore(&host->lock, flags);
3a48edc4
TK		 1498 if (!IS_ERR(mmc->supply.vmmc) &&
1499 ios->power_mode == MMC_POWER_OFF)
4e743f1f 1500 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
ceb6143b
AH		 1501 return;
1502 }
1e72859e 1503
d129bceb
PO		 1504 /*
1505 * Reset the chip on each power off.
1506 * Should clear out any weird states.
1507 */
1508 if (ios->power_mode == MMC_POWER_OFF) {
4e4141a5 1509 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
7260cf5e 1510 sdhci_reinit(host);
d129bceb
PO		 1511 }
1512
52983382 1513 if (host->version >= SDHCI_SPEC_300 &&
372c4634
DA		 1514 (ios->power_mode == MMC_POWER_UP) &&
1515 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN))
52983382
KL		 1516 sdhci_enable_preset_value(host, false);
1517
373073ef 1518 if (!ios->clock || ios->clock != host->clock) {
1771059c 1519 host->ops->set_clock(host, ios->clock);
373073ef 1520 host->clock = ios->clock;
03d6f5ff
AD		 1521
1522 if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK &&
1523 host->clock) {
1524 host->timeout_clk = host->mmc->actual_clock ?
1525 host->mmc->actual_clock / 1000 :
1526 host->clock / 1000;
1527 host->mmc->max_busy_timeout =
1528 host->ops->get_max_timeout_count ?
1529 host->ops->get_max_timeout_count(host) :
1530 1 << 27;
1531 host->mmc->max_busy_timeout /= host->timeout_clk;
1532 }
373073ef 1533 }
d129bceb 1534
24fbb3ca 1535 sdhci_set_power(host, ios->power_mode, ios->vdd);
d129bceb 1536
643a81ff
PR		 1537 if (host->ops->platform_send_init_74_clocks)
1538 host->ops->platform_send_init_74_clocks(host, ios->power_mode);
1539
2317f56c 1540 host->ops->set_bus_width(host, ios->bus_width);
ae6d6c92 1541
15ec4461 1542 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
cd9277c0 1543
3ab9c8da
PR		 1544 if ((ios->timing == MMC_TIMING_SD_HS ||
1545 ios->timing == MMC_TIMING_MMC_HS)
1546 && !(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT))
cd9277c0
PO		 1547 ctrl |= SDHCI_CTRL_HISPD;
1548 else
1549 ctrl &= ~SDHCI_CTRL_HISPD;
1550
d6d50a15 1551 if (host->version >= SDHCI_SPEC_300) {
49c468fc 1552 u16 clk, ctrl_2;
49c468fc
AN		 1553
1554 /* In case of UHS-I modes, set High Speed Enable */
e9fb05d5
AH		 1555 if ((ios->timing == MMC_TIMING_MMC_HS400) ||
1556 (ios->timing == MMC_TIMING_MMC_HS200) ||
bb8175a8 1557 (ios->timing == MMC_TIMING_MMC_DDR52) ||
069c9f14 1558 (ios->timing == MMC_TIMING_UHS_SDR50) ||
49c468fc
AN		 1559 (ios->timing == MMC_TIMING_UHS_SDR104) ||
1560 (ios->timing == MMC_TIMING_UHS_DDR50) ||
dd8df17f 1561 (ios->timing == MMC_TIMING_UHS_SDR25))
49c468fc 1562 ctrl |= SDHCI_CTRL_HISPD;
d6d50a15 1563
da91a8f9 1564 if (!host->preset_enabled) {
758535c4 1565 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d6d50a15
AN		 1566 /*
1567 * We only need to set Driver Strength if the
1568 * preset value enable is not set.
1569 */
da91a8f9 1570 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
d6d50a15
AN		 1571 ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK;
1572 if (ios->drv_type == MMC_SET_DRIVER_TYPE_A)
1573 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A;
1574 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C)
1575 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C;
1576
1577 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
758535c4
AN		 1578 } else {
1579 /*
1580 * According to SDHC Spec v3.00, if the Preset Value
1581 * Enable in the Host Control 2 register is set, we
1582 * need to reset SD Clock Enable before changing High
1583 * Speed Enable to avoid generating clock gliches.
1584 */
758535c4
AN		 1585
1586 /* Reset SD Clock Enable */
1587 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1588 clk &= ~SDHCI_CLOCK_CARD_EN;
1589 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1590
1591 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1592
1593 /* Re-enable SD Clock */
1771059c 1594 host->ops->set_clock(host, host->clock);
d6d50a15 1595 }
49c468fc 1596
49c468fc
AN		 1597 /* Reset SD Clock Enable */
1598 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1599 clk &= ~SDHCI_CLOCK_CARD_EN;
1600 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1601
96d7b78c 1602 host->ops->set_uhs_signaling(host, ios->timing);
d975f121 1603 host->timing = ios->timing;
49c468fc 1604
52983382
KL		 1605 if (!(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN) &&
1606 ((ios->timing == MMC_TIMING_UHS_SDR12) ||
1607 (ios->timing == MMC_TIMING_UHS_SDR25) ||
1608 (ios->timing == MMC_TIMING_UHS_SDR50) ||
1609 (ios->timing == MMC_TIMING_UHS_SDR104) ||
1610 (ios->timing == MMC_TIMING_UHS_DDR50))) {
1611 u16 preset;
1612
1613 sdhci_enable_preset_value(host, true);
1614 preset = sdhci_get_preset_value(host);
1615 ios->drv_type = (preset & SDHCI_PRESET_DRV_MASK)
1616 >> SDHCI_PRESET_DRV_SHIFT;
1617 }
1618
49c468fc 1619 /* Re-enable SD Clock */
1771059c 1620 host->ops->set_clock(host, host->clock);
758535c4
AN		 1621 } else
1622 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d6d50a15 1623
b8352260
LD		 1624 /*
1625 * Some (ENE) controllers go apeshit on some ios operation,
1626 * signalling timeout and CRC errors even on CMD0. Resetting
1627 * it on each ios seems to solve the problem.
1628 */
b8c86fc5 1629 if(host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
03231f9b 1630 sdhci_do_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
b8352260 1631
5f25a66f 1632 mmiowb();
d129bceb
PO		 1633 spin_unlock_irqrestore(&host->lock, flags);
1634}
1635
66fd8ad5
AH		 1636static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1637{
1638 struct sdhci_host *host = mmc_priv(mmc);
1639
1640 sdhci_runtime_pm_get(host);
1641 sdhci_do_set_ios(host, ios);
1642 sdhci_runtime_pm_put(host);
1643}
1644
94144a46
KL		 1645static int sdhci_do_get_cd(struct sdhci_host *host)
1646{
1647 int gpio_cd = mmc_gpio_get_cd(host->mmc);
1648
1649 if (host->flags & SDHCI_DEVICE_DEAD)
1650 return 0;
1651
1652 /* If polling/nonremovable, assume that the card is always present. */
1653 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) ||
1654 (host->mmc->caps & MMC_CAP_NONREMOVABLE))
1655 return 1;
1656
1657 /* Try slot gpio detect */
1658 if (!IS_ERR_VALUE(gpio_cd))
1659 return !!gpio_cd;
1660
1661 /* Host native card detect */
1662 return !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
1663}
1664
1665static int sdhci_get_cd(struct mmc_host *mmc)
1666{
1667 struct sdhci_host *host = mmc_priv(mmc);
1668 int ret;
1669
1670 sdhci_runtime_pm_get(host);
1671 ret = sdhci_do_get_cd(host);
1672 sdhci_runtime_pm_put(host);
1673 return ret;
1674}
1675
66fd8ad5 1676static int sdhci_check_ro(struct sdhci_host *host)
d129bceb 1677{
d129bceb 1678 unsigned long flags;
2dfb579c 1679 int is_readonly;
d129bceb 1680
d129bceb
PO		 1681 spin_lock_irqsave(&host->lock, flags);
1682
1e72859e 1683 if (host->flags & SDHCI_DEVICE_DEAD)
2dfb579c
WS		 1684 is_readonly = 0;
1685 else if (host->ops->get_ro)
1686 is_readonly = host->ops->get_ro(host);
1e72859e 1687 else
2dfb579c
WS		 1688 is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE)
1689 & SDHCI_WRITE_PROTECT);
d129bceb
PO		 1690
1691 spin_unlock_irqrestore(&host->lock, flags);
1692
2dfb579c
WS		 1693 /* This quirk needs to be replaced by a callback-function later */
1694 return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ?
1695 !is_readonly : is_readonly;
d129bceb
PO		 1696}
1697
82b0e23a
TI		 1698#define SAMPLE_COUNT 5
1699
66fd8ad5 1700static int sdhci_do_get_ro(struct sdhci_host *host)
82b0e23a 1701{
82b0e23a
TI		 1702 int i, ro_count;
1703
82b0e23a 1704 if (!(host->quirks & SDHCI_QUIRK_UNSTABLE_RO_DETECT))
66fd8ad5 1705 return sdhci_check_ro(host);
82b0e23a
TI		 1706
1707 ro_count = 0;
1708 for (i = 0; i < SAMPLE_COUNT; i++) {
66fd8ad5 1709 if (sdhci_check_ro(host)) {
82b0e23a
TI		 1710 if (++ro_count > SAMPLE_COUNT / 2)
1711 return 1;
1712 }
1713 msleep(30);
1714 }
1715 return 0;
1716}
1717
20758b66
AH		 1718static void sdhci_hw_reset(struct mmc_host *mmc)
1719{
1720 struct sdhci_host *host = mmc_priv(mmc);
1721
1722 if (host->ops && host->ops->hw_reset)
1723 host->ops->hw_reset(host);
1724}
1725
66fd8ad5 1726static int sdhci_get_ro(struct mmc_host *mmc)
f75979b7 1727{
66fd8ad5
AH		 1728 struct sdhci_host *host = mmc_priv(mmc);
1729 int ret;
f75979b7 1730
66fd8ad5
AH		 1731 sdhci_runtime_pm_get(host);
1732 ret = sdhci_do_get_ro(host);
1733 sdhci_runtime_pm_put(host);
1734 return ret;
1735}
f75979b7 1736
66fd8ad5
AH		 1737static void sdhci_enable_sdio_irq_nolock(struct sdhci_host *host, int enable)
1738{
be138554 1739 if (!(host->flags & SDHCI_DEVICE_DEAD)) {
ef104333 1740 if (enable)
b537f94c 1741 host->ier |= SDHCI_INT_CARD_INT;
ef104333 1742 else
b537f94c
RK		 1743 host->ier &= ~SDHCI_INT_CARD_INT;
1744
1745 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
1746 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
ef104333
RK		 1747 mmiowb();
1748 }
66fd8ad5
AH		 1749}
1750
1751static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1752{
1753 struct sdhci_host *host = mmc_priv(mmc);
1754 unsigned long flags;
f75979b7 1755
ef104333
RK		 1756 sdhci_runtime_pm_get(host);
1757
66fd8ad5 1758 spin_lock_irqsave(&host->lock, flags);
ef104333
RK		 1759 if (enable)
1760 host->flags |= SDHCI_SDIO_IRQ_ENABLED;
1761 else
1762 host->flags &= ~SDHCI_SDIO_IRQ_ENABLED;
1763
66fd8ad5 1764 sdhci_enable_sdio_irq_nolock(host, enable);
f75979b7 1765 spin_unlock_irqrestore(&host->lock, flags);
ef104333
RK		 1766
1767 sdhci_runtime_pm_put(host);
f75979b7
PO		 1768}
1769
20b92a30 1770static int sdhci_do_start_signal_voltage_switch(struct sdhci_host *host,
21f5998f 1771 struct mmc_ios *ios)
f2119df6 1772{
3a48edc4 1773 struct mmc_host *mmc = host->mmc;
20b92a30 1774 u16 ctrl;
6231f3de 1775 int ret;
f2119df6 1776
20b92a30
KL		 1777 /*
1778 * Signal Voltage Switching is only applicable for Host Controllers
1779 * v3.00 and above.
1780 */
1781 if (host->version < SDHCI_SPEC_300)
1782 return 0;
6231f3de 1783
f2119df6 1784 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
f2119df6 1785
21f5998f 1786 switch (ios->signal_voltage) {
20b92a30
KL		 1787 case MMC_SIGNAL_VOLTAGE_330:
1788 /* Set 1.8V Signal Enable in the Host Control2 register to 0 */
1789 ctrl &= ~SDHCI_CTRL_VDD_180;
1790 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
f2119df6 1791
3a48edc4
TK		 1792 if (!IS_ERR(mmc->supply.vqmmc)) {
1793 ret = regulator_set_voltage(mmc->supply.vqmmc, 2700000,
1794 3600000);
20b92a30 1795 if (ret) {
6606110d
JP		 1796 pr_warn("%s: Switching to 3.3V signalling voltage failed\n",
1797 mmc_hostname(mmc));
20b92a30
KL		 1798 return -EIO;
1799 }
1800 }
1801 /* Wait for 5ms */
1802 usleep_range(5000, 5500);
f2119df6 1803
20b92a30
KL		 1804 /* 3.3V regulator output should be stable within 5 ms */
1805 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1806 if (!(ctrl & SDHCI_CTRL_VDD_180))
1807 return 0;
6231f3de 1808
6606110d
JP		 1809 pr_warn("%s: 3.3V regulator output did not became stable\n",
1810 mmc_hostname(mmc));
20b92a30
KL		 1811
1812 return -EAGAIN;
1813 case MMC_SIGNAL_VOLTAGE_180:
3a48edc4
TK		 1814 if (!IS_ERR(mmc->supply.vqmmc)) {
1815 ret = regulator_set_voltage(mmc->supply.vqmmc,
20b92a30
KL		 1816 1700000, 1950000);
1817 if (ret) {
6606110d
JP		 1818 pr_warn("%s: Switching to 1.8V signalling voltage failed\n",
1819 mmc_hostname(mmc));
20b92a30
KL		 1820 return -EIO;
1821 }
1822 }
6231f3de 1823
6231f3de
PR		 1824 /*
1825 * Enable 1.8V Signal Enable in the Host Control2
1826 * register
1827 */
20b92a30
KL		 1828 ctrl |= SDHCI_CTRL_VDD_180;
1829 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
6231f3de 1830
20b92a30
KL		 1831 /* 1.8V regulator output should be stable within 5 ms */
1832 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1833 if (ctrl & SDHCI_CTRL_VDD_180)
1834 return 0;
f2119df6 1835
6606110d
JP		 1836 pr_warn("%s: 1.8V regulator output did not became stable\n",
1837 mmc_hostname(mmc));
f2119df6 1838
20b92a30
KL		 1839 return -EAGAIN;
1840 case MMC_SIGNAL_VOLTAGE_120:
3a48edc4
TK		 1841 if (!IS_ERR(mmc->supply.vqmmc)) {
1842 ret = regulator_set_voltage(mmc->supply.vqmmc, 1100000,
1843 1300000);
20b92a30 1844 if (ret) {
6606110d
JP		 1845 pr_warn("%s: Switching to 1.2V signalling voltage failed\n",
1846 mmc_hostname(mmc));
20b92a30 1847 return -EIO;
f2119df6
AN		 1848 }
1849 }
6231f3de 1850 return 0;
20b92a30 1851 default:
f2119df6
AN		 1852 /* No signal voltage switch required */
1853 return 0;
20b92a30 1854 }
f2119df6
AN		 1855}
1856
66fd8ad5 1857static int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
21f5998f 1858 struct mmc_ios *ios)
66fd8ad5
AH		 1859{
1860 struct sdhci_host *host = mmc_priv(mmc);
1861 int err;
1862
1863 if (host->version < SDHCI_SPEC_300)
1864 return 0;
1865 sdhci_runtime_pm_get(host);
21f5998f 1866 err = sdhci_do_start_signal_voltage_switch(host, ios);
66fd8ad5
AH		 1867 sdhci_runtime_pm_put(host);
1868 return err;
1869}
1870
20b92a30
KL		 1871static int sdhci_card_busy(struct mmc_host *mmc)
1872{
1873 struct sdhci_host *host = mmc_priv(mmc);
1874 u32 present_state;
1875
1876 sdhci_runtime_pm_get(host);
1877 /* Check whether DAT[3:0] is 0000 */
1878 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
1879 sdhci_runtime_pm_put(host);
1880
1881 return !(present_state & SDHCI_DATA_LVL_MASK);
1882}
1883
b5540ce1
AH		 1884static int sdhci_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios)
1885{
1886 struct sdhci_host *host = mmc_priv(mmc);
1887 unsigned long flags;
1888
1889 spin_lock_irqsave(&host->lock, flags);
1890 host->flags |= SDHCI_HS400_TUNING;
1891 spin_unlock_irqrestore(&host->lock, flags);
1892
1893 return 0;
1894}
1895
069c9f14 1896static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode)
b513ea25 1897{
4b6f37d3 1898 struct sdhci_host *host = mmc_priv(mmc);
b513ea25 1899 u16 ctrl;
b513ea25 1900 int tuning_loop_counter = MAX_TUNING_LOOP;
b513ea25 1901 int err = 0;
2b35bd83 1902 unsigned long flags;
38e40bf5 1903 unsigned int tuning_count = 0;
b5540ce1 1904 bool hs400_tuning;
b513ea25 1905
66fd8ad5 1906 sdhci_runtime_pm_get(host);
2b35bd83 1907 spin_lock_irqsave(&host->lock, flags);
b513ea25 1908
b5540ce1
AH		 1909 hs400_tuning = host->flags & SDHCI_HS400_TUNING;
1910 host->flags &= ~SDHCI_HS400_TUNING;
1911
38e40bf5
AH		 1912 if (host->tuning_mode == SDHCI_TUNING_MODE_1)
1913 tuning_count = host->tuning_count;
1914
b513ea25 1915 /*
069c9f14
G		 1916 * The Host Controller needs tuning only in case of SDR104 mode
1917 * and for SDR50 mode when Use Tuning for SDR50 is set in the
b513ea25 1918 * Capabilities register.
069c9f14
G		 1919 * If the Host Controller supports the HS200 mode then the
1920 * tuning function has to be executed.
b513ea25 1921 */
4b6f37d3 1922 switch (host->timing) {
b5540ce1 1923 /* HS400 tuning is done in HS200 mode */
e9fb05d5 1924 case MMC_TIMING_MMC_HS400:
b5540ce1
AH		 1925 err = -EINVAL;
1926 goto out_unlock;
1927
4b6f37d3 1928 case MMC_TIMING_MMC_HS200:
b5540ce1
AH		 1929 /*
1930 * Periodic re-tuning for HS400 is not expected to be needed, so
1931 * disable it here.
1932 */
1933 if (hs400_tuning)
1934 tuning_count = 0;
1935 break;
1936
4b6f37d3
RK		 1937 case MMC_TIMING_UHS_SDR104:
1938 break;
1939
1940 case MMC_TIMING_UHS_SDR50:
1941 if (host->flags & SDHCI_SDR50_NEEDS_TUNING ||
1942 host->flags & SDHCI_SDR104_NEEDS_TUNING)
1943 break;
1944 /* FALLTHROUGH */
1945
1946 default:
d519c863 1947 goto out_unlock;
b513ea25
AN		 1948 }
1949
45251812 1950 if (host->ops->platform_execute_tuning) {
2b35bd83 1951 spin_unlock_irqrestore(&host->lock, flags);
45251812
DA		 1952 err = host->ops->platform_execute_tuning(host, opcode);
1953 sdhci_runtime_pm_put(host);
1954 return err;
1955 }
1956
4b6f37d3
RK		 1957 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1958 ctrl |= SDHCI_CTRL_EXEC_TUNING;
b513ea25
AN		 1959 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1960
1961 /*
1962 * As per the Host Controller spec v3.00, tuning command
1963 * generates Buffer Read Ready interrupt, so enable that.
1964 *
1965 * Note: The spec clearly says that when tuning sequence
1966 * is being performed, the controller does not generate
1967 * interrupts other than Buffer Read Ready interrupt. But
1968 * to make sure we don't hit a controller bug, we _only_
1969 * enable Buffer Read Ready interrupt here.
1970 */
b537f94c
RK		 1971 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE);
1972 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE);
b513ea25
AN		 1973
1974 /*
1975 * Issue CMD19 repeatedly till Execute Tuning is set to 0 or the number
1976 * of loops reaches 40 times or a timeout of 150ms occurs.
1977 */
b513ea25
AN		 1978 do {
1979 struct mmc_command cmd = {0};
66fd8ad5 1980 struct mmc_request mrq = {NULL};
b513ea25 1981
069c9f14 1982 cmd.opcode = opcode;
b513ea25
AN		 1983 cmd.arg = 0;
1984 cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
1985 cmd.retries = 0;
1986 cmd.data = NULL;
1987 cmd.error = 0;
1988
7ce45e95
AC		 1989 if (tuning_loop_counter-- == 0)
1990 break;
1991
b513ea25
AN		 1992 mrq.cmd = &cmd;
1993 host->mrq = &mrq;
1994
1995 /*
1996 * In response to CMD19, the card sends 64 bytes of tuning
1997 * block to the Host Controller. So we set the block size
1998 * to 64 here.
1999 */
069c9f14
G		 2000 if (cmd.opcode == MMC_SEND_TUNING_BLOCK_HS200) {
2001 if (mmc->ios.bus_width == MMC_BUS_WIDTH_8)
2002 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 128),
2003 SDHCI_BLOCK_SIZE);
2004 else if (mmc->ios.bus_width == MMC_BUS_WIDTH_4)
2005 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
2006 SDHCI_BLOCK_SIZE);
2007 } else {
2008 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
2009 SDHCI_BLOCK_SIZE);
2010 }
b513ea25
AN		 2011
2012 /*
2013 * The tuning block is sent by the card to the host controller.
2014 * So we set the TRNS_READ bit in the Transfer Mode register.
2015 * This also takes care of setting DMA Enable and Multi Block
2016 * Select in the same register to 0.
2017 */
2018 sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
2019
2020 sdhci_send_command(host, &cmd);
2021
2022 host->cmd = NULL;
2023 host->mrq = NULL;
2024
2b35bd83 2025 spin_unlock_irqrestore(&host->lock, flags);
b513ea25
AN		 2026 /* Wait for Buffer Read Ready interrupt */
2027 wait_event_interruptible_timeout(host->buf_ready_int,
2028 (host->tuning_done == 1),
2029 msecs_to_jiffies(50));
2b35bd83 2030 spin_lock_irqsave(&host->lock, flags);
b513ea25
AN		 2031
2032 if (!host->tuning_done) {
a3c76eb9 2033 pr_info(DRIVER_NAME ": Timeout waiting for "
b513ea25
AN		 2034 "Buffer Read Ready interrupt during tuning "
2035 "procedure, falling back to fixed sampling "
2036 "clock\n");
2037 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2038 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
2039 ctrl &= ~SDHCI_CTRL_EXEC_TUNING;
2040 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2041
2042 err = -EIO;
2043 goto out;
2044 }
2045
2046 host->tuning_done = 0;
2047
2048 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
197160d5
NS		 2049
2050 /* eMMC spec does not require a delay between tuning cycles */
2051 if (opcode == MMC_SEND_TUNING_BLOCK)
2052 mdelay(1);
b513ea25
AN		 2053 } while (ctrl & SDHCI_CTRL_EXEC_TUNING);
2054
2055 /*
2056 * The Host Driver has exhausted the maximum number of loops allowed,
2057 * so use fixed sampling frequency.
2058 */
7ce45e95 2059 if (tuning_loop_counter < 0) {
b513ea25
AN		 2060 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
2061 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
7ce45e95
AC		 2062 }
2063 if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) {
2064 pr_info(DRIVER_NAME ": Tuning procedure"
2065 " failed, falling back to fixed sampling"
2066 " clock\n");
114f2bf6 2067 err = -EIO;
b513ea25
AN		 2068 }
2069
2070out:
38e40bf5
AH		 2071 host->flags &= ~SDHCI_NEEDS_RETUNING;
2072
2073 if (tuning_count) {
973905fe 2074 host->flags |= SDHCI_USING_RETUNING_TIMER;
38e40bf5 2075 mod_timer(&host->tuning_timer, jiffies + tuning_count * HZ);
cf2b5eea
AN		 2076 }
2077
2078 /*
2079 * In case tuning fails, host controllers which support re-tuning can
2080 * try tuning again at a later time, when the re-tuning timer expires.
2081 * So for these controllers, we return 0. Since there might be other
2082 * controllers who do not have this capability, we return error for
973905fe
AL		 2083 * them. SDHCI_USING_RETUNING_TIMER means the host is currently using
2084 * a retuning timer to do the retuning for the card.
cf2b5eea 2085 */
973905fe 2086 if (err && (host->flags & SDHCI_USING_RETUNING_TIMER))
cf2b5eea
AN		 2087 err = 0;
2088
b537f94c
RK		 2089 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2090 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
d519c863 2091out_unlock:
2b35bd83 2092 spin_unlock_irqrestore(&host->lock, flags);
66fd8ad5 2093 sdhci_runtime_pm_put(host);
b513ea25
AN		 2094
2095 return err;
2096}
2097
52983382
KL		 2098
2099static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable)
4d55c5a1 2100{
4d55c5a1
AN		 2101 /* Host Controller v3.00 defines preset value registers */
2102 if (host->version < SDHCI_SPEC_300)
2103 return;
2104
4d55c5a1
AN		 2105 /*
2106 * We only enable or disable Preset Value if they are not already
2107 * enabled or disabled respectively. Otherwise, we bail out.
2108 */
da91a8f9
RK		 2109 if (host->preset_enabled != enable) {
2110 u16 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2111
2112 if (enable)
2113 ctrl |= SDHCI_CTRL_PRESET_VAL_ENABLE;
2114 else
2115 ctrl &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
2116
4d55c5a1 2117 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
da91a8f9
RK		 2118
2119 if (enable)
2120 host->flags |= SDHCI_PV_ENABLED;
2121 else
2122 host->flags &= ~SDHCI_PV_ENABLED;
2123
2124 host->preset_enabled = enable;
4d55c5a1 2125 }
66fd8ad5
AH		 2126}
2127
71e69211 2128static void sdhci_card_event(struct mmc_host *mmc)
d129bceb 2129{
71e69211 2130 struct sdhci_host *host = mmc_priv(mmc);
d129bceb 2131 unsigned long flags;
2836766a 2132 int present;
d129bceb 2133
722e1280
CD		 2134 /* First check if client has provided their own card event */
2135 if (host->ops->card_event)
2136 host->ops->card_event(host);
2137
2836766a
KK		 2138 present = sdhci_do_get_cd(host);
2139
d129bceb
PO		 2140 spin_lock_irqsave(&host->lock, flags);
2141
66fd8ad5 2142 /* Check host->mrq first in case we are runtime suspended */
2836766a 2143 if (host->mrq && !present) {
a3c76eb9 2144 pr_err("%s: Card removed during transfer!\n",
66fd8ad5 2145 mmc_hostname(host->mmc));
a3c76eb9 2146 pr_err("%s: Resetting controller.\n",
66fd8ad5 2147 mmc_hostname(host->mmc));
d129bceb 2148
03231f9b
RK		 2149 sdhci_do_reset(host, SDHCI_RESET_CMD);
2150 sdhci_do_reset(host, SDHCI_RESET_DATA);
d129bceb 2151
66fd8ad5
AH		 2152 host->mrq->cmd->error = -ENOMEDIUM;
2153 tasklet_schedule(&host->finish_tasklet);
d129bceb
PO		 2154 }
2155
2156 spin_unlock_irqrestore(&host->lock, flags);
71e69211
GL		 2157}
2158
2159static const struct mmc_host_ops sdhci_ops = {
2160 .request = sdhci_request,
2161 .set_ios = sdhci_set_ios,
94144a46 2162 .get_cd = sdhci_get_cd,
71e69211
GL		 2163 .get_ro = sdhci_get_ro,
2164 .hw_reset = sdhci_hw_reset,
2165 .enable_sdio_irq = sdhci_enable_sdio_irq,
2166 .start_signal_voltage_switch = sdhci_start_signal_voltage_switch,
b5540ce1 2167 .prepare_hs400_tuning = sdhci_prepare_hs400_tuning,
71e69211 2168 .execute_tuning = sdhci_execute_tuning,
71e69211 2169 .card_event = sdhci_card_event,
20b92a30 2170 .card_busy = sdhci_card_busy,
71e69211
GL		 2171};
2172
2173/*****************************************************************************\
2174 * *
2175 * Tasklets *
2176 * *
2177\*****************************************************************************/
2178
d129bceb
PO		 2179static void sdhci_tasklet_finish(unsigned long param)
2180{
2181 struct sdhci_host *host;
2182 unsigned long flags;
2183 struct mmc_request *mrq;
2184
2185 host = (struct sdhci_host*)param;
2186
66fd8ad5
AH		 2187 spin_lock_irqsave(&host->lock, flags);
2188
0c9c99a7
CB		 2189 /*
2190 * If this tasklet gets rescheduled while running, it will
2191 * be run again afterwards but without any active request.
2192 */
66fd8ad5
AH		 2193 if (!host->mrq) {
2194 spin_unlock_irqrestore(&host->lock, flags);
0c9c99a7 2195 return;
66fd8ad5 2196 }
d129bceb
PO		 2197
2198 del_timer(&host->timer);
2199
2200 mrq = host->mrq;
2201
d129bceb
PO		 2202 /*
2203 * The controller needs a reset of internal state machines
2204 * upon error conditions.
2205 */
1e72859e 2206 if (!(host->flags & SDHCI_DEVICE_DEAD) &&
b7b4d342 2207 ((mrq->cmd && mrq->cmd->error) ||
fce9d33f
AG		 2208 (mrq->sbc && mrq->sbc->error) ||
2209 (mrq->data && ((mrq->data->error && !mrq->data->stop) ||
2210 (mrq->data->stop && mrq->data->stop->error))) ||
2211 (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) {
645289dc
PO		 2212
2213 /* Some controllers need this kick or reset won't work here */
8213af3b 2214 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)
645289dc 2215 /* This is to force an update */
1771059c 2216 host->ops->set_clock(host, host->clock);
645289dc
PO		 2217
2218 /* Spec says we should do both at the same time, but Ricoh
2219 controllers do not like that. */
03231f9b
RK		 2220 sdhci_do_reset(host, SDHCI_RESET_CMD);
2221 sdhci_do_reset(host, SDHCI_RESET_DATA);
d129bceb
PO		 2222 }
2223
2224 host->mrq = NULL;
2225 host->cmd = NULL;
2226 host->data = NULL;
2227
f9134319 2228#ifndef SDHCI_USE_LEDS_CLASS
d129bceb 2229 sdhci_deactivate_led(host);
2f730fec 2230#endif
d129bceb 2231
5f25a66f 2232 mmiowb();
d129bceb
PO		 2233 spin_unlock_irqrestore(&host->lock, flags);
2234
2235 mmc_request_done(host->mmc, mrq);
66fd8ad5 2236 sdhci_runtime_pm_put(host);
d129bceb
PO		 2237}
2238
2239static void sdhci_timeout_timer(unsigned long data)
2240{
2241 struct sdhci_host *host;
2242 unsigned long flags;
2243
2244 host = (struct sdhci_host*)data;
2245
2246 spin_lock_irqsave(&host->lock, flags);
2247
2248 if (host->mrq) {
a3c76eb9 2249 pr_err("%s: Timeout waiting for hardware "
acf1da45 2250 "interrupt.\n", mmc_hostname(host->mmc));
d129bceb
PO		 2251 sdhci_dumpregs(host);
2252
2253 if (host->data) {
17b0429d 2254 host->data->error = -ETIMEDOUT;
d129bceb
PO		 2255 sdhci_finish_data(host);
2256 } else {
2257 if (host->cmd)
17b0429d 2258 host->cmd->error = -ETIMEDOUT;
d129bceb 2259 else
17b0429d 2260 host->mrq->cmd->error = -ETIMEDOUT;
d129bceb
PO		 2261
2262 tasklet_schedule(&host->finish_tasklet);
2263 }
2264 }
2265
5f25a66f 2266 mmiowb();
d129bceb
PO		 2267 spin_unlock_irqrestore(&host->lock, flags);
2268}
2269
cf2b5eea
AN		 2270static void sdhci_tuning_timer(unsigned long data)
2271{
2272 struct sdhci_host *host;
2273 unsigned long flags;
2274
2275 host = (struct sdhci_host *)data;
2276
2277 spin_lock_irqsave(&host->lock, flags);
2278
2279 host->flags |= SDHCI_NEEDS_RETUNING;
2280
2281 spin_unlock_irqrestore(&host->lock, flags);
2282}
2283
d129bceb
PO		 2284/*****************************************************************************\
2285 * *
2286 * Interrupt handling *
2287 * *
2288\*****************************************************************************/
2289
61541397 2290static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask, u32 *mask)
d129bceb
PO		 2291{
2292 BUG_ON(intmask == 0);
2293
2294 if (!host->cmd) {
a3c76eb9 2295 pr_err("%s: Got command interrupt 0x%08x even "
b67ac3f3
PO		 2296 "though no command operation was in progress.\n",
2297 mmc_hostname(host->mmc), (unsigned)intmask);
d129bceb
PO		 2298 sdhci_dumpregs(host);
2299 return;
2300 }
2301
43b58b36 2302 if (intmask & SDHCI_INT_TIMEOUT)
17b0429d
PO		 2303 host->cmd->error = -ETIMEDOUT;
2304 else if (intmask & (SDHCI_INT_CRC | SDHCI_INT_END_BIT |
2305 SDHCI_INT_INDEX))
2306 host->cmd->error = -EILSEQ;
43b58b36 2307
e809517f 2308 if (host->cmd->error) {
d129bceb 2309 tasklet_schedule(&host->finish_tasklet);
e809517f
PO		 2310 return;
2311 }
2312
2313 /*
2314 * The host can send and interrupt when the busy state has
2315 * ended, allowing us to wait without wasting CPU cycles.
2316 * Unfortunately this is overloaded on the "data complete"
2317 * interrupt, so we need to take some care when handling
2318 * it.
2319 *
2320 * Note: The 1.0 specification is a bit ambiguous about this
2321 * feature so there might be some problems with older
2322 * controllers.
2323 */
2324 if (host->cmd->flags & MMC_RSP_BUSY) {
2325 if (host->cmd->data)
2326 DBG("Cannot wait for busy signal when also "
2327 "doing a data transfer");
e99783a4
CM		 2328 else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ)
2329 && !host->busy_handle) {
2330 /* Mark that command complete before busy is ended */
2331 host->busy_handle = 1;
e809517f 2332 return;
e99783a4 2333 }
f945405c
BD		 2334
2335 /* The controller does not support the end-of-busy IRQ,
2336 * fall through and take the SDHCI_INT_RESPONSE */
61541397
AH		 2337 } else if ((host->quirks2 & SDHCI_QUIRK2_STOP_WITH_TC) &&
2338 host->cmd->opcode == MMC_STOP_TRANSMISSION && !host->data) {
2339 *mask &= ~SDHCI_INT_DATA_END;
e809517f
PO		 2340 }
2341
2342 if (intmask & SDHCI_INT_RESPONSE)
43b58b36 2343 sdhci_finish_command(host);
d129bceb
PO		 2344}
2345
0957c333 2346#ifdef CONFIG_MMC_DEBUG
08621b18 2347static void sdhci_adma_show_error(struct sdhci_host *host)
6882a8c0
BD		 2348{
2349 const char *name = mmc_hostname(host->mmc);
1c3d5f6d 2350 void *desc = host->adma_table;
6882a8c0
BD		 2351
2352 sdhci_dumpregs(host);
2353
2354 while (true) {
e57a5f61
AH		 2355 struct sdhci_adma2_64_desc *dma_desc = desc;
2356
2357 if (host->flags & SDHCI_USE_64_BIT_DMA)
2358 DBG("%s: %p: DMA 0x%08x%08x, LEN 0x%04x, Attr=0x%02x\n",
2359 name, desc, le32_to_cpu(dma_desc->addr_hi),
2360 le32_to_cpu(dma_desc->addr_lo),
2361 le16_to_cpu(dma_desc->len),
2362 le16_to_cpu(dma_desc->cmd));
2363 else
2364 DBG("%s: %p: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n",
2365 name, desc, le32_to_cpu(dma_desc->addr_lo),
2366 le16_to_cpu(dma_desc->len),
2367 le16_to_cpu(dma_desc->cmd));
6882a8c0 2368
76fe379a 2369 desc += host->desc_sz;
6882a8c0 2370
0545230f 2371 if (dma_desc->cmd & cpu_to_le16(ADMA2_END))
6882a8c0
BD		 2372 break;
2373 }
2374}
2375#else
08621b18 2376static void sdhci_adma_show_error(struct sdhci_host *host) { }
6882a8c0
BD		 2377#endif
2378
d129bceb
PO		 2379static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
2380{
069c9f14 2381 u32 command;
d129bceb
PO		 2382 BUG_ON(intmask == 0);
2383
b513ea25
AN		 2384 /* CMD19 generates _only_ Buffer Read Ready interrupt */
2385 if (intmask & SDHCI_INT_DATA_AVAIL) {
069c9f14
G		 2386 command = SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND));
2387 if (command == MMC_SEND_TUNING_BLOCK ||
2388 command == MMC_SEND_TUNING_BLOCK_HS200) {
b513ea25
AN		 2389 host->tuning_done = 1;
2390 wake_up(&host->buf_ready_int);
2391 return;
2392 }
2393 }
2394
d129bceb
PO		 2395 if (!host->data) {
2396 /*
e809517f
PO		 2397 * The "data complete" interrupt is also used to
2398 * indicate that a busy state has ended. See comment
2399 * above in sdhci_cmd_irq().
d129bceb 2400 */
e809517f 2401 if (host->cmd && (host->cmd->flags & MMC_RSP_BUSY)) {
c5abd5e8
MC		 2402 if (intmask & SDHCI_INT_DATA_TIMEOUT) {
2403 host->cmd->error = -ETIMEDOUT;
2404 tasklet_schedule(&host->finish_tasklet);
2405 return;
2406 }
e809517f 2407 if (intmask & SDHCI_INT_DATA_END) {
e99783a4
CM		 2408 /*
2409 * Some cards handle busy-end interrupt
2410 * before the command completed, so make
2411 * sure we do things in the proper order.
2412 */
2413 if (host->busy_handle)
2414 sdhci_finish_command(host);
2415 else
2416 host->busy_handle = 1;
e809517f
PO		 2417 return;
2418 }
2419 }
d129bceb 2420
a3c76eb9 2421 pr_err("%s: Got data interrupt 0x%08x even "
b67ac3f3
PO		 2422 "though no data operation was in progress.\n",
2423 mmc_hostname(host->mmc), (unsigned)intmask);
d129bceb
PO		 2424 sdhci_dumpregs(host);
2425
2426 return;
2427 }
2428
2429 if (intmask & SDHCI_INT_DATA_TIMEOUT)
17b0429d 2430 host->data->error = -ETIMEDOUT;
22113efd
AL		 2431 else if (intmask & SDHCI_INT_DATA_END_BIT)
2432 host->data->error = -EILSEQ;
2433 else if ((intmask & SDHCI_INT_DATA_CRC) &&
2434 SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))
2435 != MMC_BUS_TEST_R)
17b0429d 2436 host->data->error = -EILSEQ;
6882a8c0 2437 else if (intmask & SDHCI_INT_ADMA_ERROR) {
a3c76eb9 2438 pr_err("%s: ADMA error\n", mmc_hostname(host->mmc));
08621b18 2439 sdhci_adma_show_error(host);
2134a922 2440 host->data->error = -EIO;
a4071fbb
HZ		 2441 if (host->ops->adma_workaround)
2442 host->ops->adma_workaround(host, intmask);
6882a8c0 2443 }
d129bceb 2444
17b0429d 2445 if (host->data->error)
d129bceb
PO		 2446 sdhci_finish_data(host);
2447 else {
a406f5a3 2448 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
d129bceb
PO		 2449 sdhci_transfer_pio(host);
2450
6ba736a1
PO		 2451 /*
2452 * We currently don't do anything fancy with DMA
2453 * boundaries, but as we can't disable the feature
2454 * we need to at least restart the transfer.
f6a03cbf
MV		 2455 *
2456 * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS)
2457 * should return a valid address to continue from, but as
2458 * some controllers are faulty, don't trust them.
6ba736a1 2459 */
f6a03cbf
MV		 2460 if (intmask & SDHCI_INT_DMA_END) {
2461 u32 dmastart, dmanow;
2462 dmastart = sg_dma_address(host->data->sg);
2463 dmanow = dmastart + host->data->bytes_xfered;
2464 /*
2465 * Force update to the next DMA block boundary.
2466 */
2467 dmanow = (dmanow &
2468 ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) +
2469 SDHCI_DEFAULT_BOUNDARY_SIZE;
2470 host->data->bytes_xfered = dmanow - dmastart;
2471 DBG("%s: DMA base 0x%08x, transferred 0x%06x bytes,"
2472 " next 0x%08x\n",
2473 mmc_hostname(host->mmc), dmastart,
2474 host->data->bytes_xfered, dmanow);
2475 sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS);
2476 }
6ba736a1 2477
e538fbe8
PO		 2478 if (intmask & SDHCI_INT_DATA_END) {
2479 if (host->cmd) {
2480 /*
2481 * Data managed to finish before the
2482 * command completed. Make sure we do
2483 * things in the proper order.
2484 */
2485 host->data_early = 1;
2486 } else {
2487 sdhci_finish_data(host);
2488 }
2489 }
d129bceb
PO		 2490 }
2491}
2492
7d12e780 2493static irqreturn_t sdhci_irq(int irq, void *dev_id)
d129bceb 2494{
781e989c 2495 irqreturn_t result = IRQ_NONE;
66fd8ad5 2496 struct sdhci_host *host = dev_id;
41005003 2497 u32 intmask, mask, unexpected = 0;
781e989c 2498 int max_loops = 16;
d129bceb
PO		 2499
2500 spin_lock(&host->lock);
2501
be138554 2502 if (host->runtime_suspended && !sdhci_sdio_irq_enabled(host)) {
66fd8ad5 2503 spin_unlock(&host->lock);
655bca76 2504 return IRQ_NONE;
66fd8ad5
AH		 2505 }
2506
4e4141a5 2507 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
62df67a5 2508 if (!intmask || intmask == 0xffffffff) {
d129bceb
PO		 2509 result = IRQ_NONE;
2510 goto out;
2511 }
2512
41005003
RK		 2513 do {
2514 /* Clear selected interrupts. */
2515 mask = intmask & (SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
2516 SDHCI_INT_BUS_POWER);
2517 sdhci_writel(host, mask, SDHCI_INT_STATUS);
d129bceb 2518
41005003
RK		 2519 DBG("*** %s got interrupt: 0x%08x\n",
2520 mmc_hostname(host->mmc), intmask);
d129bceb 2521
41005003
RK		 2522 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
2523 u32 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
2524 SDHCI_CARD_PRESENT;
d129bceb 2525
41005003
RK		 2526 /*
2527 * There is a observation on i.mx esdhc. INSERT
2528 * bit will be immediately set again when it gets
2529 * cleared, if a card is inserted. We have to mask
2530 * the irq to prevent interrupt storm which will
2531 * freeze the system. And the REMOVE gets the
2532 * same situation.
2533 *
2534 * More testing are needed here to ensure it works
2535 * for other platforms though.
2536 */
b537f94c
RK		 2537 host->ier &= ~(SDHCI_INT_CARD_INSERT |
2538 SDHCI_INT_CARD_REMOVE);
2539 host->ier |= present ? SDHCI_INT_CARD_REMOVE :
2540 SDHCI_INT_CARD_INSERT;
2541 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2542 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
41005003
RK		 2543
2544 sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT |
2545 SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS);
3560db8e
RK		 2546
2547 host->thread_isr |= intmask & (SDHCI_INT_CARD_INSERT |
2548 SDHCI_INT_CARD_REMOVE);
2549 result = IRQ_WAKE_THREAD;
41005003 2550 }
d129bceb 2551
41005003 2552 if (intmask & SDHCI_INT_CMD_MASK)
61541397
AH		 2553 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK,
2554 &intmask);
964f9ce2 2555
41005003
RK		 2556 if (intmask & SDHCI_INT_DATA_MASK)
2557 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
d129bceb 2558
41005003
RK		 2559 if (intmask & SDHCI_INT_BUS_POWER)
2560 pr_err("%s: Card is consuming too much power!\n",
2561 mmc_hostname(host->mmc));
3192a28f 2562
781e989c
RK		 2563 if (intmask & SDHCI_INT_CARD_INT) {
2564 sdhci_enable_sdio_irq_nolock(host, false);
2565 host->thread_isr |= SDHCI_INT_CARD_INT;
2566 result = IRQ_WAKE_THREAD;
2567 }
f75979b7 2568
41005003
RK		 2569 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE |
2570 SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
2571 SDHCI_INT_ERROR | SDHCI_INT_BUS_POWER |
2572 SDHCI_INT_CARD_INT);
f75979b7 2573
41005003
RK		 2574 if (intmask) {
2575 unexpected |= intmask;
2576 sdhci_writel(host, intmask, SDHCI_INT_STATUS);
2577 }
d129bceb 2578
781e989c
RK		 2579 if (result == IRQ_NONE)
2580 result = IRQ_HANDLED;
d129bceb 2581
41005003 2582 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
41005003 2583 } while (intmask && --max_loops);
d129bceb
PO		 2584out:
2585 spin_unlock(&host->lock);
2586
6379b237
AS		 2587 if (unexpected) {
2588 pr_err("%s: Unexpected interrupt 0x%08x.\n",
2589 mmc_hostname(host->mmc), unexpected);
2590 sdhci_dumpregs(host);
2591 }
f75979b7 2592
d129bceb
PO		 2593 return result;
2594}
2595
781e989c
RK		 2596static irqreturn_t sdhci_thread_irq(int irq, void *dev_id)
2597{
2598 struct sdhci_host *host = dev_id;
2599 unsigned long flags;
2600 u32 isr;
2601
2602 spin_lock_irqsave(&host->lock, flags);
2603 isr = host->thread_isr;
2604 host->thread_isr = 0;
2605 spin_unlock_irqrestore(&host->lock, flags);
2606
3560db8e
RK		 2607 if (isr & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
2608 sdhci_card_event(host->mmc);
2609 mmc_detect_change(host->mmc, msecs_to_jiffies(200));
2610 }
2611
781e989c
RK		 2612 if (isr & SDHCI_INT_CARD_INT) {
2613 sdio_run_irqs(host->mmc);
2614
2615 spin_lock_irqsave(&host->lock, flags);
2616 if (host->flags & SDHCI_SDIO_IRQ_ENABLED)
2617 sdhci_enable_sdio_irq_nolock(host, true);
2618 spin_unlock_irqrestore(&host->lock, flags);
2619 }
2620
2621 return isr ? IRQ_HANDLED : IRQ_NONE;
2622}
2623
d129bceb
PO		 2624/*****************************************************************************\
2625 * *
2626 * Suspend/resume *
2627 * *
2628\*****************************************************************************/
2629
2630#ifdef CONFIG_PM
ad080d79
KL		 2631void sdhci_enable_irq_wakeups(struct sdhci_host *host)
2632{
2633 u8 val;
2634 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
2635 | SDHCI_WAKE_ON_INT;
2636
2637 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2638 val |= mask ;
2639 /* Avoid fake wake up */
2640 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
2641 val &= ~(SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE);
2642 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2643}
2644EXPORT_SYMBOL_GPL(sdhci_enable_irq_wakeups);
2645
0b10f478 2646static void sdhci_disable_irq_wakeups(struct sdhci_host *host)
ad080d79
KL		 2647{
2648 u8 val;
2649 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
2650 | SDHCI_WAKE_ON_INT;
2651
2652 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2653 val &= ~mask;
2654 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2655}
d129bceb 2656
29495aa0 2657int sdhci_suspend_host(struct sdhci_host *host)
d129bceb 2658{
7260cf5e
AV		 2659 sdhci_disable_card_detection(host);
2660
cf2b5eea 2661 /* Disable tuning since we are suspending */
973905fe 2662 if (host->flags & SDHCI_USING_RETUNING_TIMER) {
c6ced0db 2663 del_timer_sync(&host->tuning_timer);
cf2b5eea 2664 host->flags &= ~SDHCI_NEEDS_RETUNING;
cf2b5eea
AN		 2665 }
2666
ad080d79 2667 if (!device_may_wakeup(mmc_dev(host->mmc))) {
b537f94c
RK		 2668 host->ier = 0;
2669 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
2670 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
ad080d79
KL		 2671 free_irq(host->irq, host);
2672 } else {
2673 sdhci_enable_irq_wakeups(host);
2674 enable_irq_wake(host->irq);
2675 }
4ee14ec6 2676 return 0;
d129bceb
PO		 2677}
2678
b8c86fc5 2679EXPORT_SYMBOL_GPL(sdhci_suspend_host);
d129bceb 2680
b8c86fc5
PO		 2681int sdhci_resume_host(struct sdhci_host *host)
2682{
4ee14ec6 2683 int ret = 0;
d129bceb 2684
a13abc7b 2685 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
b8c86fc5
PO		 2686 if (host->ops->enable_dma)
2687 host->ops->enable_dma(host);
2688 }
d129bceb 2689
ad080d79 2690 if (!device_may_wakeup(mmc_dev(host->mmc))) {
781e989c
RK		 2691 ret = request_threaded_irq(host->irq, sdhci_irq,
2692 sdhci_thread_irq, IRQF_SHARED,
2693 mmc_hostname(host->mmc), host);
ad080d79
KL		 2694 if (ret)
2695 return ret;
2696 } else {
2697 sdhci_disable_irq_wakeups(host);
2698 disable_irq_wake(host->irq);
2699 }
d129bceb 2700
6308d290
AH		 2701 if ((host->mmc->pm_flags & MMC_PM_KEEP_POWER) &&
2702 (host->quirks2 & SDHCI_QUIRK2_HOST_OFF_CARD_ON)) {
2703 /* Card keeps power but host controller does not */
2704 sdhci_init(host, 0);
2705 host->pwr = 0;
2706 host->clock = 0;
2707 sdhci_do_set_ios(host, &host->mmc->ios);
2708 } else {
2709 sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER));
2710 mmiowb();
2711 }
b8c86fc5 2712
7260cf5e
AV		 2713 sdhci_enable_card_detection(host);
2714
cf2b5eea 2715 /* Set the re-tuning expiration flag */
973905fe 2716 if (host->flags & SDHCI_USING_RETUNING_TIMER)
cf2b5eea
AN		 2717 host->flags |= SDHCI_NEEDS_RETUNING;
2718
2f4cbb3d 2719 return ret;
d129bceb
PO		 2720}
2721
b8c86fc5 2722EXPORT_SYMBOL_GPL(sdhci_resume_host);
66fd8ad5
AH		 2723
2724static int sdhci_runtime_pm_get(struct sdhci_host *host)
2725{
2726 return pm_runtime_get_sync(host->mmc->parent);
2727}
2728
2729static int sdhci_runtime_pm_put(struct sdhci_host *host)
2730{
2731 pm_runtime_mark_last_busy(host->mmc->parent);
2732 return pm_runtime_put_autosuspend(host->mmc->parent);
2733}
2734
f0710a55
AH		 2735static void sdhci_runtime_pm_bus_on(struct sdhci_host *host)
2736{
2737 if (host->runtime_suspended || host->bus_on)
2738 return;
2739 host->bus_on = true;
2740 pm_runtime_get_noresume(host->mmc->parent);
2741}
2742
2743static void sdhci_runtime_pm_bus_off(struct sdhci_host *host)
2744{
2745 if (host->runtime_suspended || !host->bus_on)
2746 return;
2747 host->bus_on = false;
2748 pm_runtime_put_noidle(host->mmc->parent);
2749}
2750
66fd8ad5
AH		 2751int sdhci_runtime_suspend_host(struct sdhci_host *host)
2752{
2753 unsigned long flags;
66fd8ad5
AH		 2754
2755 /* Disable tuning since we are suspending */
973905fe 2756 if (host->flags & SDHCI_USING_RETUNING_TIMER) {
66fd8ad5
AH		 2757 del_timer_sync(&host->tuning_timer);
2758 host->flags &= ~SDHCI_NEEDS_RETUNING;
2759 }
2760
2761 spin_lock_irqsave(&host->lock, flags);
b537f94c
RK		 2762 host->ier &= SDHCI_INT_CARD_INT;
2763 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2764 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
66fd8ad5
AH		 2765 spin_unlock_irqrestore(&host->lock, flags);
2766
781e989c 2767 synchronize_hardirq(host->irq);
66fd8ad5
AH		 2768
2769 spin_lock_irqsave(&host->lock, flags);
2770 host->runtime_suspended = true;
2771 spin_unlock_irqrestore(&host->lock, flags);
2772
8a125bad 2773 return 0;
66fd8ad5
AH		 2774}
2775EXPORT_SYMBOL_GPL(sdhci_runtime_suspend_host);
2776
2777int sdhci_runtime_resume_host(struct sdhci_host *host)
2778{
2779 unsigned long flags;
8a125bad 2780 int host_flags = host->flags;
66fd8ad5
AH		 2781
2782 if (host_flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2783 if (host->ops->enable_dma)
2784 host->ops->enable_dma(host);
2785 }
2786
2787 sdhci_init(host, 0);
2788
2789 /* Force clock and power re-program */
2790 host->pwr = 0;
2791 host->clock = 0;
2792 sdhci_do_set_ios(host, &host->mmc->ios);
2793
2794 sdhci_do_start_signal_voltage_switch(host, &host->mmc->ios);
52983382
KL		 2795 if ((host_flags & SDHCI_PV_ENABLED) &&
2796 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN)) {
2797 spin_lock_irqsave(&host->lock, flags);
2798 sdhci_enable_preset_value(host, true);
2799 spin_unlock_irqrestore(&host->lock, flags);
2800 }
66fd8ad5
AH		 2801
2802 /* Set the re-tuning expiration flag */
973905fe 2803 if (host->flags & SDHCI_USING_RETUNING_TIMER)
66fd8ad5
AH		 2804 host->flags |= SDHCI_NEEDS_RETUNING;
2805
2806 spin_lock_irqsave(&host->lock, flags);
2807
2808 host->runtime_suspended = false;
2809
2810 /* Enable SDIO IRQ */
ef104333 2811 if (host->flags & SDHCI_SDIO_IRQ_ENABLED)
66fd8ad5
AH		 2812 sdhci_enable_sdio_irq_nolock(host, true);
2813
2814 /* Enable Card Detection */
2815 sdhci_enable_card_detection(host);
2816
2817 spin_unlock_irqrestore(&host->lock, flags);
2818
8a125bad 2819 return 0;
66fd8ad5
AH		 2820}
2821EXPORT_SYMBOL_GPL(sdhci_runtime_resume_host);
2822
162d6f98 2823#endif /* CONFIG_PM */
66fd8ad5 2824
d129bceb
PO		 2825/*****************************************************************************\
2826 * *
b8c86fc5 2827 * Device allocation/registration *
d129bceb
PO		 2828 * *
2829\*****************************************************************************/
2830
b8c86fc5
PO		 2831struct sdhci_host *sdhci_alloc_host(struct device *dev,
2832 size_t priv_size)
d129bceb 2833{
d129bceb
PO		 2834 struct mmc_host *mmc;
2835 struct sdhci_host *host;
2836
b8c86fc5 2837 WARN_ON(dev == NULL);
d129bceb 2838
b8c86fc5 2839 mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev);
d129bceb 2840 if (!mmc)
b8c86fc5 2841 return ERR_PTR(-ENOMEM);
d129bceb
PO		 2842
2843 host = mmc_priv(mmc);
2844 host->mmc = mmc;
2845
b8c86fc5
PO		 2846 return host;
2847}
8a4da143 2848
b8c86fc5 2849EXPORT_SYMBOL_GPL(sdhci_alloc_host);
d129bceb 2850
b8c86fc5
PO		 2851int sdhci_add_host(struct sdhci_host *host)
2852{
2853 struct mmc_host *mmc;
bd6a8c30 2854 u32 caps[2] = {0, 0};
f2119df6
AN		 2855 u32 max_current_caps;
2856 unsigned int ocr_avail;
f5fa92e5 2857 unsigned int override_timeout_clk;
b8c86fc5 2858 int ret;
d129bceb 2859
b8c86fc5
PO		 2860 WARN_ON(host == NULL);
2861 if (host == NULL)
2862 return -EINVAL;
d129bceb 2863
b8c86fc5 2864 mmc = host->mmc;
d129bceb 2865
b8c86fc5
PO		 2866 if (debug_quirks)
2867 host->quirks = debug_quirks;
66fd8ad5
AH		 2868 if (debug_quirks2)
2869 host->quirks2 = debug_quirks2;
d129bceb 2870
f5fa92e5
AH		 2871 override_timeout_clk = host->timeout_clk;
2872
03231f9b 2873 sdhci_do_reset(host, SDHCI_RESET_ALL);
d96649ed 2874
4e4141a5 2875 host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
2134a922
PO		 2876 host->version = (host->version & SDHCI_SPEC_VER_MASK)
2877 >> SDHCI_SPEC_VER_SHIFT;
85105c53 2878 if (host->version > SDHCI_SPEC_300) {
a3c76eb9 2879 pr_err("%s: Unknown controller version (%d). "
b69c9058 2880 "You may experience problems.\n", mmc_hostname(mmc),
2134a922 2881 host->version);
4a965505
PO		 2882 }
2883
f2119df6 2884 caps[0] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ? host->caps :
ccc92c23 2885 sdhci_readl(host, SDHCI_CAPABILITIES);
d129bceb 2886
bd6a8c30
PR		 2887 if (host->version >= SDHCI_SPEC_300)
2888 caps[1] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ?
2889 host->caps1 :
2890 sdhci_readl(host, SDHCI_CAPABILITIES_1);
f2119df6 2891
b8c86fc5 2892 if (host->quirks & SDHCI_QUIRK_FORCE_DMA)
a13abc7b 2893 host->flags |= SDHCI_USE_SDMA;
f2119df6 2894 else if (!(caps[0] & SDHCI_CAN_DO_SDMA))
a13abc7b 2895 DBG("Controller doesn't have SDMA capability\n");
67435274 2896 else
a13abc7b 2897 host->flags |= SDHCI_USE_SDMA;
d129bceb 2898
b8c86fc5 2899 if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
a13abc7b 2900 (host->flags & SDHCI_USE_SDMA)) {
cee687ce 2901 DBG("Disabling DMA as it is marked broken\n");
a13abc7b 2902 host->flags &= ~SDHCI_USE_SDMA;
7c168e3d
FT		 2903 }
2904
f2119df6
AN		 2905 if ((host->version >= SDHCI_SPEC_200) &&
2906 (caps[0] & SDHCI_CAN_DO_ADMA2))
a13abc7b 2907 host->flags |= SDHCI_USE_ADMA;
2134a922
PO		 2908
2909 if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) &&
2910 (host->flags & SDHCI_USE_ADMA)) {
2911 DBG("Disabling ADMA as it is marked broken\n");
2912 host->flags &= ~SDHCI_USE_ADMA;
2913 }
2914
e57a5f61
AH		 2915 /*
2916 * It is assumed that a 64-bit capable device has set a 64-bit DMA mask
2917 * and *must* do 64-bit DMA. A driver has the opportunity to change
2918 * that during the first call to ->enable_dma(). Similarly
2919 * SDHCI_QUIRK2_BROKEN_64_BIT_DMA must be left to the drivers to
2920 * implement.
2921 */
2922 if (sdhci_readl(host, SDHCI_CAPABILITIES) & SDHCI_CAN_64BIT)
2923 host->flags |= SDHCI_USE_64_BIT_DMA;
2924
a13abc7b 2925 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
b8c86fc5
PO		 2926 if (host->ops->enable_dma) {
2927 if (host->ops->enable_dma(host)) {
6606110d 2928 pr_warn("%s: No suitable DMA available - falling back to PIO\n",
b8c86fc5 2929 mmc_hostname(mmc));
a13abc7b
RR		 2930 host->flags &=
2931 ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
b8c86fc5 2932 }
d129bceb
PO		 2933 }
2934 }
2935
e57a5f61
AH		 2936 /* SDMA does not support 64-bit DMA */
2937 if (host->flags & SDHCI_USE_64_BIT_DMA)
2938 host->flags &= ~SDHCI_USE_SDMA;
2939
2134a922
PO		 2940 if (host->flags & SDHCI_USE_ADMA) {
2941 /*
76fe379a
AH		 2942 * The DMA descriptor table size is calculated as the maximum
2943 * number of segments times 2, to allow for an alignment
2944 * descriptor for each segment, plus 1 for a nop end descriptor,
2945 * all multipled by the descriptor size.
2134a922 2946 */
e57a5f61
AH		 2947 if (host->flags & SDHCI_USE_64_BIT_DMA) {
2948 host->adma_table_sz = (SDHCI_MAX_SEGS * 2 + 1) *
2949 SDHCI_ADMA2_64_DESC_SZ;
2950 host->align_buffer_sz = SDHCI_MAX_SEGS *
2951 SDHCI_ADMA2_64_ALIGN;
2952 host->desc_sz = SDHCI_ADMA2_64_DESC_SZ;
2953 host->align_sz = SDHCI_ADMA2_64_ALIGN;
2954 host->align_mask = SDHCI_ADMA2_64_ALIGN - 1;
2955 } else {
2956 host->adma_table_sz = (SDHCI_MAX_SEGS * 2 + 1) *
2957 SDHCI_ADMA2_32_DESC_SZ;
2958 host->align_buffer_sz = SDHCI_MAX_SEGS *
2959 SDHCI_ADMA2_32_ALIGN;
2960 host->desc_sz = SDHCI_ADMA2_32_DESC_SZ;
2961 host->align_sz = SDHCI_ADMA2_32_ALIGN;
2962 host->align_mask = SDHCI_ADMA2_32_ALIGN - 1;
2963 }
4efaa6fb 2964 host->adma_table = dma_alloc_coherent(mmc_dev(mmc),
76fe379a 2965 host->adma_table_sz,
4efaa6fb
AH		 2966 &host->adma_addr,
2967 GFP_KERNEL);
76fe379a 2968 host->align_buffer = kmalloc(host->align_buffer_sz, GFP_KERNEL);
4efaa6fb 2969 if (!host->adma_table || !host->align_buffer) {
76fe379a 2970 dma_free_coherent(mmc_dev(mmc), host->adma_table_sz,
4efaa6fb 2971 host->adma_table, host->adma_addr);
2134a922 2972 kfree(host->align_buffer);
6606110d 2973 pr_warn("%s: Unable to allocate ADMA buffers - falling back to standard DMA\n",
2134a922
PO		 2974 mmc_hostname(mmc));
2975 host->flags &= ~SDHCI_USE_ADMA;
4efaa6fb 2976 host->adma_table = NULL;
d1e49f77 2977 host->align_buffer = NULL;
76fe379a 2978 } else if (host->adma_addr & host->align_mask) {
6606110d
JP		 2979 pr_warn("%s: unable to allocate aligned ADMA descriptor\n",
2980 mmc_hostname(mmc));
d1e49f77 2981 host->flags &= ~SDHCI_USE_ADMA;
76fe379a 2982 dma_free_coherent(mmc_dev(mmc), host->adma_table_sz,
4efaa6fb 2983 host->adma_table, host->adma_addr);
d1e49f77 2984 kfree(host->align_buffer);
4efaa6fb 2985 host->adma_table = NULL;
d1e49f77 2986 host->align_buffer = NULL;
2134a922
PO		 2987 }
2988 }
2989
7659150c
PO		 2990 /*
2991 * If we use DMA, then it's up to the caller to set the DMA
2992 * mask, but PIO does not need the hw shim so we set a new
2993 * mask here in that case.
2994 */
a13abc7b 2995 if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) {
7659150c 2996 host->dma_mask = DMA_BIT_MASK(64);
4e743f1f 2997 mmc_dev(mmc)->dma_mask = &host->dma_mask;
7659150c 2998 }
d129bceb 2999
c4687d5f 3000 if (host->version >= SDHCI_SPEC_300)
f2119df6 3001 host->max_clk = (caps[0] & SDHCI_CLOCK_V3_BASE_MASK)
c4687d5f
ZG		 3002 >> SDHCI_CLOCK_BASE_SHIFT;
3003 else
f2119df6 3004 host->max_clk = (caps[0] & SDHCI_CLOCK_BASE_MASK)
c4687d5f
ZG		 3005 >> SDHCI_CLOCK_BASE_SHIFT;
3006
4240ff0a 3007 host->max_clk *= 1000000;
f27f47ef
AV		 3008 if (host->max_clk == 0 || host->quirks &
3009 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) {
4240ff0a 3010 if (!host->ops->get_max_clock) {
a3c76eb9 3011 pr_err("%s: Hardware doesn't specify base clock "
4240ff0a
BD		 3012 "frequency.\n", mmc_hostname(mmc));
3013 return -ENODEV;
3014 }
3015 host->max_clk = host->ops->get_max_clock(host);
8ef1a143 3016 }
d129bceb 3017
c3ed3877
AN		 3018 /*
3019 * In case of Host Controller v3.00, find out whether clock
3020 * multiplier is supported.
3021 */
3022 host->clk_mul = (caps[1] & SDHCI_CLOCK_MUL_MASK) >>
3023 SDHCI_CLOCK_MUL_SHIFT;
3024
3025 /*
3026 * In case the value in Clock Multiplier is 0, then programmable
3027 * clock mode is not supported, otherwise the actual clock
3028 * multiplier is one more than the value of Clock Multiplier
3029 * in the Capabilities Register.
3030 */
3031 if (host->clk_mul)
3032 host->clk_mul += 1;
3033
d129bceb
PO		 3034 /*
3035 * Set host parameters.
3036 */
3037 mmc->ops = &sdhci_ops;
c3ed3877 3038 mmc->f_max = host->max_clk;
ce5f036b 3039 if (host->ops->get_min_clock)
a9e58f25 3040 mmc->f_min = host->ops->get_min_clock(host);
c3ed3877
AN		 3041 else if (host->version >= SDHCI_SPEC_300) {
3042 if (host->clk_mul) {
3043 mmc->f_min = (host->max_clk * host->clk_mul) / 1024;
3044 mmc->f_max = host->max_clk * host->clk_mul;
3045 } else
3046 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300;
3047 } else
0397526d 3048 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200;
15ec4461 3049
28aab053
AD		 3050 if (!(host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) {
3051 host->timeout_clk = (caps[0] & SDHCI_TIMEOUT_CLK_MASK) >>
3052 SDHCI_TIMEOUT_CLK_SHIFT;
3053 if (host->timeout_clk == 0) {
3054 if (host->ops->get_timeout_clock) {
3055 host->timeout_clk =
3056 host->ops->get_timeout_clock(host);
3057 } else {
3058 pr_err("%s: Hardware doesn't specify timeout clock frequency.\n",
3059 mmc_hostname(mmc));
3060 return -ENODEV;
3061 }
272308ca 3062 }
272308ca 3063
28aab053
AD		 3064 if (caps[0] & SDHCI_TIMEOUT_CLK_UNIT)
3065 host->timeout_clk *= 1000;
272308ca 3066
28aab053 3067 mmc->max_busy_timeout = host->ops->get_max_timeout_count ?
a6ff5aeb 3068 host->ops->get_max_timeout_count(host) : 1 << 27;
28aab053
AD		 3069 mmc->max_busy_timeout /= host->timeout_clk;
3070 }
58d1246d 3071
f5fa92e5
AH		 3072 if (override_timeout_clk)
3073 host->timeout_clk = override_timeout_clk;
3074
e89d456f 3075 mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_ERASE | MMC_CAP_CMD23;
781e989c 3076 mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD;
e89d456f
AW		 3077
3078 if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12)
3079 host->flags |= SDHCI_AUTO_CMD12;
5fe23c7f 3080
8edf6371 3081 /* Auto-CMD23 stuff only works in ADMA or PIO. */
4f3d3e9b 3082 if ((host->version >= SDHCI_SPEC_300) &&
8edf6371 3083 ((host->flags & SDHCI_USE_ADMA) ||
4f3d3e9b 3084 !(host->flags & SDHCI_USE_SDMA))) {
8edf6371
AW		 3085 host->flags |= SDHCI_AUTO_CMD23;
3086 DBG("%s: Auto-CMD23 available\n", mmc_hostname(mmc));
3087 } else {
3088 DBG("%s: Auto-CMD23 unavailable\n", mmc_hostname(mmc));
3089 }
3090
15ec4461
PR		 3091 /*
3092 * A controller may support 8-bit width, but the board itself
3093 * might not have the pins brought out. Boards that support
3094 * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in
3095 * their platform code before calling sdhci_add_host(), and we
3096 * won't assume 8-bit width for hosts without that CAP.
3097 */
5fe23c7f 3098 if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA))
15ec4461 3099 mmc->caps |= MMC_CAP_4_BIT_DATA;
d129bceb 3100
63ef5d8c
JH		 3101 if (host->quirks2 & SDHCI_QUIRK2_HOST_NO_CMD23)
3102 mmc->caps &= ~MMC_CAP_CMD23;
3103
f2119df6 3104 if (caps[0] & SDHCI_CAN_DO_HISPD)
a29e7e18 3105 mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
cd9277c0 3106
176d1ed4 3107 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) &&
4e743f1f 3108 !(mmc->caps & MMC_CAP_NONREMOVABLE))
68d1fb7e
AV		 3109 mmc->caps |= MMC_CAP_NEEDS_POLL;
3110
3a48edc4
TK		 3111 /* If there are external regulators, get them */
3112 if (mmc_regulator_get_supply(mmc) == -EPROBE_DEFER)
3113 return -EPROBE_DEFER;
3114
6231f3de 3115 /* If vqmmc regulator and no 1.8V signalling, then there's no UHS */
3a48edc4
TK		 3116 if (!IS_ERR(mmc->supply.vqmmc)) {
3117 ret = regulator_enable(mmc->supply.vqmmc);
3118 if (!regulator_is_supported_voltage(mmc->supply.vqmmc, 1700000,
3119 1950000))
8363c374
KL		 3120 caps[1] &= ~(SDHCI_SUPPORT_SDR104 |
3121 SDHCI_SUPPORT_SDR50 |
3122 SDHCI_SUPPORT_DDR50);
a3361aba
CB		 3123 if (ret) {
3124 pr_warn("%s: Failed to enable vqmmc regulator: %d\n",
3125 mmc_hostname(mmc), ret);
4bb74313 3126 mmc->supply.vqmmc = ERR_PTR(-EINVAL);
a3361aba 3127 }
8363c374 3128 }
6231f3de 3129
6a66180a
DD		 3130 if (host->quirks2 & SDHCI_QUIRK2_NO_1_8_V)
3131 caps[1] &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
3132 SDHCI_SUPPORT_DDR50);
3133
4188bba0
AC		 3134 /* Any UHS-I mode in caps implies SDR12 and SDR25 support. */
3135 if (caps[1] & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
3136 SDHCI_SUPPORT_DDR50))
f2119df6
AN		 3137 mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;
3138
3139 /* SDR104 supports also implies SDR50 support */
156e14b1 3140 if (caps[1] & SDHCI_SUPPORT_SDR104) {
f2119df6 3141 mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50;
156e14b1
GC		 3142 /* SD3.0: SDR104 is supported so (for eMMC) the caps2
3143 * field can be promoted to support HS200.
3144 */
549c0b18 3145 if (!(host->quirks2 & SDHCI_QUIRK2_BROKEN_HS200))
13868bf2 3146 mmc->caps2 |= MMC_CAP2_HS200;
156e14b1 3147 } else if (caps[1] & SDHCI_SUPPORT_SDR50)
f2119df6
AN		 3148 mmc->caps |= MMC_CAP_UHS_SDR50;
3149
e9fb05d5
AH		 3150 if (host->quirks2 & SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 &&
3151 (caps[1] & SDHCI_SUPPORT_HS400))
3152 mmc->caps2 |= MMC_CAP2_HS400;
3153
549c0b18
AH		 3154 if ((mmc->caps2 & MMC_CAP2_HSX00_1_2V) &&
3155 (IS_ERR(mmc->supply.vqmmc) ||
3156 !regulator_is_supported_voltage(mmc->supply.vqmmc, 1100000,
3157 1300000)))
3158 mmc->caps2 &= ~MMC_CAP2_HSX00_1_2V;
3159
9107ebbf
MC		 3160 if ((caps[1] & SDHCI_SUPPORT_DDR50) &&
3161 !(host->quirks2 & SDHCI_QUIRK2_BROKEN_DDR50))
f2119df6
AN		 3162 mmc->caps |= MMC_CAP_UHS_DDR50;
3163
069c9f14 3164 /* Does the host need tuning for SDR50? */
b513ea25
AN		 3165 if (caps[1] & SDHCI_USE_SDR50_TUNING)
3166 host->flags |= SDHCI_SDR50_NEEDS_TUNING;
3167
156e14b1 3168 /* Does the host need tuning for SDR104 / HS200? */
069c9f14 3169 if (mmc->caps2 & MMC_CAP2_HS200)
156e14b1 3170 host->flags |= SDHCI_SDR104_NEEDS_TUNING;
069c9f14 3171
d6d50a15
AN		 3172 /* Driver Type(s) (A, C, D) supported by the host */
3173 if (caps[1] & SDHCI_DRIVER_TYPE_A)
3174 mmc->caps |= MMC_CAP_DRIVER_TYPE_A;
3175 if (caps[1] & SDHCI_DRIVER_TYPE_C)
3176 mmc->caps |= MMC_CAP_DRIVER_TYPE_C;
3177 if (caps[1] & SDHCI_DRIVER_TYPE_D)
3178 mmc->caps |= MMC_CAP_DRIVER_TYPE_D;
3179
cf2b5eea
AN		 3180 /* Initial value for re-tuning timer count */
3181 host->tuning_count = (caps[1] & SDHCI_RETUNING_TIMER_COUNT_MASK) >>
3182 SDHCI_RETUNING_TIMER_COUNT_SHIFT;
3183
3184 /*
3185 * In case Re-tuning Timer is not disabled, the actual value of
3186 * re-tuning timer will be 2 ^ (n - 1).
3187 */
3188 if (host->tuning_count)
3189 host->tuning_count = 1 << (host->tuning_count - 1);
3190
3191 /* Re-tuning mode supported by the Host Controller */
3192 host->tuning_mode = (caps[1] & SDHCI_RETUNING_MODE_MASK) >>
3193 SDHCI_RETUNING_MODE_SHIFT;
3194
8f230f45 3195 ocr_avail = 0;
bad37e1a 3196
f2119df6
AN		 3197 /*
3198 * According to SD Host Controller spec v3.00, if the Host System
3199 * can afford more than 150mA, Host Driver should set XPC to 1. Also
3200 * the value is meaningful only if Voltage Support in the Capabilities
3201 * register is set. The actual current value is 4 times the register
3202 * value.
3203 */
3204 max_current_caps = sdhci_readl(host, SDHCI_MAX_CURRENT);
3a48edc4 3205 if (!max_current_caps && !IS_ERR(mmc->supply.vmmc)) {
ae906037 3206 int curr = regulator_get_current_limit(mmc->supply.vmmc);
bad37e1a
PR		 3207 if (curr > 0) {
3208
3209 /* convert to SDHCI_MAX_CURRENT format */
3210 curr = curr/1000; /* convert to mA */
3211 curr = curr/SDHCI_MAX_CURRENT_MULTIPLIER;
3212
3213 curr = min_t(u32, curr, SDHCI_MAX_CURRENT_LIMIT);
3214 max_current_caps =
3215 (curr << SDHCI_MAX_CURRENT_330_SHIFT) |
3216 (curr << SDHCI_MAX_CURRENT_300_SHIFT) |
3217 (curr << SDHCI_MAX_CURRENT_180_SHIFT);
3218 }
3219 }
f2119df6
AN		 3220
3221 if (caps[0] & SDHCI_CAN_VDD_330) {
8f230f45 3222 ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34;
f2119df6 3223
55c4665e 3224 mmc->max_current_330 = ((max_current_caps &
f2119df6
AN		 3225 SDHCI_MAX_CURRENT_330_MASK) >>
3226 SDHCI_MAX_CURRENT_330_SHIFT) *
3227 SDHCI_MAX_CURRENT_MULTIPLIER;
f2119df6
AN		 3228 }
3229 if (caps[0] & SDHCI_CAN_VDD_300) {
8f230f45 3230 ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31;
f2119df6 3231
55c4665e 3232 mmc->max_current_300 = ((max_current_caps &
f2119df6
AN		 3233 SDHCI_MAX_CURRENT_300_MASK) >>
3234 SDHCI_MAX_CURRENT_300_SHIFT) *
3235 SDHCI_MAX_CURRENT_MULTIPLIER;
f2119df6
AN		 3236 }
3237 if (caps[0] & SDHCI_CAN_VDD_180) {
8f230f45
TI		 3238 ocr_avail |= MMC_VDD_165_195;
3239
55c4665e 3240 mmc->max_current_180 = ((max_current_caps &
f2119df6
AN		 3241 SDHCI_MAX_CURRENT_180_MASK) >>
3242 SDHCI_MAX_CURRENT_180_SHIFT) *
3243 SDHCI_MAX_CURRENT_MULTIPLIER;
f2119df6
AN		 3244 }
3245
52221610 3246 /* If OCR set by external regulators, use it instead */
3a48edc4 3247 if (mmc->ocr_avail)
52221610 3248 ocr_avail = mmc->ocr_avail;
3a48edc4 3249
c0b887b6 3250 if (host->ocr_mask)
3a48edc4 3251 ocr_avail &= host->ocr_mask;
c0b887b6 3252
8f230f45
TI		 3253 mmc->ocr_avail = ocr_avail;
3254 mmc->ocr_avail_sdio = ocr_avail;
3255 if (host->ocr_avail_sdio)
3256 mmc->ocr_avail_sdio &= host->ocr_avail_sdio;
3257 mmc->ocr_avail_sd = ocr_avail;
3258 if (host->ocr_avail_sd)
3259 mmc->ocr_avail_sd &= host->ocr_avail_sd;
3260 else /* normal SD controllers don't support 1.8V */
3261 mmc->ocr_avail_sd &= ~MMC_VDD_165_195;
3262 mmc->ocr_avail_mmc = ocr_avail;
3263 if (host->ocr_avail_mmc)
3264 mmc->ocr_avail_mmc &= host->ocr_avail_mmc;
146ad66e
PO		 3265
3266 if (mmc->ocr_avail == 0) {
a3c76eb9 3267 pr_err("%s: Hardware doesn't report any "
b69c9058 3268 "support voltages.\n", mmc_hostname(mmc));
b8c86fc5 3269 return -ENODEV;
146ad66e
PO		 3270 }
3271
d129bceb
PO		 3272 spin_lock_init(&host->lock);
3273
3274 /*
2134a922
PO		 3275 * Maximum number of segments. Depends on if the hardware
3276 * can do scatter/gather or not.
d129bceb 3277 */
2134a922 3278 if (host->flags & SDHCI_USE_ADMA)
4fb213f8 3279 mmc->max_segs = SDHCI_MAX_SEGS;
a13abc7b 3280 else if (host->flags & SDHCI_USE_SDMA)
a36274e0 3281 mmc->max_segs = 1;
2134a922 3282 else /* PIO */
4fb213f8 3283 mmc->max_segs = SDHCI_MAX_SEGS;
d129bceb
PO		 3284
3285 /*
ac00531d
AH		 3286 * Maximum number of sectors in one transfer. Limited by SDMA boundary
3287 * size (512KiB). Note some tuning modes impose a 4MiB limit, but this
3288 * is less anyway.
d129bceb 3289 */
55db890a 3290 mmc->max_req_size = 524288;
d129bceb
PO		 3291
3292 /*
3293 * Maximum segment size. Could be one segment with the maximum number
2134a922
PO		 3294 * of bytes. When doing hardware scatter/gather, each entry cannot
3295 * be larger than 64 KiB though.
d129bceb 3296 */
30652aa3
OJ		 3297 if (host->flags & SDHCI_USE_ADMA) {
3298 if (host->quirks & SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC)
3299 mmc->max_seg_size = 65535;
3300 else
3301 mmc->max_seg_size = 65536;
3302 } else {
2134a922 3303 mmc->max_seg_size = mmc->max_req_size;
30652aa3 3304 }
d129bceb 3305
fe4a3c7a
PO		 3306 /*
3307 * Maximum block size. This varies from controller to controller and
3308 * is specified in the capabilities register.
3309 */
0633f654
AV		 3310 if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) {
3311 mmc->max_blk_size = 2;
3312 } else {
f2119df6 3313 mmc->max_blk_size = (caps[0] & SDHCI_MAX_BLOCK_MASK) >>
0633f654
AV		 3314 SDHCI_MAX_BLOCK_SHIFT;
3315 if (mmc->max_blk_size >= 3) {
6606110d
JP		 3316 pr_warn("%s: Invalid maximum block size, assuming 512 bytes\n",
3317 mmc_hostname(mmc));
0633f654
AV		 3318 mmc->max_blk_size = 0;
3319 }
3320 }
3321
3322 mmc->max_blk_size = 512 << mmc->max_blk_size;
fe4a3c7a 3323
55db890a
PO		 3324 /*
3325 * Maximum block count.
3326 */
1388eefd 3327 mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
55db890a 3328
d129bceb
PO		 3329 /*
3330 * Init tasklets.
3331 */
d129bceb
PO		 3332 tasklet_init(&host->finish_tasklet,
3333 sdhci_tasklet_finish, (unsigned long)host);
3334
e4cad1b5 3335 setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host);
d129bceb 3336
cf2b5eea 3337 if (host->version >= SDHCI_SPEC_300) {
b513ea25
AN		 3338 init_waitqueue_head(&host->buf_ready_int);
3339
cf2b5eea
AN		 3340 /* Initialize re-tuning timer */
3341 init_timer(&host->tuning_timer);
3342 host->tuning_timer.data = (unsigned long)host;
3343 host->tuning_timer.function = sdhci_tuning_timer;
3344 }
3345
2af502ca
SG		 3346 sdhci_init(host, 0);
3347
781e989c
RK		 3348 ret = request_threaded_irq(host->irq, sdhci_irq, sdhci_thread_irq,
3349 IRQF_SHARED, mmc_hostname(mmc), host);
0fc81ee3
MB		 3350 if (ret) {
3351 pr_err("%s: Failed to request IRQ %d: %d\n",
3352 mmc_hostname(mmc), host->irq, ret);
8ef1a143 3353 goto untasklet;
0fc81ee3 3354 }
d129bceb 3355
d129bceb
PO		 3356#ifdef CONFIG_MMC_DEBUG
3357 sdhci_dumpregs(host);
3358#endif
3359
f9134319 3360#ifdef SDHCI_USE_LEDS_CLASS
5dbace0c
HS		 3361 snprintf(host->led_name, sizeof(host->led_name),
3362 "%s::", mmc_hostname(mmc));
3363 host->led.name = host->led_name;
2f730fec
PO		 3364 host->led.brightness = LED_OFF;
3365 host->led.default_trigger = mmc_hostname(mmc);
3366 host->led.brightness_set = sdhci_led_control;
3367
b8c86fc5 3368 ret = led_classdev_register(mmc_dev(mmc), &host->led);
0fc81ee3
MB		 3369 if (ret) {
3370 pr_err("%s: Failed to register LED device: %d\n",
3371 mmc_hostname(mmc), ret);
2f730fec 3372 goto reset;
0fc81ee3 3373 }
2f730fec
PO		 3374#endif
3375
5f25a66f
PO		 3376 mmiowb();
3377
d129bceb
PO		 3378 mmc_add_host(mmc);
3379
a3c76eb9 3380 pr_info("%s: SDHCI controller on %s [%s] using %s\n",
d1b26863 3381 mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)),
e57a5f61
AH		 3382 (host->flags & SDHCI_USE_ADMA) ?
3383 (host->flags & SDHCI_USE_64_BIT_DMA) ? "ADMA 64-bit" : "ADMA" :
a13abc7b 3384 (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO");
d129bceb 3385
7260cf5e
AV		 3386 sdhci_enable_card_detection(host);
3387
d129bceb
PO		 3388 return 0;
3389
f9134319 3390#ifdef SDHCI_USE_LEDS_CLASS
2f730fec 3391reset:
03231f9b 3392 sdhci_do_reset(host, SDHCI_RESET_ALL);
b537f94c
RK		 3393 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
3394 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
2f730fec
PO		 3395 free_irq(host->irq, host);
3396#endif
8ef1a143 3397untasklet:
d129bceb 3398 tasklet_kill(&host->finish_tasklet);
d129bceb
PO		 3399
3400 return ret;
3401}
3402
b8c86fc5 3403EXPORT_SYMBOL_GPL(sdhci_add_host);
d129bceb 3404
1e72859e 3405void sdhci_remove_host(struct sdhci_host *host, int dead)
b8c86fc5 3406{
3a48edc4 3407 struct mmc_host *mmc = host->mmc;
1e72859e
PO		 3408 unsigned long flags;
3409
3410 if (dead) {
3411 spin_lock_irqsave(&host->lock, flags);
3412
3413 host->flags |= SDHCI_DEVICE_DEAD;
3414
3415 if (host->mrq) {
a3c76eb9 3416 pr_err("%s: Controller removed during "
4e743f1f 3417 " transfer!\n", mmc_hostname(mmc));
1e72859e
PO		 3418
3419 host->mrq->cmd->error = -ENOMEDIUM;
3420 tasklet_schedule(&host->finish_tasklet);
3421 }
3422
3423 spin_unlock_irqrestore(&host->lock, flags);
3424 }
3425
7260cf5e
AV		 3426 sdhci_disable_card_detection(host);
3427
4e743f1f 3428 mmc_remove_host(mmc);
d129bceb 3429
f9134319 3430#ifdef SDHCI_USE_LEDS_CLASS
2f730fec
PO		 3431 led_classdev_unregister(&host->led);
3432#endif
3433
1e72859e 3434 if (!dead)
03231f9b 3435 sdhci_do_reset(host, SDHCI_RESET_ALL);
d129bceb 3436
b537f94c
RK		 3437 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
3438 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
d129bceb
PO		 3439 free_irq(host->irq, host);
3440
3441 del_timer_sync(&host->timer);
3442
d129bceb 3443 tasklet_kill(&host->finish_tasklet);
2134a922 3444
3a48edc4
TK		 3445 if (!IS_ERR(mmc->supply.vqmmc))
3446 regulator_disable(mmc->supply.vqmmc);
6231f3de 3447
4efaa6fb 3448 if (host->adma_table)
76fe379a 3449 dma_free_coherent(mmc_dev(mmc), host->adma_table_sz,
4efaa6fb 3450 host->adma_table, host->adma_addr);
2134a922
PO		 3451 kfree(host->align_buffer);
3452
4efaa6fb 3453 host->adma_table = NULL;
2134a922 3454 host->align_buffer = NULL;
d129bceb
PO		 3455}
3456
b8c86fc5 3457EXPORT_SYMBOL_GPL(sdhci_remove_host);
d129bceb 3458
b8c86fc5 3459void sdhci_free_host(struct sdhci_host *host)
d129bceb 3460{
b8c86fc5 3461 mmc_free_host(host->mmc);
d129bceb
PO		 3462}
3463
b8c86fc5 3464EXPORT_SYMBOL_GPL(sdhci_free_host);
d129bceb
PO		 3465
3466/*****************************************************************************\
3467 * *
3468 * Driver init/exit *
3469 * *
3470\*****************************************************************************/
3471
3472static int __init sdhci_drv_init(void)
3473{
a3c76eb9 3474 pr_info(DRIVER_NAME
52fbf9c9 3475 ": Secure Digital Host Controller Interface driver\n");
a3c76eb9 3476 pr_info(DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
d129bceb 3477
b8c86fc5 3478 return 0;
d129bceb
PO		 3479}
3480
3481static void __exit sdhci_drv_exit(void)
3482{
d129bceb
PO		 3483}
3484
3485module_init(sdhci_drv_init);
3486module_exit(sdhci_drv_exit);
3487
df673b22 3488module_param(debug_quirks, uint, 0444);
66fd8ad5 3489module_param(debug_quirks2, uint, 0444);
67435274 3490
32710e8f 3491MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
b8c86fc5 3492MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver");
d129bceb 3493MODULE_LICENSE("GPL");
67435274 3494
df673b22 3495MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");
66fd8ad5 3496MODULE_PARM_DESC(debug_quirks2, "Force certain other quirks.");
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