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mmc: sdhci: Simplify use of tuning timer
[mirror_ubuntu-artful-kernel.git] / drivers / mmc / host / sdhci.c
CommitLineData
d129bceb 1/*
70f10482 2 * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
d129bceb 3 *
b69c9058 4 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
d129bceb
PO		 5 *
6 * This program is free software; you can redistribute it and/or modify
643f720c
PO		 7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or (at
9 * your option) any later version.
84c46a53
PO		 10 *
11 * Thanks to the following companies for their support:
12 *
13 * - JMicron (hardware and technical support)
d129bceb
PO		 14 */
15
d129bceb
PO		 16#include <linux/delay.h>
17#include <linux/highmem.h>
b8c86fc5 18#include <linux/io.h>
88b47679 19#include <linux/module.h>
d129bceb 20#include <linux/dma-mapping.h>
5a0e3ad6 21#include <linux/slab.h>
11763609 22#include <linux/scatterlist.h>
9bea3c85 23#include <linux/regulator/consumer.h>
66fd8ad5 24#include <linux/pm_runtime.h>
d129bceb 25
2f730fec
PO		 26#include <linux/leds.h>
27
22113efd 28#include <linux/mmc/mmc.h>
d129bceb 29#include <linux/mmc/host.h>
473b095a 30#include <linux/mmc/card.h>
bec9d4e5 31#include <linux/mmc/slot-gpio.h>
d129bceb 32
d129bceb
PO		 33#include "sdhci.h"
34
35#define DRIVER_NAME "sdhci"
d129bceb 36
d129bceb 37#define DBG(f, x...) \
c6563178 38 pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
d129bceb 39
f9134319
PO		 40#if defined(CONFIG_LEDS_CLASS) || (defined(CONFIG_LEDS_CLASS_MODULE) && \
41 defined(CONFIG_MMC_SDHCI_MODULE))
42#define SDHCI_USE_LEDS_CLASS
43#endif
44
b513ea25
AN		 45#define MAX_TUNING_LOOP 40
46
df673b22 47static unsigned int debug_quirks = 0;
66fd8ad5 48static unsigned int debug_quirks2;
67435274 49
d129bceb
PO		 50static void sdhci_finish_data(struct sdhci_host *);
51
d129bceb 52static void sdhci_finish_command(struct sdhci_host *);
069c9f14 53static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode);
cf2b5eea 54static void sdhci_tuning_timer(unsigned long data);
52983382 55static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable);
d129bceb 56
162d6f98 57#ifdef CONFIG_PM
66fd8ad5
AH		 58static int sdhci_runtime_pm_get(struct sdhci_host *host);
59static int sdhci_runtime_pm_put(struct sdhci_host *host);
f0710a55
AH		 60static void sdhci_runtime_pm_bus_on(struct sdhci_host *host);
61static void sdhci_runtime_pm_bus_off(struct sdhci_host *host);
66fd8ad5
AH		 62#else
63static inline int sdhci_runtime_pm_get(struct sdhci_host *host)
64{
65 return 0;
66}
67static inline int sdhci_runtime_pm_put(struct sdhci_host *host)
68{
69 return 0;
70}
f0710a55
AH		 71static void sdhci_runtime_pm_bus_on(struct sdhci_host *host)
72{
73}
74static void sdhci_runtime_pm_bus_off(struct sdhci_host *host)
75{
76}
66fd8ad5
AH		 77#endif
78
d129bceb
PO		 79static void sdhci_dumpregs(struct sdhci_host *host)
80{
a3c76eb9 81 pr_debug(DRIVER_NAME ": =========== REGISTER DUMP (%s)===========\n",
412ab659 82 mmc_hostname(host->mmc));
d129bceb 83
a3c76eb9 84 pr_debug(DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n",
4e4141a5
AV		 85 sdhci_readl(host, SDHCI_DMA_ADDRESS),
86 sdhci_readw(host, SDHCI_HOST_VERSION));
a3c76eb9 87 pr_debug(DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n",
4e4141a5
AV		 88 sdhci_readw(host, SDHCI_BLOCK_SIZE),
89 sdhci_readw(host, SDHCI_BLOCK_COUNT));
a3c76eb9 90 pr_debug(DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
4e4141a5
AV		 91 sdhci_readl(host, SDHCI_ARGUMENT),
92 sdhci_readw(host, SDHCI_TRANSFER_MODE));
a3c76eb9 93 pr_debug(DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n",
4e4141a5
AV		 94 sdhci_readl(host, SDHCI_PRESENT_STATE),
95 sdhci_readb(host, SDHCI_HOST_CONTROL));
a3c76eb9 96 pr_debug(DRIVER_NAME ": Power: 0x%08x | Blk gap: 0x%08x\n",
4e4141a5
AV		 97 sdhci_readb(host, SDHCI_POWER_CONTROL),
98 sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL));
a3c76eb9 99 pr_debug(DRIVER_NAME ": Wake-up: 0x%08x | Clock: 0x%08x\n",
4e4141a5
AV		 100 sdhci_readb(host, SDHCI_WAKE_UP_CONTROL),
101 sdhci_readw(host, SDHCI_CLOCK_CONTROL));
a3c76eb9 102 pr_debug(DRIVER_NAME ": Timeout: 0x%08x | Int stat: 0x%08x\n",
4e4141a5
AV		 103 sdhci_readb(host, SDHCI_TIMEOUT_CONTROL),
104 sdhci_readl(host, SDHCI_INT_STATUS));
a3c76eb9 105 pr_debug(DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
4e4141a5
AV		 106 sdhci_readl(host, SDHCI_INT_ENABLE),
107 sdhci_readl(host, SDHCI_SIGNAL_ENABLE));
a3c76eb9 108 pr_debug(DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
4e4141a5
AV		 109 sdhci_readw(host, SDHCI_ACMD12_ERR),
110 sdhci_readw(host, SDHCI_SLOT_INT_STATUS));
a3c76eb9 111 pr_debug(DRIVER_NAME ": Caps: 0x%08x | Caps_1: 0x%08x\n",
4e4141a5 112 sdhci_readl(host, SDHCI_CAPABILITIES),
e8120ad1 113 sdhci_readl(host, SDHCI_CAPABILITIES_1));
a3c76eb9 114 pr_debug(DRIVER_NAME ": Cmd: 0x%08x | Max curr: 0x%08x\n",
e8120ad1 115 sdhci_readw(host, SDHCI_COMMAND),
4e4141a5 116 sdhci_readl(host, SDHCI_MAX_CURRENT));
a3c76eb9 117 pr_debug(DRIVER_NAME ": Host ctl2: 0x%08x\n",
f2119df6 118 sdhci_readw(host, SDHCI_HOST_CONTROL2));
d129bceb 119
e57a5f61
AH		 120 if (host->flags & SDHCI_USE_ADMA) {
121 if (host->flags & SDHCI_USE_64_BIT_DMA)
122 pr_debug(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x%08x\n",
123 readl(host->ioaddr + SDHCI_ADMA_ERROR),
124 readl(host->ioaddr + SDHCI_ADMA_ADDRESS_HI),
125 readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
126 else
127 pr_debug(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n",
128 readl(host->ioaddr + SDHCI_ADMA_ERROR),
129 readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
130 }
be3f4ae0 131
a3c76eb9 132 pr_debug(DRIVER_NAME ": ===========================================\n");
d129bceb
PO		 133}
134
135/*****************************************************************************\
136 * *
137 * Low level functions *
138 * *
139\*****************************************************************************/
140
7260cf5e
AV		 141static void sdhci_set_card_detection(struct sdhci_host *host, bool enable)
142{
5b4f1f6c 143 u32 present;
7260cf5e 144
c79396c1 145 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) ||
87b87a3f 146 (host->mmc->caps & MMC_CAP_NONREMOVABLE))
66fd8ad5
AH		 147 return;
148
5b4f1f6c
RK		 149 if (enable) {
150 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
151 SDHCI_CARD_PRESENT;
d25928d1 152
5b4f1f6c
RK		 153 host->ier |= present ? SDHCI_INT_CARD_REMOVE :
154 SDHCI_INT_CARD_INSERT;
155 } else {
156 host->ier &= ~(SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT);
157 }
b537f94c
RK		 158
159 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
160 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
7260cf5e
AV		 161}
162
163static void sdhci_enable_card_detection(struct sdhci_host *host)
164{
165 sdhci_set_card_detection(host, true);
166}
167
168static void sdhci_disable_card_detection(struct sdhci_host *host)
169{
170 sdhci_set_card_detection(host, false);
171}
172
03231f9b 173void sdhci_reset(struct sdhci_host *host, u8 mask)
d129bceb 174{
e16514d8 175 unsigned long timeout;
393c1a34 176
4e4141a5 177 sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
d129bceb 178
f0710a55 179 if (mask & SDHCI_RESET_ALL) {
d129bceb 180 host->clock = 0;
f0710a55
AH		 181 /* Reset-all turns off SD Bus Power */
182 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
183 sdhci_runtime_pm_bus_off(host);
184 }
d129bceb 185
e16514d8
PO		 186 /* Wait max 100 ms */
187 timeout = 100;
188
189 /* hw clears the bit when it's done */
4e4141a5 190 while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
e16514d8 191 if (timeout == 0) {
a3c76eb9 192 pr_err("%s: Reset 0x%x never completed.\n",
e16514d8
PO		 193 mmc_hostname(host->mmc), (int)mask);
194 sdhci_dumpregs(host);
195 return;
196 }
197 timeout--;
198 mdelay(1);
d129bceb 199 }
03231f9b
RK		 200}
201EXPORT_SYMBOL_GPL(sdhci_reset);
202
203static void sdhci_do_reset(struct sdhci_host *host, u8 mask)
204{
205 if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
206 if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) &
207 SDHCI_CARD_PRESENT))
208 return;
209 }
063a9dbb 210
03231f9b 211 host->ops->reset(host, mask);
393c1a34 212
da91a8f9
RK		 213 if (mask & SDHCI_RESET_ALL) {
214 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
215 if (host->ops->enable_dma)
216 host->ops->enable_dma(host);
217 }
218
219 /* Resetting the controller clears many */
220 host->preset_enabled = false;
3abc1e80 221 }
d129bceb
PO		 222}
223
2f4cbb3d
NP		 224static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios);
225
226static void sdhci_init(struct sdhci_host *host, int soft)
d129bceb 227{
2f4cbb3d 228 if (soft)
03231f9b 229 sdhci_do_reset(host, SDHCI_RESET_CMD|SDHCI_RESET_DATA);
2f4cbb3d 230 else
03231f9b 231 sdhci_do_reset(host, SDHCI_RESET_ALL);
d129bceb 232
b537f94c
RK		 233 host->ier = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
234 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT |
235 SDHCI_INT_INDEX | SDHCI_INT_END_BIT | SDHCI_INT_CRC |
236 SDHCI_INT_TIMEOUT | SDHCI_INT_DATA_END |
237 SDHCI_INT_RESPONSE;
238
239 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
240 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2f4cbb3d
NP		 241
242 if (soft) {
243 /* force clock reconfiguration */
244 host->clock = 0;
245 sdhci_set_ios(host->mmc, &host->mmc->ios);
246 }
7260cf5e 247}
d129bceb 248
7260cf5e
AV		 249static void sdhci_reinit(struct sdhci_host *host)
250{
2f4cbb3d 251 sdhci_init(host, 0);
b67c6b41
AL		 252 /*
253 * Retuning stuffs are affected by different cards inserted and only
254 * applicable to UHS-I cards. So reset these fields to their initial
255 * value when card is removed.
256 */
973905fe
AL		 257 if (host->flags & SDHCI_USING_RETUNING_TIMER) {
258 host->flags &= ~SDHCI_USING_RETUNING_TIMER;
259
b67c6b41
AL		 260 del_timer_sync(&host->tuning_timer);
261 host->flags &= ~SDHCI_NEEDS_RETUNING;
b67c6b41 262 }
7260cf5e 263 sdhci_enable_card_detection(host);
d129bceb
PO		 264}
265
266static void sdhci_activate_led(struct sdhci_host *host)
267{
268 u8 ctrl;
269
4e4141a5 270 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
d129bceb 271 ctrl |= SDHCI_CTRL_LED;
4e4141a5 272 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d129bceb
PO		 273}
274
275static void sdhci_deactivate_led(struct sdhci_host *host)
276{
277 u8 ctrl;
278
4e4141a5 279 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
d129bceb 280 ctrl &= ~SDHCI_CTRL_LED;
4e4141a5 281 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d129bceb
PO		 282}
283
f9134319 284#ifdef SDHCI_USE_LEDS_CLASS
2f730fec
PO		 285static void sdhci_led_control(struct led_classdev *led,
286 enum led_brightness brightness)
287{
288 struct sdhci_host *host = container_of(led, struct sdhci_host, led);
289 unsigned long flags;
290
291 spin_lock_irqsave(&host->lock, flags);
292
66fd8ad5
AH		 293 if (host->runtime_suspended)
294 goto out;
295
2f730fec
PO		 296 if (brightness == LED_OFF)
297 sdhci_deactivate_led(host);
298 else
299 sdhci_activate_led(host);
66fd8ad5 300out:
2f730fec
PO		 301 spin_unlock_irqrestore(&host->lock, flags);
302}
303#endif
304
d129bceb
PO		 305/*****************************************************************************\
306 * *
307 * Core functions *
308 * *
309\*****************************************************************************/
310
a406f5a3 311static void sdhci_read_block_pio(struct sdhci_host *host)
d129bceb 312{
7659150c
PO		 313 unsigned long flags;
314 size_t blksize, len, chunk;
7244b85b 315 u32 uninitialized_var(scratch);
7659150c 316 u8 *buf;
d129bceb 317
a406f5a3 318 DBG("PIO reading\n");
d129bceb 319
a406f5a3 320 blksize = host->data->blksz;
7659150c 321 chunk = 0;
d129bceb 322
7659150c 323 local_irq_save(flags);
d129bceb 324
a406f5a3 325 while (blksize) {
7659150c
PO		 326 if (!sg_miter_next(&host->sg_miter))
327 BUG();
d129bceb 328
7659150c 329 len = min(host->sg_miter.length, blksize);
d129bceb 330
7659150c
PO		 331 blksize -= len;
332 host->sg_miter.consumed = len;
14d836e7 333
7659150c 334 buf = host->sg_miter.addr;
d129bceb 335
7659150c
PO		 336 while (len) {
337 if (chunk == 0) {
4e4141a5 338 scratch = sdhci_readl(host, SDHCI_BUFFER);
7659150c 339 chunk = 4;
a406f5a3 340 }
7659150c
PO		 341
342 *buf = scratch & 0xFF;
343
344 buf++;
345 scratch >>= 8;
346 chunk--;
347 len--;
d129bceb 348 }
a406f5a3 349 }
7659150c
PO		 350
351 sg_miter_stop(&host->sg_miter);
352
353 local_irq_restore(flags);
a406f5a3 354}
d129bceb 355
a406f5a3
PO		 356static void sdhci_write_block_pio(struct sdhci_host *host)
357{
7659150c
PO		 358 unsigned long flags;
359 size_t blksize, len, chunk;
360 u32 scratch;
361 u8 *buf;
d129bceb 362
a406f5a3
PO		 363 DBG("PIO writing\n");
364
365 blksize = host->data->blksz;
7659150c
PO		 366 chunk = 0;
367 scratch = 0;
d129bceb 368
7659150c 369 local_irq_save(flags);
d129bceb 370
a406f5a3 371 while (blksize) {
7659150c
PO		 372 if (!sg_miter_next(&host->sg_miter))
373 BUG();
a406f5a3 374
7659150c
PO		 375 len = min(host->sg_miter.length, blksize);
376
377 blksize -= len;
378 host->sg_miter.consumed = len;
379
380 buf = host->sg_miter.addr;
d129bceb 381
7659150c
PO		 382 while (len) {
383 scratch |= (u32)*buf << (chunk * 8);
384
385 buf++;
386 chunk++;
387 len--;
388
389 if ((chunk == 4) || ((len == 0) && (blksize == 0))) {
4e4141a5 390 sdhci_writel(host, scratch, SDHCI_BUFFER);
7659150c
PO		 391 chunk = 0;
392 scratch = 0;
d129bceb 393 }
d129bceb
PO		 394 }
395 }
7659150c
PO		 396
397 sg_miter_stop(&host->sg_miter);
398
399 local_irq_restore(flags);
a406f5a3
PO		 400}
401
402static void sdhci_transfer_pio(struct sdhci_host *host)
403{
404 u32 mask;
405
406 BUG_ON(!host->data);
407
7659150c 408 if (host->blocks == 0)
a406f5a3
PO		 409 return;
410
411 if (host->data->flags & MMC_DATA_READ)
412 mask = SDHCI_DATA_AVAILABLE;
413 else
414 mask = SDHCI_SPACE_AVAILABLE;
415
4a3cba32
PO		 416 /*
417 * Some controllers (JMicron JMB38x) mess up the buffer bits
418 * for transfers < 4 bytes. As long as it is just one block,
419 * we can ignore the bits.
420 */
421 if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) &&
422 (host->data->blocks == 1))
423 mask = ~0;
424
4e4141a5 425 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
3e3bf207
AV		 426 if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY)
427 udelay(100);
428
a406f5a3
PO		 429 if (host->data->flags & MMC_DATA_READ)
430 sdhci_read_block_pio(host);
431 else
432 sdhci_write_block_pio(host);
d129bceb 433
7659150c
PO		 434 host->blocks--;
435 if (host->blocks == 0)
a406f5a3 436 break;
a406f5a3 437 }
d129bceb 438
a406f5a3 439 DBG("PIO transfer complete.\n");
d129bceb
PO		 440}
441
2134a922
PO		 442static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags)
443{
444 local_irq_save(*flags);
482fce99 445 return kmap_atomic(sg_page(sg)) + sg->offset;
2134a922
PO		 446}
447
448static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags)
449{
482fce99 450 kunmap_atomic(buffer);
2134a922
PO		 451 local_irq_restore(*flags);
452}
453
e57a5f61
AH		 454static void sdhci_adma_write_desc(struct sdhci_host *host, void *desc,
455 dma_addr_t addr, int len, unsigned cmd)
118cd17d 456{
e57a5f61 457 struct sdhci_adma2_64_desc *dma_desc = desc;
118cd17d 458
e57a5f61 459 /* 32-bit and 64-bit descriptors have these members in same position */
0545230f
AH		 460 dma_desc->cmd = cpu_to_le16(cmd);
461 dma_desc->len = cpu_to_le16(len);
e57a5f61
AH		 462 dma_desc->addr_lo = cpu_to_le32((u32)addr);
463
464 if (host->flags & SDHCI_USE_64_BIT_DMA)
465 dma_desc->addr_hi = cpu_to_le32((u64)addr >> 32);
118cd17d
BD		 466}
467
b5ffa674
AH		 468static void sdhci_adma_mark_end(void *desc)
469{
e57a5f61 470 struct sdhci_adma2_64_desc *dma_desc = desc;
b5ffa674 471
e57a5f61 472 /* 32-bit and 64-bit descriptors have 'cmd' in same position */
0545230f 473 dma_desc->cmd |= cpu_to_le16(ADMA2_END);
b5ffa674
AH		 474}
475
8f1934ce 476static int sdhci_adma_table_pre(struct sdhci_host *host,
2134a922
PO		 477 struct mmc_data *data)
478{
479 int direction;
480
1c3d5f6d
AH		 481 void *desc;
482 void *align;
2134a922
PO		 483 dma_addr_t addr;
484 dma_addr_t align_addr;
485 int len, offset;
486
487 struct scatterlist *sg;
488 int i;
489 char *buffer;
490 unsigned long flags;
491
492 /*
493 * The spec does not specify endianness of descriptor table.
494 * We currently guess that it is LE.
495 */
496
497 if (data->flags & MMC_DATA_READ)
498 direction = DMA_FROM_DEVICE;
499 else
500 direction = DMA_TO_DEVICE;
501
2134a922 502 host->align_addr = dma_map_single(mmc_dev(host->mmc),
76fe379a 503 host->align_buffer, host->align_buffer_sz, direction);
8d8bb39b 504 if (dma_mapping_error(mmc_dev(host->mmc), host->align_addr))
8f1934ce 505 goto fail;
76fe379a 506 BUG_ON(host->align_addr & host->align_mask);
2134a922
PO		 507
508 host->sg_count = dma_map_sg(mmc_dev(host->mmc),
509 data->sg, data->sg_len, direction);
8f1934ce
PO		 510 if (host->sg_count == 0)
511 goto unmap_align;
2134a922 512
4efaa6fb 513 desc = host->adma_table;
2134a922
PO		 514 align = host->align_buffer;
515
516 align_addr = host->align_addr;
517
518 for_each_sg(data->sg, sg, host->sg_count, i) {
519 addr = sg_dma_address(sg);
520 len = sg_dma_len(sg);
521
522 /*
523 * The SDHCI specification states that ADMA
524 * addresses must be 32-bit aligned. If they
525 * aren't, then we use a bounce buffer for
526 * the (up to three) bytes that screw up the
527 * alignment.
528 */
76fe379a
AH		 529 offset = (host->align_sz - (addr & host->align_mask)) &
530 host->align_mask;
2134a922
PO		 531 if (offset) {
532 if (data->flags & MMC_DATA_WRITE) {
533 buffer = sdhci_kmap_atomic(sg, &flags);
8be78c6a
AH		 534 WARN_ON(((long)buffer & (PAGE_SIZE - 1)) >
535 (PAGE_SIZE - offset));
2134a922
PO		 536 memcpy(align, buffer, offset);
537 sdhci_kunmap_atomic(buffer, &flags);
538 }
539
118cd17d 540 /* tran, valid */
e57a5f61 541 sdhci_adma_write_desc(host, desc, align_addr, offset,
739d46dc 542 ADMA2_TRAN_VALID);
2134a922
PO		 543
544 BUG_ON(offset > 65536);
545
76fe379a
AH		 546 align += host->align_sz;
547 align_addr += host->align_sz;
2134a922 548
76fe379a 549 desc += host->desc_sz;
2134a922
PO		 550
551 addr += offset;
552 len -= offset;
553 }
554
2134a922
PO		 555 BUG_ON(len > 65536);
556
118cd17d 557 /* tran, valid */
e57a5f61 558 sdhci_adma_write_desc(host, desc, addr, len, ADMA2_TRAN_VALID);
76fe379a 559 desc += host->desc_sz;
2134a922
PO		 560
561 /*
562 * If this triggers then we have a calculation bug
563 * somewhere. :/
564 */
76fe379a 565 WARN_ON((desc - host->adma_table) >= host->adma_table_sz);
2134a922
PO		 566 }
567
70764a90
TA		 568 if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) {
569 /*
570 * Mark the last descriptor as the terminating descriptor
571 */
4efaa6fb 572 if (desc != host->adma_table) {
76fe379a 573 desc -= host->desc_sz;
b5ffa674 574 sdhci_adma_mark_end(desc);
70764a90
TA		 575 }
576 } else {
577 /*
578 * Add a terminating entry.
579 */
2134a922 580
70764a90 581 /* nop, end, valid */
e57a5f61 582 sdhci_adma_write_desc(host, desc, 0, 0, ADMA2_NOP_END_VALID);
70764a90 583 }
2134a922
PO		 584
585 /*
586 * Resync align buffer as we might have changed it.
587 */
588 if (data->flags & MMC_DATA_WRITE) {
589 dma_sync_single_for_device(mmc_dev(host->mmc),
76fe379a 590 host->align_addr, host->align_buffer_sz, direction);
2134a922
PO		 591 }
592
8f1934ce
PO		 593 return 0;
594
8f1934ce
PO		 595unmap_align:
596 dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
76fe379a 597 host->align_buffer_sz, direction);
8f1934ce
PO		 598fail:
599 return -EINVAL;
2134a922
PO		 600}
601
602static void sdhci_adma_table_post(struct sdhci_host *host,
603 struct mmc_data *data)
604{
605 int direction;
606
607 struct scatterlist *sg;
608 int i, size;
1c3d5f6d 609 void *align;
2134a922
PO		 610 char *buffer;
611 unsigned long flags;
de0b65a7 612 bool has_unaligned;
2134a922
PO		 613
614 if (data->flags & MMC_DATA_READ)
615 direction = DMA_FROM_DEVICE;
616 else
617 direction = DMA_TO_DEVICE;
618
2134a922 619 dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
76fe379a 620 host->align_buffer_sz, direction);
2134a922 621
de0b65a7
RK		 622 /* Do a quick scan of the SG list for any unaligned mappings */
623 has_unaligned = false;
624 for_each_sg(data->sg, sg, host->sg_count, i)
76fe379a 625 if (sg_dma_address(sg) & host->align_mask) {
de0b65a7
RK		 626 has_unaligned = true;
627 break;
628 }
629
630 if (has_unaligned && data->flags & MMC_DATA_READ) {
2134a922
PO		 631 dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
632 data->sg_len, direction);
633
634 align = host->align_buffer;
635
636 for_each_sg(data->sg, sg, host->sg_count, i) {
76fe379a
AH		 637 if (sg_dma_address(sg) & host->align_mask) {
638 size = host->align_sz -
639 (sg_dma_address(sg) & host->align_mask);
2134a922
PO		 640
641 buffer = sdhci_kmap_atomic(sg, &flags);
8be78c6a
AH		 642 WARN_ON(((long)buffer & (PAGE_SIZE - 1)) >
643 (PAGE_SIZE - size));
2134a922
PO		 644 memcpy(buffer, align, size);
645 sdhci_kunmap_atomic(buffer, &flags);
646
76fe379a 647 align += host->align_sz;
2134a922
PO		 648 }
649 }
650 }
651
652 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
653 data->sg_len, direction);
654}
655
a3c7778f 656static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd)
d129bceb 657{
1c8cde92 658 u8 count;
a3c7778f 659 struct mmc_data *data = cmd->data;
1c8cde92 660 unsigned target_timeout, current_timeout;
d129bceb 661
ee53ab5d
PO		 662 /*
663 * If the host controller provides us with an incorrect timeout
664 * value, just skip the check and use 0xE. The hardware may take
665 * longer to time out, but that's much better than having a too-short
666 * timeout value.
667 */
11a2f1b7 668 if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL)
ee53ab5d 669 return 0xE;
e538fbe8 670
a3c7778f 671 /* Unspecified timeout, assume max */
1d4d7744 672 if (!data && !cmd->busy_timeout)
a3c7778f 673 return 0xE;
d129bceb 674
a3c7778f
AW		 675 /* timeout in us */
676 if (!data)
1d4d7744 677 target_timeout = cmd->busy_timeout * 1000;
78a2ca27
AS		 678 else {
679 target_timeout = data->timeout_ns / 1000;
680 if (host->clock)
681 target_timeout += data->timeout_clks / host->clock;
682 }
81b39802 683
1c8cde92
PO		 684 /*
685 * Figure out needed cycles.
686 * We do this in steps in order to fit inside a 32 bit int.
687 * The first step is the minimum timeout, which will have a
688 * minimum resolution of 6 bits:
689 * (1) 2^13*1000 > 2^22,
690 * (2) host->timeout_clk < 2^16
691 * =>
692 * (1) / (2) > 2^6
693 */
694 count = 0;
695 current_timeout = (1 << 13) * 1000 / host->timeout_clk;
696 while (current_timeout < target_timeout) {
697 count++;
698 current_timeout <<= 1;
699 if (count >= 0xF)
700 break;
701 }
702
703 if (count >= 0xF) {
09eeff52
CB		 704 DBG("%s: Too large timeout 0x%x requested for CMD%d!\n",
705 mmc_hostname(host->mmc), count, cmd->opcode);
1c8cde92
PO		 706 count = 0xE;
707 }
708
ee53ab5d
PO		 709 return count;
710}
711
6aa943ab
AV		 712static void sdhci_set_transfer_irqs(struct sdhci_host *host)
713{
714 u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL;
715 u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR;
716
717 if (host->flags & SDHCI_REQ_USE_DMA)
b537f94c 718 host->ier = (host->ier & ~pio_irqs) | dma_irqs;
6aa943ab 719 else
b537f94c
RK		 720 host->ier = (host->ier & ~dma_irqs) | pio_irqs;
721
722 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
723 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
6aa943ab
AV		 724}
725
b45e668a 726static void sdhci_set_timeout(struct sdhci_host *host, struct mmc_command *cmd)
ee53ab5d
PO		 727{
728 u8 count;
b45e668a
AD		 729
730 if (host->ops->set_timeout) {
731 host->ops->set_timeout(host, cmd);
732 } else {
733 count = sdhci_calc_timeout(host, cmd);
734 sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
735 }
736}
737
738static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd)
739{
2134a922 740 u8 ctrl;
a3c7778f 741 struct mmc_data *data = cmd->data;
8f1934ce 742 int ret;
ee53ab5d
PO		 743
744 WARN_ON(host->data);
745
b45e668a
AD		 746 if (data || (cmd->flags & MMC_RSP_BUSY))
747 sdhci_set_timeout(host, cmd);
a3c7778f
AW		 748
749 if (!data)
ee53ab5d
PO		 750 return;
751
752 /* Sanity checks */
753 BUG_ON(data->blksz * data->blocks > 524288);
754 BUG_ON(data->blksz > host->mmc->max_blk_size);
755 BUG_ON(data->blocks > 65535);
756
757 host->data = data;
758 host->data_early = 0;
f6a03cbf 759 host->data->bytes_xfered = 0;
ee53ab5d 760
a13abc7b 761 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))
c9fddbc4
PO		 762 host->flags |= SDHCI_REQ_USE_DMA;
763
2134a922
PO		 764 /*
765 * FIXME: This doesn't account for merging when mapping the
766 * scatterlist.
767 */
768 if (host->flags & SDHCI_REQ_USE_DMA) {
769 int broken, i;
770 struct scatterlist *sg;
771
772 broken = 0;
773 if (host->flags & SDHCI_USE_ADMA) {
774 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
775 broken = 1;
776 } else {
777 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE)
778 broken = 1;
779 }
780
781 if (unlikely(broken)) {
782 for_each_sg(data->sg, sg, data->sg_len, i) {
783 if (sg->length & 0x3) {
784 DBG("Reverting to PIO because of "
785 "transfer size (%d)\n",
786 sg->length);
787 host->flags &= ~SDHCI_REQ_USE_DMA;
788 break;
789 }
790 }
791 }
c9fddbc4
PO		 792 }
793
794 /*
795 * The assumption here being that alignment is the same after
796 * translation to device address space.
797 */
2134a922
PO		 798 if (host->flags & SDHCI_REQ_USE_DMA) {
799 int broken, i;
800 struct scatterlist *sg;
801
802 broken = 0;
803 if (host->flags & SDHCI_USE_ADMA) {
804 /*
805 * As we use 3 byte chunks to work around
806 * alignment problems, we need to check this
807 * quirk.
808 */
809 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
810 broken = 1;
811 } else {
812 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR)
813 broken = 1;
814 }
815
816 if (unlikely(broken)) {
817 for_each_sg(data->sg, sg, data->sg_len, i) {
818 if (sg->offset & 0x3) {
819 DBG("Reverting to PIO because of "
820 "bad alignment\n");
821 host->flags &= ~SDHCI_REQ_USE_DMA;
822 break;
823 }
824 }
825 }
826 }
827
8f1934ce
PO		 828 if (host->flags & SDHCI_REQ_USE_DMA) {
829 if (host->flags & SDHCI_USE_ADMA) {
830 ret = sdhci_adma_table_pre(host, data);
831 if (ret) {
832 /*
833 * This only happens when someone fed
834 * us an invalid request.
835 */
836 WARN_ON(1);
ebd6d357 837 host->flags &= ~SDHCI_REQ_USE_DMA;
8f1934ce 838 } else {
4e4141a5
AV		 839 sdhci_writel(host, host->adma_addr,
840 SDHCI_ADMA_ADDRESS);
e57a5f61
AH		 841 if (host->flags & SDHCI_USE_64_BIT_DMA)
842 sdhci_writel(host,
843 (u64)host->adma_addr >> 32,
844 SDHCI_ADMA_ADDRESS_HI);
8f1934ce
PO		 845 }
846 } else {
c8b3e02e 847 int sg_cnt;
8f1934ce 848
c8b3e02e 849 sg_cnt = dma_map_sg(mmc_dev(host->mmc),
8f1934ce
PO		 850 data->sg, data->sg_len,
851 (data->flags & MMC_DATA_READ) ?
852 DMA_FROM_DEVICE :
853 DMA_TO_DEVICE);
c8b3e02e 854 if (sg_cnt == 0) {
8f1934ce
PO		 855 /*
856 * This only happens when someone fed
857 * us an invalid request.
858 */
859 WARN_ON(1);
ebd6d357 860 host->flags &= ~SDHCI_REQ_USE_DMA;
8f1934ce 861 } else {
719a61b4 862 WARN_ON(sg_cnt != 1);
4e4141a5
AV		 863 sdhci_writel(host, sg_dma_address(data->sg),
864 SDHCI_DMA_ADDRESS);
8f1934ce
PO		 865 }
866 }
867 }
868
2134a922
PO		 869 /*
870 * Always adjust the DMA selection as some controllers
871 * (e.g. JMicron) can't do PIO properly when the selection
872 * is ADMA.
873 */
874 if (host->version >= SDHCI_SPEC_200) {
4e4141a5 875 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
2134a922
PO		 876 ctrl &= ~SDHCI_CTRL_DMA_MASK;
877 if ((host->flags & SDHCI_REQ_USE_DMA) &&
e57a5f61
AH		 878 (host->flags & SDHCI_USE_ADMA)) {
879 if (host->flags & SDHCI_USE_64_BIT_DMA)
880 ctrl |= SDHCI_CTRL_ADMA64;
881 else
882 ctrl |= SDHCI_CTRL_ADMA32;
883 } else {
2134a922 884 ctrl |= SDHCI_CTRL_SDMA;
e57a5f61 885 }
4e4141a5 886 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
c9fddbc4
PO		 887 }
888
8f1934ce 889 if (!(host->flags & SDHCI_REQ_USE_DMA)) {
da60a91d
SAS		 890 int flags;
891
892 flags = SG_MITER_ATOMIC;
893 if (host->data->flags & MMC_DATA_READ)
894 flags |= SG_MITER_TO_SG;
895 else
896 flags |= SG_MITER_FROM_SG;
897 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
7659150c 898 host->blocks = data->blocks;
d129bceb 899 }
c7fa9963 900
6aa943ab
AV		 901 sdhci_set_transfer_irqs(host);
902
f6a03cbf
MV		 903 /* Set the DMA boundary value and block size */
904 sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
905 data->blksz), SDHCI_BLOCK_SIZE);
4e4141a5 906 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
c7fa9963
PO		 907}
908
909static void sdhci_set_transfer_mode(struct sdhci_host *host,
e89d456f 910 struct mmc_command *cmd)
c7fa9963
PO		 911{
912 u16 mode;
e89d456f 913 struct mmc_data *data = cmd->data;
c7fa9963 914
2b558c13 915 if (data == NULL) {
9b8ffea6
VW		 916 if (host->quirks2 &
917 SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD) {
918 sdhci_writew(host, 0x0, SDHCI_TRANSFER_MODE);
919 } else {
2b558c13 920 /* clear Auto CMD settings for no data CMDs */
9b8ffea6
VW		 921 mode = sdhci_readw(host, SDHCI_TRANSFER_MODE);
922 sdhci_writew(host, mode & ~(SDHCI_TRNS_AUTO_CMD12 |
2b558c13 923 SDHCI_TRNS_AUTO_CMD23), SDHCI_TRANSFER_MODE);
9b8ffea6 924 }
c7fa9963 925 return;
2b558c13 926 }
c7fa9963 927
e538fbe8
PO		 928 WARN_ON(!host->data);
929
c7fa9963 930 mode = SDHCI_TRNS_BLK_CNT_EN;
e89d456f
AW		 931 if (mmc_op_multi(cmd->opcode) || data->blocks > 1) {
932 mode |= SDHCI_TRNS_MULTI;
933 /*
934 * If we are sending CMD23, CMD12 never gets sent
935 * on successful completion (so no Auto-CMD12).
936 */
937 if (!host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD12))
938 mode |= SDHCI_TRNS_AUTO_CMD12;
8edf6371
AW		 939 else if (host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) {
940 mode |= SDHCI_TRNS_AUTO_CMD23;
941 sdhci_writel(host, host->mrq->sbc->arg, SDHCI_ARGUMENT2);
942 }
c4512f79 943 }
8edf6371 944
c7fa9963
PO		 945 if (data->flags & MMC_DATA_READ)
946 mode |= SDHCI_TRNS_READ;
c9fddbc4 947 if (host->flags & SDHCI_REQ_USE_DMA)
c7fa9963
PO		 948 mode |= SDHCI_TRNS_DMA;
949
4e4141a5 950 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
d129bceb
PO		 951}
952
953static void sdhci_finish_data(struct sdhci_host *host)
954{
955 struct mmc_data *data;
d129bceb
PO		 956
957 BUG_ON(!host->data);
958
959 data = host->data;
960 host->data = NULL;
961
c9fddbc4 962 if (host->flags & SDHCI_REQ_USE_DMA) {
2134a922
PO		 963 if (host->flags & SDHCI_USE_ADMA)
964 sdhci_adma_table_post(host, data);
965 else {
966 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
967 data->sg_len, (data->flags & MMC_DATA_READ) ?
968 DMA_FROM_DEVICE : DMA_TO_DEVICE);
969 }
d129bceb
PO		 970 }
971
972 /*
c9b74c5b
PO		 973 * The specification states that the block count register must
974 * be updated, but it does not specify at what point in the
975 * data flow. That makes the register entirely useless to read
976 * back so we have to assume that nothing made it to the card
977 * in the event of an error.
d129bceb 978 */
c9b74c5b
PO		 979 if (data->error)
980 data->bytes_xfered = 0;
d129bceb 981 else
c9b74c5b 982 data->bytes_xfered = data->blksz * data->blocks;
d129bceb 983
e89d456f
AW		 984 /*
985 * Need to send CMD12 if -
986 * a) open-ended multiblock transfer (no CMD23)
987 * b) error in multiblock transfer
988 */
989 if (data->stop &&
990 (data->error ||
991 !host->mrq->sbc)) {
992
d129bceb
PO		 993 /*
994 * The controller needs a reset of internal state machines
995 * upon error conditions.
996 */
17b0429d 997 if (data->error) {
03231f9b
RK		 998 sdhci_do_reset(host, SDHCI_RESET_CMD);
999 sdhci_do_reset(host, SDHCI_RESET_DATA);
d129bceb
PO		 1000 }
1001
1002 sdhci_send_command(host, data->stop);
1003 } else
1004 tasklet_schedule(&host->finish_tasklet);
1005}
1006
c0e55129 1007void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
d129bceb
PO		 1008{
1009 int flags;
fd2208d7 1010 u32 mask;
7cb2c76f 1011 unsigned long timeout;
d129bceb
PO		 1012
1013 WARN_ON(host->cmd);
1014
d129bceb 1015 /* Wait max 10 ms */
7cb2c76f 1016 timeout = 10;
fd2208d7
PO		 1017
1018 mask = SDHCI_CMD_INHIBIT;
1019 if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
1020 mask |= SDHCI_DATA_INHIBIT;
1021
1022 /* We shouldn't wait for data inihibit for stop commands, even
1023 though they might use busy signaling */
1024 if (host->mrq->data && (cmd == host->mrq->data->stop))
1025 mask &= ~SDHCI_DATA_INHIBIT;
1026
4e4141a5 1027 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
7cb2c76f 1028 if (timeout == 0) {
a3c76eb9 1029 pr_err("%s: Controller never released "
acf1da45 1030 "inhibit bit(s).\n", mmc_hostname(host->mmc));
d129bceb 1031 sdhci_dumpregs(host);
17b0429d 1032 cmd->error = -EIO;
d129bceb
PO		 1033 tasklet_schedule(&host->finish_tasklet);
1034 return;
1035 }
7cb2c76f
PO		 1036 timeout--;
1037 mdelay(1);
1038 }
d129bceb 1039
3e1a6892 1040 timeout = jiffies;
1d4d7744
UH		 1041 if (!cmd->data && cmd->busy_timeout > 9000)
1042 timeout += DIV_ROUND_UP(cmd->busy_timeout, 1000) * HZ + HZ;
3e1a6892
AH		 1043 else
1044 timeout += 10 * HZ;
1045 mod_timer(&host->timer, timeout);
d129bceb
PO		 1046
1047 host->cmd = cmd;
e99783a4 1048 host->busy_handle = 0;
d129bceb 1049
a3c7778f 1050 sdhci_prepare_data(host, cmd);
d129bceb 1051
4e4141a5 1052 sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT);
d129bceb 1053
e89d456f 1054 sdhci_set_transfer_mode(host, cmd);
c7fa9963 1055
d129bceb 1056 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
a3c76eb9 1057 pr_err("%s: Unsupported response type!\n",
d129bceb 1058 mmc_hostname(host->mmc));
17b0429d 1059 cmd->error = -EINVAL;
d129bceb
PO		 1060 tasklet_schedule(&host->finish_tasklet);
1061 return;
1062 }
1063
1064 if (!(cmd->flags & MMC_RSP_PRESENT))
1065 flags = SDHCI_CMD_RESP_NONE;
1066 else if (cmd->flags & MMC_RSP_136)
1067 flags = SDHCI_CMD_RESP_LONG;
1068 else if (cmd->flags & MMC_RSP_BUSY)
1069 flags = SDHCI_CMD_RESP_SHORT_BUSY;
1070 else
1071 flags = SDHCI_CMD_RESP_SHORT;
1072
1073 if (cmd->flags & MMC_RSP_CRC)
1074 flags |= SDHCI_CMD_CRC;
1075 if (cmd->flags & MMC_RSP_OPCODE)
1076 flags |= SDHCI_CMD_INDEX;
b513ea25
AN		 1077
1078 /* CMD19 is special in that the Data Present Select should be set */
069c9f14
G		 1079 if (cmd->data || cmd->opcode == MMC_SEND_TUNING_BLOCK ||
1080 cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200)
d129bceb
PO		 1081 flags |= SDHCI_CMD_DATA;
1082
4e4141a5 1083 sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND);
d129bceb 1084}
c0e55129 1085EXPORT_SYMBOL_GPL(sdhci_send_command);
d129bceb
PO		 1086
1087static void sdhci_finish_command(struct sdhci_host *host)
1088{
1089 int i;
1090
1091 BUG_ON(host->cmd == NULL);
1092
1093 if (host->cmd->flags & MMC_RSP_PRESENT) {
1094 if (host->cmd->flags & MMC_RSP_136) {
1095 /* CRC is stripped so we need to do some shifting. */
1096 for (i = 0;i < 4;i++) {
4e4141a5 1097 host->cmd->resp[i] = sdhci_readl(host,
d129bceb
PO		 1098 SDHCI_RESPONSE + (3-i)*4) << 8;
1099 if (i != 3)
1100 host->cmd->resp[i] |=
4e4141a5 1101 sdhci_readb(host,
d129bceb
PO		 1102 SDHCI_RESPONSE + (3-i)*4-1);
1103 }
1104 } else {
4e4141a5 1105 host->cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE);
d129bceb
PO		 1106 }
1107 }
1108
17b0429d 1109 host->cmd->error = 0;
d129bceb 1110
e89d456f
AW		 1111 /* Finished CMD23, now send actual command. */
1112 if (host->cmd == host->mrq->sbc) {
1113 host->cmd = NULL;
1114 sdhci_send_command(host, host->mrq->cmd);
1115 } else {
e538fbe8 1116
e89d456f
AW		 1117 /* Processed actual command. */
1118 if (host->data && host->data_early)
1119 sdhci_finish_data(host);
d129bceb 1120
e89d456f
AW		 1121 if (!host->cmd->data)
1122 tasklet_schedule(&host->finish_tasklet);
1123
1124 host->cmd = NULL;
1125 }
d129bceb
PO		 1126}
1127
52983382
KL		 1128static u16 sdhci_get_preset_value(struct sdhci_host *host)
1129{
d975f121 1130 u16 preset = 0;
52983382 1131
d975f121
RK		 1132 switch (host->timing) {
1133 case MMC_TIMING_UHS_SDR12:
52983382
KL		 1134 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1135 break;
d975f121 1136 case MMC_TIMING_UHS_SDR25:
52983382
KL		 1137 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR25);
1138 break;
d975f121 1139 case MMC_TIMING_UHS_SDR50:
52983382
KL		 1140 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR50);
1141 break;
d975f121
RK		 1142 case MMC_TIMING_UHS_SDR104:
1143 case MMC_TIMING_MMC_HS200:
52983382
KL		 1144 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR104);
1145 break;
d975f121 1146 case MMC_TIMING_UHS_DDR50:
52983382
KL		 1147 preset = sdhci_readw(host, SDHCI_PRESET_FOR_DDR50);
1148 break;
e9fb05d5
AH		 1149 case MMC_TIMING_MMC_HS400:
1150 preset = sdhci_readw(host, SDHCI_PRESET_FOR_HS400);
1151 break;
52983382
KL		 1152 default:
1153 pr_warn("%s: Invalid UHS-I mode selected\n",
1154 mmc_hostname(host->mmc));
1155 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1156 break;
1157 }
1158 return preset;
1159}
1160
1771059c 1161void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
d129bceb 1162{
c3ed3877 1163 int div = 0; /* Initialized for compiler warning */
df16219f 1164 int real_div = div, clk_mul = 1;
c3ed3877 1165 u16 clk = 0;
7cb2c76f 1166 unsigned long timeout;
d129bceb 1167
1650d0c7
RK		 1168 host->mmc->actual_clock = 0;
1169
4e4141a5 1170 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
d129bceb
PO		 1171
1172 if (clock == 0)
373073ef 1173 return;
d129bceb 1174
85105c53 1175 if (host->version >= SDHCI_SPEC_300) {
da91a8f9 1176 if (host->preset_enabled) {
52983382
KL		 1177 u16 pre_val;
1178
1179 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1180 pre_val = sdhci_get_preset_value(host);
1181 div = (pre_val & SDHCI_PRESET_SDCLK_FREQ_MASK)
1182 >> SDHCI_PRESET_SDCLK_FREQ_SHIFT;
1183 if (host->clk_mul &&
1184 (pre_val & SDHCI_PRESET_CLKGEN_SEL_MASK)) {
1185 clk = SDHCI_PROG_CLOCK_MODE;
1186 real_div = div + 1;
1187 clk_mul = host->clk_mul;
1188 } else {
1189 real_div = max_t(int, 1, div << 1);
1190 }
1191 goto clock_set;
1192 }
1193
c3ed3877
AN		 1194 /*
1195 * Check if the Host Controller supports Programmable Clock
1196 * Mode.
1197 */
1198 if (host->clk_mul) {
52983382
KL		 1199 for (div = 1; div <= 1024; div++) {
1200 if ((host->max_clk * host->clk_mul / div)
1201 <= clock)
1202 break;
1203 }
c3ed3877 1204 /*
52983382
KL		 1205 * Set Programmable Clock Mode in the Clock
1206 * Control register.
c3ed3877 1207 */
52983382
KL		 1208 clk = SDHCI_PROG_CLOCK_MODE;
1209 real_div = div;
1210 clk_mul = host->clk_mul;
1211 div--;
c3ed3877
AN		 1212 } else {
1213 /* Version 3.00 divisors must be a multiple of 2. */
1214 if (host->max_clk <= clock)
1215 div = 1;
1216 else {
1217 for (div = 2; div < SDHCI_MAX_DIV_SPEC_300;
1218 div += 2) {
1219 if ((host->max_clk / div) <= clock)
1220 break;
1221 }
85105c53 1222 }
df16219f 1223 real_div = div;
c3ed3877 1224 div >>= 1;
85105c53
ZG		 1225 }
1226 } else {
1227 /* Version 2.00 divisors must be a power of 2. */
0397526d 1228 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
85105c53
ZG		 1229 if ((host->max_clk / div) <= clock)
1230 break;
1231 }
df16219f 1232 real_div = div;
c3ed3877 1233 div >>= 1;
d129bceb 1234 }
d129bceb 1235
52983382 1236clock_set:
03d6f5ff 1237 if (real_div)
df16219f 1238 host->mmc->actual_clock = (host->max_clk * clk_mul) / real_div;
c3ed3877 1239 clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
85105c53
ZG		 1240 clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
1241 << SDHCI_DIVIDER_HI_SHIFT;
d129bceb 1242 clk |= SDHCI_CLOCK_INT_EN;
4e4141a5 1243 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
d129bceb 1244
27f6cb16
CB		 1245 /* Wait max 20 ms */
1246 timeout = 20;
4e4141a5 1247 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
7cb2c76f
PO		 1248 & SDHCI_CLOCK_INT_STABLE)) {
1249 if (timeout == 0) {
a3c76eb9 1250 pr_err("%s: Internal clock never "
acf1da45 1251 "stabilised.\n", mmc_hostname(host->mmc));
d129bceb
PO		 1252 sdhci_dumpregs(host);
1253 return;
1254 }
7cb2c76f
PO		 1255 timeout--;
1256 mdelay(1);
1257 }
d129bceb
PO		 1258
1259 clk |= SDHCI_CLOCK_CARD_EN;
4e4141a5 1260 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
d129bceb 1261}
1771059c 1262EXPORT_SYMBOL_GPL(sdhci_set_clock);
d129bceb 1263
24fbb3ca
RK		 1264static void sdhci_set_power(struct sdhci_host *host, unsigned char mode,
1265 unsigned short vdd)
146ad66e 1266{
3a48edc4 1267 struct mmc_host *mmc = host->mmc;
8364248a 1268 u8 pwr = 0;
146ad66e 1269
52221610
TK		 1270 if (!IS_ERR(mmc->supply.vmmc)) {
1271 spin_unlock_irq(&host->lock);
4e743f1f 1272 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd);
52221610
TK		 1273 spin_lock_irq(&host->lock);
1274 return;
1275 }
1276
24fbb3ca
RK		 1277 if (mode != MMC_POWER_OFF) {
1278 switch (1 << vdd) {
ae628903
PO		 1279 case MMC_VDD_165_195:
1280 pwr = SDHCI_POWER_180;
1281 break;
1282 case MMC_VDD_29_30:
1283 case MMC_VDD_30_31:
1284 pwr = SDHCI_POWER_300;
1285 break;
1286 case MMC_VDD_32_33:
1287 case MMC_VDD_33_34:
1288 pwr = SDHCI_POWER_330;
1289 break;
1290 default:
1291 BUG();
1292 }
1293 }
1294
1295 if (host->pwr == pwr)
e921a8b6 1296 return;
146ad66e 1297
ae628903
PO		 1298 host->pwr = pwr;
1299
1300 if (pwr == 0) {
4e4141a5 1301 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
f0710a55
AH		 1302 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
1303 sdhci_runtime_pm_bus_off(host);
24fbb3ca 1304 vdd = 0;
e921a8b6
RK		 1305 } else {
1306 /*
1307 * Spec says that we should clear the power reg before setting
1308 * a new value. Some controllers don't seem to like this though.
1309 */
1310 if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
1311 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
146ad66e 1312
e921a8b6
RK		 1313 /*
1314 * At least the Marvell CaFe chip gets confused if we set the
1315 * voltage and set turn on power at the same time, so set the
1316 * voltage first.
1317 */
1318 if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
1319 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
e08c1694 1320
e921a8b6 1321 pwr |= SDHCI_POWER_ON;
146ad66e 1322
e921a8b6 1323 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
557b0697 1324
e921a8b6
RK		 1325 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
1326 sdhci_runtime_pm_bus_on(host);
f0710a55 1327
e921a8b6
RK		 1328 /*
1329 * Some controllers need an extra 10ms delay of 10ms before
1330 * they can apply clock after applying power
1331 */
1332 if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER)
1333 mdelay(10);
1334 }
146ad66e
PO		 1335}
1336
d129bceb
PO		 1337/*****************************************************************************\
1338 * *
1339 * MMC callbacks *
1340 * *
1341\*****************************************************************************/
1342
1343static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1344{
1345 struct sdhci_host *host;
505a8680 1346 int present;
d129bceb 1347 unsigned long flags;
473b095a 1348 u32 tuning_opcode;
d129bceb
PO		 1349
1350 host = mmc_priv(mmc);
1351
66fd8ad5
AH		 1352 sdhci_runtime_pm_get(host);
1353
d129bceb
PO		 1354 spin_lock_irqsave(&host->lock, flags);
1355
1356 WARN_ON(host->mrq != NULL);
1357
f9134319 1358#ifndef SDHCI_USE_LEDS_CLASS
d129bceb 1359 sdhci_activate_led(host);
2f730fec 1360#endif
e89d456f
AW		 1361
1362 /*
1363 * Ensure we don't send the STOP for non-SET_BLOCK_COUNTED
1364 * requests if Auto-CMD12 is enabled.
1365 */
1366 if (!mrq->sbc && (host->flags & SDHCI_AUTO_CMD12)) {
c4512f79
JH		 1367 if (mrq->stop) {
1368 mrq->data->stop = NULL;
1369 mrq->stop = NULL;
1370 }
1371 }
d129bceb
PO		 1372
1373 host->mrq = mrq;
1374
505a8680
SG		 1375 /*
1376 * Firstly check card presence from cd-gpio. The return could
1377 * be one of the following possibilities:
1378 * negative: cd-gpio is not available
1379 * zero: cd-gpio is used, and card is removed
1380 * one: cd-gpio is used, and card is present
1381 */
1382 present = mmc_gpio_get_cd(host->mmc);
1383 if (present < 0) {
1384 /* If polling, assume that the card is always present. */
1385 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
1386 present = 1;
1387 else
1388 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
1389 SDHCI_CARD_PRESENT;
bec9d4e5
GL		 1390 }
1391
68d1fb7e 1392 if (!present || host->flags & SDHCI_DEVICE_DEAD) {
17b0429d 1393 host->mrq->cmd->error = -ENOMEDIUM;
d129bceb 1394 tasklet_schedule(&host->finish_tasklet);
cf2b5eea
AN		 1395 } else {
1396 u32 present_state;
1397
1398 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
1399 /*
1400 * Check if the re-tuning timer has already expired and there
7756a96d
YS		 1401 * is no on-going data transfer and DAT0 is not busy. If so,
1402 * we need to execute tuning procedure before sending command.
cf2b5eea
AN		 1403 */
1404 if ((host->flags & SDHCI_NEEDS_RETUNING) &&
7756a96d
YS		 1405 !(present_state & (SDHCI_DOING_WRITE | SDHCI_DOING_READ)) &&
1406 (present_state & SDHCI_DATA_0_LVL_MASK)) {
14efd957
CB		 1407 if (mmc->card) {
1408 /* eMMC uses cmd21 but sd and sdio use cmd19 */
1409 tuning_opcode =
1410 mmc->card->type == MMC_TYPE_MMC ?
1411 MMC_SEND_TUNING_BLOCK_HS200 :
1412 MMC_SEND_TUNING_BLOCK;
63c21180
CL		 1413
1414 /* Here we need to set the host->mrq to NULL,
1415 * in case the pending finish_tasklet
1416 * finishes it incorrectly.
1417 */
1418 host->mrq = NULL;
1419
14efd957
CB		 1420 spin_unlock_irqrestore(&host->lock, flags);
1421 sdhci_execute_tuning(mmc, tuning_opcode);
1422 spin_lock_irqsave(&host->lock, flags);
1423
1424 /* Restore original mmc_request structure */
1425 host->mrq = mrq;
1426 }
cf2b5eea
AN		 1427 }
1428
8edf6371 1429 if (mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23))
e89d456f
AW		 1430 sdhci_send_command(host, mrq->sbc);
1431 else
1432 sdhci_send_command(host, mrq->cmd);
cf2b5eea 1433 }
d129bceb 1434
5f25a66f 1435 mmiowb();
d129bceb
PO		 1436 spin_unlock_irqrestore(&host->lock, flags);
1437}
1438
2317f56c
RK		 1439void sdhci_set_bus_width(struct sdhci_host *host, int width)
1440{
1441 u8 ctrl;
1442
1443 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1444 if (width == MMC_BUS_WIDTH_8) {
1445 ctrl &= ~SDHCI_CTRL_4BITBUS;
1446 if (host->version >= SDHCI_SPEC_300)
1447 ctrl |= SDHCI_CTRL_8BITBUS;
1448 } else {
1449 if (host->version >= SDHCI_SPEC_300)
1450 ctrl &= ~SDHCI_CTRL_8BITBUS;
1451 if (width == MMC_BUS_WIDTH_4)
1452 ctrl |= SDHCI_CTRL_4BITBUS;
1453 else
1454 ctrl &= ~SDHCI_CTRL_4BITBUS;
1455 }
1456 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1457}
1458EXPORT_SYMBOL_GPL(sdhci_set_bus_width);
1459
96d7b78c
RK		 1460void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing)
1461{
1462 u16 ctrl_2;
1463
1464 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1465 /* Select Bus Speed Mode for host */
1466 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
1467 if ((timing == MMC_TIMING_MMC_HS200) ||
1468 (timing == MMC_TIMING_UHS_SDR104))
1469 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
1470 else if (timing == MMC_TIMING_UHS_SDR12)
1471 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
1472 else if (timing == MMC_TIMING_UHS_SDR25)
1473 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
1474 else if (timing == MMC_TIMING_UHS_SDR50)
1475 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
1476 else if ((timing == MMC_TIMING_UHS_DDR50) ||
1477 (timing == MMC_TIMING_MMC_DDR52))
1478 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
e9fb05d5
AH		 1479 else if (timing == MMC_TIMING_MMC_HS400)
1480 ctrl_2 |= SDHCI_CTRL_HS400; /* Non-standard */
96d7b78c
RK		 1481 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1482}
1483EXPORT_SYMBOL_GPL(sdhci_set_uhs_signaling);
1484
66fd8ad5 1485static void sdhci_do_set_ios(struct sdhci_host *host, struct mmc_ios *ios)
d129bceb 1486{
d129bceb
PO		 1487 unsigned long flags;
1488 u8 ctrl;
3a48edc4 1489 struct mmc_host *mmc = host->mmc;
d129bceb 1490
d129bceb
PO		 1491 spin_lock_irqsave(&host->lock, flags);
1492
ceb6143b
AH		 1493 if (host->flags & SDHCI_DEVICE_DEAD) {
1494 spin_unlock_irqrestore(&host->lock, flags);
3a48edc4
TK		 1495 if (!IS_ERR(mmc->supply.vmmc) &&
1496 ios->power_mode == MMC_POWER_OFF)
4e743f1f 1497 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
ceb6143b
AH		 1498 return;
1499 }
1e72859e 1500
d129bceb
PO		 1501 /*
1502 * Reset the chip on each power off.
1503 * Should clear out any weird states.
1504 */
1505 if (ios->power_mode == MMC_POWER_OFF) {
4e4141a5 1506 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
7260cf5e 1507 sdhci_reinit(host);
d129bceb
PO		 1508 }
1509
52983382 1510 if (host->version >= SDHCI_SPEC_300 &&
372c4634
DA		 1511 (ios->power_mode == MMC_POWER_UP) &&
1512 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN))
52983382
KL		 1513 sdhci_enable_preset_value(host, false);
1514
373073ef 1515 if (!ios->clock || ios->clock != host->clock) {
1771059c 1516 host->ops->set_clock(host, ios->clock);
373073ef 1517 host->clock = ios->clock;
03d6f5ff
AD		 1518
1519 if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK &&
1520 host->clock) {
1521 host->timeout_clk = host->mmc->actual_clock ?
1522 host->mmc->actual_clock / 1000 :
1523 host->clock / 1000;
1524 host->mmc->max_busy_timeout =
1525 host->ops->get_max_timeout_count ?
1526 host->ops->get_max_timeout_count(host) :
1527 1 << 27;
1528 host->mmc->max_busy_timeout /= host->timeout_clk;
1529 }
373073ef 1530 }
d129bceb 1531
24fbb3ca 1532 sdhci_set_power(host, ios->power_mode, ios->vdd);
d129bceb 1533
643a81ff
PR		 1534 if (host->ops->platform_send_init_74_clocks)
1535 host->ops->platform_send_init_74_clocks(host, ios->power_mode);
1536
2317f56c 1537 host->ops->set_bus_width(host, ios->bus_width);
ae6d6c92 1538
15ec4461 1539 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
cd9277c0 1540
3ab9c8da
PR		 1541 if ((ios->timing == MMC_TIMING_SD_HS ||
1542 ios->timing == MMC_TIMING_MMC_HS)
1543 && !(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT))
cd9277c0
PO		 1544 ctrl |= SDHCI_CTRL_HISPD;
1545 else
1546 ctrl &= ~SDHCI_CTRL_HISPD;
1547
d6d50a15 1548 if (host->version >= SDHCI_SPEC_300) {
49c468fc 1549 u16 clk, ctrl_2;
49c468fc
AN		 1550
1551 /* In case of UHS-I modes, set High Speed Enable */
e9fb05d5
AH		 1552 if ((ios->timing == MMC_TIMING_MMC_HS400) ||
1553 (ios->timing == MMC_TIMING_MMC_HS200) ||
bb8175a8 1554 (ios->timing == MMC_TIMING_MMC_DDR52) ||
069c9f14 1555 (ios->timing == MMC_TIMING_UHS_SDR50) ||
49c468fc
AN		 1556 (ios->timing == MMC_TIMING_UHS_SDR104) ||
1557 (ios->timing == MMC_TIMING_UHS_DDR50) ||
dd8df17f 1558 (ios->timing == MMC_TIMING_UHS_SDR25))
49c468fc 1559 ctrl |= SDHCI_CTRL_HISPD;
d6d50a15 1560
da91a8f9 1561 if (!host->preset_enabled) {
758535c4 1562 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d6d50a15
AN		 1563 /*
1564 * We only need to set Driver Strength if the
1565 * preset value enable is not set.
1566 */
da91a8f9 1567 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
d6d50a15
AN		 1568 ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK;
1569 if (ios->drv_type == MMC_SET_DRIVER_TYPE_A)
1570 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A;
1571 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C)
1572 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C;
1573
1574 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
758535c4
AN		 1575 } else {
1576 /*
1577 * According to SDHC Spec v3.00, if the Preset Value
1578 * Enable in the Host Control 2 register is set, we
1579 * need to reset SD Clock Enable before changing High
1580 * Speed Enable to avoid generating clock gliches.
1581 */
758535c4
AN		 1582
1583 /* Reset SD Clock Enable */
1584 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1585 clk &= ~SDHCI_CLOCK_CARD_EN;
1586 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1587
1588 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1589
1590 /* Re-enable SD Clock */
1771059c 1591 host->ops->set_clock(host, host->clock);
d6d50a15 1592 }
49c468fc 1593
49c468fc
AN		 1594 /* Reset SD Clock Enable */
1595 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1596 clk &= ~SDHCI_CLOCK_CARD_EN;
1597 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1598
96d7b78c 1599 host->ops->set_uhs_signaling(host, ios->timing);
d975f121 1600 host->timing = ios->timing;
49c468fc 1601
52983382
KL		 1602 if (!(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN) &&
1603 ((ios->timing == MMC_TIMING_UHS_SDR12) ||
1604 (ios->timing == MMC_TIMING_UHS_SDR25) ||
1605 (ios->timing == MMC_TIMING_UHS_SDR50) ||
1606 (ios->timing == MMC_TIMING_UHS_SDR104) ||
1607 (ios->timing == MMC_TIMING_UHS_DDR50))) {
1608 u16 preset;
1609
1610 sdhci_enable_preset_value(host, true);
1611 preset = sdhci_get_preset_value(host);
1612 ios->drv_type = (preset & SDHCI_PRESET_DRV_MASK)
1613 >> SDHCI_PRESET_DRV_SHIFT;
1614 }
1615
49c468fc 1616 /* Re-enable SD Clock */
1771059c 1617 host->ops->set_clock(host, host->clock);
758535c4
AN		 1618 } else
1619 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d6d50a15 1620
b8352260
LD		 1621 /*
1622 * Some (ENE) controllers go apeshit on some ios operation,
1623 * signalling timeout and CRC errors even on CMD0. Resetting
1624 * it on each ios seems to solve the problem.
1625 */
b8c86fc5 1626 if(host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
03231f9b 1627 sdhci_do_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
b8352260 1628
5f25a66f 1629 mmiowb();
d129bceb
PO		 1630 spin_unlock_irqrestore(&host->lock, flags);
1631}
1632
66fd8ad5
AH		 1633static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1634{
1635 struct sdhci_host *host = mmc_priv(mmc);
1636
1637 sdhci_runtime_pm_get(host);
1638 sdhci_do_set_ios(host, ios);
1639 sdhci_runtime_pm_put(host);
1640}
1641
94144a46
KL		 1642static int sdhci_do_get_cd(struct sdhci_host *host)
1643{
1644 int gpio_cd = mmc_gpio_get_cd(host->mmc);
1645
1646 if (host->flags & SDHCI_DEVICE_DEAD)
1647 return 0;
1648
1649 /* If polling/nonremovable, assume that the card is always present. */
1650 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) ||
1651 (host->mmc->caps & MMC_CAP_NONREMOVABLE))
1652 return 1;
1653
1654 /* Try slot gpio detect */
1655 if (!IS_ERR_VALUE(gpio_cd))
1656 return !!gpio_cd;
1657
1658 /* Host native card detect */
1659 return !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
1660}
1661
1662static int sdhci_get_cd(struct mmc_host *mmc)
1663{
1664 struct sdhci_host *host = mmc_priv(mmc);
1665 int ret;
1666
1667 sdhci_runtime_pm_get(host);
1668 ret = sdhci_do_get_cd(host);
1669 sdhci_runtime_pm_put(host);
1670 return ret;
1671}
1672
66fd8ad5 1673static int sdhci_check_ro(struct sdhci_host *host)
d129bceb 1674{
d129bceb 1675 unsigned long flags;
2dfb579c 1676 int is_readonly;
d129bceb 1677
d129bceb
PO		 1678 spin_lock_irqsave(&host->lock, flags);
1679
1e72859e 1680 if (host->flags & SDHCI_DEVICE_DEAD)
2dfb579c
WS		 1681 is_readonly = 0;
1682 else if (host->ops->get_ro)
1683 is_readonly = host->ops->get_ro(host);
1e72859e 1684 else
2dfb579c
WS		 1685 is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE)
1686 & SDHCI_WRITE_PROTECT);
d129bceb
PO		 1687
1688 spin_unlock_irqrestore(&host->lock, flags);
1689
2dfb579c
WS		 1690 /* This quirk needs to be replaced by a callback-function later */
1691 return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ?
1692 !is_readonly : is_readonly;
d129bceb
PO		 1693}
1694
82b0e23a
TI		 1695#define SAMPLE_COUNT 5
1696
66fd8ad5 1697static int sdhci_do_get_ro(struct sdhci_host *host)
82b0e23a 1698{
82b0e23a
TI		 1699 int i, ro_count;
1700
82b0e23a 1701 if (!(host->quirks & SDHCI_QUIRK_UNSTABLE_RO_DETECT))
66fd8ad5 1702 return sdhci_check_ro(host);
82b0e23a
TI		 1703
1704 ro_count = 0;
1705 for (i = 0; i < SAMPLE_COUNT; i++) {
66fd8ad5 1706 if (sdhci_check_ro(host)) {
82b0e23a
TI		 1707 if (++ro_count > SAMPLE_COUNT / 2)
1708 return 1;
1709 }
1710 msleep(30);
1711 }
1712 return 0;
1713}
1714
20758b66
AH		 1715static void sdhci_hw_reset(struct mmc_host *mmc)
1716{
1717 struct sdhci_host *host = mmc_priv(mmc);
1718
1719 if (host->ops && host->ops->hw_reset)
1720 host->ops->hw_reset(host);
1721}
1722
66fd8ad5 1723static int sdhci_get_ro(struct mmc_host *mmc)
f75979b7 1724{
66fd8ad5
AH		 1725 struct sdhci_host *host = mmc_priv(mmc);
1726 int ret;
f75979b7 1727
66fd8ad5
AH		 1728 sdhci_runtime_pm_get(host);
1729 ret = sdhci_do_get_ro(host);
1730 sdhci_runtime_pm_put(host);
1731 return ret;
1732}
f75979b7 1733
66fd8ad5
AH		 1734static void sdhci_enable_sdio_irq_nolock(struct sdhci_host *host, int enable)
1735{
be138554 1736 if (!(host->flags & SDHCI_DEVICE_DEAD)) {
ef104333 1737 if (enable)
b537f94c 1738 host->ier |= SDHCI_INT_CARD_INT;
ef104333 1739 else
b537f94c
RK		 1740 host->ier &= ~SDHCI_INT_CARD_INT;
1741
1742 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
1743 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
ef104333
RK		 1744 mmiowb();
1745 }
66fd8ad5
AH		 1746}
1747
1748static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1749{
1750 struct sdhci_host *host = mmc_priv(mmc);
1751 unsigned long flags;
f75979b7 1752
ef104333
RK		 1753 sdhci_runtime_pm_get(host);
1754
66fd8ad5 1755 spin_lock_irqsave(&host->lock, flags);
ef104333
RK		 1756 if (enable)
1757 host->flags |= SDHCI_SDIO_IRQ_ENABLED;
1758 else
1759 host->flags &= ~SDHCI_SDIO_IRQ_ENABLED;
1760
66fd8ad5 1761 sdhci_enable_sdio_irq_nolock(host, enable);
f75979b7 1762 spin_unlock_irqrestore(&host->lock, flags);
ef104333
RK		 1763
1764 sdhci_runtime_pm_put(host);
f75979b7
PO		 1765}
1766
20b92a30 1767static int sdhci_do_start_signal_voltage_switch(struct sdhci_host *host,
21f5998f 1768 struct mmc_ios *ios)
f2119df6 1769{
3a48edc4 1770 struct mmc_host *mmc = host->mmc;
20b92a30 1771 u16 ctrl;
6231f3de 1772 int ret;
f2119df6 1773
20b92a30
KL		 1774 /*
1775 * Signal Voltage Switching is only applicable for Host Controllers
1776 * v3.00 and above.
1777 */
1778 if (host->version < SDHCI_SPEC_300)
1779 return 0;
6231f3de 1780
f2119df6 1781 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
f2119df6 1782
21f5998f 1783 switch (ios->signal_voltage) {
20b92a30
KL		 1784 case MMC_SIGNAL_VOLTAGE_330:
1785 /* Set 1.8V Signal Enable in the Host Control2 register to 0 */
1786 ctrl &= ~SDHCI_CTRL_VDD_180;
1787 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
f2119df6 1788
3a48edc4
TK		 1789 if (!IS_ERR(mmc->supply.vqmmc)) {
1790 ret = regulator_set_voltage(mmc->supply.vqmmc, 2700000,
1791 3600000);
20b92a30 1792 if (ret) {
6606110d
JP		 1793 pr_warn("%s: Switching to 3.3V signalling voltage failed\n",
1794 mmc_hostname(mmc));
20b92a30
KL		 1795 return -EIO;
1796 }
1797 }
1798 /* Wait for 5ms */
1799 usleep_range(5000, 5500);
f2119df6 1800
20b92a30
KL		 1801 /* 3.3V regulator output should be stable within 5 ms */
1802 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1803 if (!(ctrl & SDHCI_CTRL_VDD_180))
1804 return 0;
6231f3de 1805
6606110d
JP		 1806 pr_warn("%s: 3.3V regulator output did not became stable\n",
1807 mmc_hostname(mmc));
20b92a30
KL		 1808
1809 return -EAGAIN;
1810 case MMC_SIGNAL_VOLTAGE_180:
3a48edc4
TK		 1811 if (!IS_ERR(mmc->supply.vqmmc)) {
1812 ret = regulator_set_voltage(mmc->supply.vqmmc,
20b92a30
KL		 1813 1700000, 1950000);
1814 if (ret) {
6606110d
JP		 1815 pr_warn("%s: Switching to 1.8V signalling voltage failed\n",
1816 mmc_hostname(mmc));
20b92a30
KL		 1817 return -EIO;
1818 }
1819 }
6231f3de 1820
6231f3de
PR		 1821 /*
1822 * Enable 1.8V Signal Enable in the Host Control2
1823 * register
1824 */
20b92a30
KL		 1825 ctrl |= SDHCI_CTRL_VDD_180;
1826 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
6231f3de 1827
20b92a30
KL		 1828 /* 1.8V regulator output should be stable within 5 ms */
1829 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1830 if (ctrl & SDHCI_CTRL_VDD_180)
1831 return 0;
f2119df6 1832
6606110d
JP		 1833 pr_warn("%s: 1.8V regulator output did not became stable\n",
1834 mmc_hostname(mmc));
f2119df6 1835
20b92a30
KL		 1836 return -EAGAIN;
1837 case MMC_SIGNAL_VOLTAGE_120:
3a48edc4
TK		 1838 if (!IS_ERR(mmc->supply.vqmmc)) {
1839 ret = regulator_set_voltage(mmc->supply.vqmmc, 1100000,
1840 1300000);
20b92a30 1841 if (ret) {
6606110d
JP		 1842 pr_warn("%s: Switching to 1.2V signalling voltage failed\n",
1843 mmc_hostname(mmc));
20b92a30 1844 return -EIO;
f2119df6
AN		 1845 }
1846 }
6231f3de 1847 return 0;
20b92a30 1848 default:
f2119df6
AN		 1849 /* No signal voltage switch required */
1850 return 0;
20b92a30 1851 }
f2119df6
AN		 1852}
1853
66fd8ad5 1854static int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
21f5998f 1855 struct mmc_ios *ios)
66fd8ad5
AH		 1856{
1857 struct sdhci_host *host = mmc_priv(mmc);
1858 int err;
1859
1860 if (host->version < SDHCI_SPEC_300)
1861 return 0;
1862 sdhci_runtime_pm_get(host);
21f5998f 1863 err = sdhci_do_start_signal_voltage_switch(host, ios);
66fd8ad5
AH		 1864 sdhci_runtime_pm_put(host);
1865 return err;
1866}
1867
20b92a30
KL		 1868static int sdhci_card_busy(struct mmc_host *mmc)
1869{
1870 struct sdhci_host *host = mmc_priv(mmc);
1871 u32 present_state;
1872
1873 sdhci_runtime_pm_get(host);
1874 /* Check whether DAT[3:0] is 0000 */
1875 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
1876 sdhci_runtime_pm_put(host);
1877
1878 return !(present_state & SDHCI_DATA_LVL_MASK);
1879}
1880
069c9f14 1881static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode)
b513ea25 1882{
4b6f37d3 1883 struct sdhci_host *host = mmc_priv(mmc);
b513ea25 1884 u16 ctrl;
b513ea25 1885 int tuning_loop_counter = MAX_TUNING_LOOP;
b513ea25 1886 int err = 0;
2b35bd83 1887 unsigned long flags;
38e40bf5 1888 unsigned int tuning_count = 0;
b513ea25 1889
66fd8ad5 1890 sdhci_runtime_pm_get(host);
2b35bd83 1891 spin_lock_irqsave(&host->lock, flags);
b513ea25 1892
38e40bf5
AH		 1893 if (host->tuning_mode == SDHCI_TUNING_MODE_1)
1894 tuning_count = host->tuning_count;
1895
b513ea25 1896 /*
069c9f14
G		 1897 * The Host Controller needs tuning only in case of SDR104 mode
1898 * and for SDR50 mode when Use Tuning for SDR50 is set in the
b513ea25 1899 * Capabilities register.
069c9f14
G		 1900 * If the Host Controller supports the HS200 mode then the
1901 * tuning function has to be executed.
b513ea25 1902 */
4b6f37d3 1903 switch (host->timing) {
e9fb05d5 1904 case MMC_TIMING_MMC_HS400:
4b6f37d3
RK		 1905 case MMC_TIMING_MMC_HS200:
1906 case MMC_TIMING_UHS_SDR104:
1907 break;
1908
1909 case MMC_TIMING_UHS_SDR50:
1910 if (host->flags & SDHCI_SDR50_NEEDS_TUNING ||
1911 host->flags & SDHCI_SDR104_NEEDS_TUNING)
1912 break;
1913 /* FALLTHROUGH */
1914
1915 default:
d519c863 1916 goto out_unlock;
b513ea25
AN		 1917 }
1918
45251812 1919 if (host->ops->platform_execute_tuning) {
2b35bd83 1920 spin_unlock_irqrestore(&host->lock, flags);
45251812
DA		 1921 err = host->ops->platform_execute_tuning(host, opcode);
1922 sdhci_runtime_pm_put(host);
1923 return err;
1924 }
1925
4b6f37d3
RK		 1926 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1927 ctrl |= SDHCI_CTRL_EXEC_TUNING;
b513ea25
AN		 1928 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1929
1930 /*
1931 * As per the Host Controller spec v3.00, tuning command
1932 * generates Buffer Read Ready interrupt, so enable that.
1933 *
1934 * Note: The spec clearly says that when tuning sequence
1935 * is being performed, the controller does not generate
1936 * interrupts other than Buffer Read Ready interrupt. But
1937 * to make sure we don't hit a controller bug, we _only_
1938 * enable Buffer Read Ready interrupt here.
1939 */
b537f94c
RK		 1940 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE);
1941 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE);
b513ea25
AN		 1942
1943 /*
1944 * Issue CMD19 repeatedly till Execute Tuning is set to 0 or the number
1945 * of loops reaches 40 times or a timeout of 150ms occurs.
1946 */
b513ea25
AN		 1947 do {
1948 struct mmc_command cmd = {0};
66fd8ad5 1949 struct mmc_request mrq = {NULL};
b513ea25 1950
069c9f14 1951 cmd.opcode = opcode;
b513ea25
AN		 1952 cmd.arg = 0;
1953 cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
1954 cmd.retries = 0;
1955 cmd.data = NULL;
1956 cmd.error = 0;
1957
7ce45e95
AC		 1958 if (tuning_loop_counter-- == 0)
1959 break;
1960
b513ea25
AN		 1961 mrq.cmd = &cmd;
1962 host->mrq = &mrq;
1963
1964 /*
1965 * In response to CMD19, the card sends 64 bytes of tuning
1966 * block to the Host Controller. So we set the block size
1967 * to 64 here.
1968 */
069c9f14
G		 1969 if (cmd.opcode == MMC_SEND_TUNING_BLOCK_HS200) {
1970 if (mmc->ios.bus_width == MMC_BUS_WIDTH_8)
1971 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 128),
1972 SDHCI_BLOCK_SIZE);
1973 else if (mmc->ios.bus_width == MMC_BUS_WIDTH_4)
1974 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
1975 SDHCI_BLOCK_SIZE);
1976 } else {
1977 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
1978 SDHCI_BLOCK_SIZE);
1979 }
b513ea25
AN		 1980
1981 /*
1982 * The tuning block is sent by the card to the host controller.
1983 * So we set the TRNS_READ bit in the Transfer Mode register.
1984 * This also takes care of setting DMA Enable and Multi Block
1985 * Select in the same register to 0.
1986 */
1987 sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
1988
1989 sdhci_send_command(host, &cmd);
1990
1991 host->cmd = NULL;
1992 host->mrq = NULL;
1993
2b35bd83 1994 spin_unlock_irqrestore(&host->lock, flags);
b513ea25
AN		 1995 /* Wait for Buffer Read Ready interrupt */
1996 wait_event_interruptible_timeout(host->buf_ready_int,
1997 (host->tuning_done == 1),
1998 msecs_to_jiffies(50));
2b35bd83 1999 spin_lock_irqsave(&host->lock, flags);
b513ea25
AN		 2000
2001 if (!host->tuning_done) {
a3c76eb9 2002 pr_info(DRIVER_NAME ": Timeout waiting for "
b513ea25
AN		 2003 "Buffer Read Ready interrupt during tuning "
2004 "procedure, falling back to fixed sampling "
2005 "clock\n");
2006 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2007 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
2008 ctrl &= ~SDHCI_CTRL_EXEC_TUNING;
2009 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2010
2011 err = -EIO;
2012 goto out;
2013 }
2014
2015 host->tuning_done = 0;
2016
2017 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
197160d5
NS		 2018
2019 /* eMMC spec does not require a delay between tuning cycles */
2020 if (opcode == MMC_SEND_TUNING_BLOCK)
2021 mdelay(1);
b513ea25
AN		 2022 } while (ctrl & SDHCI_CTRL_EXEC_TUNING);
2023
2024 /*
2025 * The Host Driver has exhausted the maximum number of loops allowed,
2026 * so use fixed sampling frequency.
2027 */
7ce45e95 2028 if (tuning_loop_counter < 0) {
b513ea25
AN		 2029 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
2030 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
7ce45e95
AC		 2031 }
2032 if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) {
2033 pr_info(DRIVER_NAME ": Tuning procedure"
2034 " failed, falling back to fixed sampling"
2035 " clock\n");
114f2bf6 2036 err = -EIO;
b513ea25
AN		 2037 }
2038
2039out:
38e40bf5
AH		 2040 host->flags &= ~SDHCI_NEEDS_RETUNING;
2041
2042 if (tuning_count) {
973905fe 2043 host->flags |= SDHCI_USING_RETUNING_TIMER;
38e40bf5 2044 mod_timer(&host->tuning_timer, jiffies + tuning_count * HZ);
cf2b5eea
AN		 2045 }
2046
2047 /*
2048 * In case tuning fails, host controllers which support re-tuning can
2049 * try tuning again at a later time, when the re-tuning timer expires.
2050 * So for these controllers, we return 0. Since there might be other
2051 * controllers who do not have this capability, we return error for
973905fe
AL		 2052 * them. SDHCI_USING_RETUNING_TIMER means the host is currently using
2053 * a retuning timer to do the retuning for the card.
cf2b5eea 2054 */
973905fe 2055 if (err && (host->flags & SDHCI_USING_RETUNING_TIMER))
cf2b5eea
AN		 2056 err = 0;
2057
b537f94c
RK		 2058 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2059 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
d519c863 2060out_unlock:
2b35bd83 2061 spin_unlock_irqrestore(&host->lock, flags);
66fd8ad5 2062 sdhci_runtime_pm_put(host);
b513ea25
AN		 2063
2064 return err;
2065}
2066
52983382
KL		 2067
2068static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable)
4d55c5a1 2069{
4d55c5a1
AN		 2070 /* Host Controller v3.00 defines preset value registers */
2071 if (host->version < SDHCI_SPEC_300)
2072 return;
2073
4d55c5a1
AN		 2074 /*
2075 * We only enable or disable Preset Value if they are not already
2076 * enabled or disabled respectively. Otherwise, we bail out.
2077 */
da91a8f9
RK		 2078 if (host->preset_enabled != enable) {
2079 u16 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2080
2081 if (enable)
2082 ctrl |= SDHCI_CTRL_PRESET_VAL_ENABLE;
2083 else
2084 ctrl &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
2085
4d55c5a1 2086 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
da91a8f9
RK		 2087
2088 if (enable)
2089 host->flags |= SDHCI_PV_ENABLED;
2090 else
2091 host->flags &= ~SDHCI_PV_ENABLED;
2092
2093 host->preset_enabled = enable;
4d55c5a1 2094 }
66fd8ad5
AH		 2095}
2096
71e69211 2097static void sdhci_card_event(struct mmc_host *mmc)
d129bceb 2098{
71e69211 2099 struct sdhci_host *host = mmc_priv(mmc);
d129bceb
PO		 2100 unsigned long flags;
2101
722e1280
CD		 2102 /* First check if client has provided their own card event */
2103 if (host->ops->card_event)
2104 host->ops->card_event(host);
2105
d129bceb
PO		 2106 spin_lock_irqsave(&host->lock, flags);
2107
66fd8ad5 2108 /* Check host->mrq first in case we are runtime suspended */
9668d765 2109 if (host->mrq && !sdhci_do_get_cd(host)) {
a3c76eb9 2110 pr_err("%s: Card removed during transfer!\n",
66fd8ad5 2111 mmc_hostname(host->mmc));
a3c76eb9 2112 pr_err("%s: Resetting controller.\n",
66fd8ad5 2113 mmc_hostname(host->mmc));
d129bceb 2114
03231f9b
RK		 2115 sdhci_do_reset(host, SDHCI_RESET_CMD);
2116 sdhci_do_reset(host, SDHCI_RESET_DATA);
d129bceb 2117
66fd8ad5
AH		 2118 host->mrq->cmd->error = -ENOMEDIUM;
2119 tasklet_schedule(&host->finish_tasklet);
d129bceb
PO		 2120 }
2121
2122 spin_unlock_irqrestore(&host->lock, flags);
71e69211
GL		 2123}
2124
2125static const struct mmc_host_ops sdhci_ops = {
2126 .request = sdhci_request,
2127 .set_ios = sdhci_set_ios,
94144a46 2128 .get_cd = sdhci_get_cd,
71e69211
GL		 2129 .get_ro = sdhci_get_ro,
2130 .hw_reset = sdhci_hw_reset,
2131 .enable_sdio_irq = sdhci_enable_sdio_irq,
2132 .start_signal_voltage_switch = sdhci_start_signal_voltage_switch,
2133 .execute_tuning = sdhci_execute_tuning,
71e69211 2134 .card_event = sdhci_card_event,
20b92a30 2135 .card_busy = sdhci_card_busy,
71e69211
GL		 2136};
2137
2138/*****************************************************************************\
2139 * *
2140 * Tasklets *
2141 * *
2142\*****************************************************************************/
2143
d129bceb
PO		 2144static void sdhci_tasklet_finish(unsigned long param)
2145{
2146 struct sdhci_host *host;
2147 unsigned long flags;
2148 struct mmc_request *mrq;
2149
2150 host = (struct sdhci_host*)param;
2151
66fd8ad5
AH		 2152 spin_lock_irqsave(&host->lock, flags);
2153
0c9c99a7
CB		 2154 /*
2155 * If this tasklet gets rescheduled while running, it will
2156 * be run again afterwards but without any active request.
2157 */
66fd8ad5
AH		 2158 if (!host->mrq) {
2159 spin_unlock_irqrestore(&host->lock, flags);
0c9c99a7 2160 return;
66fd8ad5 2161 }
d129bceb
PO		 2162
2163 del_timer(&host->timer);
2164
2165 mrq = host->mrq;
2166
d129bceb
PO		 2167 /*
2168 * The controller needs a reset of internal state machines
2169 * upon error conditions.
2170 */
1e72859e 2171 if (!(host->flags & SDHCI_DEVICE_DEAD) &&
b7b4d342 2172 ((mrq->cmd && mrq->cmd->error) ||
fce9d33f
AG		 2173 (mrq->sbc && mrq->sbc->error) ||
2174 (mrq->data && ((mrq->data->error && !mrq->data->stop) ||
2175 (mrq->data->stop && mrq->data->stop->error))) ||
2176 (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) {
645289dc
PO		 2177
2178 /* Some controllers need this kick or reset won't work here */
8213af3b 2179 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)
645289dc 2180 /* This is to force an update */
1771059c 2181 host->ops->set_clock(host, host->clock);
645289dc
PO		 2182
2183 /* Spec says we should do both at the same time, but Ricoh
2184 controllers do not like that. */
03231f9b
RK		 2185 sdhci_do_reset(host, SDHCI_RESET_CMD);
2186 sdhci_do_reset(host, SDHCI_RESET_DATA);
d129bceb
PO		 2187 }
2188
2189 host->mrq = NULL;
2190 host->cmd = NULL;
2191 host->data = NULL;
2192
f9134319 2193#ifndef SDHCI_USE_LEDS_CLASS
d129bceb 2194 sdhci_deactivate_led(host);
2f730fec 2195#endif
d129bceb 2196
5f25a66f 2197 mmiowb();
d129bceb
PO		 2198 spin_unlock_irqrestore(&host->lock, flags);
2199
2200 mmc_request_done(host->mmc, mrq);
66fd8ad5 2201 sdhci_runtime_pm_put(host);
d129bceb
PO		 2202}
2203
2204static void sdhci_timeout_timer(unsigned long data)
2205{
2206 struct sdhci_host *host;
2207 unsigned long flags;
2208
2209 host = (struct sdhci_host*)data;
2210
2211 spin_lock_irqsave(&host->lock, flags);
2212
2213 if (host->mrq) {
a3c76eb9 2214 pr_err("%s: Timeout waiting for hardware "
acf1da45 2215 "interrupt.\n", mmc_hostname(host->mmc));
d129bceb
PO		 2216 sdhci_dumpregs(host);
2217
2218 if (host->data) {
17b0429d 2219 host->data->error = -ETIMEDOUT;
d129bceb
PO		 2220 sdhci_finish_data(host);
2221 } else {
2222 if (host->cmd)
17b0429d 2223 host->cmd->error = -ETIMEDOUT;
d129bceb 2224 else
17b0429d 2225 host->mrq->cmd->error = -ETIMEDOUT;
d129bceb
PO		 2226
2227 tasklet_schedule(&host->finish_tasklet);
2228 }
2229 }
2230
5f25a66f 2231 mmiowb();
d129bceb
PO		 2232 spin_unlock_irqrestore(&host->lock, flags);
2233}
2234
cf2b5eea
AN		 2235static void sdhci_tuning_timer(unsigned long data)
2236{
2237 struct sdhci_host *host;
2238 unsigned long flags;
2239
2240 host = (struct sdhci_host *)data;
2241
2242 spin_lock_irqsave(&host->lock, flags);
2243
2244 host->flags |= SDHCI_NEEDS_RETUNING;
2245
2246 spin_unlock_irqrestore(&host->lock, flags);
2247}
2248
d129bceb
PO		 2249/*****************************************************************************\
2250 * *
2251 * Interrupt handling *
2252 * *
2253\*****************************************************************************/
2254
61541397 2255static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask, u32 *mask)
d129bceb
PO		 2256{
2257 BUG_ON(intmask == 0);
2258
2259 if (!host->cmd) {
a3c76eb9 2260 pr_err("%s: Got command interrupt 0x%08x even "
b67ac3f3
PO		 2261 "though no command operation was in progress.\n",
2262 mmc_hostname(host->mmc), (unsigned)intmask);
d129bceb
PO		 2263 sdhci_dumpregs(host);
2264 return;
2265 }
2266
43b58b36 2267 if (intmask & SDHCI_INT_TIMEOUT)
17b0429d
PO		 2268 host->cmd->error = -ETIMEDOUT;
2269 else if (intmask & (SDHCI_INT_CRC | SDHCI_INT_END_BIT |
2270 SDHCI_INT_INDEX))
2271 host->cmd->error = -EILSEQ;
43b58b36 2272
e809517f 2273 if (host->cmd->error) {
d129bceb 2274 tasklet_schedule(&host->finish_tasklet);
e809517f
PO		 2275 return;
2276 }
2277
2278 /*
2279 * The host can send and interrupt when the busy state has
2280 * ended, allowing us to wait without wasting CPU cycles.
2281 * Unfortunately this is overloaded on the "data complete"
2282 * interrupt, so we need to take some care when handling
2283 * it.
2284 *
2285 * Note: The 1.0 specification is a bit ambiguous about this
2286 * feature so there might be some problems with older
2287 * controllers.
2288 */
2289 if (host->cmd->flags & MMC_RSP_BUSY) {
2290 if (host->cmd->data)
2291 DBG("Cannot wait for busy signal when also "
2292 "doing a data transfer");
e99783a4
CM		 2293 else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ)
2294 && !host->busy_handle) {
2295 /* Mark that command complete before busy is ended */
2296 host->busy_handle = 1;
e809517f 2297 return;
e99783a4 2298 }
f945405c
BD		 2299
2300 /* The controller does not support the end-of-busy IRQ,
2301 * fall through and take the SDHCI_INT_RESPONSE */
61541397
AH		 2302 } else if ((host->quirks2 & SDHCI_QUIRK2_STOP_WITH_TC) &&
2303 host->cmd->opcode == MMC_STOP_TRANSMISSION && !host->data) {
2304 *mask &= ~SDHCI_INT_DATA_END;
e809517f
PO		 2305 }
2306
2307 if (intmask & SDHCI_INT_RESPONSE)
43b58b36 2308 sdhci_finish_command(host);
d129bceb
PO		 2309}
2310
0957c333 2311#ifdef CONFIG_MMC_DEBUG
08621b18 2312static void sdhci_adma_show_error(struct sdhci_host *host)
6882a8c0
BD		 2313{
2314 const char *name = mmc_hostname(host->mmc);
1c3d5f6d 2315 void *desc = host->adma_table;
6882a8c0
BD		 2316
2317 sdhci_dumpregs(host);
2318
2319 while (true) {
e57a5f61
AH		 2320 struct sdhci_adma2_64_desc *dma_desc = desc;
2321
2322 if (host->flags & SDHCI_USE_64_BIT_DMA)
2323 DBG("%s: %p: DMA 0x%08x%08x, LEN 0x%04x, Attr=0x%02x\n",
2324 name, desc, le32_to_cpu(dma_desc->addr_hi),
2325 le32_to_cpu(dma_desc->addr_lo),
2326 le16_to_cpu(dma_desc->len),
2327 le16_to_cpu(dma_desc->cmd));
2328 else
2329 DBG("%s: %p: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n",
2330 name, desc, le32_to_cpu(dma_desc->addr_lo),
2331 le16_to_cpu(dma_desc->len),
2332 le16_to_cpu(dma_desc->cmd));
6882a8c0 2333
76fe379a 2334 desc += host->desc_sz;
6882a8c0 2335
0545230f 2336 if (dma_desc->cmd & cpu_to_le16(ADMA2_END))
6882a8c0
BD		 2337 break;
2338 }
2339}
2340#else
08621b18 2341static void sdhci_adma_show_error(struct sdhci_host *host) { }
6882a8c0
BD		 2342#endif
2343
d129bceb
PO		 2344static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
2345{
069c9f14 2346 u32 command;
d129bceb
PO		 2347 BUG_ON(intmask == 0);
2348
b513ea25
AN		 2349 /* CMD19 generates _only_ Buffer Read Ready interrupt */
2350 if (intmask & SDHCI_INT_DATA_AVAIL) {
069c9f14
G		 2351 command = SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND));
2352 if (command == MMC_SEND_TUNING_BLOCK ||
2353 command == MMC_SEND_TUNING_BLOCK_HS200) {
b513ea25
AN		 2354 host->tuning_done = 1;
2355 wake_up(&host->buf_ready_int);
2356 return;
2357 }
2358 }
2359
d129bceb
PO		 2360 if (!host->data) {
2361 /*
e809517f
PO		 2362 * The "data complete" interrupt is also used to
2363 * indicate that a busy state has ended. See comment
2364 * above in sdhci_cmd_irq().
d129bceb 2365 */
e809517f 2366 if (host->cmd && (host->cmd->flags & MMC_RSP_BUSY)) {
c5abd5e8
MC		 2367 if (intmask & SDHCI_INT_DATA_TIMEOUT) {
2368 host->cmd->error = -ETIMEDOUT;
2369 tasklet_schedule(&host->finish_tasklet);
2370 return;
2371 }
e809517f 2372 if (intmask & SDHCI_INT_DATA_END) {
e99783a4
CM		 2373 /*
2374 * Some cards handle busy-end interrupt
2375 * before the command completed, so make
2376 * sure we do things in the proper order.
2377 */
2378 if (host->busy_handle)
2379 sdhci_finish_command(host);
2380 else
2381 host->busy_handle = 1;
e809517f
PO		 2382 return;
2383 }
2384 }
d129bceb 2385
a3c76eb9 2386 pr_err("%s: Got data interrupt 0x%08x even "
b67ac3f3
PO		 2387 "though no data operation was in progress.\n",
2388 mmc_hostname(host->mmc), (unsigned)intmask);
d129bceb
PO		 2389 sdhci_dumpregs(host);
2390
2391 return;
2392 }
2393
2394 if (intmask & SDHCI_INT_DATA_TIMEOUT)
17b0429d 2395 host->data->error = -ETIMEDOUT;
22113efd
AL		 2396 else if (intmask & SDHCI_INT_DATA_END_BIT)
2397 host->data->error = -EILSEQ;
2398 else if ((intmask & SDHCI_INT_DATA_CRC) &&
2399 SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))
2400 != MMC_BUS_TEST_R)
17b0429d 2401 host->data->error = -EILSEQ;
6882a8c0 2402 else if (intmask & SDHCI_INT_ADMA_ERROR) {
a3c76eb9 2403 pr_err("%s: ADMA error\n", mmc_hostname(host->mmc));
08621b18 2404 sdhci_adma_show_error(host);
2134a922 2405 host->data->error = -EIO;
a4071fbb
HZ		 2406 if (host->ops->adma_workaround)
2407 host->ops->adma_workaround(host, intmask);
6882a8c0 2408 }
d129bceb 2409
17b0429d 2410 if (host->data->error)
d129bceb
PO		 2411 sdhci_finish_data(host);
2412 else {
a406f5a3 2413 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
d129bceb
PO		 2414 sdhci_transfer_pio(host);
2415
6ba736a1
PO		 2416 /*
2417 * We currently don't do anything fancy with DMA
2418 * boundaries, but as we can't disable the feature
2419 * we need to at least restart the transfer.
f6a03cbf
MV		 2420 *
2421 * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS)
2422 * should return a valid address to continue from, but as
2423 * some controllers are faulty, don't trust them.
6ba736a1 2424 */
f6a03cbf
MV		 2425 if (intmask & SDHCI_INT_DMA_END) {
2426 u32 dmastart, dmanow;
2427 dmastart = sg_dma_address(host->data->sg);
2428 dmanow = dmastart + host->data->bytes_xfered;
2429 /*
2430 * Force update to the next DMA block boundary.
2431 */
2432 dmanow = (dmanow &
2433 ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) +
2434 SDHCI_DEFAULT_BOUNDARY_SIZE;
2435 host->data->bytes_xfered = dmanow - dmastart;
2436 DBG("%s: DMA base 0x%08x, transferred 0x%06x bytes,"
2437 " next 0x%08x\n",
2438 mmc_hostname(host->mmc), dmastart,
2439 host->data->bytes_xfered, dmanow);
2440 sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS);
2441 }
6ba736a1 2442
e538fbe8
PO		 2443 if (intmask & SDHCI_INT_DATA_END) {
2444 if (host->cmd) {
2445 /*
2446 * Data managed to finish before the
2447 * command completed. Make sure we do
2448 * things in the proper order.
2449 */
2450 host->data_early = 1;
2451 } else {
2452 sdhci_finish_data(host);
2453 }
2454 }
d129bceb
PO		 2455 }
2456}
2457
7d12e780 2458static irqreturn_t sdhci_irq(int irq, void *dev_id)
d129bceb 2459{
781e989c 2460 irqreturn_t result = IRQ_NONE;
66fd8ad5 2461 struct sdhci_host *host = dev_id;
41005003 2462 u32 intmask, mask, unexpected = 0;
781e989c 2463 int max_loops = 16;
d129bceb
PO		 2464
2465 spin_lock(&host->lock);
2466
be138554 2467 if (host->runtime_suspended && !sdhci_sdio_irq_enabled(host)) {
66fd8ad5 2468 spin_unlock(&host->lock);
655bca76 2469 return IRQ_NONE;
66fd8ad5
AH		 2470 }
2471
4e4141a5 2472 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
62df67a5 2473 if (!intmask || intmask == 0xffffffff) {
d129bceb
PO		 2474 result = IRQ_NONE;
2475 goto out;
2476 }
2477
41005003
RK		 2478 do {
2479 /* Clear selected interrupts. */
2480 mask = intmask & (SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
2481 SDHCI_INT_BUS_POWER);
2482 sdhci_writel(host, mask, SDHCI_INT_STATUS);
d129bceb 2483
41005003
RK		 2484 DBG("*** %s got interrupt: 0x%08x\n",
2485 mmc_hostname(host->mmc), intmask);
d129bceb 2486
41005003
RK		 2487 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
2488 u32 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
2489 SDHCI_CARD_PRESENT;
d129bceb 2490
41005003
RK		 2491 /*
2492 * There is a observation on i.mx esdhc. INSERT
2493 * bit will be immediately set again when it gets
2494 * cleared, if a card is inserted. We have to mask
2495 * the irq to prevent interrupt storm which will
2496 * freeze the system. And the REMOVE gets the
2497 * same situation.
2498 *
2499 * More testing are needed here to ensure it works
2500 * for other platforms though.
2501 */
b537f94c
RK		 2502 host->ier &= ~(SDHCI_INT_CARD_INSERT |
2503 SDHCI_INT_CARD_REMOVE);
2504 host->ier |= present ? SDHCI_INT_CARD_REMOVE :
2505 SDHCI_INT_CARD_INSERT;
2506 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2507 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
41005003
RK		 2508
2509 sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT |
2510 SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS);
3560db8e
RK		 2511
2512 host->thread_isr |= intmask & (SDHCI_INT_CARD_INSERT |
2513 SDHCI_INT_CARD_REMOVE);
2514 result = IRQ_WAKE_THREAD;
41005003 2515 }
d129bceb 2516
41005003 2517 if (intmask & SDHCI_INT_CMD_MASK)
61541397
AH		 2518 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK,
2519 &intmask);
964f9ce2 2520
41005003
RK		 2521 if (intmask & SDHCI_INT_DATA_MASK)
2522 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
d129bceb 2523
41005003
RK		 2524 if (intmask & SDHCI_INT_BUS_POWER)
2525 pr_err("%s: Card is consuming too much power!\n",
2526 mmc_hostname(host->mmc));
3192a28f 2527
781e989c
RK		 2528 if (intmask & SDHCI_INT_CARD_INT) {
2529 sdhci_enable_sdio_irq_nolock(host, false);
2530 host->thread_isr |= SDHCI_INT_CARD_INT;
2531 result = IRQ_WAKE_THREAD;
2532 }
f75979b7 2533
41005003
RK		 2534 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE |
2535 SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
2536 SDHCI_INT_ERROR | SDHCI_INT_BUS_POWER |
2537 SDHCI_INT_CARD_INT);
f75979b7 2538
41005003
RK		 2539 if (intmask) {
2540 unexpected |= intmask;
2541 sdhci_writel(host, intmask, SDHCI_INT_STATUS);
2542 }
d129bceb 2543
781e989c
RK		 2544 if (result == IRQ_NONE)
2545 result = IRQ_HANDLED;
d129bceb 2546
41005003 2547 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
41005003 2548 } while (intmask && --max_loops);
d129bceb
PO		 2549out:
2550 spin_unlock(&host->lock);
2551
6379b237
AS		 2552 if (unexpected) {
2553 pr_err("%s: Unexpected interrupt 0x%08x.\n",
2554 mmc_hostname(host->mmc), unexpected);
2555 sdhci_dumpregs(host);
2556 }
f75979b7 2557
d129bceb
PO		 2558 return result;
2559}
2560
781e989c
RK		 2561static irqreturn_t sdhci_thread_irq(int irq, void *dev_id)
2562{
2563 struct sdhci_host *host = dev_id;
2564 unsigned long flags;
2565 u32 isr;
2566
2567 spin_lock_irqsave(&host->lock, flags);
2568 isr = host->thread_isr;
2569 host->thread_isr = 0;
2570 spin_unlock_irqrestore(&host->lock, flags);
2571
3560db8e
RK		 2572 if (isr & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
2573 sdhci_card_event(host->mmc);
2574 mmc_detect_change(host->mmc, msecs_to_jiffies(200));
2575 }
2576
781e989c
RK		 2577 if (isr & SDHCI_INT_CARD_INT) {
2578 sdio_run_irqs(host->mmc);
2579
2580 spin_lock_irqsave(&host->lock, flags);
2581 if (host->flags & SDHCI_SDIO_IRQ_ENABLED)
2582 sdhci_enable_sdio_irq_nolock(host, true);
2583 spin_unlock_irqrestore(&host->lock, flags);
2584 }
2585
2586 return isr ? IRQ_HANDLED : IRQ_NONE;
2587}
2588
d129bceb
PO		 2589/*****************************************************************************\
2590 * *
2591 * Suspend/resume *
2592 * *
2593\*****************************************************************************/
2594
2595#ifdef CONFIG_PM
ad080d79
KL		 2596void sdhci_enable_irq_wakeups(struct sdhci_host *host)
2597{
2598 u8 val;
2599 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
2600 | SDHCI_WAKE_ON_INT;
2601
2602 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2603 val |= mask ;
2604 /* Avoid fake wake up */
2605 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
2606 val &= ~(SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE);
2607 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2608}
2609EXPORT_SYMBOL_GPL(sdhci_enable_irq_wakeups);
2610
0b10f478 2611static void sdhci_disable_irq_wakeups(struct sdhci_host *host)
ad080d79
KL		 2612{
2613 u8 val;
2614 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
2615 | SDHCI_WAKE_ON_INT;
2616
2617 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2618 val &= ~mask;
2619 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2620}
d129bceb 2621
29495aa0 2622int sdhci_suspend_host(struct sdhci_host *host)
d129bceb 2623{
7260cf5e
AV		 2624 sdhci_disable_card_detection(host);
2625
cf2b5eea 2626 /* Disable tuning since we are suspending */
973905fe 2627 if (host->flags & SDHCI_USING_RETUNING_TIMER) {
c6ced0db 2628 del_timer_sync(&host->tuning_timer);
cf2b5eea 2629 host->flags &= ~SDHCI_NEEDS_RETUNING;
cf2b5eea
AN		 2630 }
2631
ad080d79 2632 if (!device_may_wakeup(mmc_dev(host->mmc))) {
b537f94c
RK		 2633 host->ier = 0;
2634 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
2635 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
ad080d79
KL		 2636 free_irq(host->irq, host);
2637 } else {
2638 sdhci_enable_irq_wakeups(host);
2639 enable_irq_wake(host->irq);
2640 }
4ee14ec6 2641 return 0;
d129bceb
PO		 2642}
2643
b8c86fc5 2644EXPORT_SYMBOL_GPL(sdhci_suspend_host);
d129bceb 2645
b8c86fc5
PO		 2646int sdhci_resume_host(struct sdhci_host *host)
2647{
4ee14ec6 2648 int ret = 0;
d129bceb 2649
a13abc7b 2650 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
b8c86fc5
PO		 2651 if (host->ops->enable_dma)
2652 host->ops->enable_dma(host);
2653 }
d129bceb 2654
ad080d79 2655 if (!device_may_wakeup(mmc_dev(host->mmc))) {
781e989c
RK		 2656 ret = request_threaded_irq(host->irq, sdhci_irq,
2657 sdhci_thread_irq, IRQF_SHARED,
2658 mmc_hostname(host->mmc), host);
ad080d79
KL		 2659 if (ret)
2660 return ret;
2661 } else {
2662 sdhci_disable_irq_wakeups(host);
2663 disable_irq_wake(host->irq);
2664 }
d129bceb 2665
6308d290
AH		 2666 if ((host->mmc->pm_flags & MMC_PM_KEEP_POWER) &&
2667 (host->quirks2 & SDHCI_QUIRK2_HOST_OFF_CARD_ON)) {
2668 /* Card keeps power but host controller does not */
2669 sdhci_init(host, 0);
2670 host->pwr = 0;
2671 host->clock = 0;
2672 sdhci_do_set_ios(host, &host->mmc->ios);
2673 } else {
2674 sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER));
2675 mmiowb();
2676 }
b8c86fc5 2677
7260cf5e
AV		 2678 sdhci_enable_card_detection(host);
2679
cf2b5eea 2680 /* Set the re-tuning expiration flag */
973905fe 2681 if (host->flags & SDHCI_USING_RETUNING_TIMER)
cf2b5eea
AN		 2682 host->flags |= SDHCI_NEEDS_RETUNING;
2683
2f4cbb3d 2684 return ret;
d129bceb
PO		 2685}
2686
b8c86fc5 2687EXPORT_SYMBOL_GPL(sdhci_resume_host);
66fd8ad5
AH		 2688
2689static int sdhci_runtime_pm_get(struct sdhci_host *host)
2690{
2691 return pm_runtime_get_sync(host->mmc->parent);
2692}
2693
2694static int sdhci_runtime_pm_put(struct sdhci_host *host)
2695{
2696 pm_runtime_mark_last_busy(host->mmc->parent);
2697 return pm_runtime_put_autosuspend(host->mmc->parent);
2698}
2699
f0710a55
AH		 2700static void sdhci_runtime_pm_bus_on(struct sdhci_host *host)
2701{
2702 if (host->runtime_suspended || host->bus_on)
2703 return;
2704 host->bus_on = true;
2705 pm_runtime_get_noresume(host->mmc->parent);
2706}
2707
2708static void sdhci_runtime_pm_bus_off(struct sdhci_host *host)
2709{
2710 if (host->runtime_suspended || !host->bus_on)
2711 return;
2712 host->bus_on = false;
2713 pm_runtime_put_noidle(host->mmc->parent);
2714}
2715
66fd8ad5
AH		 2716int sdhci_runtime_suspend_host(struct sdhci_host *host)
2717{
2718 unsigned long flags;
66fd8ad5
AH		 2719
2720 /* Disable tuning since we are suspending */
973905fe 2721 if (host->flags & SDHCI_USING_RETUNING_TIMER) {
66fd8ad5
AH		 2722 del_timer_sync(&host->tuning_timer);
2723 host->flags &= ~SDHCI_NEEDS_RETUNING;
2724 }
2725
2726 spin_lock_irqsave(&host->lock, flags);
b537f94c
RK		 2727 host->ier &= SDHCI_INT_CARD_INT;
2728 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2729 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
66fd8ad5
AH		 2730 spin_unlock_irqrestore(&host->lock, flags);
2731
781e989c 2732 synchronize_hardirq(host->irq);
66fd8ad5
AH		 2733
2734 spin_lock_irqsave(&host->lock, flags);
2735 host->runtime_suspended = true;
2736 spin_unlock_irqrestore(&host->lock, flags);
2737
8a125bad 2738 return 0;
66fd8ad5
AH		 2739}
2740EXPORT_SYMBOL_GPL(sdhci_runtime_suspend_host);
2741
2742int sdhci_runtime_resume_host(struct sdhci_host *host)
2743{
2744 unsigned long flags;
8a125bad 2745 int host_flags = host->flags;
66fd8ad5
AH		 2746
2747 if (host_flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2748 if (host->ops->enable_dma)
2749 host->ops->enable_dma(host);
2750 }
2751
2752 sdhci_init(host, 0);
2753
2754 /* Force clock and power re-program */
2755 host->pwr = 0;
2756 host->clock = 0;
2757 sdhci_do_set_ios(host, &host->mmc->ios);
2758
2759 sdhci_do_start_signal_voltage_switch(host, &host->mmc->ios);
52983382
KL		 2760 if ((host_flags & SDHCI_PV_ENABLED) &&
2761 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN)) {
2762 spin_lock_irqsave(&host->lock, flags);
2763 sdhci_enable_preset_value(host, true);
2764 spin_unlock_irqrestore(&host->lock, flags);
2765 }
66fd8ad5
AH		 2766
2767 /* Set the re-tuning expiration flag */
973905fe 2768 if (host->flags & SDHCI_USING_RETUNING_TIMER)
66fd8ad5
AH		 2769 host->flags |= SDHCI_NEEDS_RETUNING;
2770
2771 spin_lock_irqsave(&host->lock, flags);
2772
2773 host->runtime_suspended = false;
2774
2775 /* Enable SDIO IRQ */
ef104333 2776 if (host->flags & SDHCI_SDIO_IRQ_ENABLED)
66fd8ad5
AH		 2777 sdhci_enable_sdio_irq_nolock(host, true);
2778
2779 /* Enable Card Detection */
2780 sdhci_enable_card_detection(host);
2781
2782 spin_unlock_irqrestore(&host->lock, flags);
2783
8a125bad 2784 return 0;
66fd8ad5
AH		 2785}
2786EXPORT_SYMBOL_GPL(sdhci_runtime_resume_host);
2787
162d6f98 2788#endif /* CONFIG_PM */
66fd8ad5 2789
d129bceb
PO		 2790/*****************************************************************************\
2791 * *
b8c86fc5 2792 * Device allocation/registration *
d129bceb
PO		 2793 * *
2794\*****************************************************************************/
2795
b8c86fc5
PO		 2796struct sdhci_host *sdhci_alloc_host(struct device *dev,
2797 size_t priv_size)
d129bceb 2798{
d129bceb
PO		 2799 struct mmc_host *mmc;
2800 struct sdhci_host *host;
2801
b8c86fc5 2802 WARN_ON(dev == NULL);
d129bceb 2803
b8c86fc5 2804 mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev);
d129bceb 2805 if (!mmc)
b8c86fc5 2806 return ERR_PTR(-ENOMEM);
d129bceb
PO		 2807
2808 host = mmc_priv(mmc);
2809 host->mmc = mmc;
2810
b8c86fc5
PO		 2811 return host;
2812}
8a4da143 2813
b8c86fc5 2814EXPORT_SYMBOL_GPL(sdhci_alloc_host);
d129bceb 2815
b8c86fc5
PO		 2816int sdhci_add_host(struct sdhci_host *host)
2817{
2818 struct mmc_host *mmc;
bd6a8c30 2819 u32 caps[2] = {0, 0};
f2119df6
AN		 2820 u32 max_current_caps;
2821 unsigned int ocr_avail;
f5fa92e5 2822 unsigned int override_timeout_clk;
b8c86fc5 2823 int ret;
d129bceb 2824
b8c86fc5
PO		 2825 WARN_ON(host == NULL);
2826 if (host == NULL)
2827 return -EINVAL;
d129bceb 2828
b8c86fc5 2829 mmc = host->mmc;
d129bceb 2830
b8c86fc5
PO		 2831 if (debug_quirks)
2832 host->quirks = debug_quirks;
66fd8ad5
AH		 2833 if (debug_quirks2)
2834 host->quirks2 = debug_quirks2;
d129bceb 2835
f5fa92e5
AH		 2836 override_timeout_clk = host->timeout_clk;
2837
03231f9b 2838 sdhci_do_reset(host, SDHCI_RESET_ALL);
d96649ed 2839
4e4141a5 2840 host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
2134a922
PO		 2841 host->version = (host->version & SDHCI_SPEC_VER_MASK)
2842 >> SDHCI_SPEC_VER_SHIFT;
85105c53 2843 if (host->version > SDHCI_SPEC_300) {
a3c76eb9 2844 pr_err("%s: Unknown controller version (%d). "
b69c9058 2845 "You may experience problems.\n", mmc_hostname(mmc),
2134a922 2846 host->version);
4a965505
PO		 2847 }
2848
f2119df6 2849 caps[0] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ? host->caps :
ccc92c23 2850 sdhci_readl(host, SDHCI_CAPABILITIES);
d129bceb 2851
bd6a8c30
PR		 2852 if (host->version >= SDHCI_SPEC_300)
2853 caps[1] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ?
2854 host->caps1 :
2855 sdhci_readl(host, SDHCI_CAPABILITIES_1);
f2119df6 2856
b8c86fc5 2857 if (host->quirks & SDHCI_QUIRK_FORCE_DMA)
a13abc7b 2858 host->flags |= SDHCI_USE_SDMA;
f2119df6 2859 else if (!(caps[0] & SDHCI_CAN_DO_SDMA))
a13abc7b 2860 DBG("Controller doesn't have SDMA capability\n");
67435274 2861 else
a13abc7b 2862 host->flags |= SDHCI_USE_SDMA;
d129bceb 2863
b8c86fc5 2864 if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
a13abc7b 2865 (host->flags & SDHCI_USE_SDMA)) {
cee687ce 2866 DBG("Disabling DMA as it is marked broken\n");
a13abc7b 2867 host->flags &= ~SDHCI_USE_SDMA;
7c168e3d
FT		 2868 }
2869
f2119df6
AN		 2870 if ((host->version >= SDHCI_SPEC_200) &&
2871 (caps[0] & SDHCI_CAN_DO_ADMA2))
a13abc7b 2872 host->flags |= SDHCI_USE_ADMA;
2134a922
PO		 2873
2874 if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) &&
2875 (host->flags & SDHCI_USE_ADMA)) {
2876 DBG("Disabling ADMA as it is marked broken\n");
2877 host->flags &= ~SDHCI_USE_ADMA;
2878 }
2879
e57a5f61
AH		 2880 /*
2881 * It is assumed that a 64-bit capable device has set a 64-bit DMA mask
2882 * and *must* do 64-bit DMA. A driver has the opportunity to change
2883 * that during the first call to ->enable_dma(). Similarly
2884 * SDHCI_QUIRK2_BROKEN_64_BIT_DMA must be left to the drivers to
2885 * implement.
2886 */
2887 if (sdhci_readl(host, SDHCI_CAPABILITIES) & SDHCI_CAN_64BIT)
2888 host->flags |= SDHCI_USE_64_BIT_DMA;
2889
a13abc7b 2890 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
b8c86fc5
PO		 2891 if (host->ops->enable_dma) {
2892 if (host->ops->enable_dma(host)) {
6606110d 2893 pr_warn("%s: No suitable DMA available - falling back to PIO\n",
b8c86fc5 2894 mmc_hostname(mmc));
a13abc7b
RR		 2895 host->flags &=
2896 ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
b8c86fc5 2897 }
d129bceb
PO		 2898 }
2899 }
2900
e57a5f61
AH		 2901 /* SDMA does not support 64-bit DMA */
2902 if (host->flags & SDHCI_USE_64_BIT_DMA)
2903 host->flags &= ~SDHCI_USE_SDMA;
2904
2134a922
PO		 2905 if (host->flags & SDHCI_USE_ADMA) {
2906 /*
76fe379a
AH		 2907 * The DMA descriptor table size is calculated as the maximum
2908 * number of segments times 2, to allow for an alignment
2909 * descriptor for each segment, plus 1 for a nop end descriptor,
2910 * all multipled by the descriptor size.
2134a922 2911 */
e57a5f61
AH		 2912 if (host->flags & SDHCI_USE_64_BIT_DMA) {
2913 host->adma_table_sz = (SDHCI_MAX_SEGS * 2 + 1) *
2914 SDHCI_ADMA2_64_DESC_SZ;
2915 host->align_buffer_sz = SDHCI_MAX_SEGS *
2916 SDHCI_ADMA2_64_ALIGN;
2917 host->desc_sz = SDHCI_ADMA2_64_DESC_SZ;
2918 host->align_sz = SDHCI_ADMA2_64_ALIGN;
2919 host->align_mask = SDHCI_ADMA2_64_ALIGN - 1;
2920 } else {
2921 host->adma_table_sz = (SDHCI_MAX_SEGS * 2 + 1) *
2922 SDHCI_ADMA2_32_DESC_SZ;
2923 host->align_buffer_sz = SDHCI_MAX_SEGS *
2924 SDHCI_ADMA2_32_ALIGN;
2925 host->desc_sz = SDHCI_ADMA2_32_DESC_SZ;
2926 host->align_sz = SDHCI_ADMA2_32_ALIGN;
2927 host->align_mask = SDHCI_ADMA2_32_ALIGN - 1;
2928 }
4efaa6fb 2929 host->adma_table = dma_alloc_coherent(mmc_dev(mmc),
76fe379a 2930 host->adma_table_sz,
4efaa6fb
AH		 2931 &host->adma_addr,
2932 GFP_KERNEL);
76fe379a 2933 host->align_buffer = kmalloc(host->align_buffer_sz, GFP_KERNEL);
4efaa6fb 2934 if (!host->adma_table || !host->align_buffer) {
76fe379a 2935 dma_free_coherent(mmc_dev(mmc), host->adma_table_sz,
4efaa6fb 2936 host->adma_table, host->adma_addr);
2134a922 2937 kfree(host->align_buffer);
6606110d 2938 pr_warn("%s: Unable to allocate ADMA buffers - falling back to standard DMA\n",
2134a922
PO		 2939 mmc_hostname(mmc));
2940 host->flags &= ~SDHCI_USE_ADMA;
4efaa6fb 2941 host->adma_table = NULL;
d1e49f77 2942 host->align_buffer = NULL;
76fe379a 2943 } else if (host->adma_addr & host->align_mask) {
6606110d
JP		 2944 pr_warn("%s: unable to allocate aligned ADMA descriptor\n",
2945 mmc_hostname(mmc));
d1e49f77 2946 host->flags &= ~SDHCI_USE_ADMA;
76fe379a 2947 dma_free_coherent(mmc_dev(mmc), host->adma_table_sz,
4efaa6fb 2948 host->adma_table, host->adma_addr);
d1e49f77 2949 kfree(host->align_buffer);
4efaa6fb 2950 host->adma_table = NULL;
d1e49f77 2951 host->align_buffer = NULL;
2134a922
PO		 2952 }
2953 }
2954
7659150c
PO		 2955 /*
2956 * If we use DMA, then it's up to the caller to set the DMA
2957 * mask, but PIO does not need the hw shim so we set a new
2958 * mask here in that case.
2959 */
a13abc7b 2960 if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) {
7659150c 2961 host->dma_mask = DMA_BIT_MASK(64);
4e743f1f 2962 mmc_dev(mmc)->dma_mask = &host->dma_mask;
7659150c 2963 }
d129bceb 2964
c4687d5f 2965 if (host->version >= SDHCI_SPEC_300)
f2119df6 2966 host->max_clk = (caps[0] & SDHCI_CLOCK_V3_BASE_MASK)
c4687d5f
ZG		 2967 >> SDHCI_CLOCK_BASE_SHIFT;
2968 else
f2119df6 2969 host->max_clk = (caps[0] & SDHCI_CLOCK_BASE_MASK)
c4687d5f
ZG		 2970 >> SDHCI_CLOCK_BASE_SHIFT;
2971
4240ff0a 2972 host->max_clk *= 1000000;
f27f47ef
AV		 2973 if (host->max_clk == 0 || host->quirks &
2974 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) {
4240ff0a 2975 if (!host->ops->get_max_clock) {
a3c76eb9 2976 pr_err("%s: Hardware doesn't specify base clock "
4240ff0a
BD		 2977 "frequency.\n", mmc_hostname(mmc));
2978 return -ENODEV;
2979 }
2980 host->max_clk = host->ops->get_max_clock(host);
8ef1a143 2981 }
d129bceb 2982
c3ed3877
AN		 2983 /*
2984 * In case of Host Controller v3.00, find out whether clock
2985 * multiplier is supported.
2986 */
2987 host->clk_mul = (caps[1] & SDHCI_CLOCK_MUL_MASK) >>
2988 SDHCI_CLOCK_MUL_SHIFT;
2989
2990 /*
2991 * In case the value in Clock Multiplier is 0, then programmable
2992 * clock mode is not supported, otherwise the actual clock
2993 * multiplier is one more than the value of Clock Multiplier
2994 * in the Capabilities Register.
2995 */
2996 if (host->clk_mul)
2997 host->clk_mul += 1;
2998
d129bceb
PO		 2999 /*
3000 * Set host parameters.
3001 */
3002 mmc->ops = &sdhci_ops;
c3ed3877 3003 mmc->f_max = host->max_clk;
ce5f036b 3004 if (host->ops->get_min_clock)
a9e58f25 3005 mmc->f_min = host->ops->get_min_clock(host);
c3ed3877
AN		 3006 else if (host->version >= SDHCI_SPEC_300) {
3007 if (host->clk_mul) {
3008 mmc->f_min = (host->max_clk * host->clk_mul) / 1024;
3009 mmc->f_max = host->max_clk * host->clk_mul;
3010 } else
3011 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300;
3012 } else
0397526d 3013 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200;
15ec4461 3014
28aab053
AD		 3015 if (!(host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) {
3016 host->timeout_clk = (caps[0] & SDHCI_TIMEOUT_CLK_MASK) >>
3017 SDHCI_TIMEOUT_CLK_SHIFT;
3018 if (host->timeout_clk == 0) {
3019 if (host->ops->get_timeout_clock) {
3020 host->timeout_clk =
3021 host->ops->get_timeout_clock(host);
3022 } else {
3023 pr_err("%s: Hardware doesn't specify timeout clock frequency.\n",
3024 mmc_hostname(mmc));
3025 return -ENODEV;
3026 }
272308ca 3027 }
272308ca 3028
28aab053
AD		 3029 if (caps[0] & SDHCI_TIMEOUT_CLK_UNIT)
3030 host->timeout_clk *= 1000;
272308ca 3031
28aab053 3032 mmc->max_busy_timeout = host->ops->get_max_timeout_count ?
a6ff5aeb 3033 host->ops->get_max_timeout_count(host) : 1 << 27;
28aab053
AD		 3034 mmc->max_busy_timeout /= host->timeout_clk;
3035 }
58d1246d 3036
f5fa92e5
AH		 3037 if (override_timeout_clk)
3038 host->timeout_clk = override_timeout_clk;
3039
e89d456f 3040 mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_ERASE | MMC_CAP_CMD23;
781e989c 3041 mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD;
e89d456f
AW		 3042
3043 if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12)
3044 host->flags |= SDHCI_AUTO_CMD12;
5fe23c7f 3045
8edf6371 3046 /* Auto-CMD23 stuff only works in ADMA or PIO. */
4f3d3e9b 3047 if ((host->version >= SDHCI_SPEC_300) &&
8edf6371 3048 ((host->flags & SDHCI_USE_ADMA) ||
4f3d3e9b 3049 !(host->flags & SDHCI_USE_SDMA))) {
8edf6371
AW		 3050 host->flags |= SDHCI_AUTO_CMD23;
3051 DBG("%s: Auto-CMD23 available\n", mmc_hostname(mmc));
3052 } else {
3053 DBG("%s: Auto-CMD23 unavailable\n", mmc_hostname(mmc));
3054 }
3055
15ec4461
PR		 3056 /*
3057 * A controller may support 8-bit width, but the board itself
3058 * might not have the pins brought out. Boards that support
3059 * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in
3060 * their platform code before calling sdhci_add_host(), and we
3061 * won't assume 8-bit width for hosts without that CAP.
3062 */
5fe23c7f 3063 if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA))
15ec4461 3064 mmc->caps |= MMC_CAP_4_BIT_DATA;
d129bceb 3065
63ef5d8c
JH		 3066 if (host->quirks2 & SDHCI_QUIRK2_HOST_NO_CMD23)
3067 mmc->caps &= ~MMC_CAP_CMD23;
3068
f2119df6 3069 if (caps[0] & SDHCI_CAN_DO_HISPD)
a29e7e18 3070 mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
cd9277c0 3071
176d1ed4 3072 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) &&
4e743f1f 3073 !(mmc->caps & MMC_CAP_NONREMOVABLE))
68d1fb7e
AV		 3074 mmc->caps |= MMC_CAP_NEEDS_POLL;
3075
3a48edc4
TK		 3076 /* If there are external regulators, get them */
3077 if (mmc_regulator_get_supply(mmc) == -EPROBE_DEFER)
3078 return -EPROBE_DEFER;
3079
6231f3de 3080 /* If vqmmc regulator and no 1.8V signalling, then there's no UHS */
3a48edc4
TK		 3081 if (!IS_ERR(mmc->supply.vqmmc)) {
3082 ret = regulator_enable(mmc->supply.vqmmc);
3083 if (!regulator_is_supported_voltage(mmc->supply.vqmmc, 1700000,
3084 1950000))
8363c374
KL		 3085 caps[1] &= ~(SDHCI_SUPPORT_SDR104 |
3086 SDHCI_SUPPORT_SDR50 |
3087 SDHCI_SUPPORT_DDR50);
a3361aba
CB		 3088 if (ret) {
3089 pr_warn("%s: Failed to enable vqmmc regulator: %d\n",
3090 mmc_hostname(mmc), ret);
4bb74313 3091 mmc->supply.vqmmc = ERR_PTR(-EINVAL);
a3361aba 3092 }
8363c374 3093 }
6231f3de 3094
6a66180a
DD		 3095 if (host->quirks2 & SDHCI_QUIRK2_NO_1_8_V)
3096 caps[1] &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
3097 SDHCI_SUPPORT_DDR50);
3098
4188bba0
AC		 3099 /* Any UHS-I mode in caps implies SDR12 and SDR25 support. */
3100 if (caps[1] & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
3101 SDHCI_SUPPORT_DDR50))
f2119df6
AN		 3102 mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;
3103
3104 /* SDR104 supports also implies SDR50 support */
156e14b1 3105 if (caps[1] & SDHCI_SUPPORT_SDR104) {
f2119df6 3106 mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50;
156e14b1
GC		 3107 /* SD3.0: SDR104 is supported so (for eMMC) the caps2
3108 * field can be promoted to support HS200.
3109 */
549c0b18 3110 if (!(host->quirks2 & SDHCI_QUIRK2_BROKEN_HS200))
13868bf2 3111 mmc->caps2 |= MMC_CAP2_HS200;
156e14b1 3112 } else if (caps[1] & SDHCI_SUPPORT_SDR50)
f2119df6
AN		 3113 mmc->caps |= MMC_CAP_UHS_SDR50;
3114
e9fb05d5
AH		 3115 if (host->quirks2 & SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 &&
3116 (caps[1] & SDHCI_SUPPORT_HS400))
3117 mmc->caps2 |= MMC_CAP2_HS400;
3118
549c0b18
AH		 3119 if ((mmc->caps2 & MMC_CAP2_HSX00_1_2V) &&
3120 (IS_ERR(mmc->supply.vqmmc) ||
3121 !regulator_is_supported_voltage(mmc->supply.vqmmc, 1100000,
3122 1300000)))
3123 mmc->caps2 &= ~MMC_CAP2_HSX00_1_2V;
3124
9107ebbf
MC		 3125 if ((caps[1] & SDHCI_SUPPORT_DDR50) &&
3126 !(host->quirks2 & SDHCI_QUIRK2_BROKEN_DDR50))
f2119df6
AN		 3127 mmc->caps |= MMC_CAP_UHS_DDR50;
3128
069c9f14 3129 /* Does the host need tuning for SDR50? */
b513ea25
AN		 3130 if (caps[1] & SDHCI_USE_SDR50_TUNING)
3131 host->flags |= SDHCI_SDR50_NEEDS_TUNING;
3132
156e14b1 3133 /* Does the host need tuning for SDR104 / HS200? */
069c9f14 3134 if (mmc->caps2 & MMC_CAP2_HS200)
156e14b1 3135 host->flags |= SDHCI_SDR104_NEEDS_TUNING;
069c9f14 3136
d6d50a15
AN		 3137 /* Driver Type(s) (A, C, D) supported by the host */
3138 if (caps[1] & SDHCI_DRIVER_TYPE_A)
3139 mmc->caps |= MMC_CAP_DRIVER_TYPE_A;
3140 if (caps[1] & SDHCI_DRIVER_TYPE_C)
3141 mmc->caps |= MMC_CAP_DRIVER_TYPE_C;
3142 if (caps[1] & SDHCI_DRIVER_TYPE_D)
3143 mmc->caps |= MMC_CAP_DRIVER_TYPE_D;
3144
cf2b5eea
AN		 3145 /* Initial value for re-tuning timer count */
3146 host->tuning_count = (caps[1] & SDHCI_RETUNING_TIMER_COUNT_MASK) >>
3147 SDHCI_RETUNING_TIMER_COUNT_SHIFT;
3148
3149 /*
3150 * In case Re-tuning Timer is not disabled, the actual value of
3151 * re-tuning timer will be 2 ^ (n - 1).
3152 */
3153 if (host->tuning_count)
3154 host->tuning_count = 1 << (host->tuning_count - 1);
3155
3156 /* Re-tuning mode supported by the Host Controller */
3157 host->tuning_mode = (caps[1] & SDHCI_RETUNING_MODE_MASK) >>
3158 SDHCI_RETUNING_MODE_SHIFT;
3159
8f230f45 3160 ocr_avail = 0;
bad37e1a 3161
f2119df6
AN		 3162 /*
3163 * According to SD Host Controller spec v3.00, if the Host System
3164 * can afford more than 150mA, Host Driver should set XPC to 1. Also
3165 * the value is meaningful only if Voltage Support in the Capabilities
3166 * register is set. The actual current value is 4 times the register
3167 * value.
3168 */
3169 max_current_caps = sdhci_readl(host, SDHCI_MAX_CURRENT);
3a48edc4 3170 if (!max_current_caps && !IS_ERR(mmc->supply.vmmc)) {
ae906037 3171 int curr = regulator_get_current_limit(mmc->supply.vmmc);
bad37e1a
PR		 3172 if (curr > 0) {
3173
3174 /* convert to SDHCI_MAX_CURRENT format */
3175 curr = curr/1000; /* convert to mA */
3176 curr = curr/SDHCI_MAX_CURRENT_MULTIPLIER;
3177
3178 curr = min_t(u32, curr, SDHCI_MAX_CURRENT_LIMIT);
3179 max_current_caps =
3180 (curr << SDHCI_MAX_CURRENT_330_SHIFT) |
3181 (curr << SDHCI_MAX_CURRENT_300_SHIFT) |
3182 (curr << SDHCI_MAX_CURRENT_180_SHIFT);
3183 }
3184 }
f2119df6
AN		 3185
3186 if (caps[0] & SDHCI_CAN_VDD_330) {
8f230f45 3187 ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34;
f2119df6 3188
55c4665e 3189 mmc->max_current_330 = ((max_current_caps &
f2119df6
AN		 3190 SDHCI_MAX_CURRENT_330_MASK) >>
3191 SDHCI_MAX_CURRENT_330_SHIFT) *
3192 SDHCI_MAX_CURRENT_MULTIPLIER;
f2119df6
AN		 3193 }
3194 if (caps[0] & SDHCI_CAN_VDD_300) {
8f230f45 3195 ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31;
f2119df6 3196
55c4665e 3197 mmc->max_current_300 = ((max_current_caps &
f2119df6
AN		 3198 SDHCI_MAX_CURRENT_300_MASK) >>
3199 SDHCI_MAX_CURRENT_300_SHIFT) *
3200 SDHCI_MAX_CURRENT_MULTIPLIER;
f2119df6
AN		 3201 }
3202 if (caps[0] & SDHCI_CAN_VDD_180) {
8f230f45
TI		 3203 ocr_avail |= MMC_VDD_165_195;
3204
55c4665e 3205 mmc->max_current_180 = ((max_current_caps &
f2119df6
AN		 3206 SDHCI_MAX_CURRENT_180_MASK) >>
3207 SDHCI_MAX_CURRENT_180_SHIFT) *
3208 SDHCI_MAX_CURRENT_MULTIPLIER;
f2119df6
AN		 3209 }
3210
52221610 3211 /* If OCR set by external regulators, use it instead */
3a48edc4 3212 if (mmc->ocr_avail)
52221610 3213 ocr_avail = mmc->ocr_avail;
3a48edc4 3214
c0b887b6 3215 if (host->ocr_mask)
3a48edc4 3216 ocr_avail &= host->ocr_mask;
c0b887b6 3217
8f230f45
TI		 3218 mmc->ocr_avail = ocr_avail;
3219 mmc->ocr_avail_sdio = ocr_avail;
3220 if (host->ocr_avail_sdio)
3221 mmc->ocr_avail_sdio &= host->ocr_avail_sdio;
3222 mmc->ocr_avail_sd = ocr_avail;
3223 if (host->ocr_avail_sd)
3224 mmc->ocr_avail_sd &= host->ocr_avail_sd;
3225 else /* normal SD controllers don't support 1.8V */
3226 mmc->ocr_avail_sd &= ~MMC_VDD_165_195;
3227 mmc->ocr_avail_mmc = ocr_avail;
3228 if (host->ocr_avail_mmc)
3229 mmc->ocr_avail_mmc &= host->ocr_avail_mmc;
146ad66e
PO		 3230
3231 if (mmc->ocr_avail == 0) {
a3c76eb9 3232 pr_err("%s: Hardware doesn't report any "
b69c9058 3233 "support voltages.\n", mmc_hostname(mmc));
b8c86fc5 3234 return -ENODEV;
146ad66e
PO		 3235 }
3236
d129bceb
PO		 3237 spin_lock_init(&host->lock);
3238
3239 /*
2134a922
PO		 3240 * Maximum number of segments. Depends on if the hardware
3241 * can do scatter/gather or not.
d129bceb 3242 */
2134a922 3243 if (host->flags & SDHCI_USE_ADMA)
4fb213f8 3244 mmc->max_segs = SDHCI_MAX_SEGS;
a13abc7b 3245 else if (host->flags & SDHCI_USE_SDMA)
a36274e0 3246 mmc->max_segs = 1;
2134a922 3247 else /* PIO */
4fb213f8 3248 mmc->max_segs = SDHCI_MAX_SEGS;
d129bceb
PO		 3249
3250 /*
ac00531d
AH		 3251 * Maximum number of sectors in one transfer. Limited by SDMA boundary
3252 * size (512KiB). Note some tuning modes impose a 4MiB limit, but this
3253 * is less anyway.
d129bceb 3254 */
55db890a 3255 mmc->max_req_size = 524288;
d129bceb
PO		 3256
3257 /*
3258 * Maximum segment size. Could be one segment with the maximum number
2134a922
PO		 3259 * of bytes. When doing hardware scatter/gather, each entry cannot
3260 * be larger than 64 KiB though.
d129bceb 3261 */
30652aa3
OJ		 3262 if (host->flags & SDHCI_USE_ADMA) {
3263 if (host->quirks & SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC)
3264 mmc->max_seg_size = 65535;
3265 else
3266 mmc->max_seg_size = 65536;
3267 } else {
2134a922 3268 mmc->max_seg_size = mmc->max_req_size;
30652aa3 3269 }
d129bceb 3270
fe4a3c7a
PO		 3271 /*
3272 * Maximum block size. This varies from controller to controller and
3273 * is specified in the capabilities register.
3274 */
0633f654
AV		 3275 if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) {
3276 mmc->max_blk_size = 2;
3277 } else {
f2119df6 3278 mmc->max_blk_size = (caps[0] & SDHCI_MAX_BLOCK_MASK) >>
0633f654
AV		 3279 SDHCI_MAX_BLOCK_SHIFT;
3280 if (mmc->max_blk_size >= 3) {
6606110d
JP		 3281 pr_warn("%s: Invalid maximum block size, assuming 512 bytes\n",
3282 mmc_hostname(mmc));
0633f654
AV		 3283 mmc->max_blk_size = 0;
3284 }
3285 }
3286
3287 mmc->max_blk_size = 512 << mmc->max_blk_size;
fe4a3c7a 3288
55db890a
PO		 3289 /*
3290 * Maximum block count.
3291 */
1388eefd 3292 mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
55db890a 3293
d129bceb
PO		 3294 /*
3295 * Init tasklets.
3296 */
d129bceb
PO		 3297 tasklet_init(&host->finish_tasklet,
3298 sdhci_tasklet_finish, (unsigned long)host);
3299
e4cad1b5 3300 setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host);
d129bceb 3301
cf2b5eea 3302 if (host->version >= SDHCI_SPEC_300) {
b513ea25
AN		 3303 init_waitqueue_head(&host->buf_ready_int);
3304
cf2b5eea
AN		 3305 /* Initialize re-tuning timer */
3306 init_timer(&host->tuning_timer);
3307 host->tuning_timer.data = (unsigned long)host;
3308 host->tuning_timer.function = sdhci_tuning_timer;
3309 }
3310
2af502ca
SG		 3311 sdhci_init(host, 0);
3312
781e989c
RK		 3313 ret = request_threaded_irq(host->irq, sdhci_irq, sdhci_thread_irq,
3314 IRQF_SHARED, mmc_hostname(mmc), host);
0fc81ee3
MB		 3315 if (ret) {
3316 pr_err("%s: Failed to request IRQ %d: %d\n",
3317 mmc_hostname(mmc), host->irq, ret);
8ef1a143 3318 goto untasklet;
0fc81ee3 3319 }
d129bceb 3320
d129bceb
PO		 3321#ifdef CONFIG_MMC_DEBUG
3322 sdhci_dumpregs(host);
3323#endif
3324
f9134319 3325#ifdef SDHCI_USE_LEDS_CLASS
5dbace0c
HS		 3326 snprintf(host->led_name, sizeof(host->led_name),
3327 "%s::", mmc_hostname(mmc));
3328 host->led.name = host->led_name;
2f730fec
PO		 3329 host->led.brightness = LED_OFF;
3330 host->led.default_trigger = mmc_hostname(mmc);
3331 host->led.brightness_set = sdhci_led_control;
3332
b8c86fc5 3333 ret = led_classdev_register(mmc_dev(mmc), &host->led);
0fc81ee3
MB		 3334 if (ret) {
3335 pr_err("%s: Failed to register LED device: %d\n",
3336 mmc_hostname(mmc), ret);
2f730fec 3337 goto reset;
0fc81ee3 3338 }
2f730fec
PO		 3339#endif
3340
5f25a66f
PO		 3341 mmiowb();
3342
d129bceb
PO		 3343 mmc_add_host(mmc);
3344
a3c76eb9 3345 pr_info("%s: SDHCI controller on %s [%s] using %s\n",
d1b26863 3346 mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)),
e57a5f61
AH		 3347 (host->flags & SDHCI_USE_ADMA) ?
3348 (host->flags & SDHCI_USE_64_BIT_DMA) ? "ADMA 64-bit" : "ADMA" :
a13abc7b 3349 (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO");
d129bceb 3350
7260cf5e
AV		 3351 sdhci_enable_card_detection(host);
3352
d129bceb
PO		 3353 return 0;
3354
f9134319 3355#ifdef SDHCI_USE_LEDS_CLASS
2f730fec 3356reset:
03231f9b 3357 sdhci_do_reset(host, SDHCI_RESET_ALL);
b537f94c
RK		 3358 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
3359 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
2f730fec
PO		 3360 free_irq(host->irq, host);
3361#endif
8ef1a143 3362untasklet:
d129bceb 3363 tasklet_kill(&host->finish_tasklet);
d129bceb
PO		 3364
3365 return ret;
3366}
3367
b8c86fc5 3368EXPORT_SYMBOL_GPL(sdhci_add_host);
d129bceb 3369
1e72859e 3370void sdhci_remove_host(struct sdhci_host *host, int dead)
b8c86fc5 3371{
3a48edc4 3372 struct mmc_host *mmc = host->mmc;
1e72859e
PO		 3373 unsigned long flags;
3374
3375 if (dead) {
3376 spin_lock_irqsave(&host->lock, flags);
3377
3378 host->flags |= SDHCI_DEVICE_DEAD;
3379
3380 if (host->mrq) {
a3c76eb9 3381 pr_err("%s: Controller removed during "
4e743f1f 3382 " transfer!\n", mmc_hostname(mmc));
1e72859e
PO		 3383
3384 host->mrq->cmd->error = -ENOMEDIUM;
3385 tasklet_schedule(&host->finish_tasklet);
3386 }
3387
3388 spin_unlock_irqrestore(&host->lock, flags);
3389 }
3390
7260cf5e
AV		 3391 sdhci_disable_card_detection(host);
3392
4e743f1f 3393 mmc_remove_host(mmc);
d129bceb 3394
f9134319 3395#ifdef SDHCI_USE_LEDS_CLASS
2f730fec
PO		 3396 led_classdev_unregister(&host->led);
3397#endif
3398
1e72859e 3399 if (!dead)
03231f9b 3400 sdhci_do_reset(host, SDHCI_RESET_ALL);
d129bceb 3401
b537f94c
RK		 3402 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
3403 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
d129bceb
PO		 3404 free_irq(host->irq, host);
3405
3406 del_timer_sync(&host->timer);
3407
d129bceb 3408 tasklet_kill(&host->finish_tasklet);
2134a922 3409
3a48edc4
TK		 3410 if (!IS_ERR(mmc->supply.vqmmc))
3411 regulator_disable(mmc->supply.vqmmc);
6231f3de 3412
4efaa6fb 3413 if (host->adma_table)
76fe379a 3414 dma_free_coherent(mmc_dev(mmc), host->adma_table_sz,
4efaa6fb 3415 host->adma_table, host->adma_addr);
2134a922
PO		 3416 kfree(host->align_buffer);
3417
4efaa6fb 3418 host->adma_table = NULL;
2134a922 3419 host->align_buffer = NULL;
d129bceb
PO		 3420}
3421
b8c86fc5 3422EXPORT_SYMBOL_GPL(sdhci_remove_host);
d129bceb 3423
b8c86fc5 3424void sdhci_free_host(struct sdhci_host *host)
d129bceb 3425{
b8c86fc5 3426 mmc_free_host(host->mmc);
d129bceb
PO		 3427}
3428
b8c86fc5 3429EXPORT_SYMBOL_GPL(sdhci_free_host);
d129bceb
PO		 3430
3431/*****************************************************************************\
3432 * *
3433 * Driver init/exit *
3434 * *
3435\*****************************************************************************/
3436
3437static int __init sdhci_drv_init(void)
3438{
a3c76eb9 3439 pr_info(DRIVER_NAME
52fbf9c9 3440 ": Secure Digital Host Controller Interface driver\n");
a3c76eb9 3441 pr_info(DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
d129bceb 3442
b8c86fc5 3443 return 0;
d129bceb
PO		 3444}
3445
3446static void __exit sdhci_drv_exit(void)
3447{
d129bceb
PO		 3448}
3449
3450module_init(sdhci_drv_init);
3451module_exit(sdhci_drv_exit);
3452
df673b22 3453module_param(debug_quirks, uint, 0444);
66fd8ad5 3454module_param(debug_quirks2, uint, 0444);
67435274 3455
32710e8f 3456MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
b8c86fc5 3457MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver");
d129bceb 3458MODULE_LICENSE("GPL");
67435274 3459
df673b22 3460MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");
66fd8ad5 3461MODULE_PARM_DESC(debug_quirks2, "Force certain other quirks.");
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