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Linux 2.6.27
[mirror_ubuntu-artful-kernel.git] / drivers / mmc / host / sdhci.c
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d129bceb 1/*
70f10482 2 * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
d129bceb 3 *
b69c9058 4 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
d129bceb
PO		 5 *
6 * This program is free software; you can redistribute it and/or modify
643f720c
PO		 7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or (at
9 * your option) any later version.
84c46a53
PO		 10 *
11 * Thanks to the following companies for their support:
12 *
13 * - JMicron (hardware and technical support)
d129bceb
PO		 14 */
15
d129bceb
PO		 16#include <linux/delay.h>
17#include <linux/highmem.h>
b8c86fc5 18#include <linux/io.h>
d129bceb 19#include <linux/dma-mapping.h>
11763609 20#include <linux/scatterlist.h>
d129bceb 21
2f730fec
PO		 22#include <linux/leds.h>
23
d129bceb 24#include <linux/mmc/host.h>
d129bceb 25
d129bceb
PO		 26#include "sdhci.h"
27
28#define DRIVER_NAME "sdhci"
d129bceb 29
d129bceb 30#define DBG(f, x...) \
c6563178 31 pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
d129bceb 32
df673b22 33static unsigned int debug_quirks = 0;
67435274 34
d129bceb
PO		 35static void sdhci_prepare_data(struct sdhci_host *, struct mmc_data *);
36static void sdhci_finish_data(struct sdhci_host *);
37
38static void sdhci_send_command(struct sdhci_host *, struct mmc_command *);
39static void sdhci_finish_command(struct sdhci_host *);
40
41static void sdhci_dumpregs(struct sdhci_host *host)
42{
43 printk(KERN_DEBUG DRIVER_NAME ": ============== REGISTER DUMP ==============\n");
44
45 printk(KERN_DEBUG DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n",
46 readl(host->ioaddr + SDHCI_DMA_ADDRESS),
47 readw(host->ioaddr + SDHCI_HOST_VERSION));
48 printk(KERN_DEBUG DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n",
49 readw(host->ioaddr + SDHCI_BLOCK_SIZE),
50 readw(host->ioaddr + SDHCI_BLOCK_COUNT));
51 printk(KERN_DEBUG DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
52 readl(host->ioaddr + SDHCI_ARGUMENT),
53 readw(host->ioaddr + SDHCI_TRANSFER_MODE));
54 printk(KERN_DEBUG DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n",
55 readl(host->ioaddr + SDHCI_PRESENT_STATE),
56 readb(host->ioaddr + SDHCI_HOST_CONTROL));
57 printk(KERN_DEBUG DRIVER_NAME ": Power: 0x%08x | Blk gap: 0x%08x\n",
58 readb(host->ioaddr + SDHCI_POWER_CONTROL),
59 readb(host->ioaddr + SDHCI_BLOCK_GAP_CONTROL));
60 printk(KERN_DEBUG DRIVER_NAME ": Wake-up: 0x%08x | Clock: 0x%08x\n",
2df3b71b 61 readb(host->ioaddr + SDHCI_WAKE_UP_CONTROL),
d129bceb
PO		 62 readw(host->ioaddr + SDHCI_CLOCK_CONTROL));
63 printk(KERN_DEBUG DRIVER_NAME ": Timeout: 0x%08x | Int stat: 0x%08x\n",
64 readb(host->ioaddr + SDHCI_TIMEOUT_CONTROL),
65 readl(host->ioaddr + SDHCI_INT_STATUS));
66 printk(KERN_DEBUG DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
67 readl(host->ioaddr + SDHCI_INT_ENABLE),
68 readl(host->ioaddr + SDHCI_SIGNAL_ENABLE));
69 printk(KERN_DEBUG DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
70 readw(host->ioaddr + SDHCI_ACMD12_ERR),
71 readw(host->ioaddr + SDHCI_SLOT_INT_STATUS));
72 printk(KERN_DEBUG DRIVER_NAME ": Caps: 0x%08x | Max curr: 0x%08x\n",
73 readl(host->ioaddr + SDHCI_CAPABILITIES),
74 readl(host->ioaddr + SDHCI_MAX_CURRENT));
75
76 printk(KERN_DEBUG DRIVER_NAME ": ===========================================\n");
77}
78
79/*****************************************************************************\
80 * *
81 * Low level functions *
82 * *
83\*****************************************************************************/
84
85static void sdhci_reset(struct sdhci_host *host, u8 mask)
86{
e16514d8
PO		 87 unsigned long timeout;
88
b8c86fc5 89 if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
8a4da143
PO		 90 if (!(readl(host->ioaddr + SDHCI_PRESENT_STATE) &
91 SDHCI_CARD_PRESENT))
92 return;
93 }
94
d129bceb
PO		 95 writeb(mask, host->ioaddr + SDHCI_SOFTWARE_RESET);
96
e16514d8 97 if (mask & SDHCI_RESET_ALL)
d129bceb
PO		 98 host->clock = 0;
99
e16514d8
PO		 100 /* Wait max 100 ms */
101 timeout = 100;
102
103 /* hw clears the bit when it's done */
104 while (readb(host->ioaddr + SDHCI_SOFTWARE_RESET) & mask) {
105 if (timeout == 0) {
acf1da45 106 printk(KERN_ERR "%s: Reset 0x%x never completed.\n",
e16514d8
PO		 107 mmc_hostname(host->mmc), (int)mask);
108 sdhci_dumpregs(host);
109 return;
110 }
111 timeout--;
112 mdelay(1);
d129bceb
PO		 113 }
114}
115
116static void sdhci_init(struct sdhci_host *host)
117{
118 u32 intmask;
119
120 sdhci_reset(host, SDHCI_RESET_ALL);
121
3192a28f
PO		 122 intmask = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
123 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX |
124 SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT |
125 SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT |
a406f5a3 126 SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL |
2134a922
PO		 127 SDHCI_INT_DMA_END | SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE |
128 SDHCI_INT_ADMA_ERROR;
d129bceb
PO		 129
130 writel(intmask, host->ioaddr + SDHCI_INT_ENABLE);
131 writel(intmask, host->ioaddr + SDHCI_SIGNAL_ENABLE);
d129bceb
PO		 132}
133
134static void sdhci_activate_led(struct sdhci_host *host)
135{
136 u8 ctrl;
137
138 ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL);
139 ctrl |= SDHCI_CTRL_LED;
140 writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL);
141}
142
143static void sdhci_deactivate_led(struct sdhci_host *host)
144{
145 u8 ctrl;
146
147 ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL);
148 ctrl &= ~SDHCI_CTRL_LED;
149 writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL);
150}
151
2f730fec
PO		 152#ifdef CONFIG_LEDS_CLASS
153static void sdhci_led_control(struct led_classdev *led,
154 enum led_brightness brightness)
155{
156 struct sdhci_host *host = container_of(led, struct sdhci_host, led);
157 unsigned long flags;
158
159 spin_lock_irqsave(&host->lock, flags);
160
161 if (brightness == LED_OFF)
162 sdhci_deactivate_led(host);
163 else
164 sdhci_activate_led(host);
165
166 spin_unlock_irqrestore(&host->lock, flags);
167}
168#endif
169
d129bceb
PO		 170/*****************************************************************************\
171 * *
172 * Core functions *
173 * *
174\*****************************************************************************/
175
a406f5a3 176static void sdhci_read_block_pio(struct sdhci_host *host)
d129bceb 177{
7659150c
PO		 178 unsigned long flags;
179 size_t blksize, len, chunk;
180 u32 scratch;
181 u8 *buf;
d129bceb 182
a406f5a3 183 DBG("PIO reading\n");
d129bceb 184
a406f5a3 185 blksize = host->data->blksz;
7659150c 186 chunk = 0;
d129bceb 187
7659150c 188 local_irq_save(flags);
d129bceb 189
a406f5a3 190 while (blksize) {
7659150c
PO		 191 if (!sg_miter_next(&host->sg_miter))
192 BUG();
d129bceb 193
7659150c 194 len = min(host->sg_miter.length, blksize);
d129bceb 195
7659150c
PO		 196 blksize -= len;
197 host->sg_miter.consumed = len;
14d836e7 198
7659150c 199 buf = host->sg_miter.addr;
d129bceb 200
7659150c
PO		 201 while (len) {
202 if (chunk == 0) {
203 scratch = readl(host->ioaddr + SDHCI_BUFFER);
204 chunk = 4;
a406f5a3 205 }
7659150c
PO		 206
207 *buf = scratch & 0xFF;
208
209 buf++;
210 scratch >>= 8;
211 chunk--;
212 len--;
d129bceb 213 }
a406f5a3 214 }
7659150c
PO		 215
216 sg_miter_stop(&host->sg_miter);
217
218 local_irq_restore(flags);
a406f5a3 219}
d129bceb 220
a406f5a3
PO		 221static void sdhci_write_block_pio(struct sdhci_host *host)
222{
7659150c
PO		 223 unsigned long flags;
224 size_t blksize, len, chunk;
225 u32 scratch;
226 u8 *buf;
d129bceb 227
a406f5a3
PO		 228 DBG("PIO writing\n");
229
230 blksize = host->data->blksz;
7659150c
PO		 231 chunk = 0;
232 scratch = 0;
d129bceb 233
7659150c 234 local_irq_save(flags);
d129bceb 235
a406f5a3 236 while (blksize) {
7659150c
PO		 237 if (!sg_miter_next(&host->sg_miter))
238 BUG();
a406f5a3 239
7659150c
PO		 240 len = min(host->sg_miter.length, blksize);
241
242 blksize -= len;
243 host->sg_miter.consumed = len;
244
245 buf = host->sg_miter.addr;
d129bceb 246
7659150c
PO		 247 while (len) {
248 scratch |= (u32)*buf << (chunk * 8);
249
250 buf++;
251 chunk++;
252 len--;
253
254 if ((chunk == 4) || ((len == 0) && (blksize == 0))) {
255 writel(scratch, host->ioaddr + SDHCI_BUFFER);
256 chunk = 0;
257 scratch = 0;
d129bceb 258 }
d129bceb
PO		 259 }
260 }
7659150c
PO		 261
262 sg_miter_stop(&host->sg_miter);
263
264 local_irq_restore(flags);
a406f5a3
PO		 265}
266
267static void sdhci_transfer_pio(struct sdhci_host *host)
268{
269 u32 mask;
270
271 BUG_ON(!host->data);
272
7659150c 273 if (host->blocks == 0)
a406f5a3
PO		 274 return;
275
276 if (host->data->flags & MMC_DATA_READ)
277 mask = SDHCI_DATA_AVAILABLE;
278 else
279 mask = SDHCI_SPACE_AVAILABLE;
280
4a3cba32
PO		 281 /*
282 * Some controllers (JMicron JMB38x) mess up the buffer bits
283 * for transfers < 4 bytes. As long as it is just one block,
284 * we can ignore the bits.
285 */
286 if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) &&
287 (host->data->blocks == 1))
288 mask = ~0;
289
a406f5a3
PO		 290 while (readl(host->ioaddr + SDHCI_PRESENT_STATE) & mask) {
291 if (host->data->flags & MMC_DATA_READ)
292 sdhci_read_block_pio(host);
293 else
294 sdhci_write_block_pio(host);
d129bceb 295
7659150c
PO		 296 host->blocks--;
297 if (host->blocks == 0)
a406f5a3 298 break;
a406f5a3 299 }
d129bceb 300
a406f5a3 301 DBG("PIO transfer complete.\n");
d129bceb
PO		 302}
303
2134a922
PO		 304static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags)
305{
306 local_irq_save(*flags);
307 return kmap_atomic(sg_page(sg), KM_BIO_SRC_IRQ) + sg->offset;
308}
309
310static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags)
311{
312 kunmap_atomic(buffer, KM_BIO_SRC_IRQ);
313 local_irq_restore(*flags);
314}
315
8f1934ce 316static int sdhci_adma_table_pre(struct sdhci_host *host,
2134a922
PO		 317 struct mmc_data *data)
318{
319 int direction;
320
321 u8 *desc;
322 u8 *align;
323 dma_addr_t addr;
324 dma_addr_t align_addr;
325 int len, offset;
326
327 struct scatterlist *sg;
328 int i;
329 char *buffer;
330 unsigned long flags;
331
332 /*
333 * The spec does not specify endianness of descriptor table.
334 * We currently guess that it is LE.
335 */
336
337 if (data->flags & MMC_DATA_READ)
338 direction = DMA_FROM_DEVICE;
339 else
340 direction = DMA_TO_DEVICE;
341
342 /*
343 * The ADMA descriptor table is mapped further down as we
344 * need to fill it with data first.
345 */
346
347 host->align_addr = dma_map_single(mmc_dev(host->mmc),
348 host->align_buffer, 128 * 4, direction);
8d8bb39b 349 if (dma_mapping_error(mmc_dev(host->mmc), host->align_addr))
8f1934ce 350 goto fail;
2134a922
PO		 351 BUG_ON(host->align_addr & 0x3);
352
353 host->sg_count = dma_map_sg(mmc_dev(host->mmc),
354 data->sg, data->sg_len, direction);
8f1934ce
PO		 355 if (host->sg_count == 0)
356 goto unmap_align;
2134a922
PO		 357
358 desc = host->adma_desc;
359 align = host->align_buffer;
360
361 align_addr = host->align_addr;
362
363 for_each_sg(data->sg, sg, host->sg_count, i) {
364 addr = sg_dma_address(sg);
365 len = sg_dma_len(sg);
366
367 /*
368 * The SDHCI specification states that ADMA
369 * addresses must be 32-bit aligned. If they
370 * aren't, then we use a bounce buffer for
371 * the (up to three) bytes that screw up the
372 * alignment.
373 */
374 offset = (4 - (addr & 0x3)) & 0x3;
375 if (offset) {
376 if (data->flags & MMC_DATA_WRITE) {
377 buffer = sdhci_kmap_atomic(sg, &flags);
6cefd05f 378 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3));
2134a922
PO		 379 memcpy(align, buffer, offset);
380 sdhci_kunmap_atomic(buffer, &flags);
381 }
382
383 desc[7] = (align_addr >> 24) & 0xff;
384 desc[6] = (align_addr >> 16) & 0xff;
385 desc[5] = (align_addr >> 8) & 0xff;
386 desc[4] = (align_addr >> 0) & 0xff;
387
388 BUG_ON(offset > 65536);
389
390 desc[3] = (offset >> 8) & 0xff;
391 desc[2] = (offset >> 0) & 0xff;
392
393 desc[1] = 0x00;
394 desc[0] = 0x21; /* tran, valid */
395
396 align += 4;
397 align_addr += 4;
398
399 desc += 8;
400
401 addr += offset;
402 len -= offset;
403 }
404
405 desc[7] = (addr >> 24) & 0xff;
406 desc[6] = (addr >> 16) & 0xff;
407 desc[5] = (addr >> 8) & 0xff;
408 desc[4] = (addr >> 0) & 0xff;
409
410 BUG_ON(len > 65536);
411
412 desc[3] = (len >> 8) & 0xff;
413 desc[2] = (len >> 0) & 0xff;
414
415 desc[1] = 0x00;
416 desc[0] = 0x21; /* tran, valid */
417
418 desc += 8;
419
420 /*
421 * If this triggers then we have a calculation bug
422 * somewhere. :/
423 */
424 WARN_ON((desc - host->adma_desc) > (128 * 2 + 1) * 4);
425 }
426
427 /*
428 * Add a terminating entry.
429 */
430 desc[7] = 0;
431 desc[6] = 0;
432 desc[5] = 0;
433 desc[4] = 0;
434
435 desc[3] = 0;
436 desc[2] = 0;
437
438 desc[1] = 0x00;
439 desc[0] = 0x03; /* nop, end, valid */
440
441 /*
442 * Resync align buffer as we might have changed it.
443 */
444 if (data->flags & MMC_DATA_WRITE) {
445 dma_sync_single_for_device(mmc_dev(host->mmc),
446 host->align_addr, 128 * 4, direction);
447 }
448
449 host->adma_addr = dma_map_single(mmc_dev(host->mmc),
450 host->adma_desc, (128 * 2 + 1) * 4, DMA_TO_DEVICE);
980167b7 451 if (dma_mapping_error(mmc_dev(host->mmc), host->adma_addr))
8f1934ce 452 goto unmap_entries;
2134a922 453 BUG_ON(host->adma_addr & 0x3);
8f1934ce
PO		 454
455 return 0;
456
457unmap_entries:
458 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
459 data->sg_len, direction);
460unmap_align:
461 dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
462 128 * 4, direction);
463fail:
464 return -EINVAL;
2134a922
PO		 465}
466
467static void sdhci_adma_table_post(struct sdhci_host *host,
468 struct mmc_data *data)
469{
470 int direction;
471
472 struct scatterlist *sg;
473 int i, size;
474 u8 *align;
475 char *buffer;
476 unsigned long flags;
477
478 if (data->flags & MMC_DATA_READ)
479 direction = DMA_FROM_DEVICE;
480 else
481 direction = DMA_TO_DEVICE;
482
483 dma_unmap_single(mmc_dev(host->mmc), host->adma_addr,
484 (128 * 2 + 1) * 4, DMA_TO_DEVICE);
485
486 dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
487 128 * 4, direction);
488
489 if (data->flags & MMC_DATA_READ) {
490 dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
491 data->sg_len, direction);
492
493 align = host->align_buffer;
494
495 for_each_sg(data->sg, sg, host->sg_count, i) {
496 if (sg_dma_address(sg) & 0x3) {
497 size = 4 - (sg_dma_address(sg) & 0x3);
498
499 buffer = sdhci_kmap_atomic(sg, &flags);
6cefd05f 500 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3));
2134a922
PO		 501 memcpy(buffer, align, size);
502 sdhci_kunmap_atomic(buffer, &flags);
503
504 align += 4;
505 }
506 }
507 }
508
509 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
510 data->sg_len, direction);
511}
512
ee53ab5d 513static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_data *data)
d129bceb 514{
1c8cde92
PO		 515 u8 count;
516 unsigned target_timeout, current_timeout;
d129bceb 517
ee53ab5d
PO		 518 /*
519 * If the host controller provides us with an incorrect timeout
520 * value, just skip the check and use 0xE. The hardware may take
521 * longer to time out, but that's much better than having a too-short
522 * timeout value.
523 */
524 if ((host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL))
525 return 0xE;
e538fbe8 526
1c8cde92
PO		 527 /* timeout in us */
528 target_timeout = data->timeout_ns / 1000 +
529 data->timeout_clks / host->clock;
d129bceb 530
1c8cde92
PO		 531 /*
532 * Figure out needed cycles.
533 * We do this in steps in order to fit inside a 32 bit int.
534 * The first step is the minimum timeout, which will have a
535 * minimum resolution of 6 bits:
536 * (1) 2^13*1000 > 2^22,
537 * (2) host->timeout_clk < 2^16
538 * =>
539 * (1) / (2) > 2^6
540 */
541 count = 0;
542 current_timeout = (1 << 13) * 1000 / host->timeout_clk;
543 while (current_timeout < target_timeout) {
544 count++;
545 current_timeout <<= 1;
546 if (count >= 0xF)
547 break;
548 }
549
550 if (count >= 0xF) {
551 printk(KERN_WARNING "%s: Too large timeout requested!\n",
552 mmc_hostname(host->mmc));
553 count = 0xE;
554 }
555
ee53ab5d
PO		 556 return count;
557}
558
559static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_data *data)
560{
561 u8 count;
2134a922 562 u8 ctrl;
8f1934ce 563 int ret;
ee53ab5d
PO		 564
565 WARN_ON(host->data);
566
567 if (data == NULL)
568 return;
569
570 /* Sanity checks */
571 BUG_ON(data->blksz * data->blocks > 524288);
572 BUG_ON(data->blksz > host->mmc->max_blk_size);
573 BUG_ON(data->blocks > 65535);
574
575 host->data = data;
576 host->data_early = 0;
577
578 count = sdhci_calc_timeout(host, data);
1c8cde92 579 writeb(count, host->ioaddr + SDHCI_TIMEOUT_CONTROL);
d129bceb 580
c9fddbc4
PO		 581 if (host->flags & SDHCI_USE_DMA)
582 host->flags |= SDHCI_REQ_USE_DMA;
583
2134a922
PO		 584 /*
585 * FIXME: This doesn't account for merging when mapping the
586 * scatterlist.
587 */
588 if (host->flags & SDHCI_REQ_USE_DMA) {
589 int broken, i;
590 struct scatterlist *sg;
591
592 broken = 0;
593 if (host->flags & SDHCI_USE_ADMA) {
594 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
595 broken = 1;
596 } else {
597 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE)
598 broken = 1;
599 }
600
601 if (unlikely(broken)) {
602 for_each_sg(data->sg, sg, data->sg_len, i) {
603 if (sg->length & 0x3) {
604 DBG("Reverting to PIO because of "
605 "transfer size (%d)\n",
606 sg->length);
607 host->flags &= ~SDHCI_REQ_USE_DMA;
608 break;
609 }
610 }
611 }
c9fddbc4
PO		 612 }
613
614 /*
615 * The assumption here being that alignment is the same after
616 * translation to device address space.
617 */
2134a922
PO		 618 if (host->flags & SDHCI_REQ_USE_DMA) {
619 int broken, i;
620 struct scatterlist *sg;
621
622 broken = 0;
623 if (host->flags & SDHCI_USE_ADMA) {
624 /*
625 * As we use 3 byte chunks to work around
626 * alignment problems, we need to check this
627 * quirk.
628 */
629 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
630 broken = 1;
631 } else {
632 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR)
633 broken = 1;
634 }
635
636 if (unlikely(broken)) {
637 for_each_sg(data->sg, sg, data->sg_len, i) {
638 if (sg->offset & 0x3) {
639 DBG("Reverting to PIO because of "
640 "bad alignment\n");
641 host->flags &= ~SDHCI_REQ_USE_DMA;
642 break;
643 }
644 }
645 }
646 }
647
8f1934ce
PO		 648 if (host->flags & SDHCI_REQ_USE_DMA) {
649 if (host->flags & SDHCI_USE_ADMA) {
650 ret = sdhci_adma_table_pre(host, data);
651 if (ret) {
652 /*
653 * This only happens when someone fed
654 * us an invalid request.
655 */
656 WARN_ON(1);
ebd6d357 657 host->flags &= ~SDHCI_REQ_USE_DMA;
8f1934ce
PO		 658 } else {
659 writel(host->adma_addr,
660 host->ioaddr + SDHCI_ADMA_ADDRESS);
661 }
662 } else {
c8b3e02e 663 int sg_cnt;
8f1934ce 664
c8b3e02e 665 sg_cnt = dma_map_sg(mmc_dev(host->mmc),
8f1934ce
PO		 666 data->sg, data->sg_len,
667 (data->flags & MMC_DATA_READ) ?
668 DMA_FROM_DEVICE :
669 DMA_TO_DEVICE);
c8b3e02e 670 if (sg_cnt == 0) {
8f1934ce
PO		 671 /*
672 * This only happens when someone fed
673 * us an invalid request.
674 */
675 WARN_ON(1);
ebd6d357 676 host->flags &= ~SDHCI_REQ_USE_DMA;
8f1934ce 677 } else {
719a61b4 678 WARN_ON(sg_cnt != 1);
8f1934ce
PO		 679 writel(sg_dma_address(data->sg),
680 host->ioaddr + SDHCI_DMA_ADDRESS);
681 }
682 }
683 }
684
2134a922
PO		 685 /*
686 * Always adjust the DMA selection as some controllers
687 * (e.g. JMicron) can't do PIO properly when the selection
688 * is ADMA.
689 */
690 if (host->version >= SDHCI_SPEC_200) {
691 ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL);
692 ctrl &= ~SDHCI_CTRL_DMA_MASK;
693 if ((host->flags & SDHCI_REQ_USE_DMA) &&
694 (host->flags & SDHCI_USE_ADMA))
695 ctrl |= SDHCI_CTRL_ADMA32;
696 else
697 ctrl |= SDHCI_CTRL_SDMA;
698 writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL);
c9fddbc4
PO		 699 }
700
8f1934ce 701 if (!(host->flags & SDHCI_REQ_USE_DMA)) {
7659150c
PO		 702 sg_miter_start(&host->sg_miter,
703 data->sg, data->sg_len, SG_MITER_ATOMIC);
704 host->blocks = data->blocks;
d129bceb 705 }
c7fa9963 706
bab76961
PO		 707 /* We do not handle DMA boundaries, so set it to max (512 KiB) */
708 writew(SDHCI_MAKE_BLKSZ(7, data->blksz),
709 host->ioaddr + SDHCI_BLOCK_SIZE);
c7fa9963
PO		 710 writew(data->blocks, host->ioaddr + SDHCI_BLOCK_COUNT);
711}
712
713static void sdhci_set_transfer_mode(struct sdhci_host *host,
714 struct mmc_data *data)
715{
716 u16 mode;
717
c7fa9963
PO		 718 if (data == NULL)
719 return;
720
e538fbe8
PO		 721 WARN_ON(!host->data);
722
c7fa9963
PO		 723 mode = SDHCI_TRNS_BLK_CNT_EN;
724 if (data->blocks > 1)
725 mode |= SDHCI_TRNS_MULTI;
726 if (data->flags & MMC_DATA_READ)
727 mode |= SDHCI_TRNS_READ;
c9fddbc4 728 if (host->flags & SDHCI_REQ_USE_DMA)
c7fa9963
PO		 729 mode |= SDHCI_TRNS_DMA;
730
731 writew(mode, host->ioaddr + SDHCI_TRANSFER_MODE);
d129bceb
PO		 732}
733
734static void sdhci_finish_data(struct sdhci_host *host)
735{
736 struct mmc_data *data;
d129bceb
PO		 737
738 BUG_ON(!host->data);
739
740 data = host->data;
741 host->data = NULL;
742
c9fddbc4 743 if (host->flags & SDHCI_REQ_USE_DMA) {
2134a922
PO		 744 if (host->flags & SDHCI_USE_ADMA)
745 sdhci_adma_table_post(host, data);
746 else {
747 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
748 data->sg_len, (data->flags & MMC_DATA_READ) ?
749 DMA_FROM_DEVICE : DMA_TO_DEVICE);
750 }
d129bceb
PO		 751 }
752
753 /*
c9b74c5b
PO		 754 * The specification states that the block count register must
755 * be updated, but it does not specify at what point in the
756 * data flow. That makes the register entirely useless to read
757 * back so we have to assume that nothing made it to the card
758 * in the event of an error.
d129bceb 759 */
c9b74c5b
PO		 760 if (data->error)
761 data->bytes_xfered = 0;
d129bceb 762 else
c9b74c5b 763 data->bytes_xfered = data->blksz * data->blocks;
d129bceb 764
d129bceb
PO		 765 if (data->stop) {
766 /*
767 * The controller needs a reset of internal state machines
768 * upon error conditions.
769 */
17b0429d 770 if (data->error) {
d129bceb
PO		 771 sdhci_reset(host, SDHCI_RESET_CMD);
772 sdhci_reset(host, SDHCI_RESET_DATA);
773 }
774
775 sdhci_send_command(host, data->stop);
776 } else
777 tasklet_schedule(&host->finish_tasklet);
778}
779
780static void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
781{
782 int flags;
fd2208d7 783 u32 mask;
7cb2c76f 784 unsigned long timeout;
d129bceb
PO		 785
786 WARN_ON(host->cmd);
787
d129bceb 788 /* Wait max 10 ms */
7cb2c76f 789 timeout = 10;
fd2208d7
PO		 790
791 mask = SDHCI_CMD_INHIBIT;
792 if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
793 mask |= SDHCI_DATA_INHIBIT;
794
795 /* We shouldn't wait for data inihibit for stop commands, even
796 though they might use busy signaling */
797 if (host->mrq->data && (cmd == host->mrq->data->stop))
798 mask &= ~SDHCI_DATA_INHIBIT;
799
800 while (readl(host->ioaddr + SDHCI_PRESENT_STATE) & mask) {
7cb2c76f 801 if (timeout == 0) {
d129bceb 802 printk(KERN_ERR "%s: Controller never released "
acf1da45 803 "inhibit bit(s).\n", mmc_hostname(host->mmc));
d129bceb 804 sdhci_dumpregs(host);
17b0429d 805 cmd->error = -EIO;
d129bceb
PO		 806 tasklet_schedule(&host->finish_tasklet);
807 return;
808 }
7cb2c76f
PO		 809 timeout--;
810 mdelay(1);
811 }
d129bceb
PO		 812
813 mod_timer(&host->timer, jiffies + 10 * HZ);
814
815 host->cmd = cmd;
816
817 sdhci_prepare_data(host, cmd->data);
818
819 writel(cmd->arg, host->ioaddr + SDHCI_ARGUMENT);
820
c7fa9963
PO		 821 sdhci_set_transfer_mode(host, cmd->data);
822
d129bceb 823 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
acf1da45 824 printk(KERN_ERR "%s: Unsupported response type!\n",
d129bceb 825 mmc_hostname(host->mmc));
17b0429d 826 cmd->error = -EINVAL;
d129bceb
PO		 827 tasklet_schedule(&host->finish_tasklet);
828 return;
829 }
830
831 if (!(cmd->flags & MMC_RSP_PRESENT))
832 flags = SDHCI_CMD_RESP_NONE;
833 else if (cmd->flags & MMC_RSP_136)
834 flags = SDHCI_CMD_RESP_LONG;
835 else if (cmd->flags & MMC_RSP_BUSY)
836 flags = SDHCI_CMD_RESP_SHORT_BUSY;
837 else
838 flags = SDHCI_CMD_RESP_SHORT;
839
840 if (cmd->flags & MMC_RSP_CRC)
841 flags |= SDHCI_CMD_CRC;
842 if (cmd->flags & MMC_RSP_OPCODE)
843 flags |= SDHCI_CMD_INDEX;
844 if (cmd->data)
845 flags |= SDHCI_CMD_DATA;
846
fb61e289 847 writew(SDHCI_MAKE_CMD(cmd->opcode, flags),
d129bceb
PO		 848 host->ioaddr + SDHCI_COMMAND);
849}
850
851static void sdhci_finish_command(struct sdhci_host *host)
852{
853 int i;
854
855 BUG_ON(host->cmd == NULL);
856
857 if (host->cmd->flags & MMC_RSP_PRESENT) {
858 if (host->cmd->flags & MMC_RSP_136) {
859 /* CRC is stripped so we need to do some shifting. */
860 for (i = 0;i < 4;i++) {
861 host->cmd->resp[i] = readl(host->ioaddr +
862 SDHCI_RESPONSE + (3-i)*4) << 8;
863 if (i != 3)
864 host->cmd->resp[i] |=
865 readb(host->ioaddr +
866 SDHCI_RESPONSE + (3-i)*4-1);
867 }
868 } else {
869 host->cmd->resp[0] = readl(host->ioaddr + SDHCI_RESPONSE);
870 }
871 }
872
17b0429d 873 host->cmd->error = 0;
d129bceb 874
e538fbe8
PO		 875 if (host->data && host->data_early)
876 sdhci_finish_data(host);
877
878 if (!host->cmd->data)
d129bceb
PO		 879 tasklet_schedule(&host->finish_tasklet);
880
881 host->cmd = NULL;
882}
883
884static void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
885{
886 int div;
887 u16 clk;
7cb2c76f 888 unsigned long timeout;
d129bceb
PO		 889
890 if (clock == host->clock)
891 return;
892
893 writew(0, host->ioaddr + SDHCI_CLOCK_CONTROL);
894
895 if (clock == 0)
896 goto out;
897
898 for (div = 1;div < 256;div *= 2) {
899 if ((host->max_clk / div) <= clock)
900 break;
901 }
902 div >>= 1;
903
904 clk = div << SDHCI_DIVIDER_SHIFT;
905 clk |= SDHCI_CLOCK_INT_EN;
906 writew(clk, host->ioaddr + SDHCI_CLOCK_CONTROL);
907
908 /* Wait max 10 ms */
7cb2c76f
PO		 909 timeout = 10;
910 while (!((clk = readw(host->ioaddr + SDHCI_CLOCK_CONTROL))
911 & SDHCI_CLOCK_INT_STABLE)) {
912 if (timeout == 0) {
acf1da45
PO		 913 printk(KERN_ERR "%s: Internal clock never "
914 "stabilised.\n", mmc_hostname(host->mmc));
d129bceb
PO		 915 sdhci_dumpregs(host);
916 return;
917 }
7cb2c76f
PO		 918 timeout--;
919 mdelay(1);
920 }
d129bceb
PO		 921
922 clk |= SDHCI_CLOCK_CARD_EN;
923 writew(clk, host->ioaddr + SDHCI_CLOCK_CONTROL);
924
925out:
926 host->clock = clock;
927}
928
146ad66e
PO		 929static void sdhci_set_power(struct sdhci_host *host, unsigned short power)
930{
931 u8 pwr;
932
933 if (host->power == power)
934 return;
935
9e9dc5f2
DS		 936 if (power == (unsigned short)-1) {
937 writeb(0, host->ioaddr + SDHCI_POWER_CONTROL);
146ad66e 938 goto out;
9e9dc5f2
DS		 939 }
940
941 /*
942 * Spec says that we should clear the power reg before setting
943 * a new value. Some controllers don't seem to like this though.
944 */
b8c86fc5 945 if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
9e9dc5f2 946 writeb(0, host->ioaddr + SDHCI_POWER_CONTROL);
146ad66e
PO		 947
948 pwr = SDHCI_POWER_ON;
949
4be34c99 950 switch (1 << power) {
55556da0 951 case MMC_VDD_165_195:
146ad66e
PO		 952 pwr |= SDHCI_POWER_180;
953 break;
4be34c99
PL		 954 case MMC_VDD_29_30:
955 case MMC_VDD_30_31:
146ad66e
PO		 956 pwr |= SDHCI_POWER_300;
957 break;
4be34c99
PL		 958 case MMC_VDD_32_33:
959 case MMC_VDD_33_34:
146ad66e
PO		 960 pwr |= SDHCI_POWER_330;
961 break;
962 default:
963 BUG();
964 }
965
e08c1694 966 /*
c71f6512 967 * At least the Marvell CaFe chip gets confused if we set the voltage
e08c1694
AS		 968 * and set turn on power at the same time, so set the voltage first.
969 */
b8c86fc5 970 if ((host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER))
e08c1694
AS		 971 writeb(pwr & ~SDHCI_POWER_ON,
972 host->ioaddr + SDHCI_POWER_CONTROL);
973
146ad66e
PO		 974 writeb(pwr, host->ioaddr + SDHCI_POWER_CONTROL);
975
976out:
977 host->power = power;
978}
979
d129bceb
PO		 980/*****************************************************************************\
981 * *
982 * MMC callbacks *
983 * *
984\*****************************************************************************/
985
986static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
987{
988 struct sdhci_host *host;
989 unsigned long flags;
990
991 host = mmc_priv(mmc);
992
993 spin_lock_irqsave(&host->lock, flags);
994
995 WARN_ON(host->mrq != NULL);
996
2f730fec 997#ifndef CONFIG_LEDS_CLASS
d129bceb 998 sdhci_activate_led(host);
2f730fec 999#endif
d129bceb
PO		 1000
1001 host->mrq = mrq;
1002
1e72859e
PO		 1003 if (!(readl(host->ioaddr + SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)
1004 || (host->flags & SDHCI_DEVICE_DEAD)) {
17b0429d 1005 host->mrq->cmd->error = -ENOMEDIUM;
d129bceb
PO		 1006 tasklet_schedule(&host->finish_tasklet);
1007 } else
1008 sdhci_send_command(host, mrq->cmd);
1009
5f25a66f 1010 mmiowb();
d129bceb
PO		 1011 spin_unlock_irqrestore(&host->lock, flags);
1012}
1013
1014static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1015{
1016 struct sdhci_host *host;
1017 unsigned long flags;
1018 u8 ctrl;
1019
1020 host = mmc_priv(mmc);
1021
1022 spin_lock_irqsave(&host->lock, flags);
1023
1e72859e
PO		 1024 if (host->flags & SDHCI_DEVICE_DEAD)
1025 goto out;
1026
d129bceb
PO		 1027 /*
1028 * Reset the chip on each power off.
1029 * Should clear out any weird states.
1030 */
1031 if (ios->power_mode == MMC_POWER_OFF) {
1032 writel(0, host->ioaddr + SDHCI_SIGNAL_ENABLE);
d129bceb 1033 sdhci_init(host);
d129bceb
PO		 1034 }
1035
1036 sdhci_set_clock(host, ios->clock);
1037
1038 if (ios->power_mode == MMC_POWER_OFF)
146ad66e 1039 sdhci_set_power(host, -1);
d129bceb 1040 else
146ad66e 1041 sdhci_set_power(host, ios->vdd);
d129bceb
PO		 1042
1043 ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL);
cd9277c0 1044
d129bceb
PO		 1045 if (ios->bus_width == MMC_BUS_WIDTH_4)
1046 ctrl |= SDHCI_CTRL_4BITBUS;
1047 else
1048 ctrl &= ~SDHCI_CTRL_4BITBUS;
cd9277c0
PO		 1049
1050 if (ios->timing == MMC_TIMING_SD_HS)
1051 ctrl |= SDHCI_CTRL_HISPD;
1052 else
1053 ctrl &= ~SDHCI_CTRL_HISPD;
1054
d129bceb
PO		 1055 writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL);
1056
b8352260
LD		 1057 /*
1058 * Some (ENE) controllers go apeshit on some ios operation,
1059 * signalling timeout and CRC errors even on CMD0. Resetting
1060 * it on each ios seems to solve the problem.
1061 */
b8c86fc5 1062 if(host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
b8352260
LD		 1063 sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
1064
1e72859e 1065out:
5f25a66f 1066 mmiowb();
d129bceb
PO		 1067 spin_unlock_irqrestore(&host->lock, flags);
1068}
1069
1070static int sdhci_get_ro(struct mmc_host *mmc)
1071{
1072 struct sdhci_host *host;
1073 unsigned long flags;
1074 int present;
1075
1076 host = mmc_priv(mmc);
1077
1078 spin_lock_irqsave(&host->lock, flags);
1079
1e72859e
PO		 1080 if (host->flags & SDHCI_DEVICE_DEAD)
1081 present = 0;
1082 else
1083 present = readl(host->ioaddr + SDHCI_PRESENT_STATE);
d129bceb
PO		 1084
1085 spin_unlock_irqrestore(&host->lock, flags);
1086
1087 return !(present & SDHCI_WRITE_PROTECT);
1088}
1089
f75979b7
PO		 1090static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1091{
1092 struct sdhci_host *host;
1093 unsigned long flags;
1094 u32 ier;
1095
1096 host = mmc_priv(mmc);
1097
1098 spin_lock_irqsave(&host->lock, flags);
1099
1e72859e
PO		 1100 if (host->flags & SDHCI_DEVICE_DEAD)
1101 goto out;
1102
f75979b7
PO		 1103 ier = readl(host->ioaddr + SDHCI_INT_ENABLE);
1104
1105 ier &= ~SDHCI_INT_CARD_INT;
1106 if (enable)
1107 ier |= SDHCI_INT_CARD_INT;
1108
1109 writel(ier, host->ioaddr + SDHCI_INT_ENABLE);
1110 writel(ier, host->ioaddr + SDHCI_SIGNAL_ENABLE);
1111
1e72859e 1112out:
f75979b7
PO		 1113 mmiowb();
1114
1115 spin_unlock_irqrestore(&host->lock, flags);
1116}
1117
ab7aefd0 1118static const struct mmc_host_ops sdhci_ops = {
d129bceb
PO		 1119 .request = sdhci_request,
1120 .set_ios = sdhci_set_ios,
1121 .get_ro = sdhci_get_ro,
f75979b7 1122 .enable_sdio_irq = sdhci_enable_sdio_irq,
d129bceb
PO		 1123};
1124
1125/*****************************************************************************\
1126 * *
1127 * Tasklets *
1128 * *
1129\*****************************************************************************/
1130
1131static void sdhci_tasklet_card(unsigned long param)
1132{
1133 struct sdhci_host *host;
1134 unsigned long flags;
1135
1136 host = (struct sdhci_host*)param;
1137
1138 spin_lock_irqsave(&host->lock, flags);
1139
1140 if (!(readl(host->ioaddr + SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) {
1141 if (host->mrq) {
1142 printk(KERN_ERR "%s: Card removed during transfer!\n",
1143 mmc_hostname(host->mmc));
1144 printk(KERN_ERR "%s: Resetting controller.\n",
1145 mmc_hostname(host->mmc));
1146
1147 sdhci_reset(host, SDHCI_RESET_CMD);
1148 sdhci_reset(host, SDHCI_RESET_DATA);
1149
17b0429d 1150 host->mrq->cmd->error = -ENOMEDIUM;
d129bceb
PO		 1151 tasklet_schedule(&host->finish_tasklet);
1152 }
1153 }
1154
1155 spin_unlock_irqrestore(&host->lock, flags);
1156
1157 mmc_detect_change(host->mmc, msecs_to_jiffies(500));
1158}
1159
1160static void sdhci_tasklet_finish(unsigned long param)
1161{
1162 struct sdhci_host *host;
1163 unsigned long flags;
1164 struct mmc_request *mrq;
1165
1166 host = (struct sdhci_host*)param;
1167
1168 spin_lock_irqsave(&host->lock, flags);
1169
1170 del_timer(&host->timer);
1171
1172 mrq = host->mrq;
1173
d129bceb
PO		 1174 /*
1175 * The controller needs a reset of internal state machines
1176 * upon error conditions.
1177 */
1e72859e
PO		 1178 if (!(host->flags & SDHCI_DEVICE_DEAD) &&
1179 (mrq->cmd->error ||
1180 (mrq->data && (mrq->data->error ||
1181 (mrq->data->stop && mrq->data->stop->error))) ||
1182 (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) {
645289dc
PO		 1183
1184 /* Some controllers need this kick or reset won't work here */
b8c86fc5 1185 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET) {
645289dc
PO		 1186 unsigned int clock;
1187
1188 /* This is to force an update */
1189 clock = host->clock;
1190 host->clock = 0;
1191 sdhci_set_clock(host, clock);
1192 }
1193
1194 /* Spec says we should do both at the same time, but Ricoh
1195 controllers do not like that. */
d129bceb
PO		 1196 sdhci_reset(host, SDHCI_RESET_CMD);
1197 sdhci_reset(host, SDHCI_RESET_DATA);
1198 }
1199
1200 host->mrq = NULL;
1201 host->cmd = NULL;
1202 host->data = NULL;
1203
2f730fec 1204#ifndef CONFIG_LEDS_CLASS
d129bceb 1205 sdhci_deactivate_led(host);
2f730fec 1206#endif
d129bceb 1207
5f25a66f 1208 mmiowb();
d129bceb
PO		 1209 spin_unlock_irqrestore(&host->lock, flags);
1210
1211 mmc_request_done(host->mmc, mrq);
1212}
1213
1214static void sdhci_timeout_timer(unsigned long data)
1215{
1216 struct sdhci_host *host;
1217 unsigned long flags;
1218
1219 host = (struct sdhci_host*)data;
1220
1221 spin_lock_irqsave(&host->lock, flags);
1222
1223 if (host->mrq) {
acf1da45
PO		 1224 printk(KERN_ERR "%s: Timeout waiting for hardware "
1225 "interrupt.\n", mmc_hostname(host->mmc));
d129bceb
PO		 1226 sdhci_dumpregs(host);
1227
1228 if (host->data) {
17b0429d 1229 host->data->error = -ETIMEDOUT;
d129bceb
PO		 1230 sdhci_finish_data(host);
1231 } else {
1232 if (host->cmd)
17b0429d 1233 host->cmd->error = -ETIMEDOUT;
d129bceb 1234 else
17b0429d 1235 host->mrq->cmd->error = -ETIMEDOUT;
d129bceb
PO		 1236
1237 tasklet_schedule(&host->finish_tasklet);
1238 }
1239 }
1240
5f25a66f 1241 mmiowb();
d129bceb
PO		 1242 spin_unlock_irqrestore(&host->lock, flags);
1243}
1244
1245/*****************************************************************************\
1246 * *
1247 * Interrupt handling *
1248 * *
1249\*****************************************************************************/
1250
1251static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask)
1252{
1253 BUG_ON(intmask == 0);
1254
1255 if (!host->cmd) {
b67ac3f3
PO		 1256 printk(KERN_ERR "%s: Got command interrupt 0x%08x even "
1257 "though no command operation was in progress.\n",
1258 mmc_hostname(host->mmc), (unsigned)intmask);
d129bceb
PO		 1259 sdhci_dumpregs(host);
1260 return;
1261 }
1262
43b58b36 1263 if (intmask & SDHCI_INT_TIMEOUT)
17b0429d
PO		 1264 host->cmd->error = -ETIMEDOUT;
1265 else if (intmask & (SDHCI_INT_CRC | SDHCI_INT_END_BIT |
1266 SDHCI_INT_INDEX))
1267 host->cmd->error = -EILSEQ;
43b58b36 1268
17b0429d 1269 if (host->cmd->error)
d129bceb 1270 tasklet_schedule(&host->finish_tasklet);
43b58b36
PO		 1271 else if (intmask & SDHCI_INT_RESPONSE)
1272 sdhci_finish_command(host);
d129bceb
PO		 1273}
1274
1275static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
1276{
1277 BUG_ON(intmask == 0);
1278
1279 if (!host->data) {
1280 /*
1281 * A data end interrupt is sent together with the response
1282 * for the stop command.
1283 */
1284 if (intmask & SDHCI_INT_DATA_END)
1285 return;
1286
b67ac3f3
PO		 1287 printk(KERN_ERR "%s: Got data interrupt 0x%08x even "
1288 "though no data operation was in progress.\n",
1289 mmc_hostname(host->mmc), (unsigned)intmask);
d129bceb
PO		 1290 sdhci_dumpregs(host);
1291
1292 return;
1293 }
1294
1295 if (intmask & SDHCI_INT_DATA_TIMEOUT)
17b0429d
PO		 1296 host->data->error = -ETIMEDOUT;
1297 else if (intmask & (SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_END_BIT))
1298 host->data->error = -EILSEQ;
2134a922
PO		 1299 else if (intmask & SDHCI_INT_ADMA_ERROR)
1300 host->data->error = -EIO;
d129bceb 1301
17b0429d 1302 if (host->data->error)
d129bceb
PO		 1303 sdhci_finish_data(host);
1304 else {
a406f5a3 1305 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
d129bceb
PO		 1306 sdhci_transfer_pio(host);
1307
6ba736a1
PO		 1308 /*
1309 * We currently don't do anything fancy with DMA
1310 * boundaries, but as we can't disable the feature
1311 * we need to at least restart the transfer.
1312 */
1313 if (intmask & SDHCI_INT_DMA_END)
1314 writel(readl(host->ioaddr + SDHCI_DMA_ADDRESS),
1315 host->ioaddr + SDHCI_DMA_ADDRESS);
1316
e538fbe8
PO		 1317 if (intmask & SDHCI_INT_DATA_END) {
1318 if (host->cmd) {
1319 /*
1320 * Data managed to finish before the
1321 * command completed. Make sure we do
1322 * things in the proper order.
1323 */
1324 host->data_early = 1;
1325 } else {
1326 sdhci_finish_data(host);
1327 }
1328 }
d129bceb
PO		 1329 }
1330}
1331
7d12e780 1332static irqreturn_t sdhci_irq(int irq, void *dev_id)
d129bceb
PO		 1333{
1334 irqreturn_t result;
1335 struct sdhci_host* host = dev_id;
1336 u32 intmask;
f75979b7 1337 int cardint = 0;
d129bceb
PO		 1338
1339 spin_lock(&host->lock);
1340
1341 intmask = readl(host->ioaddr + SDHCI_INT_STATUS);
1342
62df67a5 1343 if (!intmask || intmask == 0xffffffff) {
d129bceb
PO		 1344 result = IRQ_NONE;
1345 goto out;
1346 }
1347
b69c9058
PO		 1348 DBG("*** %s got interrupt: 0x%08x\n",
1349 mmc_hostname(host->mmc), intmask);
d129bceb 1350
3192a28f
PO		 1351 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
1352 writel(intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE),
1353 host->ioaddr + SDHCI_INT_STATUS);
d129bceb 1354 tasklet_schedule(&host->card_tasklet);
3192a28f 1355 }
d129bceb 1356
3192a28f 1357 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE);
d129bceb 1358
3192a28f 1359 if (intmask & SDHCI_INT_CMD_MASK) {
d129bceb
PO		 1360 writel(intmask & SDHCI_INT_CMD_MASK,
1361 host->ioaddr + SDHCI_INT_STATUS);
3192a28f 1362 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK);
d129bceb
PO		 1363 }
1364
1365 if (intmask & SDHCI_INT_DATA_MASK) {
d129bceb
PO		 1366 writel(intmask & SDHCI_INT_DATA_MASK,
1367 host->ioaddr + SDHCI_INT_STATUS);
3192a28f 1368 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
d129bceb
PO		 1369 }
1370
1371 intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK);
1372
964f9ce2
PO		 1373 intmask &= ~SDHCI_INT_ERROR;
1374
d129bceb 1375 if (intmask & SDHCI_INT_BUS_POWER) {
3192a28f 1376 printk(KERN_ERR "%s: Card is consuming too much power!\n",
d129bceb 1377 mmc_hostname(host->mmc));
3192a28f 1378 writel(SDHCI_INT_BUS_POWER, host->ioaddr + SDHCI_INT_STATUS);
d129bceb
PO		 1379 }
1380
9d26a5d3 1381 intmask &= ~SDHCI_INT_BUS_POWER;
3192a28f 1382
f75979b7
PO		 1383 if (intmask & SDHCI_INT_CARD_INT)
1384 cardint = 1;
1385
1386 intmask &= ~SDHCI_INT_CARD_INT;
1387
3192a28f 1388 if (intmask) {
acf1da45 1389 printk(KERN_ERR "%s: Unexpected interrupt 0x%08x.\n",
3192a28f 1390 mmc_hostname(host->mmc), intmask);
d129bceb
PO		 1391 sdhci_dumpregs(host);
1392
d129bceb 1393 writel(intmask, host->ioaddr + SDHCI_INT_STATUS);
3192a28f 1394 }
d129bceb
PO		 1395
1396 result = IRQ_HANDLED;
1397
5f25a66f 1398 mmiowb();
d129bceb
PO		 1399out:
1400 spin_unlock(&host->lock);
1401
f75979b7
PO		 1402 /*
1403 * We have to delay this as it calls back into the driver.
1404 */
1405 if (cardint)
1406 mmc_signal_sdio_irq(host->mmc);
1407
d129bceb
PO		 1408 return result;
1409}
1410
1411/*****************************************************************************\
1412 * *
1413 * Suspend/resume *
1414 * *
1415\*****************************************************************************/
1416
1417#ifdef CONFIG_PM
1418
b8c86fc5 1419int sdhci_suspend_host(struct sdhci_host *host, pm_message_t state)
d129bceb 1420{
b8c86fc5 1421 int ret;
a715dfc7 1422
b8c86fc5
PO		 1423 ret = mmc_suspend_host(host->mmc, state);
1424 if (ret)
1425 return ret;
a715dfc7 1426
b8c86fc5 1427 free_irq(host->irq, host);
d129bceb
PO		 1428
1429 return 0;
1430}
1431
b8c86fc5 1432EXPORT_SYMBOL_GPL(sdhci_suspend_host);
d129bceb 1433
b8c86fc5
PO		 1434int sdhci_resume_host(struct sdhci_host *host)
1435{
1436 int ret;
d129bceb 1437
b8c86fc5
PO		 1438 if (host->flags & SDHCI_USE_DMA) {
1439 if (host->ops->enable_dma)
1440 host->ops->enable_dma(host);
1441 }
d129bceb 1442
b8c86fc5
PO		 1443 ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
1444 mmc_hostname(host->mmc), host);
df1c4b7b
PO		 1445 if (ret)
1446 return ret;
d129bceb 1447
b8c86fc5
PO		 1448 sdhci_init(host);
1449 mmiowb();
1450
1451 ret = mmc_resume_host(host->mmc);
1452 if (ret)
1453 return ret;
d129bceb
PO		 1454
1455 return 0;
1456}
1457
b8c86fc5 1458EXPORT_SYMBOL_GPL(sdhci_resume_host);
d129bceb
PO		 1459
1460#endif /* CONFIG_PM */
1461
1462/*****************************************************************************\
1463 * *
b8c86fc5 1464 * Device allocation/registration *
d129bceb
PO		 1465 * *
1466\*****************************************************************************/
1467
b8c86fc5
PO		 1468struct sdhci_host *sdhci_alloc_host(struct device *dev,
1469 size_t priv_size)
d129bceb 1470{
d129bceb
PO		 1471 struct mmc_host *mmc;
1472 struct sdhci_host *host;
1473
b8c86fc5 1474 WARN_ON(dev == NULL);
d129bceb 1475
b8c86fc5 1476 mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev);
d129bceb 1477 if (!mmc)
b8c86fc5 1478 return ERR_PTR(-ENOMEM);
d129bceb
PO		 1479
1480 host = mmc_priv(mmc);
1481 host->mmc = mmc;
1482
b8c86fc5
PO		 1483 return host;
1484}
8a4da143 1485
b8c86fc5 1486EXPORT_SYMBOL_GPL(sdhci_alloc_host);
d129bceb 1487
b8c86fc5
PO		 1488int sdhci_add_host(struct sdhci_host *host)
1489{
1490 struct mmc_host *mmc;
1491 unsigned int caps;
b8c86fc5 1492 int ret;
d129bceb 1493
b8c86fc5
PO		 1494 WARN_ON(host == NULL);
1495 if (host == NULL)
1496 return -EINVAL;
d129bceb 1497
b8c86fc5 1498 mmc = host->mmc;
d129bceb 1499
b8c86fc5
PO		 1500 if (debug_quirks)
1501 host->quirks = debug_quirks;
d129bceb 1502
d96649ed
PO		 1503 sdhci_reset(host, SDHCI_RESET_ALL);
1504
2134a922
PO		 1505 host->version = readw(host->ioaddr + SDHCI_HOST_VERSION);
1506 host->version = (host->version & SDHCI_SPEC_VER_MASK)
1507 >> SDHCI_SPEC_VER_SHIFT;
1508 if (host->version > SDHCI_SPEC_200) {
4a965505 1509 printk(KERN_ERR "%s: Unknown controller version (%d). "
b69c9058 1510 "You may experience problems.\n", mmc_hostname(mmc),
2134a922 1511 host->version);
4a965505
PO		 1512 }
1513
d129bceb
PO		 1514 caps = readl(host->ioaddr + SDHCI_CAPABILITIES);
1515
b8c86fc5 1516 if (host->quirks & SDHCI_QUIRK_FORCE_DMA)
98608076 1517 host->flags |= SDHCI_USE_DMA;
67435274
PO		 1518 else if (!(caps & SDHCI_CAN_DO_DMA))
1519 DBG("Controller doesn't have DMA capability\n");
1520 else
d129bceb
PO		 1521 host->flags |= SDHCI_USE_DMA;
1522
b8c86fc5 1523 if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
7c168e3d 1524 (host->flags & SDHCI_USE_DMA)) {
cee687ce 1525 DBG("Disabling DMA as it is marked broken\n");
7c168e3d
FT		 1526 host->flags &= ~SDHCI_USE_DMA;
1527 }
1528
2134a922
PO		 1529 if (host->flags & SDHCI_USE_DMA) {
1530 if ((host->version >= SDHCI_SPEC_200) &&
1531 (caps & SDHCI_CAN_DO_ADMA2))
1532 host->flags |= SDHCI_USE_ADMA;
1533 }
1534
1535 if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) &&
1536 (host->flags & SDHCI_USE_ADMA)) {
1537 DBG("Disabling ADMA as it is marked broken\n");
1538 host->flags &= ~SDHCI_USE_ADMA;
1539 }
1540
d129bceb 1541 if (host->flags & SDHCI_USE_DMA) {
b8c86fc5
PO		 1542 if (host->ops->enable_dma) {
1543 if (host->ops->enable_dma(host)) {
1544 printk(KERN_WARNING "%s: No suitable DMA "
1545 "available. Falling back to PIO.\n",
1546 mmc_hostname(mmc));
2134a922 1547 host->flags &= ~(SDHCI_USE_DMA | SDHCI_USE_ADMA);
b8c86fc5 1548 }
d129bceb
PO		 1549 }
1550 }
1551
2134a922
PO		 1552 if (host->flags & SDHCI_USE_ADMA) {
1553 /*
1554 * We need to allocate descriptors for all sg entries
1555 * (128) and potentially one alignment transfer for
1556 * each of those entries.
1557 */
1558 host->adma_desc = kmalloc((128 * 2 + 1) * 4, GFP_KERNEL);
1559 host->align_buffer = kmalloc(128 * 4, GFP_KERNEL);
1560 if (!host->adma_desc || !host->align_buffer) {
1561 kfree(host->adma_desc);
1562 kfree(host->align_buffer);
1563 printk(KERN_WARNING "%s: Unable to allocate ADMA "
1564 "buffers. Falling back to standard DMA.\n",
1565 mmc_hostname(mmc));
1566 host->flags &= ~SDHCI_USE_ADMA;
1567 }
1568 }
1569
7659150c
PO		 1570 /*
1571 * If we use DMA, then it's up to the caller to set the DMA
1572 * mask, but PIO does not need the hw shim so we set a new
1573 * mask here in that case.
1574 */
1575 if (!(host->flags & SDHCI_USE_DMA)) {
1576 host->dma_mask = DMA_BIT_MASK(64);
1577 mmc_dev(host->mmc)->dma_mask = &host->dma_mask;
1578 }
d129bceb 1579
8ef1a143
PO		 1580 host->max_clk =
1581 (caps & SDHCI_CLOCK_BASE_MASK) >> SDHCI_CLOCK_BASE_SHIFT;
1582 if (host->max_clk == 0) {
1583 printk(KERN_ERR "%s: Hardware doesn't specify base clock "
b69c9058 1584 "frequency.\n", mmc_hostname(mmc));
b8c86fc5 1585 return -ENODEV;
8ef1a143 1586 }
d129bceb
PO		 1587 host->max_clk *= 1000000;
1588
1c8cde92
PO		 1589 host->timeout_clk =
1590 (caps & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT;
1591 if (host->timeout_clk == 0) {
1592 printk(KERN_ERR "%s: Hardware doesn't specify timeout clock "
b69c9058 1593 "frequency.\n", mmc_hostname(mmc));
b8c86fc5 1594 return -ENODEV;
1c8cde92
PO		 1595 }
1596 if (caps & SDHCI_TIMEOUT_CLK_UNIT)
1597 host->timeout_clk *= 1000;
d129bceb
PO		 1598
1599 /*
1600 * Set host parameters.
1601 */
1602 mmc->ops = &sdhci_ops;
1603 mmc->f_min = host->max_clk / 256;
1604 mmc->f_max = host->max_clk;
c9b74c5b 1605 mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ;
d129bceb 1606
cd9277c0
PO		 1607 if (caps & SDHCI_CAN_DO_HISPD)
1608 mmc->caps |= MMC_CAP_SD_HIGHSPEED;
1609
146ad66e
PO		 1610 mmc->ocr_avail = 0;
1611 if (caps & SDHCI_CAN_VDD_330)
1612 mmc->ocr_avail |= MMC_VDD_32_33|MMC_VDD_33_34;
c70840e8 1613 if (caps & SDHCI_CAN_VDD_300)
146ad66e 1614 mmc->ocr_avail |= MMC_VDD_29_30|MMC_VDD_30_31;
c70840e8 1615 if (caps & SDHCI_CAN_VDD_180)
55556da0 1616 mmc->ocr_avail |= MMC_VDD_165_195;
146ad66e
PO		 1617
1618 if (mmc->ocr_avail == 0) {
1619 printk(KERN_ERR "%s: Hardware doesn't report any "
b69c9058 1620 "support voltages.\n", mmc_hostname(mmc));
b8c86fc5 1621 return -ENODEV;
146ad66e
PO		 1622 }
1623
d129bceb
PO		 1624 spin_lock_init(&host->lock);
1625
1626 /*
2134a922
PO		 1627 * Maximum number of segments. Depends on if the hardware
1628 * can do scatter/gather or not.
d129bceb 1629 */
2134a922
PO		 1630 if (host->flags & SDHCI_USE_ADMA)
1631 mmc->max_hw_segs = 128;
1632 else if (host->flags & SDHCI_USE_DMA)
d129bceb 1633 mmc->max_hw_segs = 1;
2134a922
PO		 1634 else /* PIO */
1635 mmc->max_hw_segs = 128;
1636 mmc->max_phys_segs = 128;
d129bceb
PO		 1637
1638 /*
bab76961 1639 * Maximum number of sectors in one transfer. Limited by DMA boundary
55db890a 1640 * size (512KiB).
d129bceb 1641 */
55db890a 1642 mmc->max_req_size = 524288;
d129bceb
PO		 1643
1644 /*
1645 * Maximum segment size. Could be one segment with the maximum number
2134a922
PO		 1646 * of bytes. When doing hardware scatter/gather, each entry cannot
1647 * be larger than 64 KiB though.
d129bceb 1648 */
2134a922
PO		 1649 if (host->flags & SDHCI_USE_ADMA)
1650 mmc->max_seg_size = 65536;
1651 else
1652 mmc->max_seg_size = mmc->max_req_size;
d129bceb 1653
fe4a3c7a
PO		 1654 /*
1655 * Maximum block size. This varies from controller to controller and
1656 * is specified in the capabilities register.
1657 */
1658 mmc->max_blk_size = (caps & SDHCI_MAX_BLOCK_MASK) >> SDHCI_MAX_BLOCK_SHIFT;
1659 if (mmc->max_blk_size >= 3) {
b69c9058
PO		 1660 printk(KERN_WARNING "%s: Invalid maximum block size, "
1661 "assuming 512 bytes\n", mmc_hostname(mmc));
03f8590d
DV		 1662 mmc->max_blk_size = 512;
1663 } else
1664 mmc->max_blk_size = 512 << mmc->max_blk_size;
fe4a3c7a 1665
55db890a
PO		 1666 /*
1667 * Maximum block count.
1668 */
1669 mmc->max_blk_count = 65535;
1670
d129bceb
PO		 1671 /*
1672 * Init tasklets.
1673 */
1674 tasklet_init(&host->card_tasklet,
1675 sdhci_tasklet_card, (unsigned long)host);
1676 tasklet_init(&host->finish_tasklet,
1677 sdhci_tasklet_finish, (unsigned long)host);
1678
e4cad1b5 1679 setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host);
d129bceb 1680
dace1453 1681 ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
b69c9058 1682 mmc_hostname(mmc), host);
d129bceb 1683 if (ret)
8ef1a143 1684 goto untasklet;
d129bceb
PO		 1685
1686 sdhci_init(host);
1687
1688#ifdef CONFIG_MMC_DEBUG
1689 sdhci_dumpregs(host);
1690#endif
1691
2f730fec
PO		 1692#ifdef CONFIG_LEDS_CLASS
1693 host->led.name = mmc_hostname(mmc);
1694 host->led.brightness = LED_OFF;
1695 host->led.default_trigger = mmc_hostname(mmc);
1696 host->led.brightness_set = sdhci_led_control;
1697
b8c86fc5 1698 ret = led_classdev_register(mmc_dev(mmc), &host->led);
2f730fec
PO		 1699 if (ret)
1700 goto reset;
1701#endif
1702
5f25a66f
PO		 1703 mmiowb();
1704
d129bceb
PO		 1705 mmc_add_host(mmc);
1706
2134a922 1707 printk(KERN_INFO "%s: SDHCI controller on %s [%s] using %s%s\n",
b8c86fc5 1708 mmc_hostname(mmc), host->hw_name, mmc_dev(mmc)->bus_id,
2134a922 1709 (host->flags & SDHCI_USE_ADMA)?"A":"",
d129bceb
PO		 1710 (host->flags & SDHCI_USE_DMA)?"DMA":"PIO");
1711
1712 return 0;
1713
2f730fec
PO		 1714#ifdef CONFIG_LEDS_CLASS
1715reset:
1716 sdhci_reset(host, SDHCI_RESET_ALL);
1717 free_irq(host->irq, host);
1718#endif
8ef1a143 1719untasklet:
d129bceb
PO		 1720 tasklet_kill(&host->card_tasklet);
1721 tasklet_kill(&host->finish_tasklet);
d129bceb
PO		 1722
1723 return ret;
1724}
1725
b8c86fc5 1726EXPORT_SYMBOL_GPL(sdhci_add_host);
d129bceb 1727
1e72859e 1728void sdhci_remove_host(struct sdhci_host *host, int dead)
b8c86fc5 1729{
1e72859e
PO		 1730 unsigned long flags;
1731
1732 if (dead) {
1733 spin_lock_irqsave(&host->lock, flags);
1734
1735 host->flags |= SDHCI_DEVICE_DEAD;
1736
1737 if (host->mrq) {
1738 printk(KERN_ERR "%s: Controller removed during "
1739 " transfer!\n", mmc_hostname(host->mmc));
1740
1741 host->mrq->cmd->error = -ENOMEDIUM;
1742 tasklet_schedule(&host->finish_tasklet);
1743 }
1744
1745 spin_unlock_irqrestore(&host->lock, flags);
1746 }
1747
b8c86fc5 1748 mmc_remove_host(host->mmc);
d129bceb 1749
2f730fec
PO		 1750#ifdef CONFIG_LEDS_CLASS
1751 led_classdev_unregister(&host->led);
1752#endif
1753
1e72859e
PO		 1754 if (!dead)
1755 sdhci_reset(host, SDHCI_RESET_ALL);
d129bceb
PO		 1756
1757 free_irq(host->irq, host);
1758
1759 del_timer_sync(&host->timer);
1760
1761 tasklet_kill(&host->card_tasklet);
1762 tasklet_kill(&host->finish_tasklet);
2134a922
PO		 1763
1764 kfree(host->adma_desc);
1765 kfree(host->align_buffer);
1766
1767 host->adma_desc = NULL;
1768 host->align_buffer = NULL;
d129bceb
PO		 1769}
1770
b8c86fc5 1771EXPORT_SYMBOL_GPL(sdhci_remove_host);
d129bceb 1772
b8c86fc5 1773void sdhci_free_host(struct sdhci_host *host)
d129bceb 1774{
b8c86fc5 1775 mmc_free_host(host->mmc);
d129bceb
PO		 1776}
1777
b8c86fc5 1778EXPORT_SYMBOL_GPL(sdhci_free_host);
d129bceb
PO		 1779
1780/*****************************************************************************\
1781 * *
1782 * Driver init/exit *
1783 * *
1784\*****************************************************************************/
1785
1786static int __init sdhci_drv_init(void)
1787{
1788 printk(KERN_INFO DRIVER_NAME
52fbf9c9 1789 ": Secure Digital Host Controller Interface driver\n");
d129bceb
PO		 1790 printk(KERN_INFO DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
1791
b8c86fc5 1792 return 0;
d129bceb
PO		 1793}
1794
1795static void __exit sdhci_drv_exit(void)
1796{
d129bceb
PO		 1797}
1798
1799module_init(sdhci_drv_init);
1800module_exit(sdhci_drv_exit);
1801
df673b22 1802module_param(debug_quirks, uint, 0444);
67435274 1803
d129bceb 1804MODULE_AUTHOR("Pierre Ossman <drzeus@drzeus.cx>");
b8c86fc5 1805MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver");
d129bceb 1806MODULE_LICENSE("GPL");
67435274 1807
df673b22 1808MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");
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