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mmc: sdhci: move sdhci_pre_dma_transfer()
[mirror_ubuntu-artful-kernel.git] / drivers / mmc / host / sdhci.c
CommitLineData
d129bceb 1/*
70f10482 2 * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
d129bceb 3 *
b69c9058 4 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
d129bceb
PO		 5 *
6 * This program is free software; you can redistribute it and/or modify
643f720c
PO		 7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or (at
9 * your option) any later version.
84c46a53
PO		 10 *
11 * Thanks to the following companies for their support:
12 *
13 * - JMicron (hardware and technical support)
d129bceb
PO		 14 */
15
d129bceb
PO		 16#include <linux/delay.h>
17#include <linux/highmem.h>
b8c86fc5 18#include <linux/io.h>
88b47679 19#include <linux/module.h>
d129bceb 20#include <linux/dma-mapping.h>
5a0e3ad6 21#include <linux/slab.h>
11763609 22#include <linux/scatterlist.h>
9bea3c85 23#include <linux/regulator/consumer.h>
66fd8ad5 24#include <linux/pm_runtime.h>
d129bceb 25
2f730fec
PO		 26#include <linux/leds.h>
27
22113efd 28#include <linux/mmc/mmc.h>
d129bceb 29#include <linux/mmc/host.h>
473b095a 30#include <linux/mmc/card.h>
85cc1c33 31#include <linux/mmc/sdio.h>
bec9d4e5 32#include <linux/mmc/slot-gpio.h>
d129bceb 33
d129bceb
PO		 34#include "sdhci.h"
35
36#define DRIVER_NAME "sdhci"
d129bceb 37
d129bceb 38#define DBG(f, x...) \
c6563178 39 pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
d129bceb 40
f9134319
PO		 41#if defined(CONFIG_LEDS_CLASS) || (defined(CONFIG_LEDS_CLASS_MODULE) && \
42 defined(CONFIG_MMC_SDHCI_MODULE))
43#define SDHCI_USE_LEDS_CLASS
44#endif
45
b513ea25
AN		 46#define MAX_TUNING_LOOP 40
47
df673b22 48static unsigned int debug_quirks = 0;
66fd8ad5 49static unsigned int debug_quirks2;
67435274 50
d129bceb
PO		 51static void sdhci_finish_data(struct sdhci_host *);
52
d129bceb 53static void sdhci_finish_command(struct sdhci_host *);
069c9f14 54static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode);
52983382 55static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable);
04e079cf 56static int sdhci_do_get_cd(struct sdhci_host *host);
d129bceb 57
162d6f98 58#ifdef CONFIG_PM
66fd8ad5
AH		 59static int sdhci_runtime_pm_get(struct sdhci_host *host);
60static int sdhci_runtime_pm_put(struct sdhci_host *host);
f0710a55
AH		 61static void sdhci_runtime_pm_bus_on(struct sdhci_host *host);
62static void sdhci_runtime_pm_bus_off(struct sdhci_host *host);
66fd8ad5
AH		 63#else
64static inline int sdhci_runtime_pm_get(struct sdhci_host *host)
65{
66 return 0;
67}
68static inline int sdhci_runtime_pm_put(struct sdhci_host *host)
69{
70 return 0;
71}
f0710a55
AH		 72static void sdhci_runtime_pm_bus_on(struct sdhci_host *host)
73{
74}
75static void sdhci_runtime_pm_bus_off(struct sdhci_host *host)
76{
77}
66fd8ad5
AH		 78#endif
79
d129bceb
PO		 80static void sdhci_dumpregs(struct sdhci_host *host)
81{
a3c76eb9 82 pr_debug(DRIVER_NAME ": =========== REGISTER DUMP (%s)===========\n",
412ab659 83 mmc_hostname(host->mmc));
d129bceb 84
a3c76eb9 85 pr_debug(DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n",
4e4141a5
AV		 86 sdhci_readl(host, SDHCI_DMA_ADDRESS),
87 sdhci_readw(host, SDHCI_HOST_VERSION));
a3c76eb9 88 pr_debug(DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n",
4e4141a5
AV		 89 sdhci_readw(host, SDHCI_BLOCK_SIZE),
90 sdhci_readw(host, SDHCI_BLOCK_COUNT));
a3c76eb9 91 pr_debug(DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
4e4141a5
AV		 92 sdhci_readl(host, SDHCI_ARGUMENT),
93 sdhci_readw(host, SDHCI_TRANSFER_MODE));
a3c76eb9 94 pr_debug(DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n",
4e4141a5
AV		 95 sdhci_readl(host, SDHCI_PRESENT_STATE),
96 sdhci_readb(host, SDHCI_HOST_CONTROL));
a3c76eb9 97 pr_debug(DRIVER_NAME ": Power: 0x%08x | Blk gap: 0x%08x\n",
4e4141a5
AV		 98 sdhci_readb(host, SDHCI_POWER_CONTROL),
99 sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL));
a3c76eb9 100 pr_debug(DRIVER_NAME ": Wake-up: 0x%08x | Clock: 0x%08x\n",
4e4141a5
AV		 101 sdhci_readb(host, SDHCI_WAKE_UP_CONTROL),
102 sdhci_readw(host, SDHCI_CLOCK_CONTROL));
a3c76eb9 103 pr_debug(DRIVER_NAME ": Timeout: 0x%08x | Int stat: 0x%08x\n",
4e4141a5
AV		 104 sdhci_readb(host, SDHCI_TIMEOUT_CONTROL),
105 sdhci_readl(host, SDHCI_INT_STATUS));
a3c76eb9 106 pr_debug(DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
4e4141a5
AV		 107 sdhci_readl(host, SDHCI_INT_ENABLE),
108 sdhci_readl(host, SDHCI_SIGNAL_ENABLE));
a3c76eb9 109 pr_debug(DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
4e4141a5
AV		 110 sdhci_readw(host, SDHCI_ACMD12_ERR),
111 sdhci_readw(host, SDHCI_SLOT_INT_STATUS));
a3c76eb9 112 pr_debug(DRIVER_NAME ": Caps: 0x%08x | Caps_1: 0x%08x\n",
4e4141a5 113 sdhci_readl(host, SDHCI_CAPABILITIES),
e8120ad1 114 sdhci_readl(host, SDHCI_CAPABILITIES_1));
a3c76eb9 115 pr_debug(DRIVER_NAME ": Cmd: 0x%08x | Max curr: 0x%08x\n",
e8120ad1 116 sdhci_readw(host, SDHCI_COMMAND),
4e4141a5 117 sdhci_readl(host, SDHCI_MAX_CURRENT));
a3c76eb9 118 pr_debug(DRIVER_NAME ": Host ctl2: 0x%08x\n",
f2119df6 119 sdhci_readw(host, SDHCI_HOST_CONTROL2));
d129bceb 120
e57a5f61
AH		 121 if (host->flags & SDHCI_USE_ADMA) {
122 if (host->flags & SDHCI_USE_64_BIT_DMA)
123 pr_debug(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x%08x\n",
124 readl(host->ioaddr + SDHCI_ADMA_ERROR),
125 readl(host->ioaddr + SDHCI_ADMA_ADDRESS_HI),
126 readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
127 else
128 pr_debug(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n",
129 readl(host->ioaddr + SDHCI_ADMA_ERROR),
130 readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
131 }
be3f4ae0 132
a3c76eb9 133 pr_debug(DRIVER_NAME ": ===========================================\n");
d129bceb
PO		 134}
135
136/*****************************************************************************\
137 * *
138 * Low level functions *
139 * *
140\*****************************************************************************/
141
7260cf5e
AV		 142static void sdhci_set_card_detection(struct sdhci_host *host, bool enable)
143{
5b4f1f6c 144 u32 present;
7260cf5e 145
c79396c1 146 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) ||
87b87a3f 147 (host->mmc->caps & MMC_CAP_NONREMOVABLE))
66fd8ad5
AH		 148 return;
149
5b4f1f6c
RK		 150 if (enable) {
151 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
152 SDHCI_CARD_PRESENT;
d25928d1 153
5b4f1f6c
RK		 154 host->ier |= present ? SDHCI_INT_CARD_REMOVE :
155 SDHCI_INT_CARD_INSERT;
156 } else {
157 host->ier &= ~(SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT);
158 }
b537f94c
RK		 159
160 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
161 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
7260cf5e
AV		 162}
163
164static void sdhci_enable_card_detection(struct sdhci_host *host)
165{
166 sdhci_set_card_detection(host, true);
167}
168
169static void sdhci_disable_card_detection(struct sdhci_host *host)
170{
171 sdhci_set_card_detection(host, false);
172}
173
03231f9b 174void sdhci_reset(struct sdhci_host *host, u8 mask)
d129bceb 175{
e16514d8 176 unsigned long timeout;
393c1a34 177
4e4141a5 178 sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
d129bceb 179
f0710a55 180 if (mask & SDHCI_RESET_ALL) {
d129bceb 181 host->clock = 0;
f0710a55
AH		 182 /* Reset-all turns off SD Bus Power */
183 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
184 sdhci_runtime_pm_bus_off(host);
185 }
d129bceb 186
e16514d8
PO		 187 /* Wait max 100 ms */
188 timeout = 100;
189
190 /* hw clears the bit when it's done */
4e4141a5 191 while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
e16514d8 192 if (timeout == 0) {
a3c76eb9 193 pr_err("%s: Reset 0x%x never completed.\n",
e16514d8
PO		 194 mmc_hostname(host->mmc), (int)mask);
195 sdhci_dumpregs(host);
196 return;
197 }
198 timeout--;
199 mdelay(1);
d129bceb 200 }
03231f9b
RK		 201}
202EXPORT_SYMBOL_GPL(sdhci_reset);
203
204static void sdhci_do_reset(struct sdhci_host *host, u8 mask)
205{
206 if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
135b0a28 207 if (!sdhci_do_get_cd(host))
03231f9b
RK		 208 return;
209 }
063a9dbb 210
03231f9b 211 host->ops->reset(host, mask);
393c1a34 212
da91a8f9
RK		 213 if (mask & SDHCI_RESET_ALL) {
214 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
215 if (host->ops->enable_dma)
216 host->ops->enable_dma(host);
217 }
218
219 /* Resetting the controller clears many */
220 host->preset_enabled = false;
3abc1e80 221 }
d129bceb
PO		 222}
223
2f4cbb3d
NP		 224static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios);
225
226static void sdhci_init(struct sdhci_host *host, int soft)
d129bceb 227{
2f4cbb3d 228 if (soft)
03231f9b 229 sdhci_do_reset(host, SDHCI_RESET_CMD|SDHCI_RESET_DATA);
2f4cbb3d 230 else
03231f9b 231 sdhci_do_reset(host, SDHCI_RESET_ALL);
d129bceb 232
b537f94c
RK		 233 host->ier = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
234 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT |
235 SDHCI_INT_INDEX | SDHCI_INT_END_BIT | SDHCI_INT_CRC |
236 SDHCI_INT_TIMEOUT | SDHCI_INT_DATA_END |
237 SDHCI_INT_RESPONSE;
238
239 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
240 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2f4cbb3d
NP		 241
242 if (soft) {
243 /* force clock reconfiguration */
244 host->clock = 0;
245 sdhci_set_ios(host->mmc, &host->mmc->ios);
246 }
7260cf5e 247}
d129bceb 248
7260cf5e
AV		 249static void sdhci_reinit(struct sdhci_host *host)
250{
2f4cbb3d 251 sdhci_init(host, 0);
7260cf5e 252 sdhci_enable_card_detection(host);
d129bceb
PO		 253}
254
255static void sdhci_activate_led(struct sdhci_host *host)
256{
257 u8 ctrl;
258
4e4141a5 259 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
d129bceb 260 ctrl |= SDHCI_CTRL_LED;
4e4141a5 261 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d129bceb
PO		 262}
263
264static void sdhci_deactivate_led(struct sdhci_host *host)
265{
266 u8 ctrl;
267
4e4141a5 268 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
d129bceb 269 ctrl &= ~SDHCI_CTRL_LED;
4e4141a5 270 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d129bceb
PO		 271}
272
f9134319 273#ifdef SDHCI_USE_LEDS_CLASS
2f730fec
PO		 274static void sdhci_led_control(struct led_classdev *led,
275 enum led_brightness brightness)
276{
277 struct sdhci_host *host = container_of(led, struct sdhci_host, led);
278 unsigned long flags;
279
280 spin_lock_irqsave(&host->lock, flags);
281
66fd8ad5
AH		 282 if (host->runtime_suspended)
283 goto out;
284
2f730fec
PO		 285 if (brightness == LED_OFF)
286 sdhci_deactivate_led(host);
287 else
288 sdhci_activate_led(host);
66fd8ad5 289out:
2f730fec
PO		 290 spin_unlock_irqrestore(&host->lock, flags);
291}
292#endif
293
d129bceb
PO		 294/*****************************************************************************\
295 * *
296 * Core functions *
297 * *
298\*****************************************************************************/
299
a406f5a3 300static void sdhci_read_block_pio(struct sdhci_host *host)
d129bceb 301{
7659150c
PO		 302 unsigned long flags;
303 size_t blksize, len, chunk;
7244b85b 304 u32 uninitialized_var(scratch);
7659150c 305 u8 *buf;
d129bceb 306
a406f5a3 307 DBG("PIO reading\n");
d129bceb 308
a406f5a3 309 blksize = host->data->blksz;
7659150c 310 chunk = 0;
d129bceb 311
7659150c 312 local_irq_save(flags);
d129bceb 313
a406f5a3 314 while (blksize) {
bf3a35ac 315 BUG_ON(!sg_miter_next(&host->sg_miter));
d129bceb 316
7659150c 317 len = min(host->sg_miter.length, blksize);
d129bceb 318
7659150c
PO		 319 blksize -= len;
320 host->sg_miter.consumed = len;
14d836e7 321
7659150c 322 buf = host->sg_miter.addr;
d129bceb 323
7659150c
PO		 324 while (len) {
325 if (chunk == 0) {
4e4141a5 326 scratch = sdhci_readl(host, SDHCI_BUFFER);
7659150c 327 chunk = 4;
a406f5a3 328 }
7659150c
PO		 329
330 *buf = scratch & 0xFF;
331
332 buf++;
333 scratch >>= 8;
334 chunk--;
335 len--;
d129bceb 336 }
a406f5a3 337 }
7659150c
PO		 338
339 sg_miter_stop(&host->sg_miter);
340
341 local_irq_restore(flags);
a406f5a3 342}
d129bceb 343
a406f5a3
PO		 344static void sdhci_write_block_pio(struct sdhci_host *host)
345{
7659150c
PO		 346 unsigned long flags;
347 size_t blksize, len, chunk;
348 u32 scratch;
349 u8 *buf;
d129bceb 350
a406f5a3
PO		 351 DBG("PIO writing\n");
352
353 blksize = host->data->blksz;
7659150c
PO		 354 chunk = 0;
355 scratch = 0;
d129bceb 356
7659150c 357 local_irq_save(flags);
d129bceb 358
a406f5a3 359 while (blksize) {
bf3a35ac 360 BUG_ON(!sg_miter_next(&host->sg_miter));
a406f5a3 361
7659150c
PO		 362 len = min(host->sg_miter.length, blksize);
363
364 blksize -= len;
365 host->sg_miter.consumed = len;
366
367 buf = host->sg_miter.addr;
d129bceb 368
7659150c
PO		 369 while (len) {
370 scratch |= (u32)*buf << (chunk * 8);
371
372 buf++;
373 chunk++;
374 len--;
375
376 if ((chunk == 4) || ((len == 0) && (blksize == 0))) {
4e4141a5 377 sdhci_writel(host, scratch, SDHCI_BUFFER);
7659150c
PO		 378 chunk = 0;
379 scratch = 0;
d129bceb 380 }
d129bceb
PO		 381 }
382 }
7659150c
PO		 383
384 sg_miter_stop(&host->sg_miter);
385
386 local_irq_restore(flags);
a406f5a3
PO		 387}
388
389static void sdhci_transfer_pio(struct sdhci_host *host)
390{
391 u32 mask;
392
393 BUG_ON(!host->data);
394
7659150c 395 if (host->blocks == 0)
a406f5a3
PO		 396 return;
397
398 if (host->data->flags & MMC_DATA_READ)
399 mask = SDHCI_DATA_AVAILABLE;
400 else
401 mask = SDHCI_SPACE_AVAILABLE;
402
4a3cba32
PO		 403 /*
404 * Some controllers (JMicron JMB38x) mess up the buffer bits
405 * for transfers < 4 bytes. As long as it is just one block,
406 * we can ignore the bits.
407 */
408 if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) &&
409 (host->data->blocks == 1))
410 mask = ~0;
411
4e4141a5 412 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
3e3bf207
AV		 413 if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY)
414 udelay(100);
415
a406f5a3
PO		 416 if (host->data->flags & MMC_DATA_READ)
417 sdhci_read_block_pio(host);
418 else
419 sdhci_write_block_pio(host);
d129bceb 420
7659150c
PO		 421 host->blocks--;
422 if (host->blocks == 0)
a406f5a3 423 break;
a406f5a3 424 }
d129bceb 425
a406f5a3 426 DBG("PIO transfer complete.\n");
d129bceb
PO		 427}
428
48857d9b
RK		 429static int sdhci_pre_dma_transfer(struct sdhci_host *host,
430 struct mmc_data *data)
431{
432 int sg_count;
433
434 if (data->host_cookie == COOKIE_MAPPED) {
435 data->host_cookie = COOKIE_GIVEN;
436 return data->sg_count;
437 }
438
439 WARN_ON(data->host_cookie == COOKIE_GIVEN);
440
441 sg_count = dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
442 data->flags & MMC_DATA_WRITE ?
443 DMA_TO_DEVICE : DMA_FROM_DEVICE);
444
445 if (sg_count == 0)
446 return -ENOSPC;
447
448 data->sg_count = sg_count;
449 data->host_cookie = COOKIE_MAPPED;
450
451 return sg_count;
452}
453
2134a922
PO		 454static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags)
455{
456 local_irq_save(*flags);
482fce99 457 return kmap_atomic(sg_page(sg)) + sg->offset;
2134a922
PO		 458}
459
460static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags)
461{
482fce99 462 kunmap_atomic(buffer);
2134a922
PO		 463 local_irq_restore(*flags);
464}
465
e57a5f61
AH		 466static void sdhci_adma_write_desc(struct sdhci_host *host, void *desc,
467 dma_addr_t addr, int len, unsigned cmd)
118cd17d 468{
e57a5f61 469 struct sdhci_adma2_64_desc *dma_desc = desc;
118cd17d 470
e57a5f61 471 /* 32-bit and 64-bit descriptors have these members in same position */
0545230f
AH		 472 dma_desc->cmd = cpu_to_le16(cmd);
473 dma_desc->len = cpu_to_le16(len);
e57a5f61
AH		 474 dma_desc->addr_lo = cpu_to_le32((u32)addr);
475
476 if (host->flags & SDHCI_USE_64_BIT_DMA)
477 dma_desc->addr_hi = cpu_to_le32((u64)addr >> 32);
118cd17d
BD		 478}
479
b5ffa674
AH		 480static void sdhci_adma_mark_end(void *desc)
481{
e57a5f61 482 struct sdhci_adma2_64_desc *dma_desc = desc;
b5ffa674 483
e57a5f61 484 /* 32-bit and 64-bit descriptors have 'cmd' in same position */
0545230f 485 dma_desc->cmd |= cpu_to_le16(ADMA2_END);
b5ffa674
AH		 486}
487
8f1934ce 488static int sdhci_adma_table_pre(struct sdhci_host *host,
2134a922
PO		 489 struct mmc_data *data)
490{
2134a922 491 struct scatterlist *sg;
2134a922 492 unsigned long flags;
acc3ad13
RK		 493 dma_addr_t addr, align_addr;
494 void *desc, *align;
495 char *buffer;
496 int len, offset, i;
2134a922
PO		 497
498 /*
499 * The spec does not specify endianness of descriptor table.
500 * We currently guess that it is LE.
501 */
502
d31911b9 503 host->sg_count = sdhci_pre_dma_transfer(host, data);
348487cb 504 if (host->sg_count < 0)
edd63fcc 505 return -EINVAL;
2134a922 506
4efaa6fb 507 desc = host->adma_table;
2134a922
PO		 508 align = host->align_buffer;
509
510 align_addr = host->align_addr;
511
512 for_each_sg(data->sg, sg, host->sg_count, i) {
513 addr = sg_dma_address(sg);
514 len = sg_dma_len(sg);
515
516 /*
acc3ad13
RK		 517 * The SDHCI specification states that ADMA addresses must
518 * be 32-bit aligned. If they aren't, then we use a bounce
519 * buffer for the (up to three) bytes that screw up the
2134a922
PO		 520 * alignment.
521 */
04a5ae6f
AH		 522 offset = (SDHCI_ADMA2_ALIGN - (addr & SDHCI_ADMA2_MASK)) &
523 SDHCI_ADMA2_MASK;
2134a922
PO		 524 if (offset) {
525 if (data->flags & MMC_DATA_WRITE) {
526 buffer = sdhci_kmap_atomic(sg, &flags);
527 memcpy(align, buffer, offset);
528 sdhci_kunmap_atomic(buffer, &flags);
529 }
530
118cd17d 531 /* tran, valid */
e57a5f61 532 sdhci_adma_write_desc(host, desc, align_addr, offset,
739d46dc 533 ADMA2_TRAN_VALID);
2134a922
PO		 534
535 BUG_ON(offset > 65536);
536
04a5ae6f
AH		 537 align += SDHCI_ADMA2_ALIGN;
538 align_addr += SDHCI_ADMA2_ALIGN;
2134a922 539
76fe379a 540 desc += host->desc_sz;
2134a922
PO		 541
542 addr += offset;
543 len -= offset;
544 }
545
2134a922
PO		 546 BUG_ON(len > 65536);
547
347ea32d
AH		 548 if (len) {
549 /* tran, valid */
550 sdhci_adma_write_desc(host, desc, addr, len,
551 ADMA2_TRAN_VALID);
552 desc += host->desc_sz;
553 }
2134a922
PO		 554
555 /*
556 * If this triggers then we have a calculation bug
557 * somewhere. :/
558 */
76fe379a 559 WARN_ON((desc - host->adma_table) >= host->adma_table_sz);
2134a922
PO		 560 }
561
70764a90 562 if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) {
acc3ad13 563 /* Mark the last descriptor as the terminating descriptor */
4efaa6fb 564 if (desc != host->adma_table) {
76fe379a 565 desc -= host->desc_sz;
b5ffa674 566 sdhci_adma_mark_end(desc);
70764a90
TA		 567 }
568 } else {
acc3ad13 569 /* Add a terminating entry - nop, end, valid */
e57a5f61 570 sdhci_adma_write_desc(host, desc, 0, 0, ADMA2_NOP_END_VALID);
70764a90 571 }
8f1934ce 572 return 0;
2134a922
PO		 573}
574
575static void sdhci_adma_table_post(struct sdhci_host *host,
576 struct mmc_data *data)
577{
2134a922
PO		 578 struct scatterlist *sg;
579 int i, size;
1c3d5f6d 580 void *align;
2134a922
PO		 581 char *buffer;
582 unsigned long flags;
583
47fa9613
RK		 584 if (data->flags & MMC_DATA_READ) {
585 bool has_unaligned = false;
de0b65a7 586
47fa9613
RK		 587 /* Do a quick scan of the SG list for any unaligned mappings */
588 for_each_sg(data->sg, sg, host->sg_count, i)
589 if (sg_dma_address(sg) & SDHCI_ADMA2_MASK) {
590 has_unaligned = true;
591 break;
592 }
2134a922 593
47fa9613
RK		 594 if (has_unaligned) {
595 dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
f55c98f7 596 data->sg_len, DMA_FROM_DEVICE);
2134a922 597
47fa9613 598 align = host->align_buffer;
2134a922 599
47fa9613
RK		 600 for_each_sg(data->sg, sg, host->sg_count, i) {
601 if (sg_dma_address(sg) & SDHCI_ADMA2_MASK) {
602 size = SDHCI_ADMA2_ALIGN -
603 (sg_dma_address(sg) & SDHCI_ADMA2_MASK);
604
605 buffer = sdhci_kmap_atomic(sg, &flags);
606 memcpy(buffer, align, size);
607 sdhci_kunmap_atomic(buffer, &flags);
2134a922 608
47fa9613
RK		 609 align += SDHCI_ADMA2_ALIGN;
610 }
2134a922
PO		 611 }
612 }
613 }
2134a922
PO		 614}
615
a3c7778f 616static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd)
d129bceb 617{
1c8cde92 618 u8 count;
a3c7778f 619 struct mmc_data *data = cmd->data;
1c8cde92 620 unsigned target_timeout, current_timeout;
d129bceb 621
ee53ab5d
PO		 622 /*
623 * If the host controller provides us with an incorrect timeout
624 * value, just skip the check and use 0xE. The hardware may take
625 * longer to time out, but that's much better than having a too-short
626 * timeout value.
627 */
11a2f1b7 628 if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL)
ee53ab5d 629 return 0xE;
e538fbe8 630
a3c7778f 631 /* Unspecified timeout, assume max */
1d4d7744 632 if (!data && !cmd->busy_timeout)
a3c7778f 633 return 0xE;
d129bceb 634
a3c7778f
AW		 635 /* timeout in us */
636 if (!data)
1d4d7744 637 target_timeout = cmd->busy_timeout * 1000;
78a2ca27 638 else {
fafcfda9 639 target_timeout = DIV_ROUND_UP(data->timeout_ns, 1000);
7f05538a
RK		 640 if (host->clock && data->timeout_clks) {
641 unsigned long long val;
642
643 /*
644 * data->timeout_clks is in units of clock cycles.
645 * host->clock is in Hz. target_timeout is in us.
646 * Hence, us = 1000000 * cycles / Hz. Round up.
647 */
648 val = 1000000 * data->timeout_clks;
649 if (do_div(val, host->clock))
650 target_timeout++;
651 target_timeout += val;
652 }
78a2ca27 653 }
81b39802 654
1c8cde92
PO		 655 /*
656 * Figure out needed cycles.
657 * We do this in steps in order to fit inside a 32 bit int.
658 * The first step is the minimum timeout, which will have a
659 * minimum resolution of 6 bits:
660 * (1) 2^13*1000 > 2^22,
661 * (2) host->timeout_clk < 2^16
662 * =>
663 * (1) / (2) > 2^6
664 */
665 count = 0;
666 current_timeout = (1 << 13) * 1000 / host->timeout_clk;
667 while (current_timeout < target_timeout) {
668 count++;
669 current_timeout <<= 1;
670 if (count >= 0xF)
671 break;
672 }
673
674 if (count >= 0xF) {
09eeff52
CB		 675 DBG("%s: Too large timeout 0x%x requested for CMD%d!\n",
676 mmc_hostname(host->mmc), count, cmd->opcode);
1c8cde92
PO		 677 count = 0xE;
678 }
679
ee53ab5d
PO		 680 return count;
681}
682
6aa943ab
AV		 683static void sdhci_set_transfer_irqs(struct sdhci_host *host)
684{
685 u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL;
686 u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR;
687
688 if (host->flags & SDHCI_REQ_USE_DMA)
b537f94c 689 host->ier = (host->ier & ~pio_irqs) | dma_irqs;
6aa943ab 690 else
b537f94c
RK		 691 host->ier = (host->ier & ~dma_irqs) | pio_irqs;
692
693 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
694 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
6aa943ab
AV		 695}
696
b45e668a 697static void sdhci_set_timeout(struct sdhci_host *host, struct mmc_command *cmd)
ee53ab5d
PO		 698{
699 u8 count;
b45e668a
AD		 700
701 if (host->ops->set_timeout) {
702 host->ops->set_timeout(host, cmd);
703 } else {
704 count = sdhci_calc_timeout(host, cmd);
705 sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
706 }
707}
708
709static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd)
710{
2134a922 711 u8 ctrl;
a3c7778f 712 struct mmc_data *data = cmd->data;
8f1934ce 713 int ret;
ee53ab5d
PO		 714
715 WARN_ON(host->data);
716
b45e668a
AD		 717 if (data || (cmd->flags & MMC_RSP_BUSY))
718 sdhci_set_timeout(host, cmd);
a3c7778f
AW		 719
720 if (!data)
ee53ab5d
PO		 721 return;
722
723 /* Sanity checks */
724 BUG_ON(data->blksz * data->blocks > 524288);
725 BUG_ON(data->blksz > host->mmc->max_blk_size);
726 BUG_ON(data->blocks > 65535);
727
728 host->data = data;
729 host->data_early = 0;
f6a03cbf 730 host->data->bytes_xfered = 0;
ee53ab5d 731
a13abc7b 732 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))
c9fddbc4
PO		 733 host->flags |= SDHCI_REQ_USE_DMA;
734
2134a922
PO		 735 /*
736 * FIXME: This doesn't account for merging when mapping the
737 * scatterlist.
738 */
739 if (host->flags & SDHCI_REQ_USE_DMA) {
740 int broken, i;
741 struct scatterlist *sg;
742
743 broken = 0;
744 if (host->flags & SDHCI_USE_ADMA) {
745 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
746 broken = 1;
747 } else {
748 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE)
749 broken = 1;
750 }
751
752 if (unlikely(broken)) {
753 for_each_sg(data->sg, sg, data->sg_len, i) {
754 if (sg->length & 0x3) {
2e4456f0 755 DBG("Reverting to PIO because of transfer size (%d)\n",
2134a922
PO		 756 sg->length);
757 host->flags &= ~SDHCI_REQ_USE_DMA;
758 break;
759 }
760 }
761 }
c9fddbc4
PO		 762 }
763
764 /*
765 * The assumption here being that alignment is the same after
766 * translation to device address space.
767 */
2134a922
PO		 768 if (host->flags & SDHCI_REQ_USE_DMA) {
769 int broken, i;
770 struct scatterlist *sg;
771
772 broken = 0;
773 if (host->flags & SDHCI_USE_ADMA) {
774 /*
775 * As we use 3 byte chunks to work around
776 * alignment problems, we need to check this
777 * quirk.
778 */
779 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
780 broken = 1;
781 } else {
782 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR)
783 broken = 1;
784 }
785
786 if (unlikely(broken)) {
787 for_each_sg(data->sg, sg, data->sg_len, i) {
788 if (sg->offset & 0x3) {
2e4456f0 789 DBG("Reverting to PIO because of bad alignment\n");
2134a922
PO		 790 host->flags &= ~SDHCI_REQ_USE_DMA;
791 break;
792 }
793 }
794 }
795 }
796
8f1934ce
PO		 797 if (host->flags & SDHCI_REQ_USE_DMA) {
798 if (host->flags & SDHCI_USE_ADMA) {
799 ret = sdhci_adma_table_pre(host, data);
800 if (ret) {
801 /*
802 * This only happens when someone fed
803 * us an invalid request.
804 */
805 WARN_ON(1);
ebd6d357 806 host->flags &= ~SDHCI_REQ_USE_DMA;
8f1934ce 807 } else {
4e4141a5
AV		 808 sdhci_writel(host, host->adma_addr,
809 SDHCI_ADMA_ADDRESS);
e57a5f61
AH		 810 if (host->flags & SDHCI_USE_64_BIT_DMA)
811 sdhci_writel(host,
812 (u64)host->adma_addr >> 32,
813 SDHCI_ADMA_ADDRESS_HI);
8f1934ce
PO		 814 }
815 } else {
c8b3e02e 816 int sg_cnt;
8f1934ce 817
d31911b9 818 sg_cnt = sdhci_pre_dma_transfer(host, data);
62a7f368 819 if (sg_cnt <= 0) {
8f1934ce
PO		 820 /*
821 * This only happens when someone fed
822 * us an invalid request.
823 */
824 WARN_ON(1);
ebd6d357 825 host->flags &= ~SDHCI_REQ_USE_DMA;
8f1934ce 826 } else {
719a61b4 827 WARN_ON(sg_cnt != 1);
4e4141a5
AV		 828 sdhci_writel(host, sg_dma_address(data->sg),
829 SDHCI_DMA_ADDRESS);
8f1934ce
PO		 830 }
831 }
832 }
833
2134a922
PO		 834 /*
835 * Always adjust the DMA selection as some controllers
836 * (e.g. JMicron) can't do PIO properly when the selection
837 * is ADMA.
838 */
839 if (host->version >= SDHCI_SPEC_200) {
4e4141a5 840 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
2134a922
PO		 841 ctrl &= ~SDHCI_CTRL_DMA_MASK;
842 if ((host->flags & SDHCI_REQ_USE_DMA) &&
e57a5f61
AH		 843 (host->flags & SDHCI_USE_ADMA)) {
844 if (host->flags & SDHCI_USE_64_BIT_DMA)
845 ctrl |= SDHCI_CTRL_ADMA64;
846 else
847 ctrl |= SDHCI_CTRL_ADMA32;
848 } else {
2134a922 849 ctrl |= SDHCI_CTRL_SDMA;
e57a5f61 850 }
4e4141a5 851 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
c9fddbc4
PO		 852 }
853
8f1934ce 854 if (!(host->flags & SDHCI_REQ_USE_DMA)) {
da60a91d
SAS		 855 int flags;
856
857 flags = SG_MITER_ATOMIC;
858 if (host->data->flags & MMC_DATA_READ)
859 flags |= SG_MITER_TO_SG;
860 else
861 flags |= SG_MITER_FROM_SG;
862 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
7659150c 863 host->blocks = data->blocks;
d129bceb 864 }
c7fa9963 865
6aa943ab
AV		 866 sdhci_set_transfer_irqs(host);
867
f6a03cbf
MV		 868 /* Set the DMA boundary value and block size */
869 sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
870 data->blksz), SDHCI_BLOCK_SIZE);
4e4141a5 871 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
c7fa9963
PO		 872}
873
874static void sdhci_set_transfer_mode(struct sdhci_host *host,
e89d456f 875 struct mmc_command *cmd)
c7fa9963 876{
d3fc5d71 877 u16 mode = 0;
e89d456f 878 struct mmc_data *data = cmd->data;
c7fa9963 879
2b558c13 880 if (data == NULL) {
9b8ffea6
VW		 881 if (host->quirks2 &
882 SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD) {
883 sdhci_writew(host, 0x0, SDHCI_TRANSFER_MODE);
884 } else {
2b558c13 885 /* clear Auto CMD settings for no data CMDs */
9b8ffea6
VW		 886 mode = sdhci_readw(host, SDHCI_TRANSFER_MODE);
887 sdhci_writew(host, mode & ~(SDHCI_TRNS_AUTO_CMD12 |
2b558c13 888 SDHCI_TRNS_AUTO_CMD23), SDHCI_TRANSFER_MODE);
9b8ffea6 889 }
c7fa9963 890 return;
2b558c13 891 }
c7fa9963 892
e538fbe8
PO		 893 WARN_ON(!host->data);
894
d3fc5d71
VY		 895 if (!(host->quirks2 & SDHCI_QUIRK2_SUPPORT_SINGLE))
896 mode = SDHCI_TRNS_BLK_CNT_EN;
897
e89d456f 898 if (mmc_op_multi(cmd->opcode) || data->blocks > 1) {
d3fc5d71 899 mode = SDHCI_TRNS_BLK_CNT_EN | SDHCI_TRNS_MULTI;
e89d456f
AW		 900 /*
901 * If we are sending CMD23, CMD12 never gets sent
902 * on successful completion (so no Auto-CMD12).
903 */
85cc1c33
CD		 904 if (!host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD12) &&
905 (cmd->opcode != SD_IO_RW_EXTENDED))
e89d456f 906 mode |= SDHCI_TRNS_AUTO_CMD12;
8edf6371
AW		 907 else if (host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) {
908 mode |= SDHCI_TRNS_AUTO_CMD23;
909 sdhci_writel(host, host->mrq->sbc->arg, SDHCI_ARGUMENT2);
910 }
c4512f79 911 }
8edf6371 912
c7fa9963
PO		 913 if (data->flags & MMC_DATA_READ)
914 mode |= SDHCI_TRNS_READ;
c9fddbc4 915 if (host->flags & SDHCI_REQ_USE_DMA)
c7fa9963
PO		 916 mode |= SDHCI_TRNS_DMA;
917
4e4141a5 918 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
d129bceb
PO		 919}
920
921static void sdhci_finish_data(struct sdhci_host *host)
922{
923 struct mmc_data *data;
d129bceb
PO		 924
925 BUG_ON(!host->data);
926
927 data = host->data;
928 host->data = NULL;
929
c9fddbc4 930 if (host->flags & SDHCI_REQ_USE_DMA) {
2134a922
PO		 931 if (host->flags & SDHCI_USE_ADMA)
932 sdhci_adma_table_post(host, data);
f55c98f7
RK		 933
934 if (data->host_cookie == COOKIE_MAPPED) {
935 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
936 (data->flags & MMC_DATA_READ) ?
937 DMA_FROM_DEVICE : DMA_TO_DEVICE);
938 data->host_cookie = COOKIE_UNMAPPED;
2134a922 939 }
d129bceb
PO		 940 }
941
942 /*
c9b74c5b
PO		 943 * The specification states that the block count register must
944 * be updated, but it does not specify at what point in the
945 * data flow. That makes the register entirely useless to read
946 * back so we have to assume that nothing made it to the card
947 * in the event of an error.
d129bceb 948 */
c9b74c5b
PO		 949 if (data->error)
950 data->bytes_xfered = 0;
d129bceb 951 else
c9b74c5b 952 data->bytes_xfered = data->blksz * data->blocks;
d129bceb 953
e89d456f
AW		 954 /*
955 * Need to send CMD12 if -
956 * a) open-ended multiblock transfer (no CMD23)
957 * b) error in multiblock transfer
958 */
959 if (data->stop &&
960 (data->error ||
961 !host->mrq->sbc)) {
962
d129bceb
PO		 963 /*
964 * The controller needs a reset of internal state machines
965 * upon error conditions.
966 */
17b0429d 967 if (data->error) {
03231f9b
RK		 968 sdhci_do_reset(host, SDHCI_RESET_CMD);
969 sdhci_do_reset(host, SDHCI_RESET_DATA);
d129bceb
PO		 970 }
971
972 sdhci_send_command(host, data->stop);
973 } else
974 tasklet_schedule(&host->finish_tasklet);
975}
976
c0e55129 977void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
d129bceb
PO		 978{
979 int flags;
fd2208d7 980 u32 mask;
7cb2c76f 981 unsigned long timeout;
d129bceb
PO		 982
983 WARN_ON(host->cmd);
984
96776200
RK		 985 /* Initially, a command has no error */
986 cmd->error = 0;
987
d129bceb 988 /* Wait max 10 ms */
7cb2c76f 989 timeout = 10;
fd2208d7
PO		 990
991 mask = SDHCI_CMD_INHIBIT;
992 if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
993 mask |= SDHCI_DATA_INHIBIT;
994
995 /* We shouldn't wait for data inihibit for stop commands, even
996 though they might use busy signaling */
997 if (host->mrq->data && (cmd == host->mrq->data->stop))
998 mask &= ~SDHCI_DATA_INHIBIT;
999
4e4141a5 1000 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
7cb2c76f 1001 if (timeout == 0) {
2e4456f0
MV		 1002 pr_err("%s: Controller never released inhibit bit(s).\n",
1003 mmc_hostname(host->mmc));
d129bceb 1004 sdhci_dumpregs(host);
17b0429d 1005 cmd->error = -EIO;
d129bceb
PO		 1006 tasklet_schedule(&host->finish_tasklet);
1007 return;
1008 }
7cb2c76f
PO		 1009 timeout--;
1010 mdelay(1);
1011 }
d129bceb 1012
3e1a6892 1013 timeout = jiffies;
1d4d7744
UH		 1014 if (!cmd->data && cmd->busy_timeout > 9000)
1015 timeout += DIV_ROUND_UP(cmd->busy_timeout, 1000) * HZ + HZ;
3e1a6892
AH		 1016 else
1017 timeout += 10 * HZ;
1018 mod_timer(&host->timer, timeout);
d129bceb
PO		 1019
1020 host->cmd = cmd;
e99783a4 1021 host->busy_handle = 0;
d129bceb 1022
a3c7778f 1023 sdhci_prepare_data(host, cmd);
d129bceb 1024
4e4141a5 1025 sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT);
d129bceb 1026
e89d456f 1027 sdhci_set_transfer_mode(host, cmd);
c7fa9963 1028
d129bceb 1029 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
a3c76eb9 1030 pr_err("%s: Unsupported response type!\n",
d129bceb 1031 mmc_hostname(host->mmc));
17b0429d 1032 cmd->error = -EINVAL;
d129bceb
PO		 1033 tasklet_schedule(&host->finish_tasklet);
1034 return;
1035 }
1036
1037 if (!(cmd->flags & MMC_RSP_PRESENT))
1038 flags = SDHCI_CMD_RESP_NONE;
1039 else if (cmd->flags & MMC_RSP_136)
1040 flags = SDHCI_CMD_RESP_LONG;
1041 else if (cmd->flags & MMC_RSP_BUSY)
1042 flags = SDHCI_CMD_RESP_SHORT_BUSY;
1043 else
1044 flags = SDHCI_CMD_RESP_SHORT;
1045
1046 if (cmd->flags & MMC_RSP_CRC)
1047 flags |= SDHCI_CMD_CRC;
1048 if (cmd->flags & MMC_RSP_OPCODE)
1049 flags |= SDHCI_CMD_INDEX;
b513ea25
AN		 1050
1051 /* CMD19 is special in that the Data Present Select should be set */
069c9f14
G		 1052 if (cmd->data || cmd->opcode == MMC_SEND_TUNING_BLOCK ||
1053 cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200)
d129bceb
PO		 1054 flags |= SDHCI_CMD_DATA;
1055
4e4141a5 1056 sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND);
d129bceb 1057}
c0e55129 1058EXPORT_SYMBOL_GPL(sdhci_send_command);
d129bceb
PO		 1059
1060static void sdhci_finish_command(struct sdhci_host *host)
1061{
1062 int i;
1063
1064 BUG_ON(host->cmd == NULL);
1065
1066 if (host->cmd->flags & MMC_RSP_PRESENT) {
1067 if (host->cmd->flags & MMC_RSP_136) {
1068 /* CRC is stripped so we need to do some shifting. */
1069 for (i = 0;i < 4;i++) {
4e4141a5 1070 host->cmd->resp[i] = sdhci_readl(host,
d129bceb
PO		 1071 SDHCI_RESPONSE + (3-i)*4) << 8;
1072 if (i != 3)
1073 host->cmd->resp[i] |=
4e4141a5 1074 sdhci_readb(host,
d129bceb
PO		 1075 SDHCI_RESPONSE + (3-i)*4-1);
1076 }
1077 } else {
4e4141a5 1078 host->cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE);
d129bceb
PO		 1079 }
1080 }
1081
e89d456f
AW		 1082 /* Finished CMD23, now send actual command. */
1083 if (host->cmd == host->mrq->sbc) {
1084 host->cmd = NULL;
1085 sdhci_send_command(host, host->mrq->cmd);
1086 } else {
e538fbe8 1087
e89d456f
AW		 1088 /* Processed actual command. */
1089 if (host->data && host->data_early)
1090 sdhci_finish_data(host);
d129bceb 1091
e89d456f
AW		 1092 if (!host->cmd->data)
1093 tasklet_schedule(&host->finish_tasklet);
1094
1095 host->cmd = NULL;
1096 }
d129bceb
PO		 1097}
1098
52983382
KL		 1099static u16 sdhci_get_preset_value(struct sdhci_host *host)
1100{
d975f121 1101 u16 preset = 0;
52983382 1102
d975f121
RK		 1103 switch (host->timing) {
1104 case MMC_TIMING_UHS_SDR12:
52983382
KL		 1105 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1106 break;
d975f121 1107 case MMC_TIMING_UHS_SDR25:
52983382
KL		 1108 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR25);
1109 break;
d975f121 1110 case MMC_TIMING_UHS_SDR50:
52983382
KL		 1111 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR50);
1112 break;
d975f121
RK		 1113 case MMC_TIMING_UHS_SDR104:
1114 case MMC_TIMING_MMC_HS200:
52983382
KL		 1115 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR104);
1116 break;
d975f121 1117 case MMC_TIMING_UHS_DDR50:
0dafa60e 1118 case MMC_TIMING_MMC_DDR52:
52983382
KL		 1119 preset = sdhci_readw(host, SDHCI_PRESET_FOR_DDR50);
1120 break;
e9fb05d5
AH		 1121 case MMC_TIMING_MMC_HS400:
1122 preset = sdhci_readw(host, SDHCI_PRESET_FOR_HS400);
1123 break;
52983382
KL		 1124 default:
1125 pr_warn("%s: Invalid UHS-I mode selected\n",
1126 mmc_hostname(host->mmc));
1127 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1128 break;
1129 }
1130 return preset;
1131}
1132
1771059c 1133void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
d129bceb 1134{
c3ed3877 1135 int div = 0; /* Initialized for compiler warning */
df16219f 1136 int real_div = div, clk_mul = 1;
c3ed3877 1137 u16 clk = 0;
7cb2c76f 1138 unsigned long timeout;
5497159c 1139 bool switch_base_clk = false;
d129bceb 1140
1650d0c7
RK		 1141 host->mmc->actual_clock = 0;
1142
4e4141a5 1143 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
af951761 1144 if (host->quirks2 & SDHCI_QUIRK2_NEED_DELAY_AFTER_INT_CLK_RST)
1145 mdelay(1);
d129bceb
PO		 1146
1147 if (clock == 0)
373073ef 1148 return;
d129bceb 1149
85105c53 1150 if (host->version >= SDHCI_SPEC_300) {
da91a8f9 1151 if (host->preset_enabled) {
52983382
KL		 1152 u16 pre_val;
1153
1154 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1155 pre_val = sdhci_get_preset_value(host);
1156 div = (pre_val & SDHCI_PRESET_SDCLK_FREQ_MASK)
1157 >> SDHCI_PRESET_SDCLK_FREQ_SHIFT;
1158 if (host->clk_mul &&
1159 (pre_val & SDHCI_PRESET_CLKGEN_SEL_MASK)) {
1160 clk = SDHCI_PROG_CLOCK_MODE;
1161 real_div = div + 1;
1162 clk_mul = host->clk_mul;
1163 } else {
1164 real_div = max_t(int, 1, div << 1);
1165 }
1166 goto clock_set;
1167 }
1168
c3ed3877
AN		 1169 /*
1170 * Check if the Host Controller supports Programmable Clock
1171 * Mode.
1172 */
1173 if (host->clk_mul) {
52983382
KL		 1174 for (div = 1; div <= 1024; div++) {
1175 if ((host->max_clk * host->clk_mul / div)
1176 <= clock)
1177 break;
1178 }
5497159c 1179 if ((host->max_clk * host->clk_mul / div) <= clock) {
1180 /*
1181 * Set Programmable Clock Mode in the Clock
1182 * Control register.
1183 */
1184 clk = SDHCI_PROG_CLOCK_MODE;
1185 real_div = div;
1186 clk_mul = host->clk_mul;
1187 div--;
1188 } else {
1189 /*
1190 * Divisor can be too small to reach clock
1191 * speed requirement. Then use the base clock.
1192 */
1193 switch_base_clk = true;
1194 }
1195 }
1196
1197 if (!host->clk_mul || switch_base_clk) {
c3ed3877
AN		 1198 /* Version 3.00 divisors must be a multiple of 2. */
1199 if (host->max_clk <= clock)
1200 div = 1;
1201 else {
1202 for (div = 2; div < SDHCI_MAX_DIV_SPEC_300;
1203 div += 2) {
1204 if ((host->max_clk / div) <= clock)
1205 break;
1206 }
85105c53 1207 }
df16219f 1208 real_div = div;
c3ed3877 1209 div >>= 1;
d1955c3a
SG		 1210 if ((host->quirks2 & SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN)
1211 && !div && host->max_clk <= 25000000)
1212 div = 1;
85105c53
ZG		 1213 }
1214 } else {
1215 /* Version 2.00 divisors must be a power of 2. */
0397526d 1216 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
85105c53
ZG		 1217 if ((host->max_clk / div) <= clock)
1218 break;
1219 }
df16219f 1220 real_div = div;
c3ed3877 1221 div >>= 1;
d129bceb 1222 }
d129bceb 1223
52983382 1224clock_set:
03d6f5ff 1225 if (real_div)
df16219f 1226 host->mmc->actual_clock = (host->max_clk * clk_mul) / real_div;
c3ed3877 1227 clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
85105c53
ZG		 1228 clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
1229 << SDHCI_DIVIDER_HI_SHIFT;
d129bceb 1230 clk |= SDHCI_CLOCK_INT_EN;
4e4141a5 1231 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
d129bceb 1232
27f6cb16
CB		 1233 /* Wait max 20 ms */
1234 timeout = 20;
4e4141a5 1235 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
7cb2c76f
PO		 1236 & SDHCI_CLOCK_INT_STABLE)) {
1237 if (timeout == 0) {
2e4456f0
MV		 1238 pr_err("%s: Internal clock never stabilised.\n",
1239 mmc_hostname(host->mmc));
d129bceb
PO		 1240 sdhci_dumpregs(host);
1241 return;
1242 }
7cb2c76f
PO		 1243 timeout--;
1244 mdelay(1);
1245 }
d129bceb
PO		 1246
1247 clk |= SDHCI_CLOCK_CARD_EN;
4e4141a5 1248 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
d129bceb 1249}
1771059c 1250EXPORT_SYMBOL_GPL(sdhci_set_clock);
d129bceb 1251
24fbb3ca
RK		 1252static void sdhci_set_power(struct sdhci_host *host, unsigned char mode,
1253 unsigned short vdd)
146ad66e 1254{
3a48edc4 1255 struct mmc_host *mmc = host->mmc;
8364248a 1256 u8 pwr = 0;
146ad66e 1257
24fbb3ca
RK		 1258 if (mode != MMC_POWER_OFF) {
1259 switch (1 << vdd) {
ae628903
PO		 1260 case MMC_VDD_165_195:
1261 pwr = SDHCI_POWER_180;
1262 break;
1263 case MMC_VDD_29_30:
1264 case MMC_VDD_30_31:
1265 pwr = SDHCI_POWER_300;
1266 break;
1267 case MMC_VDD_32_33:
1268 case MMC_VDD_33_34:
1269 pwr = SDHCI_POWER_330;
1270 break;
1271 default:
9d5de93f
AH		 1272 WARN(1, "%s: Invalid vdd %#x\n",
1273 mmc_hostname(host->mmc), vdd);
1274 break;
ae628903
PO		 1275 }
1276 }
1277
1278 if (host->pwr == pwr)
e921a8b6 1279 return;
146ad66e 1280
ae628903
PO		 1281 host->pwr = pwr;
1282
1283 if (pwr == 0) {
4e4141a5 1284 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
f0710a55
AH		 1285 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
1286 sdhci_runtime_pm_bus_off(host);
24fbb3ca 1287 vdd = 0;
e921a8b6
RK		 1288 } else {
1289 /*
1290 * Spec says that we should clear the power reg before setting
1291 * a new value. Some controllers don't seem to like this though.
1292 */
1293 if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
1294 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
146ad66e 1295
e921a8b6
RK		 1296 /*
1297 * At least the Marvell CaFe chip gets confused if we set the
1298 * voltage and set turn on power at the same time, so set the
1299 * voltage first.
1300 */
1301 if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
1302 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
e08c1694 1303
e921a8b6 1304 pwr |= SDHCI_POWER_ON;
146ad66e 1305
e921a8b6 1306 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
557b0697 1307
e921a8b6
RK		 1308 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
1309 sdhci_runtime_pm_bus_on(host);
f0710a55 1310
e921a8b6
RK		 1311 /*
1312 * Some controllers need an extra 10ms delay of 10ms before
1313 * they can apply clock after applying power
1314 */
1315 if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER)
1316 mdelay(10);
1317 }
918f4cbd
JZ		 1318
1319 if (!IS_ERR(mmc->supply.vmmc)) {
1320 spin_unlock_irq(&host->lock);
1321 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd);
1322 spin_lock_irq(&host->lock);
1323 }
146ad66e
PO		 1324}
1325
d129bceb
PO		 1326/*****************************************************************************\
1327 * *
1328 * MMC callbacks *
1329 * *
1330\*****************************************************************************/
1331
1332static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1333{
1334 struct sdhci_host *host;
505a8680 1335 int present;
d129bceb
PO		 1336 unsigned long flags;
1337
1338 host = mmc_priv(mmc);
1339
66fd8ad5
AH		 1340 sdhci_runtime_pm_get(host);
1341
04e079cf 1342 /* Firstly check card presence */
8d28b7a7 1343 present = mmc->ops->get_cd(mmc);
2836766a 1344
d129bceb
PO		 1345 spin_lock_irqsave(&host->lock, flags);
1346
1347 WARN_ON(host->mrq != NULL);
1348
f9134319 1349#ifndef SDHCI_USE_LEDS_CLASS
d129bceb 1350 sdhci_activate_led(host);
2f730fec 1351#endif
e89d456f
AW		 1352
1353 /*
1354 * Ensure we don't send the STOP for non-SET_BLOCK_COUNTED
1355 * requests if Auto-CMD12 is enabled.
1356 */
1357 if (!mrq->sbc && (host->flags & SDHCI_AUTO_CMD12)) {
c4512f79
JH		 1358 if (mrq->stop) {
1359 mrq->data->stop = NULL;
1360 mrq->stop = NULL;
1361 }
1362 }
d129bceb
PO		 1363
1364 host->mrq = mrq;
1365
68d1fb7e 1366 if (!present || host->flags & SDHCI_DEVICE_DEAD) {
17b0429d 1367 host->mrq->cmd->error = -ENOMEDIUM;
d129bceb 1368 tasklet_schedule(&host->finish_tasklet);
cf2b5eea 1369 } else {
8edf6371 1370 if (mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23))
e89d456f
AW		 1371 sdhci_send_command(host, mrq->sbc);
1372 else
1373 sdhci_send_command(host, mrq->cmd);
cf2b5eea 1374 }
d129bceb 1375
5f25a66f 1376 mmiowb();
d129bceb
PO		 1377 spin_unlock_irqrestore(&host->lock, flags);
1378}
1379
2317f56c
RK		 1380void sdhci_set_bus_width(struct sdhci_host *host, int width)
1381{
1382 u8 ctrl;
1383
1384 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1385 if (width == MMC_BUS_WIDTH_8) {
1386 ctrl &= ~SDHCI_CTRL_4BITBUS;
1387 if (host->version >= SDHCI_SPEC_300)
1388 ctrl |= SDHCI_CTRL_8BITBUS;
1389 } else {
1390 if (host->version >= SDHCI_SPEC_300)
1391 ctrl &= ~SDHCI_CTRL_8BITBUS;
1392 if (width == MMC_BUS_WIDTH_4)
1393 ctrl |= SDHCI_CTRL_4BITBUS;
1394 else
1395 ctrl &= ~SDHCI_CTRL_4BITBUS;
1396 }
1397 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1398}
1399EXPORT_SYMBOL_GPL(sdhci_set_bus_width);
1400
96d7b78c
RK		 1401void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing)
1402{
1403 u16 ctrl_2;
1404
1405 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1406 /* Select Bus Speed Mode for host */
1407 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
1408 if ((timing == MMC_TIMING_MMC_HS200) ||
1409 (timing == MMC_TIMING_UHS_SDR104))
1410 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
1411 else if (timing == MMC_TIMING_UHS_SDR12)
1412 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
1413 else if (timing == MMC_TIMING_UHS_SDR25)
1414 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
1415 else if (timing == MMC_TIMING_UHS_SDR50)
1416 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
1417 else if ((timing == MMC_TIMING_UHS_DDR50) ||
1418 (timing == MMC_TIMING_MMC_DDR52))
1419 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
e9fb05d5
AH		 1420 else if (timing == MMC_TIMING_MMC_HS400)
1421 ctrl_2 |= SDHCI_CTRL_HS400; /* Non-standard */
96d7b78c
RK		 1422 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1423}
1424EXPORT_SYMBOL_GPL(sdhci_set_uhs_signaling);
1425
66fd8ad5 1426static void sdhci_do_set_ios(struct sdhci_host *host, struct mmc_ios *ios)
d129bceb 1427{
d129bceb
PO		 1428 unsigned long flags;
1429 u8 ctrl;
3a48edc4 1430 struct mmc_host *mmc = host->mmc;
d129bceb 1431
d129bceb
PO		 1432 spin_lock_irqsave(&host->lock, flags);
1433
ceb6143b
AH		 1434 if (host->flags & SDHCI_DEVICE_DEAD) {
1435 spin_unlock_irqrestore(&host->lock, flags);
3a48edc4
TK		 1436 if (!IS_ERR(mmc->supply.vmmc) &&
1437 ios->power_mode == MMC_POWER_OFF)
4e743f1f 1438 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
ceb6143b
AH		 1439 return;
1440 }
1e72859e 1441
d129bceb
PO		 1442 /*
1443 * Reset the chip on each power off.
1444 * Should clear out any weird states.
1445 */
1446 if (ios->power_mode == MMC_POWER_OFF) {
4e4141a5 1447 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
7260cf5e 1448 sdhci_reinit(host);
d129bceb
PO		 1449 }
1450
52983382 1451 if (host->version >= SDHCI_SPEC_300 &&
372c4634
DA		 1452 (ios->power_mode == MMC_POWER_UP) &&
1453 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN))
52983382
KL		 1454 sdhci_enable_preset_value(host, false);
1455
373073ef 1456 if (!ios->clock || ios->clock != host->clock) {
1771059c 1457 host->ops->set_clock(host, ios->clock);
373073ef 1458 host->clock = ios->clock;
03d6f5ff
AD		 1459
1460 if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK &&
1461 host->clock) {
1462 host->timeout_clk = host->mmc->actual_clock ?
1463 host->mmc->actual_clock / 1000 :
1464 host->clock / 1000;
1465 host->mmc->max_busy_timeout =
1466 host->ops->get_max_timeout_count ?
1467 host->ops->get_max_timeout_count(host) :
1468 1 << 27;
1469 host->mmc->max_busy_timeout /= host->timeout_clk;
1470 }
373073ef 1471 }
d129bceb 1472
24fbb3ca 1473 sdhci_set_power(host, ios->power_mode, ios->vdd);
d129bceb 1474
643a81ff
PR		 1475 if (host->ops->platform_send_init_74_clocks)
1476 host->ops->platform_send_init_74_clocks(host, ios->power_mode);
1477
2317f56c 1478 host->ops->set_bus_width(host, ios->bus_width);
ae6d6c92 1479
15ec4461 1480 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
cd9277c0 1481
3ab9c8da
PR		 1482 if ((ios->timing == MMC_TIMING_SD_HS ||
1483 ios->timing == MMC_TIMING_MMC_HS)
1484 && !(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT))
cd9277c0
PO		 1485 ctrl |= SDHCI_CTRL_HISPD;
1486 else
1487 ctrl &= ~SDHCI_CTRL_HISPD;
1488
d6d50a15 1489 if (host->version >= SDHCI_SPEC_300) {
49c468fc 1490 u16 clk, ctrl_2;
49c468fc
AN		 1491
1492 /* In case of UHS-I modes, set High Speed Enable */
e9fb05d5
AH		 1493 if ((ios->timing == MMC_TIMING_MMC_HS400) ||
1494 (ios->timing == MMC_TIMING_MMC_HS200) ||
bb8175a8 1495 (ios->timing == MMC_TIMING_MMC_DDR52) ||
069c9f14 1496 (ios->timing == MMC_TIMING_UHS_SDR50) ||
49c468fc
AN		 1497 (ios->timing == MMC_TIMING_UHS_SDR104) ||
1498 (ios->timing == MMC_TIMING_UHS_DDR50) ||
dd8df17f 1499 (ios->timing == MMC_TIMING_UHS_SDR25))
49c468fc 1500 ctrl |= SDHCI_CTRL_HISPD;
d6d50a15 1501
da91a8f9 1502 if (!host->preset_enabled) {
758535c4 1503 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d6d50a15
AN		 1504 /*
1505 * We only need to set Driver Strength if the
1506 * preset value enable is not set.
1507 */
da91a8f9 1508 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
d6d50a15
AN		 1509 ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK;
1510 if (ios->drv_type == MMC_SET_DRIVER_TYPE_A)
1511 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A;
43e943a0
PG		 1512 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_B)
1513 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_B;
d6d50a15
AN		 1514 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C)
1515 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C;
43e943a0
PG		 1516 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_D)
1517 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_D;
1518 else {
2e4456f0
MV		 1519 pr_warn("%s: invalid driver type, default to driver type B\n",
1520 mmc_hostname(mmc));
43e943a0
PG		 1521 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_B;
1522 }
d6d50a15
AN		 1523
1524 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
758535c4
AN		 1525 } else {
1526 /*
1527 * According to SDHC Spec v3.00, if the Preset Value
1528 * Enable in the Host Control 2 register is set, we
1529 * need to reset SD Clock Enable before changing High
1530 * Speed Enable to avoid generating clock gliches.
1531 */
758535c4
AN		 1532
1533 /* Reset SD Clock Enable */
1534 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1535 clk &= ~SDHCI_CLOCK_CARD_EN;
1536 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1537
1538 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1539
1540 /* Re-enable SD Clock */
1771059c 1541 host->ops->set_clock(host, host->clock);
d6d50a15 1542 }
49c468fc 1543
49c468fc
AN		 1544 /* Reset SD Clock Enable */
1545 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1546 clk &= ~SDHCI_CLOCK_CARD_EN;
1547 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1548
96d7b78c 1549 host->ops->set_uhs_signaling(host, ios->timing);
d975f121 1550 host->timing = ios->timing;
49c468fc 1551
52983382
KL		 1552 if (!(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN) &&
1553 ((ios->timing == MMC_TIMING_UHS_SDR12) ||
1554 (ios->timing == MMC_TIMING_UHS_SDR25) ||
1555 (ios->timing == MMC_TIMING_UHS_SDR50) ||
1556 (ios->timing == MMC_TIMING_UHS_SDR104) ||
0dafa60e
JZ		 1557 (ios->timing == MMC_TIMING_UHS_DDR50) ||
1558 (ios->timing == MMC_TIMING_MMC_DDR52))) {
52983382
KL		 1559 u16 preset;
1560
1561 sdhci_enable_preset_value(host, true);
1562 preset = sdhci_get_preset_value(host);
1563 ios->drv_type = (preset & SDHCI_PRESET_DRV_MASK)
1564 >> SDHCI_PRESET_DRV_SHIFT;
1565 }
1566
49c468fc 1567 /* Re-enable SD Clock */
1771059c 1568 host->ops->set_clock(host, host->clock);
758535c4
AN		 1569 } else
1570 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d6d50a15 1571
b8352260
LD		 1572 /*
1573 * Some (ENE) controllers go apeshit on some ios operation,
1574 * signalling timeout and CRC errors even on CMD0. Resetting
1575 * it on each ios seems to solve the problem.
1576 */
c63705e1 1577 if (host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
03231f9b 1578 sdhci_do_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
b8352260 1579
5f25a66f 1580 mmiowb();
d129bceb
PO		 1581 spin_unlock_irqrestore(&host->lock, flags);
1582}
1583
66fd8ad5
AH		 1584static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1585{
1586 struct sdhci_host *host = mmc_priv(mmc);
1587
1588 sdhci_runtime_pm_get(host);
1589 sdhci_do_set_ios(host, ios);
1590 sdhci_runtime_pm_put(host);
1591}
1592
94144a46
KL		 1593static int sdhci_do_get_cd(struct sdhci_host *host)
1594{
1595 int gpio_cd = mmc_gpio_get_cd(host->mmc);
1596
1597 if (host->flags & SDHCI_DEVICE_DEAD)
1598 return 0;
1599
88af5655
II		 1600 /* If nonremovable, assume that the card is always present. */
1601 if (host->mmc->caps & MMC_CAP_NONREMOVABLE)
94144a46
KL		 1602 return 1;
1603
88af5655
II		 1604 /*
1605 * Try slot gpio detect, if defined it take precedence
1606 * over build in controller functionality
1607 */
94144a46
KL		 1608 if (!IS_ERR_VALUE(gpio_cd))
1609 return !!gpio_cd;
1610
88af5655
II		 1611 /* If polling, assume that the card is always present. */
1612 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
1613 return 1;
1614
94144a46
KL		 1615 /* Host native card detect */
1616 return !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
1617}
1618
1619static int sdhci_get_cd(struct mmc_host *mmc)
1620{
1621 struct sdhci_host *host = mmc_priv(mmc);
1622 int ret;
1623
1624 sdhci_runtime_pm_get(host);
1625 ret = sdhci_do_get_cd(host);
1626 sdhci_runtime_pm_put(host);
1627 return ret;
1628}
1629
66fd8ad5 1630static int sdhci_check_ro(struct sdhci_host *host)
d129bceb 1631{
d129bceb 1632 unsigned long flags;
2dfb579c 1633 int is_readonly;
d129bceb 1634
d129bceb
PO		 1635 spin_lock_irqsave(&host->lock, flags);
1636
1e72859e 1637 if (host->flags & SDHCI_DEVICE_DEAD)
2dfb579c
WS		 1638 is_readonly = 0;
1639 else if (host->ops->get_ro)
1640 is_readonly = host->ops->get_ro(host);
1e72859e 1641 else
2dfb579c
WS		 1642 is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE)
1643 & SDHCI_WRITE_PROTECT);
d129bceb
PO		 1644
1645 spin_unlock_irqrestore(&host->lock, flags);
1646
2dfb579c
WS		 1647 /* This quirk needs to be replaced by a callback-function later */
1648 return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ?
1649 !is_readonly : is_readonly;
d129bceb
PO		 1650}
1651
82b0e23a
TI		 1652#define SAMPLE_COUNT 5
1653
66fd8ad5 1654static int sdhci_do_get_ro(struct sdhci_host *host)
82b0e23a 1655{
82b0e23a
TI		 1656 int i, ro_count;
1657
82b0e23a 1658 if (!(host->quirks & SDHCI_QUIRK_UNSTABLE_RO_DETECT))
66fd8ad5 1659 return sdhci_check_ro(host);
82b0e23a
TI		 1660
1661 ro_count = 0;
1662 for (i = 0; i < SAMPLE_COUNT; i++) {
66fd8ad5 1663 if (sdhci_check_ro(host)) {
82b0e23a
TI		 1664 if (++ro_count > SAMPLE_COUNT / 2)
1665 return 1;
1666 }
1667 msleep(30);
1668 }
1669 return 0;
1670}
1671
20758b66
AH		 1672static void sdhci_hw_reset(struct mmc_host *mmc)
1673{
1674 struct sdhci_host *host = mmc_priv(mmc);
1675
1676 if (host->ops && host->ops->hw_reset)
1677 host->ops->hw_reset(host);
1678}
1679
66fd8ad5 1680static int sdhci_get_ro(struct mmc_host *mmc)
f75979b7 1681{
66fd8ad5
AH		 1682 struct sdhci_host *host = mmc_priv(mmc);
1683 int ret;
f75979b7 1684
66fd8ad5
AH		 1685 sdhci_runtime_pm_get(host);
1686 ret = sdhci_do_get_ro(host);
1687 sdhci_runtime_pm_put(host);
1688 return ret;
1689}
f75979b7 1690
66fd8ad5
AH		 1691static void sdhci_enable_sdio_irq_nolock(struct sdhci_host *host, int enable)
1692{
be138554 1693 if (!(host->flags & SDHCI_DEVICE_DEAD)) {
ef104333 1694 if (enable)
b537f94c 1695 host->ier |= SDHCI_INT_CARD_INT;
ef104333 1696 else
b537f94c
RK		 1697 host->ier &= ~SDHCI_INT_CARD_INT;
1698
1699 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
1700 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
ef104333
RK		 1701 mmiowb();
1702 }
66fd8ad5
AH		 1703}
1704
1705static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1706{
1707 struct sdhci_host *host = mmc_priv(mmc);
1708 unsigned long flags;
f75979b7 1709
ef104333
RK		 1710 sdhci_runtime_pm_get(host);
1711
66fd8ad5 1712 spin_lock_irqsave(&host->lock, flags);
ef104333
RK		 1713 if (enable)
1714 host->flags |= SDHCI_SDIO_IRQ_ENABLED;
1715 else
1716 host->flags &= ~SDHCI_SDIO_IRQ_ENABLED;
1717
66fd8ad5 1718 sdhci_enable_sdio_irq_nolock(host, enable);
f75979b7 1719 spin_unlock_irqrestore(&host->lock, flags);
ef104333
RK		 1720
1721 sdhci_runtime_pm_put(host);
f75979b7
PO		 1722}
1723
20b92a30 1724static int sdhci_do_start_signal_voltage_switch(struct sdhci_host *host,
21f5998f 1725 struct mmc_ios *ios)
f2119df6 1726{
3a48edc4 1727 struct mmc_host *mmc = host->mmc;
20b92a30 1728 u16 ctrl;
6231f3de 1729 int ret;
f2119df6 1730
20b92a30
KL		 1731 /*
1732 * Signal Voltage Switching is only applicable for Host Controllers
1733 * v3.00 and above.
1734 */
1735 if (host->version < SDHCI_SPEC_300)
1736 return 0;
6231f3de 1737
f2119df6 1738 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
f2119df6 1739
21f5998f 1740 switch (ios->signal_voltage) {
20b92a30
KL		 1741 case MMC_SIGNAL_VOLTAGE_330:
1742 /* Set 1.8V Signal Enable in the Host Control2 register to 0 */
1743 ctrl &= ~SDHCI_CTRL_VDD_180;
1744 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
f2119df6 1745
3a48edc4
TK		 1746 if (!IS_ERR(mmc->supply.vqmmc)) {
1747 ret = regulator_set_voltage(mmc->supply.vqmmc, 2700000,
1748 3600000);
20b92a30 1749 if (ret) {
6606110d
JP		 1750 pr_warn("%s: Switching to 3.3V signalling voltage failed\n",
1751 mmc_hostname(mmc));
20b92a30
KL		 1752 return -EIO;
1753 }
1754 }
1755 /* Wait for 5ms */
1756 usleep_range(5000, 5500);
f2119df6 1757
20b92a30
KL		 1758 /* 3.3V regulator output should be stable within 5 ms */
1759 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1760 if (!(ctrl & SDHCI_CTRL_VDD_180))
1761 return 0;
6231f3de 1762
6606110d
JP		 1763 pr_warn("%s: 3.3V regulator output did not became stable\n",
1764 mmc_hostname(mmc));
20b92a30
KL		 1765
1766 return -EAGAIN;
1767 case MMC_SIGNAL_VOLTAGE_180:
3a48edc4
TK		 1768 if (!IS_ERR(mmc->supply.vqmmc)) {
1769 ret = regulator_set_voltage(mmc->supply.vqmmc,
20b92a30
KL		 1770 1700000, 1950000);
1771 if (ret) {
6606110d
JP		 1772 pr_warn("%s: Switching to 1.8V signalling voltage failed\n",
1773 mmc_hostname(mmc));
20b92a30
KL		 1774 return -EIO;
1775 }
1776 }
6231f3de 1777
6231f3de
PR		 1778 /*
1779 * Enable 1.8V Signal Enable in the Host Control2
1780 * register
1781 */
20b92a30
KL		 1782 ctrl |= SDHCI_CTRL_VDD_180;
1783 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
6231f3de 1784
9d967a61
VY		 1785 /* Some controller need to do more when switching */
1786 if (host->ops->voltage_switch)
1787 host->ops->voltage_switch(host);
1788
20b92a30
KL		 1789 /* 1.8V regulator output should be stable within 5 ms */
1790 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1791 if (ctrl & SDHCI_CTRL_VDD_180)
1792 return 0;
f2119df6 1793
6606110d
JP		 1794 pr_warn("%s: 1.8V regulator output did not became stable\n",
1795 mmc_hostname(mmc));
f2119df6 1796
20b92a30
KL		 1797 return -EAGAIN;
1798 case MMC_SIGNAL_VOLTAGE_120:
3a48edc4
TK		 1799 if (!IS_ERR(mmc->supply.vqmmc)) {
1800 ret = regulator_set_voltage(mmc->supply.vqmmc, 1100000,
1801 1300000);
20b92a30 1802 if (ret) {
6606110d
JP		 1803 pr_warn("%s: Switching to 1.2V signalling voltage failed\n",
1804 mmc_hostname(mmc));
20b92a30 1805 return -EIO;
f2119df6
AN		 1806 }
1807 }
6231f3de 1808 return 0;
20b92a30 1809 default:
f2119df6
AN		 1810 /* No signal voltage switch required */
1811 return 0;
20b92a30 1812 }
f2119df6
AN		 1813}
1814
66fd8ad5 1815static int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
21f5998f 1816 struct mmc_ios *ios)
66fd8ad5
AH		 1817{
1818 struct sdhci_host *host = mmc_priv(mmc);
1819 int err;
1820
1821 if (host->version < SDHCI_SPEC_300)
1822 return 0;
1823 sdhci_runtime_pm_get(host);
21f5998f 1824 err = sdhci_do_start_signal_voltage_switch(host, ios);
66fd8ad5
AH		 1825 sdhci_runtime_pm_put(host);
1826 return err;
1827}
1828
20b92a30
KL		 1829static int sdhci_card_busy(struct mmc_host *mmc)
1830{
1831 struct sdhci_host *host = mmc_priv(mmc);
1832 u32 present_state;
1833
1834 sdhci_runtime_pm_get(host);
1835 /* Check whether DAT[3:0] is 0000 */
1836 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
1837 sdhci_runtime_pm_put(host);
1838
1839 return !(present_state & SDHCI_DATA_LVL_MASK);
1840}
1841
b5540ce1
AH		 1842static int sdhci_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios)
1843{
1844 struct sdhci_host *host = mmc_priv(mmc);
1845 unsigned long flags;
1846
1847 spin_lock_irqsave(&host->lock, flags);
1848 host->flags |= SDHCI_HS400_TUNING;
1849 spin_unlock_irqrestore(&host->lock, flags);
1850
1851 return 0;
1852}
1853
069c9f14 1854static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode)
b513ea25 1855{
4b6f37d3 1856 struct sdhci_host *host = mmc_priv(mmc);
b513ea25 1857 u16 ctrl;
b513ea25 1858 int tuning_loop_counter = MAX_TUNING_LOOP;
b513ea25 1859 int err = 0;
2b35bd83 1860 unsigned long flags;
38e40bf5 1861 unsigned int tuning_count = 0;
b5540ce1 1862 bool hs400_tuning;
b513ea25 1863
66fd8ad5 1864 sdhci_runtime_pm_get(host);
2b35bd83 1865 spin_lock_irqsave(&host->lock, flags);
b513ea25 1866
b5540ce1
AH		 1867 hs400_tuning = host->flags & SDHCI_HS400_TUNING;
1868 host->flags &= ~SDHCI_HS400_TUNING;
1869
38e40bf5
AH		 1870 if (host->tuning_mode == SDHCI_TUNING_MODE_1)
1871 tuning_count = host->tuning_count;
1872
b513ea25 1873 /*
9faac7b9
WY		 1874 * The Host Controller needs tuning in case of SDR104 and DDR50
1875 * mode, and for SDR50 mode when Use Tuning for SDR50 is set in
1876 * the Capabilities register.
069c9f14
G		 1877 * If the Host Controller supports the HS200 mode then the
1878 * tuning function has to be executed.
b513ea25 1879 */
4b6f37d3 1880 switch (host->timing) {
b5540ce1 1881 /* HS400 tuning is done in HS200 mode */
e9fb05d5 1882 case MMC_TIMING_MMC_HS400:
b5540ce1
AH		 1883 err = -EINVAL;
1884 goto out_unlock;
1885
4b6f37d3 1886 case MMC_TIMING_MMC_HS200:
b5540ce1
AH		 1887 /*
1888 * Periodic re-tuning for HS400 is not expected to be needed, so
1889 * disable it here.
1890 */
1891 if (hs400_tuning)
1892 tuning_count = 0;
1893 break;
1894
4b6f37d3 1895 case MMC_TIMING_UHS_SDR104:
9faac7b9 1896 case MMC_TIMING_UHS_DDR50:
4b6f37d3
RK		 1897 break;
1898
1899 case MMC_TIMING_UHS_SDR50:
1900 if (host->flags & SDHCI_SDR50_NEEDS_TUNING ||
1901 host->flags & SDHCI_SDR104_NEEDS_TUNING)
1902 break;
1903 /* FALLTHROUGH */
1904
1905 default:
d519c863 1906 goto out_unlock;
b513ea25
AN		 1907 }
1908
45251812 1909 if (host->ops->platform_execute_tuning) {
2b35bd83 1910 spin_unlock_irqrestore(&host->lock, flags);
45251812
DA		 1911 err = host->ops->platform_execute_tuning(host, opcode);
1912 sdhci_runtime_pm_put(host);
1913 return err;
1914 }
1915
4b6f37d3
RK		 1916 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1917 ctrl |= SDHCI_CTRL_EXEC_TUNING;
67d0d04a
VY		 1918 if (host->quirks2 & SDHCI_QUIRK2_TUNING_WORK_AROUND)
1919 ctrl |= SDHCI_CTRL_TUNED_CLK;
b513ea25
AN		 1920 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1921
1922 /*
1923 * As per the Host Controller spec v3.00, tuning command
1924 * generates Buffer Read Ready interrupt, so enable that.
1925 *
1926 * Note: The spec clearly says that when tuning sequence
1927 * is being performed, the controller does not generate
1928 * interrupts other than Buffer Read Ready interrupt. But
1929 * to make sure we don't hit a controller bug, we _only_
1930 * enable Buffer Read Ready interrupt here.
1931 */
b537f94c
RK		 1932 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE);
1933 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE);
b513ea25
AN		 1934
1935 /*
1936 * Issue CMD19 repeatedly till Execute Tuning is set to 0 or the number
1937 * of loops reaches 40 times or a timeout of 150ms occurs.
1938 */
b513ea25
AN		 1939 do {
1940 struct mmc_command cmd = {0};
66fd8ad5 1941 struct mmc_request mrq = {NULL};
b513ea25 1942
069c9f14 1943 cmd.opcode = opcode;
b513ea25
AN		 1944 cmd.arg = 0;
1945 cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
1946 cmd.retries = 0;
1947 cmd.data = NULL;
1948 cmd.error = 0;
1949
7ce45e95
AC		 1950 if (tuning_loop_counter-- == 0)
1951 break;
1952
b513ea25
AN		 1953 mrq.cmd = &cmd;
1954 host->mrq = &mrq;
1955
1956 /*
1957 * In response to CMD19, the card sends 64 bytes of tuning
1958 * block to the Host Controller. So we set the block size
1959 * to 64 here.
1960 */
069c9f14
G		 1961 if (cmd.opcode == MMC_SEND_TUNING_BLOCK_HS200) {
1962 if (mmc->ios.bus_width == MMC_BUS_WIDTH_8)
1963 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 128),
1964 SDHCI_BLOCK_SIZE);
1965 else if (mmc->ios.bus_width == MMC_BUS_WIDTH_4)
1966 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
1967 SDHCI_BLOCK_SIZE);
1968 } else {
1969 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
1970 SDHCI_BLOCK_SIZE);
1971 }
b513ea25
AN		 1972
1973 /*
1974 * The tuning block is sent by the card to the host controller.
1975 * So we set the TRNS_READ bit in the Transfer Mode register.
1976 * This also takes care of setting DMA Enable and Multi Block
1977 * Select in the same register to 0.
1978 */
1979 sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
1980
1981 sdhci_send_command(host, &cmd);
1982
1983 host->cmd = NULL;
1984 host->mrq = NULL;
1985
2b35bd83 1986 spin_unlock_irqrestore(&host->lock, flags);
b513ea25
AN		 1987 /* Wait for Buffer Read Ready interrupt */
1988 wait_event_interruptible_timeout(host->buf_ready_int,
1989 (host->tuning_done == 1),
1990 msecs_to_jiffies(50));
2b35bd83 1991 spin_lock_irqsave(&host->lock, flags);
b513ea25
AN		 1992
1993 if (!host->tuning_done) {
2e4456f0 1994 pr_info(DRIVER_NAME ": Timeout waiting for Buffer Read Ready interrupt during tuning procedure, falling back to fixed sampling clock\n");
b513ea25
AN		 1995 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1996 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
1997 ctrl &= ~SDHCI_CTRL_EXEC_TUNING;
1998 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1999
2000 err = -EIO;
2001 goto out;
2002 }
2003
2004 host->tuning_done = 0;
2005
2006 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
197160d5
NS		 2007
2008 /* eMMC spec does not require a delay between tuning cycles */
2009 if (opcode == MMC_SEND_TUNING_BLOCK)
2010 mdelay(1);
b513ea25
AN		 2011 } while (ctrl & SDHCI_CTRL_EXEC_TUNING);
2012
2013 /*
2014 * The Host Driver has exhausted the maximum number of loops allowed,
2015 * so use fixed sampling frequency.
2016 */
7ce45e95 2017 if (tuning_loop_counter < 0) {
b513ea25
AN		 2018 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
2019 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
7ce45e95
AC		 2020 }
2021 if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) {
2e4456f0 2022 pr_info(DRIVER_NAME ": Tuning procedure failed, falling back to fixed sampling clock\n");
114f2bf6 2023 err = -EIO;
b513ea25
AN		 2024 }
2025
2026out:
38e40bf5 2027 if (tuning_count) {
66c39dfc
AH		 2028 /*
2029 * In case tuning fails, host controllers which support
2030 * re-tuning can try tuning again at a later time, when the
2031 * re-tuning timer expires. So for these controllers, we
2032 * return 0. Since there might be other controllers who do not
2033 * have this capability, we return error for them.
2034 */
2035 err = 0;
cf2b5eea
AN		 2036 }
2037
66c39dfc 2038 host->mmc->retune_period = err ? 0 : tuning_count;
cf2b5eea 2039
b537f94c
RK		 2040 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2041 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
d519c863 2042out_unlock:
2b35bd83 2043 spin_unlock_irqrestore(&host->lock, flags);
66fd8ad5 2044 sdhci_runtime_pm_put(host);
b513ea25
AN		 2045
2046 return err;
2047}
2048
cb849648
AH		 2049static int sdhci_select_drive_strength(struct mmc_card *card,
2050 unsigned int max_dtr, int host_drv,
2051 int card_drv, int *drv_type)
2052{
2053 struct sdhci_host *host = mmc_priv(card->host);
2054
2055 if (!host->ops->select_drive_strength)
2056 return 0;
2057
2058 return host->ops->select_drive_strength(host, card, max_dtr, host_drv,
2059 card_drv, drv_type);
2060}
52983382
KL		 2061
2062static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable)
4d55c5a1 2063{
4d55c5a1
AN		 2064 /* Host Controller v3.00 defines preset value registers */
2065 if (host->version < SDHCI_SPEC_300)
2066 return;
2067
4d55c5a1
AN		 2068 /*
2069 * We only enable or disable Preset Value if they are not already
2070 * enabled or disabled respectively. Otherwise, we bail out.
2071 */
da91a8f9
RK		 2072 if (host->preset_enabled != enable) {
2073 u16 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2074
2075 if (enable)
2076 ctrl |= SDHCI_CTRL_PRESET_VAL_ENABLE;
2077 else
2078 ctrl &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
2079
4d55c5a1 2080 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
da91a8f9
RK		 2081
2082 if (enable)
2083 host->flags |= SDHCI_PV_ENABLED;
2084 else
2085 host->flags &= ~SDHCI_PV_ENABLED;
2086
2087 host->preset_enabled = enable;
4d55c5a1 2088 }
66fd8ad5
AH		 2089}
2090
348487cb
HC		 2091static void sdhci_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
2092 int err)
2093{
2094 struct sdhci_host *host = mmc_priv(mmc);
2095 struct mmc_data *data = mrq->data;
2096
771a3dc2
RK		 2097 if (data->host_cookie == COOKIE_GIVEN ||
2098 data->host_cookie == COOKIE_MAPPED)
2099 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
2100 data->flags & MMC_DATA_WRITE ?
2101 DMA_TO_DEVICE : DMA_FROM_DEVICE);
2102
2103 data->host_cookie = COOKIE_UNMAPPED;
348487cb
HC		 2104}
2105
348487cb
HC		 2106static void sdhci_pre_req(struct mmc_host *mmc, struct mmc_request *mrq,
2107 bool is_first_req)
2108{
2109 struct sdhci_host *host = mmc_priv(mmc);
2110
d31911b9 2111 mrq->data->host_cookie = COOKIE_UNMAPPED;
348487cb
HC		 2112
2113 if (host->flags & SDHCI_REQ_USE_DMA)
d31911b9 2114 sdhci_pre_dma_transfer(host, mrq->data);
348487cb
HC		 2115}
2116
71e69211 2117static void sdhci_card_event(struct mmc_host *mmc)
d129bceb 2118{
71e69211 2119 struct sdhci_host *host = mmc_priv(mmc);
d129bceb 2120 unsigned long flags;
2836766a 2121 int present;
d129bceb 2122
722e1280
CD		 2123 /* First check if client has provided their own card event */
2124 if (host->ops->card_event)
2125 host->ops->card_event(host);
2126
2836766a
KK		 2127 present = sdhci_do_get_cd(host);
2128
d129bceb
PO		 2129 spin_lock_irqsave(&host->lock, flags);
2130
66fd8ad5 2131 /* Check host->mrq first in case we are runtime suspended */
2836766a 2132 if (host->mrq && !present) {
a3c76eb9 2133 pr_err("%s: Card removed during transfer!\n",
66fd8ad5 2134 mmc_hostname(host->mmc));
a3c76eb9 2135 pr_err("%s: Resetting controller.\n",
66fd8ad5 2136 mmc_hostname(host->mmc));
d129bceb 2137
03231f9b
RK		 2138 sdhci_do_reset(host, SDHCI_RESET_CMD);
2139 sdhci_do_reset(host, SDHCI_RESET_DATA);
d129bceb 2140
66fd8ad5
AH		 2141 host->mrq->cmd->error = -ENOMEDIUM;
2142 tasklet_schedule(&host->finish_tasklet);
d129bceb
PO		 2143 }
2144
2145 spin_unlock_irqrestore(&host->lock, flags);
71e69211
GL		 2146}
2147
2148static const struct mmc_host_ops sdhci_ops = {
2149 .request = sdhci_request,
348487cb
HC		 2150 .post_req = sdhci_post_req,
2151 .pre_req = sdhci_pre_req,
71e69211 2152 .set_ios = sdhci_set_ios,
94144a46 2153 .get_cd = sdhci_get_cd,
71e69211
GL		 2154 .get_ro = sdhci_get_ro,
2155 .hw_reset = sdhci_hw_reset,
2156 .enable_sdio_irq = sdhci_enable_sdio_irq,
2157 .start_signal_voltage_switch = sdhci_start_signal_voltage_switch,
b5540ce1 2158 .prepare_hs400_tuning = sdhci_prepare_hs400_tuning,
71e69211 2159 .execute_tuning = sdhci_execute_tuning,
cb849648 2160 .select_drive_strength = sdhci_select_drive_strength,
71e69211 2161 .card_event = sdhci_card_event,
20b92a30 2162 .card_busy = sdhci_card_busy,
71e69211
GL		 2163};
2164
2165/*****************************************************************************\
2166 * *
2167 * Tasklets *
2168 * *
2169\*****************************************************************************/
2170
d129bceb
PO		 2171static void sdhci_tasklet_finish(unsigned long param)
2172{
2173 struct sdhci_host *host;
2174 unsigned long flags;
2175 struct mmc_request *mrq;
2176
2177 host = (struct sdhci_host*)param;
2178
66fd8ad5
AH		 2179 spin_lock_irqsave(&host->lock, flags);
2180
0c9c99a7
CB		 2181 /*
2182 * If this tasklet gets rescheduled while running, it will
2183 * be run again afterwards but without any active request.
2184 */
66fd8ad5
AH		 2185 if (!host->mrq) {
2186 spin_unlock_irqrestore(&host->lock, flags);
0c9c99a7 2187 return;
66fd8ad5 2188 }
d129bceb
PO		 2189
2190 del_timer(&host->timer);
2191
2192 mrq = host->mrq;
2193
054cedff
RK		 2194 /*
2195 * Always unmap the data buffers if they were mapped by
2196 * sdhci_prepare_data() whenever we finish with a request.
2197 * This avoids leaking DMA mappings on error.
2198 */
2199 if (host->flags & SDHCI_REQ_USE_DMA) {
2200 struct mmc_data *data = mrq->data;
2201
2202 if (data && data->host_cookie == COOKIE_MAPPED) {
2203 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
2204 (data->flags & MMC_DATA_READ) ?
2205 DMA_FROM_DEVICE : DMA_TO_DEVICE);
2206 data->host_cookie = COOKIE_UNMAPPED;
2207 }
2208 }
2209
d129bceb
PO		 2210 /*
2211 * The controller needs a reset of internal state machines
2212 * upon error conditions.
2213 */
1e72859e 2214 if (!(host->flags & SDHCI_DEVICE_DEAD) &&
b7b4d342 2215 ((mrq->cmd && mrq->cmd->error) ||
fce9d33f
AG		 2216 (mrq->sbc && mrq->sbc->error) ||
2217 (mrq->data && ((mrq->data->error && !mrq->data->stop) ||
2218 (mrq->data->stop && mrq->data->stop->error))) ||
2219 (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) {
645289dc
PO		 2220
2221 /* Some controllers need this kick or reset won't work here */
8213af3b 2222 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)
645289dc 2223 /* This is to force an update */
1771059c 2224 host->ops->set_clock(host, host->clock);
645289dc
PO		 2225
2226 /* Spec says we should do both at the same time, but Ricoh
2227 controllers do not like that. */
03231f9b
RK		 2228 sdhci_do_reset(host, SDHCI_RESET_CMD);
2229 sdhci_do_reset(host, SDHCI_RESET_DATA);
d129bceb
PO		 2230 }
2231
2232 host->mrq = NULL;
2233 host->cmd = NULL;
2234 host->data = NULL;
2235
f9134319 2236#ifndef SDHCI_USE_LEDS_CLASS
d129bceb 2237 sdhci_deactivate_led(host);
2f730fec 2238#endif
d129bceb 2239
5f25a66f 2240 mmiowb();
d129bceb
PO		 2241 spin_unlock_irqrestore(&host->lock, flags);
2242
2243 mmc_request_done(host->mmc, mrq);
66fd8ad5 2244 sdhci_runtime_pm_put(host);
d129bceb
PO		 2245}
2246
2247static void sdhci_timeout_timer(unsigned long data)
2248{
2249 struct sdhci_host *host;
2250 unsigned long flags;
2251
2252 host = (struct sdhci_host*)data;
2253
2254 spin_lock_irqsave(&host->lock, flags);
2255
2256 if (host->mrq) {
2e4456f0
MV		 2257 pr_err("%s: Timeout waiting for hardware interrupt.\n",
2258 mmc_hostname(host->mmc));
d129bceb
PO		 2259 sdhci_dumpregs(host);
2260
2261 if (host->data) {
17b0429d 2262 host->data->error = -ETIMEDOUT;
d129bceb
PO		 2263 sdhci_finish_data(host);
2264 } else {
2265 if (host->cmd)
17b0429d 2266 host->cmd->error = -ETIMEDOUT;
d129bceb 2267 else
17b0429d 2268 host->mrq->cmd->error = -ETIMEDOUT;
d129bceb
PO		 2269
2270 tasklet_schedule(&host->finish_tasklet);
2271 }
2272 }
2273
5f25a66f 2274 mmiowb();
d129bceb
PO		 2275 spin_unlock_irqrestore(&host->lock, flags);
2276}
2277
2278/*****************************************************************************\
2279 * *
2280 * Interrupt handling *
2281 * *
2282\*****************************************************************************/
2283
61541397 2284static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask, u32 *mask)
d129bceb
PO		 2285{
2286 BUG_ON(intmask == 0);
2287
2288 if (!host->cmd) {
2e4456f0
MV		 2289 pr_err("%s: Got command interrupt 0x%08x even though no command operation was in progress.\n",
2290 mmc_hostname(host->mmc), (unsigned)intmask);
d129bceb
PO		 2291 sdhci_dumpregs(host);
2292 return;
2293 }
2294
ec014cba
RK		 2295 if (intmask & (SDHCI_INT_TIMEOUT | SDHCI_INT_CRC |
2296 SDHCI_INT_END_BIT | SDHCI_INT_INDEX)) {
2297 if (intmask & SDHCI_INT_TIMEOUT)
2298 host->cmd->error = -ETIMEDOUT;
2299 else
2300 host->cmd->error = -EILSEQ;
43b58b36 2301
71fcbda0
RK		 2302 /*
2303 * If this command initiates a data phase and a response
2304 * CRC error is signalled, the card can start transferring
2305 * data - the card may have received the command without
2306 * error. We must not terminate the mmc_request early.
2307 *
2308 * If the card did not receive the command or returned an
2309 * error which prevented it sending data, the data phase
2310 * will time out.
2311 */
2312 if (host->cmd->data &&
2313 (intmask & (SDHCI_INT_CRC | SDHCI_INT_TIMEOUT)) ==
2314 SDHCI_INT_CRC) {
2315 host->cmd = NULL;
2316 return;
2317 }
2318
d129bceb 2319 tasklet_schedule(&host->finish_tasklet);
e809517f
PO		 2320 return;
2321 }
2322
2323 /*
2324 * The host can send and interrupt when the busy state has
2325 * ended, allowing us to wait without wasting CPU cycles.
2326 * Unfortunately this is overloaded on the "data complete"
2327 * interrupt, so we need to take some care when handling
2328 * it.
2329 *
2330 * Note: The 1.0 specification is a bit ambiguous about this
2331 * feature so there might be some problems with older
2332 * controllers.
2333 */
2334 if (host->cmd->flags & MMC_RSP_BUSY) {
2335 if (host->cmd->data)
2e4456f0 2336 DBG("Cannot wait for busy signal when also doing a data transfer");
e99783a4
CM		 2337 else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ)
2338 && !host->busy_handle) {
2339 /* Mark that command complete before busy is ended */
2340 host->busy_handle = 1;
e809517f 2341 return;
e99783a4 2342 }
f945405c
BD		 2343
2344 /* The controller does not support the end-of-busy IRQ,
2345 * fall through and take the SDHCI_INT_RESPONSE */
61541397
AH		 2346 } else if ((host->quirks2 & SDHCI_QUIRK2_STOP_WITH_TC) &&
2347 host->cmd->opcode == MMC_STOP_TRANSMISSION && !host->data) {
2348 *mask &= ~SDHCI_INT_DATA_END;
e809517f
PO		 2349 }
2350
2351 if (intmask & SDHCI_INT_RESPONSE)
43b58b36 2352 sdhci_finish_command(host);
d129bceb
PO		 2353}
2354
0957c333 2355#ifdef CONFIG_MMC_DEBUG
08621b18 2356static void sdhci_adma_show_error(struct sdhci_host *host)
6882a8c0
BD		 2357{
2358 const char *name = mmc_hostname(host->mmc);
1c3d5f6d 2359 void *desc = host->adma_table;
6882a8c0
BD		 2360
2361 sdhci_dumpregs(host);
2362
2363 while (true) {
e57a5f61
AH		 2364 struct sdhci_adma2_64_desc *dma_desc = desc;
2365
2366 if (host->flags & SDHCI_USE_64_BIT_DMA)
2367 DBG("%s: %p: DMA 0x%08x%08x, LEN 0x%04x, Attr=0x%02x\n",
2368 name, desc, le32_to_cpu(dma_desc->addr_hi),
2369 le32_to_cpu(dma_desc->addr_lo),
2370 le16_to_cpu(dma_desc->len),
2371 le16_to_cpu(dma_desc->cmd));
2372 else
2373 DBG("%s: %p: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n",
2374 name, desc, le32_to_cpu(dma_desc->addr_lo),
2375 le16_to_cpu(dma_desc->len),
2376 le16_to_cpu(dma_desc->cmd));
6882a8c0 2377
76fe379a 2378 desc += host->desc_sz;
6882a8c0 2379
0545230f 2380 if (dma_desc->cmd & cpu_to_le16(ADMA2_END))
6882a8c0
BD		 2381 break;
2382 }
2383}
2384#else
08621b18 2385static void sdhci_adma_show_error(struct sdhci_host *host) { }
6882a8c0
BD		 2386#endif
2387
d129bceb
PO		 2388static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
2389{
069c9f14 2390 u32 command;
d129bceb
PO		 2391 BUG_ON(intmask == 0);
2392
b513ea25
AN		 2393 /* CMD19 generates _only_ Buffer Read Ready interrupt */
2394 if (intmask & SDHCI_INT_DATA_AVAIL) {
069c9f14
G		 2395 command = SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND));
2396 if (command == MMC_SEND_TUNING_BLOCK ||
2397 command == MMC_SEND_TUNING_BLOCK_HS200) {
b513ea25
AN		 2398 host->tuning_done = 1;
2399 wake_up(&host->buf_ready_int);
2400 return;
2401 }
2402 }
2403
d129bceb
PO		 2404 if (!host->data) {
2405 /*
e809517f
PO		 2406 * The "data complete" interrupt is also used to
2407 * indicate that a busy state has ended. See comment
2408 * above in sdhci_cmd_irq().
d129bceb 2409 */
e809517f 2410 if (host->cmd && (host->cmd->flags & MMC_RSP_BUSY)) {
c5abd5e8
MC		 2411 if (intmask & SDHCI_INT_DATA_TIMEOUT) {
2412 host->cmd->error = -ETIMEDOUT;
2413 tasklet_schedule(&host->finish_tasklet);
2414 return;
2415 }
e809517f 2416 if (intmask & SDHCI_INT_DATA_END) {
e99783a4
CM		 2417 /*
2418 * Some cards handle busy-end interrupt
2419 * before the command completed, so make
2420 * sure we do things in the proper order.
2421 */
2422 if (host->busy_handle)
2423 sdhci_finish_command(host);
2424 else
2425 host->busy_handle = 1;
e809517f
PO		 2426 return;
2427 }
2428 }
d129bceb 2429
2e4456f0
MV		 2430 pr_err("%s: Got data interrupt 0x%08x even though no data operation was in progress.\n",
2431 mmc_hostname(host->mmc), (unsigned)intmask);
d129bceb
PO		 2432 sdhci_dumpregs(host);
2433
2434 return;
2435 }
2436
2437 if (intmask & SDHCI_INT_DATA_TIMEOUT)
17b0429d 2438 host->data->error = -ETIMEDOUT;
22113efd
AL		 2439 else if (intmask & SDHCI_INT_DATA_END_BIT)
2440 host->data->error = -EILSEQ;
2441 else if ((intmask & SDHCI_INT_DATA_CRC) &&
2442 SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))
2443 != MMC_BUS_TEST_R)
17b0429d 2444 host->data->error = -EILSEQ;
6882a8c0 2445 else if (intmask & SDHCI_INT_ADMA_ERROR) {
a3c76eb9 2446 pr_err("%s: ADMA error\n", mmc_hostname(host->mmc));
08621b18 2447 sdhci_adma_show_error(host);
2134a922 2448 host->data->error = -EIO;
a4071fbb
HZ		 2449 if (host->ops->adma_workaround)
2450 host->ops->adma_workaround(host, intmask);
6882a8c0 2451 }
d129bceb 2452
17b0429d 2453 if (host->data->error)
d129bceb
PO		 2454 sdhci_finish_data(host);
2455 else {
a406f5a3 2456 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
d129bceb
PO		 2457 sdhci_transfer_pio(host);
2458
6ba736a1
PO		 2459 /*
2460 * We currently don't do anything fancy with DMA
2461 * boundaries, but as we can't disable the feature
2462 * we need to at least restart the transfer.
f6a03cbf
MV		 2463 *
2464 * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS)
2465 * should return a valid address to continue from, but as
2466 * some controllers are faulty, don't trust them.
6ba736a1 2467 */
f6a03cbf
MV		 2468 if (intmask & SDHCI_INT_DMA_END) {
2469 u32 dmastart, dmanow;
2470 dmastart = sg_dma_address(host->data->sg);
2471 dmanow = dmastart + host->data->bytes_xfered;
2472 /*
2473 * Force update to the next DMA block boundary.
2474 */
2475 dmanow = (dmanow &
2476 ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) +
2477 SDHCI_DEFAULT_BOUNDARY_SIZE;
2478 host->data->bytes_xfered = dmanow - dmastart;
2479 DBG("%s: DMA base 0x%08x, transferred 0x%06x bytes,"
2480 " next 0x%08x\n",
2481 mmc_hostname(host->mmc), dmastart,
2482 host->data->bytes_xfered, dmanow);
2483 sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS);
2484 }
6ba736a1 2485
e538fbe8
PO		 2486 if (intmask & SDHCI_INT_DATA_END) {
2487 if (host->cmd) {
2488 /*
2489 * Data managed to finish before the
2490 * command completed. Make sure we do
2491 * things in the proper order.
2492 */
2493 host->data_early = 1;
2494 } else {
2495 sdhci_finish_data(host);
2496 }
2497 }
d129bceb
PO		 2498 }
2499}
2500
7d12e780 2501static irqreturn_t sdhci_irq(int irq, void *dev_id)
d129bceb 2502{
781e989c 2503 irqreturn_t result = IRQ_NONE;
66fd8ad5 2504 struct sdhci_host *host = dev_id;
41005003 2505 u32 intmask, mask, unexpected = 0;
781e989c 2506 int max_loops = 16;
d129bceb
PO		 2507
2508 spin_lock(&host->lock);
2509
be138554 2510 if (host->runtime_suspended && !sdhci_sdio_irq_enabled(host)) {
66fd8ad5 2511 spin_unlock(&host->lock);
655bca76 2512 return IRQ_NONE;
66fd8ad5
AH		 2513 }
2514
4e4141a5 2515 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
62df67a5 2516 if (!intmask || intmask == 0xffffffff) {
d129bceb
PO		 2517 result = IRQ_NONE;
2518 goto out;
2519 }
2520
41005003
RK		 2521 do {
2522 /* Clear selected interrupts. */
2523 mask = intmask & (SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
2524 SDHCI_INT_BUS_POWER);
2525 sdhci_writel(host, mask, SDHCI_INT_STATUS);
d129bceb 2526
41005003
RK		 2527 DBG("*** %s got interrupt: 0x%08x\n",
2528 mmc_hostname(host->mmc), intmask);
d129bceb 2529
41005003
RK		 2530 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
2531 u32 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
2532 SDHCI_CARD_PRESENT;
d129bceb 2533
41005003
RK		 2534 /*
2535 * There is a observation on i.mx esdhc. INSERT
2536 * bit will be immediately set again when it gets
2537 * cleared, if a card is inserted. We have to mask
2538 * the irq to prevent interrupt storm which will
2539 * freeze the system. And the REMOVE gets the
2540 * same situation.
2541 *
2542 * More testing are needed here to ensure it works
2543 * for other platforms though.
2544 */
b537f94c
RK		 2545 host->ier &= ~(SDHCI_INT_CARD_INSERT |
2546 SDHCI_INT_CARD_REMOVE);
2547 host->ier |= present ? SDHCI_INT_CARD_REMOVE :
2548 SDHCI_INT_CARD_INSERT;
2549 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2550 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
41005003
RK		 2551
2552 sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT |
2553 SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS);
3560db8e
RK		 2554
2555 host->thread_isr |= intmask & (SDHCI_INT_CARD_INSERT |
2556 SDHCI_INT_CARD_REMOVE);
2557 result = IRQ_WAKE_THREAD;
41005003 2558 }
d129bceb 2559
41005003 2560 if (intmask & SDHCI_INT_CMD_MASK)
61541397
AH		 2561 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK,
2562 &intmask);
964f9ce2 2563
41005003
RK		 2564 if (intmask & SDHCI_INT_DATA_MASK)
2565 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
d129bceb 2566
41005003
RK		 2567 if (intmask & SDHCI_INT_BUS_POWER)
2568 pr_err("%s: Card is consuming too much power!\n",
2569 mmc_hostname(host->mmc));
3192a28f 2570
781e989c
RK		 2571 if (intmask & SDHCI_INT_CARD_INT) {
2572 sdhci_enable_sdio_irq_nolock(host, false);
2573 host->thread_isr |= SDHCI_INT_CARD_INT;
2574 result = IRQ_WAKE_THREAD;
2575 }
f75979b7 2576
41005003
RK		 2577 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE |
2578 SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
2579 SDHCI_INT_ERROR | SDHCI_INT_BUS_POWER |
2580 SDHCI_INT_CARD_INT);
f75979b7 2581
41005003
RK		 2582 if (intmask) {
2583 unexpected |= intmask;
2584 sdhci_writel(host, intmask, SDHCI_INT_STATUS);
2585 }
d129bceb 2586
781e989c
RK		 2587 if (result == IRQ_NONE)
2588 result = IRQ_HANDLED;
d129bceb 2589
41005003 2590 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
41005003 2591 } while (intmask && --max_loops);
d129bceb
PO		 2592out:
2593 spin_unlock(&host->lock);
2594
6379b237
AS		 2595 if (unexpected) {
2596 pr_err("%s: Unexpected interrupt 0x%08x.\n",
2597 mmc_hostname(host->mmc), unexpected);
2598 sdhci_dumpregs(host);
2599 }
f75979b7 2600
d129bceb
PO		 2601 return result;
2602}
2603
781e989c
RK		 2604static irqreturn_t sdhci_thread_irq(int irq, void *dev_id)
2605{
2606 struct sdhci_host *host = dev_id;
2607 unsigned long flags;
2608 u32 isr;
2609
2610 spin_lock_irqsave(&host->lock, flags);
2611 isr = host->thread_isr;
2612 host->thread_isr = 0;
2613 spin_unlock_irqrestore(&host->lock, flags);
2614
3560db8e
RK		 2615 if (isr & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
2616 sdhci_card_event(host->mmc);
2617 mmc_detect_change(host->mmc, msecs_to_jiffies(200));
2618 }
2619
781e989c
RK		 2620 if (isr & SDHCI_INT_CARD_INT) {
2621 sdio_run_irqs(host->mmc);
2622
2623 spin_lock_irqsave(&host->lock, flags);
2624 if (host->flags & SDHCI_SDIO_IRQ_ENABLED)
2625 sdhci_enable_sdio_irq_nolock(host, true);
2626 spin_unlock_irqrestore(&host->lock, flags);
2627 }
2628
2629 return isr ? IRQ_HANDLED : IRQ_NONE;
2630}
2631
d129bceb
PO		 2632/*****************************************************************************\
2633 * *
2634 * Suspend/resume *
2635 * *
2636\*****************************************************************************/
2637
2638#ifdef CONFIG_PM
ad080d79
KL		 2639void sdhci_enable_irq_wakeups(struct sdhci_host *host)
2640{
2641 u8 val;
2642 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
2643 | SDHCI_WAKE_ON_INT;
2644
2645 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2646 val |= mask ;
2647 /* Avoid fake wake up */
2648 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
2649 val &= ~(SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE);
2650 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2651}
2652EXPORT_SYMBOL_GPL(sdhci_enable_irq_wakeups);
2653
0b10f478 2654static void sdhci_disable_irq_wakeups(struct sdhci_host *host)
ad080d79
KL		 2655{
2656 u8 val;
2657 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
2658 | SDHCI_WAKE_ON_INT;
2659
2660 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2661 val &= ~mask;
2662 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2663}
d129bceb 2664
29495aa0 2665int sdhci_suspend_host(struct sdhci_host *host)
d129bceb 2666{
7260cf5e
AV		 2667 sdhci_disable_card_detection(host);
2668
66c39dfc
AH		 2669 mmc_retune_timer_stop(host->mmc);
2670 mmc_retune_needed(host->mmc);
cf2b5eea 2671
ad080d79 2672 if (!device_may_wakeup(mmc_dev(host->mmc))) {
b537f94c
RK		 2673 host->ier = 0;
2674 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
2675 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
ad080d79
KL		 2676 free_irq(host->irq, host);
2677 } else {
2678 sdhci_enable_irq_wakeups(host);
2679 enable_irq_wake(host->irq);
2680 }
4ee14ec6 2681 return 0;
d129bceb
PO		 2682}
2683
b8c86fc5 2684EXPORT_SYMBOL_GPL(sdhci_suspend_host);
d129bceb 2685
b8c86fc5
PO		 2686int sdhci_resume_host(struct sdhci_host *host)
2687{
4ee14ec6 2688 int ret = 0;
d129bceb 2689
a13abc7b 2690 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
b8c86fc5
PO		 2691 if (host->ops->enable_dma)
2692 host->ops->enable_dma(host);
2693 }
d129bceb 2694
6308d290
AH		 2695 if ((host->mmc->pm_flags & MMC_PM_KEEP_POWER) &&
2696 (host->quirks2 & SDHCI_QUIRK2_HOST_OFF_CARD_ON)) {
2697 /* Card keeps power but host controller does not */
2698 sdhci_init(host, 0);
2699 host->pwr = 0;
2700 host->clock = 0;
2701 sdhci_do_set_ios(host, &host->mmc->ios);
2702 } else {
2703 sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER));
2704 mmiowb();
2705 }
b8c86fc5 2706
14a7b416
HC		 2707 if (!device_may_wakeup(mmc_dev(host->mmc))) {
2708 ret = request_threaded_irq(host->irq, sdhci_irq,
2709 sdhci_thread_irq, IRQF_SHARED,
2710 mmc_hostname(host->mmc), host);
2711 if (ret)
2712 return ret;
2713 } else {
2714 sdhci_disable_irq_wakeups(host);
2715 disable_irq_wake(host->irq);
2716 }
2717
7260cf5e
AV		 2718 sdhci_enable_card_detection(host);
2719
2f4cbb3d 2720 return ret;
d129bceb
PO		 2721}
2722
b8c86fc5 2723EXPORT_SYMBOL_GPL(sdhci_resume_host);
66fd8ad5
AH		 2724
2725static int sdhci_runtime_pm_get(struct sdhci_host *host)
2726{
2727 return pm_runtime_get_sync(host->mmc->parent);
2728}
2729
2730static int sdhci_runtime_pm_put(struct sdhci_host *host)
2731{
2732 pm_runtime_mark_last_busy(host->mmc->parent);
2733 return pm_runtime_put_autosuspend(host->mmc->parent);
2734}
2735
f0710a55
AH		 2736static void sdhci_runtime_pm_bus_on(struct sdhci_host *host)
2737{
5c671c41 2738 if (host->bus_on)
f0710a55
AH		 2739 return;
2740 host->bus_on = true;
2741 pm_runtime_get_noresume(host->mmc->parent);
2742}
2743
2744static void sdhci_runtime_pm_bus_off(struct sdhci_host *host)
2745{
5c671c41 2746 if (!host->bus_on)
f0710a55
AH		 2747 return;
2748 host->bus_on = false;
2749 pm_runtime_put_noidle(host->mmc->parent);
2750}
2751
66fd8ad5
AH		 2752int sdhci_runtime_suspend_host(struct sdhci_host *host)
2753{
2754 unsigned long flags;
66fd8ad5 2755
66c39dfc
AH		 2756 mmc_retune_timer_stop(host->mmc);
2757 mmc_retune_needed(host->mmc);
66fd8ad5
AH		 2758
2759 spin_lock_irqsave(&host->lock, flags);
b537f94c
RK		 2760 host->ier &= SDHCI_INT_CARD_INT;
2761 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2762 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
66fd8ad5
AH		 2763 spin_unlock_irqrestore(&host->lock, flags);
2764
781e989c 2765 synchronize_hardirq(host->irq);
66fd8ad5
AH		 2766
2767 spin_lock_irqsave(&host->lock, flags);
2768 host->runtime_suspended = true;
2769 spin_unlock_irqrestore(&host->lock, flags);
2770
8a125bad 2771 return 0;
66fd8ad5
AH		 2772}
2773EXPORT_SYMBOL_GPL(sdhci_runtime_suspend_host);
2774
2775int sdhci_runtime_resume_host(struct sdhci_host *host)
2776{
2777 unsigned long flags;
8a125bad 2778 int host_flags = host->flags;
66fd8ad5
AH		 2779
2780 if (host_flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2781 if (host->ops->enable_dma)
2782 host->ops->enable_dma(host);
2783 }
2784
2785 sdhci_init(host, 0);
2786
2787 /* Force clock and power re-program */
2788 host->pwr = 0;
2789 host->clock = 0;
3396e736 2790 sdhci_do_start_signal_voltage_switch(host, &host->mmc->ios);
66fd8ad5
AH		 2791 sdhci_do_set_ios(host, &host->mmc->ios);
2792
52983382
KL		 2793 if ((host_flags & SDHCI_PV_ENABLED) &&
2794 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN)) {
2795 spin_lock_irqsave(&host->lock, flags);
2796 sdhci_enable_preset_value(host, true);
2797 spin_unlock_irqrestore(&host->lock, flags);
2798 }
66fd8ad5 2799
66fd8ad5
AH		 2800 spin_lock_irqsave(&host->lock, flags);
2801
2802 host->runtime_suspended = false;
2803
2804 /* Enable SDIO IRQ */
ef104333 2805 if (host->flags & SDHCI_SDIO_IRQ_ENABLED)
66fd8ad5
AH		 2806 sdhci_enable_sdio_irq_nolock(host, true);
2807
2808 /* Enable Card Detection */
2809 sdhci_enable_card_detection(host);
2810
2811 spin_unlock_irqrestore(&host->lock, flags);
2812
8a125bad 2813 return 0;
66fd8ad5
AH		 2814}
2815EXPORT_SYMBOL_GPL(sdhci_runtime_resume_host);
2816
162d6f98 2817#endif /* CONFIG_PM */
66fd8ad5 2818
d129bceb
PO		 2819/*****************************************************************************\
2820 * *
b8c86fc5 2821 * Device allocation/registration *
d129bceb
PO		 2822 * *
2823\*****************************************************************************/
2824
b8c86fc5
PO		 2825struct sdhci_host *sdhci_alloc_host(struct device *dev,
2826 size_t priv_size)
d129bceb 2827{
d129bceb
PO		 2828 struct mmc_host *mmc;
2829 struct sdhci_host *host;
2830
b8c86fc5 2831 WARN_ON(dev == NULL);
d129bceb 2832
b8c86fc5 2833 mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev);
d129bceb 2834 if (!mmc)
b8c86fc5 2835 return ERR_PTR(-ENOMEM);
d129bceb
PO		 2836
2837 host = mmc_priv(mmc);
2838 host->mmc = mmc;
bf60e592
AH		 2839 host->mmc_host_ops = sdhci_ops;
2840 mmc->ops = &host->mmc_host_ops;
d129bceb 2841
b8c86fc5
PO		 2842 return host;
2843}
8a4da143 2844
b8c86fc5 2845EXPORT_SYMBOL_GPL(sdhci_alloc_host);
d129bceb 2846
b8c86fc5
PO		 2847int sdhci_add_host(struct sdhci_host *host)
2848{
2849 struct mmc_host *mmc;
bd6a8c30 2850 u32 caps[2] = {0, 0};
f2119df6
AN		 2851 u32 max_current_caps;
2852 unsigned int ocr_avail;
f5fa92e5 2853 unsigned int override_timeout_clk;
59241757 2854 u32 max_clk;
b8c86fc5 2855 int ret;
d129bceb 2856
b8c86fc5
PO		 2857 WARN_ON(host == NULL);
2858 if (host == NULL)
2859 return -EINVAL;
d129bceb 2860
b8c86fc5 2861 mmc = host->mmc;
d129bceb 2862
b8c86fc5
PO		 2863 if (debug_quirks)
2864 host->quirks = debug_quirks;
66fd8ad5
AH		 2865 if (debug_quirks2)
2866 host->quirks2 = debug_quirks2;
d129bceb 2867
f5fa92e5
AH		 2868 override_timeout_clk = host->timeout_clk;
2869
03231f9b 2870 sdhci_do_reset(host, SDHCI_RESET_ALL);
d96649ed 2871
4e4141a5 2872 host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
2134a922
PO		 2873 host->version = (host->version & SDHCI_SPEC_VER_MASK)
2874 >> SDHCI_SPEC_VER_SHIFT;
85105c53 2875 if (host->version > SDHCI_SPEC_300) {
2e4456f0
MV		 2876 pr_err("%s: Unknown controller version (%d). You may experience problems.\n",
2877 mmc_hostname(mmc), host->version);
4a965505
PO		 2878 }
2879
f2119df6 2880 caps[0] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ? host->caps :
ccc92c23 2881 sdhci_readl(host, SDHCI_CAPABILITIES);
d129bceb 2882
bd6a8c30
PR		 2883 if (host->version >= SDHCI_SPEC_300)
2884 caps[1] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ?
2885 host->caps1 :
2886 sdhci_readl(host, SDHCI_CAPABILITIES_1);
f2119df6 2887
b8c86fc5 2888 if (host->quirks & SDHCI_QUIRK_FORCE_DMA)
a13abc7b 2889 host->flags |= SDHCI_USE_SDMA;
f2119df6 2890 else if (!(caps[0] & SDHCI_CAN_DO_SDMA))
a13abc7b 2891 DBG("Controller doesn't have SDMA capability\n");
67435274 2892 else
a13abc7b 2893 host->flags |= SDHCI_USE_SDMA;
d129bceb 2894
b8c86fc5 2895 if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
a13abc7b 2896 (host->flags & SDHCI_USE_SDMA)) {
cee687ce 2897 DBG("Disabling DMA as it is marked broken\n");
a13abc7b 2898 host->flags &= ~SDHCI_USE_SDMA;
7c168e3d
FT		 2899 }
2900
f2119df6
AN		 2901 if ((host->version >= SDHCI_SPEC_200) &&
2902 (caps[0] & SDHCI_CAN_DO_ADMA2))
a13abc7b 2903 host->flags |= SDHCI_USE_ADMA;
2134a922
PO		 2904
2905 if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) &&
2906 (host->flags & SDHCI_USE_ADMA)) {
2907 DBG("Disabling ADMA as it is marked broken\n");
2908 host->flags &= ~SDHCI_USE_ADMA;
2909 }
2910
e57a5f61
AH		 2911 /*
2912 * It is assumed that a 64-bit capable device has set a 64-bit DMA mask
2913 * and *must* do 64-bit DMA. A driver has the opportunity to change
2914 * that during the first call to ->enable_dma(). Similarly
2915 * SDHCI_QUIRK2_BROKEN_64_BIT_DMA must be left to the drivers to
2916 * implement.
2917 */
5eaa7476 2918 if (caps[0] & SDHCI_CAN_64BIT)
e57a5f61
AH		 2919 host->flags |= SDHCI_USE_64_BIT_DMA;
2920
a13abc7b 2921 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
b8c86fc5
PO		 2922 if (host->ops->enable_dma) {
2923 if (host->ops->enable_dma(host)) {
6606110d 2924 pr_warn("%s: No suitable DMA available - falling back to PIO\n",
b8c86fc5 2925 mmc_hostname(mmc));
a13abc7b
RR		 2926 host->flags &=
2927 ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
b8c86fc5 2928 }
d129bceb
PO		 2929 }
2930 }
2931
e57a5f61
AH		 2932 /* SDMA does not support 64-bit DMA */
2933 if (host->flags & SDHCI_USE_64_BIT_DMA)
2934 host->flags &= ~SDHCI_USE_SDMA;
2935
2134a922 2936 if (host->flags & SDHCI_USE_ADMA) {
e66e61cb
RK		 2937 dma_addr_t dma;
2938 void *buf;
2939
2134a922 2940 /*
76fe379a
AH		 2941 * The DMA descriptor table size is calculated as the maximum
2942 * number of segments times 2, to allow for an alignment
2943 * descriptor for each segment, plus 1 for a nop end descriptor,
2944 * all multipled by the descriptor size.
2134a922 2945 */
e57a5f61
AH		 2946 if (host->flags & SDHCI_USE_64_BIT_DMA) {
2947 host->adma_table_sz = (SDHCI_MAX_SEGS * 2 + 1) *
2948 SDHCI_ADMA2_64_DESC_SZ;
e57a5f61 2949 host->desc_sz = SDHCI_ADMA2_64_DESC_SZ;
e57a5f61
AH		 2950 } else {
2951 host->adma_table_sz = (SDHCI_MAX_SEGS * 2 + 1) *
2952 SDHCI_ADMA2_32_DESC_SZ;
e57a5f61 2953 host->desc_sz = SDHCI_ADMA2_32_DESC_SZ;
e57a5f61 2954 }
e66e61cb 2955
04a5ae6f 2956 host->align_buffer_sz = SDHCI_MAX_SEGS * SDHCI_ADMA2_ALIGN;
e66e61cb
RK		 2957 buf = dma_alloc_coherent(mmc_dev(mmc), host->align_buffer_sz +
2958 host->adma_table_sz, &dma, GFP_KERNEL);
2959 if (!buf) {
6606110d 2960 pr_warn("%s: Unable to allocate ADMA buffers - falling back to standard DMA\n",
2134a922
PO		 2961 mmc_hostname(mmc));
2962 host->flags &= ~SDHCI_USE_ADMA;
e66e61cb
RK		 2963 } else if ((dma + host->align_buffer_sz) &
2964 (SDHCI_ADMA2_DESC_ALIGN - 1)) {
6606110d
JP		 2965 pr_warn("%s: unable to allocate aligned ADMA descriptor\n",
2966 mmc_hostname(mmc));
d1e49f77 2967 host->flags &= ~SDHCI_USE_ADMA;
e66e61cb
RK		 2968 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
2969 host->adma_table_sz, buf, dma);
2970 } else {
2971 host->align_buffer = buf;
2972 host->align_addr = dma;
edd63fcc 2973
e66e61cb
RK		 2974 host->adma_table = buf + host->align_buffer_sz;
2975 host->adma_addr = dma + host->align_buffer_sz;
2976 }
2134a922
PO		 2977 }
2978
7659150c
PO		 2979 /*
2980 * If we use DMA, then it's up to the caller to set the DMA
2981 * mask, but PIO does not need the hw shim so we set a new
2982 * mask here in that case.
2983 */
a13abc7b 2984 if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) {
7659150c 2985 host->dma_mask = DMA_BIT_MASK(64);
4e743f1f 2986 mmc_dev(mmc)->dma_mask = &host->dma_mask;
7659150c 2987 }
d129bceb 2988
c4687d5f 2989 if (host->version >= SDHCI_SPEC_300)
f2119df6 2990 host->max_clk = (caps[0] & SDHCI_CLOCK_V3_BASE_MASK)
c4687d5f
ZG		 2991 >> SDHCI_CLOCK_BASE_SHIFT;
2992 else
f2119df6 2993 host->max_clk = (caps[0] & SDHCI_CLOCK_BASE_MASK)
c4687d5f
ZG		 2994 >> SDHCI_CLOCK_BASE_SHIFT;
2995
4240ff0a 2996 host->max_clk *= 1000000;
f27f47ef
AV		 2997 if (host->max_clk == 0 || host->quirks &
2998 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) {
4240ff0a 2999 if (!host->ops->get_max_clock) {
2e4456f0
MV		 3000 pr_err("%s: Hardware doesn't specify base clock frequency.\n",
3001 mmc_hostname(mmc));
4240ff0a
BD		 3002 return -ENODEV;
3003 }
3004 host->max_clk = host->ops->get_max_clock(host);
8ef1a143 3005 }
d129bceb 3006
c3ed3877
AN		 3007 /*
3008 * In case of Host Controller v3.00, find out whether clock
3009 * multiplier is supported.
3010 */
3011 host->clk_mul = (caps[1] & SDHCI_CLOCK_MUL_MASK) >>
3012 SDHCI_CLOCK_MUL_SHIFT;
3013
3014 /*
3015 * In case the value in Clock Multiplier is 0, then programmable
3016 * clock mode is not supported, otherwise the actual clock
3017 * multiplier is one more than the value of Clock Multiplier
3018 * in the Capabilities Register.
3019 */
3020 if (host->clk_mul)
3021 host->clk_mul += 1;
3022
d129bceb
PO		 3023 /*
3024 * Set host parameters.
3025 */
59241757
DA		 3026 max_clk = host->max_clk;
3027
ce5f036b 3028 if (host->ops->get_min_clock)
a9e58f25 3029 mmc->f_min = host->ops->get_min_clock(host);
c3ed3877
AN		 3030 else if (host->version >= SDHCI_SPEC_300) {
3031 if (host->clk_mul) {
3032 mmc->f_min = (host->max_clk * host->clk_mul) / 1024;
59241757 3033 max_clk = host->max_clk * host->clk_mul;
c3ed3877
AN		 3034 } else
3035 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300;
3036 } else
0397526d 3037 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200;
15ec4461 3038
59241757
DA		 3039 if (!mmc->f_max || (mmc->f_max && (mmc->f_max > max_clk)))
3040 mmc->f_max = max_clk;
3041
28aab053
AD		 3042 if (!(host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) {
3043 host->timeout_clk = (caps[0] & SDHCI_TIMEOUT_CLK_MASK) >>
3044 SDHCI_TIMEOUT_CLK_SHIFT;
3045 if (host->timeout_clk == 0) {
3046 if (host->ops->get_timeout_clock) {
3047 host->timeout_clk =
3048 host->ops->get_timeout_clock(host);
3049 } else {
3050 pr_err("%s: Hardware doesn't specify timeout clock frequency.\n",
3051 mmc_hostname(mmc));
3052 return -ENODEV;
3053 }
272308ca 3054 }
272308ca 3055
28aab053
AD		 3056 if (caps[0] & SDHCI_TIMEOUT_CLK_UNIT)
3057 host->timeout_clk *= 1000;
272308ca 3058
28aab053 3059 mmc->max_busy_timeout = host->ops->get_max_timeout_count ?
a6ff5aeb 3060 host->ops->get_max_timeout_count(host) : 1 << 27;
28aab053
AD		 3061 mmc->max_busy_timeout /= host->timeout_clk;
3062 }
58d1246d 3063
f5fa92e5
AH		 3064 if (override_timeout_clk)
3065 host->timeout_clk = override_timeout_clk;
3066
e89d456f 3067 mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_ERASE | MMC_CAP_CMD23;
781e989c 3068 mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD;
e89d456f
AW		 3069
3070 if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12)
3071 host->flags |= SDHCI_AUTO_CMD12;
5fe23c7f 3072
8edf6371 3073 /* Auto-CMD23 stuff only works in ADMA or PIO. */
4f3d3e9b 3074 if ((host->version >= SDHCI_SPEC_300) &&
8edf6371 3075 ((host->flags & SDHCI_USE_ADMA) ||
3bfa6f03
SB		 3076 !(host->flags & SDHCI_USE_SDMA)) &&
3077 !(host->quirks2 & SDHCI_QUIRK2_ACMD23_BROKEN)) {
8edf6371
AW		 3078 host->flags |= SDHCI_AUTO_CMD23;
3079 DBG("%s: Auto-CMD23 available\n", mmc_hostname(mmc));
3080 } else {
3081 DBG("%s: Auto-CMD23 unavailable\n", mmc_hostname(mmc));
3082 }
3083
15ec4461
PR		 3084 /*
3085 * A controller may support 8-bit width, but the board itself
3086 * might not have the pins brought out. Boards that support
3087 * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in
3088 * their platform code before calling sdhci_add_host(), and we
3089 * won't assume 8-bit width for hosts without that CAP.
3090 */
5fe23c7f 3091 if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA))
15ec4461 3092 mmc->caps |= MMC_CAP_4_BIT_DATA;
d129bceb 3093
63ef5d8c
JH		 3094 if (host->quirks2 & SDHCI_QUIRK2_HOST_NO_CMD23)
3095 mmc->caps &= ~MMC_CAP_CMD23;
3096
f2119df6 3097 if (caps[0] & SDHCI_CAN_DO_HISPD)
a29e7e18 3098 mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
cd9277c0 3099
176d1ed4 3100 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) &&
c31d22eb
II		 3101 !(mmc->caps & MMC_CAP_NONREMOVABLE) &&
3102 IS_ERR_VALUE(mmc_gpio_get_cd(host->mmc)))
68d1fb7e
AV		 3103 mmc->caps |= MMC_CAP_NEEDS_POLL;
3104
3a48edc4
TK		 3105 /* If there are external regulators, get them */
3106 if (mmc_regulator_get_supply(mmc) == -EPROBE_DEFER)
3107 return -EPROBE_DEFER;
3108
6231f3de 3109 /* If vqmmc regulator and no 1.8V signalling, then there's no UHS */
3a48edc4
TK		 3110 if (!IS_ERR(mmc->supply.vqmmc)) {
3111 ret = regulator_enable(mmc->supply.vqmmc);
3112 if (!regulator_is_supported_voltage(mmc->supply.vqmmc, 1700000,
3113 1950000))
8363c374
KL		 3114 caps[1] &= ~(SDHCI_SUPPORT_SDR104 |
3115 SDHCI_SUPPORT_SDR50 |
3116 SDHCI_SUPPORT_DDR50);
a3361aba
CB		 3117 if (ret) {
3118 pr_warn("%s: Failed to enable vqmmc regulator: %d\n",
3119 mmc_hostname(mmc), ret);
4bb74313 3120 mmc->supply.vqmmc = ERR_PTR(-EINVAL);
a3361aba 3121 }
8363c374 3122 }
6231f3de 3123
6a66180a
DD		 3124 if (host->quirks2 & SDHCI_QUIRK2_NO_1_8_V)
3125 caps[1] &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
3126 SDHCI_SUPPORT_DDR50);
3127
4188bba0
AC		 3128 /* Any UHS-I mode in caps implies SDR12 and SDR25 support. */
3129 if (caps[1] & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
3130 SDHCI_SUPPORT_DDR50))
f2119df6
AN		 3131 mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;
3132
3133 /* SDR104 supports also implies SDR50 support */
156e14b1 3134 if (caps[1] & SDHCI_SUPPORT_SDR104) {
f2119df6 3135 mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50;
156e14b1
GC		 3136 /* SD3.0: SDR104 is supported so (for eMMC) the caps2
3137 * field can be promoted to support HS200.
3138 */
549c0b18 3139 if (!(host->quirks2 & SDHCI_QUIRK2_BROKEN_HS200))
13868bf2 3140 mmc->caps2 |= MMC_CAP2_HS200;
156e14b1 3141 } else if (caps[1] & SDHCI_SUPPORT_SDR50)
f2119df6
AN		 3142 mmc->caps |= MMC_CAP_UHS_SDR50;
3143
e9fb05d5
AH		 3144 if (host->quirks2 & SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 &&
3145 (caps[1] & SDHCI_SUPPORT_HS400))
3146 mmc->caps2 |= MMC_CAP2_HS400;
3147
549c0b18
AH		 3148 if ((mmc->caps2 & MMC_CAP2_HSX00_1_2V) &&
3149 (IS_ERR(mmc->supply.vqmmc) ||
3150 !regulator_is_supported_voltage(mmc->supply.vqmmc, 1100000,
3151 1300000)))
3152 mmc->caps2 &= ~MMC_CAP2_HSX00_1_2V;
3153
9107ebbf
MC		 3154 if ((caps[1] & SDHCI_SUPPORT_DDR50) &&
3155 !(host->quirks2 & SDHCI_QUIRK2_BROKEN_DDR50))
f2119df6
AN		 3156 mmc->caps |= MMC_CAP_UHS_DDR50;
3157
069c9f14 3158 /* Does the host need tuning for SDR50? */
b513ea25
AN		 3159 if (caps[1] & SDHCI_USE_SDR50_TUNING)
3160 host->flags |= SDHCI_SDR50_NEEDS_TUNING;
3161
156e14b1 3162 /* Does the host need tuning for SDR104 / HS200? */
069c9f14 3163 if (mmc->caps2 & MMC_CAP2_HS200)
156e14b1 3164 host->flags |= SDHCI_SDR104_NEEDS_TUNING;
069c9f14 3165
d6d50a15
AN		 3166 /* Driver Type(s) (A, C, D) supported by the host */
3167 if (caps[1] & SDHCI_DRIVER_TYPE_A)
3168 mmc->caps |= MMC_CAP_DRIVER_TYPE_A;
3169 if (caps[1] & SDHCI_DRIVER_TYPE_C)
3170 mmc->caps |= MMC_CAP_DRIVER_TYPE_C;
3171 if (caps[1] & SDHCI_DRIVER_TYPE_D)
3172 mmc->caps |= MMC_CAP_DRIVER_TYPE_D;
3173
cf2b5eea
AN		 3174 /* Initial value for re-tuning timer count */
3175 host->tuning_count = (caps[1] & SDHCI_RETUNING_TIMER_COUNT_MASK) >>
3176 SDHCI_RETUNING_TIMER_COUNT_SHIFT;
3177
3178 /*
3179 * In case Re-tuning Timer is not disabled, the actual value of
3180 * re-tuning timer will be 2 ^ (n - 1).
3181 */
3182 if (host->tuning_count)
3183 host->tuning_count = 1 << (host->tuning_count - 1);
3184
3185 /* Re-tuning mode supported by the Host Controller */
3186 host->tuning_mode = (caps[1] & SDHCI_RETUNING_MODE_MASK) >>
3187 SDHCI_RETUNING_MODE_SHIFT;
3188
8f230f45 3189 ocr_avail = 0;
bad37e1a 3190
f2119df6
AN		 3191 /*
3192 * According to SD Host Controller spec v3.00, if the Host System
3193 * can afford more than 150mA, Host Driver should set XPC to 1. Also
3194 * the value is meaningful only if Voltage Support in the Capabilities
3195 * register is set. The actual current value is 4 times the register
3196 * value.
3197 */
3198 max_current_caps = sdhci_readl(host, SDHCI_MAX_CURRENT);
3a48edc4 3199 if (!max_current_caps && !IS_ERR(mmc->supply.vmmc)) {
ae906037 3200 int curr = regulator_get_current_limit(mmc->supply.vmmc);
bad37e1a
PR		 3201 if (curr > 0) {
3202
3203 /* convert to SDHCI_MAX_CURRENT format */
3204 curr = curr/1000; /* convert to mA */
3205 curr = curr/SDHCI_MAX_CURRENT_MULTIPLIER;
3206
3207 curr = min_t(u32, curr, SDHCI_MAX_CURRENT_LIMIT);
3208 max_current_caps =
3209 (curr << SDHCI_MAX_CURRENT_330_SHIFT) |
3210 (curr << SDHCI_MAX_CURRENT_300_SHIFT) |
3211 (curr << SDHCI_MAX_CURRENT_180_SHIFT);
3212 }
3213 }
f2119df6
AN		 3214
3215 if (caps[0] & SDHCI_CAN_VDD_330) {
8f230f45 3216 ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34;
f2119df6 3217
55c4665e 3218 mmc->max_current_330 = ((max_current_caps &
f2119df6
AN		 3219 SDHCI_MAX_CURRENT_330_MASK) >>
3220 SDHCI_MAX_CURRENT_330_SHIFT) *
3221 SDHCI_MAX_CURRENT_MULTIPLIER;
f2119df6
AN		 3222 }
3223 if (caps[0] & SDHCI_CAN_VDD_300) {
8f230f45 3224 ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31;
f2119df6 3225
55c4665e 3226 mmc->max_current_300 = ((max_current_caps &
f2119df6
AN		 3227 SDHCI_MAX_CURRENT_300_MASK) >>
3228 SDHCI_MAX_CURRENT_300_SHIFT) *
3229 SDHCI_MAX_CURRENT_MULTIPLIER;
f2119df6
AN		 3230 }
3231 if (caps[0] & SDHCI_CAN_VDD_180) {
8f230f45
TI		 3232 ocr_avail |= MMC_VDD_165_195;
3233
55c4665e 3234 mmc->max_current_180 = ((max_current_caps &
f2119df6
AN		 3235 SDHCI_MAX_CURRENT_180_MASK) >>
3236 SDHCI_MAX_CURRENT_180_SHIFT) *
3237 SDHCI_MAX_CURRENT_MULTIPLIER;
f2119df6
AN		 3238 }
3239
5fd26c7e
UH		 3240 /* If OCR set by host, use it instead. */
3241 if (host->ocr_mask)
3242 ocr_avail = host->ocr_mask;
3243
3244 /* If OCR set by external regulators, give it highest prio. */
3a48edc4 3245 if (mmc->ocr_avail)
52221610 3246 ocr_avail = mmc->ocr_avail;
3a48edc4 3247
8f230f45
TI		 3248 mmc->ocr_avail = ocr_avail;
3249 mmc->ocr_avail_sdio = ocr_avail;
3250 if (host->ocr_avail_sdio)
3251 mmc->ocr_avail_sdio &= host->ocr_avail_sdio;
3252 mmc->ocr_avail_sd = ocr_avail;
3253 if (host->ocr_avail_sd)
3254 mmc->ocr_avail_sd &= host->ocr_avail_sd;
3255 else /* normal SD controllers don't support 1.8V */
3256 mmc->ocr_avail_sd &= ~MMC_VDD_165_195;
3257 mmc->ocr_avail_mmc = ocr_avail;
3258 if (host->ocr_avail_mmc)
3259 mmc->ocr_avail_mmc &= host->ocr_avail_mmc;
146ad66e
PO		 3260
3261 if (mmc->ocr_avail == 0) {
2e4456f0
MV		 3262 pr_err("%s: Hardware doesn't report any support voltages.\n",
3263 mmc_hostname(mmc));
b8c86fc5 3264 return -ENODEV;
146ad66e
PO		 3265 }
3266
d129bceb
PO		 3267 spin_lock_init(&host->lock);
3268
3269 /*
2134a922
PO		 3270 * Maximum number of segments. Depends on if the hardware
3271 * can do scatter/gather or not.
d129bceb 3272 */
2134a922 3273 if (host->flags & SDHCI_USE_ADMA)
4fb213f8 3274 mmc->max_segs = SDHCI_MAX_SEGS;
a13abc7b 3275 else if (host->flags & SDHCI_USE_SDMA)
a36274e0 3276 mmc->max_segs = 1;
2134a922 3277 else /* PIO */
4fb213f8 3278 mmc->max_segs = SDHCI_MAX_SEGS;
d129bceb
PO		 3279
3280 /*
ac00531d
AH		 3281 * Maximum number of sectors in one transfer. Limited by SDMA boundary
3282 * size (512KiB). Note some tuning modes impose a 4MiB limit, but this
3283 * is less anyway.
d129bceb 3284 */
55db890a 3285 mmc->max_req_size = 524288;
d129bceb
PO		 3286
3287 /*
3288 * Maximum segment size. Could be one segment with the maximum number
2134a922
PO		 3289 * of bytes. When doing hardware scatter/gather, each entry cannot
3290 * be larger than 64 KiB though.
d129bceb 3291 */
30652aa3
OJ		 3292 if (host->flags & SDHCI_USE_ADMA) {
3293 if (host->quirks & SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC)
3294 mmc->max_seg_size = 65535;
3295 else
3296 mmc->max_seg_size = 65536;
3297 } else {
2134a922 3298 mmc->max_seg_size = mmc->max_req_size;
30652aa3 3299 }
d129bceb 3300
fe4a3c7a
PO		 3301 /*
3302 * Maximum block size. This varies from controller to controller and
3303 * is specified in the capabilities register.
3304 */
0633f654
AV		 3305 if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) {
3306 mmc->max_blk_size = 2;
3307 } else {
f2119df6 3308 mmc->max_blk_size = (caps[0] & SDHCI_MAX_BLOCK_MASK) >>
0633f654
AV		 3309 SDHCI_MAX_BLOCK_SHIFT;
3310 if (mmc->max_blk_size >= 3) {
6606110d
JP		 3311 pr_warn("%s: Invalid maximum block size, assuming 512 bytes\n",
3312 mmc_hostname(mmc));
0633f654
AV		 3313 mmc->max_blk_size = 0;
3314 }
3315 }
3316
3317 mmc->max_blk_size = 512 << mmc->max_blk_size;
fe4a3c7a 3318
55db890a
PO		 3319 /*
3320 * Maximum block count.
3321 */
1388eefd 3322 mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
55db890a 3323
d129bceb
PO		 3324 /*
3325 * Init tasklets.
3326 */
d129bceb
PO		 3327 tasklet_init(&host->finish_tasklet,
3328 sdhci_tasklet_finish, (unsigned long)host);
3329
e4cad1b5 3330 setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host);
d129bceb 3331
250fb7b4 3332 init_waitqueue_head(&host->buf_ready_int);
b513ea25 3333
2af502ca
SG		 3334 sdhci_init(host, 0);
3335
781e989c
RK		 3336 ret = request_threaded_irq(host->irq, sdhci_irq, sdhci_thread_irq,
3337 IRQF_SHARED, mmc_hostname(mmc), host);
0fc81ee3
MB		 3338 if (ret) {
3339 pr_err("%s: Failed to request IRQ %d: %d\n",
3340 mmc_hostname(mmc), host->irq, ret);
8ef1a143 3341 goto untasklet;
0fc81ee3 3342 }
d129bceb 3343
d129bceb
PO		 3344#ifdef CONFIG_MMC_DEBUG
3345 sdhci_dumpregs(host);
3346#endif
3347
f9134319 3348#ifdef SDHCI_USE_LEDS_CLASS
5dbace0c
HS		 3349 snprintf(host->led_name, sizeof(host->led_name),
3350 "%s::", mmc_hostname(mmc));
3351 host->led.name = host->led_name;
2f730fec
PO		 3352 host->led.brightness = LED_OFF;
3353 host->led.default_trigger = mmc_hostname(mmc);
3354 host->led.brightness_set = sdhci_led_control;
3355
b8c86fc5 3356 ret = led_classdev_register(mmc_dev(mmc), &host->led);
0fc81ee3
MB		 3357 if (ret) {
3358 pr_err("%s: Failed to register LED device: %d\n",
3359 mmc_hostname(mmc), ret);
2f730fec 3360 goto reset;
0fc81ee3 3361 }
2f730fec
PO		 3362#endif
3363
5f25a66f
PO		 3364 mmiowb();
3365
d129bceb
PO		 3366 mmc_add_host(mmc);
3367
a3c76eb9 3368 pr_info("%s: SDHCI controller on %s [%s] using %s\n",
d1b26863 3369 mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)),
e57a5f61
AH		 3370 (host->flags & SDHCI_USE_ADMA) ?
3371 (host->flags & SDHCI_USE_64_BIT_DMA) ? "ADMA 64-bit" : "ADMA" :
a13abc7b 3372 (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO");
d129bceb 3373
7260cf5e
AV		 3374 sdhci_enable_card_detection(host);
3375
d129bceb
PO		 3376 return 0;
3377
f9134319 3378#ifdef SDHCI_USE_LEDS_CLASS
2f730fec 3379reset:
03231f9b 3380 sdhci_do_reset(host, SDHCI_RESET_ALL);
b537f94c
RK		 3381 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
3382 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
2f730fec
PO		 3383 free_irq(host->irq, host);
3384#endif
8ef1a143 3385untasklet:
d129bceb 3386 tasklet_kill(&host->finish_tasklet);
d129bceb
PO		 3387
3388 return ret;
3389}
3390
b8c86fc5 3391EXPORT_SYMBOL_GPL(sdhci_add_host);
d129bceb 3392
1e72859e 3393void sdhci_remove_host(struct sdhci_host *host, int dead)
b8c86fc5 3394{
3a48edc4 3395 struct mmc_host *mmc = host->mmc;
1e72859e
PO		 3396 unsigned long flags;
3397
3398 if (dead) {
3399 spin_lock_irqsave(&host->lock, flags);
3400
3401 host->flags |= SDHCI_DEVICE_DEAD;
3402
3403 if (host->mrq) {
a3c76eb9 3404 pr_err("%s: Controller removed during "
4e743f1f 3405 " transfer!\n", mmc_hostname(mmc));
1e72859e
PO		 3406
3407 host->mrq->cmd->error = -ENOMEDIUM;
3408 tasklet_schedule(&host->finish_tasklet);
3409 }
3410
3411 spin_unlock_irqrestore(&host->lock, flags);
3412 }
3413
7260cf5e
AV		 3414 sdhci_disable_card_detection(host);
3415
4e743f1f 3416 mmc_remove_host(mmc);
d129bceb 3417
f9134319 3418#ifdef SDHCI_USE_LEDS_CLASS
2f730fec
PO		 3419 led_classdev_unregister(&host->led);
3420#endif
3421
1e72859e 3422 if (!dead)
03231f9b 3423 sdhci_do_reset(host, SDHCI_RESET_ALL);
d129bceb 3424
b537f94c
RK		 3425 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
3426 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
d129bceb
PO		 3427 free_irq(host->irq, host);
3428
3429 del_timer_sync(&host->timer);
3430
d129bceb 3431 tasklet_kill(&host->finish_tasklet);
2134a922 3432
3a48edc4
TK		 3433 if (!IS_ERR(mmc->supply.vqmmc))
3434 regulator_disable(mmc->supply.vqmmc);
6231f3de 3435
edd63fcc 3436 if (host->align_buffer)
e66e61cb
RK		 3437 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
3438 host->adma_table_sz, host->align_buffer,
3439 host->align_addr);
2134a922 3440
4efaa6fb 3441 host->adma_table = NULL;
2134a922 3442 host->align_buffer = NULL;
d129bceb
PO		 3443}
3444
b8c86fc5 3445EXPORT_SYMBOL_GPL(sdhci_remove_host);
d129bceb 3446
b8c86fc5 3447void sdhci_free_host(struct sdhci_host *host)
d129bceb 3448{
b8c86fc5 3449 mmc_free_host(host->mmc);
d129bceb
PO		 3450}
3451
b8c86fc5 3452EXPORT_SYMBOL_GPL(sdhci_free_host);
d129bceb
PO		 3453
3454/*****************************************************************************\
3455 * *
3456 * Driver init/exit *
3457 * *
3458\*****************************************************************************/
3459
3460static int __init sdhci_drv_init(void)
3461{
a3c76eb9 3462 pr_info(DRIVER_NAME
52fbf9c9 3463 ": Secure Digital Host Controller Interface driver\n");
a3c76eb9 3464 pr_info(DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
d129bceb 3465
b8c86fc5 3466 return 0;
d129bceb
PO		 3467}
3468
3469static void __exit sdhci_drv_exit(void)
3470{
d129bceb
PO		 3471}
3472
3473module_init(sdhci_drv_init);
3474module_exit(sdhci_drv_exit);
3475
df673b22 3476module_param(debug_quirks, uint, 0444);
66fd8ad5 3477module_param(debug_quirks2, uint, 0444);
67435274 3478
32710e8f 3479MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
b8c86fc5 3480MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver");
d129bceb 3481MODULE_LICENSE("GPL");
67435274 3482
df673b22 3483MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");
66fd8ad5 3484MODULE_PARM_DESC(debug_quirks2, "Force certain other quirks.");
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