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mmc: Consolidate emmc tuning blocks
[mirror_ubuntu-artful-kernel.git] / drivers / mmc / host / sdhci.c
CommitLineData
d129bceb 1/*
70f10482 2 * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
d129bceb 3 *
b69c9058 4 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
d129bceb
PO		 5 *
6 * This program is free software; you can redistribute it and/or modify
643f720c
PO		 7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or (at
9 * your option) any later version.
84c46a53
PO		 10 *
11 * Thanks to the following companies for their support:
12 *
13 * - JMicron (hardware and technical support)
d129bceb
PO		 14 */
15
d129bceb
PO		 16#include <linux/delay.h>
17#include <linux/highmem.h>
b8c86fc5 18#include <linux/io.h>
88b47679 19#include <linux/module.h>
d129bceb 20#include <linux/dma-mapping.h>
5a0e3ad6 21#include <linux/slab.h>
11763609 22#include <linux/scatterlist.h>
9bea3c85 23#include <linux/regulator/consumer.h>
66fd8ad5 24#include <linux/pm_runtime.h>
d129bceb 25
2f730fec
PO		 26#include <linux/leds.h>
27
22113efd 28#include <linux/mmc/mmc.h>
d129bceb 29#include <linux/mmc/host.h>
473b095a 30#include <linux/mmc/card.h>
bec9d4e5 31#include <linux/mmc/slot-gpio.h>
d129bceb 32
d129bceb
PO		 33#include "sdhci.h"
34
35#define DRIVER_NAME "sdhci"
d129bceb 36
d129bceb 37#define DBG(f, x...) \
c6563178 38 pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
d129bceb 39
f9134319
PO		 40#if defined(CONFIG_LEDS_CLASS) || (defined(CONFIG_LEDS_CLASS_MODULE) && \
41 defined(CONFIG_MMC_SDHCI_MODULE))
42#define SDHCI_USE_LEDS_CLASS
43#endif
44
b513ea25
AN		 45#define MAX_TUNING_LOOP 40
46
d1e49f77
RK		 47#define ADMA_SIZE ((128 * 2 + 1) * 4)
48
df673b22 49static unsigned int debug_quirks = 0;
66fd8ad5 50static unsigned int debug_quirks2;
67435274 51
d129bceb
PO		 52static void sdhci_finish_data(struct sdhci_host *);
53
d129bceb 54static void sdhci_finish_command(struct sdhci_host *);
069c9f14 55static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode);
cf2b5eea 56static void sdhci_tuning_timer(unsigned long data);
52983382 57static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable);
d129bceb 58
66fd8ad5
AH		 59#ifdef CONFIG_PM_RUNTIME
60static int sdhci_runtime_pm_get(struct sdhci_host *host);
61static int sdhci_runtime_pm_put(struct sdhci_host *host);
f0710a55
AH		 62static void sdhci_runtime_pm_bus_on(struct sdhci_host *host);
63static void sdhci_runtime_pm_bus_off(struct sdhci_host *host);
66fd8ad5
AH		 64#else
65static inline int sdhci_runtime_pm_get(struct sdhci_host *host)
66{
67 return 0;
68}
69static inline int sdhci_runtime_pm_put(struct sdhci_host *host)
70{
71 return 0;
72}
f0710a55
AH		 73static void sdhci_runtime_pm_bus_on(struct sdhci_host *host)
74{
75}
76static void sdhci_runtime_pm_bus_off(struct sdhci_host *host)
77{
78}
66fd8ad5
AH		 79#endif
80
d129bceb
PO		 81static void sdhci_dumpregs(struct sdhci_host *host)
82{
a3c76eb9 83 pr_debug(DRIVER_NAME ": =========== REGISTER DUMP (%s)===========\n",
412ab659 84 mmc_hostname(host->mmc));
d129bceb 85
a3c76eb9 86 pr_debug(DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n",
4e4141a5
AV		 87 sdhci_readl(host, SDHCI_DMA_ADDRESS),
88 sdhci_readw(host, SDHCI_HOST_VERSION));
a3c76eb9 89 pr_debug(DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n",
4e4141a5
AV		 90 sdhci_readw(host, SDHCI_BLOCK_SIZE),
91 sdhci_readw(host, SDHCI_BLOCK_COUNT));
a3c76eb9 92 pr_debug(DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
4e4141a5
AV		 93 sdhci_readl(host, SDHCI_ARGUMENT),
94 sdhci_readw(host, SDHCI_TRANSFER_MODE));
a3c76eb9 95 pr_debug(DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n",
4e4141a5
AV		 96 sdhci_readl(host, SDHCI_PRESENT_STATE),
97 sdhci_readb(host, SDHCI_HOST_CONTROL));
a3c76eb9 98 pr_debug(DRIVER_NAME ": Power: 0x%08x | Blk gap: 0x%08x\n",
4e4141a5
AV		 99 sdhci_readb(host, SDHCI_POWER_CONTROL),
100 sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL));
a3c76eb9 101 pr_debug(DRIVER_NAME ": Wake-up: 0x%08x | Clock: 0x%08x\n",
4e4141a5
AV		 102 sdhci_readb(host, SDHCI_WAKE_UP_CONTROL),
103 sdhci_readw(host, SDHCI_CLOCK_CONTROL));
a3c76eb9 104 pr_debug(DRIVER_NAME ": Timeout: 0x%08x | Int stat: 0x%08x\n",
4e4141a5
AV		 105 sdhci_readb(host, SDHCI_TIMEOUT_CONTROL),
106 sdhci_readl(host, SDHCI_INT_STATUS));
a3c76eb9 107 pr_debug(DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
4e4141a5
AV		 108 sdhci_readl(host, SDHCI_INT_ENABLE),
109 sdhci_readl(host, SDHCI_SIGNAL_ENABLE));
a3c76eb9 110 pr_debug(DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
4e4141a5
AV		 111 sdhci_readw(host, SDHCI_ACMD12_ERR),
112 sdhci_readw(host, SDHCI_SLOT_INT_STATUS));
a3c76eb9 113 pr_debug(DRIVER_NAME ": Caps: 0x%08x | Caps_1: 0x%08x\n",
4e4141a5 114 sdhci_readl(host, SDHCI_CAPABILITIES),
e8120ad1 115 sdhci_readl(host, SDHCI_CAPABILITIES_1));
a3c76eb9 116 pr_debug(DRIVER_NAME ": Cmd: 0x%08x | Max curr: 0x%08x\n",
e8120ad1 117 sdhci_readw(host, SDHCI_COMMAND),
4e4141a5 118 sdhci_readl(host, SDHCI_MAX_CURRENT));
a3c76eb9 119 pr_debug(DRIVER_NAME ": Host ctl2: 0x%08x\n",
f2119df6 120 sdhci_readw(host, SDHCI_HOST_CONTROL2));
d129bceb 121
be3f4ae0 122 if (host->flags & SDHCI_USE_ADMA)
a3c76eb9 123 pr_debug(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n",
be3f4ae0
BD		 124 readl(host->ioaddr + SDHCI_ADMA_ERROR),
125 readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
126
a3c76eb9 127 pr_debug(DRIVER_NAME ": ===========================================\n");
d129bceb
PO		 128}
129
130/*****************************************************************************\
131 * *
132 * Low level functions *
133 * *
134\*****************************************************************************/
135
7260cf5e
AV		 136static void sdhci_set_card_detection(struct sdhci_host *host, bool enable)
137{
5b4f1f6c 138 u32 present;
7260cf5e 139
c79396c1 140 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) ||
87b87a3f 141 (host->mmc->caps & MMC_CAP_NONREMOVABLE))
66fd8ad5
AH		 142 return;
143
5b4f1f6c
RK		 144 if (enable) {
145 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
146 SDHCI_CARD_PRESENT;
d25928d1 147
5b4f1f6c
RK		 148 host->ier |= present ? SDHCI_INT_CARD_REMOVE :
149 SDHCI_INT_CARD_INSERT;
150 } else {
151 host->ier &= ~(SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT);
152 }
b537f94c
RK		 153
154 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
155 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
7260cf5e
AV		 156}
157
158static void sdhci_enable_card_detection(struct sdhci_host *host)
159{
160 sdhci_set_card_detection(host, true);
161}
162
163static void sdhci_disable_card_detection(struct sdhci_host *host)
164{
165 sdhci_set_card_detection(host, false);
166}
167
03231f9b 168void sdhci_reset(struct sdhci_host *host, u8 mask)
d129bceb 169{
e16514d8 170 unsigned long timeout;
393c1a34 171
4e4141a5 172 sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
d129bceb 173
f0710a55 174 if (mask & SDHCI_RESET_ALL) {
d129bceb 175 host->clock = 0;
f0710a55
AH		 176 /* Reset-all turns off SD Bus Power */
177 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
178 sdhci_runtime_pm_bus_off(host);
179 }
d129bceb 180
e16514d8
PO		 181 /* Wait max 100 ms */
182 timeout = 100;
183
184 /* hw clears the bit when it's done */
4e4141a5 185 while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
e16514d8 186 if (timeout == 0) {
a3c76eb9 187 pr_err("%s: Reset 0x%x never completed.\n",
e16514d8
PO		 188 mmc_hostname(host->mmc), (int)mask);
189 sdhci_dumpregs(host);
190 return;
191 }
192 timeout--;
193 mdelay(1);
d129bceb 194 }
03231f9b
RK		 195}
196EXPORT_SYMBOL_GPL(sdhci_reset);
197
198static void sdhci_do_reset(struct sdhci_host *host, u8 mask)
199{
200 if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
201 if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) &
202 SDHCI_CARD_PRESENT))
203 return;
204 }
063a9dbb 205
03231f9b 206 host->ops->reset(host, mask);
393c1a34 207
da91a8f9
RK		 208 if (mask & SDHCI_RESET_ALL) {
209 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
210 if (host->ops->enable_dma)
211 host->ops->enable_dma(host);
212 }
213
214 /* Resetting the controller clears many */
215 host->preset_enabled = false;
3abc1e80 216 }
d129bceb
PO		 217}
218
2f4cbb3d
NP		 219static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios);
220
221static void sdhci_init(struct sdhci_host *host, int soft)
d129bceb 222{
2f4cbb3d 223 if (soft)
03231f9b 224 sdhci_do_reset(host, SDHCI_RESET_CMD|SDHCI_RESET_DATA);
2f4cbb3d 225 else
03231f9b 226 sdhci_do_reset(host, SDHCI_RESET_ALL);
d129bceb 227
b537f94c
RK		 228 host->ier = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
229 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT |
230 SDHCI_INT_INDEX | SDHCI_INT_END_BIT | SDHCI_INT_CRC |
231 SDHCI_INT_TIMEOUT | SDHCI_INT_DATA_END |
232 SDHCI_INT_RESPONSE;
233
234 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
235 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2f4cbb3d
NP		 236
237 if (soft) {
238 /* force clock reconfiguration */
239 host->clock = 0;
240 sdhci_set_ios(host->mmc, &host->mmc->ios);
241 }
7260cf5e 242}
d129bceb 243
7260cf5e
AV		 244static void sdhci_reinit(struct sdhci_host *host)
245{
2f4cbb3d 246 sdhci_init(host, 0);
b67c6b41
AL		 247 /*
248 * Retuning stuffs are affected by different cards inserted and only
249 * applicable to UHS-I cards. So reset these fields to their initial
250 * value when card is removed.
251 */
973905fe
AL		 252 if (host->flags & SDHCI_USING_RETUNING_TIMER) {
253 host->flags &= ~SDHCI_USING_RETUNING_TIMER;
254
b67c6b41
AL		 255 del_timer_sync(&host->tuning_timer);
256 host->flags &= ~SDHCI_NEEDS_RETUNING;
257 host->mmc->max_blk_count =
258 (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
259 }
7260cf5e 260 sdhci_enable_card_detection(host);
d129bceb
PO		 261}
262
263static void sdhci_activate_led(struct sdhci_host *host)
264{
265 u8 ctrl;
266
4e4141a5 267 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
d129bceb 268 ctrl |= SDHCI_CTRL_LED;
4e4141a5 269 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d129bceb
PO		 270}
271
272static void sdhci_deactivate_led(struct sdhci_host *host)
273{
274 u8 ctrl;
275
4e4141a5 276 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
d129bceb 277 ctrl &= ~SDHCI_CTRL_LED;
4e4141a5 278 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d129bceb
PO		 279}
280
f9134319 281#ifdef SDHCI_USE_LEDS_CLASS
2f730fec
PO		 282static void sdhci_led_control(struct led_classdev *led,
283 enum led_brightness brightness)
284{
285 struct sdhci_host *host = container_of(led, struct sdhci_host, led);
286 unsigned long flags;
287
288 spin_lock_irqsave(&host->lock, flags);
289
66fd8ad5
AH		 290 if (host->runtime_suspended)
291 goto out;
292
2f730fec
PO		 293 if (brightness == LED_OFF)
294 sdhci_deactivate_led(host);
295 else
296 sdhci_activate_led(host);
66fd8ad5 297out:
2f730fec
PO		 298 spin_unlock_irqrestore(&host->lock, flags);
299}
300#endif
301
d129bceb
PO		 302/*****************************************************************************\
303 * *
304 * Core functions *
305 * *
306\*****************************************************************************/
307
a406f5a3 308static void sdhci_read_block_pio(struct sdhci_host *host)
d129bceb 309{
7659150c
PO		 310 unsigned long flags;
311 size_t blksize, len, chunk;
7244b85b 312 u32 uninitialized_var(scratch);
7659150c 313 u8 *buf;
d129bceb 314
a406f5a3 315 DBG("PIO reading\n");
d129bceb 316
a406f5a3 317 blksize = host->data->blksz;
7659150c 318 chunk = 0;
d129bceb 319
7659150c 320 local_irq_save(flags);
d129bceb 321
a406f5a3 322 while (blksize) {
7659150c
PO		 323 if (!sg_miter_next(&host->sg_miter))
324 BUG();
d129bceb 325
7659150c 326 len = min(host->sg_miter.length, blksize);
d129bceb 327
7659150c
PO		 328 blksize -= len;
329 host->sg_miter.consumed = len;
14d836e7 330
7659150c 331 buf = host->sg_miter.addr;
d129bceb 332
7659150c
PO		 333 while (len) {
334 if (chunk == 0) {
4e4141a5 335 scratch = sdhci_readl(host, SDHCI_BUFFER);
7659150c 336 chunk = 4;
a406f5a3 337 }
7659150c
PO		 338
339 *buf = scratch & 0xFF;
340
341 buf++;
342 scratch >>= 8;
343 chunk--;
344 len--;
d129bceb 345 }
a406f5a3 346 }
7659150c
PO		 347
348 sg_miter_stop(&host->sg_miter);
349
350 local_irq_restore(flags);
a406f5a3 351}
d129bceb 352
a406f5a3
PO		 353static void sdhci_write_block_pio(struct sdhci_host *host)
354{
7659150c
PO		 355 unsigned long flags;
356 size_t blksize, len, chunk;
357 u32 scratch;
358 u8 *buf;
d129bceb 359
a406f5a3
PO		 360 DBG("PIO writing\n");
361
362 blksize = host->data->blksz;
7659150c
PO		 363 chunk = 0;
364 scratch = 0;
d129bceb 365
7659150c 366 local_irq_save(flags);
d129bceb 367
a406f5a3 368 while (blksize) {
7659150c
PO		 369 if (!sg_miter_next(&host->sg_miter))
370 BUG();
a406f5a3 371
7659150c
PO		 372 len = min(host->sg_miter.length, blksize);
373
374 blksize -= len;
375 host->sg_miter.consumed = len;
376
377 buf = host->sg_miter.addr;
d129bceb 378
7659150c
PO		 379 while (len) {
380 scratch |= (u32)*buf << (chunk * 8);
381
382 buf++;
383 chunk++;
384 len--;
385
386 if ((chunk == 4) || ((len == 0) && (blksize == 0))) {
4e4141a5 387 sdhci_writel(host, scratch, SDHCI_BUFFER);
7659150c
PO		 388 chunk = 0;
389 scratch = 0;
d129bceb 390 }
d129bceb
PO		 391 }
392 }
7659150c
PO		 393
394 sg_miter_stop(&host->sg_miter);
395
396 local_irq_restore(flags);
a406f5a3
PO		 397}
398
399static void sdhci_transfer_pio(struct sdhci_host *host)
400{
401 u32 mask;
402
403 BUG_ON(!host->data);
404
7659150c 405 if (host->blocks == 0)
a406f5a3
PO		 406 return;
407
408 if (host->data->flags & MMC_DATA_READ)
409 mask = SDHCI_DATA_AVAILABLE;
410 else
411 mask = SDHCI_SPACE_AVAILABLE;
412
4a3cba32
PO		 413 /*
414 * Some controllers (JMicron JMB38x) mess up the buffer bits
415 * for transfers < 4 bytes. As long as it is just one block,
416 * we can ignore the bits.
417 */
418 if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) &&
419 (host->data->blocks == 1))
420 mask = ~0;
421
4e4141a5 422 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
3e3bf207
AV		 423 if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY)
424 udelay(100);
425
a406f5a3
PO		 426 if (host->data->flags & MMC_DATA_READ)
427 sdhci_read_block_pio(host);
428 else
429 sdhci_write_block_pio(host);
d129bceb 430
7659150c
PO		 431 host->blocks--;
432 if (host->blocks == 0)
a406f5a3 433 break;
a406f5a3 434 }
d129bceb 435
a406f5a3 436 DBG("PIO transfer complete.\n");
d129bceb
PO		 437}
438
2134a922
PO		 439static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags)
440{
441 local_irq_save(*flags);
482fce99 442 return kmap_atomic(sg_page(sg)) + sg->offset;
2134a922
PO		 443}
444
445static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags)
446{
482fce99 447 kunmap_atomic(buffer);
2134a922
PO		 448 local_irq_restore(*flags);
449}
450
118cd17d
BD		 451static void sdhci_set_adma_desc(u8 *desc, u32 addr, int len, unsigned cmd)
452{
9e506f35
BD		 453 __le32 *dataddr = (__le32 __force *)(desc + 4);
454 __le16 *cmdlen = (__le16 __force *)desc;
118cd17d 455
9e506f35
BD		 456 /* SDHCI specification says ADMA descriptors should be 4 byte
457 * aligned, so using 16 or 32bit operations should be safe. */
118cd17d 458
9e506f35
BD		 459 cmdlen[0] = cpu_to_le16(cmd);
460 cmdlen[1] = cpu_to_le16(len);
461
462 dataddr[0] = cpu_to_le32(addr);
118cd17d
BD		 463}
464
8f1934ce 465static int sdhci_adma_table_pre(struct sdhci_host *host,
2134a922
PO		 466 struct mmc_data *data)
467{
468 int direction;
469
470 u8 *desc;
471 u8 *align;
472 dma_addr_t addr;
473 dma_addr_t align_addr;
474 int len, offset;
475
476 struct scatterlist *sg;
477 int i;
478 char *buffer;
479 unsigned long flags;
480
481 /*
482 * The spec does not specify endianness of descriptor table.
483 * We currently guess that it is LE.
484 */
485
486 if (data->flags & MMC_DATA_READ)
487 direction = DMA_FROM_DEVICE;
488 else
489 direction = DMA_TO_DEVICE;
490
2134a922
PO		 491 host->align_addr = dma_map_single(mmc_dev(host->mmc),
492 host->align_buffer, 128 * 4, direction);
8d8bb39b 493 if (dma_mapping_error(mmc_dev(host->mmc), host->align_addr))
8f1934ce 494 goto fail;
2134a922
PO		 495 BUG_ON(host->align_addr & 0x3);
496
497 host->sg_count = dma_map_sg(mmc_dev(host->mmc),
498 data->sg, data->sg_len, direction);
8f1934ce
PO		 499 if (host->sg_count == 0)
500 goto unmap_align;
2134a922
PO		 501
502 desc = host->adma_desc;
503 align = host->align_buffer;
504
505 align_addr = host->align_addr;
506
507 for_each_sg(data->sg, sg, host->sg_count, i) {
508 addr = sg_dma_address(sg);
509 len = sg_dma_len(sg);
510
511 /*
512 * The SDHCI specification states that ADMA
513 * addresses must be 32-bit aligned. If they
514 * aren't, then we use a bounce buffer for
515 * the (up to three) bytes that screw up the
516 * alignment.
517 */
518 offset = (4 - (addr & 0x3)) & 0x3;
519 if (offset) {
520 if (data->flags & MMC_DATA_WRITE) {
521 buffer = sdhci_kmap_atomic(sg, &flags);
6cefd05f 522 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3));
2134a922
PO		 523 memcpy(align, buffer, offset);
524 sdhci_kunmap_atomic(buffer, &flags);
525 }
526
118cd17d
BD		 527 /* tran, valid */
528 sdhci_set_adma_desc(desc, align_addr, offset, 0x21);
2134a922
PO		 529
530 BUG_ON(offset > 65536);
531
2134a922
PO		 532 align += 4;
533 align_addr += 4;
534
535 desc += 8;
536
537 addr += offset;
538 len -= offset;
539 }
540
2134a922
PO		 541 BUG_ON(len > 65536);
542
118cd17d
BD		 543 /* tran, valid */
544 sdhci_set_adma_desc(desc, addr, len, 0x21);
2134a922
PO		 545 desc += 8;
546
547 /*
548 * If this triggers then we have a calculation bug
549 * somewhere. :/
550 */
d1e49f77 551 WARN_ON((desc - host->adma_desc) > ADMA_SIZE);
2134a922
PO		 552 }
553
70764a90
TA		 554 if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) {
555 /*
556 * Mark the last descriptor as the terminating descriptor
557 */
558 if (desc != host->adma_desc) {
559 desc -= 8;
560 desc[0] |= 0x2; /* end */
561 }
562 } else {
563 /*
564 * Add a terminating entry.
565 */
2134a922 566
70764a90
TA		 567 /* nop, end, valid */
568 sdhci_set_adma_desc(desc, 0, 0, 0x3);
569 }
2134a922
PO		 570
571 /*
572 * Resync align buffer as we might have changed it.
573 */
574 if (data->flags & MMC_DATA_WRITE) {
575 dma_sync_single_for_device(mmc_dev(host->mmc),
576 host->align_addr, 128 * 4, direction);
577 }
578
8f1934ce
PO		 579 return 0;
580
8f1934ce
PO		 581unmap_align:
582 dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
583 128 * 4, direction);
584fail:
585 return -EINVAL;
2134a922
PO		 586}
587
588static void sdhci_adma_table_post(struct sdhci_host *host,
589 struct mmc_data *data)
590{
591 int direction;
592
593 struct scatterlist *sg;
594 int i, size;
595 u8 *align;
596 char *buffer;
597 unsigned long flags;
de0b65a7 598 bool has_unaligned;
2134a922
PO		 599
600 if (data->flags & MMC_DATA_READ)
601 direction = DMA_FROM_DEVICE;
602 else
603 direction = DMA_TO_DEVICE;
604
2134a922
PO		 605 dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
606 128 * 4, direction);
607
de0b65a7
RK		 608 /* Do a quick scan of the SG list for any unaligned mappings */
609 has_unaligned = false;
610 for_each_sg(data->sg, sg, host->sg_count, i)
611 if (sg_dma_address(sg) & 3) {
612 has_unaligned = true;
613 break;
614 }
615
616 if (has_unaligned && data->flags & MMC_DATA_READ) {
2134a922
PO		 617 dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
618 data->sg_len, direction);
619
620 align = host->align_buffer;
621
622 for_each_sg(data->sg, sg, host->sg_count, i) {
623 if (sg_dma_address(sg) & 0x3) {
624 size = 4 - (sg_dma_address(sg) & 0x3);
625
626 buffer = sdhci_kmap_atomic(sg, &flags);
6cefd05f 627 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3));
2134a922
PO		 628 memcpy(buffer, align, size);
629 sdhci_kunmap_atomic(buffer, &flags);
630
631 align += 4;
632 }
633 }
634 }
635
636 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
637 data->sg_len, direction);
638}
639
a3c7778f 640static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd)
d129bceb 641{
1c8cde92 642 u8 count;
a3c7778f 643 struct mmc_data *data = cmd->data;
1c8cde92 644 unsigned target_timeout, current_timeout;
d129bceb 645
ee53ab5d
PO		 646 /*
647 * If the host controller provides us with an incorrect timeout
648 * value, just skip the check and use 0xE. The hardware may take
649 * longer to time out, but that's much better than having a too-short
650 * timeout value.
651 */
11a2f1b7 652 if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL)
ee53ab5d 653 return 0xE;
e538fbe8 654
a3c7778f 655 /* Unspecified timeout, assume max */
1d4d7744 656 if (!data && !cmd->busy_timeout)
a3c7778f 657 return 0xE;
d129bceb 658
a3c7778f
AW		 659 /* timeout in us */
660 if (!data)
1d4d7744 661 target_timeout = cmd->busy_timeout * 1000;
78a2ca27
AS		 662 else {
663 target_timeout = data->timeout_ns / 1000;
664 if (host->clock)
665 target_timeout += data->timeout_clks / host->clock;
666 }
81b39802 667
1c8cde92
PO		 668 /*
669 * Figure out needed cycles.
670 * We do this in steps in order to fit inside a 32 bit int.
671 * The first step is the minimum timeout, which will have a
672 * minimum resolution of 6 bits:
673 * (1) 2^13*1000 > 2^22,
674 * (2) host->timeout_clk < 2^16
675 * =>
676 * (1) / (2) > 2^6
677 */
678 count = 0;
679 current_timeout = (1 << 13) * 1000 / host->timeout_clk;
680 while (current_timeout < target_timeout) {
681 count++;
682 current_timeout <<= 1;
683 if (count >= 0xF)
684 break;
685 }
686
687 if (count >= 0xF) {
09eeff52
CB		 688 DBG("%s: Too large timeout 0x%x requested for CMD%d!\n",
689 mmc_hostname(host->mmc), count, cmd->opcode);
1c8cde92
PO		 690 count = 0xE;
691 }
692
ee53ab5d
PO		 693 return count;
694}
695
6aa943ab
AV		 696static void sdhci_set_transfer_irqs(struct sdhci_host *host)
697{
698 u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL;
699 u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR;
700
701 if (host->flags & SDHCI_REQ_USE_DMA)
b537f94c 702 host->ier = (host->ier & ~pio_irqs) | dma_irqs;
6aa943ab 703 else
b537f94c
RK		 704 host->ier = (host->ier & ~dma_irqs) | pio_irqs;
705
706 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
707 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
6aa943ab
AV		 708}
709
b45e668a 710static void sdhci_set_timeout(struct sdhci_host *host, struct mmc_command *cmd)
ee53ab5d
PO		 711{
712 u8 count;
b45e668a
AD		 713
714 if (host->ops->set_timeout) {
715 host->ops->set_timeout(host, cmd);
716 } else {
717 count = sdhci_calc_timeout(host, cmd);
718 sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
719 }
720}
721
722static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd)
723{
2134a922 724 u8 ctrl;
a3c7778f 725 struct mmc_data *data = cmd->data;
8f1934ce 726 int ret;
ee53ab5d
PO		 727
728 WARN_ON(host->data);
729
b45e668a
AD		 730 if (data || (cmd->flags & MMC_RSP_BUSY))
731 sdhci_set_timeout(host, cmd);
a3c7778f
AW		 732
733 if (!data)
ee53ab5d
PO		 734 return;
735
736 /* Sanity checks */
737 BUG_ON(data->blksz * data->blocks > 524288);
738 BUG_ON(data->blksz > host->mmc->max_blk_size);
739 BUG_ON(data->blocks > 65535);
740
741 host->data = data;
742 host->data_early = 0;
f6a03cbf 743 host->data->bytes_xfered = 0;
ee53ab5d 744
a13abc7b 745 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))
c9fddbc4
PO		 746 host->flags |= SDHCI_REQ_USE_DMA;
747
2134a922
PO		 748 /*
749 * FIXME: This doesn't account for merging when mapping the
750 * scatterlist.
751 */
752 if (host->flags & SDHCI_REQ_USE_DMA) {
753 int broken, i;
754 struct scatterlist *sg;
755
756 broken = 0;
757 if (host->flags & SDHCI_USE_ADMA) {
758 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
759 broken = 1;
760 } else {
761 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE)
762 broken = 1;
763 }
764
765 if (unlikely(broken)) {
766 for_each_sg(data->sg, sg, data->sg_len, i) {
767 if (sg->length & 0x3) {
768 DBG("Reverting to PIO because of "
769 "transfer size (%d)\n",
770 sg->length);
771 host->flags &= ~SDHCI_REQ_USE_DMA;
772 break;
773 }
774 }
775 }
c9fddbc4
PO		 776 }
777
778 /*
779 * The assumption here being that alignment is the same after
780 * translation to device address space.
781 */
2134a922
PO		 782 if (host->flags & SDHCI_REQ_USE_DMA) {
783 int broken, i;
784 struct scatterlist *sg;
785
786 broken = 0;
787 if (host->flags & SDHCI_USE_ADMA) {
788 /*
789 * As we use 3 byte chunks to work around
790 * alignment problems, we need to check this
791 * quirk.
792 */
793 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
794 broken = 1;
795 } else {
796 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR)
797 broken = 1;
798 }
799
800 if (unlikely(broken)) {
801 for_each_sg(data->sg, sg, data->sg_len, i) {
802 if (sg->offset & 0x3) {
803 DBG("Reverting to PIO because of "
804 "bad alignment\n");
805 host->flags &= ~SDHCI_REQ_USE_DMA;
806 break;
807 }
808 }
809 }
810 }
811
8f1934ce
PO		 812 if (host->flags & SDHCI_REQ_USE_DMA) {
813 if (host->flags & SDHCI_USE_ADMA) {
814 ret = sdhci_adma_table_pre(host, data);
815 if (ret) {
816 /*
817 * This only happens when someone fed
818 * us an invalid request.
819 */
820 WARN_ON(1);
ebd6d357 821 host->flags &= ~SDHCI_REQ_USE_DMA;
8f1934ce 822 } else {
4e4141a5
AV		 823 sdhci_writel(host, host->adma_addr,
824 SDHCI_ADMA_ADDRESS);
8f1934ce
PO		 825 }
826 } else {
c8b3e02e 827 int sg_cnt;
8f1934ce 828
c8b3e02e 829 sg_cnt = dma_map_sg(mmc_dev(host->mmc),
8f1934ce
PO		 830 data->sg, data->sg_len,
831 (data->flags & MMC_DATA_READ) ?
832 DMA_FROM_DEVICE :
833 DMA_TO_DEVICE);
c8b3e02e 834 if (sg_cnt == 0) {
8f1934ce
PO		 835 /*
836 * This only happens when someone fed
837 * us an invalid request.
838 */
839 WARN_ON(1);
ebd6d357 840 host->flags &= ~SDHCI_REQ_USE_DMA;
8f1934ce 841 } else {
719a61b4 842 WARN_ON(sg_cnt != 1);
4e4141a5
AV		 843 sdhci_writel(host, sg_dma_address(data->sg),
844 SDHCI_DMA_ADDRESS);
8f1934ce
PO		 845 }
846 }
847 }
848
2134a922
PO		 849 /*
850 * Always adjust the DMA selection as some controllers
851 * (e.g. JMicron) can't do PIO properly when the selection
852 * is ADMA.
853 */
854 if (host->version >= SDHCI_SPEC_200) {
4e4141a5 855 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
2134a922
PO		 856 ctrl &= ~SDHCI_CTRL_DMA_MASK;
857 if ((host->flags & SDHCI_REQ_USE_DMA) &&
858 (host->flags & SDHCI_USE_ADMA))
859 ctrl |= SDHCI_CTRL_ADMA32;
860 else
861 ctrl |= SDHCI_CTRL_SDMA;
4e4141a5 862 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
c9fddbc4
PO		 863 }
864
8f1934ce 865 if (!(host->flags & SDHCI_REQ_USE_DMA)) {
da60a91d
SAS		 866 int flags;
867
868 flags = SG_MITER_ATOMIC;
869 if (host->data->flags & MMC_DATA_READ)
870 flags |= SG_MITER_TO_SG;
871 else
872 flags |= SG_MITER_FROM_SG;
873 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
7659150c 874 host->blocks = data->blocks;
d129bceb 875 }
c7fa9963 876
6aa943ab
AV		 877 sdhci_set_transfer_irqs(host);
878
f6a03cbf
MV		 879 /* Set the DMA boundary value and block size */
880 sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
881 data->blksz), SDHCI_BLOCK_SIZE);
4e4141a5 882 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
c7fa9963
PO		 883}
884
885static void sdhci_set_transfer_mode(struct sdhci_host *host,
e89d456f 886 struct mmc_command *cmd)
c7fa9963
PO		 887{
888 u16 mode;
e89d456f 889 struct mmc_data *data = cmd->data;
c7fa9963 890
2b558c13
DA		 891 if (data == NULL) {
892 /* clear Auto CMD settings for no data CMDs */
893 mode = sdhci_readw(host, SDHCI_TRANSFER_MODE);
894 sdhci_writew(host, mode & ~(SDHCI_TRNS_AUTO_CMD12 |
895 SDHCI_TRNS_AUTO_CMD23), SDHCI_TRANSFER_MODE);
c7fa9963 896 return;
2b558c13 897 }
c7fa9963 898
e538fbe8
PO		 899 WARN_ON(!host->data);
900
c7fa9963 901 mode = SDHCI_TRNS_BLK_CNT_EN;
e89d456f
AW		 902 if (mmc_op_multi(cmd->opcode) || data->blocks > 1) {
903 mode |= SDHCI_TRNS_MULTI;
904 /*
905 * If we are sending CMD23, CMD12 never gets sent
906 * on successful completion (so no Auto-CMD12).
907 */
908 if (!host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD12))
909 mode |= SDHCI_TRNS_AUTO_CMD12;
8edf6371
AW		 910 else if (host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) {
911 mode |= SDHCI_TRNS_AUTO_CMD23;
912 sdhci_writel(host, host->mrq->sbc->arg, SDHCI_ARGUMENT2);
913 }
c4512f79 914 }
8edf6371 915
c7fa9963
PO		 916 if (data->flags & MMC_DATA_READ)
917 mode |= SDHCI_TRNS_READ;
c9fddbc4 918 if (host->flags & SDHCI_REQ_USE_DMA)
c7fa9963
PO		 919 mode |= SDHCI_TRNS_DMA;
920
4e4141a5 921 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
d129bceb
PO		 922}
923
924static void sdhci_finish_data(struct sdhci_host *host)
925{
926 struct mmc_data *data;
d129bceb
PO		 927
928 BUG_ON(!host->data);
929
930 data = host->data;
931 host->data = NULL;
932
c9fddbc4 933 if (host->flags & SDHCI_REQ_USE_DMA) {
2134a922
PO		 934 if (host->flags & SDHCI_USE_ADMA)
935 sdhci_adma_table_post(host, data);
936 else {
937 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
938 data->sg_len, (data->flags & MMC_DATA_READ) ?
939 DMA_FROM_DEVICE : DMA_TO_DEVICE);
940 }
d129bceb
PO		 941 }
942
943 /*
c9b74c5b
PO		 944 * The specification states that the block count register must
945 * be updated, but it does not specify at what point in the
946 * data flow. That makes the register entirely useless to read
947 * back so we have to assume that nothing made it to the card
948 * in the event of an error.
d129bceb 949 */
c9b74c5b
PO		 950 if (data->error)
951 data->bytes_xfered = 0;
d129bceb 952 else
c9b74c5b 953 data->bytes_xfered = data->blksz * data->blocks;
d129bceb 954
e89d456f
AW		 955 /*
956 * Need to send CMD12 if -
957 * a) open-ended multiblock transfer (no CMD23)
958 * b) error in multiblock transfer
959 */
960 if (data->stop &&
961 (data->error ||
962 !host->mrq->sbc)) {
963
d129bceb
PO		 964 /*
965 * The controller needs a reset of internal state machines
966 * upon error conditions.
967 */
17b0429d 968 if (data->error) {
03231f9b
RK		 969 sdhci_do_reset(host, SDHCI_RESET_CMD);
970 sdhci_do_reset(host, SDHCI_RESET_DATA);
d129bceb
PO		 971 }
972
973 sdhci_send_command(host, data->stop);
974 } else
975 tasklet_schedule(&host->finish_tasklet);
976}
977
c0e55129 978void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
d129bceb
PO		 979{
980 int flags;
fd2208d7 981 u32 mask;
7cb2c76f 982 unsigned long timeout;
d129bceb
PO		 983
984 WARN_ON(host->cmd);
985
d129bceb 986 /* Wait max 10 ms */
7cb2c76f 987 timeout = 10;
fd2208d7
PO		 988
989 mask = SDHCI_CMD_INHIBIT;
990 if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
991 mask |= SDHCI_DATA_INHIBIT;
992
993 /* We shouldn't wait for data inihibit for stop commands, even
994 though they might use busy signaling */
995 if (host->mrq->data && (cmd == host->mrq->data->stop))
996 mask &= ~SDHCI_DATA_INHIBIT;
997
4e4141a5 998 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
7cb2c76f 999 if (timeout == 0) {
a3c76eb9 1000 pr_err("%s: Controller never released "
acf1da45 1001 "inhibit bit(s).\n", mmc_hostname(host->mmc));
d129bceb 1002 sdhci_dumpregs(host);
17b0429d 1003 cmd->error = -EIO;
d129bceb
PO		 1004 tasklet_schedule(&host->finish_tasklet);
1005 return;
1006 }
7cb2c76f
PO		 1007 timeout--;
1008 mdelay(1);
1009 }
d129bceb 1010
3e1a6892 1011 timeout = jiffies;
1d4d7744
UH		 1012 if (!cmd->data && cmd->busy_timeout > 9000)
1013 timeout += DIV_ROUND_UP(cmd->busy_timeout, 1000) * HZ + HZ;
3e1a6892
AH		 1014 else
1015 timeout += 10 * HZ;
1016 mod_timer(&host->timer, timeout);
d129bceb
PO		 1017
1018 host->cmd = cmd;
e99783a4 1019 host->busy_handle = 0;
d129bceb 1020
a3c7778f 1021 sdhci_prepare_data(host, cmd);
d129bceb 1022
4e4141a5 1023 sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT);
d129bceb 1024
e89d456f 1025 sdhci_set_transfer_mode(host, cmd);
c7fa9963 1026
d129bceb 1027 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
a3c76eb9 1028 pr_err("%s: Unsupported response type!\n",
d129bceb 1029 mmc_hostname(host->mmc));
17b0429d 1030 cmd->error = -EINVAL;
d129bceb
PO		 1031 tasklet_schedule(&host->finish_tasklet);
1032 return;
1033 }
1034
1035 if (!(cmd->flags & MMC_RSP_PRESENT))
1036 flags = SDHCI_CMD_RESP_NONE;
1037 else if (cmd->flags & MMC_RSP_136)
1038 flags = SDHCI_CMD_RESP_LONG;
1039 else if (cmd->flags & MMC_RSP_BUSY)
1040 flags = SDHCI_CMD_RESP_SHORT_BUSY;
1041 else
1042 flags = SDHCI_CMD_RESP_SHORT;
1043
1044 if (cmd->flags & MMC_RSP_CRC)
1045 flags |= SDHCI_CMD_CRC;
1046 if (cmd->flags & MMC_RSP_OPCODE)
1047 flags |= SDHCI_CMD_INDEX;
b513ea25
AN		 1048
1049 /* CMD19 is special in that the Data Present Select should be set */
069c9f14
G		 1050 if (cmd->data || cmd->opcode == MMC_SEND_TUNING_BLOCK ||
1051 cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200)
d129bceb
PO		 1052 flags |= SDHCI_CMD_DATA;
1053
4e4141a5 1054 sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND);
d129bceb 1055}
c0e55129 1056EXPORT_SYMBOL_GPL(sdhci_send_command);
d129bceb
PO		 1057
1058static void sdhci_finish_command(struct sdhci_host *host)
1059{
1060 int i;
1061
1062 BUG_ON(host->cmd == NULL);
1063
1064 if (host->cmd->flags & MMC_RSP_PRESENT) {
1065 if (host->cmd->flags & MMC_RSP_136) {
1066 /* CRC is stripped so we need to do some shifting. */
1067 for (i = 0;i < 4;i++) {
4e4141a5 1068 host->cmd->resp[i] = sdhci_readl(host,
d129bceb
PO		 1069 SDHCI_RESPONSE + (3-i)*4) << 8;
1070 if (i != 3)
1071 host->cmd->resp[i] |=
4e4141a5 1072 sdhci_readb(host,
d129bceb
PO		 1073 SDHCI_RESPONSE + (3-i)*4-1);
1074 }
1075 } else {
4e4141a5 1076 host->cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE);
d129bceb
PO		 1077 }
1078 }
1079
17b0429d 1080 host->cmd->error = 0;
d129bceb 1081
e89d456f
AW		 1082 /* Finished CMD23, now send actual command. */
1083 if (host->cmd == host->mrq->sbc) {
1084 host->cmd = NULL;
1085 sdhci_send_command(host, host->mrq->cmd);
1086 } else {
e538fbe8 1087
e89d456f
AW		 1088 /* Processed actual command. */
1089 if (host->data && host->data_early)
1090 sdhci_finish_data(host);
d129bceb 1091
e89d456f
AW		 1092 if (!host->cmd->data)
1093 tasklet_schedule(&host->finish_tasklet);
1094
1095 host->cmd = NULL;
1096 }
d129bceb
PO		 1097}
1098
52983382
KL		 1099static u16 sdhci_get_preset_value(struct sdhci_host *host)
1100{
d975f121 1101 u16 preset = 0;
52983382 1102
d975f121
RK		 1103 switch (host->timing) {
1104 case MMC_TIMING_UHS_SDR12:
52983382
KL		 1105 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1106 break;
d975f121 1107 case MMC_TIMING_UHS_SDR25:
52983382
KL		 1108 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR25);
1109 break;
d975f121 1110 case MMC_TIMING_UHS_SDR50:
52983382
KL		 1111 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR50);
1112 break;
d975f121
RK		 1113 case MMC_TIMING_UHS_SDR104:
1114 case MMC_TIMING_MMC_HS200:
52983382
KL		 1115 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR104);
1116 break;
d975f121 1117 case MMC_TIMING_UHS_DDR50:
52983382
KL		 1118 preset = sdhci_readw(host, SDHCI_PRESET_FOR_DDR50);
1119 break;
1120 default:
1121 pr_warn("%s: Invalid UHS-I mode selected\n",
1122 mmc_hostname(host->mmc));
1123 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1124 break;
1125 }
1126 return preset;
1127}
1128
1771059c 1129void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
d129bceb 1130{
c3ed3877 1131 int div = 0; /* Initialized for compiler warning */
df16219f 1132 int real_div = div, clk_mul = 1;
c3ed3877 1133 u16 clk = 0;
7cb2c76f 1134 unsigned long timeout;
d129bceb 1135
1650d0c7
RK		 1136 host->mmc->actual_clock = 0;
1137
4e4141a5 1138 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
d129bceb
PO		 1139
1140 if (clock == 0)
373073ef 1141 return;
d129bceb 1142
85105c53 1143 if (host->version >= SDHCI_SPEC_300) {
da91a8f9 1144 if (host->preset_enabled) {
52983382
KL		 1145 u16 pre_val;
1146
1147 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1148 pre_val = sdhci_get_preset_value(host);
1149 div = (pre_val & SDHCI_PRESET_SDCLK_FREQ_MASK)
1150 >> SDHCI_PRESET_SDCLK_FREQ_SHIFT;
1151 if (host->clk_mul &&
1152 (pre_val & SDHCI_PRESET_CLKGEN_SEL_MASK)) {
1153 clk = SDHCI_PROG_CLOCK_MODE;
1154 real_div = div + 1;
1155 clk_mul = host->clk_mul;
1156 } else {
1157 real_div = max_t(int, 1, div << 1);
1158 }
1159 goto clock_set;
1160 }
1161
c3ed3877
AN		 1162 /*
1163 * Check if the Host Controller supports Programmable Clock
1164 * Mode.
1165 */
1166 if (host->clk_mul) {
52983382
KL		 1167 for (div = 1; div <= 1024; div++) {
1168 if ((host->max_clk * host->clk_mul / div)
1169 <= clock)
1170 break;
1171 }
c3ed3877 1172 /*
52983382
KL		 1173 * Set Programmable Clock Mode in the Clock
1174 * Control register.
c3ed3877 1175 */
52983382
KL		 1176 clk = SDHCI_PROG_CLOCK_MODE;
1177 real_div = div;
1178 clk_mul = host->clk_mul;
1179 div--;
c3ed3877
AN		 1180 } else {
1181 /* Version 3.00 divisors must be a multiple of 2. */
1182 if (host->max_clk <= clock)
1183 div = 1;
1184 else {
1185 for (div = 2; div < SDHCI_MAX_DIV_SPEC_300;
1186 div += 2) {
1187 if ((host->max_clk / div) <= clock)
1188 break;
1189 }
85105c53 1190 }
df16219f 1191 real_div = div;
c3ed3877 1192 div >>= 1;
85105c53
ZG		 1193 }
1194 } else {
1195 /* Version 2.00 divisors must be a power of 2. */
0397526d 1196 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
85105c53
ZG		 1197 if ((host->max_clk / div) <= clock)
1198 break;
1199 }
df16219f 1200 real_div = div;
c3ed3877 1201 div >>= 1;
d129bceb 1202 }
d129bceb 1203
52983382 1204clock_set:
03d6f5ff 1205 if (real_div)
df16219f 1206 host->mmc->actual_clock = (host->max_clk * clk_mul) / real_div;
c3ed3877 1207 clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
85105c53
ZG		 1208 clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
1209 << SDHCI_DIVIDER_HI_SHIFT;
d129bceb 1210 clk |= SDHCI_CLOCK_INT_EN;
4e4141a5 1211 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
d129bceb 1212
27f6cb16
CB		 1213 /* Wait max 20 ms */
1214 timeout = 20;
4e4141a5 1215 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
7cb2c76f
PO		 1216 & SDHCI_CLOCK_INT_STABLE)) {
1217 if (timeout == 0) {
a3c76eb9 1218 pr_err("%s: Internal clock never "
acf1da45 1219 "stabilised.\n", mmc_hostname(host->mmc));
d129bceb
PO		 1220 sdhci_dumpregs(host);
1221 return;
1222 }
7cb2c76f
PO		 1223 timeout--;
1224 mdelay(1);
1225 }
d129bceb
PO		 1226
1227 clk |= SDHCI_CLOCK_CARD_EN;
4e4141a5 1228 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
d129bceb 1229}
1771059c 1230EXPORT_SYMBOL_GPL(sdhci_set_clock);
d129bceb 1231
24fbb3ca
RK		 1232static void sdhci_set_power(struct sdhci_host *host, unsigned char mode,
1233 unsigned short vdd)
146ad66e 1234{
3a48edc4 1235 struct mmc_host *mmc = host->mmc;
8364248a 1236 u8 pwr = 0;
146ad66e 1237
52221610
TK		 1238 if (!IS_ERR(mmc->supply.vmmc)) {
1239 spin_unlock_irq(&host->lock);
4e743f1f 1240 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd);
52221610
TK		 1241 spin_lock_irq(&host->lock);
1242 return;
1243 }
1244
24fbb3ca
RK		 1245 if (mode != MMC_POWER_OFF) {
1246 switch (1 << vdd) {
ae628903
PO		 1247 case MMC_VDD_165_195:
1248 pwr = SDHCI_POWER_180;
1249 break;
1250 case MMC_VDD_29_30:
1251 case MMC_VDD_30_31:
1252 pwr = SDHCI_POWER_300;
1253 break;
1254 case MMC_VDD_32_33:
1255 case MMC_VDD_33_34:
1256 pwr = SDHCI_POWER_330;
1257 break;
1258 default:
1259 BUG();
1260 }
1261 }
1262
1263 if (host->pwr == pwr)
e921a8b6 1264 return;
146ad66e 1265
ae628903
PO		 1266 host->pwr = pwr;
1267
1268 if (pwr == 0) {
4e4141a5 1269 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
f0710a55
AH		 1270 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
1271 sdhci_runtime_pm_bus_off(host);
24fbb3ca 1272 vdd = 0;
e921a8b6
RK		 1273 } else {
1274 /*
1275 * Spec says that we should clear the power reg before setting
1276 * a new value. Some controllers don't seem to like this though.
1277 */
1278 if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
1279 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
146ad66e 1280
e921a8b6
RK		 1281 /*
1282 * At least the Marvell CaFe chip gets confused if we set the
1283 * voltage and set turn on power at the same time, so set the
1284 * voltage first.
1285 */
1286 if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
1287 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
e08c1694 1288
e921a8b6 1289 pwr |= SDHCI_POWER_ON;
146ad66e 1290
e921a8b6 1291 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
557b0697 1292
e921a8b6
RK		 1293 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
1294 sdhci_runtime_pm_bus_on(host);
f0710a55 1295
e921a8b6
RK		 1296 /*
1297 * Some controllers need an extra 10ms delay of 10ms before
1298 * they can apply clock after applying power
1299 */
1300 if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER)
1301 mdelay(10);
1302 }
146ad66e
PO		 1303}
1304
d129bceb
PO		 1305/*****************************************************************************\
1306 * *
1307 * MMC callbacks *
1308 * *
1309\*****************************************************************************/
1310
1311static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1312{
1313 struct sdhci_host *host;
505a8680 1314 int present;
d129bceb 1315 unsigned long flags;
473b095a 1316 u32 tuning_opcode;
d129bceb
PO		 1317
1318 host = mmc_priv(mmc);
1319
66fd8ad5
AH		 1320 sdhci_runtime_pm_get(host);
1321
d129bceb
PO		 1322 spin_lock_irqsave(&host->lock, flags);
1323
1324 WARN_ON(host->mrq != NULL);
1325
f9134319 1326#ifndef SDHCI_USE_LEDS_CLASS
d129bceb 1327 sdhci_activate_led(host);
2f730fec 1328#endif
e89d456f
AW		 1329
1330 /*
1331 * Ensure we don't send the STOP for non-SET_BLOCK_COUNTED
1332 * requests if Auto-CMD12 is enabled.
1333 */
1334 if (!mrq->sbc && (host->flags & SDHCI_AUTO_CMD12)) {
c4512f79
JH		 1335 if (mrq->stop) {
1336 mrq->data->stop = NULL;
1337 mrq->stop = NULL;
1338 }
1339 }
d129bceb
PO		 1340
1341 host->mrq = mrq;
1342
505a8680
SG		 1343 /*
1344 * Firstly check card presence from cd-gpio. The return could
1345 * be one of the following possibilities:
1346 * negative: cd-gpio is not available
1347 * zero: cd-gpio is used, and card is removed
1348 * one: cd-gpio is used, and card is present
1349 */
1350 present = mmc_gpio_get_cd(host->mmc);
1351 if (present < 0) {
1352 /* If polling, assume that the card is always present. */
1353 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
1354 present = 1;
1355 else
1356 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
1357 SDHCI_CARD_PRESENT;
bec9d4e5
GL		 1358 }
1359
68d1fb7e 1360 if (!present || host->flags & SDHCI_DEVICE_DEAD) {
17b0429d 1361 host->mrq->cmd->error = -ENOMEDIUM;
d129bceb 1362 tasklet_schedule(&host->finish_tasklet);
cf2b5eea
AN		 1363 } else {
1364 u32 present_state;
1365
1366 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
1367 /*
1368 * Check if the re-tuning timer has already expired and there
1369 * is no on-going data transfer. If so, we need to execute
1370 * tuning procedure before sending command.
1371 */
1372 if ((host->flags & SDHCI_NEEDS_RETUNING) &&
1373 !(present_state & (SDHCI_DOING_WRITE | SDHCI_DOING_READ))) {
14efd957
CB		 1374 if (mmc->card) {
1375 /* eMMC uses cmd21 but sd and sdio use cmd19 */
1376 tuning_opcode =
1377 mmc->card->type == MMC_TYPE_MMC ?
1378 MMC_SEND_TUNING_BLOCK_HS200 :
1379 MMC_SEND_TUNING_BLOCK;
63c21180
CL		 1380
1381 /* Here we need to set the host->mrq to NULL,
1382 * in case the pending finish_tasklet
1383 * finishes it incorrectly.
1384 */
1385 host->mrq = NULL;
1386
14efd957
CB		 1387 spin_unlock_irqrestore(&host->lock, flags);
1388 sdhci_execute_tuning(mmc, tuning_opcode);
1389 spin_lock_irqsave(&host->lock, flags);
1390
1391 /* Restore original mmc_request structure */
1392 host->mrq = mrq;
1393 }
cf2b5eea
AN		 1394 }
1395
8edf6371 1396 if (mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23))
e89d456f
AW		 1397 sdhci_send_command(host, mrq->sbc);
1398 else
1399 sdhci_send_command(host, mrq->cmd);
cf2b5eea 1400 }
d129bceb 1401
5f25a66f 1402 mmiowb();
d129bceb
PO		 1403 spin_unlock_irqrestore(&host->lock, flags);
1404}
1405
2317f56c
RK		 1406void sdhci_set_bus_width(struct sdhci_host *host, int width)
1407{
1408 u8 ctrl;
1409
1410 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1411 if (width == MMC_BUS_WIDTH_8) {
1412 ctrl &= ~SDHCI_CTRL_4BITBUS;
1413 if (host->version >= SDHCI_SPEC_300)
1414 ctrl |= SDHCI_CTRL_8BITBUS;
1415 } else {
1416 if (host->version >= SDHCI_SPEC_300)
1417 ctrl &= ~SDHCI_CTRL_8BITBUS;
1418 if (width == MMC_BUS_WIDTH_4)
1419 ctrl |= SDHCI_CTRL_4BITBUS;
1420 else
1421 ctrl &= ~SDHCI_CTRL_4BITBUS;
1422 }
1423 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1424}
1425EXPORT_SYMBOL_GPL(sdhci_set_bus_width);
1426
96d7b78c
RK		 1427void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing)
1428{
1429 u16 ctrl_2;
1430
1431 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1432 /* Select Bus Speed Mode for host */
1433 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
1434 if ((timing == MMC_TIMING_MMC_HS200) ||
1435 (timing == MMC_TIMING_UHS_SDR104))
1436 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
1437 else if (timing == MMC_TIMING_UHS_SDR12)
1438 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
1439 else if (timing == MMC_TIMING_UHS_SDR25)
1440 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
1441 else if (timing == MMC_TIMING_UHS_SDR50)
1442 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
1443 else if ((timing == MMC_TIMING_UHS_DDR50) ||
1444 (timing == MMC_TIMING_MMC_DDR52))
1445 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
1446 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1447}
1448EXPORT_SYMBOL_GPL(sdhci_set_uhs_signaling);
1449
66fd8ad5 1450static void sdhci_do_set_ios(struct sdhci_host *host, struct mmc_ios *ios)
d129bceb 1451{
d129bceb
PO		 1452 unsigned long flags;
1453 u8 ctrl;
3a48edc4 1454 struct mmc_host *mmc = host->mmc;
d129bceb 1455
d129bceb
PO		 1456 spin_lock_irqsave(&host->lock, flags);
1457
ceb6143b
AH		 1458 if (host->flags & SDHCI_DEVICE_DEAD) {
1459 spin_unlock_irqrestore(&host->lock, flags);
3a48edc4
TK		 1460 if (!IS_ERR(mmc->supply.vmmc) &&
1461 ios->power_mode == MMC_POWER_OFF)
4e743f1f 1462 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
ceb6143b
AH		 1463 return;
1464 }
1e72859e 1465
d129bceb
PO		 1466 /*
1467 * Reset the chip on each power off.
1468 * Should clear out any weird states.
1469 */
1470 if (ios->power_mode == MMC_POWER_OFF) {
4e4141a5 1471 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
7260cf5e 1472 sdhci_reinit(host);
d129bceb
PO		 1473 }
1474
52983382 1475 if (host->version >= SDHCI_SPEC_300 &&
372c4634
DA		 1476 (ios->power_mode == MMC_POWER_UP) &&
1477 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN))
52983382
KL		 1478 sdhci_enable_preset_value(host, false);
1479
373073ef 1480 if (!ios->clock || ios->clock != host->clock) {
1771059c 1481 host->ops->set_clock(host, ios->clock);
373073ef 1482 host->clock = ios->clock;
03d6f5ff
AD		 1483
1484 if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK &&
1485 host->clock) {
1486 host->timeout_clk = host->mmc->actual_clock ?
1487 host->mmc->actual_clock / 1000 :
1488 host->clock / 1000;
1489 host->mmc->max_busy_timeout =
1490 host->ops->get_max_timeout_count ?
1491 host->ops->get_max_timeout_count(host) :
1492 1 << 27;
1493 host->mmc->max_busy_timeout /= host->timeout_clk;
1494 }
373073ef 1495 }
d129bceb 1496
24fbb3ca 1497 sdhci_set_power(host, ios->power_mode, ios->vdd);
d129bceb 1498
643a81ff
PR		 1499 if (host->ops->platform_send_init_74_clocks)
1500 host->ops->platform_send_init_74_clocks(host, ios->power_mode);
1501
2317f56c 1502 host->ops->set_bus_width(host, ios->bus_width);
ae6d6c92 1503
15ec4461 1504 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
cd9277c0 1505
3ab9c8da
PR		 1506 if ((ios->timing == MMC_TIMING_SD_HS ||
1507 ios->timing == MMC_TIMING_MMC_HS)
1508 && !(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT))
cd9277c0
PO		 1509 ctrl |= SDHCI_CTRL_HISPD;
1510 else
1511 ctrl &= ~SDHCI_CTRL_HISPD;
1512
d6d50a15 1513 if (host->version >= SDHCI_SPEC_300) {
49c468fc 1514 u16 clk, ctrl_2;
49c468fc
AN		 1515
1516 /* In case of UHS-I modes, set High Speed Enable */
069c9f14 1517 if ((ios->timing == MMC_TIMING_MMC_HS200) ||
bb8175a8 1518 (ios->timing == MMC_TIMING_MMC_DDR52) ||
069c9f14 1519 (ios->timing == MMC_TIMING_UHS_SDR50) ||
49c468fc
AN		 1520 (ios->timing == MMC_TIMING_UHS_SDR104) ||
1521 (ios->timing == MMC_TIMING_UHS_DDR50) ||
dd8df17f 1522 (ios->timing == MMC_TIMING_UHS_SDR25))
49c468fc 1523 ctrl |= SDHCI_CTRL_HISPD;
d6d50a15 1524
da91a8f9 1525 if (!host->preset_enabled) {
758535c4 1526 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d6d50a15
AN		 1527 /*
1528 * We only need to set Driver Strength if the
1529 * preset value enable is not set.
1530 */
da91a8f9 1531 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
d6d50a15
AN		 1532 ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK;
1533 if (ios->drv_type == MMC_SET_DRIVER_TYPE_A)
1534 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A;
1535 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C)
1536 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C;
1537
1538 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
758535c4
AN		 1539 } else {
1540 /*
1541 * According to SDHC Spec v3.00, if the Preset Value
1542 * Enable in the Host Control 2 register is set, we
1543 * need to reset SD Clock Enable before changing High
1544 * Speed Enable to avoid generating clock gliches.
1545 */
758535c4
AN		 1546
1547 /* Reset SD Clock Enable */
1548 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1549 clk &= ~SDHCI_CLOCK_CARD_EN;
1550 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1551
1552 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1553
1554 /* Re-enable SD Clock */
1771059c 1555 host->ops->set_clock(host, host->clock);
d6d50a15 1556 }
49c468fc 1557
49c468fc
AN		 1558 /* Reset SD Clock Enable */
1559 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1560 clk &= ~SDHCI_CLOCK_CARD_EN;
1561 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1562
96d7b78c 1563 host->ops->set_uhs_signaling(host, ios->timing);
d975f121 1564 host->timing = ios->timing;
49c468fc 1565
52983382
KL		 1566 if (!(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN) &&
1567 ((ios->timing == MMC_TIMING_UHS_SDR12) ||
1568 (ios->timing == MMC_TIMING_UHS_SDR25) ||
1569 (ios->timing == MMC_TIMING_UHS_SDR50) ||
1570 (ios->timing == MMC_TIMING_UHS_SDR104) ||
1571 (ios->timing == MMC_TIMING_UHS_DDR50))) {
1572 u16 preset;
1573
1574 sdhci_enable_preset_value(host, true);
1575 preset = sdhci_get_preset_value(host);
1576 ios->drv_type = (preset & SDHCI_PRESET_DRV_MASK)
1577 >> SDHCI_PRESET_DRV_SHIFT;
1578 }
1579
49c468fc 1580 /* Re-enable SD Clock */
1771059c 1581 host->ops->set_clock(host, host->clock);
758535c4
AN		 1582 } else
1583 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d6d50a15 1584
b8352260
LD		 1585 /*
1586 * Some (ENE) controllers go apeshit on some ios operation,
1587 * signalling timeout and CRC errors even on CMD0. Resetting
1588 * it on each ios seems to solve the problem.
1589 */
b8c86fc5 1590 if(host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
03231f9b 1591 sdhci_do_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
b8352260 1592
5f25a66f 1593 mmiowb();
d129bceb
PO		 1594 spin_unlock_irqrestore(&host->lock, flags);
1595}
1596
66fd8ad5
AH		 1597static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1598{
1599 struct sdhci_host *host = mmc_priv(mmc);
1600
1601 sdhci_runtime_pm_get(host);
1602 sdhci_do_set_ios(host, ios);
1603 sdhci_runtime_pm_put(host);
1604}
1605
94144a46
KL		 1606static int sdhci_do_get_cd(struct sdhci_host *host)
1607{
1608 int gpio_cd = mmc_gpio_get_cd(host->mmc);
1609
1610 if (host->flags & SDHCI_DEVICE_DEAD)
1611 return 0;
1612
1613 /* If polling/nonremovable, assume that the card is always present. */
1614 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) ||
1615 (host->mmc->caps & MMC_CAP_NONREMOVABLE))
1616 return 1;
1617
1618 /* Try slot gpio detect */
1619 if (!IS_ERR_VALUE(gpio_cd))
1620 return !!gpio_cd;
1621
1622 /* Host native card detect */
1623 return !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
1624}
1625
1626static int sdhci_get_cd(struct mmc_host *mmc)
1627{
1628 struct sdhci_host *host = mmc_priv(mmc);
1629 int ret;
1630
1631 sdhci_runtime_pm_get(host);
1632 ret = sdhci_do_get_cd(host);
1633 sdhci_runtime_pm_put(host);
1634 return ret;
1635}
1636
66fd8ad5 1637static int sdhci_check_ro(struct sdhci_host *host)
d129bceb 1638{
d129bceb 1639 unsigned long flags;
2dfb579c 1640 int is_readonly;
d129bceb 1641
d129bceb
PO		 1642 spin_lock_irqsave(&host->lock, flags);
1643
1e72859e 1644 if (host->flags & SDHCI_DEVICE_DEAD)
2dfb579c
WS		 1645 is_readonly = 0;
1646 else if (host->ops->get_ro)
1647 is_readonly = host->ops->get_ro(host);
1e72859e 1648 else
2dfb579c
WS		 1649 is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE)
1650 & SDHCI_WRITE_PROTECT);
d129bceb
PO		 1651
1652 spin_unlock_irqrestore(&host->lock, flags);
1653
2dfb579c
WS		 1654 /* This quirk needs to be replaced by a callback-function later */
1655 return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ?
1656 !is_readonly : is_readonly;
d129bceb
PO		 1657}
1658
82b0e23a
TI		 1659#define SAMPLE_COUNT 5
1660
66fd8ad5 1661static int sdhci_do_get_ro(struct sdhci_host *host)
82b0e23a 1662{
82b0e23a
TI		 1663 int i, ro_count;
1664
82b0e23a 1665 if (!(host->quirks & SDHCI_QUIRK_UNSTABLE_RO_DETECT))
66fd8ad5 1666 return sdhci_check_ro(host);
82b0e23a
TI		 1667
1668 ro_count = 0;
1669 for (i = 0; i < SAMPLE_COUNT; i++) {
66fd8ad5 1670 if (sdhci_check_ro(host)) {
82b0e23a
TI		 1671 if (++ro_count > SAMPLE_COUNT / 2)
1672 return 1;
1673 }
1674 msleep(30);
1675 }
1676 return 0;
1677}
1678
20758b66
AH		 1679static void sdhci_hw_reset(struct mmc_host *mmc)
1680{
1681 struct sdhci_host *host = mmc_priv(mmc);
1682
1683 if (host->ops && host->ops->hw_reset)
1684 host->ops->hw_reset(host);
1685}
1686
66fd8ad5 1687static int sdhci_get_ro(struct mmc_host *mmc)
f75979b7 1688{
66fd8ad5
AH		 1689 struct sdhci_host *host = mmc_priv(mmc);
1690 int ret;
f75979b7 1691
66fd8ad5
AH		 1692 sdhci_runtime_pm_get(host);
1693 ret = sdhci_do_get_ro(host);
1694 sdhci_runtime_pm_put(host);
1695 return ret;
1696}
f75979b7 1697
66fd8ad5
AH		 1698static void sdhci_enable_sdio_irq_nolock(struct sdhci_host *host, int enable)
1699{
be138554 1700 if (!(host->flags & SDHCI_DEVICE_DEAD)) {
ef104333 1701 if (enable)
b537f94c 1702 host->ier |= SDHCI_INT_CARD_INT;
ef104333 1703 else
b537f94c
RK		 1704 host->ier &= ~SDHCI_INT_CARD_INT;
1705
1706 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
1707 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
ef104333
RK		 1708 mmiowb();
1709 }
66fd8ad5
AH		 1710}
1711
1712static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1713{
1714 struct sdhci_host *host = mmc_priv(mmc);
1715 unsigned long flags;
f75979b7 1716
ef104333
RK		 1717 sdhci_runtime_pm_get(host);
1718
66fd8ad5 1719 spin_lock_irqsave(&host->lock, flags);
ef104333
RK		 1720 if (enable)
1721 host->flags |= SDHCI_SDIO_IRQ_ENABLED;
1722 else
1723 host->flags &= ~SDHCI_SDIO_IRQ_ENABLED;
1724
66fd8ad5 1725 sdhci_enable_sdio_irq_nolock(host, enable);
f75979b7 1726 spin_unlock_irqrestore(&host->lock, flags);
ef104333
RK		 1727
1728 sdhci_runtime_pm_put(host);
f75979b7
PO		 1729}
1730
20b92a30 1731static int sdhci_do_start_signal_voltage_switch(struct sdhci_host *host,
21f5998f 1732 struct mmc_ios *ios)
f2119df6 1733{
3a48edc4 1734 struct mmc_host *mmc = host->mmc;
20b92a30 1735 u16 ctrl;
6231f3de 1736 int ret;
f2119df6 1737
20b92a30
KL		 1738 /*
1739 * Signal Voltage Switching is only applicable for Host Controllers
1740 * v3.00 and above.
1741 */
1742 if (host->version < SDHCI_SPEC_300)
1743 return 0;
6231f3de 1744
f2119df6 1745 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
f2119df6 1746
21f5998f 1747 switch (ios->signal_voltage) {
20b92a30
KL		 1748 case MMC_SIGNAL_VOLTAGE_330:
1749 /* Set 1.8V Signal Enable in the Host Control2 register to 0 */
1750 ctrl &= ~SDHCI_CTRL_VDD_180;
1751 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
f2119df6 1752
3a48edc4
TK		 1753 if (!IS_ERR(mmc->supply.vqmmc)) {
1754 ret = regulator_set_voltage(mmc->supply.vqmmc, 2700000,
1755 3600000);
20b92a30
KL		 1756 if (ret) {
1757 pr_warning("%s: Switching to 3.3V signalling voltage "
4e743f1f 1758 " failed\n", mmc_hostname(mmc));
20b92a30
KL		 1759 return -EIO;
1760 }
1761 }
1762 /* Wait for 5ms */
1763 usleep_range(5000, 5500);
f2119df6 1764
20b92a30
KL		 1765 /* 3.3V regulator output should be stable within 5 ms */
1766 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1767 if (!(ctrl & SDHCI_CTRL_VDD_180))
1768 return 0;
6231f3de 1769
20b92a30 1770 pr_warning("%s: 3.3V regulator output did not became stable\n",
4e743f1f 1771 mmc_hostname(mmc));
20b92a30
KL		 1772
1773 return -EAGAIN;
1774 case MMC_SIGNAL_VOLTAGE_180:
3a48edc4
TK		 1775 if (!IS_ERR(mmc->supply.vqmmc)) {
1776 ret = regulator_set_voltage(mmc->supply.vqmmc,
20b92a30
KL		 1777 1700000, 1950000);
1778 if (ret) {
1779 pr_warning("%s: Switching to 1.8V signalling voltage "
4e743f1f 1780 " failed\n", mmc_hostname(mmc));
20b92a30
KL		 1781 return -EIO;
1782 }
1783 }
6231f3de 1784
6231f3de
PR		 1785 /*
1786 * Enable 1.8V Signal Enable in the Host Control2
1787 * register
1788 */
20b92a30
KL		 1789 ctrl |= SDHCI_CTRL_VDD_180;
1790 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
6231f3de 1791
20b92a30
KL		 1792 /* 1.8V regulator output should be stable within 5 ms */
1793 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1794 if (ctrl & SDHCI_CTRL_VDD_180)
1795 return 0;
f2119df6 1796
20b92a30 1797 pr_warning("%s: 1.8V regulator output did not became stable\n",
4e743f1f 1798 mmc_hostname(mmc));
f2119df6 1799
20b92a30
KL		 1800 return -EAGAIN;
1801 case MMC_SIGNAL_VOLTAGE_120:
3a48edc4
TK		 1802 if (!IS_ERR(mmc->supply.vqmmc)) {
1803 ret = regulator_set_voltage(mmc->supply.vqmmc, 1100000,
1804 1300000);
20b92a30
KL		 1805 if (ret) {
1806 pr_warning("%s: Switching to 1.2V signalling voltage "
4e743f1f 1807 " failed\n", mmc_hostname(mmc));
20b92a30 1808 return -EIO;
f2119df6
AN		 1809 }
1810 }
6231f3de 1811 return 0;
20b92a30 1812 default:
f2119df6
AN		 1813 /* No signal voltage switch required */
1814 return 0;
20b92a30 1815 }
f2119df6
AN		 1816}
1817
66fd8ad5 1818static int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
21f5998f 1819 struct mmc_ios *ios)
66fd8ad5
AH		 1820{
1821 struct sdhci_host *host = mmc_priv(mmc);
1822 int err;
1823
1824 if (host->version < SDHCI_SPEC_300)
1825 return 0;
1826 sdhci_runtime_pm_get(host);
21f5998f 1827 err = sdhci_do_start_signal_voltage_switch(host, ios);
66fd8ad5
AH		 1828 sdhci_runtime_pm_put(host);
1829 return err;
1830}
1831
20b92a30
KL		 1832static int sdhci_card_busy(struct mmc_host *mmc)
1833{
1834 struct sdhci_host *host = mmc_priv(mmc);
1835 u32 present_state;
1836
1837 sdhci_runtime_pm_get(host);
1838 /* Check whether DAT[3:0] is 0000 */
1839 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
1840 sdhci_runtime_pm_put(host);
1841
1842 return !(present_state & SDHCI_DATA_LVL_MASK);
1843}
1844
069c9f14 1845static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode)
b513ea25 1846{
4b6f37d3 1847 struct sdhci_host *host = mmc_priv(mmc);
b513ea25 1848 u16 ctrl;
b513ea25 1849 int tuning_loop_counter = MAX_TUNING_LOOP;
b513ea25 1850 int err = 0;
2b35bd83 1851 unsigned long flags;
b513ea25 1852
66fd8ad5 1853 sdhci_runtime_pm_get(host);
2b35bd83 1854 spin_lock_irqsave(&host->lock, flags);
b513ea25 1855
b513ea25 1856 /*
069c9f14
G		 1857 * The Host Controller needs tuning only in case of SDR104 mode
1858 * and for SDR50 mode when Use Tuning for SDR50 is set in the
b513ea25 1859 * Capabilities register.
069c9f14
G		 1860 * If the Host Controller supports the HS200 mode then the
1861 * tuning function has to be executed.
b513ea25 1862 */
4b6f37d3
RK		 1863 switch (host->timing) {
1864 case MMC_TIMING_MMC_HS200:
1865 case MMC_TIMING_UHS_SDR104:
1866 break;
1867
1868 case MMC_TIMING_UHS_SDR50:
1869 if (host->flags & SDHCI_SDR50_NEEDS_TUNING ||
1870 host->flags & SDHCI_SDR104_NEEDS_TUNING)
1871 break;
1872 /* FALLTHROUGH */
1873
1874 default:
2b35bd83 1875 spin_unlock_irqrestore(&host->lock, flags);
66fd8ad5 1876 sdhci_runtime_pm_put(host);
b513ea25
AN		 1877 return 0;
1878 }
1879
45251812 1880 if (host->ops->platform_execute_tuning) {
2b35bd83 1881 spin_unlock_irqrestore(&host->lock, flags);
45251812
DA		 1882 err = host->ops->platform_execute_tuning(host, opcode);
1883 sdhci_runtime_pm_put(host);
1884 return err;
1885 }
1886
4b6f37d3
RK		 1887 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1888 ctrl |= SDHCI_CTRL_EXEC_TUNING;
b513ea25
AN		 1889 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1890
1891 /*
1892 * As per the Host Controller spec v3.00, tuning command
1893 * generates Buffer Read Ready interrupt, so enable that.
1894 *
1895 * Note: The spec clearly says that when tuning sequence
1896 * is being performed, the controller does not generate
1897 * interrupts other than Buffer Read Ready interrupt. But
1898 * to make sure we don't hit a controller bug, we _only_
1899 * enable Buffer Read Ready interrupt here.
1900 */
b537f94c
RK		 1901 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE);
1902 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE);
b513ea25
AN		 1903
1904 /*
1905 * Issue CMD19 repeatedly till Execute Tuning is set to 0 or the number
1906 * of loops reaches 40 times or a timeout of 150ms occurs.
1907 */
b513ea25
AN		 1908 do {
1909 struct mmc_command cmd = {0};
66fd8ad5 1910 struct mmc_request mrq = {NULL};
b513ea25 1911
069c9f14 1912 cmd.opcode = opcode;
b513ea25
AN		 1913 cmd.arg = 0;
1914 cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
1915 cmd.retries = 0;
1916 cmd.data = NULL;
1917 cmd.error = 0;
1918
7ce45e95
AC		 1919 if (tuning_loop_counter-- == 0)
1920 break;
1921
b513ea25
AN		 1922 mrq.cmd = &cmd;
1923 host->mrq = &mrq;
1924
1925 /*
1926 * In response to CMD19, the card sends 64 bytes of tuning
1927 * block to the Host Controller. So we set the block size
1928 * to 64 here.
1929 */
069c9f14
G		 1930 if (cmd.opcode == MMC_SEND_TUNING_BLOCK_HS200) {
1931 if (mmc->ios.bus_width == MMC_BUS_WIDTH_8)
1932 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 128),
1933 SDHCI_BLOCK_SIZE);
1934 else if (mmc->ios.bus_width == MMC_BUS_WIDTH_4)
1935 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
1936 SDHCI_BLOCK_SIZE);
1937 } else {
1938 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
1939 SDHCI_BLOCK_SIZE);
1940 }
b513ea25
AN		 1941
1942 /*
1943 * The tuning block is sent by the card to the host controller.
1944 * So we set the TRNS_READ bit in the Transfer Mode register.
1945 * This also takes care of setting DMA Enable and Multi Block
1946 * Select in the same register to 0.
1947 */
1948 sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
1949
1950 sdhci_send_command(host, &cmd);
1951
1952 host->cmd = NULL;
1953 host->mrq = NULL;
1954
2b35bd83 1955 spin_unlock_irqrestore(&host->lock, flags);
b513ea25
AN		 1956 /* Wait for Buffer Read Ready interrupt */
1957 wait_event_interruptible_timeout(host->buf_ready_int,
1958 (host->tuning_done == 1),
1959 msecs_to_jiffies(50));
2b35bd83 1960 spin_lock_irqsave(&host->lock, flags);
b513ea25
AN		 1961
1962 if (!host->tuning_done) {
a3c76eb9 1963 pr_info(DRIVER_NAME ": Timeout waiting for "
b513ea25
AN		 1964 "Buffer Read Ready interrupt during tuning "
1965 "procedure, falling back to fixed sampling "
1966 "clock\n");
1967 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1968 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
1969 ctrl &= ~SDHCI_CTRL_EXEC_TUNING;
1970 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1971
1972 err = -EIO;
1973 goto out;
1974 }
1975
1976 host->tuning_done = 0;
1977
1978 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
197160d5
NS		 1979
1980 /* eMMC spec does not require a delay between tuning cycles */
1981 if (opcode == MMC_SEND_TUNING_BLOCK)
1982 mdelay(1);
b513ea25
AN		 1983 } while (ctrl & SDHCI_CTRL_EXEC_TUNING);
1984
1985 /*
1986 * The Host Driver has exhausted the maximum number of loops allowed,
1987 * so use fixed sampling frequency.
1988 */
7ce45e95 1989 if (tuning_loop_counter < 0) {
b513ea25
AN		 1990 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
1991 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
7ce45e95
AC		 1992 }
1993 if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) {
1994 pr_info(DRIVER_NAME ": Tuning procedure"
1995 " failed, falling back to fixed sampling"
1996 " clock\n");
114f2bf6 1997 err = -EIO;
b513ea25
AN		 1998 }
1999
2000out:
cf2b5eea
AN		 2001 /*
2002 * If this is the very first time we are here, we start the retuning
2003 * timer. Since only during the first time, SDHCI_NEEDS_RETUNING
2004 * flag won't be set, we check this condition before actually starting
2005 * the timer.
2006 */
2007 if (!(host->flags & SDHCI_NEEDS_RETUNING) && host->tuning_count &&
2008 (host->tuning_mode == SDHCI_TUNING_MODE_1)) {
973905fe 2009 host->flags |= SDHCI_USING_RETUNING_TIMER;
cf2b5eea
AN		 2010 mod_timer(&host->tuning_timer, jiffies +
2011 host->tuning_count * HZ);
2012 /* Tuning mode 1 limits the maximum data length to 4MB */
2013 mmc->max_blk_count = (4 * 1024 * 1024) / mmc->max_blk_size;
2bc02485 2014 } else if (host->flags & SDHCI_USING_RETUNING_TIMER) {
cf2b5eea
AN		 2015 host->flags &= ~SDHCI_NEEDS_RETUNING;
2016 /* Reload the new initial value for timer */
2bc02485
AS		 2017 mod_timer(&host->tuning_timer, jiffies +
2018 host->tuning_count * HZ);
cf2b5eea
AN		 2019 }
2020
2021 /*
2022 * In case tuning fails, host controllers which support re-tuning can
2023 * try tuning again at a later time, when the re-tuning timer expires.
2024 * So for these controllers, we return 0. Since there might be other
2025 * controllers who do not have this capability, we return error for
973905fe
AL		 2026 * them. SDHCI_USING_RETUNING_TIMER means the host is currently using
2027 * a retuning timer to do the retuning for the card.
cf2b5eea 2028 */
973905fe 2029 if (err && (host->flags & SDHCI_USING_RETUNING_TIMER))
cf2b5eea
AN		 2030 err = 0;
2031
b537f94c
RK		 2032 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2033 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2b35bd83 2034 spin_unlock_irqrestore(&host->lock, flags);
66fd8ad5 2035 sdhci_runtime_pm_put(host);
b513ea25
AN		 2036
2037 return err;
2038}
2039
52983382
KL		 2040
2041static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable)
4d55c5a1 2042{
4d55c5a1
AN		 2043 /* Host Controller v3.00 defines preset value registers */
2044 if (host->version < SDHCI_SPEC_300)
2045 return;
2046
4d55c5a1
AN		 2047 /*
2048 * We only enable or disable Preset Value if they are not already
2049 * enabled or disabled respectively. Otherwise, we bail out.
2050 */
da91a8f9
RK		 2051 if (host->preset_enabled != enable) {
2052 u16 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2053
2054 if (enable)
2055 ctrl |= SDHCI_CTRL_PRESET_VAL_ENABLE;
2056 else
2057 ctrl &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
2058
4d55c5a1 2059 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
da91a8f9
RK		 2060
2061 if (enable)
2062 host->flags |= SDHCI_PV_ENABLED;
2063 else
2064 host->flags &= ~SDHCI_PV_ENABLED;
2065
2066 host->preset_enabled = enable;
4d55c5a1 2067 }
66fd8ad5
AH		 2068}
2069
71e69211 2070static void sdhci_card_event(struct mmc_host *mmc)
d129bceb 2071{
71e69211 2072 struct sdhci_host *host = mmc_priv(mmc);
d129bceb
PO		 2073 unsigned long flags;
2074
722e1280
CD		 2075 /* First check if client has provided their own card event */
2076 if (host->ops->card_event)
2077 host->ops->card_event(host);
2078
d129bceb
PO		 2079 spin_lock_irqsave(&host->lock, flags);
2080
66fd8ad5 2081 /* Check host->mrq first in case we are runtime suspended */
9668d765 2082 if (host->mrq && !sdhci_do_get_cd(host)) {
a3c76eb9 2083 pr_err("%s: Card removed during transfer!\n",
66fd8ad5 2084 mmc_hostname(host->mmc));
a3c76eb9 2085 pr_err("%s: Resetting controller.\n",
66fd8ad5 2086 mmc_hostname(host->mmc));
d129bceb 2087
03231f9b
RK		 2088 sdhci_do_reset(host, SDHCI_RESET_CMD);
2089 sdhci_do_reset(host, SDHCI_RESET_DATA);
d129bceb 2090
66fd8ad5
AH		 2091 host->mrq->cmd->error = -ENOMEDIUM;
2092 tasklet_schedule(&host->finish_tasklet);
d129bceb
PO		 2093 }
2094
2095 spin_unlock_irqrestore(&host->lock, flags);
71e69211
GL		 2096}
2097
2098static const struct mmc_host_ops sdhci_ops = {
2099 .request = sdhci_request,
2100 .set_ios = sdhci_set_ios,
94144a46 2101 .get_cd = sdhci_get_cd,
71e69211
GL		 2102 .get_ro = sdhci_get_ro,
2103 .hw_reset = sdhci_hw_reset,
2104 .enable_sdio_irq = sdhci_enable_sdio_irq,
2105 .start_signal_voltage_switch = sdhci_start_signal_voltage_switch,
2106 .execute_tuning = sdhci_execute_tuning,
71e69211 2107 .card_event = sdhci_card_event,
20b92a30 2108 .card_busy = sdhci_card_busy,
71e69211
GL		 2109};
2110
2111/*****************************************************************************\
2112 * *
2113 * Tasklets *
2114 * *
2115\*****************************************************************************/
2116
d129bceb
PO		 2117static void sdhci_tasklet_finish(unsigned long param)
2118{
2119 struct sdhci_host *host;
2120 unsigned long flags;
2121 struct mmc_request *mrq;
2122
2123 host = (struct sdhci_host*)param;
2124
66fd8ad5
AH		 2125 spin_lock_irqsave(&host->lock, flags);
2126
0c9c99a7
CB		 2127 /*
2128 * If this tasklet gets rescheduled while running, it will
2129 * be run again afterwards but without any active request.
2130 */
66fd8ad5
AH		 2131 if (!host->mrq) {
2132 spin_unlock_irqrestore(&host->lock, flags);
0c9c99a7 2133 return;
66fd8ad5 2134 }
d129bceb
PO		 2135
2136 del_timer(&host->timer);
2137
2138 mrq = host->mrq;
2139
d129bceb
PO		 2140 /*
2141 * The controller needs a reset of internal state machines
2142 * upon error conditions.
2143 */
1e72859e 2144 if (!(host->flags & SDHCI_DEVICE_DEAD) &&
b7b4d342 2145 ((mrq->cmd && mrq->cmd->error) ||
1e72859e
PO		 2146 (mrq->data && (mrq->data->error ||
2147 (mrq->data->stop && mrq->data->stop->error))) ||
2148 (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) {
645289dc
PO		 2149
2150 /* Some controllers need this kick or reset won't work here */
8213af3b 2151 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)
645289dc 2152 /* This is to force an update */
1771059c 2153 host->ops->set_clock(host, host->clock);
645289dc
PO		 2154
2155 /* Spec says we should do both at the same time, but Ricoh
2156 controllers do not like that. */
03231f9b
RK		 2157 sdhci_do_reset(host, SDHCI_RESET_CMD);
2158 sdhci_do_reset(host, SDHCI_RESET_DATA);
d129bceb
PO		 2159 }
2160
2161 host->mrq = NULL;
2162 host->cmd = NULL;
2163 host->data = NULL;
2164
f9134319 2165#ifndef SDHCI_USE_LEDS_CLASS
d129bceb 2166 sdhci_deactivate_led(host);
2f730fec 2167#endif
d129bceb 2168
5f25a66f 2169 mmiowb();
d129bceb
PO		 2170 spin_unlock_irqrestore(&host->lock, flags);
2171
2172 mmc_request_done(host->mmc, mrq);
66fd8ad5 2173 sdhci_runtime_pm_put(host);
d129bceb
PO		 2174}
2175
2176static void sdhci_timeout_timer(unsigned long data)
2177{
2178 struct sdhci_host *host;
2179 unsigned long flags;
2180
2181 host = (struct sdhci_host*)data;
2182
2183 spin_lock_irqsave(&host->lock, flags);
2184
2185 if (host->mrq) {
a3c76eb9 2186 pr_err("%s: Timeout waiting for hardware "
acf1da45 2187 "interrupt.\n", mmc_hostname(host->mmc));
d129bceb
PO		 2188 sdhci_dumpregs(host);
2189
2190 if (host->data) {
17b0429d 2191 host->data->error = -ETIMEDOUT;
d129bceb
PO		 2192 sdhci_finish_data(host);
2193 } else {
2194 if (host->cmd)
17b0429d 2195 host->cmd->error = -ETIMEDOUT;
d129bceb 2196 else
17b0429d 2197 host->mrq->cmd->error = -ETIMEDOUT;
d129bceb
PO		 2198
2199 tasklet_schedule(&host->finish_tasklet);
2200 }
2201 }
2202
5f25a66f 2203 mmiowb();
d129bceb
PO		 2204 spin_unlock_irqrestore(&host->lock, flags);
2205}
2206
cf2b5eea
AN		 2207static void sdhci_tuning_timer(unsigned long data)
2208{
2209 struct sdhci_host *host;
2210 unsigned long flags;
2211
2212 host = (struct sdhci_host *)data;
2213
2214 spin_lock_irqsave(&host->lock, flags);
2215
2216 host->flags |= SDHCI_NEEDS_RETUNING;
2217
2218 spin_unlock_irqrestore(&host->lock, flags);
2219}
2220
d129bceb
PO		 2221/*****************************************************************************\
2222 * *
2223 * Interrupt handling *
2224 * *
2225\*****************************************************************************/
2226
2227static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask)
2228{
2229 BUG_ON(intmask == 0);
2230
2231 if (!host->cmd) {
a3c76eb9 2232 pr_err("%s: Got command interrupt 0x%08x even "
b67ac3f3
PO		 2233 "though no command operation was in progress.\n",
2234 mmc_hostname(host->mmc), (unsigned)intmask);
d129bceb
PO		 2235 sdhci_dumpregs(host);
2236 return;
2237 }
2238
43b58b36 2239 if (intmask & SDHCI_INT_TIMEOUT)
17b0429d
PO		 2240 host->cmd->error = -ETIMEDOUT;
2241 else if (intmask & (SDHCI_INT_CRC | SDHCI_INT_END_BIT |
2242 SDHCI_INT_INDEX))
2243 host->cmd->error = -EILSEQ;
43b58b36 2244
e809517f 2245 if (host->cmd->error) {
d129bceb 2246 tasklet_schedule(&host->finish_tasklet);
e809517f
PO		 2247 return;
2248 }
2249
2250 /*
2251 * The host can send and interrupt when the busy state has
2252 * ended, allowing us to wait without wasting CPU cycles.
2253 * Unfortunately this is overloaded on the "data complete"
2254 * interrupt, so we need to take some care when handling
2255 * it.
2256 *
2257 * Note: The 1.0 specification is a bit ambiguous about this
2258 * feature so there might be some problems with older
2259 * controllers.
2260 */
2261 if (host->cmd->flags & MMC_RSP_BUSY) {
2262 if (host->cmd->data)
2263 DBG("Cannot wait for busy signal when also "
2264 "doing a data transfer");
e99783a4
CM		 2265 else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ)
2266 && !host->busy_handle) {
2267 /* Mark that command complete before busy is ended */
2268 host->busy_handle = 1;
e809517f 2269 return;
e99783a4 2270 }
f945405c
BD		 2271
2272 /* The controller does not support the end-of-busy IRQ,
2273 * fall through and take the SDHCI_INT_RESPONSE */
e809517f
PO		 2274 }
2275
2276 if (intmask & SDHCI_INT_RESPONSE)
43b58b36 2277 sdhci_finish_command(host);
d129bceb
PO		 2278}
2279
0957c333 2280#ifdef CONFIG_MMC_DEBUG
6882a8c0
BD		 2281static void sdhci_show_adma_error(struct sdhci_host *host)
2282{
2283 const char *name = mmc_hostname(host->mmc);
2284 u8 *desc = host->adma_desc;
2285 __le32 *dma;
2286 __le16 *len;
2287 u8 attr;
2288
2289 sdhci_dumpregs(host);
2290
2291 while (true) {
2292 dma = (__le32 *)(desc + 4);
2293 len = (__le16 *)(desc + 2);
2294 attr = *desc;
2295
2296 DBG("%s: %p: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n",
2297 name, desc, le32_to_cpu(*dma), le16_to_cpu(*len), attr);
2298
2299 desc += 8;
2300
2301 if (attr & 2)
2302 break;
2303 }
2304}
2305#else
2306static void sdhci_show_adma_error(struct sdhci_host *host) { }
2307#endif
2308
d129bceb
PO		 2309static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
2310{
069c9f14 2311 u32 command;
d129bceb
PO		 2312 BUG_ON(intmask == 0);
2313
b513ea25
AN		 2314 /* CMD19 generates _only_ Buffer Read Ready interrupt */
2315 if (intmask & SDHCI_INT_DATA_AVAIL) {
069c9f14
G		 2316 command = SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND));
2317 if (command == MMC_SEND_TUNING_BLOCK ||
2318 command == MMC_SEND_TUNING_BLOCK_HS200) {
b513ea25
AN		 2319 host->tuning_done = 1;
2320 wake_up(&host->buf_ready_int);
2321 return;
2322 }
2323 }
2324
d129bceb
PO		 2325 if (!host->data) {
2326 /*
e809517f
PO		 2327 * The "data complete" interrupt is also used to
2328 * indicate that a busy state has ended. See comment
2329 * above in sdhci_cmd_irq().
d129bceb 2330 */
e809517f 2331 if (host->cmd && (host->cmd->flags & MMC_RSP_BUSY)) {
c5abd5e8
MC		 2332 if (intmask & SDHCI_INT_DATA_TIMEOUT) {
2333 host->cmd->error = -ETIMEDOUT;
2334 tasklet_schedule(&host->finish_tasklet);
2335 return;
2336 }
e809517f 2337 if (intmask & SDHCI_INT_DATA_END) {
e99783a4
CM		 2338 /*
2339 * Some cards handle busy-end interrupt
2340 * before the command completed, so make
2341 * sure we do things in the proper order.
2342 */
2343 if (host->busy_handle)
2344 sdhci_finish_command(host);
2345 else
2346 host->busy_handle = 1;
e809517f
PO		 2347 return;
2348 }
2349 }
d129bceb 2350
a3c76eb9 2351 pr_err("%s: Got data interrupt 0x%08x even "
b67ac3f3
PO		 2352 "though no data operation was in progress.\n",
2353 mmc_hostname(host->mmc), (unsigned)intmask);
d129bceb
PO		 2354 sdhci_dumpregs(host);
2355
2356 return;
2357 }
2358
2359 if (intmask & SDHCI_INT_DATA_TIMEOUT)
17b0429d 2360 host->data->error = -ETIMEDOUT;
22113efd
AL		 2361 else if (intmask & SDHCI_INT_DATA_END_BIT)
2362 host->data->error = -EILSEQ;
2363 else if ((intmask & SDHCI_INT_DATA_CRC) &&
2364 SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))
2365 != MMC_BUS_TEST_R)
17b0429d 2366 host->data->error = -EILSEQ;
6882a8c0 2367 else if (intmask & SDHCI_INT_ADMA_ERROR) {
a3c76eb9 2368 pr_err("%s: ADMA error\n", mmc_hostname(host->mmc));
6882a8c0 2369 sdhci_show_adma_error(host);
2134a922 2370 host->data->error = -EIO;
a4071fbb
HZ		 2371 if (host->ops->adma_workaround)
2372 host->ops->adma_workaround(host, intmask);
6882a8c0 2373 }
d129bceb 2374
17b0429d 2375 if (host->data->error)
d129bceb
PO		 2376 sdhci_finish_data(host);
2377 else {
a406f5a3 2378 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
d129bceb
PO		 2379 sdhci_transfer_pio(host);
2380
6ba736a1
PO		 2381 /*
2382 * We currently don't do anything fancy with DMA
2383 * boundaries, but as we can't disable the feature
2384 * we need to at least restart the transfer.
f6a03cbf
MV		 2385 *
2386 * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS)
2387 * should return a valid address to continue from, but as
2388 * some controllers are faulty, don't trust them.
6ba736a1 2389 */
f6a03cbf
MV		 2390 if (intmask & SDHCI_INT_DMA_END) {
2391 u32 dmastart, dmanow;
2392 dmastart = sg_dma_address(host->data->sg);
2393 dmanow = dmastart + host->data->bytes_xfered;
2394 /*
2395 * Force update to the next DMA block boundary.
2396 */
2397 dmanow = (dmanow &
2398 ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) +
2399 SDHCI_DEFAULT_BOUNDARY_SIZE;
2400 host->data->bytes_xfered = dmanow - dmastart;
2401 DBG("%s: DMA base 0x%08x, transferred 0x%06x bytes,"
2402 " next 0x%08x\n",
2403 mmc_hostname(host->mmc), dmastart,
2404 host->data->bytes_xfered, dmanow);
2405 sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS);
2406 }
6ba736a1 2407
e538fbe8
PO		 2408 if (intmask & SDHCI_INT_DATA_END) {
2409 if (host->cmd) {
2410 /*
2411 * Data managed to finish before the
2412 * command completed. Make sure we do
2413 * things in the proper order.
2414 */
2415 host->data_early = 1;
2416 } else {
2417 sdhci_finish_data(host);
2418 }
2419 }
d129bceb
PO		 2420 }
2421}
2422
7d12e780 2423static irqreturn_t sdhci_irq(int irq, void *dev_id)
d129bceb 2424{
781e989c 2425 irqreturn_t result = IRQ_NONE;
66fd8ad5 2426 struct sdhci_host *host = dev_id;
41005003 2427 u32 intmask, mask, unexpected = 0;
781e989c 2428 int max_loops = 16;
d129bceb
PO		 2429
2430 spin_lock(&host->lock);
2431
be138554 2432 if (host->runtime_suspended && !sdhci_sdio_irq_enabled(host)) {
66fd8ad5 2433 spin_unlock(&host->lock);
655bca76 2434 return IRQ_NONE;
66fd8ad5
AH		 2435 }
2436
4e4141a5 2437 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
62df67a5 2438 if (!intmask || intmask == 0xffffffff) {
d129bceb
PO		 2439 result = IRQ_NONE;
2440 goto out;
2441 }
2442
41005003
RK		 2443 do {
2444 /* Clear selected interrupts. */
2445 mask = intmask & (SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
2446 SDHCI_INT_BUS_POWER);
2447 sdhci_writel(host, mask, SDHCI_INT_STATUS);
d129bceb 2448
41005003
RK		 2449 DBG("*** %s got interrupt: 0x%08x\n",
2450 mmc_hostname(host->mmc), intmask);
d129bceb 2451
41005003
RK		 2452 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
2453 u32 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
2454 SDHCI_CARD_PRESENT;
d129bceb 2455
41005003
RK		 2456 /*
2457 * There is a observation on i.mx esdhc. INSERT
2458 * bit will be immediately set again when it gets
2459 * cleared, if a card is inserted. We have to mask
2460 * the irq to prevent interrupt storm which will
2461 * freeze the system. And the REMOVE gets the
2462 * same situation.
2463 *
2464 * More testing are needed here to ensure it works
2465 * for other platforms though.
2466 */
b537f94c
RK		 2467 host->ier &= ~(SDHCI_INT_CARD_INSERT |
2468 SDHCI_INT_CARD_REMOVE);
2469 host->ier |= present ? SDHCI_INT_CARD_REMOVE :
2470 SDHCI_INT_CARD_INSERT;
2471 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2472 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
41005003
RK		 2473
2474 sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT |
2475 SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS);
3560db8e
RK		 2476
2477 host->thread_isr |= intmask & (SDHCI_INT_CARD_INSERT |
2478 SDHCI_INT_CARD_REMOVE);
2479 result = IRQ_WAKE_THREAD;
41005003 2480 }
d129bceb 2481
41005003
RK		 2482 if (intmask & SDHCI_INT_CMD_MASK)
2483 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK);
964f9ce2 2484
41005003
RK		 2485 if (intmask & SDHCI_INT_DATA_MASK)
2486 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
d129bceb 2487
41005003
RK		 2488 if (intmask & SDHCI_INT_BUS_POWER)
2489 pr_err("%s: Card is consuming too much power!\n",
2490 mmc_hostname(host->mmc));
3192a28f 2491
781e989c
RK		 2492 if (intmask & SDHCI_INT_CARD_INT) {
2493 sdhci_enable_sdio_irq_nolock(host, false);
2494 host->thread_isr |= SDHCI_INT_CARD_INT;
2495 result = IRQ_WAKE_THREAD;
2496 }
f75979b7 2497
41005003
RK		 2498 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE |
2499 SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
2500 SDHCI_INT_ERROR | SDHCI_INT_BUS_POWER |
2501 SDHCI_INT_CARD_INT);
f75979b7 2502
41005003
RK		 2503 if (intmask) {
2504 unexpected |= intmask;
2505 sdhci_writel(host, intmask, SDHCI_INT_STATUS);
2506 }
d129bceb 2507
781e989c
RK		 2508 if (result == IRQ_NONE)
2509 result = IRQ_HANDLED;
d129bceb 2510
41005003 2511 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
41005003 2512 } while (intmask && --max_loops);
d129bceb
PO		 2513out:
2514 spin_unlock(&host->lock);
2515
6379b237
AS		 2516 if (unexpected) {
2517 pr_err("%s: Unexpected interrupt 0x%08x.\n",
2518 mmc_hostname(host->mmc), unexpected);
2519 sdhci_dumpregs(host);
2520 }
f75979b7 2521
d129bceb
PO		 2522 return result;
2523}
2524
781e989c
RK		 2525static irqreturn_t sdhci_thread_irq(int irq, void *dev_id)
2526{
2527 struct sdhci_host *host = dev_id;
2528 unsigned long flags;
2529 u32 isr;
2530
2531 spin_lock_irqsave(&host->lock, flags);
2532 isr = host->thread_isr;
2533 host->thread_isr = 0;
2534 spin_unlock_irqrestore(&host->lock, flags);
2535
3560db8e
RK		 2536 if (isr & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
2537 sdhci_card_event(host->mmc);
2538 mmc_detect_change(host->mmc, msecs_to_jiffies(200));
2539 }
2540
781e989c
RK		 2541 if (isr & SDHCI_INT_CARD_INT) {
2542 sdio_run_irqs(host->mmc);
2543
2544 spin_lock_irqsave(&host->lock, flags);
2545 if (host->flags & SDHCI_SDIO_IRQ_ENABLED)
2546 sdhci_enable_sdio_irq_nolock(host, true);
2547 spin_unlock_irqrestore(&host->lock, flags);
2548 }
2549
2550 return isr ? IRQ_HANDLED : IRQ_NONE;
2551}
2552
d129bceb
PO		 2553/*****************************************************************************\
2554 * *
2555 * Suspend/resume *
2556 * *
2557\*****************************************************************************/
2558
2559#ifdef CONFIG_PM
ad080d79
KL		 2560void sdhci_enable_irq_wakeups(struct sdhci_host *host)
2561{
2562 u8 val;
2563 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
2564 | SDHCI_WAKE_ON_INT;
2565
2566 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2567 val |= mask ;
2568 /* Avoid fake wake up */
2569 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
2570 val &= ~(SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE);
2571 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2572}
2573EXPORT_SYMBOL_GPL(sdhci_enable_irq_wakeups);
2574
0b10f478 2575static void sdhci_disable_irq_wakeups(struct sdhci_host *host)
ad080d79
KL		 2576{
2577 u8 val;
2578 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
2579 | SDHCI_WAKE_ON_INT;
2580
2581 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2582 val &= ~mask;
2583 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2584}
d129bceb 2585
29495aa0 2586int sdhci_suspend_host(struct sdhci_host *host)
d129bceb 2587{
7260cf5e
AV		 2588 sdhci_disable_card_detection(host);
2589
cf2b5eea 2590 /* Disable tuning since we are suspending */
973905fe 2591 if (host->flags & SDHCI_USING_RETUNING_TIMER) {
c6ced0db 2592 del_timer_sync(&host->tuning_timer);
cf2b5eea 2593 host->flags &= ~SDHCI_NEEDS_RETUNING;
cf2b5eea
AN		 2594 }
2595
ad080d79 2596 if (!device_may_wakeup(mmc_dev(host->mmc))) {
b537f94c
RK		 2597 host->ier = 0;
2598 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
2599 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
ad080d79
KL		 2600 free_irq(host->irq, host);
2601 } else {
2602 sdhci_enable_irq_wakeups(host);
2603 enable_irq_wake(host->irq);
2604 }
4ee14ec6 2605 return 0;
d129bceb
PO		 2606}
2607
b8c86fc5 2608EXPORT_SYMBOL_GPL(sdhci_suspend_host);
d129bceb 2609
b8c86fc5
PO		 2610int sdhci_resume_host(struct sdhci_host *host)
2611{
4ee14ec6 2612 int ret = 0;
d129bceb 2613
a13abc7b 2614 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
b8c86fc5
PO		 2615 if (host->ops->enable_dma)
2616 host->ops->enable_dma(host);
2617 }
d129bceb 2618
ad080d79 2619 if (!device_may_wakeup(mmc_dev(host->mmc))) {
781e989c
RK		 2620 ret = request_threaded_irq(host->irq, sdhci_irq,
2621 sdhci_thread_irq, IRQF_SHARED,
2622 mmc_hostname(host->mmc), host);
ad080d79
KL		 2623 if (ret)
2624 return ret;
2625 } else {
2626 sdhci_disable_irq_wakeups(host);
2627 disable_irq_wake(host->irq);
2628 }
d129bceb 2629
6308d290
AH		 2630 if ((host->mmc->pm_flags & MMC_PM_KEEP_POWER) &&
2631 (host->quirks2 & SDHCI_QUIRK2_HOST_OFF_CARD_ON)) {
2632 /* Card keeps power but host controller does not */
2633 sdhci_init(host, 0);
2634 host->pwr = 0;
2635 host->clock = 0;
2636 sdhci_do_set_ios(host, &host->mmc->ios);
2637 } else {
2638 sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER));
2639 mmiowb();
2640 }
b8c86fc5 2641
7260cf5e
AV		 2642 sdhci_enable_card_detection(host);
2643
cf2b5eea 2644 /* Set the re-tuning expiration flag */
973905fe 2645 if (host->flags & SDHCI_USING_RETUNING_TIMER)
cf2b5eea
AN		 2646 host->flags |= SDHCI_NEEDS_RETUNING;
2647
2f4cbb3d 2648 return ret;
d129bceb
PO		 2649}
2650
b8c86fc5 2651EXPORT_SYMBOL_GPL(sdhci_resume_host);
d129bceb
PO		 2652#endif /* CONFIG_PM */
2653
66fd8ad5
AH		 2654#ifdef CONFIG_PM_RUNTIME
2655
2656static int sdhci_runtime_pm_get(struct sdhci_host *host)
2657{
2658 return pm_runtime_get_sync(host->mmc->parent);
2659}
2660
2661static int sdhci_runtime_pm_put(struct sdhci_host *host)
2662{
2663 pm_runtime_mark_last_busy(host->mmc->parent);
2664 return pm_runtime_put_autosuspend(host->mmc->parent);
2665}
2666
f0710a55
AH		 2667static void sdhci_runtime_pm_bus_on(struct sdhci_host *host)
2668{
2669 if (host->runtime_suspended || host->bus_on)
2670 return;
2671 host->bus_on = true;
2672 pm_runtime_get_noresume(host->mmc->parent);
2673}
2674
2675static void sdhci_runtime_pm_bus_off(struct sdhci_host *host)
2676{
2677 if (host->runtime_suspended || !host->bus_on)
2678 return;
2679 host->bus_on = false;
2680 pm_runtime_put_noidle(host->mmc->parent);
2681}
2682
66fd8ad5
AH		 2683int sdhci_runtime_suspend_host(struct sdhci_host *host)
2684{
2685 unsigned long flags;
66fd8ad5
AH		 2686
2687 /* Disable tuning since we are suspending */
973905fe 2688 if (host->flags & SDHCI_USING_RETUNING_TIMER) {
66fd8ad5
AH		 2689 del_timer_sync(&host->tuning_timer);
2690 host->flags &= ~SDHCI_NEEDS_RETUNING;
2691 }
2692
2693 spin_lock_irqsave(&host->lock, flags);
b537f94c
RK		 2694 host->ier &= SDHCI_INT_CARD_INT;
2695 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2696 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
66fd8ad5
AH		 2697 spin_unlock_irqrestore(&host->lock, flags);
2698
781e989c 2699 synchronize_hardirq(host->irq);
66fd8ad5
AH		 2700
2701 spin_lock_irqsave(&host->lock, flags);
2702 host->runtime_suspended = true;
2703 spin_unlock_irqrestore(&host->lock, flags);
2704
8a125bad 2705 return 0;
66fd8ad5
AH		 2706}
2707EXPORT_SYMBOL_GPL(sdhci_runtime_suspend_host);
2708
2709int sdhci_runtime_resume_host(struct sdhci_host *host)
2710{
2711 unsigned long flags;
8a125bad 2712 int host_flags = host->flags;
66fd8ad5
AH		 2713
2714 if (host_flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2715 if (host->ops->enable_dma)
2716 host->ops->enable_dma(host);
2717 }
2718
2719 sdhci_init(host, 0);
2720
2721 /* Force clock and power re-program */
2722 host->pwr = 0;
2723 host->clock = 0;
2724 sdhci_do_set_ios(host, &host->mmc->ios);
2725
2726 sdhci_do_start_signal_voltage_switch(host, &host->mmc->ios);
52983382
KL		 2727 if ((host_flags & SDHCI_PV_ENABLED) &&
2728 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN)) {
2729 spin_lock_irqsave(&host->lock, flags);
2730 sdhci_enable_preset_value(host, true);
2731 spin_unlock_irqrestore(&host->lock, flags);
2732 }
66fd8ad5
AH		 2733
2734 /* Set the re-tuning expiration flag */
973905fe 2735 if (host->flags & SDHCI_USING_RETUNING_TIMER)
66fd8ad5
AH		 2736 host->flags |= SDHCI_NEEDS_RETUNING;
2737
2738 spin_lock_irqsave(&host->lock, flags);
2739
2740 host->runtime_suspended = false;
2741
2742 /* Enable SDIO IRQ */
ef104333 2743 if (host->flags & SDHCI_SDIO_IRQ_ENABLED)
66fd8ad5
AH		 2744 sdhci_enable_sdio_irq_nolock(host, true);
2745
2746 /* Enable Card Detection */
2747 sdhci_enable_card_detection(host);
2748
2749 spin_unlock_irqrestore(&host->lock, flags);
2750
8a125bad 2751 return 0;
66fd8ad5
AH		 2752}
2753EXPORT_SYMBOL_GPL(sdhci_runtime_resume_host);
2754
2755#endif
2756
d129bceb
PO		 2757/*****************************************************************************\
2758 * *
b8c86fc5 2759 * Device allocation/registration *
d129bceb
PO		 2760 * *
2761\*****************************************************************************/
2762
b8c86fc5
PO		 2763struct sdhci_host *sdhci_alloc_host(struct device *dev,
2764 size_t priv_size)
d129bceb 2765{
d129bceb
PO		 2766 struct mmc_host *mmc;
2767 struct sdhci_host *host;
2768
b8c86fc5 2769 WARN_ON(dev == NULL);
d129bceb 2770
b8c86fc5 2771 mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev);
d129bceb 2772 if (!mmc)
b8c86fc5 2773 return ERR_PTR(-ENOMEM);
d129bceb
PO		 2774
2775 host = mmc_priv(mmc);
2776 host->mmc = mmc;
2777
b8c86fc5
PO		 2778 return host;
2779}
8a4da143 2780
b8c86fc5 2781EXPORT_SYMBOL_GPL(sdhci_alloc_host);
d129bceb 2782
b8c86fc5
PO		 2783int sdhci_add_host(struct sdhci_host *host)
2784{
2785 struct mmc_host *mmc;
bd6a8c30 2786 u32 caps[2] = {0, 0};
f2119df6
AN		 2787 u32 max_current_caps;
2788 unsigned int ocr_avail;
b8c86fc5 2789 int ret;
d129bceb 2790
b8c86fc5
PO		 2791 WARN_ON(host == NULL);
2792 if (host == NULL)
2793 return -EINVAL;
d129bceb 2794
b8c86fc5 2795 mmc = host->mmc;
d129bceb 2796
b8c86fc5
PO		 2797 if (debug_quirks)
2798 host->quirks = debug_quirks;
66fd8ad5
AH		 2799 if (debug_quirks2)
2800 host->quirks2 = debug_quirks2;
d129bceb 2801
03231f9b 2802 sdhci_do_reset(host, SDHCI_RESET_ALL);
d96649ed 2803
4e4141a5 2804 host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
2134a922
PO		 2805 host->version = (host->version & SDHCI_SPEC_VER_MASK)
2806 >> SDHCI_SPEC_VER_SHIFT;
85105c53 2807 if (host->version > SDHCI_SPEC_300) {
a3c76eb9 2808 pr_err("%s: Unknown controller version (%d). "
b69c9058 2809 "You may experience problems.\n", mmc_hostname(mmc),
2134a922 2810 host->version);
4a965505
PO		 2811 }
2812
f2119df6 2813 caps[0] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ? host->caps :
ccc92c23 2814 sdhci_readl(host, SDHCI_CAPABILITIES);
d129bceb 2815
bd6a8c30
PR		 2816 if (host->version >= SDHCI_SPEC_300)
2817 caps[1] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ?
2818 host->caps1 :
2819 sdhci_readl(host, SDHCI_CAPABILITIES_1);
f2119df6 2820
b8c86fc5 2821 if (host->quirks & SDHCI_QUIRK_FORCE_DMA)
a13abc7b 2822 host->flags |= SDHCI_USE_SDMA;
f2119df6 2823 else if (!(caps[0] & SDHCI_CAN_DO_SDMA))
a13abc7b 2824 DBG("Controller doesn't have SDMA capability\n");
67435274 2825 else
a13abc7b 2826 host->flags |= SDHCI_USE_SDMA;
d129bceb 2827
b8c86fc5 2828 if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
a13abc7b 2829 (host->flags & SDHCI_USE_SDMA)) {
cee687ce 2830 DBG("Disabling DMA as it is marked broken\n");
a13abc7b 2831 host->flags &= ~SDHCI_USE_SDMA;
7c168e3d
FT		 2832 }
2833
f2119df6
AN		 2834 if ((host->version >= SDHCI_SPEC_200) &&
2835 (caps[0] & SDHCI_CAN_DO_ADMA2))
a13abc7b 2836 host->flags |= SDHCI_USE_ADMA;
2134a922
PO		 2837
2838 if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) &&
2839 (host->flags & SDHCI_USE_ADMA)) {
2840 DBG("Disabling ADMA as it is marked broken\n");
2841 host->flags &= ~SDHCI_USE_ADMA;
2842 }
2843
a13abc7b 2844 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
b8c86fc5
PO		 2845 if (host->ops->enable_dma) {
2846 if (host->ops->enable_dma(host)) {
a3c76eb9 2847 pr_warning("%s: No suitable DMA "
b8c86fc5
PO		 2848 "available. Falling back to PIO.\n",
2849 mmc_hostname(mmc));
a13abc7b
RR		 2850 host->flags &=
2851 ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
b8c86fc5 2852 }
d129bceb
PO		 2853 }
2854 }
2855
2134a922
PO		 2856 if (host->flags & SDHCI_USE_ADMA) {
2857 /*
2858 * We need to allocate descriptors for all sg entries
2859 * (128) and potentially one alignment transfer for
2860 * each of those entries.
2861 */
4e743f1f 2862 host->adma_desc = dma_alloc_coherent(mmc_dev(mmc),
d1e49f77
RK		 2863 ADMA_SIZE, &host->adma_addr,
2864 GFP_KERNEL);
2134a922
PO		 2865 host->align_buffer = kmalloc(128 * 4, GFP_KERNEL);
2866 if (!host->adma_desc || !host->align_buffer) {
4e743f1f 2867 dma_free_coherent(mmc_dev(mmc), ADMA_SIZE,
d1e49f77 2868 host->adma_desc, host->adma_addr);
2134a922 2869 kfree(host->align_buffer);
a3c76eb9 2870 pr_warning("%s: Unable to allocate ADMA "
2134a922
PO		 2871 "buffers. Falling back to standard DMA.\n",
2872 mmc_hostname(mmc));
2873 host->flags &= ~SDHCI_USE_ADMA;
d1e49f77
RK		 2874 host->adma_desc = NULL;
2875 host->align_buffer = NULL;
2876 } else if (host->adma_addr & 3) {
2877 pr_warning("%s: unable to allocate aligned ADMA descriptor\n",
2878 mmc_hostname(mmc));
2879 host->flags &= ~SDHCI_USE_ADMA;
4e743f1f 2880 dma_free_coherent(mmc_dev(mmc), ADMA_SIZE,
d1e49f77
RK		 2881 host->adma_desc, host->adma_addr);
2882 kfree(host->align_buffer);
2883 host->adma_desc = NULL;
2884 host->align_buffer = NULL;
2134a922
PO		 2885 }
2886 }
2887
7659150c
PO		 2888 /*
2889 * If we use DMA, then it's up to the caller to set the DMA
2890 * mask, but PIO does not need the hw shim so we set a new
2891 * mask here in that case.
2892 */
a13abc7b 2893 if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) {
7659150c 2894 host->dma_mask = DMA_BIT_MASK(64);
4e743f1f 2895 mmc_dev(mmc)->dma_mask = &host->dma_mask;
7659150c 2896 }
d129bceb 2897
c4687d5f 2898 if (host->version >= SDHCI_SPEC_300)
f2119df6 2899 host->max_clk = (caps[0] & SDHCI_CLOCK_V3_BASE_MASK)
c4687d5f
ZG		 2900 >> SDHCI_CLOCK_BASE_SHIFT;
2901 else
f2119df6 2902 host->max_clk = (caps[0] & SDHCI_CLOCK_BASE_MASK)
c4687d5f
ZG		 2903 >> SDHCI_CLOCK_BASE_SHIFT;
2904
4240ff0a 2905 host->max_clk *= 1000000;
f27f47ef
AV		 2906 if (host->max_clk == 0 || host->quirks &
2907 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) {
4240ff0a 2908 if (!host->ops->get_max_clock) {
a3c76eb9 2909 pr_err("%s: Hardware doesn't specify base clock "
4240ff0a
BD		 2910 "frequency.\n", mmc_hostname(mmc));
2911 return -ENODEV;
2912 }
2913 host->max_clk = host->ops->get_max_clock(host);
8ef1a143 2914 }
d129bceb 2915
c3ed3877
AN		 2916 /*
2917 * In case of Host Controller v3.00, find out whether clock
2918 * multiplier is supported.
2919 */
2920 host->clk_mul = (caps[1] & SDHCI_CLOCK_MUL_MASK) >>
2921 SDHCI_CLOCK_MUL_SHIFT;
2922
2923 /*
2924 * In case the value in Clock Multiplier is 0, then programmable
2925 * clock mode is not supported, otherwise the actual clock
2926 * multiplier is one more than the value of Clock Multiplier
2927 * in the Capabilities Register.
2928 */
2929 if (host->clk_mul)
2930 host->clk_mul += 1;
2931
d129bceb
PO		 2932 /*
2933 * Set host parameters.
2934 */
2935 mmc->ops = &sdhci_ops;
c3ed3877 2936 mmc->f_max = host->max_clk;
ce5f036b 2937 if (host->ops->get_min_clock)
a9e58f25 2938 mmc->f_min = host->ops->get_min_clock(host);
c3ed3877
AN		 2939 else if (host->version >= SDHCI_SPEC_300) {
2940 if (host->clk_mul) {
2941 mmc->f_min = (host->max_clk * host->clk_mul) / 1024;
2942 mmc->f_max = host->max_clk * host->clk_mul;
2943 } else
2944 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300;
2945 } else
0397526d 2946 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200;
15ec4461 2947
28aab053
AD		 2948 if (!(host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) {
2949 host->timeout_clk = (caps[0] & SDHCI_TIMEOUT_CLK_MASK) >>
2950 SDHCI_TIMEOUT_CLK_SHIFT;
2951 if (host->timeout_clk == 0) {
2952 if (host->ops->get_timeout_clock) {
2953 host->timeout_clk =
2954 host->ops->get_timeout_clock(host);
2955 } else {
2956 pr_err("%s: Hardware doesn't specify timeout clock frequency.\n",
2957 mmc_hostname(mmc));
2958 return -ENODEV;
2959 }
272308ca 2960 }
272308ca 2961
28aab053
AD		 2962 if (caps[0] & SDHCI_TIMEOUT_CLK_UNIT)
2963 host->timeout_clk *= 1000;
272308ca 2964
28aab053 2965 mmc->max_busy_timeout = host->ops->get_max_timeout_count ?
a6ff5aeb 2966 host->ops->get_max_timeout_count(host) : 1 << 27;
28aab053
AD		 2967 mmc->max_busy_timeout /= host->timeout_clk;
2968 }
58d1246d 2969
e89d456f 2970 mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_ERASE | MMC_CAP_CMD23;
781e989c 2971 mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD;
e89d456f
AW		 2972
2973 if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12)
2974 host->flags |= SDHCI_AUTO_CMD12;
5fe23c7f 2975
8edf6371 2976 /* Auto-CMD23 stuff only works in ADMA or PIO. */
4f3d3e9b 2977 if ((host->version >= SDHCI_SPEC_300) &&
8edf6371 2978 ((host->flags & SDHCI_USE_ADMA) ||
4f3d3e9b 2979 !(host->flags & SDHCI_USE_SDMA))) {
8edf6371
AW		 2980 host->flags |= SDHCI_AUTO_CMD23;
2981 DBG("%s: Auto-CMD23 available\n", mmc_hostname(mmc));
2982 } else {
2983 DBG("%s: Auto-CMD23 unavailable\n", mmc_hostname(mmc));
2984 }
2985
15ec4461
PR		 2986 /*
2987 * A controller may support 8-bit width, but the board itself
2988 * might not have the pins brought out. Boards that support
2989 * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in
2990 * their platform code before calling sdhci_add_host(), and we
2991 * won't assume 8-bit width for hosts without that CAP.
2992 */
5fe23c7f 2993 if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA))
15ec4461 2994 mmc->caps |= MMC_CAP_4_BIT_DATA;
d129bceb 2995
63ef5d8c
JH		 2996 if (host->quirks2 & SDHCI_QUIRK2_HOST_NO_CMD23)
2997 mmc->caps &= ~MMC_CAP_CMD23;
2998
f2119df6 2999 if (caps[0] & SDHCI_CAN_DO_HISPD)
a29e7e18 3000 mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
cd9277c0 3001
176d1ed4 3002 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) &&
4e743f1f 3003 !(mmc->caps & MMC_CAP_NONREMOVABLE))
68d1fb7e
AV		 3004 mmc->caps |= MMC_CAP_NEEDS_POLL;
3005
3a48edc4
TK		 3006 /* If there are external regulators, get them */
3007 if (mmc_regulator_get_supply(mmc) == -EPROBE_DEFER)
3008 return -EPROBE_DEFER;
3009
6231f3de 3010 /* If vqmmc regulator and no 1.8V signalling, then there's no UHS */
3a48edc4
TK		 3011 if (!IS_ERR(mmc->supply.vqmmc)) {
3012 ret = regulator_enable(mmc->supply.vqmmc);
3013 if (!regulator_is_supported_voltage(mmc->supply.vqmmc, 1700000,
3014 1950000))
8363c374
KL		 3015 caps[1] &= ~(SDHCI_SUPPORT_SDR104 |
3016 SDHCI_SUPPORT_SDR50 |
3017 SDHCI_SUPPORT_DDR50);
a3361aba
CB		 3018 if (ret) {
3019 pr_warn("%s: Failed to enable vqmmc regulator: %d\n",
3020 mmc_hostname(mmc), ret);
3a48edc4 3021 mmc->supply.vqmmc = NULL;
a3361aba 3022 }
8363c374 3023 }
6231f3de 3024
6a66180a
DD		 3025 if (host->quirks2 & SDHCI_QUIRK2_NO_1_8_V)
3026 caps[1] &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
3027 SDHCI_SUPPORT_DDR50);
3028
4188bba0
AC		 3029 /* Any UHS-I mode in caps implies SDR12 and SDR25 support. */
3030 if (caps[1] & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
3031 SDHCI_SUPPORT_DDR50))
f2119df6
AN		 3032 mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;
3033
3034 /* SDR104 supports also implies SDR50 support */
156e14b1 3035 if (caps[1] & SDHCI_SUPPORT_SDR104) {
f2119df6 3036 mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50;
156e14b1
GC		 3037 /* SD3.0: SDR104 is supported so (for eMMC) the caps2
3038 * field can be promoted to support HS200.
3039 */
adc82855 3040 if (!(host->quirks2 & SDHCI_QUIRK2_BROKEN_HS200)) {
13868bf2 3041 mmc->caps2 |= MMC_CAP2_HS200;
adc82855
CD		 3042 if (IS_ERR(mmc->supply.vqmmc) ||
3043 !regulator_is_supported_voltage
3044 (mmc->supply.vqmmc, 1100000, 1300000))
3045 mmc->caps2 &= ~MMC_CAP2_HS200_1_2V_SDR;
3046 }
156e14b1 3047 } else if (caps[1] & SDHCI_SUPPORT_SDR50)
f2119df6
AN		 3048 mmc->caps |= MMC_CAP_UHS_SDR50;
3049
9107ebbf
MC		 3050 if ((caps[1] & SDHCI_SUPPORT_DDR50) &&
3051 !(host->quirks2 & SDHCI_QUIRK2_BROKEN_DDR50))
f2119df6
AN		 3052 mmc->caps |= MMC_CAP_UHS_DDR50;
3053
069c9f14 3054 /* Does the host need tuning for SDR50? */
b513ea25
AN		 3055 if (caps[1] & SDHCI_USE_SDR50_TUNING)
3056 host->flags |= SDHCI_SDR50_NEEDS_TUNING;
3057
156e14b1 3058 /* Does the host need tuning for SDR104 / HS200? */
069c9f14 3059 if (mmc->caps2 & MMC_CAP2_HS200)
156e14b1 3060 host->flags |= SDHCI_SDR104_NEEDS_TUNING;
069c9f14 3061
d6d50a15
AN		 3062 /* Driver Type(s) (A, C, D) supported by the host */
3063 if (caps[1] & SDHCI_DRIVER_TYPE_A)
3064 mmc->caps |= MMC_CAP_DRIVER_TYPE_A;
3065 if (caps[1] & SDHCI_DRIVER_TYPE_C)
3066 mmc->caps |= MMC_CAP_DRIVER_TYPE_C;
3067 if (caps[1] & SDHCI_DRIVER_TYPE_D)
3068 mmc->caps |= MMC_CAP_DRIVER_TYPE_D;
3069
cf2b5eea
AN		 3070 /* Initial value for re-tuning timer count */
3071 host->tuning_count = (caps[1] & SDHCI_RETUNING_TIMER_COUNT_MASK) >>
3072 SDHCI_RETUNING_TIMER_COUNT_SHIFT;
3073
3074 /*
3075 * In case Re-tuning Timer is not disabled, the actual value of
3076 * re-tuning timer will be 2 ^ (n - 1).
3077 */
3078 if (host->tuning_count)
3079 host->tuning_count = 1 << (host->tuning_count - 1);
3080
3081 /* Re-tuning mode supported by the Host Controller */
3082 host->tuning_mode = (caps[1] & SDHCI_RETUNING_MODE_MASK) >>
3083 SDHCI_RETUNING_MODE_SHIFT;
3084
8f230f45 3085 ocr_avail = 0;
bad37e1a 3086
f2119df6
AN		 3087 /*
3088 * According to SD Host Controller spec v3.00, if the Host System
3089 * can afford more than 150mA, Host Driver should set XPC to 1. Also
3090 * the value is meaningful only if Voltage Support in the Capabilities
3091 * register is set. The actual current value is 4 times the register
3092 * value.
3093 */
3094 max_current_caps = sdhci_readl(host, SDHCI_MAX_CURRENT);
3a48edc4 3095 if (!max_current_caps && !IS_ERR(mmc->supply.vmmc)) {
ae906037 3096 int curr = regulator_get_current_limit(mmc->supply.vmmc);
bad37e1a
PR		 3097 if (curr > 0) {
3098
3099 /* convert to SDHCI_MAX_CURRENT format */
3100 curr = curr/1000; /* convert to mA */
3101 curr = curr/SDHCI_MAX_CURRENT_MULTIPLIER;
3102
3103 curr = min_t(u32, curr, SDHCI_MAX_CURRENT_LIMIT);
3104 max_current_caps =
3105 (curr << SDHCI_MAX_CURRENT_330_SHIFT) |
3106 (curr << SDHCI_MAX_CURRENT_300_SHIFT) |
3107 (curr << SDHCI_MAX_CURRENT_180_SHIFT);
3108 }
3109 }
f2119df6
AN		 3110
3111 if (caps[0] & SDHCI_CAN_VDD_330) {
8f230f45 3112 ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34;
f2119df6 3113
55c4665e 3114 mmc->max_current_330 = ((max_current_caps &
f2119df6
AN		 3115 SDHCI_MAX_CURRENT_330_MASK) >>
3116 SDHCI_MAX_CURRENT_330_SHIFT) *
3117 SDHCI_MAX_CURRENT_MULTIPLIER;
f2119df6
AN		 3118 }
3119 if (caps[0] & SDHCI_CAN_VDD_300) {
8f230f45 3120 ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31;
f2119df6 3121
55c4665e 3122 mmc->max_current_300 = ((max_current_caps &
f2119df6
AN		 3123 SDHCI_MAX_CURRENT_300_MASK) >>
3124 SDHCI_MAX_CURRENT_300_SHIFT) *
3125 SDHCI_MAX_CURRENT_MULTIPLIER;
f2119df6
AN		 3126 }
3127 if (caps[0] & SDHCI_CAN_VDD_180) {
8f230f45
TI		 3128 ocr_avail |= MMC_VDD_165_195;
3129
55c4665e 3130 mmc->max_current_180 = ((max_current_caps &
f2119df6
AN		 3131 SDHCI_MAX_CURRENT_180_MASK) >>
3132 SDHCI_MAX_CURRENT_180_SHIFT) *
3133 SDHCI_MAX_CURRENT_MULTIPLIER;
f2119df6
AN		 3134 }
3135
52221610 3136 /* If OCR set by external regulators, use it instead */
3a48edc4 3137 if (mmc->ocr_avail)
52221610 3138 ocr_avail = mmc->ocr_avail;
3a48edc4 3139
c0b887b6 3140 if (host->ocr_mask)
3a48edc4 3141 ocr_avail &= host->ocr_mask;
c0b887b6 3142
8f230f45
TI		 3143 mmc->ocr_avail = ocr_avail;
3144 mmc->ocr_avail_sdio = ocr_avail;
3145 if (host->ocr_avail_sdio)
3146 mmc->ocr_avail_sdio &= host->ocr_avail_sdio;
3147 mmc->ocr_avail_sd = ocr_avail;
3148 if (host->ocr_avail_sd)
3149 mmc->ocr_avail_sd &= host->ocr_avail_sd;
3150 else /* normal SD controllers don't support 1.8V */
3151 mmc->ocr_avail_sd &= ~MMC_VDD_165_195;
3152 mmc->ocr_avail_mmc = ocr_avail;
3153 if (host->ocr_avail_mmc)
3154 mmc->ocr_avail_mmc &= host->ocr_avail_mmc;
146ad66e
PO		 3155
3156 if (mmc->ocr_avail == 0) {
a3c76eb9 3157 pr_err("%s: Hardware doesn't report any "
b69c9058 3158 "support voltages.\n", mmc_hostname(mmc));
b8c86fc5 3159 return -ENODEV;
146ad66e
PO		 3160 }
3161
d129bceb
PO		 3162 spin_lock_init(&host->lock);
3163
3164 /*
2134a922
PO		 3165 * Maximum number of segments. Depends on if the hardware
3166 * can do scatter/gather or not.
d129bceb 3167 */
2134a922 3168 if (host->flags & SDHCI_USE_ADMA)
a36274e0 3169 mmc->max_segs = 128;
a13abc7b 3170 else if (host->flags & SDHCI_USE_SDMA)
a36274e0 3171 mmc->max_segs = 1;
2134a922 3172 else /* PIO */
a36274e0 3173 mmc->max_segs = 128;
d129bceb
PO		 3174
3175 /*
bab76961 3176 * Maximum number of sectors in one transfer. Limited by DMA boundary
55db890a 3177 * size (512KiB).
d129bceb 3178 */
55db890a 3179 mmc->max_req_size = 524288;
d129bceb
PO		 3180
3181 /*
3182 * Maximum segment size. Could be one segment with the maximum number
2134a922
PO		 3183 * of bytes. When doing hardware scatter/gather, each entry cannot
3184 * be larger than 64 KiB though.
d129bceb 3185 */
30652aa3
OJ		 3186 if (host->flags & SDHCI_USE_ADMA) {
3187 if (host->quirks & SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC)
3188 mmc->max_seg_size = 65535;
3189 else
3190 mmc->max_seg_size = 65536;
3191 } else {
2134a922 3192 mmc->max_seg_size = mmc->max_req_size;
30652aa3 3193 }
d129bceb 3194
fe4a3c7a
PO		 3195 /*
3196 * Maximum block size. This varies from controller to controller and
3197 * is specified in the capabilities register.
3198 */
0633f654
AV		 3199 if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) {
3200 mmc->max_blk_size = 2;
3201 } else {
f2119df6 3202 mmc->max_blk_size = (caps[0] & SDHCI_MAX_BLOCK_MASK) >>
0633f654
AV		 3203 SDHCI_MAX_BLOCK_SHIFT;
3204 if (mmc->max_blk_size >= 3) {
a3c76eb9 3205 pr_warning("%s: Invalid maximum block size, "
0633f654
AV		 3206 "assuming 512 bytes\n", mmc_hostname(mmc));
3207 mmc->max_blk_size = 0;
3208 }
3209 }
3210
3211 mmc->max_blk_size = 512 << mmc->max_blk_size;
fe4a3c7a 3212
55db890a
PO		 3213 /*
3214 * Maximum block count.
3215 */
1388eefd 3216 mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
55db890a 3217
d129bceb
PO		 3218 /*
3219 * Init tasklets.
3220 */
d129bceb
PO		 3221 tasklet_init(&host->finish_tasklet,
3222 sdhci_tasklet_finish, (unsigned long)host);
3223
e4cad1b5 3224 setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host);
d129bceb 3225
cf2b5eea 3226 if (host->version >= SDHCI_SPEC_300) {
b513ea25
AN		 3227 init_waitqueue_head(&host->buf_ready_int);
3228
cf2b5eea
AN		 3229 /* Initialize re-tuning timer */
3230 init_timer(&host->tuning_timer);
3231 host->tuning_timer.data = (unsigned long)host;
3232 host->tuning_timer.function = sdhci_tuning_timer;
3233 }
3234
2af502ca
SG		 3235 sdhci_init(host, 0);
3236
781e989c
RK		 3237 ret = request_threaded_irq(host->irq, sdhci_irq, sdhci_thread_irq,
3238 IRQF_SHARED, mmc_hostname(mmc), host);
0fc81ee3
MB		 3239 if (ret) {
3240 pr_err("%s: Failed to request IRQ %d: %d\n",
3241 mmc_hostname(mmc), host->irq, ret);
8ef1a143 3242 goto untasklet;
0fc81ee3 3243 }
d129bceb 3244
d129bceb
PO		 3245#ifdef CONFIG_MMC_DEBUG
3246 sdhci_dumpregs(host);
3247#endif
3248
f9134319 3249#ifdef SDHCI_USE_LEDS_CLASS
5dbace0c
HS		 3250 snprintf(host->led_name, sizeof(host->led_name),
3251 "%s::", mmc_hostname(mmc));
3252 host->led.name = host->led_name;
2f730fec
PO		 3253 host->led.brightness = LED_OFF;
3254 host->led.default_trigger = mmc_hostname(mmc);
3255 host->led.brightness_set = sdhci_led_control;
3256
b8c86fc5 3257 ret = led_classdev_register(mmc_dev(mmc), &host->led);
0fc81ee3
MB		 3258 if (ret) {
3259 pr_err("%s: Failed to register LED device: %d\n",
3260 mmc_hostname(mmc), ret);
2f730fec 3261 goto reset;
0fc81ee3 3262 }
2f730fec
PO		 3263#endif
3264
5f25a66f
PO		 3265 mmiowb();
3266
d129bceb
PO		 3267 mmc_add_host(mmc);
3268
a3c76eb9 3269 pr_info("%s: SDHCI controller on %s [%s] using %s\n",
d1b26863 3270 mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)),
a13abc7b
RR		 3271 (host->flags & SDHCI_USE_ADMA) ? "ADMA" :
3272 (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO");
d129bceb 3273
7260cf5e
AV		 3274 sdhci_enable_card_detection(host);
3275
d129bceb
PO		 3276 return 0;
3277
f9134319 3278#ifdef SDHCI_USE_LEDS_CLASS
2f730fec 3279reset:
03231f9b 3280 sdhci_do_reset(host, SDHCI_RESET_ALL);
b537f94c
RK		 3281 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
3282 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
2f730fec
PO		 3283 free_irq(host->irq, host);
3284#endif
8ef1a143 3285untasklet:
d129bceb 3286 tasklet_kill(&host->finish_tasklet);
d129bceb
PO		 3287
3288 return ret;
3289}
3290
b8c86fc5 3291EXPORT_SYMBOL_GPL(sdhci_add_host);
d129bceb 3292
1e72859e 3293void sdhci_remove_host(struct sdhci_host *host, int dead)
b8c86fc5 3294{
3a48edc4 3295 struct mmc_host *mmc = host->mmc;
1e72859e
PO		 3296 unsigned long flags;
3297
3298 if (dead) {
3299 spin_lock_irqsave(&host->lock, flags);
3300
3301 host->flags |= SDHCI_DEVICE_DEAD;
3302
3303 if (host->mrq) {
a3c76eb9 3304 pr_err("%s: Controller removed during "
4e743f1f 3305 " transfer!\n", mmc_hostname(mmc));
1e72859e
PO		 3306
3307 host->mrq->cmd->error = -ENOMEDIUM;
3308 tasklet_schedule(&host->finish_tasklet);
3309 }
3310
3311 spin_unlock_irqrestore(&host->lock, flags);
3312 }
3313
7260cf5e
AV		 3314 sdhci_disable_card_detection(host);
3315
4e743f1f 3316 mmc_remove_host(mmc);
d129bceb 3317
f9134319 3318#ifdef SDHCI_USE_LEDS_CLASS
2f730fec
PO		 3319 led_classdev_unregister(&host->led);
3320#endif
3321
1e72859e 3322 if (!dead)
03231f9b 3323 sdhci_do_reset(host, SDHCI_RESET_ALL);
d129bceb 3324
b537f94c
RK		 3325 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
3326 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
d129bceb
PO		 3327 free_irq(host->irq, host);
3328
3329 del_timer_sync(&host->timer);
3330
d129bceb 3331 tasklet_kill(&host->finish_tasklet);
2134a922 3332
3a48edc4
TK		 3333 if (!IS_ERR(mmc->supply.vmmc))
3334 regulator_disable(mmc->supply.vmmc);
9bea3c85 3335
3a48edc4
TK		 3336 if (!IS_ERR(mmc->supply.vqmmc))
3337 regulator_disable(mmc->supply.vqmmc);
6231f3de 3338
d1e49f77 3339 if (host->adma_desc)
4e743f1f 3340 dma_free_coherent(mmc_dev(mmc), ADMA_SIZE,
d1e49f77 3341 host->adma_desc, host->adma_addr);
2134a922
PO		 3342 kfree(host->align_buffer);
3343
3344 host->adma_desc = NULL;
3345 host->align_buffer = NULL;
d129bceb
PO		 3346}
3347
b8c86fc5 3348EXPORT_SYMBOL_GPL(sdhci_remove_host);
d129bceb 3349
b8c86fc5 3350void sdhci_free_host(struct sdhci_host *host)
d129bceb 3351{
b8c86fc5 3352 mmc_free_host(host->mmc);
d129bceb
PO		 3353}
3354
b8c86fc5 3355EXPORT_SYMBOL_GPL(sdhci_free_host);
d129bceb
PO		 3356
3357/*****************************************************************************\
3358 * *
3359 * Driver init/exit *
3360 * *
3361\*****************************************************************************/
3362
3363static int __init sdhci_drv_init(void)
3364{
a3c76eb9 3365 pr_info(DRIVER_NAME
52fbf9c9 3366 ": Secure Digital Host Controller Interface driver\n");
a3c76eb9 3367 pr_info(DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
d129bceb 3368
b8c86fc5 3369 return 0;
d129bceb
PO		 3370}
3371
3372static void __exit sdhci_drv_exit(void)
3373{
d129bceb
PO		 3374}
3375
3376module_init(sdhci_drv_init);
3377module_exit(sdhci_drv_exit);
3378
df673b22 3379module_param(debug_quirks, uint, 0444);
66fd8ad5 3380module_param(debug_quirks2, uint, 0444);
67435274 3381
32710e8f 3382MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
b8c86fc5 3383MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver");
d129bceb 3384MODULE_LICENSE("GPL");
67435274 3385
df673b22 3386MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");
66fd8ad5 3387MODULE_PARM_DESC(debug_quirks2, "Force certain other quirks.");
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