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mmc: sdhci: Allow for finishing multiple requests
[mirror_ubuntu-artful-kernel.git] / drivers / mmc / host / sdhci.c
CommitLineData
d129bceb 1/*
70f10482 2 * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
d129bceb 3 *
b69c9058 4 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
d129bceb
PO		 5 *
6 * This program is free software; you can redistribute it and/or modify
643f720c
PO		 7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or (at
9 * your option) any later version.
84c46a53
PO		 10 *
11 * Thanks to the following companies for their support:
12 *
13 * - JMicron (hardware and technical support)
d129bceb
PO		 14 */
15
d129bceb
PO		 16#include <linux/delay.h>
17#include <linux/highmem.h>
b8c86fc5 18#include <linux/io.h>
88b47679 19#include <linux/module.h>
d129bceb 20#include <linux/dma-mapping.h>
5a0e3ad6 21#include <linux/slab.h>
11763609 22#include <linux/scatterlist.h>
9bea3c85 23#include <linux/regulator/consumer.h>
66fd8ad5 24#include <linux/pm_runtime.h>
d129bceb 25
2f730fec
PO		 26#include <linux/leds.h>
27
22113efd 28#include <linux/mmc/mmc.h>
d129bceb 29#include <linux/mmc/host.h>
473b095a 30#include <linux/mmc/card.h>
85cc1c33 31#include <linux/mmc/sdio.h>
bec9d4e5 32#include <linux/mmc/slot-gpio.h>
d129bceb 33
d129bceb
PO		 34#include "sdhci.h"
35
36#define DRIVER_NAME "sdhci"
d129bceb 37
d129bceb 38#define DBG(f, x...) \
c6563178 39 pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
d129bceb 40
b513ea25
AN		 41#define MAX_TUNING_LOOP 40
42
df673b22 43static unsigned int debug_quirks = 0;
66fd8ad5 44static unsigned int debug_quirks2;
67435274 45
d129bceb
PO		 46static void sdhci_finish_data(struct sdhci_host *);
47
52983382 48static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable);
d129bceb
PO		 49
50static void sdhci_dumpregs(struct sdhci_host *host)
51{
a7c53671
CD		 52 pr_err(DRIVER_NAME ": =========== REGISTER DUMP (%s)===========\n",
53 mmc_hostname(host->mmc));
d129bceb 54
a7c53671
CD		 55 pr_err(DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n",
56 sdhci_readl(host, SDHCI_DMA_ADDRESS),
57 sdhci_readw(host, SDHCI_HOST_VERSION));
58 pr_err(DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n",
59 sdhci_readw(host, SDHCI_BLOCK_SIZE),
60 sdhci_readw(host, SDHCI_BLOCK_COUNT));
61 pr_err(DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
62 sdhci_readl(host, SDHCI_ARGUMENT),
63 sdhci_readw(host, SDHCI_TRANSFER_MODE));
64 pr_err(DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n",
65 sdhci_readl(host, SDHCI_PRESENT_STATE),
66 sdhci_readb(host, SDHCI_HOST_CONTROL));
67 pr_err(DRIVER_NAME ": Power: 0x%08x | Blk gap: 0x%08x\n",
68 sdhci_readb(host, SDHCI_POWER_CONTROL),
69 sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL));
70 pr_err(DRIVER_NAME ": Wake-up: 0x%08x | Clock: 0x%08x\n",
71 sdhci_readb(host, SDHCI_WAKE_UP_CONTROL),
72 sdhci_readw(host, SDHCI_CLOCK_CONTROL));
73 pr_err(DRIVER_NAME ": Timeout: 0x%08x | Int stat: 0x%08x\n",
74 sdhci_readb(host, SDHCI_TIMEOUT_CONTROL),
75 sdhci_readl(host, SDHCI_INT_STATUS));
76 pr_err(DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
77 sdhci_readl(host, SDHCI_INT_ENABLE),
78 sdhci_readl(host, SDHCI_SIGNAL_ENABLE));
79 pr_err(DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
80 sdhci_readw(host, SDHCI_ACMD12_ERR),
81 sdhci_readw(host, SDHCI_SLOT_INT_STATUS));
82 pr_err(DRIVER_NAME ": Caps: 0x%08x | Caps_1: 0x%08x\n",
83 sdhci_readl(host, SDHCI_CAPABILITIES),
84 sdhci_readl(host, SDHCI_CAPABILITIES_1));
85 pr_err(DRIVER_NAME ": Cmd: 0x%08x | Max curr: 0x%08x\n",
86 sdhci_readw(host, SDHCI_COMMAND),
87 sdhci_readl(host, SDHCI_MAX_CURRENT));
88 pr_err(DRIVER_NAME ": Host ctl2: 0x%08x\n",
89 sdhci_readw(host, SDHCI_HOST_CONTROL2));
d129bceb 90
e57a5f61
AH		 91 if (host->flags & SDHCI_USE_ADMA) {
92 if (host->flags & SDHCI_USE_64_BIT_DMA)
a7c53671
CD		 93 pr_err(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x%08x\n",
94 readl(host->ioaddr + SDHCI_ADMA_ERROR),
95 readl(host->ioaddr + SDHCI_ADMA_ADDRESS_HI),
96 readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
e57a5f61 97 else
a7c53671
CD		 98 pr_err(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n",
99 readl(host->ioaddr + SDHCI_ADMA_ERROR),
100 readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
e57a5f61 101 }
be3f4ae0 102
a7c53671 103 pr_err(DRIVER_NAME ": ===========================================\n");
d129bceb
PO		 104}
105
106/*****************************************************************************\
107 * *
108 * Low level functions *
109 * *
110\*****************************************************************************/
111
56a590dc
AH		 112static inline bool sdhci_data_line_cmd(struct mmc_command *cmd)
113{
114 return cmd->data || cmd->flags & MMC_RSP_BUSY;
115}
116
7260cf5e
AV		 117static void sdhci_set_card_detection(struct sdhci_host *host, bool enable)
118{
5b4f1f6c 119 u32 present;
7260cf5e 120
c79396c1 121 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) ||
860951c5 122 !mmc_card_is_removable(host->mmc))
66fd8ad5
AH		 123 return;
124
5b4f1f6c
RK		 125 if (enable) {
126 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
127 SDHCI_CARD_PRESENT;
d25928d1 128
5b4f1f6c
RK		 129 host->ier |= present ? SDHCI_INT_CARD_REMOVE :
130 SDHCI_INT_CARD_INSERT;
131 } else {
132 host->ier &= ~(SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT);
133 }
b537f94c
RK		 134
135 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
136 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
7260cf5e
AV		 137}
138
139static void sdhci_enable_card_detection(struct sdhci_host *host)
140{
141 sdhci_set_card_detection(host, true);
142}
143
144static void sdhci_disable_card_detection(struct sdhci_host *host)
145{
146 sdhci_set_card_detection(host, false);
147}
148
02d0b685
UH		 149static void sdhci_runtime_pm_bus_on(struct sdhci_host *host)
150{
151 if (host->bus_on)
152 return;
153 host->bus_on = true;
154 pm_runtime_get_noresume(host->mmc->parent);
155}
156
157static void sdhci_runtime_pm_bus_off(struct sdhci_host *host)
158{
159 if (!host->bus_on)
160 return;
161 host->bus_on = false;
162 pm_runtime_put_noidle(host->mmc->parent);
163}
164
03231f9b 165void sdhci_reset(struct sdhci_host *host, u8 mask)
d129bceb 166{
e16514d8 167 unsigned long timeout;
393c1a34 168
4e4141a5 169 sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
d129bceb 170
f0710a55 171 if (mask & SDHCI_RESET_ALL) {
d129bceb 172 host->clock = 0;
f0710a55
AH		 173 /* Reset-all turns off SD Bus Power */
174 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
175 sdhci_runtime_pm_bus_off(host);
176 }
d129bceb 177
e16514d8
PO		 178 /* Wait max 100 ms */
179 timeout = 100;
180
181 /* hw clears the bit when it's done */
4e4141a5 182 while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
e16514d8 183 if (timeout == 0) {
a3c76eb9 184 pr_err("%s: Reset 0x%x never completed.\n",
e16514d8
PO		 185 mmc_hostname(host->mmc), (int)mask);
186 sdhci_dumpregs(host);
187 return;
188 }
189 timeout--;
190 mdelay(1);
d129bceb 191 }
03231f9b
RK		 192}
193EXPORT_SYMBOL_GPL(sdhci_reset);
194
195static void sdhci_do_reset(struct sdhci_host *host, u8 mask)
196{
197 if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
d3940f27
AH		 198 struct mmc_host *mmc = host->mmc;
199
200 if (!mmc->ops->get_cd(mmc))
03231f9b
RK		 201 return;
202 }
063a9dbb 203
03231f9b 204 host->ops->reset(host, mask);
393c1a34 205
da91a8f9
RK		 206 if (mask & SDHCI_RESET_ALL) {
207 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
208 if (host->ops->enable_dma)
209 host->ops->enable_dma(host);
210 }
211
212 /* Resetting the controller clears many */
213 host->preset_enabled = false;
3abc1e80 214 }
d129bceb
PO		 215}
216
2f4cbb3d 217static void sdhci_init(struct sdhci_host *host, int soft)
d129bceb 218{
d3940f27
AH		 219 struct mmc_host *mmc = host->mmc;
220
2f4cbb3d 221 if (soft)
03231f9b 222 sdhci_do_reset(host, SDHCI_RESET_CMD|SDHCI_RESET_DATA);
2f4cbb3d 223 else
03231f9b 224 sdhci_do_reset(host, SDHCI_RESET_ALL);
d129bceb 225
b537f94c
RK		 226 host->ier = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
227 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT |
228 SDHCI_INT_INDEX | SDHCI_INT_END_BIT | SDHCI_INT_CRC |
229 SDHCI_INT_TIMEOUT | SDHCI_INT_DATA_END |
230 SDHCI_INT_RESPONSE;
231
232 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
233 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2f4cbb3d
NP		 234
235 if (soft) {
236 /* force clock reconfiguration */
237 host->clock = 0;
d3940f27 238 mmc->ops->set_ios(mmc, &mmc->ios);
2f4cbb3d 239 }
7260cf5e 240}
d129bceb 241
7260cf5e
AV		 242static void sdhci_reinit(struct sdhci_host *host)
243{
2f4cbb3d 244 sdhci_init(host, 0);
7260cf5e 245 sdhci_enable_card_detection(host);
d129bceb
PO		 246}
247
061d17a6 248static void __sdhci_led_activate(struct sdhci_host *host)
d129bceb
PO		 249{
250 u8 ctrl;
251
4e4141a5 252 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
d129bceb 253 ctrl |= SDHCI_CTRL_LED;
4e4141a5 254 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d129bceb
PO		 255}
256
061d17a6 257static void __sdhci_led_deactivate(struct sdhci_host *host)
d129bceb
PO		 258{
259 u8 ctrl;
260
4e4141a5 261 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
d129bceb 262 ctrl &= ~SDHCI_CTRL_LED;
4e4141a5 263 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d129bceb
PO		 264}
265
4f78230f 266#if IS_REACHABLE(CONFIG_LEDS_CLASS)
2f730fec 267static void sdhci_led_control(struct led_classdev *led,
061d17a6 268 enum led_brightness brightness)
2f730fec
PO		 269{
270 struct sdhci_host *host = container_of(led, struct sdhci_host, led);
271 unsigned long flags;
272
273 spin_lock_irqsave(&host->lock, flags);
274
66fd8ad5
AH		 275 if (host->runtime_suspended)
276 goto out;
277
2f730fec 278 if (brightness == LED_OFF)
061d17a6 279 __sdhci_led_deactivate(host);
2f730fec 280 else
061d17a6 281 __sdhci_led_activate(host);
66fd8ad5 282out:
2f730fec
PO		 283 spin_unlock_irqrestore(&host->lock, flags);
284}
061d17a6
AH		 285
286static int sdhci_led_register(struct sdhci_host *host)
287{
288 struct mmc_host *mmc = host->mmc;
289
290 snprintf(host->led_name, sizeof(host->led_name),
291 "%s::", mmc_hostname(mmc));
292
293 host->led.name = host->led_name;
294 host->led.brightness = LED_OFF;
295 host->led.default_trigger = mmc_hostname(mmc);
296 host->led.brightness_set = sdhci_led_control;
297
298 return led_classdev_register(mmc_dev(mmc), &host->led);
299}
300
301static void sdhci_led_unregister(struct sdhci_host *host)
302{
303 led_classdev_unregister(&host->led);
304}
305
306static inline void sdhci_led_activate(struct sdhci_host *host)
307{
308}
309
310static inline void sdhci_led_deactivate(struct sdhci_host *host)
311{
312}
313
314#else
315
316static inline int sdhci_led_register(struct sdhci_host *host)
317{
318 return 0;
319}
320
321static inline void sdhci_led_unregister(struct sdhci_host *host)
322{
323}
324
325static inline void sdhci_led_activate(struct sdhci_host *host)
326{
327 __sdhci_led_activate(host);
328}
329
330static inline void sdhci_led_deactivate(struct sdhci_host *host)
331{
332 __sdhci_led_deactivate(host);
333}
334
2f730fec
PO		 335#endif
336
d129bceb
PO		 337/*****************************************************************************\
338 * *
339 * Core functions *
340 * *
341\*****************************************************************************/
342
a406f5a3 343static void sdhci_read_block_pio(struct sdhci_host *host)
d129bceb 344{
7659150c
PO		 345 unsigned long flags;
346 size_t blksize, len, chunk;
7244b85b 347 u32 uninitialized_var(scratch);
7659150c 348 u8 *buf;
d129bceb 349
a406f5a3 350 DBG("PIO reading\n");
d129bceb 351
a406f5a3 352 blksize = host->data->blksz;
7659150c 353 chunk = 0;
d129bceb 354
7659150c 355 local_irq_save(flags);
d129bceb 356
a406f5a3 357 while (blksize) {
bf3a35ac 358 BUG_ON(!sg_miter_next(&host->sg_miter));
d129bceb 359
7659150c 360 len = min(host->sg_miter.length, blksize);
d129bceb 361
7659150c
PO		 362 blksize -= len;
363 host->sg_miter.consumed = len;
14d836e7 364
7659150c 365 buf = host->sg_miter.addr;
d129bceb 366
7659150c
PO		 367 while (len) {
368 if (chunk == 0) {
4e4141a5 369 scratch = sdhci_readl(host, SDHCI_BUFFER);
7659150c 370 chunk = 4;
a406f5a3 371 }
7659150c
PO		 372
373 *buf = scratch & 0xFF;
374
375 buf++;
376 scratch >>= 8;
377 chunk--;
378 len--;
d129bceb 379 }
a406f5a3 380 }
7659150c
PO		 381
382 sg_miter_stop(&host->sg_miter);
383
384 local_irq_restore(flags);
a406f5a3 385}
d129bceb 386
a406f5a3
PO		 387static void sdhci_write_block_pio(struct sdhci_host *host)
388{
7659150c
PO		 389 unsigned long flags;
390 size_t blksize, len, chunk;
391 u32 scratch;
392 u8 *buf;
d129bceb 393
a406f5a3
PO		 394 DBG("PIO writing\n");
395
396 blksize = host->data->blksz;
7659150c
PO		 397 chunk = 0;
398 scratch = 0;
d129bceb 399
7659150c 400 local_irq_save(flags);
d129bceb 401
a406f5a3 402 while (blksize) {
bf3a35ac 403 BUG_ON(!sg_miter_next(&host->sg_miter));
a406f5a3 404
7659150c
PO		 405 len = min(host->sg_miter.length, blksize);
406
407 blksize -= len;
408 host->sg_miter.consumed = len;
409
410 buf = host->sg_miter.addr;
d129bceb 411
7659150c
PO		 412 while (len) {
413 scratch |= (u32)*buf << (chunk * 8);
414
415 buf++;
416 chunk++;
417 len--;
418
419 if ((chunk == 4) || ((len == 0) && (blksize == 0))) {
4e4141a5 420 sdhci_writel(host, scratch, SDHCI_BUFFER);
7659150c
PO		 421 chunk = 0;
422 scratch = 0;
d129bceb 423 }
d129bceb
PO		 424 }
425 }
7659150c
PO		 426
427 sg_miter_stop(&host->sg_miter);
428
429 local_irq_restore(flags);
a406f5a3
PO		 430}
431
432static void sdhci_transfer_pio(struct sdhci_host *host)
433{
434 u32 mask;
435
7659150c 436 if (host->blocks == 0)
a406f5a3
PO		 437 return;
438
439 if (host->data->flags & MMC_DATA_READ)
440 mask = SDHCI_DATA_AVAILABLE;
441 else
442 mask = SDHCI_SPACE_AVAILABLE;
443
4a3cba32
PO		 444 /*
445 * Some controllers (JMicron JMB38x) mess up the buffer bits
446 * for transfers < 4 bytes. As long as it is just one block,
447 * we can ignore the bits.
448 */
449 if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) &&
450 (host->data->blocks == 1))
451 mask = ~0;
452
4e4141a5 453 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
3e3bf207
AV		 454 if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY)
455 udelay(100);
456
a406f5a3
PO		 457 if (host->data->flags & MMC_DATA_READ)
458 sdhci_read_block_pio(host);
459 else
460 sdhci_write_block_pio(host);
d129bceb 461
7659150c
PO		 462 host->blocks--;
463 if (host->blocks == 0)
a406f5a3 464 break;
a406f5a3 465 }
d129bceb 466
a406f5a3 467 DBG("PIO transfer complete.\n");
d129bceb
PO		 468}
469
48857d9b 470static int sdhci_pre_dma_transfer(struct sdhci_host *host,
c0999b72 471 struct mmc_data *data, int cookie)
48857d9b
RK		 472{
473 int sg_count;
474
94538e51
RK		 475 /*
476 * If the data buffers are already mapped, return the previous
477 * dma_map_sg() result.
478 */
479 if (data->host_cookie == COOKIE_PRE_MAPPED)
48857d9b 480 return data->sg_count;
48857d9b
RK		 481
482 sg_count = dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
483 data->flags & MMC_DATA_WRITE ?
484 DMA_TO_DEVICE : DMA_FROM_DEVICE);
485
486 if (sg_count == 0)
487 return -ENOSPC;
488
489 data->sg_count = sg_count;
c0999b72 490 data->host_cookie = cookie;
48857d9b
RK		 491
492 return sg_count;
493}
494
2134a922
PO		 495static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags)
496{
497 local_irq_save(*flags);
482fce99 498 return kmap_atomic(sg_page(sg)) + sg->offset;
2134a922
PO		 499}
500
501static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags)
502{
482fce99 503 kunmap_atomic(buffer);
2134a922
PO		 504 local_irq_restore(*flags);
505}
506
e57a5f61
AH		 507static void sdhci_adma_write_desc(struct sdhci_host *host, void *desc,
508 dma_addr_t addr, int len, unsigned cmd)
118cd17d 509{
e57a5f61 510 struct sdhci_adma2_64_desc *dma_desc = desc;
118cd17d 511
e57a5f61 512 /* 32-bit and 64-bit descriptors have these members in same position */
0545230f
AH		 513 dma_desc->cmd = cpu_to_le16(cmd);
514 dma_desc->len = cpu_to_le16(len);
e57a5f61
AH		 515 dma_desc->addr_lo = cpu_to_le32((u32)addr);
516
517 if (host->flags & SDHCI_USE_64_BIT_DMA)
518 dma_desc->addr_hi = cpu_to_le32((u64)addr >> 32);
118cd17d
BD		 519}
520
b5ffa674
AH		 521static void sdhci_adma_mark_end(void *desc)
522{
e57a5f61 523 struct sdhci_adma2_64_desc *dma_desc = desc;
b5ffa674 524
e57a5f61 525 /* 32-bit and 64-bit descriptors have 'cmd' in same position */
0545230f 526 dma_desc->cmd |= cpu_to_le16(ADMA2_END);
b5ffa674
AH		 527}
528
60c64762
RK		 529static void sdhci_adma_table_pre(struct sdhci_host *host,
530 struct mmc_data *data, int sg_count)
2134a922 531{
2134a922 532 struct scatterlist *sg;
2134a922 533 unsigned long flags;
acc3ad13
RK		 534 dma_addr_t addr, align_addr;
535 void *desc, *align;
536 char *buffer;
537 int len, offset, i;
2134a922
PO		 538
539 /*
540 * The spec does not specify endianness of descriptor table.
541 * We currently guess that it is LE.
542 */
543
60c64762 544 host->sg_count = sg_count;
2134a922 545
4efaa6fb 546 desc = host->adma_table;
2134a922
PO		 547 align = host->align_buffer;
548
549 align_addr = host->align_addr;
550
551 for_each_sg(data->sg, sg, host->sg_count, i) {
552 addr = sg_dma_address(sg);
553 len = sg_dma_len(sg);
554
555 /*
acc3ad13
RK		 556 * The SDHCI specification states that ADMA addresses must
557 * be 32-bit aligned. If they aren't, then we use a bounce
558 * buffer for the (up to three) bytes that screw up the
2134a922
PO		 559 * alignment.
560 */
04a5ae6f
AH		 561 offset = (SDHCI_ADMA2_ALIGN - (addr & SDHCI_ADMA2_MASK)) &
562 SDHCI_ADMA2_MASK;
2134a922
PO		 563 if (offset) {
564 if (data->flags & MMC_DATA_WRITE) {
565 buffer = sdhci_kmap_atomic(sg, &flags);
566 memcpy(align, buffer, offset);
567 sdhci_kunmap_atomic(buffer, &flags);
568 }
569
118cd17d 570 /* tran, valid */
e57a5f61 571 sdhci_adma_write_desc(host, desc, align_addr, offset,
739d46dc 572 ADMA2_TRAN_VALID);
2134a922
PO		 573
574 BUG_ON(offset > 65536);
575
04a5ae6f
AH		 576 align += SDHCI_ADMA2_ALIGN;
577 align_addr += SDHCI_ADMA2_ALIGN;
2134a922 578
76fe379a 579 desc += host->desc_sz;
2134a922
PO		 580
581 addr += offset;
582 len -= offset;
583 }
584
2134a922
PO		 585 BUG_ON(len > 65536);
586
347ea32d
AH		 587 if (len) {
588 /* tran, valid */
589 sdhci_adma_write_desc(host, desc, addr, len,
590 ADMA2_TRAN_VALID);
591 desc += host->desc_sz;
592 }
2134a922
PO		 593
594 /*
595 * If this triggers then we have a calculation bug
596 * somewhere. :/
597 */
76fe379a 598 WARN_ON((desc - host->adma_table) >= host->adma_table_sz);
2134a922
PO		 599 }
600
70764a90 601 if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) {
acc3ad13 602 /* Mark the last descriptor as the terminating descriptor */
4efaa6fb 603 if (desc != host->adma_table) {
76fe379a 604 desc -= host->desc_sz;
b5ffa674 605 sdhci_adma_mark_end(desc);
70764a90
TA		 606 }
607 } else {
acc3ad13 608 /* Add a terminating entry - nop, end, valid */
e57a5f61 609 sdhci_adma_write_desc(host, desc, 0, 0, ADMA2_NOP_END_VALID);
70764a90 610 }
2134a922
PO		 611}
612
613static void sdhci_adma_table_post(struct sdhci_host *host,
614 struct mmc_data *data)
615{
2134a922
PO		 616 struct scatterlist *sg;
617 int i, size;
1c3d5f6d 618 void *align;
2134a922
PO		 619 char *buffer;
620 unsigned long flags;
621
47fa9613
RK		 622 if (data->flags & MMC_DATA_READ) {
623 bool has_unaligned = false;
de0b65a7 624
47fa9613
RK		 625 /* Do a quick scan of the SG list for any unaligned mappings */
626 for_each_sg(data->sg, sg, host->sg_count, i)
627 if (sg_dma_address(sg) & SDHCI_ADMA2_MASK) {
628 has_unaligned = true;
629 break;
630 }
2134a922 631
47fa9613
RK		 632 if (has_unaligned) {
633 dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
f55c98f7 634 data->sg_len, DMA_FROM_DEVICE);
2134a922 635
47fa9613 636 align = host->align_buffer;
2134a922 637
47fa9613
RK		 638 for_each_sg(data->sg, sg, host->sg_count, i) {
639 if (sg_dma_address(sg) & SDHCI_ADMA2_MASK) {
640 size = SDHCI_ADMA2_ALIGN -
641 (sg_dma_address(sg) & SDHCI_ADMA2_MASK);
642
643 buffer = sdhci_kmap_atomic(sg, &flags);
644 memcpy(buffer, align, size);
645 sdhci_kunmap_atomic(buffer, &flags);
2134a922 646
47fa9613
RK		 647 align += SDHCI_ADMA2_ALIGN;
648 }
2134a922
PO		 649 }
650 }
651 }
2134a922
PO		 652}
653
a3c7778f 654static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd)
d129bceb 655{
1c8cde92 656 u8 count;
a3c7778f 657 struct mmc_data *data = cmd->data;
1c8cde92 658 unsigned target_timeout, current_timeout;
d129bceb 659
ee53ab5d
PO		 660 /*
661 * If the host controller provides us with an incorrect timeout
662 * value, just skip the check and use 0xE. The hardware may take
663 * longer to time out, but that's much better than having a too-short
664 * timeout value.
665 */
11a2f1b7 666 if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL)
ee53ab5d 667 return 0xE;
e538fbe8 668
a3c7778f 669 /* Unspecified timeout, assume max */
1d4d7744 670 if (!data && !cmd->busy_timeout)
a3c7778f 671 return 0xE;
d129bceb 672
a3c7778f
AW		 673 /* timeout in us */
674 if (!data)
1d4d7744 675 target_timeout = cmd->busy_timeout * 1000;
78a2ca27 676 else {
fafcfda9 677 target_timeout = DIV_ROUND_UP(data->timeout_ns, 1000);
7f05538a
RK		 678 if (host->clock && data->timeout_clks) {
679 unsigned long long val;
680
681 /*
682 * data->timeout_clks is in units of clock cycles.
683 * host->clock is in Hz. target_timeout is in us.
684 * Hence, us = 1000000 * cycles / Hz. Round up.
685 */
686 val = 1000000 * data->timeout_clks;
687 if (do_div(val, host->clock))
688 target_timeout++;
689 target_timeout += val;
690 }
78a2ca27 691 }
81b39802 692
1c8cde92
PO		 693 /*
694 * Figure out needed cycles.
695 * We do this in steps in order to fit inside a 32 bit int.
696 * The first step is the minimum timeout, which will have a
697 * minimum resolution of 6 bits:
698 * (1) 2^13*1000 > 2^22,
699 * (2) host->timeout_clk < 2^16
700 * =>
701 * (1) / (2) > 2^6
702 */
703 count = 0;
704 current_timeout = (1 << 13) * 1000 / host->timeout_clk;
705 while (current_timeout < target_timeout) {
706 count++;
707 current_timeout <<= 1;
708 if (count >= 0xF)
709 break;
710 }
711
712 if (count >= 0xF) {
09eeff52
CB		 713 DBG("%s: Too large timeout 0x%x requested for CMD%d!\n",
714 mmc_hostname(host->mmc), count, cmd->opcode);
1c8cde92
PO		 715 count = 0xE;
716 }
717
ee53ab5d
PO		 718 return count;
719}
720
6aa943ab
AV		 721static void sdhci_set_transfer_irqs(struct sdhci_host *host)
722{
723 u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL;
724 u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR;
725
726 if (host->flags & SDHCI_REQ_USE_DMA)
b537f94c 727 host->ier = (host->ier & ~pio_irqs) | dma_irqs;
6aa943ab 728 else
b537f94c
RK		 729 host->ier = (host->ier & ~dma_irqs) | pio_irqs;
730
731 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
732 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
6aa943ab
AV		 733}
734
b45e668a 735static void sdhci_set_timeout(struct sdhci_host *host, struct mmc_command *cmd)
ee53ab5d
PO		 736{
737 u8 count;
b45e668a
AD		 738
739 if (host->ops->set_timeout) {
740 host->ops->set_timeout(host, cmd);
741 } else {
742 count = sdhci_calc_timeout(host, cmd);
743 sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
744 }
745}
746
747static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd)
748{
2134a922 749 u8 ctrl;
a3c7778f 750 struct mmc_data *data = cmd->data;
ee53ab5d 751
56a590dc 752 if (sdhci_data_line_cmd(cmd))
b45e668a 753 sdhci_set_timeout(host, cmd);
a3c7778f
AW		 754
755 if (!data)
ee53ab5d
PO		 756 return;
757
43dea098
AH		 758 WARN_ON(host->data);
759
ee53ab5d
PO		 760 /* Sanity checks */
761 BUG_ON(data->blksz * data->blocks > 524288);
762 BUG_ON(data->blksz > host->mmc->max_blk_size);
763 BUG_ON(data->blocks > 65535);
764
765 host->data = data;
766 host->data_early = 0;
f6a03cbf 767 host->data->bytes_xfered = 0;
ee53ab5d 768
fce14421 769 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2134a922 770 struct scatterlist *sg;
df953925 771 unsigned int length_mask, offset_mask;
a0eaf0f9 772 int i;
2134a922 773
fce14421
RK		 774 host->flags |= SDHCI_REQ_USE_DMA;
775
776 /*
777 * FIXME: This doesn't account for merging when mapping the
778 * scatterlist.
779 *
780 * The assumption here being that alignment and lengths are
781 * the same after DMA mapping to device address space.
782 */
a0eaf0f9 783 length_mask = 0;
df953925 784 offset_mask = 0;
2134a922 785 if (host->flags & SDHCI_USE_ADMA) {
df953925 786 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE) {
a0eaf0f9 787 length_mask = 3;
df953925
RK		 788 /*
789 * As we use up to 3 byte chunks to work
790 * around alignment problems, we need to
791 * check the offset as well.
792 */
793 offset_mask = 3;
794 }
2134a922
PO		 795 } else {
796 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE)
a0eaf0f9 797 length_mask = 3;
df953925
RK		 798 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR)
799 offset_mask = 3;
2134a922
PO		 800 }
801
df953925 802 if (unlikely(length_mask | offset_mask)) {
2134a922 803 for_each_sg(data->sg, sg, data->sg_len, i) {
a0eaf0f9 804 if (sg->length & length_mask) {
2e4456f0 805 DBG("Reverting to PIO because of transfer size (%d)\n",
a0eaf0f9 806 sg->length);
2134a922
PO		 807 host->flags &= ~SDHCI_REQ_USE_DMA;
808 break;
809 }
a0eaf0f9 810 if (sg->offset & offset_mask) {
2e4456f0 811 DBG("Reverting to PIO because of bad alignment\n");
2134a922
PO		 812 host->flags &= ~SDHCI_REQ_USE_DMA;
813 break;
814 }
815 }
816 }
817 }
818
8f1934ce 819 if (host->flags & SDHCI_REQ_USE_DMA) {
c0999b72 820 int sg_cnt = sdhci_pre_dma_transfer(host, data, COOKIE_MAPPED);
60c64762
RK		 821
822 if (sg_cnt <= 0) {
823 /*
824 * This only happens when someone fed
825 * us an invalid request.
826 */
827 WARN_ON(1);
828 host->flags &= ~SDHCI_REQ_USE_DMA;
829 } else if (host->flags & SDHCI_USE_ADMA) {
830 sdhci_adma_table_pre(host, data, sg_cnt);
831
832 sdhci_writel(host, host->adma_addr, SDHCI_ADMA_ADDRESS);
833 if (host->flags & SDHCI_USE_64_BIT_DMA)
834 sdhci_writel(host,
835 (u64)host->adma_addr >> 32,
836 SDHCI_ADMA_ADDRESS_HI);
8f1934ce 837 } else {
60c64762
RK		 838 WARN_ON(sg_cnt != 1);
839 sdhci_writel(host, sg_dma_address(data->sg),
840 SDHCI_DMA_ADDRESS);
8f1934ce
PO		 841 }
842 }
843
2134a922
PO		 844 /*
845 * Always adjust the DMA selection as some controllers
846 * (e.g. JMicron) can't do PIO properly when the selection
847 * is ADMA.
848 */
849 if (host->version >= SDHCI_SPEC_200) {
4e4141a5 850 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
2134a922
PO		 851 ctrl &= ~SDHCI_CTRL_DMA_MASK;
852 if ((host->flags & SDHCI_REQ_USE_DMA) &&
e57a5f61
AH		 853 (host->flags & SDHCI_USE_ADMA)) {
854 if (host->flags & SDHCI_USE_64_BIT_DMA)
855 ctrl |= SDHCI_CTRL_ADMA64;
856 else
857 ctrl |= SDHCI_CTRL_ADMA32;
858 } else {
2134a922 859 ctrl |= SDHCI_CTRL_SDMA;
e57a5f61 860 }
4e4141a5 861 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
c9fddbc4
PO		 862 }
863
8f1934ce 864 if (!(host->flags & SDHCI_REQ_USE_DMA)) {
da60a91d
SAS		 865 int flags;
866
867 flags = SG_MITER_ATOMIC;
868 if (host->data->flags & MMC_DATA_READ)
869 flags |= SG_MITER_TO_SG;
870 else
871 flags |= SG_MITER_FROM_SG;
872 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
7659150c 873 host->blocks = data->blocks;
d129bceb 874 }
c7fa9963 875
6aa943ab
AV		 876 sdhci_set_transfer_irqs(host);
877
f6a03cbf
MV		 878 /* Set the DMA boundary value and block size */
879 sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
880 data->blksz), SDHCI_BLOCK_SIZE);
4e4141a5 881 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
c7fa9963
PO		 882}
883
884static void sdhci_set_transfer_mode(struct sdhci_host *host,
e89d456f 885 struct mmc_command *cmd)
c7fa9963 886{
d3fc5d71 887 u16 mode = 0;
e89d456f 888 struct mmc_data *data = cmd->data;
c7fa9963 889
2b558c13 890 if (data == NULL) {
9b8ffea6
VW		 891 if (host->quirks2 &
892 SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD) {
893 sdhci_writew(host, 0x0, SDHCI_TRANSFER_MODE);
894 } else {
2b558c13 895 /* clear Auto CMD settings for no data CMDs */
9b8ffea6
VW		 896 mode = sdhci_readw(host, SDHCI_TRANSFER_MODE);
897 sdhci_writew(host, mode & ~(SDHCI_TRNS_AUTO_CMD12 |
2b558c13 898 SDHCI_TRNS_AUTO_CMD23), SDHCI_TRANSFER_MODE);
9b8ffea6 899 }
c7fa9963 900 return;
2b558c13 901 }
c7fa9963 902
e538fbe8
PO		 903 WARN_ON(!host->data);
904
d3fc5d71
VY		 905 if (!(host->quirks2 & SDHCI_QUIRK2_SUPPORT_SINGLE))
906 mode = SDHCI_TRNS_BLK_CNT_EN;
907
e89d456f 908 if (mmc_op_multi(cmd->opcode) || data->blocks > 1) {
d3fc5d71 909 mode = SDHCI_TRNS_BLK_CNT_EN | SDHCI_TRNS_MULTI;
e89d456f
AW		 910 /*
911 * If we are sending CMD23, CMD12 never gets sent
912 * on successful completion (so no Auto-CMD12).
913 */
a4c73aba 914 if (!cmd->mrq->sbc && (host->flags & SDHCI_AUTO_CMD12) &&
85cc1c33 915 (cmd->opcode != SD_IO_RW_EXTENDED))
e89d456f 916 mode |= SDHCI_TRNS_AUTO_CMD12;
a4c73aba 917 else if (cmd->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) {
8edf6371 918 mode |= SDHCI_TRNS_AUTO_CMD23;
a4c73aba 919 sdhci_writel(host, cmd->mrq->sbc->arg, SDHCI_ARGUMENT2);
8edf6371 920 }
c4512f79 921 }
8edf6371 922
c7fa9963
PO		 923 if (data->flags & MMC_DATA_READ)
924 mode |= SDHCI_TRNS_READ;
c9fddbc4 925 if (host->flags & SDHCI_REQ_USE_DMA)
c7fa9963
PO		 926 mode |= SDHCI_TRNS_DMA;
927
4e4141a5 928 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
d129bceb
PO		 929}
930
0cc563ce
AH		 931static bool sdhci_needs_reset(struct sdhci_host *host, struct mmc_request *mrq)
932{
933 return (!(host->flags & SDHCI_DEVICE_DEAD) &&
934 ((mrq->cmd && mrq->cmd->error) ||
935 (mrq->sbc && mrq->sbc->error) ||
936 (mrq->data && ((mrq->data->error && !mrq->data->stop) ||
937 (mrq->data->stop && mrq->data->stop->error))) ||
938 (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST)));
939}
940
4e9f8fe5
AH		 941static void __sdhci_finish_mrq(struct sdhci_host *host, struct mmc_request *mrq)
942{
943 int i;
944
945 for (i = 0; i < SDHCI_MAX_MRQS; i++) {
946 if (host->mrqs_done[i] == mrq) {
947 WARN_ON(1);
948 return;
949 }
950 }
951
952 for (i = 0; i < SDHCI_MAX_MRQS; i++) {
953 if (!host->mrqs_done[i]) {
954 host->mrqs_done[i] = mrq;
955 break;
956 }
957 }
958
959 WARN_ON(i >= SDHCI_MAX_MRQS);
960
961 tasklet_schedule(&host->finish_tasklet);
962}
963
a6d3bdd5
AH		 964static void sdhci_finish_mrq(struct sdhci_host *host, struct mmc_request *mrq)
965{
5a8a3fef
AH		 966 if (host->cmd && host->cmd->mrq == mrq)
967 host->cmd = NULL;
968
969 if (host->data_cmd && host->data_cmd->mrq == mrq)
970 host->data_cmd = NULL;
971
972 if (host->data && host->data->mrq == mrq)
973 host->data = NULL;
974
ed1563de
AH		 975 if (sdhci_needs_reset(host, mrq))
976 host->pending_reset = true;
977
4e9f8fe5 978 __sdhci_finish_mrq(host, mrq);
a6d3bdd5
AH		 979}
980
d129bceb
PO		 981static void sdhci_finish_data(struct sdhci_host *host)
982{
983 struct mmc_data *data;
d129bceb 984
d129bceb
PO		 985 data = host->data;
986 host->data = NULL;
7c89a3d9 987 host->data_cmd = NULL;
d129bceb 988
add8913d
RK		 989 if ((host->flags & (SDHCI_REQ_USE_DMA | SDHCI_USE_ADMA)) ==
990 (SDHCI_REQ_USE_DMA | SDHCI_USE_ADMA))
991 sdhci_adma_table_post(host, data);
d129bceb
PO		 992
993 /*
c9b74c5b
PO		 994 * The specification states that the block count register must
995 * be updated, but it does not specify at what point in the
996 * data flow. That makes the register entirely useless to read
997 * back so we have to assume that nothing made it to the card
998 * in the event of an error.
d129bceb 999 */
c9b74c5b
PO		 1000 if (data->error)
1001 data->bytes_xfered = 0;
d129bceb 1002 else
c9b74c5b 1003 data->bytes_xfered = data->blksz * data->blocks;
d129bceb 1004
e89d456f
AW		 1005 /*
1006 * Need to send CMD12 if -
1007 * a) open-ended multiblock transfer (no CMD23)
1008 * b) error in multiblock transfer
1009 */
1010 if (data->stop &&
1011 (data->error ||
a4c73aba 1012 !data->mrq->sbc)) {
e89d456f 1013
d129bceb
PO		 1014 /*
1015 * The controller needs a reset of internal state machines
1016 * upon error conditions.
1017 */
17b0429d 1018 if (data->error) {
03231f9b
RK		 1019 sdhci_do_reset(host, SDHCI_RESET_CMD);
1020 sdhci_do_reset(host, SDHCI_RESET_DATA);
d129bceb
PO		 1021 }
1022
1023 sdhci_send_command(host, data->stop);
a6d3bdd5
AH		 1024 } else {
1025 sdhci_finish_mrq(host, data->mrq);
1026 }
d129bceb
PO		 1027}
1028
d7422fb4
AH		 1029static void sdhci_mod_timer(struct sdhci_host *host, struct mmc_request *mrq,
1030 unsigned long timeout)
1031{
1032 if (sdhci_data_line_cmd(mrq->cmd))
1033 mod_timer(&host->data_timer, timeout);
1034 else
1035 mod_timer(&host->timer, timeout);
1036}
1037
1038static void sdhci_del_timer(struct sdhci_host *host, struct mmc_request *mrq)
1039{
1040 if (sdhci_data_line_cmd(mrq->cmd))
1041 del_timer(&host->data_timer);
1042 else
1043 del_timer(&host->timer);
1044}
1045
c0e55129 1046void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
d129bceb
PO		 1047{
1048 int flags;
fd2208d7 1049 u32 mask;
7cb2c76f 1050 unsigned long timeout;
d129bceb
PO		 1051
1052 WARN_ON(host->cmd);
1053
96776200
RK		 1054 /* Initially, a command has no error */
1055 cmd->error = 0;
1056
d129bceb 1057 /* Wait max 10 ms */
7cb2c76f 1058 timeout = 10;
fd2208d7
PO		 1059
1060 mask = SDHCI_CMD_INHIBIT;
56a590dc 1061 if (sdhci_data_line_cmd(cmd))
fd2208d7
PO		 1062 mask |= SDHCI_DATA_INHIBIT;
1063
1064 /* We shouldn't wait for data inihibit for stop commands, even
1065 though they might use busy signaling */
a4c73aba 1066 if (cmd->mrq->data && (cmd == cmd->mrq->data->stop))
fd2208d7
PO		 1067 mask &= ~SDHCI_DATA_INHIBIT;
1068
4e4141a5 1069 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
7cb2c76f 1070 if (timeout == 0) {
2e4456f0
MV		 1071 pr_err("%s: Controller never released inhibit bit(s).\n",
1072 mmc_hostname(host->mmc));
d129bceb 1073 sdhci_dumpregs(host);
17b0429d 1074 cmd->error = -EIO;
a6d3bdd5 1075 sdhci_finish_mrq(host, cmd->mrq);
d129bceb
PO		 1076 return;
1077 }
7cb2c76f
PO		 1078 timeout--;
1079 mdelay(1);
1080 }
d129bceb 1081
3e1a6892 1082 timeout = jiffies;
1d4d7744
UH		 1083 if (!cmd->data && cmd->busy_timeout > 9000)
1084 timeout += DIV_ROUND_UP(cmd->busy_timeout, 1000) * HZ + HZ;
3e1a6892
AH		 1085 else
1086 timeout += 10 * HZ;
d7422fb4 1087 sdhci_mod_timer(host, cmd->mrq, timeout);
d129bceb
PO		 1088
1089 host->cmd = cmd;
56a590dc 1090 if (sdhci_data_line_cmd(cmd)) {
7c89a3d9
AH		 1091 WARN_ON(host->data_cmd);
1092 host->data_cmd = cmd;
1093 }
d129bceb 1094
a3c7778f 1095 sdhci_prepare_data(host, cmd);
d129bceb 1096
4e4141a5 1097 sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT);
d129bceb 1098
e89d456f 1099 sdhci_set_transfer_mode(host, cmd);
c7fa9963 1100
d129bceb 1101 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
a3c76eb9 1102 pr_err("%s: Unsupported response type!\n",
d129bceb 1103 mmc_hostname(host->mmc));
17b0429d 1104 cmd->error = -EINVAL;
a6d3bdd5 1105 sdhci_finish_mrq(host, cmd->mrq);
d129bceb
PO		 1106 return;
1107 }
1108
1109 if (!(cmd->flags & MMC_RSP_PRESENT))
1110 flags = SDHCI_CMD_RESP_NONE;
1111 else if (cmd->flags & MMC_RSP_136)
1112 flags = SDHCI_CMD_RESP_LONG;
1113 else if (cmd->flags & MMC_RSP_BUSY)
1114 flags = SDHCI_CMD_RESP_SHORT_BUSY;
1115 else
1116 flags = SDHCI_CMD_RESP_SHORT;
1117
1118 if (cmd->flags & MMC_RSP_CRC)
1119 flags |= SDHCI_CMD_CRC;
1120 if (cmd->flags & MMC_RSP_OPCODE)
1121 flags |= SDHCI_CMD_INDEX;
b513ea25
AN		 1122
1123 /* CMD19 is special in that the Data Present Select should be set */
069c9f14
G		 1124 if (cmd->data || cmd->opcode == MMC_SEND_TUNING_BLOCK ||
1125 cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200)
d129bceb
PO		 1126 flags |= SDHCI_CMD_DATA;
1127
4e4141a5 1128 sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND);
d129bceb 1129}
c0e55129 1130EXPORT_SYMBOL_GPL(sdhci_send_command);
d129bceb
PO		 1131
1132static void sdhci_finish_command(struct sdhci_host *host)
1133{
e0a5640a 1134 struct mmc_command *cmd = host->cmd;
d129bceb
PO		 1135 int i;
1136
e0a5640a
AH		 1137 host->cmd = NULL;
1138
1139 if (cmd->flags & MMC_RSP_PRESENT) {
1140 if (cmd->flags & MMC_RSP_136) {
d129bceb
PO		 1141 /* CRC is stripped so we need to do some shifting. */
1142 for (i = 0;i < 4;i++) {
e0a5640a 1143 cmd->resp[i] = sdhci_readl(host,
d129bceb
PO		 1144 SDHCI_RESPONSE + (3-i)*4) << 8;
1145 if (i != 3)
e0a5640a 1146 cmd->resp[i] |=
4e4141a5 1147 sdhci_readb(host,
d129bceb
PO		 1148 SDHCI_RESPONSE + (3-i)*4-1);
1149 }
1150 } else {
e0a5640a 1151 cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE);
d129bceb
PO		 1152 }
1153 }
1154
6bde8681
AH		 1155 /*
1156 * The host can send and interrupt when the busy state has
1157 * ended, allowing us to wait without wasting CPU cycles.
1158 * The busy signal uses DAT0 so this is similar to waiting
1159 * for data to complete.
1160 *
1161 * Note: The 1.0 specification is a bit ambiguous about this
1162 * feature so there might be some problems with older
1163 * controllers.
1164 */
e0a5640a
AH		 1165 if (cmd->flags & MMC_RSP_BUSY) {
1166 if (cmd->data) {
6bde8681
AH		 1167 DBG("Cannot wait for busy signal when also doing a data transfer");
1168 } else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ) &&
ea968023
AH		 1169 cmd == host->data_cmd) {
1170 /* Command complete before busy is ended */
6bde8681
AH		 1171 return;
1172 }
1173 }
1174
e89d456f 1175 /* Finished CMD23, now send actual command. */
a4c73aba
AH		 1176 if (cmd == cmd->mrq->sbc) {
1177 sdhci_send_command(host, cmd->mrq->cmd);
e89d456f 1178 } else {
e538fbe8 1179
e89d456f
AW		 1180 /* Processed actual command. */
1181 if (host->data && host->data_early)
1182 sdhci_finish_data(host);
d129bceb 1183
e0a5640a 1184 if (!cmd->data)
a6d3bdd5 1185 sdhci_finish_mrq(host, cmd->mrq);
e89d456f 1186 }
d129bceb
PO		 1187}
1188
52983382
KL		 1189static u16 sdhci_get_preset_value(struct sdhci_host *host)
1190{
d975f121 1191 u16 preset = 0;
52983382 1192
d975f121
RK		 1193 switch (host->timing) {
1194 case MMC_TIMING_UHS_SDR12:
52983382
KL		 1195 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1196 break;
d975f121 1197 case MMC_TIMING_UHS_SDR25:
52983382
KL		 1198 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR25);
1199 break;
d975f121 1200 case MMC_TIMING_UHS_SDR50:
52983382
KL		 1201 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR50);
1202 break;
d975f121
RK		 1203 case MMC_TIMING_UHS_SDR104:
1204 case MMC_TIMING_MMC_HS200:
52983382
KL		 1205 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR104);
1206 break;
d975f121 1207 case MMC_TIMING_UHS_DDR50:
0dafa60e 1208 case MMC_TIMING_MMC_DDR52:
52983382
KL		 1209 preset = sdhci_readw(host, SDHCI_PRESET_FOR_DDR50);
1210 break;
e9fb05d5
AH		 1211 case MMC_TIMING_MMC_HS400:
1212 preset = sdhci_readw(host, SDHCI_PRESET_FOR_HS400);
1213 break;
52983382
KL		 1214 default:
1215 pr_warn("%s: Invalid UHS-I mode selected\n",
1216 mmc_hostname(host->mmc));
1217 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1218 break;
1219 }
1220 return preset;
1221}
1222
fb9ee047
LD		 1223u16 sdhci_calc_clk(struct sdhci_host *host, unsigned int clock,
1224 unsigned int *actual_clock)
d129bceb 1225{
c3ed3877 1226 int div = 0; /* Initialized for compiler warning */
df16219f 1227 int real_div = div, clk_mul = 1;
c3ed3877 1228 u16 clk = 0;
5497159c 1229 bool switch_base_clk = false;
d129bceb 1230
85105c53 1231 if (host->version >= SDHCI_SPEC_300) {
da91a8f9 1232 if (host->preset_enabled) {
52983382
KL		 1233 u16 pre_val;
1234
1235 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1236 pre_val = sdhci_get_preset_value(host);
1237 div = (pre_val & SDHCI_PRESET_SDCLK_FREQ_MASK)
1238 >> SDHCI_PRESET_SDCLK_FREQ_SHIFT;
1239 if (host->clk_mul &&
1240 (pre_val & SDHCI_PRESET_CLKGEN_SEL_MASK)) {
1241 clk = SDHCI_PROG_CLOCK_MODE;
1242 real_div = div + 1;
1243 clk_mul = host->clk_mul;
1244 } else {
1245 real_div = max_t(int, 1, div << 1);
1246 }
1247 goto clock_set;
1248 }
1249
c3ed3877
AN		 1250 /*
1251 * Check if the Host Controller supports Programmable Clock
1252 * Mode.
1253 */
1254 if (host->clk_mul) {
52983382
KL		 1255 for (div = 1; div <= 1024; div++) {
1256 if ((host->max_clk * host->clk_mul / div)
1257 <= clock)
1258 break;
1259 }
5497159c 1260 if ((host->max_clk * host->clk_mul / div) <= clock) {
1261 /*
1262 * Set Programmable Clock Mode in the Clock
1263 * Control register.
1264 */
1265 clk = SDHCI_PROG_CLOCK_MODE;
1266 real_div = div;
1267 clk_mul = host->clk_mul;
1268 div--;
1269 } else {
1270 /*
1271 * Divisor can be too small to reach clock
1272 * speed requirement. Then use the base clock.
1273 */
1274 switch_base_clk = true;
1275 }
1276 }
1277
1278 if (!host->clk_mul || switch_base_clk) {
c3ed3877
AN		 1279 /* Version 3.00 divisors must be a multiple of 2. */
1280 if (host->max_clk <= clock)
1281 div = 1;
1282 else {
1283 for (div = 2; div < SDHCI_MAX_DIV_SPEC_300;
1284 div += 2) {
1285 if ((host->max_clk / div) <= clock)
1286 break;
1287 }
85105c53 1288 }
df16219f 1289 real_div = div;
c3ed3877 1290 div >>= 1;
d1955c3a
SG		 1291 if ((host->quirks2 & SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN)
1292 && !div && host->max_clk <= 25000000)
1293 div = 1;
85105c53
ZG		 1294 }
1295 } else {
1296 /* Version 2.00 divisors must be a power of 2. */
0397526d 1297 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
85105c53
ZG		 1298 if ((host->max_clk / div) <= clock)
1299 break;
1300 }
df16219f 1301 real_div = div;
c3ed3877 1302 div >>= 1;
d129bceb 1303 }
d129bceb 1304
52983382 1305clock_set:
03d6f5ff 1306 if (real_div)
fb9ee047 1307 *actual_clock = (host->max_clk * clk_mul) / real_div;
c3ed3877 1308 clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
85105c53
ZG		 1309 clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
1310 << SDHCI_DIVIDER_HI_SHIFT;
fb9ee047
LD		 1311
1312 return clk;
1313}
1314EXPORT_SYMBOL_GPL(sdhci_calc_clk);
1315
1316void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
1317{
1318 u16 clk;
1319 unsigned long timeout;
1320
1321 host->mmc->actual_clock = 0;
1322
1323 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
fb9ee047
LD		 1324
1325 if (clock == 0)
1326 return;
1327
1328 clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock);
1329
d129bceb 1330 clk |= SDHCI_CLOCK_INT_EN;
4e4141a5 1331 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
d129bceb 1332
27f6cb16
CB		 1333 /* Wait max 20 ms */
1334 timeout = 20;
4e4141a5 1335 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
7cb2c76f
PO		 1336 & SDHCI_CLOCK_INT_STABLE)) {
1337 if (timeout == 0) {
2e4456f0
MV		 1338 pr_err("%s: Internal clock never stabilised.\n",
1339 mmc_hostname(host->mmc));
d129bceb
PO		 1340 sdhci_dumpregs(host);
1341 return;
1342 }
7cb2c76f
PO		 1343 timeout--;
1344 mdelay(1);
1345 }
d129bceb
PO		 1346
1347 clk |= SDHCI_CLOCK_CARD_EN;
4e4141a5 1348 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
d129bceb 1349}
1771059c 1350EXPORT_SYMBOL_GPL(sdhci_set_clock);
d129bceb 1351
1dceb041
AH		 1352static void sdhci_set_power_reg(struct sdhci_host *host, unsigned char mode,
1353 unsigned short vdd)
146ad66e 1354{
3a48edc4 1355 struct mmc_host *mmc = host->mmc;
1dceb041
AH		 1356
1357 spin_unlock_irq(&host->lock);
1358 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd);
1359 spin_lock_irq(&host->lock);
1360
1361 if (mode != MMC_POWER_OFF)
1362 sdhci_writeb(host, SDHCI_POWER_ON, SDHCI_POWER_CONTROL);
1363 else
1364 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1365}
1366
1367void sdhci_set_power(struct sdhci_host *host, unsigned char mode,
1368 unsigned short vdd)
1369{
8364248a 1370 u8 pwr = 0;
146ad66e 1371
24fbb3ca
RK		 1372 if (mode != MMC_POWER_OFF) {
1373 switch (1 << vdd) {
ae628903
PO		 1374 case MMC_VDD_165_195:
1375 pwr = SDHCI_POWER_180;
1376 break;
1377 case MMC_VDD_29_30:
1378 case MMC_VDD_30_31:
1379 pwr = SDHCI_POWER_300;
1380 break;
1381 case MMC_VDD_32_33:
1382 case MMC_VDD_33_34:
1383 pwr = SDHCI_POWER_330;
1384 break;
1385 default:
9d5de93f
AH		 1386 WARN(1, "%s: Invalid vdd %#x\n",
1387 mmc_hostname(host->mmc), vdd);
1388 break;
ae628903
PO		 1389 }
1390 }
1391
1392 if (host->pwr == pwr)
e921a8b6 1393 return;
146ad66e 1394
ae628903
PO		 1395 host->pwr = pwr;
1396
1397 if (pwr == 0) {
4e4141a5 1398 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
f0710a55
AH		 1399 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
1400 sdhci_runtime_pm_bus_off(host);
e921a8b6
RK		 1401 } else {
1402 /*
1403 * Spec says that we should clear the power reg before setting
1404 * a new value. Some controllers don't seem to like this though.
1405 */
1406 if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
1407 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
146ad66e 1408
e921a8b6
RK		 1409 /*
1410 * At least the Marvell CaFe chip gets confused if we set the
1411 * voltage and set turn on power at the same time, so set the
1412 * voltage first.
1413 */
1414 if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
1415 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
e08c1694 1416
e921a8b6 1417 pwr |= SDHCI_POWER_ON;
146ad66e 1418
e921a8b6 1419 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
557b0697 1420
e921a8b6
RK		 1421 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
1422 sdhci_runtime_pm_bus_on(host);
f0710a55 1423
e921a8b6
RK		 1424 /*
1425 * Some controllers need an extra 10ms delay of 10ms before
1426 * they can apply clock after applying power
1427 */
1428 if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER)
1429 mdelay(10);
1430 }
1dceb041
AH		 1431}
1432EXPORT_SYMBOL_GPL(sdhci_set_power);
918f4cbd 1433
1dceb041
AH		 1434static void __sdhci_set_power(struct sdhci_host *host, unsigned char mode,
1435 unsigned short vdd)
1436{
1437 struct mmc_host *mmc = host->mmc;
1438
1439 if (host->ops->set_power)
1440 host->ops->set_power(host, mode, vdd);
1441 else if (!IS_ERR(mmc->supply.vmmc))
1442 sdhci_set_power_reg(host, mode, vdd);
1443 else
1444 sdhci_set_power(host, mode, vdd);
146ad66e
PO		 1445}
1446
d129bceb
PO		 1447/*****************************************************************************\
1448 * *
1449 * MMC callbacks *
1450 * *
1451\*****************************************************************************/
1452
1453static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1454{
1455 struct sdhci_host *host;
505a8680 1456 int present;
d129bceb
PO		 1457 unsigned long flags;
1458
1459 host = mmc_priv(mmc);
1460
04e079cf 1461 /* Firstly check card presence */
8d28b7a7 1462 present = mmc->ops->get_cd(mmc);
2836766a 1463
d129bceb
PO		 1464 spin_lock_irqsave(&host->lock, flags);
1465
061d17a6 1466 sdhci_led_activate(host);
e89d456f
AW		 1467
1468 /*
1469 * Ensure we don't send the STOP for non-SET_BLOCK_COUNTED
1470 * requests if Auto-CMD12 is enabled.
1471 */
1472 if (!mrq->sbc && (host->flags & SDHCI_AUTO_CMD12)) {
c4512f79
JH		 1473 if (mrq->stop) {
1474 mrq->data->stop = NULL;
1475 mrq->stop = NULL;
1476 }
1477 }
d129bceb 1478
68d1fb7e 1479 if (!present || host->flags & SDHCI_DEVICE_DEAD) {
a4c73aba 1480 mrq->cmd->error = -ENOMEDIUM;
a6d3bdd5 1481 sdhci_finish_mrq(host, mrq);
cf2b5eea 1482 } else {
8edf6371 1483 if (mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23))
e89d456f
AW		 1484 sdhci_send_command(host, mrq->sbc);
1485 else
1486 sdhci_send_command(host, mrq->cmd);
cf2b5eea 1487 }
d129bceb 1488
5f25a66f 1489 mmiowb();
d129bceb
PO		 1490 spin_unlock_irqrestore(&host->lock, flags);
1491}
1492
2317f56c
RK		 1493void sdhci_set_bus_width(struct sdhci_host *host, int width)
1494{
1495 u8 ctrl;
1496
1497 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1498 if (width == MMC_BUS_WIDTH_8) {
1499 ctrl &= ~SDHCI_CTRL_4BITBUS;
1500 if (host->version >= SDHCI_SPEC_300)
1501 ctrl |= SDHCI_CTRL_8BITBUS;
1502 } else {
1503 if (host->version >= SDHCI_SPEC_300)
1504 ctrl &= ~SDHCI_CTRL_8BITBUS;
1505 if (width == MMC_BUS_WIDTH_4)
1506 ctrl |= SDHCI_CTRL_4BITBUS;
1507 else
1508 ctrl &= ~SDHCI_CTRL_4BITBUS;
1509 }
1510 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1511}
1512EXPORT_SYMBOL_GPL(sdhci_set_bus_width);
1513
96d7b78c
RK		 1514void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing)
1515{
1516 u16 ctrl_2;
1517
1518 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1519 /* Select Bus Speed Mode for host */
1520 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
1521 if ((timing == MMC_TIMING_MMC_HS200) ||
1522 (timing == MMC_TIMING_UHS_SDR104))
1523 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
1524 else if (timing == MMC_TIMING_UHS_SDR12)
1525 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
1526 else if (timing == MMC_TIMING_UHS_SDR25)
1527 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
1528 else if (timing == MMC_TIMING_UHS_SDR50)
1529 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
1530 else if ((timing == MMC_TIMING_UHS_DDR50) ||
1531 (timing == MMC_TIMING_MMC_DDR52))
1532 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
e9fb05d5
AH		 1533 else if (timing == MMC_TIMING_MMC_HS400)
1534 ctrl_2 |= SDHCI_CTRL_HS400; /* Non-standard */
96d7b78c
RK		 1535 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1536}
1537EXPORT_SYMBOL_GPL(sdhci_set_uhs_signaling);
1538
ded97e0b 1539static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
d129bceb 1540{
ded97e0b 1541 struct sdhci_host *host = mmc_priv(mmc);
d129bceb
PO		 1542 unsigned long flags;
1543 u8 ctrl;
1544
d129bceb
PO		 1545 spin_lock_irqsave(&host->lock, flags);
1546
ceb6143b
AH		 1547 if (host->flags & SDHCI_DEVICE_DEAD) {
1548 spin_unlock_irqrestore(&host->lock, flags);
3a48edc4
TK		 1549 if (!IS_ERR(mmc->supply.vmmc) &&
1550 ios->power_mode == MMC_POWER_OFF)
4e743f1f 1551 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
ceb6143b
AH		 1552 return;
1553 }
1e72859e 1554
d129bceb
PO		 1555 /*
1556 * Reset the chip on each power off.
1557 * Should clear out any weird states.
1558 */
1559 if (ios->power_mode == MMC_POWER_OFF) {
4e4141a5 1560 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
7260cf5e 1561 sdhci_reinit(host);
d129bceb
PO		 1562 }
1563
52983382 1564 if (host->version >= SDHCI_SPEC_300 &&
372c4634
DA		 1565 (ios->power_mode == MMC_POWER_UP) &&
1566 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN))
52983382
KL		 1567 sdhci_enable_preset_value(host, false);
1568
373073ef 1569 if (!ios->clock || ios->clock != host->clock) {
1771059c 1570 host->ops->set_clock(host, ios->clock);
373073ef 1571 host->clock = ios->clock;
03d6f5ff
AD		 1572
1573 if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK &&
1574 host->clock) {
1575 host->timeout_clk = host->mmc->actual_clock ?
1576 host->mmc->actual_clock / 1000 :
1577 host->clock / 1000;
1578 host->mmc->max_busy_timeout =
1579 host->ops->get_max_timeout_count ?
1580 host->ops->get_max_timeout_count(host) :
1581 1 << 27;
1582 host->mmc->max_busy_timeout /= host->timeout_clk;
1583 }
373073ef 1584 }
d129bceb 1585
1dceb041 1586 __sdhci_set_power(host, ios->power_mode, ios->vdd);
d129bceb 1587
643a81ff
PR		 1588 if (host->ops->platform_send_init_74_clocks)
1589 host->ops->platform_send_init_74_clocks(host, ios->power_mode);
1590
2317f56c 1591 host->ops->set_bus_width(host, ios->bus_width);
ae6d6c92 1592
15ec4461 1593 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
cd9277c0 1594
3ab9c8da
PR		 1595 if ((ios->timing == MMC_TIMING_SD_HS ||
1596 ios->timing == MMC_TIMING_MMC_HS)
1597 && !(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT))
cd9277c0
PO		 1598 ctrl |= SDHCI_CTRL_HISPD;
1599 else
1600 ctrl &= ~SDHCI_CTRL_HISPD;
1601
d6d50a15 1602 if (host->version >= SDHCI_SPEC_300) {
49c468fc 1603 u16 clk, ctrl_2;
49c468fc
AN		 1604
1605 /* In case of UHS-I modes, set High Speed Enable */
e9fb05d5
AH		 1606 if ((ios->timing == MMC_TIMING_MMC_HS400) ||
1607 (ios->timing == MMC_TIMING_MMC_HS200) ||
bb8175a8 1608 (ios->timing == MMC_TIMING_MMC_DDR52) ||
069c9f14 1609 (ios->timing == MMC_TIMING_UHS_SDR50) ||
49c468fc
AN		 1610 (ios->timing == MMC_TIMING_UHS_SDR104) ||
1611 (ios->timing == MMC_TIMING_UHS_DDR50) ||
dd8df17f 1612 (ios->timing == MMC_TIMING_UHS_SDR25))
49c468fc 1613 ctrl |= SDHCI_CTRL_HISPD;
d6d50a15 1614
da91a8f9 1615 if (!host->preset_enabled) {
758535c4 1616 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d6d50a15
AN		 1617 /*
1618 * We only need to set Driver Strength if the
1619 * preset value enable is not set.
1620 */
da91a8f9 1621 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
d6d50a15
AN		 1622 ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK;
1623 if (ios->drv_type == MMC_SET_DRIVER_TYPE_A)
1624 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A;
43e943a0
PG		 1625 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_B)
1626 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_B;
d6d50a15
AN		 1627 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C)
1628 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C;
43e943a0
PG		 1629 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_D)
1630 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_D;
1631 else {
2e4456f0
MV		 1632 pr_warn("%s: invalid driver type, default to driver type B\n",
1633 mmc_hostname(mmc));
43e943a0
PG		 1634 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_B;
1635 }
d6d50a15
AN		 1636
1637 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
758535c4
AN		 1638 } else {
1639 /*
1640 * According to SDHC Spec v3.00, if the Preset Value
1641 * Enable in the Host Control 2 register is set, we
1642 * need to reset SD Clock Enable before changing High
1643 * Speed Enable to avoid generating clock gliches.
1644 */
758535c4
AN		 1645
1646 /* Reset SD Clock Enable */
1647 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1648 clk &= ~SDHCI_CLOCK_CARD_EN;
1649 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1650
1651 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1652
1653 /* Re-enable SD Clock */
1771059c 1654 host->ops->set_clock(host, host->clock);
d6d50a15 1655 }
49c468fc 1656
49c468fc
AN		 1657 /* Reset SD Clock Enable */
1658 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1659 clk &= ~SDHCI_CLOCK_CARD_EN;
1660 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1661
96d7b78c 1662 host->ops->set_uhs_signaling(host, ios->timing);
d975f121 1663 host->timing = ios->timing;
49c468fc 1664
52983382
KL		 1665 if (!(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN) &&
1666 ((ios->timing == MMC_TIMING_UHS_SDR12) ||
1667 (ios->timing == MMC_TIMING_UHS_SDR25) ||
1668 (ios->timing == MMC_TIMING_UHS_SDR50) ||
1669 (ios->timing == MMC_TIMING_UHS_SDR104) ||
0dafa60e
JZ		 1670 (ios->timing == MMC_TIMING_UHS_DDR50) ||
1671 (ios->timing == MMC_TIMING_MMC_DDR52))) {
52983382
KL		 1672 u16 preset;
1673
1674 sdhci_enable_preset_value(host, true);
1675 preset = sdhci_get_preset_value(host);
1676 ios->drv_type = (preset & SDHCI_PRESET_DRV_MASK)
1677 >> SDHCI_PRESET_DRV_SHIFT;
1678 }
1679
49c468fc 1680 /* Re-enable SD Clock */
1771059c 1681 host->ops->set_clock(host, host->clock);
758535c4
AN		 1682 } else
1683 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d6d50a15 1684
b8352260
LD		 1685 /*
1686 * Some (ENE) controllers go apeshit on some ios operation,
1687 * signalling timeout and CRC errors even on CMD0. Resetting
1688 * it on each ios seems to solve the problem.
1689 */
c63705e1 1690 if (host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
03231f9b 1691 sdhci_do_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
b8352260 1692
5f25a66f 1693 mmiowb();
d129bceb
PO		 1694 spin_unlock_irqrestore(&host->lock, flags);
1695}
1696
ded97e0b 1697static int sdhci_get_cd(struct mmc_host *mmc)
66fd8ad5
AH		 1698{
1699 struct sdhci_host *host = mmc_priv(mmc);
ded97e0b 1700 int gpio_cd = mmc_gpio_get_cd(mmc);
94144a46
KL		 1701
1702 if (host->flags & SDHCI_DEVICE_DEAD)
1703 return 0;
1704
88af5655 1705 /* If nonremovable, assume that the card is always present. */
860951c5 1706 if (!mmc_card_is_removable(host->mmc))
94144a46
KL		 1707 return 1;
1708
88af5655
II		 1709 /*
1710 * Try slot gpio detect, if defined it take precedence
1711 * over build in controller functionality
1712 */
287980e4 1713 if (gpio_cd >= 0)
94144a46
KL		 1714 return !!gpio_cd;
1715
88af5655
II		 1716 /* If polling, assume that the card is always present. */
1717 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
1718 return 1;
1719
94144a46
KL		 1720 /* Host native card detect */
1721 return !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
1722}
1723
66fd8ad5 1724static int sdhci_check_ro(struct sdhci_host *host)
d129bceb 1725{
d129bceb 1726 unsigned long flags;
2dfb579c 1727 int is_readonly;
d129bceb 1728
d129bceb
PO		 1729 spin_lock_irqsave(&host->lock, flags);
1730
1e72859e 1731 if (host->flags & SDHCI_DEVICE_DEAD)
2dfb579c
WS		 1732 is_readonly = 0;
1733 else if (host->ops->get_ro)
1734 is_readonly = host->ops->get_ro(host);
1e72859e 1735 else
2dfb579c
WS		 1736 is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE)
1737 & SDHCI_WRITE_PROTECT);
d129bceb
PO		 1738
1739 spin_unlock_irqrestore(&host->lock, flags);
1740
2dfb579c
WS		 1741 /* This quirk needs to be replaced by a callback-function later */
1742 return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ?
1743 !is_readonly : is_readonly;
d129bceb
PO		 1744}
1745
82b0e23a
TI		 1746#define SAMPLE_COUNT 5
1747
ded97e0b 1748static int sdhci_get_ro(struct mmc_host *mmc)
82b0e23a 1749{
ded97e0b 1750 struct sdhci_host *host = mmc_priv(mmc);
82b0e23a
TI		 1751 int i, ro_count;
1752
82b0e23a 1753 if (!(host->quirks & SDHCI_QUIRK_UNSTABLE_RO_DETECT))
66fd8ad5 1754 return sdhci_check_ro(host);
82b0e23a
TI		 1755
1756 ro_count = 0;
1757 for (i = 0; i < SAMPLE_COUNT; i++) {
66fd8ad5 1758 if (sdhci_check_ro(host)) {
82b0e23a
TI		 1759 if (++ro_count > SAMPLE_COUNT / 2)
1760 return 1;
1761 }
1762 msleep(30);
1763 }
1764 return 0;
1765}
1766
20758b66
AH		 1767static void sdhci_hw_reset(struct mmc_host *mmc)
1768{
1769 struct sdhci_host *host = mmc_priv(mmc);
1770
1771 if (host->ops && host->ops->hw_reset)
1772 host->ops->hw_reset(host);
1773}
1774
66fd8ad5
AH		 1775static void sdhci_enable_sdio_irq_nolock(struct sdhci_host *host, int enable)
1776{
be138554 1777 if (!(host->flags & SDHCI_DEVICE_DEAD)) {
ef104333 1778 if (enable)
b537f94c 1779 host->ier |= SDHCI_INT_CARD_INT;
ef104333 1780 else
b537f94c
RK		 1781 host->ier &= ~SDHCI_INT_CARD_INT;
1782
1783 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
1784 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
ef104333
RK		 1785 mmiowb();
1786 }
66fd8ad5
AH		 1787}
1788
1789static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1790{
1791 struct sdhci_host *host = mmc_priv(mmc);
1792 unsigned long flags;
f75979b7 1793
66fd8ad5 1794 spin_lock_irqsave(&host->lock, flags);
ef104333
RK		 1795 if (enable)
1796 host->flags |= SDHCI_SDIO_IRQ_ENABLED;
1797 else
1798 host->flags &= ~SDHCI_SDIO_IRQ_ENABLED;
1799
66fd8ad5 1800 sdhci_enable_sdio_irq_nolock(host, enable);
f75979b7
PO		 1801 spin_unlock_irqrestore(&host->lock, flags);
1802}
1803
ded97e0b
DA		 1804static int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
1805 struct mmc_ios *ios)
f2119df6 1806{
ded97e0b 1807 struct sdhci_host *host = mmc_priv(mmc);
20b92a30 1808 u16 ctrl;
6231f3de 1809 int ret;
f2119df6 1810
20b92a30
KL		 1811 /*
1812 * Signal Voltage Switching is only applicable for Host Controllers
1813 * v3.00 and above.
1814 */
1815 if (host->version < SDHCI_SPEC_300)
1816 return 0;
6231f3de 1817
f2119df6 1818 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
f2119df6 1819
21f5998f 1820 switch (ios->signal_voltage) {
20b92a30 1821 case MMC_SIGNAL_VOLTAGE_330:
8cb851a4
AH		 1822 if (!(host->flags & SDHCI_SIGNALING_330))
1823 return -EINVAL;
20b92a30
KL		 1824 /* Set 1.8V Signal Enable in the Host Control2 register to 0 */
1825 ctrl &= ~SDHCI_CTRL_VDD_180;
1826 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
f2119df6 1827
3a48edc4
TK		 1828 if (!IS_ERR(mmc->supply.vqmmc)) {
1829 ret = regulator_set_voltage(mmc->supply.vqmmc, 2700000,
1830 3600000);
20b92a30 1831 if (ret) {
6606110d
JP		 1832 pr_warn("%s: Switching to 3.3V signalling voltage failed\n",
1833 mmc_hostname(mmc));
20b92a30
KL		 1834 return -EIO;
1835 }
1836 }
1837 /* Wait for 5ms */
1838 usleep_range(5000, 5500);
f2119df6 1839
20b92a30
KL		 1840 /* 3.3V regulator output should be stable within 5 ms */
1841 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1842 if (!(ctrl & SDHCI_CTRL_VDD_180))
1843 return 0;
6231f3de 1844
6606110d
JP		 1845 pr_warn("%s: 3.3V regulator output did not became stable\n",
1846 mmc_hostname(mmc));
20b92a30
KL		 1847
1848 return -EAGAIN;
1849 case MMC_SIGNAL_VOLTAGE_180:
8cb851a4
AH		 1850 if (!(host->flags & SDHCI_SIGNALING_180))
1851 return -EINVAL;
3a48edc4
TK		 1852 if (!IS_ERR(mmc->supply.vqmmc)) {
1853 ret = regulator_set_voltage(mmc->supply.vqmmc,
20b92a30
KL		 1854 1700000, 1950000);
1855 if (ret) {
6606110d
JP		 1856 pr_warn("%s: Switching to 1.8V signalling voltage failed\n",
1857 mmc_hostname(mmc));
20b92a30
KL		 1858 return -EIO;
1859 }
1860 }
6231f3de 1861
6231f3de
PR		 1862 /*
1863 * Enable 1.8V Signal Enable in the Host Control2
1864 * register
1865 */
20b92a30
KL		 1866 ctrl |= SDHCI_CTRL_VDD_180;
1867 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
6231f3de 1868
9d967a61
VY		 1869 /* Some controller need to do more when switching */
1870 if (host->ops->voltage_switch)
1871 host->ops->voltage_switch(host);
1872
20b92a30
KL		 1873 /* 1.8V regulator output should be stable within 5 ms */
1874 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1875 if (ctrl & SDHCI_CTRL_VDD_180)
1876 return 0;
f2119df6 1877
6606110d
JP		 1878 pr_warn("%s: 1.8V regulator output did not became stable\n",
1879 mmc_hostname(mmc));
f2119df6 1880
20b92a30
KL		 1881 return -EAGAIN;
1882 case MMC_SIGNAL_VOLTAGE_120:
8cb851a4
AH		 1883 if (!(host->flags & SDHCI_SIGNALING_120))
1884 return -EINVAL;
3a48edc4
TK		 1885 if (!IS_ERR(mmc->supply.vqmmc)) {
1886 ret = regulator_set_voltage(mmc->supply.vqmmc, 1100000,
1887 1300000);
20b92a30 1888 if (ret) {
6606110d
JP		 1889 pr_warn("%s: Switching to 1.2V signalling voltage failed\n",
1890 mmc_hostname(mmc));
20b92a30 1891 return -EIO;
f2119df6
AN		 1892 }
1893 }
6231f3de 1894 return 0;
20b92a30 1895 default:
f2119df6
AN		 1896 /* No signal voltage switch required */
1897 return 0;
20b92a30 1898 }
f2119df6
AN		 1899}
1900
20b92a30
KL		 1901static int sdhci_card_busy(struct mmc_host *mmc)
1902{
1903 struct sdhci_host *host = mmc_priv(mmc);
1904 u32 present_state;
1905
e613cc47 1906 /* Check whether DAT[0] is 0 */
20b92a30 1907 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
20b92a30 1908
e613cc47 1909 return !(present_state & SDHCI_DATA_0_LVL_MASK);
20b92a30
KL		 1910}
1911
b5540ce1
AH		 1912static int sdhci_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios)
1913{
1914 struct sdhci_host *host = mmc_priv(mmc);
1915 unsigned long flags;
1916
1917 spin_lock_irqsave(&host->lock, flags);
1918 host->flags |= SDHCI_HS400_TUNING;
1919 spin_unlock_irqrestore(&host->lock, flags);
1920
1921 return 0;
1922}
1923
069c9f14 1924static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode)
b513ea25 1925{
4b6f37d3 1926 struct sdhci_host *host = mmc_priv(mmc);
b513ea25 1927 u16 ctrl;
b513ea25 1928 int tuning_loop_counter = MAX_TUNING_LOOP;
b513ea25 1929 int err = 0;
2b35bd83 1930 unsigned long flags;
38e40bf5 1931 unsigned int tuning_count = 0;
b5540ce1 1932 bool hs400_tuning;
b513ea25 1933
2b35bd83 1934 spin_lock_irqsave(&host->lock, flags);
b513ea25 1935
b5540ce1
AH		 1936 hs400_tuning = host->flags & SDHCI_HS400_TUNING;
1937 host->flags &= ~SDHCI_HS400_TUNING;
1938
38e40bf5
AH		 1939 if (host->tuning_mode == SDHCI_TUNING_MODE_1)
1940 tuning_count = host->tuning_count;
1941
b513ea25 1942 /*
9faac7b9
WY		 1943 * The Host Controller needs tuning in case of SDR104 and DDR50
1944 * mode, and for SDR50 mode when Use Tuning for SDR50 is set in
1945 * the Capabilities register.
069c9f14
G		 1946 * If the Host Controller supports the HS200 mode then the
1947 * tuning function has to be executed.
b513ea25 1948 */
4b6f37d3 1949 switch (host->timing) {
b5540ce1 1950 /* HS400 tuning is done in HS200 mode */
e9fb05d5 1951 case MMC_TIMING_MMC_HS400:
b5540ce1
AH		 1952 err = -EINVAL;
1953 goto out_unlock;
1954
4b6f37d3 1955 case MMC_TIMING_MMC_HS200:
b5540ce1
AH		 1956 /*
1957 * Periodic re-tuning for HS400 is not expected to be needed, so
1958 * disable it here.
1959 */
1960 if (hs400_tuning)
1961 tuning_count = 0;
1962 break;
1963
4b6f37d3 1964 case MMC_TIMING_UHS_SDR104:
9faac7b9 1965 case MMC_TIMING_UHS_DDR50:
4b6f37d3
RK		 1966 break;
1967
1968 case MMC_TIMING_UHS_SDR50:
4228b213 1969 if (host->flags & SDHCI_SDR50_NEEDS_TUNING)
4b6f37d3
RK		 1970 break;
1971 /* FALLTHROUGH */
1972
1973 default:
d519c863 1974 goto out_unlock;
b513ea25
AN		 1975 }
1976
45251812 1977 if (host->ops->platform_execute_tuning) {
2b35bd83 1978 spin_unlock_irqrestore(&host->lock, flags);
45251812 1979 err = host->ops->platform_execute_tuning(host, opcode);
45251812
DA		 1980 return err;
1981 }
1982
4b6f37d3
RK		 1983 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1984 ctrl |= SDHCI_CTRL_EXEC_TUNING;
67d0d04a
VY		 1985 if (host->quirks2 & SDHCI_QUIRK2_TUNING_WORK_AROUND)
1986 ctrl |= SDHCI_CTRL_TUNED_CLK;
b513ea25
AN		 1987 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1988
1989 /*
1990 * As per the Host Controller spec v3.00, tuning command
1991 * generates Buffer Read Ready interrupt, so enable that.
1992 *
1993 * Note: The spec clearly says that when tuning sequence
1994 * is being performed, the controller does not generate
1995 * interrupts other than Buffer Read Ready interrupt. But
1996 * to make sure we don't hit a controller bug, we _only_
1997 * enable Buffer Read Ready interrupt here.
1998 */
b537f94c
RK		 1999 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE);
2000 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE);
b513ea25
AN		 2001
2002 /*
2003 * Issue CMD19 repeatedly till Execute Tuning is set to 0 or the number
1473bdd5 2004 * of loops reaches 40 times.
b513ea25 2005 */
b513ea25
AN		 2006 do {
2007 struct mmc_command cmd = {0};
66fd8ad5 2008 struct mmc_request mrq = {NULL};
b513ea25 2009
069c9f14 2010 cmd.opcode = opcode;
b513ea25
AN		 2011 cmd.arg = 0;
2012 cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
2013 cmd.retries = 0;
2014 cmd.data = NULL;
4e9f8fe5 2015 cmd.mrq = &mrq;
b513ea25
AN		 2016 cmd.error = 0;
2017
7ce45e95
AC		 2018 if (tuning_loop_counter-- == 0)
2019 break;
2020
b513ea25 2021 mrq.cmd = &cmd;
b513ea25
AN		 2022
2023 /*
2024 * In response to CMD19, the card sends 64 bytes of tuning
2025 * block to the Host Controller. So we set the block size
2026 * to 64 here.
2027 */
069c9f14
G		 2028 if (cmd.opcode == MMC_SEND_TUNING_BLOCK_HS200) {
2029 if (mmc->ios.bus_width == MMC_BUS_WIDTH_8)
2030 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 128),
2031 SDHCI_BLOCK_SIZE);
2032 else if (mmc->ios.bus_width == MMC_BUS_WIDTH_4)
2033 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
2034 SDHCI_BLOCK_SIZE);
2035 } else {
2036 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
2037 SDHCI_BLOCK_SIZE);
2038 }
b513ea25
AN		 2039
2040 /*
2041 * The tuning block is sent by the card to the host controller.
2042 * So we set the TRNS_READ bit in the Transfer Mode register.
2043 * This also takes care of setting DMA Enable and Multi Block
2044 * Select in the same register to 0.
2045 */
2046 sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
2047
2048 sdhci_send_command(host, &cmd);
2049
2050 host->cmd = NULL;
b513ea25 2051
2b35bd83 2052 spin_unlock_irqrestore(&host->lock, flags);
b513ea25
AN		 2053 /* Wait for Buffer Read Ready interrupt */
2054 wait_event_interruptible_timeout(host->buf_ready_int,
2055 (host->tuning_done == 1),
2056 msecs_to_jiffies(50));
2b35bd83 2057 spin_lock_irqsave(&host->lock, flags);
b513ea25
AN		 2058
2059 if (!host->tuning_done) {
2e4456f0 2060 pr_info(DRIVER_NAME ": Timeout waiting for Buffer Read Ready interrupt during tuning procedure, falling back to fixed sampling clock\n");
b513ea25
AN		 2061 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2062 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
2063 ctrl &= ~SDHCI_CTRL_EXEC_TUNING;
2064 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2065
2066 err = -EIO;
2067 goto out;
2068 }
2069
2070 host->tuning_done = 0;
2071
2072 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
197160d5
NS		 2073
2074 /* eMMC spec does not require a delay between tuning cycles */
2075 if (opcode == MMC_SEND_TUNING_BLOCK)
2076 mdelay(1);
b513ea25
AN		 2077 } while (ctrl & SDHCI_CTRL_EXEC_TUNING);
2078
2079 /*
2080 * The Host Driver has exhausted the maximum number of loops allowed,
2081 * so use fixed sampling frequency.
2082 */
7ce45e95 2083 if (tuning_loop_counter < 0) {
b513ea25
AN		 2084 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
2085 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
7ce45e95
AC		 2086 }
2087 if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) {
2e4456f0 2088 pr_info(DRIVER_NAME ": Tuning procedure failed, falling back to fixed sampling clock\n");
114f2bf6 2089 err = -EIO;
b513ea25
AN		 2090 }
2091
2092out:
38e40bf5 2093 if (tuning_count) {
66c39dfc
AH		 2094 /*
2095 * In case tuning fails, host controllers which support
2096 * re-tuning can try tuning again at a later time, when the
2097 * re-tuning timer expires. So for these controllers, we
2098 * return 0. Since there might be other controllers who do not
2099 * have this capability, we return error for them.
2100 */
2101 err = 0;
cf2b5eea
AN		 2102 }
2103
66c39dfc 2104 host->mmc->retune_period = err ? 0 : tuning_count;
cf2b5eea 2105
b537f94c
RK		 2106 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2107 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
d519c863 2108out_unlock:
2b35bd83 2109 spin_unlock_irqrestore(&host->lock, flags);
b513ea25
AN		 2110 return err;
2111}
2112
cb849648
AH		 2113static int sdhci_select_drive_strength(struct mmc_card *card,
2114 unsigned int max_dtr, int host_drv,
2115 int card_drv, int *drv_type)
2116{
2117 struct sdhci_host *host = mmc_priv(card->host);
2118
2119 if (!host->ops->select_drive_strength)
2120 return 0;
2121
2122 return host->ops->select_drive_strength(host, card, max_dtr, host_drv,
2123 card_drv, drv_type);
2124}
52983382
KL		 2125
2126static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable)
4d55c5a1 2127{
4d55c5a1
AN		 2128 /* Host Controller v3.00 defines preset value registers */
2129 if (host->version < SDHCI_SPEC_300)
2130 return;
2131
4d55c5a1
AN		 2132 /*
2133 * We only enable or disable Preset Value if they are not already
2134 * enabled or disabled respectively. Otherwise, we bail out.
2135 */
da91a8f9
RK		 2136 if (host->preset_enabled != enable) {
2137 u16 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2138
2139 if (enable)
2140 ctrl |= SDHCI_CTRL_PRESET_VAL_ENABLE;
2141 else
2142 ctrl &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
2143
4d55c5a1 2144 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
da91a8f9
RK		 2145
2146 if (enable)
2147 host->flags |= SDHCI_PV_ENABLED;
2148 else
2149 host->flags &= ~SDHCI_PV_ENABLED;
2150
2151 host->preset_enabled = enable;
4d55c5a1 2152 }
66fd8ad5
AH		 2153}
2154
348487cb
HC		 2155static void sdhci_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
2156 int err)
2157{
2158 struct sdhci_host *host = mmc_priv(mmc);
2159 struct mmc_data *data = mrq->data;
2160
f48f039c 2161 if (data->host_cookie != COOKIE_UNMAPPED)
771a3dc2
RK		 2162 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
2163 data->flags & MMC_DATA_WRITE ?
2164 DMA_TO_DEVICE : DMA_FROM_DEVICE);
2165
2166 data->host_cookie = COOKIE_UNMAPPED;
348487cb
HC		 2167}
2168
348487cb
HC		 2169static void sdhci_pre_req(struct mmc_host *mmc, struct mmc_request *mrq,
2170 bool is_first_req)
2171{
2172 struct sdhci_host *host = mmc_priv(mmc);
2173
d31911b9 2174 mrq->data->host_cookie = COOKIE_UNMAPPED;
348487cb
HC		 2175
2176 if (host->flags & SDHCI_REQ_USE_DMA)
94538e51 2177 sdhci_pre_dma_transfer(host, mrq->data, COOKIE_PRE_MAPPED);
348487cb
HC		 2178}
2179
5d0d11c5
AH		 2180static inline bool sdhci_has_requests(struct sdhci_host *host)
2181{
2182 return host->cmd || host->data_cmd;
2183}
2184
2185static void sdhci_error_out_mrqs(struct sdhci_host *host, int err)
2186{
2187 if (host->data_cmd) {
2188 host->data_cmd->error = err;
2189 sdhci_finish_mrq(host, host->data_cmd->mrq);
2190 }
2191
2192 if (host->cmd) {
2193 host->cmd->error = err;
2194 sdhci_finish_mrq(host, host->cmd->mrq);
2195 }
2196}
2197
71e69211 2198static void sdhci_card_event(struct mmc_host *mmc)
d129bceb 2199{
71e69211 2200 struct sdhci_host *host = mmc_priv(mmc);
d129bceb 2201 unsigned long flags;
2836766a 2202 int present;
d129bceb 2203
722e1280
CD		 2204 /* First check if client has provided their own card event */
2205 if (host->ops->card_event)
2206 host->ops->card_event(host);
2207
d3940f27 2208 present = mmc->ops->get_cd(mmc);
2836766a 2209
d129bceb
PO		 2210 spin_lock_irqsave(&host->lock, flags);
2211
5d0d11c5
AH		 2212 /* Check sdhci_has_requests() first in case we are runtime suspended */
2213 if (sdhci_has_requests(host) && !present) {
a3c76eb9 2214 pr_err("%s: Card removed during transfer!\n",
66fd8ad5 2215 mmc_hostname(host->mmc));
a3c76eb9 2216 pr_err("%s: Resetting controller.\n",
66fd8ad5 2217 mmc_hostname(host->mmc));
d129bceb 2218
03231f9b
RK		 2219 sdhci_do_reset(host, SDHCI_RESET_CMD);
2220 sdhci_do_reset(host, SDHCI_RESET_DATA);
d129bceb 2221
5d0d11c5 2222 sdhci_error_out_mrqs(host, -ENOMEDIUM);
d129bceb
PO		 2223 }
2224
2225 spin_unlock_irqrestore(&host->lock, flags);
71e69211
GL		 2226}
2227
2228static const struct mmc_host_ops sdhci_ops = {
2229 .request = sdhci_request,
348487cb
HC		 2230 .post_req = sdhci_post_req,
2231 .pre_req = sdhci_pre_req,
71e69211 2232 .set_ios = sdhci_set_ios,
94144a46 2233 .get_cd = sdhci_get_cd,
71e69211
GL		 2234 .get_ro = sdhci_get_ro,
2235 .hw_reset = sdhci_hw_reset,
2236 .enable_sdio_irq = sdhci_enable_sdio_irq,
2237 .start_signal_voltage_switch = sdhci_start_signal_voltage_switch,
b5540ce1 2238 .prepare_hs400_tuning = sdhci_prepare_hs400_tuning,
71e69211 2239 .execute_tuning = sdhci_execute_tuning,
cb849648 2240 .select_drive_strength = sdhci_select_drive_strength,
71e69211 2241 .card_event = sdhci_card_event,
20b92a30 2242 .card_busy = sdhci_card_busy,
71e69211
GL		 2243};
2244
2245/*****************************************************************************\
2246 * *
2247 * Tasklets *
2248 * *
2249\*****************************************************************************/
2250
4e9f8fe5 2251static bool sdhci_request_done(struct sdhci_host *host)
d129bceb 2252{
d129bceb
PO		 2253 unsigned long flags;
2254 struct mmc_request *mrq;
4e9f8fe5 2255 int i;
d129bceb 2256
66fd8ad5
AH		 2257 spin_lock_irqsave(&host->lock, flags);
2258
4e9f8fe5
AH		 2259 for (i = 0; i < SDHCI_MAX_MRQS; i++) {
2260 mrq = host->mrqs_done[i];
2261 if (mrq) {
2262 host->mrqs_done[i] = NULL;
2263 break;
2264 }
66fd8ad5 2265 }
d129bceb 2266
4e9f8fe5
AH		 2267 if (!mrq) {
2268 spin_unlock_irqrestore(&host->lock, flags);
2269 return true;
2270 }
d129bceb 2271
d7422fb4
AH		 2272 sdhci_del_timer(host, mrq);
2273
054cedff
RK		 2274 /*
2275 * Always unmap the data buffers if they were mapped by
2276 * sdhci_prepare_data() whenever we finish with a request.
2277 * This avoids leaking DMA mappings on error.
2278 */
2279 if (host->flags & SDHCI_REQ_USE_DMA) {
2280 struct mmc_data *data = mrq->data;
2281
2282 if (data && data->host_cookie == COOKIE_MAPPED) {
2283 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
2284 (data->flags & MMC_DATA_READ) ?
2285 DMA_FROM_DEVICE : DMA_TO_DEVICE);
2286 data->host_cookie = COOKIE_UNMAPPED;
2287 }
2288 }
2289
d129bceb
PO		 2290 /*
2291 * The controller needs a reset of internal state machines
2292 * upon error conditions.
2293 */
0cc563ce 2294 if (sdhci_needs_reset(host, mrq)) {
645289dc 2295 /* Some controllers need this kick or reset won't work here */
8213af3b 2296 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)
645289dc 2297 /* This is to force an update */
1771059c 2298 host->ops->set_clock(host, host->clock);
645289dc
PO		 2299
2300 /* Spec says we should do both at the same time, but Ricoh
2301 controllers do not like that. */
03231f9b
RK		 2302 sdhci_do_reset(host, SDHCI_RESET_CMD);
2303 sdhci_do_reset(host, SDHCI_RESET_DATA);
ed1563de
AH		 2304
2305 host->pending_reset = false;
d129bceb
PO		 2306 }
2307
4e9f8fe5
AH		 2308 if (!sdhci_has_requests(host))
2309 sdhci_led_deactivate(host);
d129bceb 2310
5f25a66f 2311 mmiowb();
d129bceb
PO		 2312 spin_unlock_irqrestore(&host->lock, flags);
2313
2314 mmc_request_done(host->mmc, mrq);
4e9f8fe5
AH		 2315
2316 return false;
2317}
2318
2319static void sdhci_tasklet_finish(unsigned long param)
2320{
2321 struct sdhci_host *host = (struct sdhci_host *)param;
2322
2323 while (!sdhci_request_done(host))
2324 ;
d129bceb
PO		 2325}
2326
2327static void sdhci_timeout_timer(unsigned long data)
2328{
2329 struct sdhci_host *host;
2330 unsigned long flags;
2331
2332 host = (struct sdhci_host*)data;
2333
2334 spin_lock_irqsave(&host->lock, flags);
2335
d7422fb4
AH		 2336 if (host->cmd && !sdhci_data_line_cmd(host->cmd)) {
2337 pr_err("%s: Timeout waiting for hardware cmd interrupt.\n",
2338 mmc_hostname(host->mmc));
2339 sdhci_dumpregs(host);
2340
2341 host->cmd->error = -ETIMEDOUT;
2342 sdhci_finish_mrq(host, host->cmd->mrq);
2343 }
2344
2345 mmiowb();
2346 spin_unlock_irqrestore(&host->lock, flags);
2347}
2348
2349static void sdhci_timeout_data_timer(unsigned long data)
2350{
2351 struct sdhci_host *host;
2352 unsigned long flags;
2353
2354 host = (struct sdhci_host *)data;
2355
2356 spin_lock_irqsave(&host->lock, flags);
2357
2358 if (host->data || host->data_cmd ||
2359 (host->cmd && sdhci_data_line_cmd(host->cmd))) {
2e4456f0
MV		 2360 pr_err("%s: Timeout waiting for hardware interrupt.\n",
2361 mmc_hostname(host->mmc));
d129bceb
PO		 2362 sdhci_dumpregs(host);
2363
2364 if (host->data) {
17b0429d 2365 host->data->error = -ETIMEDOUT;
d129bceb 2366 sdhci_finish_data(host);
d7422fb4
AH		 2367 } else if (host->data_cmd) {
2368 host->data_cmd->error = -ETIMEDOUT;
2369 sdhci_finish_mrq(host, host->data_cmd->mrq);
d129bceb 2370 } else {
d7422fb4
AH		 2371 host->cmd->error = -ETIMEDOUT;
2372 sdhci_finish_mrq(host, host->cmd->mrq);
d129bceb
PO		 2373 }
2374 }
2375
5f25a66f 2376 mmiowb();
d129bceb
PO		 2377 spin_unlock_irqrestore(&host->lock, flags);
2378}
2379
2380/*****************************************************************************\
2381 * *
2382 * Interrupt handling *
2383 * *
2384\*****************************************************************************/
2385
61541397 2386static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask, u32 *mask)
d129bceb 2387{
d129bceb 2388 if (!host->cmd) {
ed1563de
AH		 2389 /*
2390 * SDHCI recovers from errors by resetting the cmd and data
2391 * circuits. Until that is done, there very well might be more
2392 * interrupts, so ignore them in that case.
2393 */
2394 if (host->pending_reset)
2395 return;
2e4456f0
MV		 2396 pr_err("%s: Got command interrupt 0x%08x even though no command operation was in progress.\n",
2397 mmc_hostname(host->mmc), (unsigned)intmask);
d129bceb
PO		 2398 sdhci_dumpregs(host);
2399 return;
2400 }
2401
ec014cba
RK		 2402 if (intmask & (SDHCI_INT_TIMEOUT | SDHCI_INT_CRC |
2403 SDHCI_INT_END_BIT | SDHCI_INT_INDEX)) {
2404 if (intmask & SDHCI_INT_TIMEOUT)
2405 host->cmd->error = -ETIMEDOUT;
2406 else
2407 host->cmd->error = -EILSEQ;
43b58b36 2408
71fcbda0
RK		 2409 /*
2410 * If this command initiates a data phase and a response
2411 * CRC error is signalled, the card can start transferring
2412 * data - the card may have received the command without
2413 * error. We must not terminate the mmc_request early.
2414 *
2415 * If the card did not receive the command or returned an
2416 * error which prevented it sending data, the data phase
2417 * will time out.
2418 */
2419 if (host->cmd->data &&
2420 (intmask & (SDHCI_INT_CRC | SDHCI_INT_TIMEOUT)) ==
2421 SDHCI_INT_CRC) {
2422 host->cmd = NULL;
2423 return;
2424 }
2425
a6d3bdd5 2426 sdhci_finish_mrq(host, host->cmd->mrq);
e809517f
PO		 2427 return;
2428 }
2429
6bde8681
AH		 2430 if ((host->quirks2 & SDHCI_QUIRK2_STOP_WITH_TC) &&
2431 !(host->cmd->flags & MMC_RSP_BUSY) && !host->data &&
2432 host->cmd->opcode == MMC_STOP_TRANSMISSION)
61541397 2433 *mask &= ~SDHCI_INT_DATA_END;
e809517f
PO		 2434
2435 if (intmask & SDHCI_INT_RESPONSE)
43b58b36 2436 sdhci_finish_command(host);
d129bceb
PO		 2437}
2438
0957c333 2439#ifdef CONFIG_MMC_DEBUG
08621b18 2440static void sdhci_adma_show_error(struct sdhci_host *host)
6882a8c0
BD		 2441{
2442 const char *name = mmc_hostname(host->mmc);
1c3d5f6d 2443 void *desc = host->adma_table;
6882a8c0
BD		 2444
2445 sdhci_dumpregs(host);
2446
2447 while (true) {
e57a5f61
AH		 2448 struct sdhci_adma2_64_desc *dma_desc = desc;
2449
2450 if (host->flags & SDHCI_USE_64_BIT_DMA)
2451 DBG("%s: %p: DMA 0x%08x%08x, LEN 0x%04x, Attr=0x%02x\n",
2452 name, desc, le32_to_cpu(dma_desc->addr_hi),
2453 le32_to_cpu(dma_desc->addr_lo),
2454 le16_to_cpu(dma_desc->len),
2455 le16_to_cpu(dma_desc->cmd));
2456 else
2457 DBG("%s: %p: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n",
2458 name, desc, le32_to_cpu(dma_desc->addr_lo),
2459 le16_to_cpu(dma_desc->len),
2460 le16_to_cpu(dma_desc->cmd));
6882a8c0 2461
76fe379a 2462 desc += host->desc_sz;
6882a8c0 2463
0545230f 2464 if (dma_desc->cmd & cpu_to_le16(ADMA2_END))
6882a8c0
BD		 2465 break;
2466 }
2467}
2468#else
08621b18 2469static void sdhci_adma_show_error(struct sdhci_host *host) { }
6882a8c0
BD		 2470#endif
2471
d129bceb
PO		 2472static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
2473{
069c9f14 2474 u32 command;
d129bceb 2475
b513ea25
AN		 2476 /* CMD19 generates _only_ Buffer Read Ready interrupt */
2477 if (intmask & SDHCI_INT_DATA_AVAIL) {
069c9f14
G		 2478 command = SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND));
2479 if (command == MMC_SEND_TUNING_BLOCK ||
2480 command == MMC_SEND_TUNING_BLOCK_HS200) {
b513ea25
AN		 2481 host->tuning_done = 1;
2482 wake_up(&host->buf_ready_int);
2483 return;
2484 }
2485 }
2486
d129bceb 2487 if (!host->data) {
7c89a3d9
AH		 2488 struct mmc_command *data_cmd = host->data_cmd;
2489
2490 if (data_cmd)
2491 host->data_cmd = NULL;
2492
d129bceb 2493 /*
e809517f
PO		 2494 * The "data complete" interrupt is also used to
2495 * indicate that a busy state has ended. See comment
2496 * above in sdhci_cmd_irq().
d129bceb 2497 */
7c89a3d9 2498 if (data_cmd && (data_cmd->flags & MMC_RSP_BUSY)) {
c5abd5e8 2499 if (intmask & SDHCI_INT_DATA_TIMEOUT) {
7c89a3d9 2500 data_cmd->error = -ETIMEDOUT;
a6d3bdd5 2501 sdhci_finish_mrq(host, data_cmd->mrq);
c5abd5e8
MC		 2502 return;
2503 }
e809517f 2504 if (intmask & SDHCI_INT_DATA_END) {
e99783a4
CM		 2505 /*
2506 * Some cards handle busy-end interrupt
2507 * before the command completed, so make
2508 * sure we do things in the proper order.
2509 */
ea968023
AH		 2510 if (host->cmd == data_cmd)
2511 return;
2512
a6d3bdd5 2513 sdhci_finish_mrq(host, data_cmd->mrq);
e809517f
PO		 2514 return;
2515 }
2516 }
d129bceb 2517
ed1563de
AH		 2518 /*
2519 * SDHCI recovers from errors by resetting the cmd and data
2520 * circuits. Until that is done, there very well might be more
2521 * interrupts, so ignore them in that case.
2522 */
2523 if (host->pending_reset)
2524 return;
2525
2e4456f0
MV		 2526 pr_err("%s: Got data interrupt 0x%08x even though no data operation was in progress.\n",
2527 mmc_hostname(host->mmc), (unsigned)intmask);
d129bceb
PO		 2528 sdhci_dumpregs(host);
2529
2530 return;
2531 }
2532
2533 if (intmask & SDHCI_INT_DATA_TIMEOUT)
17b0429d 2534 host->data->error = -ETIMEDOUT;
22113efd
AL		 2535 else if (intmask & SDHCI_INT_DATA_END_BIT)
2536 host->data->error = -EILSEQ;
2537 else if ((intmask & SDHCI_INT_DATA_CRC) &&
2538 SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))
2539 != MMC_BUS_TEST_R)
17b0429d 2540 host->data->error = -EILSEQ;
6882a8c0 2541 else if (intmask & SDHCI_INT_ADMA_ERROR) {
a3c76eb9 2542 pr_err("%s: ADMA error\n", mmc_hostname(host->mmc));
08621b18 2543 sdhci_adma_show_error(host);
2134a922 2544 host->data->error = -EIO;
a4071fbb
HZ		 2545 if (host->ops->adma_workaround)
2546 host->ops->adma_workaround(host, intmask);
6882a8c0 2547 }
d129bceb 2548
17b0429d 2549 if (host->data->error)
d129bceb
PO		 2550 sdhci_finish_data(host);
2551 else {
a406f5a3 2552 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
d129bceb
PO		 2553 sdhci_transfer_pio(host);
2554
6ba736a1
PO		 2555 /*
2556 * We currently don't do anything fancy with DMA
2557 * boundaries, but as we can't disable the feature
2558 * we need to at least restart the transfer.
f6a03cbf
MV		 2559 *
2560 * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS)
2561 * should return a valid address to continue from, but as
2562 * some controllers are faulty, don't trust them.
6ba736a1 2563 */
f6a03cbf
MV		 2564 if (intmask & SDHCI_INT_DMA_END) {
2565 u32 dmastart, dmanow;
2566 dmastart = sg_dma_address(host->data->sg);
2567 dmanow = dmastart + host->data->bytes_xfered;
2568 /*
2569 * Force update to the next DMA block boundary.
2570 */
2571 dmanow = (dmanow &
2572 ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) +
2573 SDHCI_DEFAULT_BOUNDARY_SIZE;
2574 host->data->bytes_xfered = dmanow - dmastart;
2575 DBG("%s: DMA base 0x%08x, transferred 0x%06x bytes,"
2576 " next 0x%08x\n",
2577 mmc_hostname(host->mmc), dmastart,
2578 host->data->bytes_xfered, dmanow);
2579 sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS);
2580 }
6ba736a1 2581
e538fbe8 2582 if (intmask & SDHCI_INT_DATA_END) {
7c89a3d9 2583 if (host->cmd == host->data_cmd) {
e538fbe8
PO		 2584 /*
2585 * Data managed to finish before the
2586 * command completed. Make sure we do
2587 * things in the proper order.
2588 */
2589 host->data_early = 1;
2590 } else {
2591 sdhci_finish_data(host);
2592 }
2593 }
d129bceb
PO		 2594 }
2595}
2596
7d12e780 2597static irqreturn_t sdhci_irq(int irq, void *dev_id)
d129bceb 2598{
781e989c 2599 irqreturn_t result = IRQ_NONE;
66fd8ad5 2600 struct sdhci_host *host = dev_id;
41005003 2601 u32 intmask, mask, unexpected = 0;
781e989c 2602 int max_loops = 16;
d129bceb
PO		 2603
2604 spin_lock(&host->lock);
2605
be138554 2606 if (host->runtime_suspended && !sdhci_sdio_irq_enabled(host)) {
66fd8ad5 2607 spin_unlock(&host->lock);
655bca76 2608 return IRQ_NONE;
66fd8ad5
AH		 2609 }
2610
4e4141a5 2611 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
62df67a5 2612 if (!intmask || intmask == 0xffffffff) {
d129bceb
PO		 2613 result = IRQ_NONE;
2614 goto out;
2615 }
2616
41005003
RK		 2617 do {
2618 /* Clear selected interrupts. */
2619 mask = intmask & (SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
2620 SDHCI_INT_BUS_POWER);
2621 sdhci_writel(host, mask, SDHCI_INT_STATUS);
d129bceb 2622
41005003
RK		 2623 DBG("*** %s got interrupt: 0x%08x\n",
2624 mmc_hostname(host->mmc), intmask);
d129bceb 2625
41005003
RK		 2626 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
2627 u32 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
2628 SDHCI_CARD_PRESENT;
d129bceb 2629
41005003
RK		 2630 /*
2631 * There is a observation on i.mx esdhc. INSERT
2632 * bit will be immediately set again when it gets
2633 * cleared, if a card is inserted. We have to mask
2634 * the irq to prevent interrupt storm which will
2635 * freeze the system. And the REMOVE gets the
2636 * same situation.
2637 *
2638 * More testing are needed here to ensure it works
2639 * for other platforms though.
2640 */
b537f94c
RK		 2641 host->ier &= ~(SDHCI_INT_CARD_INSERT |
2642 SDHCI_INT_CARD_REMOVE);
2643 host->ier |= present ? SDHCI_INT_CARD_REMOVE :
2644 SDHCI_INT_CARD_INSERT;
2645 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2646 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
41005003
RK		 2647
2648 sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT |
2649 SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS);
3560db8e
RK		 2650
2651 host->thread_isr |= intmask & (SDHCI_INT_CARD_INSERT |
2652 SDHCI_INT_CARD_REMOVE);
2653 result = IRQ_WAKE_THREAD;
41005003 2654 }
d129bceb 2655
41005003 2656 if (intmask & SDHCI_INT_CMD_MASK)
61541397
AH		 2657 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK,
2658 &intmask);
964f9ce2 2659
41005003
RK		 2660 if (intmask & SDHCI_INT_DATA_MASK)
2661 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
d129bceb 2662
41005003
RK		 2663 if (intmask & SDHCI_INT_BUS_POWER)
2664 pr_err("%s: Card is consuming too much power!\n",
2665 mmc_hostname(host->mmc));
3192a28f 2666
781e989c
RK		 2667 if (intmask & SDHCI_INT_CARD_INT) {
2668 sdhci_enable_sdio_irq_nolock(host, false);
2669 host->thread_isr |= SDHCI_INT_CARD_INT;
2670 result = IRQ_WAKE_THREAD;
2671 }
f75979b7 2672
41005003
RK		 2673 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE |
2674 SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
2675 SDHCI_INT_ERROR | SDHCI_INT_BUS_POWER |
2676 SDHCI_INT_CARD_INT);
f75979b7 2677
41005003
RK		 2678 if (intmask) {
2679 unexpected |= intmask;
2680 sdhci_writel(host, intmask, SDHCI_INT_STATUS);
2681 }
d129bceb 2682
781e989c
RK		 2683 if (result == IRQ_NONE)
2684 result = IRQ_HANDLED;
d129bceb 2685
41005003 2686 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
41005003 2687 } while (intmask && --max_loops);
d129bceb
PO		 2688out:
2689 spin_unlock(&host->lock);
2690
6379b237
AS		 2691 if (unexpected) {
2692 pr_err("%s: Unexpected interrupt 0x%08x.\n",
2693 mmc_hostname(host->mmc), unexpected);
2694 sdhci_dumpregs(host);
2695 }
f75979b7 2696
d129bceb
PO		 2697 return result;
2698}
2699
781e989c
RK		 2700static irqreturn_t sdhci_thread_irq(int irq, void *dev_id)
2701{
2702 struct sdhci_host *host = dev_id;
2703 unsigned long flags;
2704 u32 isr;
2705
2706 spin_lock_irqsave(&host->lock, flags);
2707 isr = host->thread_isr;
2708 host->thread_isr = 0;
2709 spin_unlock_irqrestore(&host->lock, flags);
2710
3560db8e 2711 if (isr & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
d3940f27
AH		 2712 struct mmc_host *mmc = host->mmc;
2713
2714 mmc->ops->card_event(mmc);
2715 mmc_detect_change(mmc, msecs_to_jiffies(200));
3560db8e
RK		 2716 }
2717
781e989c
RK		 2718 if (isr & SDHCI_INT_CARD_INT) {
2719 sdio_run_irqs(host->mmc);
2720
2721 spin_lock_irqsave(&host->lock, flags);
2722 if (host->flags & SDHCI_SDIO_IRQ_ENABLED)
2723 sdhci_enable_sdio_irq_nolock(host, true);
2724 spin_unlock_irqrestore(&host->lock, flags);
2725 }
2726
2727 return isr ? IRQ_HANDLED : IRQ_NONE;
2728}
2729
d129bceb
PO		 2730/*****************************************************************************\
2731 * *
2732 * Suspend/resume *
2733 * *
2734\*****************************************************************************/
2735
2736#ifdef CONFIG_PM
84d62605
LD		 2737/*
2738 * To enable wakeup events, the corresponding events have to be enabled in
2739 * the Interrupt Status Enable register too. See 'Table 1-6: Wakeup Signal
2740 * Table' in the SD Host Controller Standard Specification.
2741 * It is useless to restore SDHCI_INT_ENABLE state in
2742 * sdhci_disable_irq_wakeups() since it will be set by
2743 * sdhci_enable_card_detection() or sdhci_init().
2744 */
ad080d79
KL		 2745void sdhci_enable_irq_wakeups(struct sdhci_host *host)
2746{
2747 u8 val;
2748 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
2749 | SDHCI_WAKE_ON_INT;
84d62605
LD		 2750 u32 irq_val = SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE |
2751 SDHCI_INT_CARD_INT;
ad080d79
KL		 2752
2753 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2754 val |= mask ;
2755 /* Avoid fake wake up */
84d62605 2756 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) {
ad080d79 2757 val &= ~(SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE);
84d62605
LD		 2758 irq_val &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE);
2759 }
ad080d79 2760 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
84d62605 2761 sdhci_writel(host, irq_val, SDHCI_INT_ENABLE);
ad080d79
KL		 2762}
2763EXPORT_SYMBOL_GPL(sdhci_enable_irq_wakeups);
2764
0b10f478 2765static void sdhci_disable_irq_wakeups(struct sdhci_host *host)
ad080d79
KL		 2766{
2767 u8 val;
2768 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
2769 | SDHCI_WAKE_ON_INT;
2770
2771 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2772 val &= ~mask;
2773 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2774}
d129bceb 2775
29495aa0 2776int sdhci_suspend_host(struct sdhci_host *host)
d129bceb 2777{
7260cf5e
AV		 2778 sdhci_disable_card_detection(host);
2779
66c39dfc
AH		 2780 mmc_retune_timer_stop(host->mmc);
2781 mmc_retune_needed(host->mmc);
cf2b5eea 2782
ad080d79 2783 if (!device_may_wakeup(mmc_dev(host->mmc))) {
b537f94c
RK		 2784 host->ier = 0;
2785 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
2786 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
ad080d79
KL		 2787 free_irq(host->irq, host);
2788 } else {
2789 sdhci_enable_irq_wakeups(host);
2790 enable_irq_wake(host->irq);
2791 }
4ee14ec6 2792 return 0;
d129bceb
PO		 2793}
2794
b8c86fc5 2795EXPORT_SYMBOL_GPL(sdhci_suspend_host);
d129bceb 2796
b8c86fc5
PO		 2797int sdhci_resume_host(struct sdhci_host *host)
2798{
d3940f27 2799 struct mmc_host *mmc = host->mmc;
4ee14ec6 2800 int ret = 0;
d129bceb 2801
a13abc7b 2802 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
b8c86fc5
PO		 2803 if (host->ops->enable_dma)
2804 host->ops->enable_dma(host);
2805 }
d129bceb 2806
6308d290
AH		 2807 if ((host->mmc->pm_flags & MMC_PM_KEEP_POWER) &&
2808 (host->quirks2 & SDHCI_QUIRK2_HOST_OFF_CARD_ON)) {
2809 /* Card keeps power but host controller does not */
2810 sdhci_init(host, 0);
2811 host->pwr = 0;
2812 host->clock = 0;
d3940f27 2813 mmc->ops->set_ios(mmc, &mmc->ios);
6308d290
AH		 2814 } else {
2815 sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER));
2816 mmiowb();
2817 }
b8c86fc5 2818
14a7b416
HC		 2819 if (!device_may_wakeup(mmc_dev(host->mmc))) {
2820 ret = request_threaded_irq(host->irq, sdhci_irq,
2821 sdhci_thread_irq, IRQF_SHARED,
2822 mmc_hostname(host->mmc), host);
2823 if (ret)
2824 return ret;
2825 } else {
2826 sdhci_disable_irq_wakeups(host);
2827 disable_irq_wake(host->irq);
2828 }
2829
7260cf5e
AV		 2830 sdhci_enable_card_detection(host);
2831
2f4cbb3d 2832 return ret;
d129bceb
PO		 2833}
2834
b8c86fc5 2835EXPORT_SYMBOL_GPL(sdhci_resume_host);
66fd8ad5 2836
66fd8ad5
AH		 2837int sdhci_runtime_suspend_host(struct sdhci_host *host)
2838{
2839 unsigned long flags;
66fd8ad5 2840
66c39dfc
AH		 2841 mmc_retune_timer_stop(host->mmc);
2842 mmc_retune_needed(host->mmc);
66fd8ad5
AH		 2843
2844 spin_lock_irqsave(&host->lock, flags);
b537f94c
RK		 2845 host->ier &= SDHCI_INT_CARD_INT;
2846 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2847 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
66fd8ad5
AH		 2848 spin_unlock_irqrestore(&host->lock, flags);
2849
781e989c 2850 synchronize_hardirq(host->irq);
66fd8ad5
AH		 2851
2852 spin_lock_irqsave(&host->lock, flags);
2853 host->runtime_suspended = true;
2854 spin_unlock_irqrestore(&host->lock, flags);
2855
8a125bad 2856 return 0;
66fd8ad5
AH		 2857}
2858EXPORT_SYMBOL_GPL(sdhci_runtime_suspend_host);
2859
2860int sdhci_runtime_resume_host(struct sdhci_host *host)
2861{
d3940f27 2862 struct mmc_host *mmc = host->mmc;
66fd8ad5 2863 unsigned long flags;
8a125bad 2864 int host_flags = host->flags;
66fd8ad5
AH		 2865
2866 if (host_flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2867 if (host->ops->enable_dma)
2868 host->ops->enable_dma(host);
2869 }
2870
2871 sdhci_init(host, 0);
2872
2873 /* Force clock and power re-program */
2874 host->pwr = 0;
2875 host->clock = 0;
d3940f27
AH		 2876 mmc->ops->start_signal_voltage_switch(mmc, &mmc->ios);
2877 mmc->ops->set_ios(mmc, &mmc->ios);
66fd8ad5 2878
52983382
KL		 2879 if ((host_flags & SDHCI_PV_ENABLED) &&
2880 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN)) {
2881 spin_lock_irqsave(&host->lock, flags);
2882 sdhci_enable_preset_value(host, true);
2883 spin_unlock_irqrestore(&host->lock, flags);
2884 }
66fd8ad5 2885
66fd8ad5
AH		 2886 spin_lock_irqsave(&host->lock, flags);
2887
2888 host->runtime_suspended = false;
2889
2890 /* Enable SDIO IRQ */
ef104333 2891 if (host->flags & SDHCI_SDIO_IRQ_ENABLED)
66fd8ad5
AH		 2892 sdhci_enable_sdio_irq_nolock(host, true);
2893
2894 /* Enable Card Detection */
2895 sdhci_enable_card_detection(host);
2896
2897 spin_unlock_irqrestore(&host->lock, flags);
2898
8a125bad 2899 return 0;
66fd8ad5
AH		 2900}
2901EXPORT_SYMBOL_GPL(sdhci_runtime_resume_host);
2902
162d6f98 2903#endif /* CONFIG_PM */
66fd8ad5 2904
d129bceb
PO		 2905/*****************************************************************************\
2906 * *
b8c86fc5 2907 * Device allocation/registration *
d129bceb
PO		 2908 * *
2909\*****************************************************************************/
2910
b8c86fc5
PO		 2911struct sdhci_host *sdhci_alloc_host(struct device *dev,
2912 size_t priv_size)
d129bceb 2913{
d129bceb
PO		 2914 struct mmc_host *mmc;
2915 struct sdhci_host *host;
2916
b8c86fc5 2917 WARN_ON(dev == NULL);
d129bceb 2918
b8c86fc5 2919 mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev);
d129bceb 2920 if (!mmc)
b8c86fc5 2921 return ERR_PTR(-ENOMEM);
d129bceb
PO		 2922
2923 host = mmc_priv(mmc);
2924 host->mmc = mmc;
bf60e592
AH		 2925 host->mmc_host_ops = sdhci_ops;
2926 mmc->ops = &host->mmc_host_ops;
d129bceb 2927
8cb851a4
AH		 2928 host->flags = SDHCI_SIGNALING_330;
2929
b8c86fc5
PO		 2930 return host;
2931}
8a4da143 2932
b8c86fc5 2933EXPORT_SYMBOL_GPL(sdhci_alloc_host);
d129bceb 2934
7b91369b
AC		 2935static int sdhci_set_dma_mask(struct sdhci_host *host)
2936{
2937 struct mmc_host *mmc = host->mmc;
2938 struct device *dev = mmc_dev(mmc);
2939 int ret = -EINVAL;
2940
2941 if (host->quirks2 & SDHCI_QUIRK2_BROKEN_64_BIT_DMA)
2942 host->flags &= ~SDHCI_USE_64_BIT_DMA;
2943
2944 /* Try 64-bit mask if hardware is capable of it */
2945 if (host->flags & SDHCI_USE_64_BIT_DMA) {
2946 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64));
2947 if (ret) {
2948 pr_warn("%s: Failed to set 64-bit DMA mask.\n",
2949 mmc_hostname(mmc));
2950 host->flags &= ~SDHCI_USE_64_BIT_DMA;
2951 }
2952 }
2953
2954 /* 32-bit mask as default & fallback */
2955 if (ret) {
2956 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32));
2957 if (ret)
2958 pr_warn("%s: Failed to set 32-bit DMA mask.\n",
2959 mmc_hostname(mmc));
2960 }
2961
2962 return ret;
2963}
2964
6132a3bf
AH		 2965void __sdhci_read_caps(struct sdhci_host *host, u16 *ver, u32 *caps, u32 *caps1)
2966{
2967 u16 v;
2968
2969 if (host->read_caps)
2970 return;
2971
2972 host->read_caps = true;
2973
2974 if (debug_quirks)
2975 host->quirks = debug_quirks;
2976
2977 if (debug_quirks2)
2978 host->quirks2 = debug_quirks2;
2979
2980 sdhci_do_reset(host, SDHCI_RESET_ALL);
2981
2982 v = ver ? *ver : sdhci_readw(host, SDHCI_HOST_VERSION);
2983 host->version = (v & SDHCI_SPEC_VER_MASK) >> SDHCI_SPEC_VER_SHIFT;
2984
2985 if (host->quirks & SDHCI_QUIRK_MISSING_CAPS)
2986 return;
2987
2988 host->caps = caps ? *caps : sdhci_readl(host, SDHCI_CAPABILITIES);
2989
2990 if (host->version < SDHCI_SPEC_300)
2991 return;
2992
2993 host->caps1 = caps1 ? *caps1 : sdhci_readl(host, SDHCI_CAPABILITIES_1);
2994}
2995EXPORT_SYMBOL_GPL(__sdhci_read_caps);
2996
52f5336d 2997int sdhci_setup_host(struct sdhci_host *host)
b8c86fc5
PO		 2998{
2999 struct mmc_host *mmc;
f2119df6
AN		 3000 u32 max_current_caps;
3001 unsigned int ocr_avail;
f5fa92e5 3002 unsigned int override_timeout_clk;
59241757 3003 u32 max_clk;
b8c86fc5 3004 int ret;
d129bceb 3005
b8c86fc5
PO		 3006 WARN_ON(host == NULL);
3007 if (host == NULL)
3008 return -EINVAL;
d129bceb 3009
b8c86fc5 3010 mmc = host->mmc;
d129bceb 3011
6132a3bf 3012 sdhci_read_caps(host);
d129bceb 3013
f5fa92e5
AH		 3014 override_timeout_clk = host->timeout_clk;
3015
85105c53 3016 if (host->version > SDHCI_SPEC_300) {
2e4456f0
MV		 3017 pr_err("%s: Unknown controller version (%d). You may experience problems.\n",
3018 mmc_hostname(mmc), host->version);
4a965505
PO		 3019 }
3020
b8c86fc5 3021 if (host->quirks & SDHCI_QUIRK_FORCE_DMA)
a13abc7b 3022 host->flags |= SDHCI_USE_SDMA;
28da3589 3023 else if (!(host->caps & SDHCI_CAN_DO_SDMA))
a13abc7b 3024 DBG("Controller doesn't have SDMA capability\n");
67435274 3025 else
a13abc7b 3026 host->flags |= SDHCI_USE_SDMA;
d129bceb 3027
b8c86fc5 3028 if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
a13abc7b 3029 (host->flags & SDHCI_USE_SDMA)) {
cee687ce 3030 DBG("Disabling DMA as it is marked broken\n");
a13abc7b 3031 host->flags &= ~SDHCI_USE_SDMA;
7c168e3d
FT		 3032 }
3033
f2119df6 3034 if ((host->version >= SDHCI_SPEC_200) &&
28da3589 3035 (host->caps & SDHCI_CAN_DO_ADMA2))
a13abc7b 3036 host->flags |= SDHCI_USE_ADMA;
2134a922
PO		 3037
3038 if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) &&
3039 (host->flags & SDHCI_USE_ADMA)) {
3040 DBG("Disabling ADMA as it is marked broken\n");
3041 host->flags &= ~SDHCI_USE_ADMA;
3042 }
3043
e57a5f61
AH		 3044 /*
3045 * It is assumed that a 64-bit capable device has set a 64-bit DMA mask
3046 * and *must* do 64-bit DMA. A driver has the opportunity to change
3047 * that during the first call to ->enable_dma(). Similarly
3048 * SDHCI_QUIRK2_BROKEN_64_BIT_DMA must be left to the drivers to
3049 * implement.
3050 */
28da3589 3051 if (host->caps & SDHCI_CAN_64BIT)
e57a5f61
AH		 3052 host->flags |= SDHCI_USE_64_BIT_DMA;
3053
a13abc7b 3054 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
7b91369b
AC		 3055 ret = sdhci_set_dma_mask(host);
3056
3057 if (!ret && host->ops->enable_dma)
3058 ret = host->ops->enable_dma(host);
3059
3060 if (ret) {
3061 pr_warn("%s: No suitable DMA available - falling back to PIO\n",
3062 mmc_hostname(mmc));
3063 host->flags &= ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
3064
3065 ret = 0;
d129bceb
PO		 3066 }
3067 }
3068
e57a5f61
AH		 3069 /* SDMA does not support 64-bit DMA */
3070 if (host->flags & SDHCI_USE_64_BIT_DMA)
3071 host->flags &= ~SDHCI_USE_SDMA;
3072
2134a922 3073 if (host->flags & SDHCI_USE_ADMA) {
e66e61cb
RK		 3074 dma_addr_t dma;
3075 void *buf;
3076
2134a922 3077 /*
76fe379a
AH		 3078 * The DMA descriptor table size is calculated as the maximum
3079 * number of segments times 2, to allow for an alignment
3080 * descriptor for each segment, plus 1 for a nop end descriptor,
3081 * all multipled by the descriptor size.
2134a922 3082 */
e57a5f61
AH		 3083 if (host->flags & SDHCI_USE_64_BIT_DMA) {
3084 host->adma_table_sz = (SDHCI_MAX_SEGS * 2 + 1) *
3085 SDHCI_ADMA2_64_DESC_SZ;
e57a5f61 3086 host->desc_sz = SDHCI_ADMA2_64_DESC_SZ;
e57a5f61
AH		 3087 } else {
3088 host->adma_table_sz = (SDHCI_MAX_SEGS * 2 + 1) *
3089 SDHCI_ADMA2_32_DESC_SZ;
e57a5f61 3090 host->desc_sz = SDHCI_ADMA2_32_DESC_SZ;
e57a5f61 3091 }
e66e61cb 3092
04a5ae6f 3093 host->align_buffer_sz = SDHCI_MAX_SEGS * SDHCI_ADMA2_ALIGN;
e66e61cb
RK		 3094 buf = dma_alloc_coherent(mmc_dev(mmc), host->align_buffer_sz +
3095 host->adma_table_sz, &dma, GFP_KERNEL);
3096 if (!buf) {
6606110d 3097 pr_warn("%s: Unable to allocate ADMA buffers - falling back to standard DMA\n",
2134a922
PO		 3098 mmc_hostname(mmc));
3099 host->flags &= ~SDHCI_USE_ADMA;
e66e61cb
RK		 3100 } else if ((dma + host->align_buffer_sz) &
3101 (SDHCI_ADMA2_DESC_ALIGN - 1)) {
6606110d
JP		 3102 pr_warn("%s: unable to allocate aligned ADMA descriptor\n",
3103 mmc_hostname(mmc));
d1e49f77 3104 host->flags &= ~SDHCI_USE_ADMA;
e66e61cb
RK		 3105 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
3106 host->adma_table_sz, buf, dma);
3107 } else {
3108 host->align_buffer = buf;
3109 host->align_addr = dma;
edd63fcc 3110
e66e61cb
RK		 3111 host->adma_table = buf + host->align_buffer_sz;
3112 host->adma_addr = dma + host->align_buffer_sz;
3113 }
2134a922
PO		 3114 }
3115
7659150c
PO		 3116 /*
3117 * If we use DMA, then it's up to the caller to set the DMA
3118 * mask, but PIO does not need the hw shim so we set a new
3119 * mask here in that case.
3120 */
a13abc7b 3121 if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) {
7659150c 3122 host->dma_mask = DMA_BIT_MASK(64);
4e743f1f 3123 mmc_dev(mmc)->dma_mask = &host->dma_mask;
7659150c 3124 }
d129bceb 3125
c4687d5f 3126 if (host->version >= SDHCI_SPEC_300)
28da3589 3127 host->max_clk = (host->caps & SDHCI_CLOCK_V3_BASE_MASK)
c4687d5f
ZG		 3128 >> SDHCI_CLOCK_BASE_SHIFT;
3129 else
28da3589 3130 host->max_clk = (host->caps & SDHCI_CLOCK_BASE_MASK)
c4687d5f
ZG		 3131 >> SDHCI_CLOCK_BASE_SHIFT;
3132
4240ff0a 3133 host->max_clk *= 1000000;
f27f47ef
AV		 3134 if (host->max_clk == 0 || host->quirks &
3135 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) {
4240ff0a 3136 if (!host->ops->get_max_clock) {
2e4456f0
MV		 3137 pr_err("%s: Hardware doesn't specify base clock frequency.\n",
3138 mmc_hostname(mmc));
eb5c20de
AH		 3139 ret = -ENODEV;
3140 goto undma;
4240ff0a
BD		 3141 }
3142 host->max_clk = host->ops->get_max_clock(host);
8ef1a143 3143 }
d129bceb 3144
c3ed3877
AN		 3145 /*
3146 * In case of Host Controller v3.00, find out whether clock
3147 * multiplier is supported.
3148 */
28da3589 3149 host->clk_mul = (host->caps1 & SDHCI_CLOCK_MUL_MASK) >>
c3ed3877
AN		 3150 SDHCI_CLOCK_MUL_SHIFT;
3151
3152 /*
3153 * In case the value in Clock Multiplier is 0, then programmable
3154 * clock mode is not supported, otherwise the actual clock
3155 * multiplier is one more than the value of Clock Multiplier
3156 * in the Capabilities Register.
3157 */
3158 if (host->clk_mul)
3159 host->clk_mul += 1;
3160
d129bceb
PO		 3161 /*
3162 * Set host parameters.
3163 */
59241757
DA		 3164 max_clk = host->max_clk;
3165
ce5f036b 3166 if (host->ops->get_min_clock)
a9e58f25 3167 mmc->f_min = host->ops->get_min_clock(host);
c3ed3877
AN		 3168 else if (host->version >= SDHCI_SPEC_300) {
3169 if (host->clk_mul) {
3170 mmc->f_min = (host->max_clk * host->clk_mul) / 1024;
59241757 3171 max_clk = host->max_clk * host->clk_mul;
c3ed3877
AN		 3172 } else
3173 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300;
3174 } else
0397526d 3175 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200;
15ec4461 3176
d310ae49 3177 if (!mmc->f_max || mmc->f_max > max_clk)
59241757
DA		 3178 mmc->f_max = max_clk;
3179
28aab053 3180 if (!(host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) {
28da3589 3181 host->timeout_clk = (host->caps & SDHCI_TIMEOUT_CLK_MASK) >>
28aab053
AD		 3182 SDHCI_TIMEOUT_CLK_SHIFT;
3183 if (host->timeout_clk == 0) {
3184 if (host->ops->get_timeout_clock) {
3185 host->timeout_clk =
3186 host->ops->get_timeout_clock(host);
3187 } else {
3188 pr_err("%s: Hardware doesn't specify timeout clock frequency.\n",
3189 mmc_hostname(mmc));
eb5c20de
AH		 3190 ret = -ENODEV;
3191 goto undma;
28aab053 3192 }
272308ca 3193 }
272308ca 3194
28da3589 3195 if (host->caps & SDHCI_TIMEOUT_CLK_UNIT)
28aab053 3196 host->timeout_clk *= 1000;
272308ca 3197
99513624
AH		 3198 if (override_timeout_clk)
3199 host->timeout_clk = override_timeout_clk;
3200
28aab053 3201 mmc->max_busy_timeout = host->ops->get_max_timeout_count ?
a6ff5aeb 3202 host->ops->get_max_timeout_count(host) : 1 << 27;
28aab053
AD		 3203 mmc->max_busy_timeout /= host->timeout_clk;
3204 }
58d1246d 3205
e89d456f 3206 mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_ERASE | MMC_CAP_CMD23;
781e989c 3207 mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD;
e89d456f
AW		 3208
3209 if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12)
3210 host->flags |= SDHCI_AUTO_CMD12;
5fe23c7f 3211
8edf6371 3212 /* Auto-CMD23 stuff only works in ADMA or PIO. */
4f3d3e9b 3213 if ((host->version >= SDHCI_SPEC_300) &&
8edf6371 3214 ((host->flags & SDHCI_USE_ADMA) ||
3bfa6f03
SB		 3215 !(host->flags & SDHCI_USE_SDMA)) &&
3216 !(host->quirks2 & SDHCI_QUIRK2_ACMD23_BROKEN)) {
8edf6371
AW		 3217 host->flags |= SDHCI_AUTO_CMD23;
3218 DBG("%s: Auto-CMD23 available\n", mmc_hostname(mmc));
3219 } else {
3220 DBG("%s: Auto-CMD23 unavailable\n", mmc_hostname(mmc));
3221 }
3222
15ec4461
PR		 3223 /*
3224 * A controller may support 8-bit width, but the board itself
3225 * might not have the pins brought out. Boards that support
3226 * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in
3227 * their platform code before calling sdhci_add_host(), and we
3228 * won't assume 8-bit width for hosts without that CAP.
3229 */
5fe23c7f 3230 if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA))
15ec4461 3231 mmc->caps |= MMC_CAP_4_BIT_DATA;
d129bceb 3232
63ef5d8c
JH		 3233 if (host->quirks2 & SDHCI_QUIRK2_HOST_NO_CMD23)
3234 mmc->caps &= ~MMC_CAP_CMD23;
3235
28da3589 3236 if (host->caps & SDHCI_CAN_DO_HISPD)
a29e7e18 3237 mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
cd9277c0 3238
176d1ed4 3239 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) &&
860951c5 3240 mmc_card_is_removable(mmc) &&
287980e4 3241 mmc_gpio_get_cd(host->mmc) < 0)
68d1fb7e
AV		 3242 mmc->caps |= MMC_CAP_NEEDS_POLL;
3243
3a48edc4 3244 /* If there are external regulators, get them */
eb5c20de
AH		 3245 ret = mmc_regulator_get_supply(mmc);
3246 if (ret == -EPROBE_DEFER)
3247 goto undma;
3a48edc4 3248
6231f3de 3249 /* If vqmmc regulator and no 1.8V signalling, then there's no UHS */
3a48edc4
TK		 3250 if (!IS_ERR(mmc->supply.vqmmc)) {
3251 ret = regulator_enable(mmc->supply.vqmmc);
3252 if (!regulator_is_supported_voltage(mmc->supply.vqmmc, 1700000,
3253 1950000))
28da3589
AH		 3254 host->caps1 &= ~(SDHCI_SUPPORT_SDR104 |
3255 SDHCI_SUPPORT_SDR50 |
3256 SDHCI_SUPPORT_DDR50);
a3361aba
CB		 3257 if (ret) {
3258 pr_warn("%s: Failed to enable vqmmc regulator: %d\n",
3259 mmc_hostname(mmc), ret);
4bb74313 3260 mmc->supply.vqmmc = ERR_PTR(-EINVAL);
a3361aba 3261 }
8363c374 3262 }
6231f3de 3263
28da3589
AH		 3264 if (host->quirks2 & SDHCI_QUIRK2_NO_1_8_V) {
3265 host->caps1 &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
3266 SDHCI_SUPPORT_DDR50);
3267 }
6a66180a 3268
4188bba0 3269 /* Any UHS-I mode in caps implies SDR12 and SDR25 support. */
28da3589
AH		 3270 if (host->caps1 & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
3271 SDHCI_SUPPORT_DDR50))
f2119df6
AN		 3272 mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;
3273
3274 /* SDR104 supports also implies SDR50 support */
28da3589 3275 if (host->caps1 & SDHCI_SUPPORT_SDR104) {
f2119df6 3276 mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50;
156e14b1
GC		 3277 /* SD3.0: SDR104 is supported so (for eMMC) the caps2
3278 * field can be promoted to support HS200.
3279 */
549c0b18 3280 if (!(host->quirks2 & SDHCI_QUIRK2_BROKEN_HS200))
13868bf2 3281 mmc->caps2 |= MMC_CAP2_HS200;
28da3589 3282 } else if (host->caps1 & SDHCI_SUPPORT_SDR50) {
f2119df6 3283 mmc->caps |= MMC_CAP_UHS_SDR50;
28da3589 3284 }
f2119df6 3285
e9fb05d5 3286 if (host->quirks2 & SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 &&
28da3589 3287 (host->caps1 & SDHCI_SUPPORT_HS400))
e9fb05d5
AH		 3288 mmc->caps2 |= MMC_CAP2_HS400;
3289
549c0b18
AH		 3290 if ((mmc->caps2 & MMC_CAP2_HSX00_1_2V) &&
3291 (IS_ERR(mmc->supply.vqmmc) ||
3292 !regulator_is_supported_voltage(mmc->supply.vqmmc, 1100000,
3293 1300000)))
3294 mmc->caps2 &= ~MMC_CAP2_HSX00_1_2V;
3295
28da3589
AH		 3296 if ((host->caps1 & SDHCI_SUPPORT_DDR50) &&
3297 !(host->quirks2 & SDHCI_QUIRK2_BROKEN_DDR50))
f2119df6
AN		 3298 mmc->caps |= MMC_CAP_UHS_DDR50;
3299
069c9f14 3300 /* Does the host need tuning for SDR50? */
28da3589 3301 if (host->caps1 & SDHCI_USE_SDR50_TUNING)
b513ea25
AN		 3302 host->flags |= SDHCI_SDR50_NEEDS_TUNING;
3303
d6d50a15 3304 /* Driver Type(s) (A, C, D) supported by the host */
28da3589 3305 if (host->caps1 & SDHCI_DRIVER_TYPE_A)
d6d50a15 3306 mmc->caps |= MMC_CAP_DRIVER_TYPE_A;
28da3589 3307 if (host->caps1 & SDHCI_DRIVER_TYPE_C)
d6d50a15 3308 mmc->caps |= MMC_CAP_DRIVER_TYPE_C;
28da3589 3309 if (host->caps1 & SDHCI_DRIVER_TYPE_D)
d6d50a15
AN		 3310 mmc->caps |= MMC_CAP_DRIVER_TYPE_D;
3311
cf2b5eea 3312 /* Initial value for re-tuning timer count */
28da3589
AH		 3313 host->tuning_count = (host->caps1 & SDHCI_RETUNING_TIMER_COUNT_MASK) >>
3314 SDHCI_RETUNING_TIMER_COUNT_SHIFT;
cf2b5eea
AN		 3315
3316 /*
3317 * In case Re-tuning Timer is not disabled, the actual value of
3318 * re-tuning timer will be 2 ^ (n - 1).
3319 */
3320 if (host->tuning_count)
3321 host->tuning_count = 1 << (host->tuning_count - 1);
3322
3323 /* Re-tuning mode supported by the Host Controller */
28da3589 3324 host->tuning_mode = (host->caps1 & SDHCI_RETUNING_MODE_MASK) >>
cf2b5eea
AN		 3325 SDHCI_RETUNING_MODE_SHIFT;
3326
8f230f45 3327 ocr_avail = 0;
bad37e1a 3328
f2119df6
AN		 3329 /*
3330 * According to SD Host Controller spec v3.00, if the Host System
3331 * can afford more than 150mA, Host Driver should set XPC to 1. Also
3332 * the value is meaningful only if Voltage Support in the Capabilities
3333 * register is set. The actual current value is 4 times the register
3334 * value.
3335 */
3336 max_current_caps = sdhci_readl(host, SDHCI_MAX_CURRENT);
3a48edc4 3337 if (!max_current_caps && !IS_ERR(mmc->supply.vmmc)) {
ae906037 3338 int curr = regulator_get_current_limit(mmc->supply.vmmc);
bad37e1a
PR		 3339 if (curr > 0) {
3340
3341 /* convert to SDHCI_MAX_CURRENT format */
3342 curr = curr/1000; /* convert to mA */
3343 curr = curr/SDHCI_MAX_CURRENT_MULTIPLIER;
3344
3345 curr = min_t(u32, curr, SDHCI_MAX_CURRENT_LIMIT);
3346 max_current_caps =
3347 (curr << SDHCI_MAX_CURRENT_330_SHIFT) |
3348 (curr << SDHCI_MAX_CURRENT_300_SHIFT) |
3349 (curr << SDHCI_MAX_CURRENT_180_SHIFT);
3350 }
3351 }
f2119df6 3352
28da3589 3353 if (host->caps & SDHCI_CAN_VDD_330) {
8f230f45 3354 ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34;
f2119df6 3355
55c4665e 3356 mmc->max_current_330 = ((max_current_caps &
f2119df6
AN		 3357 SDHCI_MAX_CURRENT_330_MASK) >>
3358 SDHCI_MAX_CURRENT_330_SHIFT) *
3359 SDHCI_MAX_CURRENT_MULTIPLIER;
f2119df6 3360 }
28da3589 3361 if (host->caps & SDHCI_CAN_VDD_300) {
8f230f45 3362 ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31;
f2119df6 3363
55c4665e 3364 mmc->max_current_300 = ((max_current_caps &
f2119df6
AN		 3365 SDHCI_MAX_CURRENT_300_MASK) >>
3366 SDHCI_MAX_CURRENT_300_SHIFT) *
3367 SDHCI_MAX_CURRENT_MULTIPLIER;
f2119df6 3368 }
28da3589 3369 if (host->caps & SDHCI_CAN_VDD_180) {
8f230f45
TI		 3370 ocr_avail |= MMC_VDD_165_195;
3371
55c4665e 3372 mmc->max_current_180 = ((max_current_caps &
f2119df6
AN		 3373 SDHCI_MAX_CURRENT_180_MASK) >>
3374 SDHCI_MAX_CURRENT_180_SHIFT) *
3375 SDHCI_MAX_CURRENT_MULTIPLIER;
f2119df6
AN		 3376 }
3377
5fd26c7e
UH		 3378 /* If OCR set by host, use it instead. */
3379 if (host->ocr_mask)
3380 ocr_avail = host->ocr_mask;
3381
3382 /* If OCR set by external regulators, give it highest prio. */
3a48edc4 3383 if (mmc->ocr_avail)
52221610 3384 ocr_avail = mmc->ocr_avail;
3a48edc4 3385
8f230f45
TI		 3386 mmc->ocr_avail = ocr_avail;
3387 mmc->ocr_avail_sdio = ocr_avail;
3388 if (host->ocr_avail_sdio)
3389 mmc->ocr_avail_sdio &= host->ocr_avail_sdio;
3390 mmc->ocr_avail_sd = ocr_avail;
3391 if (host->ocr_avail_sd)
3392 mmc->ocr_avail_sd &= host->ocr_avail_sd;
3393 else /* normal SD controllers don't support 1.8V */
3394 mmc->ocr_avail_sd &= ~MMC_VDD_165_195;
3395 mmc->ocr_avail_mmc = ocr_avail;
3396 if (host->ocr_avail_mmc)
3397 mmc->ocr_avail_mmc &= host->ocr_avail_mmc;
146ad66e
PO		 3398
3399 if (mmc->ocr_avail == 0) {
2e4456f0
MV		 3400 pr_err("%s: Hardware doesn't report any support voltages.\n",
3401 mmc_hostname(mmc));
eb5c20de
AH		 3402 ret = -ENODEV;
3403 goto unreg;
146ad66e
PO		 3404 }
3405
8cb851a4
AH		 3406 if ((mmc->caps & (MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 |
3407 MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_SDR104 |
3408 MMC_CAP_UHS_DDR50 | MMC_CAP_1_8V_DDR)) ||
3409 (mmc->caps2 & (MMC_CAP2_HS200_1_8V_SDR | MMC_CAP2_HS400_1_8V)))
3410 host->flags |= SDHCI_SIGNALING_180;
3411
3412 if (mmc->caps2 & MMC_CAP2_HSX00_1_2V)
3413 host->flags |= SDHCI_SIGNALING_120;
3414
d129bceb
PO		 3415 spin_lock_init(&host->lock);
3416
3417 /*
2134a922
PO		 3418 * Maximum number of segments. Depends on if the hardware
3419 * can do scatter/gather or not.
d129bceb 3420 */
2134a922 3421 if (host->flags & SDHCI_USE_ADMA)
4fb213f8 3422 mmc->max_segs = SDHCI_MAX_SEGS;
a13abc7b 3423 else if (host->flags & SDHCI_USE_SDMA)
a36274e0 3424 mmc->max_segs = 1;
2134a922 3425 else /* PIO */
4fb213f8 3426 mmc->max_segs = SDHCI_MAX_SEGS;
d129bceb
PO		 3427
3428 /*
ac00531d
AH		 3429 * Maximum number of sectors in one transfer. Limited by SDMA boundary
3430 * size (512KiB). Note some tuning modes impose a 4MiB limit, but this
3431 * is less anyway.
d129bceb 3432 */
55db890a 3433 mmc->max_req_size = 524288;
d129bceb
PO		 3434
3435 /*
3436 * Maximum segment size. Could be one segment with the maximum number
2134a922
PO		 3437 * of bytes. When doing hardware scatter/gather, each entry cannot
3438 * be larger than 64 KiB though.
d129bceb 3439 */
30652aa3
OJ		 3440 if (host->flags & SDHCI_USE_ADMA) {
3441 if (host->quirks & SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC)
3442 mmc->max_seg_size = 65535;
3443 else
3444 mmc->max_seg_size = 65536;
3445 } else {
2134a922 3446 mmc->max_seg_size = mmc->max_req_size;
30652aa3 3447 }
d129bceb 3448
fe4a3c7a
PO		 3449 /*
3450 * Maximum block size. This varies from controller to controller and
3451 * is specified in the capabilities register.
3452 */
0633f654
AV		 3453 if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) {
3454 mmc->max_blk_size = 2;
3455 } else {
28da3589 3456 mmc->max_blk_size = (host->caps & SDHCI_MAX_BLOCK_MASK) >>
0633f654
AV		 3457 SDHCI_MAX_BLOCK_SHIFT;
3458 if (mmc->max_blk_size >= 3) {
6606110d
JP		 3459 pr_warn("%s: Invalid maximum block size, assuming 512 bytes\n",
3460 mmc_hostname(mmc));
0633f654
AV		 3461 mmc->max_blk_size = 0;
3462 }
3463 }
3464
3465 mmc->max_blk_size = 512 << mmc->max_blk_size;
fe4a3c7a 3466
55db890a
PO		 3467 /*
3468 * Maximum block count.
3469 */
1388eefd 3470 mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
55db890a 3471
52f5336d
AH		 3472 return 0;
3473
3474unreg:
3475 if (!IS_ERR(mmc->supply.vqmmc))
3476 regulator_disable(mmc->supply.vqmmc);
3477undma:
3478 if (host->align_buffer)
3479 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
3480 host->adma_table_sz, host->align_buffer,
3481 host->align_addr);
3482 host->adma_table = NULL;
3483 host->align_buffer = NULL;
3484
3485 return ret;
3486}
3487EXPORT_SYMBOL_GPL(sdhci_setup_host);
3488
3489int __sdhci_add_host(struct sdhci_host *host)
3490{
3491 struct mmc_host *mmc = host->mmc;
3492 int ret;
3493
d129bceb
PO		 3494 /*
3495 * Init tasklets.
3496 */
d129bceb
PO		 3497 tasklet_init(&host->finish_tasklet,
3498 sdhci_tasklet_finish, (unsigned long)host);
3499
e4cad1b5 3500 setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host);
d7422fb4
AH		 3501 setup_timer(&host->data_timer, sdhci_timeout_data_timer,
3502 (unsigned long)host);
d129bceb 3503
250fb7b4 3504 init_waitqueue_head(&host->buf_ready_int);
b513ea25 3505
2af502ca
SG		 3506 sdhci_init(host, 0);
3507
781e989c
RK		 3508 ret = request_threaded_irq(host->irq, sdhci_irq, sdhci_thread_irq,
3509 IRQF_SHARED, mmc_hostname(mmc), host);
0fc81ee3
MB		 3510 if (ret) {
3511 pr_err("%s: Failed to request IRQ %d: %d\n",
3512 mmc_hostname(mmc), host->irq, ret);
8ef1a143 3513 goto untasklet;
0fc81ee3 3514 }
d129bceb 3515
d129bceb
PO		 3516#ifdef CONFIG_MMC_DEBUG
3517 sdhci_dumpregs(host);
3518#endif
3519
061d17a6 3520 ret = sdhci_led_register(host);
0fc81ee3
MB		 3521 if (ret) {
3522 pr_err("%s: Failed to register LED device: %d\n",
3523 mmc_hostname(mmc), ret);
eb5c20de 3524 goto unirq;
0fc81ee3 3525 }
2f730fec 3526
5f25a66f
PO		 3527 mmiowb();
3528
eb5c20de
AH		 3529 ret = mmc_add_host(mmc);
3530 if (ret)
3531 goto unled;
d129bceb 3532
a3c76eb9 3533 pr_info("%s: SDHCI controller on %s [%s] using %s\n",
d1b26863 3534 mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)),
e57a5f61
AH		 3535 (host->flags & SDHCI_USE_ADMA) ?
3536 (host->flags & SDHCI_USE_64_BIT_DMA) ? "ADMA 64-bit" : "ADMA" :
a13abc7b 3537 (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO");
d129bceb 3538
7260cf5e
AV		 3539 sdhci_enable_card_detection(host);
3540
d129bceb
PO		 3541 return 0;
3542
eb5c20de 3543unled:
061d17a6 3544 sdhci_led_unregister(host);
eb5c20de 3545unirq:
03231f9b 3546 sdhci_do_reset(host, SDHCI_RESET_ALL);
b537f94c
RK		 3547 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
3548 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
2f730fec 3549 free_irq(host->irq, host);
8ef1a143 3550untasklet:
d129bceb 3551 tasklet_kill(&host->finish_tasklet);
52f5336d 3552
eb5c20de
AH		 3553 if (!IS_ERR(mmc->supply.vqmmc))
3554 regulator_disable(mmc->supply.vqmmc);
52f5336d 3555
eb5c20de
AH		 3556 if (host->align_buffer)
3557 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
3558 host->adma_table_sz, host->align_buffer,
3559 host->align_addr);
3560 host->adma_table = NULL;
3561 host->align_buffer = NULL;
d129bceb
PO		 3562
3563 return ret;
3564}
52f5336d
AH		 3565EXPORT_SYMBOL_GPL(__sdhci_add_host);
3566
3567int sdhci_add_host(struct sdhci_host *host)
3568{
3569 int ret;
3570
3571 ret = sdhci_setup_host(host);
3572 if (ret)
3573 return ret;
d129bceb 3574
52f5336d
AH		 3575 return __sdhci_add_host(host);
3576}
b8c86fc5 3577EXPORT_SYMBOL_GPL(sdhci_add_host);
d129bceb 3578
1e72859e 3579void sdhci_remove_host(struct sdhci_host *host, int dead)
b8c86fc5 3580{
3a48edc4 3581 struct mmc_host *mmc = host->mmc;
1e72859e
PO		 3582 unsigned long flags;
3583
3584 if (dead) {
3585 spin_lock_irqsave(&host->lock, flags);
3586
3587 host->flags |= SDHCI_DEVICE_DEAD;
3588
5d0d11c5 3589 if (sdhci_has_requests(host)) {
a3c76eb9 3590 pr_err("%s: Controller removed during "
4e743f1f 3591 " transfer!\n", mmc_hostname(mmc));
5d0d11c5 3592 sdhci_error_out_mrqs(host, -ENOMEDIUM);
1e72859e
PO		 3593 }
3594
3595 spin_unlock_irqrestore(&host->lock, flags);
3596 }
3597
7260cf5e
AV		 3598 sdhci_disable_card_detection(host);
3599
4e743f1f 3600 mmc_remove_host(mmc);
d129bceb 3601
061d17a6 3602 sdhci_led_unregister(host);
2f730fec 3603
1e72859e 3604 if (!dead)
03231f9b 3605 sdhci_do_reset(host, SDHCI_RESET_ALL);
d129bceb 3606
b537f94c
RK		 3607 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
3608 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
d129bceb
PO		 3609 free_irq(host->irq, host);
3610
3611 del_timer_sync(&host->timer);
d7422fb4 3612 del_timer_sync(&host->data_timer);
d129bceb 3613
d129bceb 3614 tasklet_kill(&host->finish_tasklet);
2134a922 3615
3a48edc4
TK		 3616 if (!IS_ERR(mmc->supply.vqmmc))
3617 regulator_disable(mmc->supply.vqmmc);
6231f3de 3618
edd63fcc 3619 if (host->align_buffer)
e66e61cb
RK		 3620 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
3621 host->adma_table_sz, host->align_buffer,
3622 host->align_addr);
2134a922 3623
4efaa6fb 3624 host->adma_table = NULL;
2134a922 3625 host->align_buffer = NULL;
d129bceb
PO		 3626}
3627
b8c86fc5 3628EXPORT_SYMBOL_GPL(sdhci_remove_host);
d129bceb 3629
b8c86fc5 3630void sdhci_free_host(struct sdhci_host *host)
d129bceb 3631{
b8c86fc5 3632 mmc_free_host(host->mmc);
d129bceb
PO		 3633}
3634
b8c86fc5 3635EXPORT_SYMBOL_GPL(sdhci_free_host);
d129bceb
PO		 3636
3637/*****************************************************************************\
3638 * *
3639 * Driver init/exit *
3640 * *
3641\*****************************************************************************/
3642
3643static int __init sdhci_drv_init(void)
3644{
a3c76eb9 3645 pr_info(DRIVER_NAME
52fbf9c9 3646 ": Secure Digital Host Controller Interface driver\n");
a3c76eb9 3647 pr_info(DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
d129bceb 3648
b8c86fc5 3649 return 0;
d129bceb
PO		 3650}
3651
3652static void __exit sdhci_drv_exit(void)
3653{
d129bceb
PO		 3654}
3655
3656module_init(sdhci_drv_init);
3657module_exit(sdhci_drv_exit);
3658
df673b22 3659module_param(debug_quirks, uint, 0444);
66fd8ad5 3660module_param(debug_quirks2, uint, 0444);
67435274 3661
32710e8f 3662MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
b8c86fc5 3663MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver");
d129bceb 3664MODULE_LICENSE("GPL");
67435274 3665
df673b22 3666MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");
66fd8ad5 3667MODULE_PARM_DESC(debug_quirks2, "Force certain other quirks.");
Ubuntu Artful kernel mirror