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mmc: sdhci: Clear pointers when a request finishes
[mirror_ubuntu-artful-kernel.git] / drivers / mmc / host / sdhci.c
CommitLineData
d129bceb 1/*
70f10482 2 * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
d129bceb 3 *
b69c9058 4 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
d129bceb
PO		 5 *
6 * This program is free software; you can redistribute it and/or modify
643f720c
PO		 7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or (at
9 * your option) any later version.
84c46a53
PO		 10 *
11 * Thanks to the following companies for their support:
12 *
13 * - JMicron (hardware and technical support)
d129bceb
PO		 14 */
15
d129bceb
PO		 16#include <linux/delay.h>
17#include <linux/highmem.h>
b8c86fc5 18#include <linux/io.h>
88b47679 19#include <linux/module.h>
d129bceb 20#include <linux/dma-mapping.h>
5a0e3ad6 21#include <linux/slab.h>
11763609 22#include <linux/scatterlist.h>
9bea3c85 23#include <linux/regulator/consumer.h>
66fd8ad5 24#include <linux/pm_runtime.h>
d129bceb 25
2f730fec
PO		 26#include <linux/leds.h>
27
22113efd 28#include <linux/mmc/mmc.h>
d129bceb 29#include <linux/mmc/host.h>
473b095a 30#include <linux/mmc/card.h>
85cc1c33 31#include <linux/mmc/sdio.h>
bec9d4e5 32#include <linux/mmc/slot-gpio.h>
d129bceb 33
d129bceb
PO		 34#include "sdhci.h"
35
36#define DRIVER_NAME "sdhci"
d129bceb 37
d129bceb 38#define DBG(f, x...) \
c6563178 39 pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
d129bceb 40
b513ea25
AN		 41#define MAX_TUNING_LOOP 40
42
df673b22 43static unsigned int debug_quirks = 0;
66fd8ad5 44static unsigned int debug_quirks2;
67435274 45
d129bceb
PO		 46static void sdhci_finish_data(struct sdhci_host *);
47
52983382 48static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable);
d129bceb
PO		 49
50static void sdhci_dumpregs(struct sdhci_host *host)
51{
a7c53671
CD		 52 pr_err(DRIVER_NAME ": =========== REGISTER DUMP (%s)===========\n",
53 mmc_hostname(host->mmc));
d129bceb 54
a7c53671
CD		 55 pr_err(DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n",
56 sdhci_readl(host, SDHCI_DMA_ADDRESS),
57 sdhci_readw(host, SDHCI_HOST_VERSION));
58 pr_err(DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n",
59 sdhci_readw(host, SDHCI_BLOCK_SIZE),
60 sdhci_readw(host, SDHCI_BLOCK_COUNT));
61 pr_err(DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
62 sdhci_readl(host, SDHCI_ARGUMENT),
63 sdhci_readw(host, SDHCI_TRANSFER_MODE));
64 pr_err(DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n",
65 sdhci_readl(host, SDHCI_PRESENT_STATE),
66 sdhci_readb(host, SDHCI_HOST_CONTROL));
67 pr_err(DRIVER_NAME ": Power: 0x%08x | Blk gap: 0x%08x\n",
68 sdhci_readb(host, SDHCI_POWER_CONTROL),
69 sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL));
70 pr_err(DRIVER_NAME ": Wake-up: 0x%08x | Clock: 0x%08x\n",
71 sdhci_readb(host, SDHCI_WAKE_UP_CONTROL),
72 sdhci_readw(host, SDHCI_CLOCK_CONTROL));
73 pr_err(DRIVER_NAME ": Timeout: 0x%08x | Int stat: 0x%08x\n",
74 sdhci_readb(host, SDHCI_TIMEOUT_CONTROL),
75 sdhci_readl(host, SDHCI_INT_STATUS));
76 pr_err(DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
77 sdhci_readl(host, SDHCI_INT_ENABLE),
78 sdhci_readl(host, SDHCI_SIGNAL_ENABLE));
79 pr_err(DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
80 sdhci_readw(host, SDHCI_ACMD12_ERR),
81 sdhci_readw(host, SDHCI_SLOT_INT_STATUS));
82 pr_err(DRIVER_NAME ": Caps: 0x%08x | Caps_1: 0x%08x\n",
83 sdhci_readl(host, SDHCI_CAPABILITIES),
84 sdhci_readl(host, SDHCI_CAPABILITIES_1));
85 pr_err(DRIVER_NAME ": Cmd: 0x%08x | Max curr: 0x%08x\n",
86 sdhci_readw(host, SDHCI_COMMAND),
87 sdhci_readl(host, SDHCI_MAX_CURRENT));
88 pr_err(DRIVER_NAME ": Host ctl2: 0x%08x\n",
89 sdhci_readw(host, SDHCI_HOST_CONTROL2));
d129bceb 90
e57a5f61
AH		 91 if (host->flags & SDHCI_USE_ADMA) {
92 if (host->flags & SDHCI_USE_64_BIT_DMA)
a7c53671
CD		 93 pr_err(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x%08x\n",
94 readl(host->ioaddr + SDHCI_ADMA_ERROR),
95 readl(host->ioaddr + SDHCI_ADMA_ADDRESS_HI),
96 readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
e57a5f61 97 else
a7c53671
CD		 98 pr_err(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n",
99 readl(host->ioaddr + SDHCI_ADMA_ERROR),
100 readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
e57a5f61 101 }
be3f4ae0 102
a7c53671 103 pr_err(DRIVER_NAME ": ===========================================\n");
d129bceb
PO		 104}
105
106/*****************************************************************************\
107 * *
108 * Low level functions *
109 * *
110\*****************************************************************************/
111
7260cf5e
AV		 112static void sdhci_set_card_detection(struct sdhci_host *host, bool enable)
113{
5b4f1f6c 114 u32 present;
7260cf5e 115
c79396c1 116 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) ||
860951c5 117 !mmc_card_is_removable(host->mmc))
66fd8ad5
AH		 118 return;
119
5b4f1f6c
RK		 120 if (enable) {
121 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
122 SDHCI_CARD_PRESENT;
d25928d1 123
5b4f1f6c
RK		 124 host->ier |= present ? SDHCI_INT_CARD_REMOVE :
125 SDHCI_INT_CARD_INSERT;
126 } else {
127 host->ier &= ~(SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT);
128 }
b537f94c
RK		 129
130 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
131 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
7260cf5e
AV		 132}
133
134static void sdhci_enable_card_detection(struct sdhci_host *host)
135{
136 sdhci_set_card_detection(host, true);
137}
138
139static void sdhci_disable_card_detection(struct sdhci_host *host)
140{
141 sdhci_set_card_detection(host, false);
142}
143
02d0b685
UH		 144static void sdhci_runtime_pm_bus_on(struct sdhci_host *host)
145{
146 if (host->bus_on)
147 return;
148 host->bus_on = true;
149 pm_runtime_get_noresume(host->mmc->parent);
150}
151
152static void sdhci_runtime_pm_bus_off(struct sdhci_host *host)
153{
154 if (!host->bus_on)
155 return;
156 host->bus_on = false;
157 pm_runtime_put_noidle(host->mmc->parent);
158}
159
03231f9b 160void sdhci_reset(struct sdhci_host *host, u8 mask)
d129bceb 161{
e16514d8 162 unsigned long timeout;
393c1a34 163
4e4141a5 164 sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
d129bceb 165
f0710a55 166 if (mask & SDHCI_RESET_ALL) {
d129bceb 167 host->clock = 0;
f0710a55
AH		 168 /* Reset-all turns off SD Bus Power */
169 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
170 sdhci_runtime_pm_bus_off(host);
171 }
d129bceb 172
e16514d8
PO		 173 /* Wait max 100 ms */
174 timeout = 100;
175
176 /* hw clears the bit when it's done */
4e4141a5 177 while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
e16514d8 178 if (timeout == 0) {
a3c76eb9 179 pr_err("%s: Reset 0x%x never completed.\n",
e16514d8
PO		 180 mmc_hostname(host->mmc), (int)mask);
181 sdhci_dumpregs(host);
182 return;
183 }
184 timeout--;
185 mdelay(1);
d129bceb 186 }
03231f9b
RK		 187}
188EXPORT_SYMBOL_GPL(sdhci_reset);
189
190static void sdhci_do_reset(struct sdhci_host *host, u8 mask)
191{
192 if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
d3940f27
AH		 193 struct mmc_host *mmc = host->mmc;
194
195 if (!mmc->ops->get_cd(mmc))
03231f9b
RK		 196 return;
197 }
063a9dbb 198
03231f9b 199 host->ops->reset(host, mask);
393c1a34 200
da91a8f9
RK		 201 if (mask & SDHCI_RESET_ALL) {
202 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
203 if (host->ops->enable_dma)
204 host->ops->enable_dma(host);
205 }
206
207 /* Resetting the controller clears many */
208 host->preset_enabled = false;
3abc1e80 209 }
d129bceb
PO		 210}
211
2f4cbb3d 212static void sdhci_init(struct sdhci_host *host, int soft)
d129bceb 213{
d3940f27
AH		 214 struct mmc_host *mmc = host->mmc;
215
2f4cbb3d 216 if (soft)
03231f9b 217 sdhci_do_reset(host, SDHCI_RESET_CMD|SDHCI_RESET_DATA);
2f4cbb3d 218 else
03231f9b 219 sdhci_do_reset(host, SDHCI_RESET_ALL);
d129bceb 220
b537f94c
RK		 221 host->ier = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
222 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT |
223 SDHCI_INT_INDEX | SDHCI_INT_END_BIT | SDHCI_INT_CRC |
224 SDHCI_INT_TIMEOUT | SDHCI_INT_DATA_END |
225 SDHCI_INT_RESPONSE;
226
227 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
228 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2f4cbb3d
NP		 229
230 if (soft) {
231 /* force clock reconfiguration */
232 host->clock = 0;
d3940f27 233 mmc->ops->set_ios(mmc, &mmc->ios);
2f4cbb3d 234 }
7260cf5e 235}
d129bceb 236
7260cf5e
AV		 237static void sdhci_reinit(struct sdhci_host *host)
238{
2f4cbb3d 239 sdhci_init(host, 0);
7260cf5e 240 sdhci_enable_card_detection(host);
d129bceb
PO		 241}
242
061d17a6 243static void __sdhci_led_activate(struct sdhci_host *host)
d129bceb
PO		 244{
245 u8 ctrl;
246
4e4141a5 247 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
d129bceb 248 ctrl |= SDHCI_CTRL_LED;
4e4141a5 249 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d129bceb
PO		 250}
251
061d17a6 252static void __sdhci_led_deactivate(struct sdhci_host *host)
d129bceb
PO		 253{
254 u8 ctrl;
255
4e4141a5 256 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
d129bceb 257 ctrl &= ~SDHCI_CTRL_LED;
4e4141a5 258 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d129bceb
PO		 259}
260
4f78230f 261#if IS_REACHABLE(CONFIG_LEDS_CLASS)
2f730fec 262static void sdhci_led_control(struct led_classdev *led,
061d17a6 263 enum led_brightness brightness)
2f730fec
PO		 264{
265 struct sdhci_host *host = container_of(led, struct sdhci_host, led);
266 unsigned long flags;
267
268 spin_lock_irqsave(&host->lock, flags);
269
66fd8ad5
AH		 270 if (host->runtime_suspended)
271 goto out;
272
2f730fec 273 if (brightness == LED_OFF)
061d17a6 274 __sdhci_led_deactivate(host);
2f730fec 275 else
061d17a6 276 __sdhci_led_activate(host);
66fd8ad5 277out:
2f730fec
PO		 278 spin_unlock_irqrestore(&host->lock, flags);
279}
061d17a6
AH		 280
281static int sdhci_led_register(struct sdhci_host *host)
282{
283 struct mmc_host *mmc = host->mmc;
284
285 snprintf(host->led_name, sizeof(host->led_name),
286 "%s::", mmc_hostname(mmc));
287
288 host->led.name = host->led_name;
289 host->led.brightness = LED_OFF;
290 host->led.default_trigger = mmc_hostname(mmc);
291 host->led.brightness_set = sdhci_led_control;
292
293 return led_classdev_register(mmc_dev(mmc), &host->led);
294}
295
296static void sdhci_led_unregister(struct sdhci_host *host)
297{
298 led_classdev_unregister(&host->led);
299}
300
301static inline void sdhci_led_activate(struct sdhci_host *host)
302{
303}
304
305static inline void sdhci_led_deactivate(struct sdhci_host *host)
306{
307}
308
309#else
310
311static inline int sdhci_led_register(struct sdhci_host *host)
312{
313 return 0;
314}
315
316static inline void sdhci_led_unregister(struct sdhci_host *host)
317{
318}
319
320static inline void sdhci_led_activate(struct sdhci_host *host)
321{
322 __sdhci_led_activate(host);
323}
324
325static inline void sdhci_led_deactivate(struct sdhci_host *host)
326{
327 __sdhci_led_deactivate(host);
328}
329
2f730fec
PO		 330#endif
331
d129bceb
PO		 332/*****************************************************************************\
333 * *
334 * Core functions *
335 * *
336\*****************************************************************************/
337
a406f5a3 338static void sdhci_read_block_pio(struct sdhci_host *host)
d129bceb 339{
7659150c
PO		 340 unsigned long flags;
341 size_t blksize, len, chunk;
7244b85b 342 u32 uninitialized_var(scratch);
7659150c 343 u8 *buf;
d129bceb 344
a406f5a3 345 DBG("PIO reading\n");
d129bceb 346
a406f5a3 347 blksize = host->data->blksz;
7659150c 348 chunk = 0;
d129bceb 349
7659150c 350 local_irq_save(flags);
d129bceb 351
a406f5a3 352 while (blksize) {
bf3a35ac 353 BUG_ON(!sg_miter_next(&host->sg_miter));
d129bceb 354
7659150c 355 len = min(host->sg_miter.length, blksize);
d129bceb 356
7659150c
PO		 357 blksize -= len;
358 host->sg_miter.consumed = len;
14d836e7 359
7659150c 360 buf = host->sg_miter.addr;
d129bceb 361
7659150c
PO		 362 while (len) {
363 if (chunk == 0) {
4e4141a5 364 scratch = sdhci_readl(host, SDHCI_BUFFER);
7659150c 365 chunk = 4;
a406f5a3 366 }
7659150c
PO		 367
368 *buf = scratch & 0xFF;
369
370 buf++;
371 scratch >>= 8;
372 chunk--;
373 len--;
d129bceb 374 }
a406f5a3 375 }
7659150c
PO		 376
377 sg_miter_stop(&host->sg_miter);
378
379 local_irq_restore(flags);
a406f5a3 380}
d129bceb 381
a406f5a3
PO		 382static void sdhci_write_block_pio(struct sdhci_host *host)
383{
7659150c
PO		 384 unsigned long flags;
385 size_t blksize, len, chunk;
386 u32 scratch;
387 u8 *buf;
d129bceb 388
a406f5a3
PO		 389 DBG("PIO writing\n");
390
391 blksize = host->data->blksz;
7659150c
PO		 392 chunk = 0;
393 scratch = 0;
d129bceb 394
7659150c 395 local_irq_save(flags);
d129bceb 396
a406f5a3 397 while (blksize) {
bf3a35ac 398 BUG_ON(!sg_miter_next(&host->sg_miter));
a406f5a3 399
7659150c
PO		 400 len = min(host->sg_miter.length, blksize);
401
402 blksize -= len;
403 host->sg_miter.consumed = len;
404
405 buf = host->sg_miter.addr;
d129bceb 406
7659150c
PO		 407 while (len) {
408 scratch |= (u32)*buf << (chunk * 8);
409
410 buf++;
411 chunk++;
412 len--;
413
414 if ((chunk == 4) || ((len == 0) && (blksize == 0))) {
4e4141a5 415 sdhci_writel(host, scratch, SDHCI_BUFFER);
7659150c
PO		 416 chunk = 0;
417 scratch = 0;
d129bceb 418 }
d129bceb
PO		 419 }
420 }
7659150c
PO		 421
422 sg_miter_stop(&host->sg_miter);
423
424 local_irq_restore(flags);
a406f5a3
PO		 425}
426
427static void sdhci_transfer_pio(struct sdhci_host *host)
428{
429 u32 mask;
430
7659150c 431 if (host->blocks == 0)
a406f5a3
PO		 432 return;
433
434 if (host->data->flags & MMC_DATA_READ)
435 mask = SDHCI_DATA_AVAILABLE;
436 else
437 mask = SDHCI_SPACE_AVAILABLE;
438
4a3cba32
PO		 439 /*
440 * Some controllers (JMicron JMB38x) mess up the buffer bits
441 * for transfers < 4 bytes. As long as it is just one block,
442 * we can ignore the bits.
443 */
444 if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) &&
445 (host->data->blocks == 1))
446 mask = ~0;
447
4e4141a5 448 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
3e3bf207
AV		 449 if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY)
450 udelay(100);
451
a406f5a3
PO		 452 if (host->data->flags & MMC_DATA_READ)
453 sdhci_read_block_pio(host);
454 else
455 sdhci_write_block_pio(host);
d129bceb 456
7659150c
PO		 457 host->blocks--;
458 if (host->blocks == 0)
a406f5a3 459 break;
a406f5a3 460 }
d129bceb 461
a406f5a3 462 DBG("PIO transfer complete.\n");
d129bceb
PO		 463}
464
48857d9b 465static int sdhci_pre_dma_transfer(struct sdhci_host *host,
c0999b72 466 struct mmc_data *data, int cookie)
48857d9b
RK		 467{
468 int sg_count;
469
94538e51
RK		 470 /*
471 * If the data buffers are already mapped, return the previous
472 * dma_map_sg() result.
473 */
474 if (data->host_cookie == COOKIE_PRE_MAPPED)
48857d9b 475 return data->sg_count;
48857d9b
RK		 476
477 sg_count = dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
478 data->flags & MMC_DATA_WRITE ?
479 DMA_TO_DEVICE : DMA_FROM_DEVICE);
480
481 if (sg_count == 0)
482 return -ENOSPC;
483
484 data->sg_count = sg_count;
c0999b72 485 data->host_cookie = cookie;
48857d9b
RK		 486
487 return sg_count;
488}
489
2134a922
PO		 490static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags)
491{
492 local_irq_save(*flags);
482fce99 493 return kmap_atomic(sg_page(sg)) + sg->offset;
2134a922
PO		 494}
495
496static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags)
497{
482fce99 498 kunmap_atomic(buffer);
2134a922
PO		 499 local_irq_restore(*flags);
500}
501
e57a5f61
AH		 502static void sdhci_adma_write_desc(struct sdhci_host *host, void *desc,
503 dma_addr_t addr, int len, unsigned cmd)
118cd17d 504{
e57a5f61 505 struct sdhci_adma2_64_desc *dma_desc = desc;
118cd17d 506
e57a5f61 507 /* 32-bit and 64-bit descriptors have these members in same position */
0545230f
AH		 508 dma_desc->cmd = cpu_to_le16(cmd);
509 dma_desc->len = cpu_to_le16(len);
e57a5f61
AH		 510 dma_desc->addr_lo = cpu_to_le32((u32)addr);
511
512 if (host->flags & SDHCI_USE_64_BIT_DMA)
513 dma_desc->addr_hi = cpu_to_le32((u64)addr >> 32);
118cd17d
BD		 514}
515
b5ffa674
AH		 516static void sdhci_adma_mark_end(void *desc)
517{
e57a5f61 518 struct sdhci_adma2_64_desc *dma_desc = desc;
b5ffa674 519
e57a5f61 520 /* 32-bit and 64-bit descriptors have 'cmd' in same position */
0545230f 521 dma_desc->cmd |= cpu_to_le16(ADMA2_END);
b5ffa674
AH		 522}
523
60c64762
RK		 524static void sdhci_adma_table_pre(struct sdhci_host *host,
525 struct mmc_data *data, int sg_count)
2134a922 526{
2134a922 527 struct scatterlist *sg;
2134a922 528 unsigned long flags;
acc3ad13
RK		 529 dma_addr_t addr, align_addr;
530 void *desc, *align;
531 char *buffer;
532 int len, offset, i;
2134a922
PO		 533
534 /*
535 * The spec does not specify endianness of descriptor table.
536 * We currently guess that it is LE.
537 */
538
60c64762 539 host->sg_count = sg_count;
2134a922 540
4efaa6fb 541 desc = host->adma_table;
2134a922
PO		 542 align = host->align_buffer;
543
544 align_addr = host->align_addr;
545
546 for_each_sg(data->sg, sg, host->sg_count, i) {
547 addr = sg_dma_address(sg);
548 len = sg_dma_len(sg);
549
550 /*
acc3ad13
RK		 551 * The SDHCI specification states that ADMA addresses must
552 * be 32-bit aligned. If they aren't, then we use a bounce
553 * buffer for the (up to three) bytes that screw up the
2134a922
PO		 554 * alignment.
555 */
04a5ae6f
AH		 556 offset = (SDHCI_ADMA2_ALIGN - (addr & SDHCI_ADMA2_MASK)) &
557 SDHCI_ADMA2_MASK;
2134a922
PO		 558 if (offset) {
559 if (data->flags & MMC_DATA_WRITE) {
560 buffer = sdhci_kmap_atomic(sg, &flags);
561 memcpy(align, buffer, offset);
562 sdhci_kunmap_atomic(buffer, &flags);
563 }
564
118cd17d 565 /* tran, valid */
e57a5f61 566 sdhci_adma_write_desc(host, desc, align_addr, offset,
739d46dc 567 ADMA2_TRAN_VALID);
2134a922
PO		 568
569 BUG_ON(offset > 65536);
570
04a5ae6f
AH		 571 align += SDHCI_ADMA2_ALIGN;
572 align_addr += SDHCI_ADMA2_ALIGN;
2134a922 573
76fe379a 574 desc += host->desc_sz;
2134a922
PO		 575
576 addr += offset;
577 len -= offset;
578 }
579
2134a922
PO		 580 BUG_ON(len > 65536);
581
347ea32d
AH		 582 if (len) {
583 /* tran, valid */
584 sdhci_adma_write_desc(host, desc, addr, len,
585 ADMA2_TRAN_VALID);
586 desc += host->desc_sz;
587 }
2134a922
PO		 588
589 /*
590 * If this triggers then we have a calculation bug
591 * somewhere. :/
592 */
76fe379a 593 WARN_ON((desc - host->adma_table) >= host->adma_table_sz);
2134a922
PO		 594 }
595
70764a90 596 if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) {
acc3ad13 597 /* Mark the last descriptor as the terminating descriptor */
4efaa6fb 598 if (desc != host->adma_table) {
76fe379a 599 desc -= host->desc_sz;
b5ffa674 600 sdhci_adma_mark_end(desc);
70764a90
TA		 601 }
602 } else {
acc3ad13 603 /* Add a terminating entry - nop, end, valid */
e57a5f61 604 sdhci_adma_write_desc(host, desc, 0, 0, ADMA2_NOP_END_VALID);
70764a90 605 }
2134a922
PO		 606}
607
608static void sdhci_adma_table_post(struct sdhci_host *host,
609 struct mmc_data *data)
610{
2134a922
PO		 611 struct scatterlist *sg;
612 int i, size;
1c3d5f6d 613 void *align;
2134a922
PO		 614 char *buffer;
615 unsigned long flags;
616
47fa9613
RK		 617 if (data->flags & MMC_DATA_READ) {
618 bool has_unaligned = false;
de0b65a7 619
47fa9613
RK		 620 /* Do a quick scan of the SG list for any unaligned mappings */
621 for_each_sg(data->sg, sg, host->sg_count, i)
622 if (sg_dma_address(sg) & SDHCI_ADMA2_MASK) {
623 has_unaligned = true;
624 break;
625 }
2134a922 626
47fa9613
RK		 627 if (has_unaligned) {
628 dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
f55c98f7 629 data->sg_len, DMA_FROM_DEVICE);
2134a922 630
47fa9613 631 align = host->align_buffer;
2134a922 632
47fa9613
RK		 633 for_each_sg(data->sg, sg, host->sg_count, i) {
634 if (sg_dma_address(sg) & SDHCI_ADMA2_MASK) {
635 size = SDHCI_ADMA2_ALIGN -
636 (sg_dma_address(sg) & SDHCI_ADMA2_MASK);
637
638 buffer = sdhci_kmap_atomic(sg, &flags);
639 memcpy(buffer, align, size);
640 sdhci_kunmap_atomic(buffer, &flags);
2134a922 641
47fa9613
RK		 642 align += SDHCI_ADMA2_ALIGN;
643 }
2134a922
PO		 644 }
645 }
646 }
2134a922
PO		 647}
648
a3c7778f 649static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd)
d129bceb 650{
1c8cde92 651 u8 count;
a3c7778f 652 struct mmc_data *data = cmd->data;
1c8cde92 653 unsigned target_timeout, current_timeout;
d129bceb 654
ee53ab5d
PO		 655 /*
656 * If the host controller provides us with an incorrect timeout
657 * value, just skip the check and use 0xE. The hardware may take
658 * longer to time out, but that's much better than having a too-short
659 * timeout value.
660 */
11a2f1b7 661 if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL)
ee53ab5d 662 return 0xE;
e538fbe8 663
a3c7778f 664 /* Unspecified timeout, assume max */
1d4d7744 665 if (!data && !cmd->busy_timeout)
a3c7778f 666 return 0xE;
d129bceb 667
a3c7778f
AW		 668 /* timeout in us */
669 if (!data)
1d4d7744 670 target_timeout = cmd->busy_timeout * 1000;
78a2ca27 671 else {
fafcfda9 672 target_timeout = DIV_ROUND_UP(data->timeout_ns, 1000);
7f05538a
RK		 673 if (host->clock && data->timeout_clks) {
674 unsigned long long val;
675
676 /*
677 * data->timeout_clks is in units of clock cycles.
678 * host->clock is in Hz. target_timeout is in us.
679 * Hence, us = 1000000 * cycles / Hz. Round up.
680 */
681 val = 1000000 * data->timeout_clks;
682 if (do_div(val, host->clock))
683 target_timeout++;
684 target_timeout += val;
685 }
78a2ca27 686 }
81b39802 687
1c8cde92
PO		 688 /*
689 * Figure out needed cycles.
690 * We do this in steps in order to fit inside a 32 bit int.
691 * The first step is the minimum timeout, which will have a
692 * minimum resolution of 6 bits:
693 * (1) 2^13*1000 > 2^22,
694 * (2) host->timeout_clk < 2^16
695 * =>
696 * (1) / (2) > 2^6
697 */
698 count = 0;
699 current_timeout = (1 << 13) * 1000 / host->timeout_clk;
700 while (current_timeout < target_timeout) {
701 count++;
702 current_timeout <<= 1;
703 if (count >= 0xF)
704 break;
705 }
706
707 if (count >= 0xF) {
09eeff52
CB		 708 DBG("%s: Too large timeout 0x%x requested for CMD%d!\n",
709 mmc_hostname(host->mmc), count, cmd->opcode);
1c8cde92
PO		 710 count = 0xE;
711 }
712
ee53ab5d
PO		 713 return count;
714}
715
6aa943ab
AV		 716static void sdhci_set_transfer_irqs(struct sdhci_host *host)
717{
718 u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL;
719 u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR;
720
721 if (host->flags & SDHCI_REQ_USE_DMA)
b537f94c 722 host->ier = (host->ier & ~pio_irqs) | dma_irqs;
6aa943ab 723 else
b537f94c
RK		 724 host->ier = (host->ier & ~dma_irqs) | pio_irqs;
725
726 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
727 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
6aa943ab
AV		 728}
729
b45e668a 730static void sdhci_set_timeout(struct sdhci_host *host, struct mmc_command *cmd)
ee53ab5d
PO		 731{
732 u8 count;
b45e668a
AD		 733
734 if (host->ops->set_timeout) {
735 host->ops->set_timeout(host, cmd);
736 } else {
737 count = sdhci_calc_timeout(host, cmd);
738 sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
739 }
740}
741
742static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd)
743{
2134a922 744 u8 ctrl;
a3c7778f 745 struct mmc_data *data = cmd->data;
ee53ab5d 746
b45e668a
AD		 747 if (data || (cmd->flags & MMC_RSP_BUSY))
748 sdhci_set_timeout(host, cmd);
a3c7778f
AW		 749
750 if (!data)
ee53ab5d
PO		 751 return;
752
43dea098
AH		 753 WARN_ON(host->data);
754
ee53ab5d
PO		 755 /* Sanity checks */
756 BUG_ON(data->blksz * data->blocks > 524288);
757 BUG_ON(data->blksz > host->mmc->max_blk_size);
758 BUG_ON(data->blocks > 65535);
759
760 host->data = data;
761 host->data_early = 0;
f6a03cbf 762 host->data->bytes_xfered = 0;
ee53ab5d 763
fce14421 764 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2134a922 765 struct scatterlist *sg;
df953925 766 unsigned int length_mask, offset_mask;
a0eaf0f9 767 int i;
2134a922 768
fce14421
RK		 769 host->flags |= SDHCI_REQ_USE_DMA;
770
771 /*
772 * FIXME: This doesn't account for merging when mapping the
773 * scatterlist.
774 *
775 * The assumption here being that alignment and lengths are
776 * the same after DMA mapping to device address space.
777 */
a0eaf0f9 778 length_mask = 0;
df953925 779 offset_mask = 0;
2134a922 780 if (host->flags & SDHCI_USE_ADMA) {
df953925 781 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE) {
a0eaf0f9 782 length_mask = 3;
df953925
RK		 783 /*
784 * As we use up to 3 byte chunks to work
785 * around alignment problems, we need to
786 * check the offset as well.
787 */
788 offset_mask = 3;
789 }
2134a922
PO		 790 } else {
791 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE)
a0eaf0f9 792 length_mask = 3;
df953925
RK		 793 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR)
794 offset_mask = 3;
2134a922
PO		 795 }
796
df953925 797 if (unlikely(length_mask | offset_mask)) {
2134a922 798 for_each_sg(data->sg, sg, data->sg_len, i) {
a0eaf0f9 799 if (sg->length & length_mask) {
2e4456f0 800 DBG("Reverting to PIO because of transfer size (%d)\n",
a0eaf0f9 801 sg->length);
2134a922
PO		 802 host->flags &= ~SDHCI_REQ_USE_DMA;
803 break;
804 }
a0eaf0f9 805 if (sg->offset & offset_mask) {
2e4456f0 806 DBG("Reverting to PIO because of bad alignment\n");
2134a922
PO		 807 host->flags &= ~SDHCI_REQ_USE_DMA;
808 break;
809 }
810 }
811 }
812 }
813
8f1934ce 814 if (host->flags & SDHCI_REQ_USE_DMA) {
c0999b72 815 int sg_cnt = sdhci_pre_dma_transfer(host, data, COOKIE_MAPPED);
60c64762
RK		 816
817 if (sg_cnt <= 0) {
818 /*
819 * This only happens when someone fed
820 * us an invalid request.
821 */
822 WARN_ON(1);
823 host->flags &= ~SDHCI_REQ_USE_DMA;
824 } else if (host->flags & SDHCI_USE_ADMA) {
825 sdhci_adma_table_pre(host, data, sg_cnt);
826
827 sdhci_writel(host, host->adma_addr, SDHCI_ADMA_ADDRESS);
828 if (host->flags & SDHCI_USE_64_BIT_DMA)
829 sdhci_writel(host,
830 (u64)host->adma_addr >> 32,
831 SDHCI_ADMA_ADDRESS_HI);
8f1934ce 832 } else {
60c64762
RK		 833 WARN_ON(sg_cnt != 1);
834 sdhci_writel(host, sg_dma_address(data->sg),
835 SDHCI_DMA_ADDRESS);
8f1934ce
PO		 836 }
837 }
838
2134a922
PO		 839 /*
840 * Always adjust the DMA selection as some controllers
841 * (e.g. JMicron) can't do PIO properly when the selection
842 * is ADMA.
843 */
844 if (host->version >= SDHCI_SPEC_200) {
4e4141a5 845 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
2134a922
PO		 846 ctrl &= ~SDHCI_CTRL_DMA_MASK;
847 if ((host->flags & SDHCI_REQ_USE_DMA) &&
e57a5f61
AH		 848 (host->flags & SDHCI_USE_ADMA)) {
849 if (host->flags & SDHCI_USE_64_BIT_DMA)
850 ctrl |= SDHCI_CTRL_ADMA64;
851 else
852 ctrl |= SDHCI_CTRL_ADMA32;
853 } else {
2134a922 854 ctrl |= SDHCI_CTRL_SDMA;
e57a5f61 855 }
4e4141a5 856 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
c9fddbc4
PO		 857 }
858
8f1934ce 859 if (!(host->flags & SDHCI_REQ_USE_DMA)) {
da60a91d
SAS		 860 int flags;
861
862 flags = SG_MITER_ATOMIC;
863 if (host->data->flags & MMC_DATA_READ)
864 flags |= SG_MITER_TO_SG;
865 else
866 flags |= SG_MITER_FROM_SG;
867 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
7659150c 868 host->blocks = data->blocks;
d129bceb 869 }
c7fa9963 870
6aa943ab
AV		 871 sdhci_set_transfer_irqs(host);
872
f6a03cbf
MV		 873 /* Set the DMA boundary value and block size */
874 sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
875 data->blksz), SDHCI_BLOCK_SIZE);
4e4141a5 876 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
c7fa9963
PO		 877}
878
879static void sdhci_set_transfer_mode(struct sdhci_host *host,
e89d456f 880 struct mmc_command *cmd)
c7fa9963 881{
d3fc5d71 882 u16 mode = 0;
e89d456f 883 struct mmc_data *data = cmd->data;
c7fa9963 884
2b558c13 885 if (data == NULL) {
9b8ffea6
VW		 886 if (host->quirks2 &
887 SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD) {
888 sdhci_writew(host, 0x0, SDHCI_TRANSFER_MODE);
889 } else {
2b558c13 890 /* clear Auto CMD settings for no data CMDs */
9b8ffea6
VW		 891 mode = sdhci_readw(host, SDHCI_TRANSFER_MODE);
892 sdhci_writew(host, mode & ~(SDHCI_TRNS_AUTO_CMD12 |
2b558c13 893 SDHCI_TRNS_AUTO_CMD23), SDHCI_TRANSFER_MODE);
9b8ffea6 894 }
c7fa9963 895 return;
2b558c13 896 }
c7fa9963 897
e538fbe8
PO		 898 WARN_ON(!host->data);
899
d3fc5d71
VY		 900 if (!(host->quirks2 & SDHCI_QUIRK2_SUPPORT_SINGLE))
901 mode = SDHCI_TRNS_BLK_CNT_EN;
902
e89d456f 903 if (mmc_op_multi(cmd->opcode) || data->blocks > 1) {
d3fc5d71 904 mode = SDHCI_TRNS_BLK_CNT_EN | SDHCI_TRNS_MULTI;
e89d456f
AW		 905 /*
906 * If we are sending CMD23, CMD12 never gets sent
907 * on successful completion (so no Auto-CMD12).
908 */
a4c73aba 909 if (!cmd->mrq->sbc && (host->flags & SDHCI_AUTO_CMD12) &&
85cc1c33 910 (cmd->opcode != SD_IO_RW_EXTENDED))
e89d456f 911 mode |= SDHCI_TRNS_AUTO_CMD12;
a4c73aba 912 else if (cmd->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) {
8edf6371 913 mode |= SDHCI_TRNS_AUTO_CMD23;
a4c73aba 914 sdhci_writel(host, cmd->mrq->sbc->arg, SDHCI_ARGUMENT2);
8edf6371 915 }
c4512f79 916 }
8edf6371 917
c7fa9963
PO		 918 if (data->flags & MMC_DATA_READ)
919 mode |= SDHCI_TRNS_READ;
c9fddbc4 920 if (host->flags & SDHCI_REQ_USE_DMA)
c7fa9963
PO		 921 mode |= SDHCI_TRNS_DMA;
922
4e4141a5 923 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
d129bceb
PO		 924}
925
0cc563ce
AH		 926static bool sdhci_needs_reset(struct sdhci_host *host, struct mmc_request *mrq)
927{
928 return (!(host->flags & SDHCI_DEVICE_DEAD) &&
929 ((mrq->cmd && mrq->cmd->error) ||
930 (mrq->sbc && mrq->sbc->error) ||
931 (mrq->data && ((mrq->data->error && !mrq->data->stop) ||
932 (mrq->data->stop && mrq->data->stop->error))) ||
933 (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST)));
934}
935
a6d3bdd5
AH		 936static void sdhci_finish_mrq(struct sdhci_host *host, struct mmc_request *mrq)
937{
5a8a3fef
AH		 938 if (host->cmd && host->cmd->mrq == mrq)
939 host->cmd = NULL;
940
941 if (host->data_cmd && host->data_cmd->mrq == mrq)
942 host->data_cmd = NULL;
943
944 if (host->data && host->data->mrq == mrq)
945 host->data = NULL;
946
ed1563de
AH		 947 if (sdhci_needs_reset(host, mrq))
948 host->pending_reset = true;
949
a6d3bdd5
AH		 950 tasklet_schedule(&host->finish_tasklet);
951}
952
d129bceb
PO		 953static void sdhci_finish_data(struct sdhci_host *host)
954{
955 struct mmc_data *data;
d129bceb 956
d129bceb
PO		 957 data = host->data;
958 host->data = NULL;
7c89a3d9 959 host->data_cmd = NULL;
d129bceb 960
add8913d
RK		 961 if ((host->flags & (SDHCI_REQ_USE_DMA | SDHCI_USE_ADMA)) ==
962 (SDHCI_REQ_USE_DMA | SDHCI_USE_ADMA))
963 sdhci_adma_table_post(host, data);
d129bceb
PO		 964
965 /*
c9b74c5b
PO		 966 * The specification states that the block count register must
967 * be updated, but it does not specify at what point in the
968 * data flow. That makes the register entirely useless to read
969 * back so we have to assume that nothing made it to the card
970 * in the event of an error.
d129bceb 971 */
c9b74c5b
PO		 972 if (data->error)
973 data->bytes_xfered = 0;
d129bceb 974 else
c9b74c5b 975 data->bytes_xfered = data->blksz * data->blocks;
d129bceb 976
e89d456f
AW		 977 /*
978 * Need to send CMD12 if -
979 * a) open-ended multiblock transfer (no CMD23)
980 * b) error in multiblock transfer
981 */
982 if (data->stop &&
983 (data->error ||
a4c73aba 984 !data->mrq->sbc)) {
e89d456f 985
d129bceb
PO		 986 /*
987 * The controller needs a reset of internal state machines
988 * upon error conditions.
989 */
17b0429d 990 if (data->error) {
03231f9b
RK		 991 sdhci_do_reset(host, SDHCI_RESET_CMD);
992 sdhci_do_reset(host, SDHCI_RESET_DATA);
d129bceb
PO		 993 }
994
995 sdhci_send_command(host, data->stop);
a6d3bdd5
AH		 996 } else {
997 sdhci_finish_mrq(host, data->mrq);
998 }
d129bceb
PO		 999}
1000
c0e55129 1001void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
d129bceb
PO		 1002{
1003 int flags;
fd2208d7 1004 u32 mask;
7cb2c76f 1005 unsigned long timeout;
d129bceb
PO		 1006
1007 WARN_ON(host->cmd);
1008
96776200
RK		 1009 /* Initially, a command has no error */
1010 cmd->error = 0;
1011
d129bceb 1012 /* Wait max 10 ms */
7cb2c76f 1013 timeout = 10;
fd2208d7
PO		 1014
1015 mask = SDHCI_CMD_INHIBIT;
1016 if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
1017 mask |= SDHCI_DATA_INHIBIT;
1018
1019 /* We shouldn't wait for data inihibit for stop commands, even
1020 though they might use busy signaling */
a4c73aba 1021 if (cmd->mrq->data && (cmd == cmd->mrq->data->stop))
fd2208d7
PO		 1022 mask &= ~SDHCI_DATA_INHIBIT;
1023
4e4141a5 1024 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
7cb2c76f 1025 if (timeout == 0) {
2e4456f0
MV		 1026 pr_err("%s: Controller never released inhibit bit(s).\n",
1027 mmc_hostname(host->mmc));
d129bceb 1028 sdhci_dumpregs(host);
17b0429d 1029 cmd->error = -EIO;
a6d3bdd5 1030 sdhci_finish_mrq(host, cmd->mrq);
d129bceb
PO		 1031 return;
1032 }
7cb2c76f
PO		 1033 timeout--;
1034 mdelay(1);
1035 }
d129bceb 1036
3e1a6892 1037 timeout = jiffies;
1d4d7744
UH		 1038 if (!cmd->data && cmd->busy_timeout > 9000)
1039 timeout += DIV_ROUND_UP(cmd->busy_timeout, 1000) * HZ + HZ;
3e1a6892
AH		 1040 else
1041 timeout += 10 * HZ;
1042 mod_timer(&host->timer, timeout);
d129bceb
PO		 1043
1044 host->cmd = cmd;
7c89a3d9
AH		 1045 if (cmd->data || cmd->flags & MMC_RSP_BUSY) {
1046 WARN_ON(host->data_cmd);
1047 host->data_cmd = cmd;
1048 }
d129bceb 1049
a3c7778f 1050 sdhci_prepare_data(host, cmd);
d129bceb 1051
4e4141a5 1052 sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT);
d129bceb 1053
e89d456f 1054 sdhci_set_transfer_mode(host, cmd);
c7fa9963 1055
d129bceb 1056 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
a3c76eb9 1057 pr_err("%s: Unsupported response type!\n",
d129bceb 1058 mmc_hostname(host->mmc));
17b0429d 1059 cmd->error = -EINVAL;
a6d3bdd5 1060 sdhci_finish_mrq(host, cmd->mrq);
d129bceb
PO		 1061 return;
1062 }
1063
1064 if (!(cmd->flags & MMC_RSP_PRESENT))
1065 flags = SDHCI_CMD_RESP_NONE;
1066 else if (cmd->flags & MMC_RSP_136)
1067 flags = SDHCI_CMD_RESP_LONG;
1068 else if (cmd->flags & MMC_RSP_BUSY)
1069 flags = SDHCI_CMD_RESP_SHORT_BUSY;
1070 else
1071 flags = SDHCI_CMD_RESP_SHORT;
1072
1073 if (cmd->flags & MMC_RSP_CRC)
1074 flags |= SDHCI_CMD_CRC;
1075 if (cmd->flags & MMC_RSP_OPCODE)
1076 flags |= SDHCI_CMD_INDEX;
b513ea25
AN		 1077
1078 /* CMD19 is special in that the Data Present Select should be set */
069c9f14
G		 1079 if (cmd->data || cmd->opcode == MMC_SEND_TUNING_BLOCK ||
1080 cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200)
d129bceb
PO		 1081 flags |= SDHCI_CMD_DATA;
1082
4e4141a5 1083 sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND);
d129bceb 1084}
c0e55129 1085EXPORT_SYMBOL_GPL(sdhci_send_command);
d129bceb
PO		 1086
1087static void sdhci_finish_command(struct sdhci_host *host)
1088{
e0a5640a 1089 struct mmc_command *cmd = host->cmd;
d129bceb
PO		 1090 int i;
1091
e0a5640a
AH		 1092 host->cmd = NULL;
1093
1094 if (cmd->flags & MMC_RSP_PRESENT) {
1095 if (cmd->flags & MMC_RSP_136) {
d129bceb
PO		 1096 /* CRC is stripped so we need to do some shifting. */
1097 for (i = 0;i < 4;i++) {
e0a5640a 1098 cmd->resp[i] = sdhci_readl(host,
d129bceb
PO		 1099 SDHCI_RESPONSE + (3-i)*4) << 8;
1100 if (i != 3)
e0a5640a 1101 cmd->resp[i] |=
4e4141a5 1102 sdhci_readb(host,
d129bceb
PO		 1103 SDHCI_RESPONSE + (3-i)*4-1);
1104 }
1105 } else {
e0a5640a 1106 cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE);
d129bceb
PO		 1107 }
1108 }
1109
6bde8681
AH		 1110 /*
1111 * The host can send and interrupt when the busy state has
1112 * ended, allowing us to wait without wasting CPU cycles.
1113 * The busy signal uses DAT0 so this is similar to waiting
1114 * for data to complete.
1115 *
1116 * Note: The 1.0 specification is a bit ambiguous about this
1117 * feature so there might be some problems with older
1118 * controllers.
1119 */
e0a5640a
AH		 1120 if (cmd->flags & MMC_RSP_BUSY) {
1121 if (cmd->data) {
6bde8681
AH		 1122 DBG("Cannot wait for busy signal when also doing a data transfer");
1123 } else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ) &&
ea968023
AH		 1124 cmd == host->data_cmd) {
1125 /* Command complete before busy is ended */
6bde8681
AH		 1126 return;
1127 }
1128 }
1129
e89d456f 1130 /* Finished CMD23, now send actual command. */
a4c73aba
AH		 1131 if (cmd == cmd->mrq->sbc) {
1132 sdhci_send_command(host, cmd->mrq->cmd);
e89d456f 1133 } else {
e538fbe8 1134
e89d456f
AW		 1135 /* Processed actual command. */
1136 if (host->data && host->data_early)
1137 sdhci_finish_data(host);
d129bceb 1138
e0a5640a 1139 if (!cmd->data)
a6d3bdd5 1140 sdhci_finish_mrq(host, cmd->mrq);
e89d456f 1141 }
d129bceb
PO		 1142}
1143
52983382
KL		 1144static u16 sdhci_get_preset_value(struct sdhci_host *host)
1145{
d975f121 1146 u16 preset = 0;
52983382 1147
d975f121
RK		 1148 switch (host->timing) {
1149 case MMC_TIMING_UHS_SDR12:
52983382
KL		 1150 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1151 break;
d975f121 1152 case MMC_TIMING_UHS_SDR25:
52983382
KL		 1153 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR25);
1154 break;
d975f121 1155 case MMC_TIMING_UHS_SDR50:
52983382
KL		 1156 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR50);
1157 break;
d975f121
RK		 1158 case MMC_TIMING_UHS_SDR104:
1159 case MMC_TIMING_MMC_HS200:
52983382
KL		 1160 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR104);
1161 break;
d975f121 1162 case MMC_TIMING_UHS_DDR50:
0dafa60e 1163 case MMC_TIMING_MMC_DDR52:
52983382
KL		 1164 preset = sdhci_readw(host, SDHCI_PRESET_FOR_DDR50);
1165 break;
e9fb05d5
AH		 1166 case MMC_TIMING_MMC_HS400:
1167 preset = sdhci_readw(host, SDHCI_PRESET_FOR_HS400);
1168 break;
52983382
KL		 1169 default:
1170 pr_warn("%s: Invalid UHS-I mode selected\n",
1171 mmc_hostname(host->mmc));
1172 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1173 break;
1174 }
1175 return preset;
1176}
1177
fb9ee047
LD		 1178u16 sdhci_calc_clk(struct sdhci_host *host, unsigned int clock,
1179 unsigned int *actual_clock)
d129bceb 1180{
c3ed3877 1181 int div = 0; /* Initialized for compiler warning */
df16219f 1182 int real_div = div, clk_mul = 1;
c3ed3877 1183 u16 clk = 0;
5497159c 1184 bool switch_base_clk = false;
d129bceb 1185
85105c53 1186 if (host->version >= SDHCI_SPEC_300) {
da91a8f9 1187 if (host->preset_enabled) {
52983382
KL		 1188 u16 pre_val;
1189
1190 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1191 pre_val = sdhci_get_preset_value(host);
1192 div = (pre_val & SDHCI_PRESET_SDCLK_FREQ_MASK)
1193 >> SDHCI_PRESET_SDCLK_FREQ_SHIFT;
1194 if (host->clk_mul &&
1195 (pre_val & SDHCI_PRESET_CLKGEN_SEL_MASK)) {
1196 clk = SDHCI_PROG_CLOCK_MODE;
1197 real_div = div + 1;
1198 clk_mul = host->clk_mul;
1199 } else {
1200 real_div = max_t(int, 1, div << 1);
1201 }
1202 goto clock_set;
1203 }
1204
c3ed3877
AN		 1205 /*
1206 * Check if the Host Controller supports Programmable Clock
1207 * Mode.
1208 */
1209 if (host->clk_mul) {
52983382
KL		 1210 for (div = 1; div <= 1024; div++) {
1211 if ((host->max_clk * host->clk_mul / div)
1212 <= clock)
1213 break;
1214 }
5497159c 1215 if ((host->max_clk * host->clk_mul / div) <= clock) {
1216 /*
1217 * Set Programmable Clock Mode in the Clock
1218 * Control register.
1219 */
1220 clk = SDHCI_PROG_CLOCK_MODE;
1221 real_div = div;
1222 clk_mul = host->clk_mul;
1223 div--;
1224 } else {
1225 /*
1226 * Divisor can be too small to reach clock
1227 * speed requirement. Then use the base clock.
1228 */
1229 switch_base_clk = true;
1230 }
1231 }
1232
1233 if (!host->clk_mul || switch_base_clk) {
c3ed3877
AN		 1234 /* Version 3.00 divisors must be a multiple of 2. */
1235 if (host->max_clk <= clock)
1236 div = 1;
1237 else {
1238 for (div = 2; div < SDHCI_MAX_DIV_SPEC_300;
1239 div += 2) {
1240 if ((host->max_clk / div) <= clock)
1241 break;
1242 }
85105c53 1243 }
df16219f 1244 real_div = div;
c3ed3877 1245 div >>= 1;
d1955c3a
SG		 1246 if ((host->quirks2 & SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN)
1247 && !div && host->max_clk <= 25000000)
1248 div = 1;
85105c53
ZG		 1249 }
1250 } else {
1251 /* Version 2.00 divisors must be a power of 2. */
0397526d 1252 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
85105c53
ZG		 1253 if ((host->max_clk / div) <= clock)
1254 break;
1255 }
df16219f 1256 real_div = div;
c3ed3877 1257 div >>= 1;
d129bceb 1258 }
d129bceb 1259
52983382 1260clock_set:
03d6f5ff 1261 if (real_div)
fb9ee047 1262 *actual_clock = (host->max_clk * clk_mul) / real_div;
c3ed3877 1263 clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
85105c53
ZG		 1264 clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
1265 << SDHCI_DIVIDER_HI_SHIFT;
fb9ee047
LD		 1266
1267 return clk;
1268}
1269EXPORT_SYMBOL_GPL(sdhci_calc_clk);
1270
1271void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
1272{
1273 u16 clk;
1274 unsigned long timeout;
1275
1276 host->mmc->actual_clock = 0;
1277
1278 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
fb9ee047
LD		 1279
1280 if (clock == 0)
1281 return;
1282
1283 clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock);
1284
d129bceb 1285 clk |= SDHCI_CLOCK_INT_EN;
4e4141a5 1286 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
d129bceb 1287
27f6cb16
CB		 1288 /* Wait max 20 ms */
1289 timeout = 20;
4e4141a5 1290 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
7cb2c76f
PO		 1291 & SDHCI_CLOCK_INT_STABLE)) {
1292 if (timeout == 0) {
2e4456f0
MV		 1293 pr_err("%s: Internal clock never stabilised.\n",
1294 mmc_hostname(host->mmc));
d129bceb
PO		 1295 sdhci_dumpregs(host);
1296 return;
1297 }
7cb2c76f
PO		 1298 timeout--;
1299 mdelay(1);
1300 }
d129bceb
PO		 1301
1302 clk |= SDHCI_CLOCK_CARD_EN;
4e4141a5 1303 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
d129bceb 1304}
1771059c 1305EXPORT_SYMBOL_GPL(sdhci_set_clock);
d129bceb 1306
1dceb041
AH		 1307static void sdhci_set_power_reg(struct sdhci_host *host, unsigned char mode,
1308 unsigned short vdd)
146ad66e 1309{
3a48edc4 1310 struct mmc_host *mmc = host->mmc;
1dceb041
AH		 1311
1312 spin_unlock_irq(&host->lock);
1313 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd);
1314 spin_lock_irq(&host->lock);
1315
1316 if (mode != MMC_POWER_OFF)
1317 sdhci_writeb(host, SDHCI_POWER_ON, SDHCI_POWER_CONTROL);
1318 else
1319 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1320}
1321
1322void sdhci_set_power(struct sdhci_host *host, unsigned char mode,
1323 unsigned short vdd)
1324{
8364248a 1325 u8 pwr = 0;
146ad66e 1326
24fbb3ca
RK		 1327 if (mode != MMC_POWER_OFF) {
1328 switch (1 << vdd) {
ae628903
PO		 1329 case MMC_VDD_165_195:
1330 pwr = SDHCI_POWER_180;
1331 break;
1332 case MMC_VDD_29_30:
1333 case MMC_VDD_30_31:
1334 pwr = SDHCI_POWER_300;
1335 break;
1336 case MMC_VDD_32_33:
1337 case MMC_VDD_33_34:
1338 pwr = SDHCI_POWER_330;
1339 break;
1340 default:
9d5de93f
AH		 1341 WARN(1, "%s: Invalid vdd %#x\n",
1342 mmc_hostname(host->mmc), vdd);
1343 break;
ae628903
PO		 1344 }
1345 }
1346
1347 if (host->pwr == pwr)
e921a8b6 1348 return;
146ad66e 1349
ae628903
PO		 1350 host->pwr = pwr;
1351
1352 if (pwr == 0) {
4e4141a5 1353 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
f0710a55
AH		 1354 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
1355 sdhci_runtime_pm_bus_off(host);
e921a8b6
RK		 1356 } else {
1357 /*
1358 * Spec says that we should clear the power reg before setting
1359 * a new value. Some controllers don't seem to like this though.
1360 */
1361 if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
1362 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
146ad66e 1363
e921a8b6
RK		 1364 /*
1365 * At least the Marvell CaFe chip gets confused if we set the
1366 * voltage and set turn on power at the same time, so set the
1367 * voltage first.
1368 */
1369 if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
1370 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
e08c1694 1371
e921a8b6 1372 pwr |= SDHCI_POWER_ON;
146ad66e 1373
e921a8b6 1374 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
557b0697 1375
e921a8b6
RK		 1376 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
1377 sdhci_runtime_pm_bus_on(host);
f0710a55 1378
e921a8b6
RK		 1379 /*
1380 * Some controllers need an extra 10ms delay of 10ms before
1381 * they can apply clock after applying power
1382 */
1383 if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER)
1384 mdelay(10);
1385 }
1dceb041
AH		 1386}
1387EXPORT_SYMBOL_GPL(sdhci_set_power);
918f4cbd 1388
1dceb041
AH		 1389static void __sdhci_set_power(struct sdhci_host *host, unsigned char mode,
1390 unsigned short vdd)
1391{
1392 struct mmc_host *mmc = host->mmc;
1393
1394 if (host->ops->set_power)
1395 host->ops->set_power(host, mode, vdd);
1396 else if (!IS_ERR(mmc->supply.vmmc))
1397 sdhci_set_power_reg(host, mode, vdd);
1398 else
1399 sdhci_set_power(host, mode, vdd);
146ad66e
PO		 1400}
1401
d129bceb
PO		 1402/*****************************************************************************\
1403 * *
1404 * MMC callbacks *
1405 * *
1406\*****************************************************************************/
1407
1408static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1409{
1410 struct sdhci_host *host;
505a8680 1411 int present;
d129bceb
PO		 1412 unsigned long flags;
1413
1414 host = mmc_priv(mmc);
1415
04e079cf 1416 /* Firstly check card presence */
8d28b7a7 1417 present = mmc->ops->get_cd(mmc);
2836766a 1418
d129bceb
PO		 1419 spin_lock_irqsave(&host->lock, flags);
1420
1421 WARN_ON(host->mrq != NULL);
1422
061d17a6 1423 sdhci_led_activate(host);
e89d456f
AW		 1424
1425 /*
1426 * Ensure we don't send the STOP for non-SET_BLOCK_COUNTED
1427 * requests if Auto-CMD12 is enabled.
1428 */
1429 if (!mrq->sbc && (host->flags & SDHCI_AUTO_CMD12)) {
c4512f79
JH		 1430 if (mrq->stop) {
1431 mrq->data->stop = NULL;
1432 mrq->stop = NULL;
1433 }
1434 }
d129bceb
PO		 1435
1436 host->mrq = mrq;
1437
68d1fb7e 1438 if (!present || host->flags & SDHCI_DEVICE_DEAD) {
a4c73aba 1439 mrq->cmd->error = -ENOMEDIUM;
a6d3bdd5 1440 sdhci_finish_mrq(host, mrq);
cf2b5eea 1441 } else {
8edf6371 1442 if (mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23))
e89d456f
AW		 1443 sdhci_send_command(host, mrq->sbc);
1444 else
1445 sdhci_send_command(host, mrq->cmd);
cf2b5eea 1446 }
d129bceb 1447
5f25a66f 1448 mmiowb();
d129bceb
PO		 1449 spin_unlock_irqrestore(&host->lock, flags);
1450}
1451
2317f56c
RK		 1452void sdhci_set_bus_width(struct sdhci_host *host, int width)
1453{
1454 u8 ctrl;
1455
1456 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1457 if (width == MMC_BUS_WIDTH_8) {
1458 ctrl &= ~SDHCI_CTRL_4BITBUS;
1459 if (host->version >= SDHCI_SPEC_300)
1460 ctrl |= SDHCI_CTRL_8BITBUS;
1461 } else {
1462 if (host->version >= SDHCI_SPEC_300)
1463 ctrl &= ~SDHCI_CTRL_8BITBUS;
1464 if (width == MMC_BUS_WIDTH_4)
1465 ctrl |= SDHCI_CTRL_4BITBUS;
1466 else
1467 ctrl &= ~SDHCI_CTRL_4BITBUS;
1468 }
1469 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1470}
1471EXPORT_SYMBOL_GPL(sdhci_set_bus_width);
1472
96d7b78c
RK		 1473void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing)
1474{
1475 u16 ctrl_2;
1476
1477 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1478 /* Select Bus Speed Mode for host */
1479 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
1480 if ((timing == MMC_TIMING_MMC_HS200) ||
1481 (timing == MMC_TIMING_UHS_SDR104))
1482 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
1483 else if (timing == MMC_TIMING_UHS_SDR12)
1484 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
1485 else if (timing == MMC_TIMING_UHS_SDR25)
1486 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
1487 else if (timing == MMC_TIMING_UHS_SDR50)
1488 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
1489 else if ((timing == MMC_TIMING_UHS_DDR50) ||
1490 (timing == MMC_TIMING_MMC_DDR52))
1491 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
e9fb05d5
AH		 1492 else if (timing == MMC_TIMING_MMC_HS400)
1493 ctrl_2 |= SDHCI_CTRL_HS400; /* Non-standard */
96d7b78c
RK		 1494 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1495}
1496EXPORT_SYMBOL_GPL(sdhci_set_uhs_signaling);
1497
ded97e0b 1498static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
d129bceb 1499{
ded97e0b 1500 struct sdhci_host *host = mmc_priv(mmc);
d129bceb
PO		 1501 unsigned long flags;
1502 u8 ctrl;
1503
d129bceb
PO		 1504 spin_lock_irqsave(&host->lock, flags);
1505
ceb6143b
AH		 1506 if (host->flags & SDHCI_DEVICE_DEAD) {
1507 spin_unlock_irqrestore(&host->lock, flags);
3a48edc4
TK		 1508 if (!IS_ERR(mmc->supply.vmmc) &&
1509 ios->power_mode == MMC_POWER_OFF)
4e743f1f 1510 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
ceb6143b
AH		 1511 return;
1512 }
1e72859e 1513
d129bceb
PO		 1514 /*
1515 * Reset the chip on each power off.
1516 * Should clear out any weird states.
1517 */
1518 if (ios->power_mode == MMC_POWER_OFF) {
4e4141a5 1519 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
7260cf5e 1520 sdhci_reinit(host);
d129bceb
PO		 1521 }
1522
52983382 1523 if (host->version >= SDHCI_SPEC_300 &&
372c4634
DA		 1524 (ios->power_mode == MMC_POWER_UP) &&
1525 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN))
52983382
KL		 1526 sdhci_enable_preset_value(host, false);
1527
373073ef 1528 if (!ios->clock || ios->clock != host->clock) {
1771059c 1529 host->ops->set_clock(host, ios->clock);
373073ef 1530 host->clock = ios->clock;
03d6f5ff
AD		 1531
1532 if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK &&
1533 host->clock) {
1534 host->timeout_clk = host->mmc->actual_clock ?
1535 host->mmc->actual_clock / 1000 :
1536 host->clock / 1000;
1537 host->mmc->max_busy_timeout =
1538 host->ops->get_max_timeout_count ?
1539 host->ops->get_max_timeout_count(host) :
1540 1 << 27;
1541 host->mmc->max_busy_timeout /= host->timeout_clk;
1542 }
373073ef 1543 }
d129bceb 1544
1dceb041 1545 __sdhci_set_power(host, ios->power_mode, ios->vdd);
d129bceb 1546
643a81ff
PR		 1547 if (host->ops->platform_send_init_74_clocks)
1548 host->ops->platform_send_init_74_clocks(host, ios->power_mode);
1549
2317f56c 1550 host->ops->set_bus_width(host, ios->bus_width);
ae6d6c92 1551
15ec4461 1552 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
cd9277c0 1553
3ab9c8da
PR		 1554 if ((ios->timing == MMC_TIMING_SD_HS ||
1555 ios->timing == MMC_TIMING_MMC_HS)
1556 && !(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT))
cd9277c0
PO		 1557 ctrl |= SDHCI_CTRL_HISPD;
1558 else
1559 ctrl &= ~SDHCI_CTRL_HISPD;
1560
d6d50a15 1561 if (host->version >= SDHCI_SPEC_300) {
49c468fc 1562 u16 clk, ctrl_2;
49c468fc
AN		 1563
1564 /* In case of UHS-I modes, set High Speed Enable */
e9fb05d5
AH		 1565 if ((ios->timing == MMC_TIMING_MMC_HS400) ||
1566 (ios->timing == MMC_TIMING_MMC_HS200) ||
bb8175a8 1567 (ios->timing == MMC_TIMING_MMC_DDR52) ||
069c9f14 1568 (ios->timing == MMC_TIMING_UHS_SDR50) ||
49c468fc
AN		 1569 (ios->timing == MMC_TIMING_UHS_SDR104) ||
1570 (ios->timing == MMC_TIMING_UHS_DDR50) ||
dd8df17f 1571 (ios->timing == MMC_TIMING_UHS_SDR25))
49c468fc 1572 ctrl |= SDHCI_CTRL_HISPD;
d6d50a15 1573
da91a8f9 1574 if (!host->preset_enabled) {
758535c4 1575 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d6d50a15
AN		 1576 /*
1577 * We only need to set Driver Strength if the
1578 * preset value enable is not set.
1579 */
da91a8f9 1580 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
d6d50a15
AN		 1581 ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK;
1582 if (ios->drv_type == MMC_SET_DRIVER_TYPE_A)
1583 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A;
43e943a0
PG		 1584 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_B)
1585 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_B;
d6d50a15
AN		 1586 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C)
1587 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C;
43e943a0
PG		 1588 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_D)
1589 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_D;
1590 else {
2e4456f0
MV		 1591 pr_warn("%s: invalid driver type, default to driver type B\n",
1592 mmc_hostname(mmc));
43e943a0
PG		 1593 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_B;
1594 }
d6d50a15
AN		 1595
1596 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
758535c4
AN		 1597 } else {
1598 /*
1599 * According to SDHC Spec v3.00, if the Preset Value
1600 * Enable in the Host Control 2 register is set, we
1601 * need to reset SD Clock Enable before changing High
1602 * Speed Enable to avoid generating clock gliches.
1603 */
758535c4
AN		 1604
1605 /* Reset SD Clock Enable */
1606 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1607 clk &= ~SDHCI_CLOCK_CARD_EN;
1608 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1609
1610 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1611
1612 /* Re-enable SD Clock */
1771059c 1613 host->ops->set_clock(host, host->clock);
d6d50a15 1614 }
49c468fc 1615
49c468fc
AN		 1616 /* Reset SD Clock Enable */
1617 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1618 clk &= ~SDHCI_CLOCK_CARD_EN;
1619 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1620
96d7b78c 1621 host->ops->set_uhs_signaling(host, ios->timing);
d975f121 1622 host->timing = ios->timing;
49c468fc 1623
52983382
KL		 1624 if (!(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN) &&
1625 ((ios->timing == MMC_TIMING_UHS_SDR12) ||
1626 (ios->timing == MMC_TIMING_UHS_SDR25) ||
1627 (ios->timing == MMC_TIMING_UHS_SDR50) ||
1628 (ios->timing == MMC_TIMING_UHS_SDR104) ||
0dafa60e
JZ		 1629 (ios->timing == MMC_TIMING_UHS_DDR50) ||
1630 (ios->timing == MMC_TIMING_MMC_DDR52))) {
52983382
KL		 1631 u16 preset;
1632
1633 sdhci_enable_preset_value(host, true);
1634 preset = sdhci_get_preset_value(host);
1635 ios->drv_type = (preset & SDHCI_PRESET_DRV_MASK)
1636 >> SDHCI_PRESET_DRV_SHIFT;
1637 }
1638
49c468fc 1639 /* Re-enable SD Clock */
1771059c 1640 host->ops->set_clock(host, host->clock);
758535c4
AN		 1641 } else
1642 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d6d50a15 1643
b8352260
LD		 1644 /*
1645 * Some (ENE) controllers go apeshit on some ios operation,
1646 * signalling timeout and CRC errors even on CMD0. Resetting
1647 * it on each ios seems to solve the problem.
1648 */
c63705e1 1649 if (host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
03231f9b 1650 sdhci_do_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
b8352260 1651
5f25a66f 1652 mmiowb();
d129bceb
PO		 1653 spin_unlock_irqrestore(&host->lock, flags);
1654}
1655
ded97e0b 1656static int sdhci_get_cd(struct mmc_host *mmc)
66fd8ad5
AH		 1657{
1658 struct sdhci_host *host = mmc_priv(mmc);
ded97e0b 1659 int gpio_cd = mmc_gpio_get_cd(mmc);
94144a46
KL		 1660
1661 if (host->flags & SDHCI_DEVICE_DEAD)
1662 return 0;
1663
88af5655 1664 /* If nonremovable, assume that the card is always present. */
860951c5 1665 if (!mmc_card_is_removable(host->mmc))
94144a46
KL		 1666 return 1;
1667
88af5655
II		 1668 /*
1669 * Try slot gpio detect, if defined it take precedence
1670 * over build in controller functionality
1671 */
287980e4 1672 if (gpio_cd >= 0)
94144a46
KL		 1673 return !!gpio_cd;
1674
88af5655
II		 1675 /* If polling, assume that the card is always present. */
1676 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
1677 return 1;
1678
94144a46
KL		 1679 /* Host native card detect */
1680 return !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
1681}
1682
66fd8ad5 1683static int sdhci_check_ro(struct sdhci_host *host)
d129bceb 1684{
d129bceb 1685 unsigned long flags;
2dfb579c 1686 int is_readonly;
d129bceb 1687
d129bceb
PO		 1688 spin_lock_irqsave(&host->lock, flags);
1689
1e72859e 1690 if (host->flags & SDHCI_DEVICE_DEAD)
2dfb579c
WS		 1691 is_readonly = 0;
1692 else if (host->ops->get_ro)
1693 is_readonly = host->ops->get_ro(host);
1e72859e 1694 else
2dfb579c
WS		 1695 is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE)
1696 & SDHCI_WRITE_PROTECT);
d129bceb
PO		 1697
1698 spin_unlock_irqrestore(&host->lock, flags);
1699
2dfb579c
WS		 1700 /* This quirk needs to be replaced by a callback-function later */
1701 return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ?
1702 !is_readonly : is_readonly;
d129bceb
PO		 1703}
1704
82b0e23a
TI		 1705#define SAMPLE_COUNT 5
1706
ded97e0b 1707static int sdhci_get_ro(struct mmc_host *mmc)
82b0e23a 1708{
ded97e0b 1709 struct sdhci_host *host = mmc_priv(mmc);
82b0e23a
TI		 1710 int i, ro_count;
1711
82b0e23a 1712 if (!(host->quirks & SDHCI_QUIRK_UNSTABLE_RO_DETECT))
66fd8ad5 1713 return sdhci_check_ro(host);
82b0e23a
TI		 1714
1715 ro_count = 0;
1716 for (i = 0; i < SAMPLE_COUNT; i++) {
66fd8ad5 1717 if (sdhci_check_ro(host)) {
82b0e23a
TI		 1718 if (++ro_count > SAMPLE_COUNT / 2)
1719 return 1;
1720 }
1721 msleep(30);
1722 }
1723 return 0;
1724}
1725
20758b66
AH		 1726static void sdhci_hw_reset(struct mmc_host *mmc)
1727{
1728 struct sdhci_host *host = mmc_priv(mmc);
1729
1730 if (host->ops && host->ops->hw_reset)
1731 host->ops->hw_reset(host);
1732}
1733
66fd8ad5
AH		 1734static void sdhci_enable_sdio_irq_nolock(struct sdhci_host *host, int enable)
1735{
be138554 1736 if (!(host->flags & SDHCI_DEVICE_DEAD)) {
ef104333 1737 if (enable)
b537f94c 1738 host->ier |= SDHCI_INT_CARD_INT;
ef104333 1739 else
b537f94c
RK		 1740 host->ier &= ~SDHCI_INT_CARD_INT;
1741
1742 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
1743 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
ef104333
RK		 1744 mmiowb();
1745 }
66fd8ad5
AH		 1746}
1747
1748static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1749{
1750 struct sdhci_host *host = mmc_priv(mmc);
1751 unsigned long flags;
f75979b7 1752
66fd8ad5 1753 spin_lock_irqsave(&host->lock, flags);
ef104333
RK		 1754 if (enable)
1755 host->flags |= SDHCI_SDIO_IRQ_ENABLED;
1756 else
1757 host->flags &= ~SDHCI_SDIO_IRQ_ENABLED;
1758
66fd8ad5 1759 sdhci_enable_sdio_irq_nolock(host, enable);
f75979b7
PO		 1760 spin_unlock_irqrestore(&host->lock, flags);
1761}
1762
ded97e0b
DA		 1763static int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
1764 struct mmc_ios *ios)
f2119df6 1765{
ded97e0b 1766 struct sdhci_host *host = mmc_priv(mmc);
20b92a30 1767 u16 ctrl;
6231f3de 1768 int ret;
f2119df6 1769
20b92a30
KL		 1770 /*
1771 * Signal Voltage Switching is only applicable for Host Controllers
1772 * v3.00 and above.
1773 */
1774 if (host->version < SDHCI_SPEC_300)
1775 return 0;
6231f3de 1776
f2119df6 1777 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
f2119df6 1778
21f5998f 1779 switch (ios->signal_voltage) {
20b92a30 1780 case MMC_SIGNAL_VOLTAGE_330:
8cb851a4
AH		 1781 if (!(host->flags & SDHCI_SIGNALING_330))
1782 return -EINVAL;
20b92a30
KL		 1783 /* Set 1.8V Signal Enable in the Host Control2 register to 0 */
1784 ctrl &= ~SDHCI_CTRL_VDD_180;
1785 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
f2119df6 1786
3a48edc4
TK		 1787 if (!IS_ERR(mmc->supply.vqmmc)) {
1788 ret = regulator_set_voltage(mmc->supply.vqmmc, 2700000,
1789 3600000);
20b92a30 1790 if (ret) {
6606110d
JP		 1791 pr_warn("%s: Switching to 3.3V signalling voltage failed\n",
1792 mmc_hostname(mmc));
20b92a30
KL		 1793 return -EIO;
1794 }
1795 }
1796 /* Wait for 5ms */
1797 usleep_range(5000, 5500);
f2119df6 1798
20b92a30
KL		 1799 /* 3.3V regulator output should be stable within 5 ms */
1800 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1801 if (!(ctrl & SDHCI_CTRL_VDD_180))
1802 return 0;
6231f3de 1803
6606110d
JP		 1804 pr_warn("%s: 3.3V regulator output did not became stable\n",
1805 mmc_hostname(mmc));
20b92a30
KL		 1806
1807 return -EAGAIN;
1808 case MMC_SIGNAL_VOLTAGE_180:
8cb851a4
AH		 1809 if (!(host->flags & SDHCI_SIGNALING_180))
1810 return -EINVAL;
3a48edc4
TK		 1811 if (!IS_ERR(mmc->supply.vqmmc)) {
1812 ret = regulator_set_voltage(mmc->supply.vqmmc,
20b92a30
KL		 1813 1700000, 1950000);
1814 if (ret) {
6606110d
JP		 1815 pr_warn("%s: Switching to 1.8V signalling voltage failed\n",
1816 mmc_hostname(mmc));
20b92a30
KL		 1817 return -EIO;
1818 }
1819 }
6231f3de 1820
6231f3de
PR		 1821 /*
1822 * Enable 1.8V Signal Enable in the Host Control2
1823 * register
1824 */
20b92a30
KL		 1825 ctrl |= SDHCI_CTRL_VDD_180;
1826 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
6231f3de 1827
9d967a61
VY		 1828 /* Some controller need to do more when switching */
1829 if (host->ops->voltage_switch)
1830 host->ops->voltage_switch(host);
1831
20b92a30
KL		 1832 /* 1.8V regulator output should be stable within 5 ms */
1833 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1834 if (ctrl & SDHCI_CTRL_VDD_180)
1835 return 0;
f2119df6 1836
6606110d
JP		 1837 pr_warn("%s: 1.8V regulator output did not became stable\n",
1838 mmc_hostname(mmc));
f2119df6 1839
20b92a30
KL		 1840 return -EAGAIN;
1841 case MMC_SIGNAL_VOLTAGE_120:
8cb851a4
AH		 1842 if (!(host->flags & SDHCI_SIGNALING_120))
1843 return -EINVAL;
3a48edc4
TK		 1844 if (!IS_ERR(mmc->supply.vqmmc)) {
1845 ret = regulator_set_voltage(mmc->supply.vqmmc, 1100000,
1846 1300000);
20b92a30 1847 if (ret) {
6606110d
JP		 1848 pr_warn("%s: Switching to 1.2V signalling voltage failed\n",
1849 mmc_hostname(mmc));
20b92a30 1850 return -EIO;
f2119df6
AN		 1851 }
1852 }
6231f3de 1853 return 0;
20b92a30 1854 default:
f2119df6
AN		 1855 /* No signal voltage switch required */
1856 return 0;
20b92a30 1857 }
f2119df6
AN		 1858}
1859
20b92a30
KL		 1860static int sdhci_card_busy(struct mmc_host *mmc)
1861{
1862 struct sdhci_host *host = mmc_priv(mmc);
1863 u32 present_state;
1864
e613cc47 1865 /* Check whether DAT[0] is 0 */
20b92a30 1866 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
20b92a30 1867
e613cc47 1868 return !(present_state & SDHCI_DATA_0_LVL_MASK);
20b92a30
KL		 1869}
1870
b5540ce1
AH		 1871static int sdhci_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios)
1872{
1873 struct sdhci_host *host = mmc_priv(mmc);
1874 unsigned long flags;
1875
1876 spin_lock_irqsave(&host->lock, flags);
1877 host->flags |= SDHCI_HS400_TUNING;
1878 spin_unlock_irqrestore(&host->lock, flags);
1879
1880 return 0;
1881}
1882
069c9f14 1883static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode)
b513ea25 1884{
4b6f37d3 1885 struct sdhci_host *host = mmc_priv(mmc);
b513ea25 1886 u16 ctrl;
b513ea25 1887 int tuning_loop_counter = MAX_TUNING_LOOP;
b513ea25 1888 int err = 0;
2b35bd83 1889 unsigned long flags;
38e40bf5 1890 unsigned int tuning_count = 0;
b5540ce1 1891 bool hs400_tuning;
b513ea25 1892
2b35bd83 1893 spin_lock_irqsave(&host->lock, flags);
b513ea25 1894
b5540ce1
AH		 1895 hs400_tuning = host->flags & SDHCI_HS400_TUNING;
1896 host->flags &= ~SDHCI_HS400_TUNING;
1897
38e40bf5
AH		 1898 if (host->tuning_mode == SDHCI_TUNING_MODE_1)
1899 tuning_count = host->tuning_count;
1900
b513ea25 1901 /*
9faac7b9
WY		 1902 * The Host Controller needs tuning in case of SDR104 and DDR50
1903 * mode, and for SDR50 mode when Use Tuning for SDR50 is set in
1904 * the Capabilities register.
069c9f14
G		 1905 * If the Host Controller supports the HS200 mode then the
1906 * tuning function has to be executed.
b513ea25 1907 */
4b6f37d3 1908 switch (host->timing) {
b5540ce1 1909 /* HS400 tuning is done in HS200 mode */
e9fb05d5 1910 case MMC_TIMING_MMC_HS400:
b5540ce1
AH		 1911 err = -EINVAL;
1912 goto out_unlock;
1913
4b6f37d3 1914 case MMC_TIMING_MMC_HS200:
b5540ce1
AH		 1915 /*
1916 * Periodic re-tuning for HS400 is not expected to be needed, so
1917 * disable it here.
1918 */
1919 if (hs400_tuning)
1920 tuning_count = 0;
1921 break;
1922
4b6f37d3 1923 case MMC_TIMING_UHS_SDR104:
9faac7b9 1924 case MMC_TIMING_UHS_DDR50:
4b6f37d3
RK		 1925 break;
1926
1927 case MMC_TIMING_UHS_SDR50:
4228b213 1928 if (host->flags & SDHCI_SDR50_NEEDS_TUNING)
4b6f37d3
RK		 1929 break;
1930 /* FALLTHROUGH */
1931
1932 default:
d519c863 1933 goto out_unlock;
b513ea25
AN		 1934 }
1935
45251812 1936 if (host->ops->platform_execute_tuning) {
2b35bd83 1937 spin_unlock_irqrestore(&host->lock, flags);
45251812 1938 err = host->ops->platform_execute_tuning(host, opcode);
45251812
DA		 1939 return err;
1940 }
1941
4b6f37d3
RK		 1942 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1943 ctrl |= SDHCI_CTRL_EXEC_TUNING;
67d0d04a
VY		 1944 if (host->quirks2 & SDHCI_QUIRK2_TUNING_WORK_AROUND)
1945 ctrl |= SDHCI_CTRL_TUNED_CLK;
b513ea25
AN		 1946 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1947
1948 /*
1949 * As per the Host Controller spec v3.00, tuning command
1950 * generates Buffer Read Ready interrupt, so enable that.
1951 *
1952 * Note: The spec clearly says that when tuning sequence
1953 * is being performed, the controller does not generate
1954 * interrupts other than Buffer Read Ready interrupt. But
1955 * to make sure we don't hit a controller bug, we _only_
1956 * enable Buffer Read Ready interrupt here.
1957 */
b537f94c
RK		 1958 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE);
1959 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE);
b513ea25
AN		 1960
1961 /*
1962 * Issue CMD19 repeatedly till Execute Tuning is set to 0 or the number
1473bdd5 1963 * of loops reaches 40 times.
b513ea25 1964 */
b513ea25
AN		 1965 do {
1966 struct mmc_command cmd = {0};
66fd8ad5 1967 struct mmc_request mrq = {NULL};
b513ea25 1968
069c9f14 1969 cmd.opcode = opcode;
b513ea25
AN		 1970 cmd.arg = 0;
1971 cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
1972 cmd.retries = 0;
1973 cmd.data = NULL;
1974 cmd.error = 0;
1975
7ce45e95
AC		 1976 if (tuning_loop_counter-- == 0)
1977 break;
1978
b513ea25
AN		 1979 mrq.cmd = &cmd;
1980 host->mrq = &mrq;
1981
1982 /*
1983 * In response to CMD19, the card sends 64 bytes of tuning
1984 * block to the Host Controller. So we set the block size
1985 * to 64 here.
1986 */
069c9f14
G		 1987 if (cmd.opcode == MMC_SEND_TUNING_BLOCK_HS200) {
1988 if (mmc->ios.bus_width == MMC_BUS_WIDTH_8)
1989 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 128),
1990 SDHCI_BLOCK_SIZE);
1991 else if (mmc->ios.bus_width == MMC_BUS_WIDTH_4)
1992 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
1993 SDHCI_BLOCK_SIZE);
1994 } else {
1995 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
1996 SDHCI_BLOCK_SIZE);
1997 }
b513ea25
AN		 1998
1999 /*
2000 * The tuning block is sent by the card to the host controller.
2001 * So we set the TRNS_READ bit in the Transfer Mode register.
2002 * This also takes care of setting DMA Enable and Multi Block
2003 * Select in the same register to 0.
2004 */
2005 sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
2006
2007 sdhci_send_command(host, &cmd);
2008
2009 host->cmd = NULL;
2010 host->mrq = NULL;
2011
2b35bd83 2012 spin_unlock_irqrestore(&host->lock, flags);
b513ea25
AN		 2013 /* Wait for Buffer Read Ready interrupt */
2014 wait_event_interruptible_timeout(host->buf_ready_int,
2015 (host->tuning_done == 1),
2016 msecs_to_jiffies(50));
2b35bd83 2017 spin_lock_irqsave(&host->lock, flags);
b513ea25
AN		 2018
2019 if (!host->tuning_done) {
2e4456f0 2020 pr_info(DRIVER_NAME ": Timeout waiting for Buffer Read Ready interrupt during tuning procedure, falling back to fixed sampling clock\n");
b513ea25
AN		 2021 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2022 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
2023 ctrl &= ~SDHCI_CTRL_EXEC_TUNING;
2024 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2025
2026 err = -EIO;
2027 goto out;
2028 }
2029
2030 host->tuning_done = 0;
2031
2032 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
197160d5
NS		 2033
2034 /* eMMC spec does not require a delay between tuning cycles */
2035 if (opcode == MMC_SEND_TUNING_BLOCK)
2036 mdelay(1);
b513ea25
AN		 2037 } while (ctrl & SDHCI_CTRL_EXEC_TUNING);
2038
2039 /*
2040 * The Host Driver has exhausted the maximum number of loops allowed,
2041 * so use fixed sampling frequency.
2042 */
7ce45e95 2043 if (tuning_loop_counter < 0) {
b513ea25
AN		 2044 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
2045 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
7ce45e95
AC		 2046 }
2047 if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) {
2e4456f0 2048 pr_info(DRIVER_NAME ": Tuning procedure failed, falling back to fixed sampling clock\n");
114f2bf6 2049 err = -EIO;
b513ea25
AN		 2050 }
2051
2052out:
38e40bf5 2053 if (tuning_count) {
66c39dfc
AH		 2054 /*
2055 * In case tuning fails, host controllers which support
2056 * re-tuning can try tuning again at a later time, when the
2057 * re-tuning timer expires. So for these controllers, we
2058 * return 0. Since there might be other controllers who do not
2059 * have this capability, we return error for them.
2060 */
2061 err = 0;
cf2b5eea
AN		 2062 }
2063
66c39dfc 2064 host->mmc->retune_period = err ? 0 : tuning_count;
cf2b5eea 2065
b537f94c
RK		 2066 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2067 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
d519c863 2068out_unlock:
2b35bd83 2069 spin_unlock_irqrestore(&host->lock, flags);
b513ea25
AN		 2070 return err;
2071}
2072
cb849648
AH		 2073static int sdhci_select_drive_strength(struct mmc_card *card,
2074 unsigned int max_dtr, int host_drv,
2075 int card_drv, int *drv_type)
2076{
2077 struct sdhci_host *host = mmc_priv(card->host);
2078
2079 if (!host->ops->select_drive_strength)
2080 return 0;
2081
2082 return host->ops->select_drive_strength(host, card, max_dtr, host_drv,
2083 card_drv, drv_type);
2084}
52983382
KL		 2085
2086static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable)
4d55c5a1 2087{
4d55c5a1
AN		 2088 /* Host Controller v3.00 defines preset value registers */
2089 if (host->version < SDHCI_SPEC_300)
2090 return;
2091
4d55c5a1
AN		 2092 /*
2093 * We only enable or disable Preset Value if they are not already
2094 * enabled or disabled respectively. Otherwise, we bail out.
2095 */
da91a8f9
RK		 2096 if (host->preset_enabled != enable) {
2097 u16 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2098
2099 if (enable)
2100 ctrl |= SDHCI_CTRL_PRESET_VAL_ENABLE;
2101 else
2102 ctrl &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
2103
4d55c5a1 2104 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
da91a8f9
RK		 2105
2106 if (enable)
2107 host->flags |= SDHCI_PV_ENABLED;
2108 else
2109 host->flags &= ~SDHCI_PV_ENABLED;
2110
2111 host->preset_enabled = enable;
4d55c5a1 2112 }
66fd8ad5
AH		 2113}
2114
348487cb
HC		 2115static void sdhci_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
2116 int err)
2117{
2118 struct sdhci_host *host = mmc_priv(mmc);
2119 struct mmc_data *data = mrq->data;
2120
f48f039c 2121 if (data->host_cookie != COOKIE_UNMAPPED)
771a3dc2
RK		 2122 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
2123 data->flags & MMC_DATA_WRITE ?
2124 DMA_TO_DEVICE : DMA_FROM_DEVICE);
2125
2126 data->host_cookie = COOKIE_UNMAPPED;
348487cb
HC		 2127}
2128
348487cb
HC		 2129static void sdhci_pre_req(struct mmc_host *mmc, struct mmc_request *mrq,
2130 bool is_first_req)
2131{
2132 struct sdhci_host *host = mmc_priv(mmc);
2133
d31911b9 2134 mrq->data->host_cookie = COOKIE_UNMAPPED;
348487cb
HC		 2135
2136 if (host->flags & SDHCI_REQ_USE_DMA)
94538e51 2137 sdhci_pre_dma_transfer(host, mrq->data, COOKIE_PRE_MAPPED);
348487cb
HC		 2138}
2139
71e69211 2140static void sdhci_card_event(struct mmc_host *mmc)
d129bceb 2141{
71e69211 2142 struct sdhci_host *host = mmc_priv(mmc);
d129bceb 2143 unsigned long flags;
2836766a 2144 int present;
d129bceb 2145
722e1280
CD		 2146 /* First check if client has provided their own card event */
2147 if (host->ops->card_event)
2148 host->ops->card_event(host);
2149
d3940f27 2150 present = mmc->ops->get_cd(mmc);
2836766a 2151
d129bceb
PO		 2152 spin_lock_irqsave(&host->lock, flags);
2153
66fd8ad5 2154 /* Check host->mrq first in case we are runtime suspended */
2836766a 2155 if (host->mrq && !present) {
a3c76eb9 2156 pr_err("%s: Card removed during transfer!\n",
66fd8ad5 2157 mmc_hostname(host->mmc));
a3c76eb9 2158 pr_err("%s: Resetting controller.\n",
66fd8ad5 2159 mmc_hostname(host->mmc));
d129bceb 2160
03231f9b
RK		 2161 sdhci_do_reset(host, SDHCI_RESET_CMD);
2162 sdhci_do_reset(host, SDHCI_RESET_DATA);
d129bceb 2163
66fd8ad5 2164 host->mrq->cmd->error = -ENOMEDIUM;
a6d3bdd5 2165 sdhci_finish_mrq(host, host->mrq);
d129bceb
PO		 2166 }
2167
2168 spin_unlock_irqrestore(&host->lock, flags);
71e69211
GL		 2169}
2170
2171static const struct mmc_host_ops sdhci_ops = {
2172 .request = sdhci_request,
348487cb
HC		 2173 .post_req = sdhci_post_req,
2174 .pre_req = sdhci_pre_req,
71e69211 2175 .set_ios = sdhci_set_ios,
94144a46 2176 .get_cd = sdhci_get_cd,
71e69211
GL		 2177 .get_ro = sdhci_get_ro,
2178 .hw_reset = sdhci_hw_reset,
2179 .enable_sdio_irq = sdhci_enable_sdio_irq,
2180 .start_signal_voltage_switch = sdhci_start_signal_voltage_switch,
b5540ce1 2181 .prepare_hs400_tuning = sdhci_prepare_hs400_tuning,
71e69211 2182 .execute_tuning = sdhci_execute_tuning,
cb849648 2183 .select_drive_strength = sdhci_select_drive_strength,
71e69211 2184 .card_event = sdhci_card_event,
20b92a30 2185 .card_busy = sdhci_card_busy,
71e69211
GL		 2186};
2187
2188/*****************************************************************************\
2189 * *
2190 * Tasklets *
2191 * *
2192\*****************************************************************************/
2193
d129bceb
PO		 2194static void sdhci_tasklet_finish(unsigned long param)
2195{
2196 struct sdhci_host *host;
2197 unsigned long flags;
2198 struct mmc_request *mrq;
2199
2200 host = (struct sdhci_host*)param;
2201
66fd8ad5
AH		 2202 spin_lock_irqsave(&host->lock, flags);
2203
0c9c99a7
CB		 2204 /*
2205 * If this tasklet gets rescheduled while running, it will
2206 * be run again afterwards but without any active request.
2207 */
66fd8ad5
AH		 2208 if (!host->mrq) {
2209 spin_unlock_irqrestore(&host->lock, flags);
0c9c99a7 2210 return;
66fd8ad5 2211 }
d129bceb
PO		 2212
2213 del_timer(&host->timer);
2214
2215 mrq = host->mrq;
2216
054cedff
RK		 2217 /*
2218 * Always unmap the data buffers if they were mapped by
2219 * sdhci_prepare_data() whenever we finish with a request.
2220 * This avoids leaking DMA mappings on error.
2221 */
2222 if (host->flags & SDHCI_REQ_USE_DMA) {
2223 struct mmc_data *data = mrq->data;
2224
2225 if (data && data->host_cookie == COOKIE_MAPPED) {
2226 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
2227 (data->flags & MMC_DATA_READ) ?
2228 DMA_FROM_DEVICE : DMA_TO_DEVICE);
2229 data->host_cookie = COOKIE_UNMAPPED;
2230 }
2231 }
2232
d129bceb
PO		 2233 /*
2234 * The controller needs a reset of internal state machines
2235 * upon error conditions.
2236 */
0cc563ce 2237 if (sdhci_needs_reset(host, mrq)) {
645289dc 2238 /* Some controllers need this kick or reset won't work here */
8213af3b 2239 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)
645289dc 2240 /* This is to force an update */
1771059c 2241 host->ops->set_clock(host, host->clock);
645289dc
PO		 2242
2243 /* Spec says we should do both at the same time, but Ricoh
2244 controllers do not like that. */
03231f9b
RK		 2245 sdhci_do_reset(host, SDHCI_RESET_CMD);
2246 sdhci_do_reset(host, SDHCI_RESET_DATA);
ed1563de
AH		 2247
2248 host->pending_reset = false;
d129bceb
PO		 2249 }
2250
2251 host->mrq = NULL;
d129bceb 2252
061d17a6 2253 sdhci_led_deactivate(host);
d129bceb 2254
5f25a66f 2255 mmiowb();
d129bceb
PO		 2256 spin_unlock_irqrestore(&host->lock, flags);
2257
2258 mmc_request_done(host->mmc, mrq);
2259}
2260
2261static void sdhci_timeout_timer(unsigned long data)
2262{
2263 struct sdhci_host *host;
2264 unsigned long flags;
2265
2266 host = (struct sdhci_host*)data;
2267
2268 spin_lock_irqsave(&host->lock, flags);
2269
2270 if (host->mrq) {
2e4456f0
MV		 2271 pr_err("%s: Timeout waiting for hardware interrupt.\n",
2272 mmc_hostname(host->mmc));
d129bceb
PO		 2273 sdhci_dumpregs(host);
2274
2275 if (host->data) {
17b0429d 2276 host->data->error = -ETIMEDOUT;
d129bceb
PO		 2277 sdhci_finish_data(host);
2278 } else {
2279 if (host->cmd)
17b0429d 2280 host->cmd->error = -ETIMEDOUT;
d129bceb 2281 else
17b0429d 2282 host->mrq->cmd->error = -ETIMEDOUT;
d129bceb 2283
a6d3bdd5 2284 sdhci_finish_mrq(host, host->mrq);
d129bceb
PO		 2285 }
2286 }
2287
5f25a66f 2288 mmiowb();
d129bceb
PO		 2289 spin_unlock_irqrestore(&host->lock, flags);
2290}
2291
2292/*****************************************************************************\
2293 * *
2294 * Interrupt handling *
2295 * *
2296\*****************************************************************************/
2297
61541397 2298static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask, u32 *mask)
d129bceb 2299{
d129bceb 2300 if (!host->cmd) {
ed1563de
AH		 2301 /*
2302 * SDHCI recovers from errors by resetting the cmd and data
2303 * circuits. Until that is done, there very well might be more
2304 * interrupts, so ignore them in that case.
2305 */
2306 if (host->pending_reset)
2307 return;
2e4456f0
MV		 2308 pr_err("%s: Got command interrupt 0x%08x even though no command operation was in progress.\n",
2309 mmc_hostname(host->mmc), (unsigned)intmask);
d129bceb
PO		 2310 sdhci_dumpregs(host);
2311 return;
2312 }
2313
ec014cba
RK		 2314 if (intmask & (SDHCI_INT_TIMEOUT | SDHCI_INT_CRC |
2315 SDHCI_INT_END_BIT | SDHCI_INT_INDEX)) {
2316 if (intmask & SDHCI_INT_TIMEOUT)
2317 host->cmd->error = -ETIMEDOUT;
2318 else
2319 host->cmd->error = -EILSEQ;
43b58b36 2320
71fcbda0
RK		 2321 /*
2322 * If this command initiates a data phase and a response
2323 * CRC error is signalled, the card can start transferring
2324 * data - the card may have received the command without
2325 * error. We must not terminate the mmc_request early.
2326 *
2327 * If the card did not receive the command or returned an
2328 * error which prevented it sending data, the data phase
2329 * will time out.
2330 */
2331 if (host->cmd->data &&
2332 (intmask & (SDHCI_INT_CRC | SDHCI_INT_TIMEOUT)) ==
2333 SDHCI_INT_CRC) {
2334 host->cmd = NULL;
2335 return;
2336 }
2337
a6d3bdd5 2338 sdhci_finish_mrq(host, host->cmd->mrq);
e809517f
PO		 2339 return;
2340 }
2341
6bde8681
AH		 2342 if ((host->quirks2 & SDHCI_QUIRK2_STOP_WITH_TC) &&
2343 !(host->cmd->flags & MMC_RSP_BUSY) && !host->data &&
2344 host->cmd->opcode == MMC_STOP_TRANSMISSION)
61541397 2345 *mask &= ~SDHCI_INT_DATA_END;
e809517f
PO		 2346
2347 if (intmask & SDHCI_INT_RESPONSE)
43b58b36 2348 sdhci_finish_command(host);
d129bceb
PO		 2349}
2350
0957c333 2351#ifdef CONFIG_MMC_DEBUG
08621b18 2352static void sdhci_adma_show_error(struct sdhci_host *host)
6882a8c0
BD		 2353{
2354 const char *name = mmc_hostname(host->mmc);
1c3d5f6d 2355 void *desc = host->adma_table;
6882a8c0
BD		 2356
2357 sdhci_dumpregs(host);
2358
2359 while (true) {
e57a5f61
AH		 2360 struct sdhci_adma2_64_desc *dma_desc = desc;
2361
2362 if (host->flags & SDHCI_USE_64_BIT_DMA)
2363 DBG("%s: %p: DMA 0x%08x%08x, LEN 0x%04x, Attr=0x%02x\n",
2364 name, desc, le32_to_cpu(dma_desc->addr_hi),
2365 le32_to_cpu(dma_desc->addr_lo),
2366 le16_to_cpu(dma_desc->len),
2367 le16_to_cpu(dma_desc->cmd));
2368 else
2369 DBG("%s: %p: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n",
2370 name, desc, le32_to_cpu(dma_desc->addr_lo),
2371 le16_to_cpu(dma_desc->len),
2372 le16_to_cpu(dma_desc->cmd));
6882a8c0 2373
76fe379a 2374 desc += host->desc_sz;
6882a8c0 2375
0545230f 2376 if (dma_desc->cmd & cpu_to_le16(ADMA2_END))
6882a8c0
BD		 2377 break;
2378 }
2379}
2380#else
08621b18 2381static void sdhci_adma_show_error(struct sdhci_host *host) { }
6882a8c0
BD		 2382#endif
2383
d129bceb
PO		 2384static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
2385{
069c9f14 2386 u32 command;
d129bceb 2387
b513ea25
AN		 2388 /* CMD19 generates _only_ Buffer Read Ready interrupt */
2389 if (intmask & SDHCI_INT_DATA_AVAIL) {
069c9f14
G		 2390 command = SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND));
2391 if (command == MMC_SEND_TUNING_BLOCK ||
2392 command == MMC_SEND_TUNING_BLOCK_HS200) {
b513ea25
AN		 2393 host->tuning_done = 1;
2394 wake_up(&host->buf_ready_int);
2395 return;
2396 }
2397 }
2398
d129bceb 2399 if (!host->data) {
7c89a3d9
AH		 2400 struct mmc_command *data_cmd = host->data_cmd;
2401
2402 if (data_cmd)
2403 host->data_cmd = NULL;
2404
d129bceb 2405 /*
e809517f
PO		 2406 * The "data complete" interrupt is also used to
2407 * indicate that a busy state has ended. See comment
2408 * above in sdhci_cmd_irq().
d129bceb 2409 */
7c89a3d9 2410 if (data_cmd && (data_cmd->flags & MMC_RSP_BUSY)) {
c5abd5e8 2411 if (intmask & SDHCI_INT_DATA_TIMEOUT) {
7c89a3d9 2412 data_cmd->error = -ETIMEDOUT;
a6d3bdd5 2413 sdhci_finish_mrq(host, data_cmd->mrq);
c5abd5e8
MC		 2414 return;
2415 }
e809517f 2416 if (intmask & SDHCI_INT_DATA_END) {
e99783a4
CM		 2417 /*
2418 * Some cards handle busy-end interrupt
2419 * before the command completed, so make
2420 * sure we do things in the proper order.
2421 */
ea968023
AH		 2422 if (host->cmd == data_cmd)
2423 return;
2424
a6d3bdd5 2425 sdhci_finish_mrq(host, data_cmd->mrq);
e809517f
PO		 2426 return;
2427 }
2428 }
d129bceb 2429
ed1563de
AH		 2430 /*
2431 * SDHCI recovers from errors by resetting the cmd and data
2432 * circuits. Until that is done, there very well might be more
2433 * interrupts, so ignore them in that case.
2434 */
2435 if (host->pending_reset)
2436 return;
2437
2e4456f0
MV		 2438 pr_err("%s: Got data interrupt 0x%08x even though no data operation was in progress.\n",
2439 mmc_hostname(host->mmc), (unsigned)intmask);
d129bceb
PO		 2440 sdhci_dumpregs(host);
2441
2442 return;
2443 }
2444
2445 if (intmask & SDHCI_INT_DATA_TIMEOUT)
17b0429d 2446 host->data->error = -ETIMEDOUT;
22113efd
AL		 2447 else if (intmask & SDHCI_INT_DATA_END_BIT)
2448 host->data->error = -EILSEQ;
2449 else if ((intmask & SDHCI_INT_DATA_CRC) &&
2450 SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))
2451 != MMC_BUS_TEST_R)
17b0429d 2452 host->data->error = -EILSEQ;
6882a8c0 2453 else if (intmask & SDHCI_INT_ADMA_ERROR) {
a3c76eb9 2454 pr_err("%s: ADMA error\n", mmc_hostname(host->mmc));
08621b18 2455 sdhci_adma_show_error(host);
2134a922 2456 host->data->error = -EIO;
a4071fbb
HZ		 2457 if (host->ops->adma_workaround)
2458 host->ops->adma_workaround(host, intmask);
6882a8c0 2459 }
d129bceb 2460
17b0429d 2461 if (host->data->error)
d129bceb
PO		 2462 sdhci_finish_data(host);
2463 else {
a406f5a3 2464 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
d129bceb
PO		 2465 sdhci_transfer_pio(host);
2466
6ba736a1
PO		 2467 /*
2468 * We currently don't do anything fancy with DMA
2469 * boundaries, but as we can't disable the feature
2470 * we need to at least restart the transfer.
f6a03cbf
MV		 2471 *
2472 * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS)
2473 * should return a valid address to continue from, but as
2474 * some controllers are faulty, don't trust them.
6ba736a1 2475 */
f6a03cbf
MV		 2476 if (intmask & SDHCI_INT_DMA_END) {
2477 u32 dmastart, dmanow;
2478 dmastart = sg_dma_address(host->data->sg);
2479 dmanow = dmastart + host->data->bytes_xfered;
2480 /*
2481 * Force update to the next DMA block boundary.
2482 */
2483 dmanow = (dmanow &
2484 ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) +
2485 SDHCI_DEFAULT_BOUNDARY_SIZE;
2486 host->data->bytes_xfered = dmanow - dmastart;
2487 DBG("%s: DMA base 0x%08x, transferred 0x%06x bytes,"
2488 " next 0x%08x\n",
2489 mmc_hostname(host->mmc), dmastart,
2490 host->data->bytes_xfered, dmanow);
2491 sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS);
2492 }
6ba736a1 2493
e538fbe8 2494 if (intmask & SDHCI_INT_DATA_END) {
7c89a3d9 2495 if (host->cmd == host->data_cmd) {
e538fbe8
PO		 2496 /*
2497 * Data managed to finish before the
2498 * command completed. Make sure we do
2499 * things in the proper order.
2500 */
2501 host->data_early = 1;
2502 } else {
2503 sdhci_finish_data(host);
2504 }
2505 }
d129bceb
PO		 2506 }
2507}
2508
7d12e780 2509static irqreturn_t sdhci_irq(int irq, void *dev_id)
d129bceb 2510{
781e989c 2511 irqreturn_t result = IRQ_NONE;
66fd8ad5 2512 struct sdhci_host *host = dev_id;
41005003 2513 u32 intmask, mask, unexpected = 0;
781e989c 2514 int max_loops = 16;
d129bceb
PO		 2515
2516 spin_lock(&host->lock);
2517
be138554 2518 if (host->runtime_suspended && !sdhci_sdio_irq_enabled(host)) {
66fd8ad5 2519 spin_unlock(&host->lock);
655bca76 2520 return IRQ_NONE;
66fd8ad5
AH		 2521 }
2522
4e4141a5 2523 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
62df67a5 2524 if (!intmask || intmask == 0xffffffff) {
d129bceb
PO		 2525 result = IRQ_NONE;
2526 goto out;
2527 }
2528
41005003
RK		 2529 do {
2530 /* Clear selected interrupts. */
2531 mask = intmask & (SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
2532 SDHCI_INT_BUS_POWER);
2533 sdhci_writel(host, mask, SDHCI_INT_STATUS);
d129bceb 2534
41005003
RK		 2535 DBG("*** %s got interrupt: 0x%08x\n",
2536 mmc_hostname(host->mmc), intmask);
d129bceb 2537
41005003
RK		 2538 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
2539 u32 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
2540 SDHCI_CARD_PRESENT;
d129bceb 2541
41005003
RK		 2542 /*
2543 * There is a observation on i.mx esdhc. INSERT
2544 * bit will be immediately set again when it gets
2545 * cleared, if a card is inserted. We have to mask
2546 * the irq to prevent interrupt storm which will
2547 * freeze the system. And the REMOVE gets the
2548 * same situation.
2549 *
2550 * More testing are needed here to ensure it works
2551 * for other platforms though.
2552 */
b537f94c
RK		 2553 host->ier &= ~(SDHCI_INT_CARD_INSERT |
2554 SDHCI_INT_CARD_REMOVE);
2555 host->ier |= present ? SDHCI_INT_CARD_REMOVE :
2556 SDHCI_INT_CARD_INSERT;
2557 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2558 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
41005003
RK		 2559
2560 sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT |
2561 SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS);
3560db8e
RK		 2562
2563 host->thread_isr |= intmask & (SDHCI_INT_CARD_INSERT |
2564 SDHCI_INT_CARD_REMOVE);
2565 result = IRQ_WAKE_THREAD;
41005003 2566 }
d129bceb 2567
41005003 2568 if (intmask & SDHCI_INT_CMD_MASK)
61541397
AH		 2569 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK,
2570 &intmask);
964f9ce2 2571
41005003
RK		 2572 if (intmask & SDHCI_INT_DATA_MASK)
2573 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
d129bceb 2574
41005003
RK		 2575 if (intmask & SDHCI_INT_BUS_POWER)
2576 pr_err("%s: Card is consuming too much power!\n",
2577 mmc_hostname(host->mmc));
3192a28f 2578
781e989c
RK		 2579 if (intmask & SDHCI_INT_CARD_INT) {
2580 sdhci_enable_sdio_irq_nolock(host, false);
2581 host->thread_isr |= SDHCI_INT_CARD_INT;
2582 result = IRQ_WAKE_THREAD;
2583 }
f75979b7 2584
41005003
RK		 2585 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE |
2586 SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
2587 SDHCI_INT_ERROR | SDHCI_INT_BUS_POWER |
2588 SDHCI_INT_CARD_INT);
f75979b7 2589
41005003
RK		 2590 if (intmask) {
2591 unexpected |= intmask;
2592 sdhci_writel(host, intmask, SDHCI_INT_STATUS);
2593 }
d129bceb 2594
781e989c
RK		 2595 if (result == IRQ_NONE)
2596 result = IRQ_HANDLED;
d129bceb 2597
41005003 2598 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
41005003 2599 } while (intmask && --max_loops);
d129bceb
PO		 2600out:
2601 spin_unlock(&host->lock);
2602
6379b237
AS		 2603 if (unexpected) {
2604 pr_err("%s: Unexpected interrupt 0x%08x.\n",
2605 mmc_hostname(host->mmc), unexpected);
2606 sdhci_dumpregs(host);
2607 }
f75979b7 2608
d129bceb
PO		 2609 return result;
2610}
2611
781e989c
RK		 2612static irqreturn_t sdhci_thread_irq(int irq, void *dev_id)
2613{
2614 struct sdhci_host *host = dev_id;
2615 unsigned long flags;
2616 u32 isr;
2617
2618 spin_lock_irqsave(&host->lock, flags);
2619 isr = host->thread_isr;
2620 host->thread_isr = 0;
2621 spin_unlock_irqrestore(&host->lock, flags);
2622
3560db8e 2623 if (isr & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
d3940f27
AH		 2624 struct mmc_host *mmc = host->mmc;
2625
2626 mmc->ops->card_event(mmc);
2627 mmc_detect_change(mmc, msecs_to_jiffies(200));
3560db8e
RK		 2628 }
2629
781e989c
RK		 2630 if (isr & SDHCI_INT_CARD_INT) {
2631 sdio_run_irqs(host->mmc);
2632
2633 spin_lock_irqsave(&host->lock, flags);
2634 if (host->flags & SDHCI_SDIO_IRQ_ENABLED)
2635 sdhci_enable_sdio_irq_nolock(host, true);
2636 spin_unlock_irqrestore(&host->lock, flags);
2637 }
2638
2639 return isr ? IRQ_HANDLED : IRQ_NONE;
2640}
2641
d129bceb
PO		 2642/*****************************************************************************\
2643 * *
2644 * Suspend/resume *
2645 * *
2646\*****************************************************************************/
2647
2648#ifdef CONFIG_PM
84d62605
LD		 2649/*
2650 * To enable wakeup events, the corresponding events have to be enabled in
2651 * the Interrupt Status Enable register too. See 'Table 1-6: Wakeup Signal
2652 * Table' in the SD Host Controller Standard Specification.
2653 * It is useless to restore SDHCI_INT_ENABLE state in
2654 * sdhci_disable_irq_wakeups() since it will be set by
2655 * sdhci_enable_card_detection() or sdhci_init().
2656 */
ad080d79
KL		 2657void sdhci_enable_irq_wakeups(struct sdhci_host *host)
2658{
2659 u8 val;
2660 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
2661 | SDHCI_WAKE_ON_INT;
84d62605
LD		 2662 u32 irq_val = SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE |
2663 SDHCI_INT_CARD_INT;
ad080d79
KL		 2664
2665 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2666 val |= mask ;
2667 /* Avoid fake wake up */
84d62605 2668 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) {
ad080d79 2669 val &= ~(SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE);
84d62605
LD		 2670 irq_val &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE);
2671 }
ad080d79 2672 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
84d62605 2673 sdhci_writel(host, irq_val, SDHCI_INT_ENABLE);
ad080d79
KL		 2674}
2675EXPORT_SYMBOL_GPL(sdhci_enable_irq_wakeups);
2676
0b10f478 2677static void sdhci_disable_irq_wakeups(struct sdhci_host *host)
ad080d79
KL		 2678{
2679 u8 val;
2680 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
2681 | SDHCI_WAKE_ON_INT;
2682
2683 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2684 val &= ~mask;
2685 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2686}
d129bceb 2687
29495aa0 2688int sdhci_suspend_host(struct sdhci_host *host)
d129bceb 2689{
7260cf5e
AV		 2690 sdhci_disable_card_detection(host);
2691
66c39dfc
AH		 2692 mmc_retune_timer_stop(host->mmc);
2693 mmc_retune_needed(host->mmc);
cf2b5eea 2694
ad080d79 2695 if (!device_may_wakeup(mmc_dev(host->mmc))) {
b537f94c
RK		 2696 host->ier = 0;
2697 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
2698 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
ad080d79
KL		 2699 free_irq(host->irq, host);
2700 } else {
2701 sdhci_enable_irq_wakeups(host);
2702 enable_irq_wake(host->irq);
2703 }
4ee14ec6 2704 return 0;
d129bceb
PO		 2705}
2706
b8c86fc5 2707EXPORT_SYMBOL_GPL(sdhci_suspend_host);
d129bceb 2708
b8c86fc5
PO		 2709int sdhci_resume_host(struct sdhci_host *host)
2710{
d3940f27 2711 struct mmc_host *mmc = host->mmc;
4ee14ec6 2712 int ret = 0;
d129bceb 2713
a13abc7b 2714 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
b8c86fc5
PO		 2715 if (host->ops->enable_dma)
2716 host->ops->enable_dma(host);
2717 }
d129bceb 2718
6308d290
AH		 2719 if ((host->mmc->pm_flags & MMC_PM_KEEP_POWER) &&
2720 (host->quirks2 & SDHCI_QUIRK2_HOST_OFF_CARD_ON)) {
2721 /* Card keeps power but host controller does not */
2722 sdhci_init(host, 0);
2723 host->pwr = 0;
2724 host->clock = 0;
d3940f27 2725 mmc->ops->set_ios(mmc, &mmc->ios);
6308d290
AH		 2726 } else {
2727 sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER));
2728 mmiowb();
2729 }
b8c86fc5 2730
14a7b416
HC		 2731 if (!device_may_wakeup(mmc_dev(host->mmc))) {
2732 ret = request_threaded_irq(host->irq, sdhci_irq,
2733 sdhci_thread_irq, IRQF_SHARED,
2734 mmc_hostname(host->mmc), host);
2735 if (ret)
2736 return ret;
2737 } else {
2738 sdhci_disable_irq_wakeups(host);
2739 disable_irq_wake(host->irq);
2740 }
2741
7260cf5e
AV		 2742 sdhci_enable_card_detection(host);
2743
2f4cbb3d 2744 return ret;
d129bceb
PO		 2745}
2746
b8c86fc5 2747EXPORT_SYMBOL_GPL(sdhci_resume_host);
66fd8ad5 2748
66fd8ad5
AH		 2749int sdhci_runtime_suspend_host(struct sdhci_host *host)
2750{
2751 unsigned long flags;
66fd8ad5 2752
66c39dfc
AH		 2753 mmc_retune_timer_stop(host->mmc);
2754 mmc_retune_needed(host->mmc);
66fd8ad5
AH		 2755
2756 spin_lock_irqsave(&host->lock, flags);
b537f94c
RK		 2757 host->ier &= SDHCI_INT_CARD_INT;
2758 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2759 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
66fd8ad5
AH		 2760 spin_unlock_irqrestore(&host->lock, flags);
2761
781e989c 2762 synchronize_hardirq(host->irq);
66fd8ad5
AH		 2763
2764 spin_lock_irqsave(&host->lock, flags);
2765 host->runtime_suspended = true;
2766 spin_unlock_irqrestore(&host->lock, flags);
2767
8a125bad 2768 return 0;
66fd8ad5
AH		 2769}
2770EXPORT_SYMBOL_GPL(sdhci_runtime_suspend_host);
2771
2772int sdhci_runtime_resume_host(struct sdhci_host *host)
2773{
d3940f27 2774 struct mmc_host *mmc = host->mmc;
66fd8ad5 2775 unsigned long flags;
8a125bad 2776 int host_flags = host->flags;
66fd8ad5
AH		 2777
2778 if (host_flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2779 if (host->ops->enable_dma)
2780 host->ops->enable_dma(host);
2781 }
2782
2783 sdhci_init(host, 0);
2784
2785 /* Force clock and power re-program */
2786 host->pwr = 0;
2787 host->clock = 0;
d3940f27
AH		 2788 mmc->ops->start_signal_voltage_switch(mmc, &mmc->ios);
2789 mmc->ops->set_ios(mmc, &mmc->ios);
66fd8ad5 2790
52983382
KL		 2791 if ((host_flags & SDHCI_PV_ENABLED) &&
2792 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN)) {
2793 spin_lock_irqsave(&host->lock, flags);
2794 sdhci_enable_preset_value(host, true);
2795 spin_unlock_irqrestore(&host->lock, flags);
2796 }
66fd8ad5 2797
66fd8ad5
AH		 2798 spin_lock_irqsave(&host->lock, flags);
2799
2800 host->runtime_suspended = false;
2801
2802 /* Enable SDIO IRQ */
ef104333 2803 if (host->flags & SDHCI_SDIO_IRQ_ENABLED)
66fd8ad5
AH		 2804 sdhci_enable_sdio_irq_nolock(host, true);
2805
2806 /* Enable Card Detection */
2807 sdhci_enable_card_detection(host);
2808
2809 spin_unlock_irqrestore(&host->lock, flags);
2810
8a125bad 2811 return 0;
66fd8ad5
AH		 2812}
2813EXPORT_SYMBOL_GPL(sdhci_runtime_resume_host);
2814
162d6f98 2815#endif /* CONFIG_PM */
66fd8ad5 2816
d129bceb
PO		 2817/*****************************************************************************\
2818 * *
b8c86fc5 2819 * Device allocation/registration *
d129bceb
PO		 2820 * *
2821\*****************************************************************************/
2822
b8c86fc5
PO		 2823struct sdhci_host *sdhci_alloc_host(struct device *dev,
2824 size_t priv_size)
d129bceb 2825{
d129bceb
PO		 2826 struct mmc_host *mmc;
2827 struct sdhci_host *host;
2828
b8c86fc5 2829 WARN_ON(dev == NULL);
d129bceb 2830
b8c86fc5 2831 mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev);
d129bceb 2832 if (!mmc)
b8c86fc5 2833 return ERR_PTR(-ENOMEM);
d129bceb
PO		 2834
2835 host = mmc_priv(mmc);
2836 host->mmc = mmc;
bf60e592
AH		 2837 host->mmc_host_ops = sdhci_ops;
2838 mmc->ops = &host->mmc_host_ops;
d129bceb 2839
8cb851a4
AH		 2840 host->flags = SDHCI_SIGNALING_330;
2841
b8c86fc5
PO		 2842 return host;
2843}
8a4da143 2844
b8c86fc5 2845EXPORT_SYMBOL_GPL(sdhci_alloc_host);
d129bceb 2846
7b91369b
AC		 2847static int sdhci_set_dma_mask(struct sdhci_host *host)
2848{
2849 struct mmc_host *mmc = host->mmc;
2850 struct device *dev = mmc_dev(mmc);
2851 int ret = -EINVAL;
2852
2853 if (host->quirks2 & SDHCI_QUIRK2_BROKEN_64_BIT_DMA)
2854 host->flags &= ~SDHCI_USE_64_BIT_DMA;
2855
2856 /* Try 64-bit mask if hardware is capable of it */
2857 if (host->flags & SDHCI_USE_64_BIT_DMA) {
2858 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64));
2859 if (ret) {
2860 pr_warn("%s: Failed to set 64-bit DMA mask.\n",
2861 mmc_hostname(mmc));
2862 host->flags &= ~SDHCI_USE_64_BIT_DMA;
2863 }
2864 }
2865
2866 /* 32-bit mask as default & fallback */
2867 if (ret) {
2868 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32));
2869 if (ret)
2870 pr_warn("%s: Failed to set 32-bit DMA mask.\n",
2871 mmc_hostname(mmc));
2872 }
2873
2874 return ret;
2875}
2876
6132a3bf
AH		 2877void __sdhci_read_caps(struct sdhci_host *host, u16 *ver, u32 *caps, u32 *caps1)
2878{
2879 u16 v;
2880
2881 if (host->read_caps)
2882 return;
2883
2884 host->read_caps = true;
2885
2886 if (debug_quirks)
2887 host->quirks = debug_quirks;
2888
2889 if (debug_quirks2)
2890 host->quirks2 = debug_quirks2;
2891
2892 sdhci_do_reset(host, SDHCI_RESET_ALL);
2893
2894 v = ver ? *ver : sdhci_readw(host, SDHCI_HOST_VERSION);
2895 host->version = (v & SDHCI_SPEC_VER_MASK) >> SDHCI_SPEC_VER_SHIFT;
2896
2897 if (host->quirks & SDHCI_QUIRK_MISSING_CAPS)
2898 return;
2899
2900 host->caps = caps ? *caps : sdhci_readl(host, SDHCI_CAPABILITIES);
2901
2902 if (host->version < SDHCI_SPEC_300)
2903 return;
2904
2905 host->caps1 = caps1 ? *caps1 : sdhci_readl(host, SDHCI_CAPABILITIES_1);
2906}
2907EXPORT_SYMBOL_GPL(__sdhci_read_caps);
2908
52f5336d 2909int sdhci_setup_host(struct sdhci_host *host)
b8c86fc5
PO		 2910{
2911 struct mmc_host *mmc;
f2119df6
AN		 2912 u32 max_current_caps;
2913 unsigned int ocr_avail;
f5fa92e5 2914 unsigned int override_timeout_clk;
59241757 2915 u32 max_clk;
b8c86fc5 2916 int ret;
d129bceb 2917
b8c86fc5
PO		 2918 WARN_ON(host == NULL);
2919 if (host == NULL)
2920 return -EINVAL;
d129bceb 2921
b8c86fc5 2922 mmc = host->mmc;
d129bceb 2923
6132a3bf 2924 sdhci_read_caps(host);
d129bceb 2925
f5fa92e5
AH		 2926 override_timeout_clk = host->timeout_clk;
2927
85105c53 2928 if (host->version > SDHCI_SPEC_300) {
2e4456f0
MV		 2929 pr_err("%s: Unknown controller version (%d). You may experience problems.\n",
2930 mmc_hostname(mmc), host->version);
4a965505
PO		 2931 }
2932
b8c86fc5 2933 if (host->quirks & SDHCI_QUIRK_FORCE_DMA)
a13abc7b 2934 host->flags |= SDHCI_USE_SDMA;
28da3589 2935 else if (!(host->caps & SDHCI_CAN_DO_SDMA))
a13abc7b 2936 DBG("Controller doesn't have SDMA capability\n");
67435274 2937 else
a13abc7b 2938 host->flags |= SDHCI_USE_SDMA;
d129bceb 2939
b8c86fc5 2940 if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
a13abc7b 2941 (host->flags & SDHCI_USE_SDMA)) {
cee687ce 2942 DBG("Disabling DMA as it is marked broken\n");
a13abc7b 2943 host->flags &= ~SDHCI_USE_SDMA;
7c168e3d
FT		 2944 }
2945
f2119df6 2946 if ((host->version >= SDHCI_SPEC_200) &&
28da3589 2947 (host->caps & SDHCI_CAN_DO_ADMA2))
a13abc7b 2948 host->flags |= SDHCI_USE_ADMA;
2134a922
PO		 2949
2950 if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) &&
2951 (host->flags & SDHCI_USE_ADMA)) {
2952 DBG("Disabling ADMA as it is marked broken\n");
2953 host->flags &= ~SDHCI_USE_ADMA;
2954 }
2955
e57a5f61
AH		 2956 /*
2957 * It is assumed that a 64-bit capable device has set a 64-bit DMA mask
2958 * and *must* do 64-bit DMA. A driver has the opportunity to change
2959 * that during the first call to ->enable_dma(). Similarly
2960 * SDHCI_QUIRK2_BROKEN_64_BIT_DMA must be left to the drivers to
2961 * implement.
2962 */
28da3589 2963 if (host->caps & SDHCI_CAN_64BIT)
e57a5f61
AH		 2964 host->flags |= SDHCI_USE_64_BIT_DMA;
2965
a13abc7b 2966 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
7b91369b
AC		 2967 ret = sdhci_set_dma_mask(host);
2968
2969 if (!ret && host->ops->enable_dma)
2970 ret = host->ops->enable_dma(host);
2971
2972 if (ret) {
2973 pr_warn("%s: No suitable DMA available - falling back to PIO\n",
2974 mmc_hostname(mmc));
2975 host->flags &= ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
2976
2977 ret = 0;
d129bceb
PO		 2978 }
2979 }
2980
e57a5f61
AH		 2981 /* SDMA does not support 64-bit DMA */
2982 if (host->flags & SDHCI_USE_64_BIT_DMA)
2983 host->flags &= ~SDHCI_USE_SDMA;
2984
2134a922 2985 if (host->flags & SDHCI_USE_ADMA) {
e66e61cb
RK		 2986 dma_addr_t dma;
2987 void *buf;
2988
2134a922 2989 /*
76fe379a
AH		 2990 * The DMA descriptor table size is calculated as the maximum
2991 * number of segments times 2, to allow for an alignment
2992 * descriptor for each segment, plus 1 for a nop end descriptor,
2993 * all multipled by the descriptor size.
2134a922 2994 */
e57a5f61
AH		 2995 if (host->flags & SDHCI_USE_64_BIT_DMA) {
2996 host->adma_table_sz = (SDHCI_MAX_SEGS * 2 + 1) *
2997 SDHCI_ADMA2_64_DESC_SZ;
e57a5f61 2998 host->desc_sz = SDHCI_ADMA2_64_DESC_SZ;
e57a5f61
AH		 2999 } else {
3000 host->adma_table_sz = (SDHCI_MAX_SEGS * 2 + 1) *
3001 SDHCI_ADMA2_32_DESC_SZ;
e57a5f61 3002 host->desc_sz = SDHCI_ADMA2_32_DESC_SZ;
e57a5f61 3003 }
e66e61cb 3004
04a5ae6f 3005 host->align_buffer_sz = SDHCI_MAX_SEGS * SDHCI_ADMA2_ALIGN;
e66e61cb
RK		 3006 buf = dma_alloc_coherent(mmc_dev(mmc), host->align_buffer_sz +
3007 host->adma_table_sz, &dma, GFP_KERNEL);
3008 if (!buf) {
6606110d 3009 pr_warn("%s: Unable to allocate ADMA buffers - falling back to standard DMA\n",
2134a922
PO		 3010 mmc_hostname(mmc));
3011 host->flags &= ~SDHCI_USE_ADMA;
e66e61cb
RK		 3012 } else if ((dma + host->align_buffer_sz) &
3013 (SDHCI_ADMA2_DESC_ALIGN - 1)) {
6606110d
JP		 3014 pr_warn("%s: unable to allocate aligned ADMA descriptor\n",
3015 mmc_hostname(mmc));
d1e49f77 3016 host->flags &= ~SDHCI_USE_ADMA;
e66e61cb
RK		 3017 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
3018 host->adma_table_sz, buf, dma);
3019 } else {
3020 host->align_buffer = buf;
3021 host->align_addr = dma;
edd63fcc 3022
e66e61cb
RK		 3023 host->adma_table = buf + host->align_buffer_sz;
3024 host->adma_addr = dma + host->align_buffer_sz;
3025 }
2134a922
PO		 3026 }
3027
7659150c
PO		 3028 /*
3029 * If we use DMA, then it's up to the caller to set the DMA
3030 * mask, but PIO does not need the hw shim so we set a new
3031 * mask here in that case.
3032 */
a13abc7b 3033 if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) {
7659150c 3034 host->dma_mask = DMA_BIT_MASK(64);
4e743f1f 3035 mmc_dev(mmc)->dma_mask = &host->dma_mask;
7659150c 3036 }
d129bceb 3037
c4687d5f 3038 if (host->version >= SDHCI_SPEC_300)
28da3589 3039 host->max_clk = (host->caps & SDHCI_CLOCK_V3_BASE_MASK)
c4687d5f
ZG		 3040 >> SDHCI_CLOCK_BASE_SHIFT;
3041 else
28da3589 3042 host->max_clk = (host->caps & SDHCI_CLOCK_BASE_MASK)
c4687d5f
ZG		 3043 >> SDHCI_CLOCK_BASE_SHIFT;
3044
4240ff0a 3045 host->max_clk *= 1000000;
f27f47ef
AV		 3046 if (host->max_clk == 0 || host->quirks &
3047 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) {
4240ff0a 3048 if (!host->ops->get_max_clock) {
2e4456f0
MV		 3049 pr_err("%s: Hardware doesn't specify base clock frequency.\n",
3050 mmc_hostname(mmc));
eb5c20de
AH		 3051 ret = -ENODEV;
3052 goto undma;
4240ff0a
BD		 3053 }
3054 host->max_clk = host->ops->get_max_clock(host);
8ef1a143 3055 }
d129bceb 3056
c3ed3877
AN		 3057 /*
3058 * In case of Host Controller v3.00, find out whether clock
3059 * multiplier is supported.
3060 */
28da3589 3061 host->clk_mul = (host->caps1 & SDHCI_CLOCK_MUL_MASK) >>
c3ed3877
AN		 3062 SDHCI_CLOCK_MUL_SHIFT;
3063
3064 /*
3065 * In case the value in Clock Multiplier is 0, then programmable
3066 * clock mode is not supported, otherwise the actual clock
3067 * multiplier is one more than the value of Clock Multiplier
3068 * in the Capabilities Register.
3069 */
3070 if (host->clk_mul)
3071 host->clk_mul += 1;
3072
d129bceb
PO		 3073 /*
3074 * Set host parameters.
3075 */
59241757
DA		 3076 max_clk = host->max_clk;
3077
ce5f036b 3078 if (host->ops->get_min_clock)
a9e58f25 3079 mmc->f_min = host->ops->get_min_clock(host);
c3ed3877
AN		 3080 else if (host->version >= SDHCI_SPEC_300) {
3081 if (host->clk_mul) {
3082 mmc->f_min = (host->max_clk * host->clk_mul) / 1024;
59241757 3083 max_clk = host->max_clk * host->clk_mul;
c3ed3877
AN		 3084 } else
3085 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300;
3086 } else
0397526d 3087 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200;
15ec4461 3088
d310ae49 3089 if (!mmc->f_max || mmc->f_max > max_clk)
59241757
DA		 3090 mmc->f_max = max_clk;
3091
28aab053 3092 if (!(host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) {
28da3589 3093 host->timeout_clk = (host->caps & SDHCI_TIMEOUT_CLK_MASK) >>
28aab053
AD		 3094 SDHCI_TIMEOUT_CLK_SHIFT;
3095 if (host->timeout_clk == 0) {
3096 if (host->ops->get_timeout_clock) {
3097 host->timeout_clk =
3098 host->ops->get_timeout_clock(host);
3099 } else {
3100 pr_err("%s: Hardware doesn't specify timeout clock frequency.\n",
3101 mmc_hostname(mmc));
eb5c20de
AH		 3102 ret = -ENODEV;
3103 goto undma;
28aab053 3104 }
272308ca 3105 }
272308ca 3106
28da3589 3107 if (host->caps & SDHCI_TIMEOUT_CLK_UNIT)
28aab053 3108 host->timeout_clk *= 1000;
272308ca 3109
99513624
AH		 3110 if (override_timeout_clk)
3111 host->timeout_clk = override_timeout_clk;
3112
28aab053 3113 mmc->max_busy_timeout = host->ops->get_max_timeout_count ?
a6ff5aeb 3114 host->ops->get_max_timeout_count(host) : 1 << 27;
28aab053
AD		 3115 mmc->max_busy_timeout /= host->timeout_clk;
3116 }
58d1246d 3117
e89d456f 3118 mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_ERASE | MMC_CAP_CMD23;
781e989c 3119 mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD;
e89d456f
AW		 3120
3121 if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12)
3122 host->flags |= SDHCI_AUTO_CMD12;
5fe23c7f 3123
8edf6371 3124 /* Auto-CMD23 stuff only works in ADMA or PIO. */
4f3d3e9b 3125 if ((host->version >= SDHCI_SPEC_300) &&
8edf6371 3126 ((host->flags & SDHCI_USE_ADMA) ||
3bfa6f03
SB		 3127 !(host->flags & SDHCI_USE_SDMA)) &&
3128 !(host->quirks2 & SDHCI_QUIRK2_ACMD23_BROKEN)) {
8edf6371
AW		 3129 host->flags |= SDHCI_AUTO_CMD23;
3130 DBG("%s: Auto-CMD23 available\n", mmc_hostname(mmc));
3131 } else {
3132 DBG("%s: Auto-CMD23 unavailable\n", mmc_hostname(mmc));
3133 }
3134
15ec4461
PR		 3135 /*
3136 * A controller may support 8-bit width, but the board itself
3137 * might not have the pins brought out. Boards that support
3138 * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in
3139 * their platform code before calling sdhci_add_host(), and we
3140 * won't assume 8-bit width for hosts without that CAP.
3141 */
5fe23c7f 3142 if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA))
15ec4461 3143 mmc->caps |= MMC_CAP_4_BIT_DATA;
d129bceb 3144
63ef5d8c
JH		 3145 if (host->quirks2 & SDHCI_QUIRK2_HOST_NO_CMD23)
3146 mmc->caps &= ~MMC_CAP_CMD23;
3147
28da3589 3148 if (host->caps & SDHCI_CAN_DO_HISPD)
a29e7e18 3149 mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
cd9277c0 3150
176d1ed4 3151 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) &&
860951c5 3152 mmc_card_is_removable(mmc) &&
287980e4 3153 mmc_gpio_get_cd(host->mmc) < 0)
68d1fb7e
AV		 3154 mmc->caps |= MMC_CAP_NEEDS_POLL;
3155
3a48edc4 3156 /* If there are external regulators, get them */
eb5c20de
AH		 3157 ret = mmc_regulator_get_supply(mmc);
3158 if (ret == -EPROBE_DEFER)
3159 goto undma;
3a48edc4 3160
6231f3de 3161 /* If vqmmc regulator and no 1.8V signalling, then there's no UHS */
3a48edc4
TK		 3162 if (!IS_ERR(mmc->supply.vqmmc)) {
3163 ret = regulator_enable(mmc->supply.vqmmc);
3164 if (!regulator_is_supported_voltage(mmc->supply.vqmmc, 1700000,
3165 1950000))
28da3589
AH		 3166 host->caps1 &= ~(SDHCI_SUPPORT_SDR104 |
3167 SDHCI_SUPPORT_SDR50 |
3168 SDHCI_SUPPORT_DDR50);
a3361aba
CB		 3169 if (ret) {
3170 pr_warn("%s: Failed to enable vqmmc regulator: %d\n",
3171 mmc_hostname(mmc), ret);
4bb74313 3172 mmc->supply.vqmmc = ERR_PTR(-EINVAL);
a3361aba 3173 }
8363c374 3174 }
6231f3de 3175
28da3589
AH		 3176 if (host->quirks2 & SDHCI_QUIRK2_NO_1_8_V) {
3177 host->caps1 &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
3178 SDHCI_SUPPORT_DDR50);
3179 }
6a66180a 3180
4188bba0 3181 /* Any UHS-I mode in caps implies SDR12 and SDR25 support. */
28da3589
AH		 3182 if (host->caps1 & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
3183 SDHCI_SUPPORT_DDR50))
f2119df6
AN		 3184 mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;
3185
3186 /* SDR104 supports also implies SDR50 support */
28da3589 3187 if (host->caps1 & SDHCI_SUPPORT_SDR104) {
f2119df6 3188 mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50;
156e14b1
GC		 3189 /* SD3.0: SDR104 is supported so (for eMMC) the caps2
3190 * field can be promoted to support HS200.
3191 */
549c0b18 3192 if (!(host->quirks2 & SDHCI_QUIRK2_BROKEN_HS200))
13868bf2 3193 mmc->caps2 |= MMC_CAP2_HS200;
28da3589 3194 } else if (host->caps1 & SDHCI_SUPPORT_SDR50) {
f2119df6 3195 mmc->caps |= MMC_CAP_UHS_SDR50;
28da3589 3196 }
f2119df6 3197
e9fb05d5 3198 if (host->quirks2 & SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 &&
28da3589 3199 (host->caps1 & SDHCI_SUPPORT_HS400))
e9fb05d5
AH		 3200 mmc->caps2 |= MMC_CAP2_HS400;
3201
549c0b18
AH		 3202 if ((mmc->caps2 & MMC_CAP2_HSX00_1_2V) &&
3203 (IS_ERR(mmc->supply.vqmmc) ||
3204 !regulator_is_supported_voltage(mmc->supply.vqmmc, 1100000,
3205 1300000)))
3206 mmc->caps2 &= ~MMC_CAP2_HSX00_1_2V;
3207
28da3589
AH		 3208 if ((host->caps1 & SDHCI_SUPPORT_DDR50) &&
3209 !(host->quirks2 & SDHCI_QUIRK2_BROKEN_DDR50))
f2119df6
AN		 3210 mmc->caps |= MMC_CAP_UHS_DDR50;
3211
069c9f14 3212 /* Does the host need tuning for SDR50? */
28da3589 3213 if (host->caps1 & SDHCI_USE_SDR50_TUNING)
b513ea25
AN		 3214 host->flags |= SDHCI_SDR50_NEEDS_TUNING;
3215
d6d50a15 3216 /* Driver Type(s) (A, C, D) supported by the host */
28da3589 3217 if (host->caps1 & SDHCI_DRIVER_TYPE_A)
d6d50a15 3218 mmc->caps |= MMC_CAP_DRIVER_TYPE_A;
28da3589 3219 if (host->caps1 & SDHCI_DRIVER_TYPE_C)
d6d50a15 3220 mmc->caps |= MMC_CAP_DRIVER_TYPE_C;
28da3589 3221 if (host->caps1 & SDHCI_DRIVER_TYPE_D)
d6d50a15
AN		 3222 mmc->caps |= MMC_CAP_DRIVER_TYPE_D;
3223
cf2b5eea 3224 /* Initial value for re-tuning timer count */
28da3589
AH		 3225 host->tuning_count = (host->caps1 & SDHCI_RETUNING_TIMER_COUNT_MASK) >>
3226 SDHCI_RETUNING_TIMER_COUNT_SHIFT;
cf2b5eea
AN		 3227
3228 /*
3229 * In case Re-tuning Timer is not disabled, the actual value of
3230 * re-tuning timer will be 2 ^ (n - 1).
3231 */
3232 if (host->tuning_count)
3233 host->tuning_count = 1 << (host->tuning_count - 1);
3234
3235 /* Re-tuning mode supported by the Host Controller */
28da3589 3236 host->tuning_mode = (host->caps1 & SDHCI_RETUNING_MODE_MASK) >>
cf2b5eea
AN		 3237 SDHCI_RETUNING_MODE_SHIFT;
3238
8f230f45 3239 ocr_avail = 0;
bad37e1a 3240
f2119df6
AN		 3241 /*
3242 * According to SD Host Controller spec v3.00, if the Host System
3243 * can afford more than 150mA, Host Driver should set XPC to 1. Also
3244 * the value is meaningful only if Voltage Support in the Capabilities
3245 * register is set. The actual current value is 4 times the register
3246 * value.
3247 */
3248 max_current_caps = sdhci_readl(host, SDHCI_MAX_CURRENT);
3a48edc4 3249 if (!max_current_caps && !IS_ERR(mmc->supply.vmmc)) {
ae906037 3250 int curr = regulator_get_current_limit(mmc->supply.vmmc);
bad37e1a
PR		 3251 if (curr > 0) {
3252
3253 /* convert to SDHCI_MAX_CURRENT format */
3254 curr = curr/1000; /* convert to mA */
3255 curr = curr/SDHCI_MAX_CURRENT_MULTIPLIER;
3256
3257 curr = min_t(u32, curr, SDHCI_MAX_CURRENT_LIMIT);
3258 max_current_caps =
3259 (curr << SDHCI_MAX_CURRENT_330_SHIFT) |
3260 (curr << SDHCI_MAX_CURRENT_300_SHIFT) |
3261 (curr << SDHCI_MAX_CURRENT_180_SHIFT);
3262 }
3263 }
f2119df6 3264
28da3589 3265 if (host->caps & SDHCI_CAN_VDD_330) {
8f230f45 3266 ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34;
f2119df6 3267
55c4665e 3268 mmc->max_current_330 = ((max_current_caps &
f2119df6
AN		 3269 SDHCI_MAX_CURRENT_330_MASK) >>
3270 SDHCI_MAX_CURRENT_330_SHIFT) *
3271 SDHCI_MAX_CURRENT_MULTIPLIER;
f2119df6 3272 }
28da3589 3273 if (host->caps & SDHCI_CAN_VDD_300) {
8f230f45 3274 ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31;
f2119df6 3275
55c4665e 3276 mmc->max_current_300 = ((max_current_caps &
f2119df6
AN		 3277 SDHCI_MAX_CURRENT_300_MASK) >>
3278 SDHCI_MAX_CURRENT_300_SHIFT) *
3279 SDHCI_MAX_CURRENT_MULTIPLIER;
f2119df6 3280 }
28da3589 3281 if (host->caps & SDHCI_CAN_VDD_180) {
8f230f45
TI		 3282 ocr_avail |= MMC_VDD_165_195;
3283
55c4665e 3284 mmc->max_current_180 = ((max_current_caps &
f2119df6
AN		 3285 SDHCI_MAX_CURRENT_180_MASK) >>
3286 SDHCI_MAX_CURRENT_180_SHIFT) *
3287 SDHCI_MAX_CURRENT_MULTIPLIER;
f2119df6
AN		 3288 }
3289
5fd26c7e
UH		 3290 /* If OCR set by host, use it instead. */
3291 if (host->ocr_mask)
3292 ocr_avail = host->ocr_mask;
3293
3294 /* If OCR set by external regulators, give it highest prio. */
3a48edc4 3295 if (mmc->ocr_avail)
52221610 3296 ocr_avail = mmc->ocr_avail;
3a48edc4 3297
8f230f45
TI		 3298 mmc->ocr_avail = ocr_avail;
3299 mmc->ocr_avail_sdio = ocr_avail;
3300 if (host->ocr_avail_sdio)
3301 mmc->ocr_avail_sdio &= host->ocr_avail_sdio;
3302 mmc->ocr_avail_sd = ocr_avail;
3303 if (host->ocr_avail_sd)
3304 mmc->ocr_avail_sd &= host->ocr_avail_sd;
3305 else /* normal SD controllers don't support 1.8V */
3306 mmc->ocr_avail_sd &= ~MMC_VDD_165_195;
3307 mmc->ocr_avail_mmc = ocr_avail;
3308 if (host->ocr_avail_mmc)
3309 mmc->ocr_avail_mmc &= host->ocr_avail_mmc;
146ad66e
PO		 3310
3311 if (mmc->ocr_avail == 0) {
2e4456f0
MV		 3312 pr_err("%s: Hardware doesn't report any support voltages.\n",
3313 mmc_hostname(mmc));
eb5c20de
AH		 3314 ret = -ENODEV;
3315 goto unreg;
146ad66e
PO		 3316 }
3317
8cb851a4
AH		 3318 if ((mmc->caps & (MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 |
3319 MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_SDR104 |
3320 MMC_CAP_UHS_DDR50 | MMC_CAP_1_8V_DDR)) ||
3321 (mmc->caps2 & (MMC_CAP2_HS200_1_8V_SDR | MMC_CAP2_HS400_1_8V)))
3322 host->flags |= SDHCI_SIGNALING_180;
3323
3324 if (mmc->caps2 & MMC_CAP2_HSX00_1_2V)
3325 host->flags |= SDHCI_SIGNALING_120;
3326
d129bceb
PO		 3327 spin_lock_init(&host->lock);
3328
3329 /*
2134a922
PO		 3330 * Maximum number of segments. Depends on if the hardware
3331 * can do scatter/gather or not.
d129bceb 3332 */
2134a922 3333 if (host->flags & SDHCI_USE_ADMA)
4fb213f8 3334 mmc->max_segs = SDHCI_MAX_SEGS;
a13abc7b 3335 else if (host->flags & SDHCI_USE_SDMA)
a36274e0 3336 mmc->max_segs = 1;
2134a922 3337 else /* PIO */
4fb213f8 3338 mmc->max_segs = SDHCI_MAX_SEGS;
d129bceb
PO		 3339
3340 /*
ac00531d
AH		 3341 * Maximum number of sectors in one transfer. Limited by SDMA boundary
3342 * size (512KiB). Note some tuning modes impose a 4MiB limit, but this
3343 * is less anyway.
d129bceb 3344 */
55db890a 3345 mmc->max_req_size = 524288;
d129bceb
PO		 3346
3347 /*
3348 * Maximum segment size. Could be one segment with the maximum number
2134a922
PO		 3349 * of bytes. When doing hardware scatter/gather, each entry cannot
3350 * be larger than 64 KiB though.
d129bceb 3351 */
30652aa3
OJ		 3352 if (host->flags & SDHCI_USE_ADMA) {
3353 if (host->quirks & SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC)
3354 mmc->max_seg_size = 65535;
3355 else
3356 mmc->max_seg_size = 65536;
3357 } else {
2134a922 3358 mmc->max_seg_size = mmc->max_req_size;
30652aa3 3359 }
d129bceb 3360
fe4a3c7a
PO		 3361 /*
3362 * Maximum block size. This varies from controller to controller and
3363 * is specified in the capabilities register.
3364 */
0633f654
AV		 3365 if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) {
3366 mmc->max_blk_size = 2;
3367 } else {
28da3589 3368 mmc->max_blk_size = (host->caps & SDHCI_MAX_BLOCK_MASK) >>
0633f654
AV		 3369 SDHCI_MAX_BLOCK_SHIFT;
3370 if (mmc->max_blk_size >= 3) {
6606110d
JP		 3371 pr_warn("%s: Invalid maximum block size, assuming 512 bytes\n",
3372 mmc_hostname(mmc));
0633f654
AV		 3373 mmc->max_blk_size = 0;
3374 }
3375 }
3376
3377 mmc->max_blk_size = 512 << mmc->max_blk_size;
fe4a3c7a 3378
55db890a
PO		 3379 /*
3380 * Maximum block count.
3381 */
1388eefd 3382 mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
55db890a 3383
52f5336d
AH		 3384 return 0;
3385
3386unreg:
3387 if (!IS_ERR(mmc->supply.vqmmc))
3388 regulator_disable(mmc->supply.vqmmc);
3389undma:
3390 if (host->align_buffer)
3391 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
3392 host->adma_table_sz, host->align_buffer,
3393 host->align_addr);
3394 host->adma_table = NULL;
3395 host->align_buffer = NULL;
3396
3397 return ret;
3398}
3399EXPORT_SYMBOL_GPL(sdhci_setup_host);
3400
3401int __sdhci_add_host(struct sdhci_host *host)
3402{
3403 struct mmc_host *mmc = host->mmc;
3404 int ret;
3405
d129bceb
PO		 3406 /*
3407 * Init tasklets.
3408 */
d129bceb
PO		 3409 tasklet_init(&host->finish_tasklet,
3410 sdhci_tasklet_finish, (unsigned long)host);
3411
e4cad1b5 3412 setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host);
d129bceb 3413
250fb7b4 3414 init_waitqueue_head(&host->buf_ready_int);
b513ea25 3415
2af502ca
SG		 3416 sdhci_init(host, 0);
3417
781e989c
RK		 3418 ret = request_threaded_irq(host->irq, sdhci_irq, sdhci_thread_irq,
3419 IRQF_SHARED, mmc_hostname(mmc), host);
0fc81ee3
MB		 3420 if (ret) {
3421 pr_err("%s: Failed to request IRQ %d: %d\n",
3422 mmc_hostname(mmc), host->irq, ret);
8ef1a143 3423 goto untasklet;
0fc81ee3 3424 }
d129bceb 3425
d129bceb
PO		 3426#ifdef CONFIG_MMC_DEBUG
3427 sdhci_dumpregs(host);
3428#endif
3429
061d17a6 3430 ret = sdhci_led_register(host);
0fc81ee3
MB		 3431 if (ret) {
3432 pr_err("%s: Failed to register LED device: %d\n",
3433 mmc_hostname(mmc), ret);
eb5c20de 3434 goto unirq;
0fc81ee3 3435 }
2f730fec 3436
5f25a66f
PO		 3437 mmiowb();
3438
eb5c20de
AH		 3439 ret = mmc_add_host(mmc);
3440 if (ret)
3441 goto unled;
d129bceb 3442
a3c76eb9 3443 pr_info("%s: SDHCI controller on %s [%s] using %s\n",
d1b26863 3444 mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)),
e57a5f61
AH		 3445 (host->flags & SDHCI_USE_ADMA) ?
3446 (host->flags & SDHCI_USE_64_BIT_DMA) ? "ADMA 64-bit" : "ADMA" :
a13abc7b 3447 (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO");
d129bceb 3448
7260cf5e
AV		 3449 sdhci_enable_card_detection(host);
3450
d129bceb
PO		 3451 return 0;
3452
eb5c20de 3453unled:
061d17a6 3454 sdhci_led_unregister(host);
eb5c20de 3455unirq:
03231f9b 3456 sdhci_do_reset(host, SDHCI_RESET_ALL);
b537f94c
RK		 3457 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
3458 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
2f730fec 3459 free_irq(host->irq, host);
8ef1a143 3460untasklet:
d129bceb 3461 tasklet_kill(&host->finish_tasklet);
52f5336d 3462
eb5c20de
AH		 3463 if (!IS_ERR(mmc->supply.vqmmc))
3464 regulator_disable(mmc->supply.vqmmc);
52f5336d 3465
eb5c20de
AH		 3466 if (host->align_buffer)
3467 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
3468 host->adma_table_sz, host->align_buffer,
3469 host->align_addr);
3470 host->adma_table = NULL;
3471 host->align_buffer = NULL;
d129bceb
PO		 3472
3473 return ret;
3474}
52f5336d
AH		 3475EXPORT_SYMBOL_GPL(__sdhci_add_host);
3476
3477int sdhci_add_host(struct sdhci_host *host)
3478{
3479 int ret;
3480
3481 ret = sdhci_setup_host(host);
3482 if (ret)
3483 return ret;
d129bceb 3484
52f5336d
AH		 3485 return __sdhci_add_host(host);
3486}
b8c86fc5 3487EXPORT_SYMBOL_GPL(sdhci_add_host);
d129bceb 3488
1e72859e 3489void sdhci_remove_host(struct sdhci_host *host, int dead)
b8c86fc5 3490{
3a48edc4 3491 struct mmc_host *mmc = host->mmc;
1e72859e
PO		 3492 unsigned long flags;
3493
3494 if (dead) {
3495 spin_lock_irqsave(&host->lock, flags);
3496
3497 host->flags |= SDHCI_DEVICE_DEAD;
3498
3499 if (host->mrq) {
a3c76eb9 3500 pr_err("%s: Controller removed during "
4e743f1f 3501 " transfer!\n", mmc_hostname(mmc));
1e72859e
PO		 3502
3503 host->mrq->cmd->error = -ENOMEDIUM;
a6d3bdd5 3504 sdhci_finish_mrq(host, host->mrq);
1e72859e
PO		 3505 }
3506
3507 spin_unlock_irqrestore(&host->lock, flags);
3508 }
3509
7260cf5e
AV		 3510 sdhci_disable_card_detection(host);
3511
4e743f1f 3512 mmc_remove_host(mmc);
d129bceb 3513
061d17a6 3514 sdhci_led_unregister(host);
2f730fec 3515
1e72859e 3516 if (!dead)
03231f9b 3517 sdhci_do_reset(host, SDHCI_RESET_ALL);
d129bceb 3518
b537f94c
RK		 3519 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
3520 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
d129bceb
PO		 3521 free_irq(host->irq, host);
3522
3523 del_timer_sync(&host->timer);
3524
d129bceb 3525 tasklet_kill(&host->finish_tasklet);
2134a922 3526
3a48edc4
TK		 3527 if (!IS_ERR(mmc->supply.vqmmc))
3528 regulator_disable(mmc->supply.vqmmc);
6231f3de 3529
edd63fcc 3530 if (host->align_buffer)
e66e61cb
RK		 3531 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
3532 host->adma_table_sz, host->align_buffer,
3533 host->align_addr);
2134a922 3534
4efaa6fb 3535 host->adma_table = NULL;
2134a922 3536 host->align_buffer = NULL;
d129bceb
PO		 3537}
3538
b8c86fc5 3539EXPORT_SYMBOL_GPL(sdhci_remove_host);
d129bceb 3540
b8c86fc5 3541void sdhci_free_host(struct sdhci_host *host)
d129bceb 3542{
b8c86fc5 3543 mmc_free_host(host->mmc);
d129bceb
PO		 3544}
3545
b8c86fc5 3546EXPORT_SYMBOL_GPL(sdhci_free_host);
d129bceb
PO		 3547
3548/*****************************************************************************\
3549 * *
3550 * Driver init/exit *
3551 * *
3552\*****************************************************************************/
3553
3554static int __init sdhci_drv_init(void)
3555{
a3c76eb9 3556 pr_info(DRIVER_NAME
52fbf9c9 3557 ": Secure Digital Host Controller Interface driver\n");
a3c76eb9 3558 pr_info(DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
d129bceb 3559
b8c86fc5 3560 return 0;
d129bceb
PO		 3561}
3562
3563static void __exit sdhci_drv_exit(void)
3564{
d129bceb
PO		 3565}
3566
3567module_init(sdhci_drv_init);
3568module_exit(sdhci_drv_exit);
3569
df673b22 3570module_param(debug_quirks, uint, 0444);
66fd8ad5 3571module_param(debug_quirks2, uint, 0444);
67435274 3572
32710e8f 3573MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
b8c86fc5 3574MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver");
d129bceb 3575MODULE_LICENSE("GPL");
67435274 3576
df673b22 3577MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");
66fd8ad5 3578MODULE_PARM_DESC(debug_quirks2, "Force certain other quirks.");
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