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mmc: sdhci: Get rid of redundant BUG_ONs
[mirror_ubuntu-artful-kernel.git] / drivers / mmc / host / sdhci.c
CommitLineData
d129bceb 1/*
70f10482 2 * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
d129bceb 3 *
b69c9058 4 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
d129bceb
PO		 5 *
6 * This program is free software; you can redistribute it and/or modify
643f720c
PO		 7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or (at
9 * your option) any later version.
84c46a53
PO		 10 *
11 * Thanks to the following companies for their support:
12 *
13 * - JMicron (hardware and technical support)
d129bceb
PO		 14 */
15
d129bceb
PO		 16#include <linux/delay.h>
17#include <linux/highmem.h>
b8c86fc5 18#include <linux/io.h>
88b47679 19#include <linux/module.h>
d129bceb 20#include <linux/dma-mapping.h>
5a0e3ad6 21#include <linux/slab.h>
11763609 22#include <linux/scatterlist.h>
9bea3c85 23#include <linux/regulator/consumer.h>
66fd8ad5 24#include <linux/pm_runtime.h>
d129bceb 25
2f730fec
PO		 26#include <linux/leds.h>
27
22113efd 28#include <linux/mmc/mmc.h>
d129bceb 29#include <linux/mmc/host.h>
473b095a 30#include <linux/mmc/card.h>
85cc1c33 31#include <linux/mmc/sdio.h>
bec9d4e5 32#include <linux/mmc/slot-gpio.h>
d129bceb 33
d129bceb
PO		 34#include "sdhci.h"
35
36#define DRIVER_NAME "sdhci"
d129bceb 37
d129bceb 38#define DBG(f, x...) \
c6563178 39 pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
d129bceb 40
b513ea25
AN		 41#define MAX_TUNING_LOOP 40
42
df673b22 43static unsigned int debug_quirks = 0;
66fd8ad5 44static unsigned int debug_quirks2;
67435274 45
d129bceb
PO		 46static void sdhci_finish_data(struct sdhci_host *);
47
52983382 48static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable);
d129bceb
PO		 49
50static void sdhci_dumpregs(struct sdhci_host *host)
51{
a7c53671
CD		 52 pr_err(DRIVER_NAME ": =========== REGISTER DUMP (%s)===========\n",
53 mmc_hostname(host->mmc));
d129bceb 54
a7c53671
CD		 55 pr_err(DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n",
56 sdhci_readl(host, SDHCI_DMA_ADDRESS),
57 sdhci_readw(host, SDHCI_HOST_VERSION));
58 pr_err(DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n",
59 sdhci_readw(host, SDHCI_BLOCK_SIZE),
60 sdhci_readw(host, SDHCI_BLOCK_COUNT));
61 pr_err(DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
62 sdhci_readl(host, SDHCI_ARGUMENT),
63 sdhci_readw(host, SDHCI_TRANSFER_MODE));
64 pr_err(DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n",
65 sdhci_readl(host, SDHCI_PRESENT_STATE),
66 sdhci_readb(host, SDHCI_HOST_CONTROL));
67 pr_err(DRIVER_NAME ": Power: 0x%08x | Blk gap: 0x%08x\n",
68 sdhci_readb(host, SDHCI_POWER_CONTROL),
69 sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL));
70 pr_err(DRIVER_NAME ": Wake-up: 0x%08x | Clock: 0x%08x\n",
71 sdhci_readb(host, SDHCI_WAKE_UP_CONTROL),
72 sdhci_readw(host, SDHCI_CLOCK_CONTROL));
73 pr_err(DRIVER_NAME ": Timeout: 0x%08x | Int stat: 0x%08x\n",
74 sdhci_readb(host, SDHCI_TIMEOUT_CONTROL),
75 sdhci_readl(host, SDHCI_INT_STATUS));
76 pr_err(DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
77 sdhci_readl(host, SDHCI_INT_ENABLE),
78 sdhci_readl(host, SDHCI_SIGNAL_ENABLE));
79 pr_err(DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
80 sdhci_readw(host, SDHCI_ACMD12_ERR),
81 sdhci_readw(host, SDHCI_SLOT_INT_STATUS));
82 pr_err(DRIVER_NAME ": Caps: 0x%08x | Caps_1: 0x%08x\n",
83 sdhci_readl(host, SDHCI_CAPABILITIES),
84 sdhci_readl(host, SDHCI_CAPABILITIES_1));
85 pr_err(DRIVER_NAME ": Cmd: 0x%08x | Max curr: 0x%08x\n",
86 sdhci_readw(host, SDHCI_COMMAND),
87 sdhci_readl(host, SDHCI_MAX_CURRENT));
88 pr_err(DRIVER_NAME ": Host ctl2: 0x%08x\n",
89 sdhci_readw(host, SDHCI_HOST_CONTROL2));
d129bceb 90
e57a5f61
AH		 91 if (host->flags & SDHCI_USE_ADMA) {
92 if (host->flags & SDHCI_USE_64_BIT_DMA)
a7c53671
CD		 93 pr_err(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x%08x\n",
94 readl(host->ioaddr + SDHCI_ADMA_ERROR),
95 readl(host->ioaddr + SDHCI_ADMA_ADDRESS_HI),
96 readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
e57a5f61 97 else
a7c53671
CD		 98 pr_err(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n",
99 readl(host->ioaddr + SDHCI_ADMA_ERROR),
100 readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
e57a5f61 101 }
be3f4ae0 102
a7c53671 103 pr_err(DRIVER_NAME ": ===========================================\n");
d129bceb
PO		 104}
105
106/*****************************************************************************\
107 * *
108 * Low level functions *
109 * *
110\*****************************************************************************/
111
7260cf5e
AV		 112static void sdhci_set_card_detection(struct sdhci_host *host, bool enable)
113{
5b4f1f6c 114 u32 present;
7260cf5e 115
c79396c1 116 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) ||
860951c5 117 !mmc_card_is_removable(host->mmc))
66fd8ad5
AH		 118 return;
119
5b4f1f6c
RK		 120 if (enable) {
121 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
122 SDHCI_CARD_PRESENT;
d25928d1 123
5b4f1f6c
RK		 124 host->ier |= present ? SDHCI_INT_CARD_REMOVE :
125 SDHCI_INT_CARD_INSERT;
126 } else {
127 host->ier &= ~(SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT);
128 }
b537f94c
RK		 129
130 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
131 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
7260cf5e
AV		 132}
133
134static void sdhci_enable_card_detection(struct sdhci_host *host)
135{
136 sdhci_set_card_detection(host, true);
137}
138
139static void sdhci_disable_card_detection(struct sdhci_host *host)
140{
141 sdhci_set_card_detection(host, false);
142}
143
02d0b685
UH		 144static void sdhci_runtime_pm_bus_on(struct sdhci_host *host)
145{
146 if (host->bus_on)
147 return;
148 host->bus_on = true;
149 pm_runtime_get_noresume(host->mmc->parent);
150}
151
152static void sdhci_runtime_pm_bus_off(struct sdhci_host *host)
153{
154 if (!host->bus_on)
155 return;
156 host->bus_on = false;
157 pm_runtime_put_noidle(host->mmc->parent);
158}
159
03231f9b 160void sdhci_reset(struct sdhci_host *host, u8 mask)
d129bceb 161{
e16514d8 162 unsigned long timeout;
393c1a34 163
4e4141a5 164 sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
d129bceb 165
f0710a55 166 if (mask & SDHCI_RESET_ALL) {
d129bceb 167 host->clock = 0;
f0710a55
AH		 168 /* Reset-all turns off SD Bus Power */
169 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
170 sdhci_runtime_pm_bus_off(host);
171 }
d129bceb 172
e16514d8
PO		 173 /* Wait max 100 ms */
174 timeout = 100;
175
176 /* hw clears the bit when it's done */
4e4141a5 177 while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
e16514d8 178 if (timeout == 0) {
a3c76eb9 179 pr_err("%s: Reset 0x%x never completed.\n",
e16514d8
PO		 180 mmc_hostname(host->mmc), (int)mask);
181 sdhci_dumpregs(host);
182 return;
183 }
184 timeout--;
185 mdelay(1);
d129bceb 186 }
03231f9b
RK		 187}
188EXPORT_SYMBOL_GPL(sdhci_reset);
189
190static void sdhci_do_reset(struct sdhci_host *host, u8 mask)
191{
192 if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
d3940f27
AH		 193 struct mmc_host *mmc = host->mmc;
194
195 if (!mmc->ops->get_cd(mmc))
03231f9b
RK		 196 return;
197 }
063a9dbb 198
03231f9b 199 host->ops->reset(host, mask);
393c1a34 200
da91a8f9
RK		 201 if (mask & SDHCI_RESET_ALL) {
202 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
203 if (host->ops->enable_dma)
204 host->ops->enable_dma(host);
205 }
206
207 /* Resetting the controller clears many */
208 host->preset_enabled = false;
3abc1e80 209 }
d129bceb
PO		 210}
211
2f4cbb3d 212static void sdhci_init(struct sdhci_host *host, int soft)
d129bceb 213{
d3940f27
AH		 214 struct mmc_host *mmc = host->mmc;
215
2f4cbb3d 216 if (soft)
03231f9b 217 sdhci_do_reset(host, SDHCI_RESET_CMD|SDHCI_RESET_DATA);
2f4cbb3d 218 else
03231f9b 219 sdhci_do_reset(host, SDHCI_RESET_ALL);
d129bceb 220
b537f94c
RK		 221 host->ier = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
222 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT |
223 SDHCI_INT_INDEX | SDHCI_INT_END_BIT | SDHCI_INT_CRC |
224 SDHCI_INT_TIMEOUT | SDHCI_INT_DATA_END |
225 SDHCI_INT_RESPONSE;
226
227 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
228 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2f4cbb3d
NP		 229
230 if (soft) {
231 /* force clock reconfiguration */
232 host->clock = 0;
d3940f27 233 mmc->ops->set_ios(mmc, &mmc->ios);
2f4cbb3d 234 }
7260cf5e 235}
d129bceb 236
7260cf5e
AV		 237static void sdhci_reinit(struct sdhci_host *host)
238{
2f4cbb3d 239 sdhci_init(host, 0);
7260cf5e 240 sdhci_enable_card_detection(host);
d129bceb
PO		 241}
242
061d17a6 243static void __sdhci_led_activate(struct sdhci_host *host)
d129bceb
PO		 244{
245 u8 ctrl;
246
4e4141a5 247 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
d129bceb 248 ctrl |= SDHCI_CTRL_LED;
4e4141a5 249 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d129bceb
PO		 250}
251
061d17a6 252static void __sdhci_led_deactivate(struct sdhci_host *host)
d129bceb
PO		 253{
254 u8 ctrl;
255
4e4141a5 256 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
d129bceb 257 ctrl &= ~SDHCI_CTRL_LED;
4e4141a5 258 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d129bceb
PO		 259}
260
4f78230f 261#if IS_REACHABLE(CONFIG_LEDS_CLASS)
2f730fec 262static void sdhci_led_control(struct led_classdev *led,
061d17a6 263 enum led_brightness brightness)
2f730fec
PO		 264{
265 struct sdhci_host *host = container_of(led, struct sdhci_host, led);
266 unsigned long flags;
267
268 spin_lock_irqsave(&host->lock, flags);
269
66fd8ad5
AH		 270 if (host->runtime_suspended)
271 goto out;
272
2f730fec 273 if (brightness == LED_OFF)
061d17a6 274 __sdhci_led_deactivate(host);
2f730fec 275 else
061d17a6 276 __sdhci_led_activate(host);
66fd8ad5 277out:
2f730fec
PO		 278 spin_unlock_irqrestore(&host->lock, flags);
279}
061d17a6
AH		 280
281static int sdhci_led_register(struct sdhci_host *host)
282{
283 struct mmc_host *mmc = host->mmc;
284
285 snprintf(host->led_name, sizeof(host->led_name),
286 "%s::", mmc_hostname(mmc));
287
288 host->led.name = host->led_name;
289 host->led.brightness = LED_OFF;
290 host->led.default_trigger = mmc_hostname(mmc);
291 host->led.brightness_set = sdhci_led_control;
292
293 return led_classdev_register(mmc_dev(mmc), &host->led);
294}
295
296static void sdhci_led_unregister(struct sdhci_host *host)
297{
298 led_classdev_unregister(&host->led);
299}
300
301static inline void sdhci_led_activate(struct sdhci_host *host)
302{
303}
304
305static inline void sdhci_led_deactivate(struct sdhci_host *host)
306{
307}
308
309#else
310
311static inline int sdhci_led_register(struct sdhci_host *host)
312{
313 return 0;
314}
315
316static inline void sdhci_led_unregister(struct sdhci_host *host)
317{
318}
319
320static inline void sdhci_led_activate(struct sdhci_host *host)
321{
322 __sdhci_led_activate(host);
323}
324
325static inline void sdhci_led_deactivate(struct sdhci_host *host)
326{
327 __sdhci_led_deactivate(host);
328}
329
2f730fec
PO		 330#endif
331
d129bceb
PO		 332/*****************************************************************************\
333 * *
334 * Core functions *
335 * *
336\*****************************************************************************/
337
a406f5a3 338static void sdhci_read_block_pio(struct sdhci_host *host)
d129bceb 339{
7659150c
PO		 340 unsigned long flags;
341 size_t blksize, len, chunk;
7244b85b 342 u32 uninitialized_var(scratch);
7659150c 343 u8 *buf;
d129bceb 344
a406f5a3 345 DBG("PIO reading\n");
d129bceb 346
a406f5a3 347 blksize = host->data->blksz;
7659150c 348 chunk = 0;
d129bceb 349
7659150c 350 local_irq_save(flags);
d129bceb 351
a406f5a3 352 while (blksize) {
bf3a35ac 353 BUG_ON(!sg_miter_next(&host->sg_miter));
d129bceb 354
7659150c 355 len = min(host->sg_miter.length, blksize);
d129bceb 356
7659150c
PO		 357 blksize -= len;
358 host->sg_miter.consumed = len;
14d836e7 359
7659150c 360 buf = host->sg_miter.addr;
d129bceb 361
7659150c
PO		 362 while (len) {
363 if (chunk == 0) {
4e4141a5 364 scratch = sdhci_readl(host, SDHCI_BUFFER);
7659150c 365 chunk = 4;
a406f5a3 366 }
7659150c
PO		 367
368 *buf = scratch & 0xFF;
369
370 buf++;
371 scratch >>= 8;
372 chunk--;
373 len--;
d129bceb 374 }
a406f5a3 375 }
7659150c
PO		 376
377 sg_miter_stop(&host->sg_miter);
378
379 local_irq_restore(flags);
a406f5a3 380}
d129bceb 381
a406f5a3
PO		 382static void sdhci_write_block_pio(struct sdhci_host *host)
383{
7659150c
PO		 384 unsigned long flags;
385 size_t blksize, len, chunk;
386 u32 scratch;
387 u8 *buf;
d129bceb 388
a406f5a3
PO		 389 DBG("PIO writing\n");
390
391 blksize = host->data->blksz;
7659150c
PO		 392 chunk = 0;
393 scratch = 0;
d129bceb 394
7659150c 395 local_irq_save(flags);
d129bceb 396
a406f5a3 397 while (blksize) {
bf3a35ac 398 BUG_ON(!sg_miter_next(&host->sg_miter));
a406f5a3 399
7659150c
PO		 400 len = min(host->sg_miter.length, blksize);
401
402 blksize -= len;
403 host->sg_miter.consumed = len;
404
405 buf = host->sg_miter.addr;
d129bceb 406
7659150c
PO		 407 while (len) {
408 scratch |= (u32)*buf << (chunk * 8);
409
410 buf++;
411 chunk++;
412 len--;
413
414 if ((chunk == 4) || ((len == 0) && (blksize == 0))) {
4e4141a5 415 sdhci_writel(host, scratch, SDHCI_BUFFER);
7659150c
PO		 416 chunk = 0;
417 scratch = 0;
d129bceb 418 }
d129bceb
PO		 419 }
420 }
7659150c
PO		 421
422 sg_miter_stop(&host->sg_miter);
423
424 local_irq_restore(flags);
a406f5a3
PO		 425}
426
427static void sdhci_transfer_pio(struct sdhci_host *host)
428{
429 u32 mask;
430
7659150c 431 if (host->blocks == 0)
a406f5a3
PO		 432 return;
433
434 if (host->data->flags & MMC_DATA_READ)
435 mask = SDHCI_DATA_AVAILABLE;
436 else
437 mask = SDHCI_SPACE_AVAILABLE;
438
4a3cba32
PO		 439 /*
440 * Some controllers (JMicron JMB38x) mess up the buffer bits
441 * for transfers < 4 bytes. As long as it is just one block,
442 * we can ignore the bits.
443 */
444 if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) &&
445 (host->data->blocks == 1))
446 mask = ~0;
447
4e4141a5 448 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
3e3bf207
AV		 449 if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY)
450 udelay(100);
451
a406f5a3
PO		 452 if (host->data->flags & MMC_DATA_READ)
453 sdhci_read_block_pio(host);
454 else
455 sdhci_write_block_pio(host);
d129bceb 456
7659150c
PO		 457 host->blocks--;
458 if (host->blocks == 0)
a406f5a3 459 break;
a406f5a3 460 }
d129bceb 461
a406f5a3 462 DBG("PIO transfer complete.\n");
d129bceb
PO		 463}
464
48857d9b 465static int sdhci_pre_dma_transfer(struct sdhci_host *host,
c0999b72 466 struct mmc_data *data, int cookie)
48857d9b
RK		 467{
468 int sg_count;
469
94538e51
RK		 470 /*
471 * If the data buffers are already mapped, return the previous
472 * dma_map_sg() result.
473 */
474 if (data->host_cookie == COOKIE_PRE_MAPPED)
48857d9b 475 return data->sg_count;
48857d9b
RK		 476
477 sg_count = dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
478 data->flags & MMC_DATA_WRITE ?
479 DMA_TO_DEVICE : DMA_FROM_DEVICE);
480
481 if (sg_count == 0)
482 return -ENOSPC;
483
484 data->sg_count = sg_count;
c0999b72 485 data->host_cookie = cookie;
48857d9b
RK		 486
487 return sg_count;
488}
489
2134a922
PO		 490static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags)
491{
492 local_irq_save(*flags);
482fce99 493 return kmap_atomic(sg_page(sg)) + sg->offset;
2134a922
PO		 494}
495
496static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags)
497{
482fce99 498 kunmap_atomic(buffer);
2134a922
PO		 499 local_irq_restore(*flags);
500}
501
e57a5f61
AH		 502static void sdhci_adma_write_desc(struct sdhci_host *host, void *desc,
503 dma_addr_t addr, int len, unsigned cmd)
118cd17d 504{
e57a5f61 505 struct sdhci_adma2_64_desc *dma_desc = desc;
118cd17d 506
e57a5f61 507 /* 32-bit and 64-bit descriptors have these members in same position */
0545230f
AH		 508 dma_desc->cmd = cpu_to_le16(cmd);
509 dma_desc->len = cpu_to_le16(len);
e57a5f61
AH		 510 dma_desc->addr_lo = cpu_to_le32((u32)addr);
511
512 if (host->flags & SDHCI_USE_64_BIT_DMA)
513 dma_desc->addr_hi = cpu_to_le32((u64)addr >> 32);
118cd17d
BD		 514}
515
b5ffa674
AH		 516static void sdhci_adma_mark_end(void *desc)
517{
e57a5f61 518 struct sdhci_adma2_64_desc *dma_desc = desc;
b5ffa674 519
e57a5f61 520 /* 32-bit and 64-bit descriptors have 'cmd' in same position */
0545230f 521 dma_desc->cmd |= cpu_to_le16(ADMA2_END);
b5ffa674
AH		 522}
523
60c64762
RK		 524static void sdhci_adma_table_pre(struct sdhci_host *host,
525 struct mmc_data *data, int sg_count)
2134a922 526{
2134a922 527 struct scatterlist *sg;
2134a922 528 unsigned long flags;
acc3ad13
RK		 529 dma_addr_t addr, align_addr;
530 void *desc, *align;
531 char *buffer;
532 int len, offset, i;
2134a922
PO		 533
534 /*
535 * The spec does not specify endianness of descriptor table.
536 * We currently guess that it is LE.
537 */
538
60c64762 539 host->sg_count = sg_count;
2134a922 540
4efaa6fb 541 desc = host->adma_table;
2134a922
PO		 542 align = host->align_buffer;
543
544 align_addr = host->align_addr;
545
546 for_each_sg(data->sg, sg, host->sg_count, i) {
547 addr = sg_dma_address(sg);
548 len = sg_dma_len(sg);
549
550 /*
acc3ad13
RK		 551 * The SDHCI specification states that ADMA addresses must
552 * be 32-bit aligned. If they aren't, then we use a bounce
553 * buffer for the (up to three) bytes that screw up the
2134a922
PO		 554 * alignment.
555 */
04a5ae6f
AH		 556 offset = (SDHCI_ADMA2_ALIGN - (addr & SDHCI_ADMA2_MASK)) &
557 SDHCI_ADMA2_MASK;
2134a922
PO		 558 if (offset) {
559 if (data->flags & MMC_DATA_WRITE) {
560 buffer = sdhci_kmap_atomic(sg, &flags);
561 memcpy(align, buffer, offset);
562 sdhci_kunmap_atomic(buffer, &flags);
563 }
564
118cd17d 565 /* tran, valid */
e57a5f61 566 sdhci_adma_write_desc(host, desc, align_addr, offset,
739d46dc 567 ADMA2_TRAN_VALID);
2134a922
PO		 568
569 BUG_ON(offset > 65536);
570
04a5ae6f
AH		 571 align += SDHCI_ADMA2_ALIGN;
572 align_addr += SDHCI_ADMA2_ALIGN;
2134a922 573
76fe379a 574 desc += host->desc_sz;
2134a922
PO		 575
576 addr += offset;
577 len -= offset;
578 }
579
2134a922
PO		 580 BUG_ON(len > 65536);
581
347ea32d
AH		 582 if (len) {
583 /* tran, valid */
584 sdhci_adma_write_desc(host, desc, addr, len,
585 ADMA2_TRAN_VALID);
586 desc += host->desc_sz;
587 }
2134a922
PO		 588
589 /*
590 * If this triggers then we have a calculation bug
591 * somewhere. :/
592 */
76fe379a 593 WARN_ON((desc - host->adma_table) >= host->adma_table_sz);
2134a922
PO		 594 }
595
70764a90 596 if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) {
acc3ad13 597 /* Mark the last descriptor as the terminating descriptor */
4efaa6fb 598 if (desc != host->adma_table) {
76fe379a 599 desc -= host->desc_sz;
b5ffa674 600 sdhci_adma_mark_end(desc);
70764a90
TA		 601 }
602 } else {
acc3ad13 603 /* Add a terminating entry - nop, end, valid */
e57a5f61 604 sdhci_adma_write_desc(host, desc, 0, 0, ADMA2_NOP_END_VALID);
70764a90 605 }
2134a922
PO		 606}
607
608static void sdhci_adma_table_post(struct sdhci_host *host,
609 struct mmc_data *data)
610{
2134a922
PO		 611 struct scatterlist *sg;
612 int i, size;
1c3d5f6d 613 void *align;
2134a922
PO		 614 char *buffer;
615 unsigned long flags;
616
47fa9613
RK		 617 if (data->flags & MMC_DATA_READ) {
618 bool has_unaligned = false;
de0b65a7 619
47fa9613
RK		 620 /* Do a quick scan of the SG list for any unaligned mappings */
621 for_each_sg(data->sg, sg, host->sg_count, i)
622 if (sg_dma_address(sg) & SDHCI_ADMA2_MASK) {
623 has_unaligned = true;
624 break;
625 }
2134a922 626
47fa9613
RK		 627 if (has_unaligned) {
628 dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
f55c98f7 629 data->sg_len, DMA_FROM_DEVICE);
2134a922 630
47fa9613 631 align = host->align_buffer;
2134a922 632
47fa9613
RK		 633 for_each_sg(data->sg, sg, host->sg_count, i) {
634 if (sg_dma_address(sg) & SDHCI_ADMA2_MASK) {
635 size = SDHCI_ADMA2_ALIGN -
636 (sg_dma_address(sg) & SDHCI_ADMA2_MASK);
637
638 buffer = sdhci_kmap_atomic(sg, &flags);
639 memcpy(buffer, align, size);
640 sdhci_kunmap_atomic(buffer, &flags);
2134a922 641
47fa9613
RK		 642 align += SDHCI_ADMA2_ALIGN;
643 }
2134a922
PO		 644 }
645 }
646 }
2134a922
PO		 647}
648
a3c7778f 649static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd)
d129bceb 650{
1c8cde92 651 u8 count;
a3c7778f 652 struct mmc_data *data = cmd->data;
1c8cde92 653 unsigned target_timeout, current_timeout;
d129bceb 654
ee53ab5d
PO		 655 /*
656 * If the host controller provides us with an incorrect timeout
657 * value, just skip the check and use 0xE. The hardware may take
658 * longer to time out, but that's much better than having a too-short
659 * timeout value.
660 */
11a2f1b7 661 if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL)
ee53ab5d 662 return 0xE;
e538fbe8 663
a3c7778f 664 /* Unspecified timeout, assume max */
1d4d7744 665 if (!data && !cmd->busy_timeout)
a3c7778f 666 return 0xE;
d129bceb 667
a3c7778f
AW		 668 /* timeout in us */
669 if (!data)
1d4d7744 670 target_timeout = cmd->busy_timeout * 1000;
78a2ca27 671 else {
fafcfda9 672 target_timeout = DIV_ROUND_UP(data->timeout_ns, 1000);
7f05538a
RK		 673 if (host->clock && data->timeout_clks) {
674 unsigned long long val;
675
676 /*
677 * data->timeout_clks is in units of clock cycles.
678 * host->clock is in Hz. target_timeout is in us.
679 * Hence, us = 1000000 * cycles / Hz. Round up.
680 */
681 val = 1000000 * data->timeout_clks;
682 if (do_div(val, host->clock))
683 target_timeout++;
684 target_timeout += val;
685 }
78a2ca27 686 }
81b39802 687
1c8cde92
PO		 688 /*
689 * Figure out needed cycles.
690 * We do this in steps in order to fit inside a 32 bit int.
691 * The first step is the minimum timeout, which will have a
692 * minimum resolution of 6 bits:
693 * (1) 2^13*1000 > 2^22,
694 * (2) host->timeout_clk < 2^16
695 * =>
696 * (1) / (2) > 2^6
697 */
698 count = 0;
699 current_timeout = (1 << 13) * 1000 / host->timeout_clk;
700 while (current_timeout < target_timeout) {
701 count++;
702 current_timeout <<= 1;
703 if (count >= 0xF)
704 break;
705 }
706
707 if (count >= 0xF) {
09eeff52
CB		 708 DBG("%s: Too large timeout 0x%x requested for CMD%d!\n",
709 mmc_hostname(host->mmc), count, cmd->opcode);
1c8cde92
PO		 710 count = 0xE;
711 }
712
ee53ab5d
PO		 713 return count;
714}
715
6aa943ab
AV		 716static void sdhci_set_transfer_irqs(struct sdhci_host *host)
717{
718 u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL;
719 u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR;
720
721 if (host->flags & SDHCI_REQ_USE_DMA)
b537f94c 722 host->ier = (host->ier & ~pio_irqs) | dma_irqs;
6aa943ab 723 else
b537f94c
RK		 724 host->ier = (host->ier & ~dma_irqs) | pio_irqs;
725
726 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
727 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
6aa943ab
AV		 728}
729
b45e668a 730static void sdhci_set_timeout(struct sdhci_host *host, struct mmc_command *cmd)
ee53ab5d
PO		 731{
732 u8 count;
b45e668a
AD		 733
734 if (host->ops->set_timeout) {
735 host->ops->set_timeout(host, cmd);
736 } else {
737 count = sdhci_calc_timeout(host, cmd);
738 sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
739 }
740}
741
742static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd)
743{
2134a922 744 u8 ctrl;
a3c7778f 745 struct mmc_data *data = cmd->data;
ee53ab5d
PO		 746
747 WARN_ON(host->data);
748
b45e668a
AD		 749 if (data || (cmd->flags & MMC_RSP_BUSY))
750 sdhci_set_timeout(host, cmd);
a3c7778f
AW		 751
752 if (!data)
ee53ab5d
PO		 753 return;
754
755 /* Sanity checks */
756 BUG_ON(data->blksz * data->blocks > 524288);
757 BUG_ON(data->blksz > host->mmc->max_blk_size);
758 BUG_ON(data->blocks > 65535);
759
760 host->data = data;
761 host->data_early = 0;
f6a03cbf 762 host->data->bytes_xfered = 0;
ee53ab5d 763
fce14421 764 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2134a922 765 struct scatterlist *sg;
df953925 766 unsigned int length_mask, offset_mask;
a0eaf0f9 767 int i;
2134a922 768
fce14421
RK		 769 host->flags |= SDHCI_REQ_USE_DMA;
770
771 /*
772 * FIXME: This doesn't account for merging when mapping the
773 * scatterlist.
774 *
775 * The assumption here being that alignment and lengths are
776 * the same after DMA mapping to device address space.
777 */
a0eaf0f9 778 length_mask = 0;
df953925 779 offset_mask = 0;
2134a922 780 if (host->flags & SDHCI_USE_ADMA) {
df953925 781 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE) {
a0eaf0f9 782 length_mask = 3;
df953925
RK		 783 /*
784 * As we use up to 3 byte chunks to work
785 * around alignment problems, we need to
786 * check the offset as well.
787 */
788 offset_mask = 3;
789 }
2134a922
PO		 790 } else {
791 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE)
a0eaf0f9 792 length_mask = 3;
df953925
RK		 793 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR)
794 offset_mask = 3;
2134a922
PO		 795 }
796
df953925 797 if (unlikely(length_mask | offset_mask)) {
2134a922 798 for_each_sg(data->sg, sg, data->sg_len, i) {
a0eaf0f9 799 if (sg->length & length_mask) {
2e4456f0 800 DBG("Reverting to PIO because of transfer size (%d)\n",
a0eaf0f9 801 sg->length);
2134a922
PO		 802 host->flags &= ~SDHCI_REQ_USE_DMA;
803 break;
804 }
a0eaf0f9 805 if (sg->offset & offset_mask) {
2e4456f0 806 DBG("Reverting to PIO because of bad alignment\n");
2134a922
PO		 807 host->flags &= ~SDHCI_REQ_USE_DMA;
808 break;
809 }
810 }
811 }
812 }
813
8f1934ce 814 if (host->flags & SDHCI_REQ_USE_DMA) {
c0999b72 815 int sg_cnt = sdhci_pre_dma_transfer(host, data, COOKIE_MAPPED);
60c64762
RK		 816
817 if (sg_cnt <= 0) {
818 /*
819 * This only happens when someone fed
820 * us an invalid request.
821 */
822 WARN_ON(1);
823 host->flags &= ~SDHCI_REQ_USE_DMA;
824 } else if (host->flags & SDHCI_USE_ADMA) {
825 sdhci_adma_table_pre(host, data, sg_cnt);
826
827 sdhci_writel(host, host->adma_addr, SDHCI_ADMA_ADDRESS);
828 if (host->flags & SDHCI_USE_64_BIT_DMA)
829 sdhci_writel(host,
830 (u64)host->adma_addr >> 32,
831 SDHCI_ADMA_ADDRESS_HI);
8f1934ce 832 } else {
60c64762
RK		 833 WARN_ON(sg_cnt != 1);
834 sdhci_writel(host, sg_dma_address(data->sg),
835 SDHCI_DMA_ADDRESS);
8f1934ce
PO		 836 }
837 }
838
2134a922
PO		 839 /*
840 * Always adjust the DMA selection as some controllers
841 * (e.g. JMicron) can't do PIO properly when the selection
842 * is ADMA.
843 */
844 if (host->version >= SDHCI_SPEC_200) {
4e4141a5 845 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
2134a922
PO		 846 ctrl &= ~SDHCI_CTRL_DMA_MASK;
847 if ((host->flags & SDHCI_REQ_USE_DMA) &&
e57a5f61
AH		 848 (host->flags & SDHCI_USE_ADMA)) {
849 if (host->flags & SDHCI_USE_64_BIT_DMA)
850 ctrl |= SDHCI_CTRL_ADMA64;
851 else
852 ctrl |= SDHCI_CTRL_ADMA32;
853 } else {
2134a922 854 ctrl |= SDHCI_CTRL_SDMA;
e57a5f61 855 }
4e4141a5 856 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
c9fddbc4
PO		 857 }
858
8f1934ce 859 if (!(host->flags & SDHCI_REQ_USE_DMA)) {
da60a91d
SAS		 860 int flags;
861
862 flags = SG_MITER_ATOMIC;
863 if (host->data->flags & MMC_DATA_READ)
864 flags |= SG_MITER_TO_SG;
865 else
866 flags |= SG_MITER_FROM_SG;
867 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
7659150c 868 host->blocks = data->blocks;
d129bceb 869 }
c7fa9963 870
6aa943ab
AV		 871 sdhci_set_transfer_irqs(host);
872
f6a03cbf
MV		 873 /* Set the DMA boundary value and block size */
874 sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
875 data->blksz), SDHCI_BLOCK_SIZE);
4e4141a5 876 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
c7fa9963
PO		 877}
878
879static void sdhci_set_transfer_mode(struct sdhci_host *host,
e89d456f 880 struct mmc_command *cmd)
c7fa9963 881{
d3fc5d71 882 u16 mode = 0;
e89d456f 883 struct mmc_data *data = cmd->data;
c7fa9963 884
2b558c13 885 if (data == NULL) {
9b8ffea6
VW		 886 if (host->quirks2 &
887 SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD) {
888 sdhci_writew(host, 0x0, SDHCI_TRANSFER_MODE);
889 } else {
2b558c13 890 /* clear Auto CMD settings for no data CMDs */
9b8ffea6
VW		 891 mode = sdhci_readw(host, SDHCI_TRANSFER_MODE);
892 sdhci_writew(host, mode & ~(SDHCI_TRNS_AUTO_CMD12 |
2b558c13 893 SDHCI_TRNS_AUTO_CMD23), SDHCI_TRANSFER_MODE);
9b8ffea6 894 }
c7fa9963 895 return;
2b558c13 896 }
c7fa9963 897
e538fbe8
PO		 898 WARN_ON(!host->data);
899
d3fc5d71
VY		 900 if (!(host->quirks2 & SDHCI_QUIRK2_SUPPORT_SINGLE))
901 mode = SDHCI_TRNS_BLK_CNT_EN;
902
e89d456f 903 if (mmc_op_multi(cmd->opcode) || data->blocks > 1) {
d3fc5d71 904 mode = SDHCI_TRNS_BLK_CNT_EN | SDHCI_TRNS_MULTI;
e89d456f
AW		 905 /*
906 * If we are sending CMD23, CMD12 never gets sent
907 * on successful completion (so no Auto-CMD12).
908 */
85cc1c33
CD		 909 if (!host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD12) &&
910 (cmd->opcode != SD_IO_RW_EXTENDED))
e89d456f 911 mode |= SDHCI_TRNS_AUTO_CMD12;
8edf6371
AW		 912 else if (host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) {
913 mode |= SDHCI_TRNS_AUTO_CMD23;
914 sdhci_writel(host, host->mrq->sbc->arg, SDHCI_ARGUMENT2);
915 }
c4512f79 916 }
8edf6371 917
c7fa9963
PO		 918 if (data->flags & MMC_DATA_READ)
919 mode |= SDHCI_TRNS_READ;
c9fddbc4 920 if (host->flags & SDHCI_REQ_USE_DMA)
c7fa9963
PO		 921 mode |= SDHCI_TRNS_DMA;
922
4e4141a5 923 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
d129bceb
PO		 924}
925
926static void sdhci_finish_data(struct sdhci_host *host)
927{
928 struct mmc_data *data;
d129bceb 929
d129bceb
PO		 930 data = host->data;
931 host->data = NULL;
932
add8913d
RK		 933 if ((host->flags & (SDHCI_REQ_USE_DMA | SDHCI_USE_ADMA)) ==
934 (SDHCI_REQ_USE_DMA | SDHCI_USE_ADMA))
935 sdhci_adma_table_post(host, data);
d129bceb
PO		 936
937 /*
c9b74c5b
PO		 938 * The specification states that the block count register must
939 * be updated, but it does not specify at what point in the
940 * data flow. That makes the register entirely useless to read
941 * back so we have to assume that nothing made it to the card
942 * in the event of an error.
d129bceb 943 */
c9b74c5b
PO		 944 if (data->error)
945 data->bytes_xfered = 0;
d129bceb 946 else
c9b74c5b 947 data->bytes_xfered = data->blksz * data->blocks;
d129bceb 948
e89d456f
AW		 949 /*
950 * Need to send CMD12 if -
951 * a) open-ended multiblock transfer (no CMD23)
952 * b) error in multiblock transfer
953 */
954 if (data->stop &&
955 (data->error ||
956 !host->mrq->sbc)) {
957
d129bceb
PO		 958 /*
959 * The controller needs a reset of internal state machines
960 * upon error conditions.
961 */
17b0429d 962 if (data->error) {
03231f9b
RK		 963 sdhci_do_reset(host, SDHCI_RESET_CMD);
964 sdhci_do_reset(host, SDHCI_RESET_DATA);
d129bceb
PO		 965 }
966
967 sdhci_send_command(host, data->stop);
968 } else
969 tasklet_schedule(&host->finish_tasklet);
970}
971
c0e55129 972void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
d129bceb
PO		 973{
974 int flags;
fd2208d7 975 u32 mask;
7cb2c76f 976 unsigned long timeout;
d129bceb
PO		 977
978 WARN_ON(host->cmd);
979
96776200
RK		 980 /* Initially, a command has no error */
981 cmd->error = 0;
982
d129bceb 983 /* Wait max 10 ms */
7cb2c76f 984 timeout = 10;
fd2208d7
PO		 985
986 mask = SDHCI_CMD_INHIBIT;
987 if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
988 mask |= SDHCI_DATA_INHIBIT;
989
990 /* We shouldn't wait for data inihibit for stop commands, even
991 though they might use busy signaling */
992 if (host->mrq->data && (cmd == host->mrq->data->stop))
993 mask &= ~SDHCI_DATA_INHIBIT;
994
4e4141a5 995 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
7cb2c76f 996 if (timeout == 0) {
2e4456f0
MV		 997 pr_err("%s: Controller never released inhibit bit(s).\n",
998 mmc_hostname(host->mmc));
d129bceb 999 sdhci_dumpregs(host);
17b0429d 1000 cmd->error = -EIO;
d129bceb
PO		 1001 tasklet_schedule(&host->finish_tasklet);
1002 return;
1003 }
7cb2c76f
PO		 1004 timeout--;
1005 mdelay(1);
1006 }
d129bceb 1007
3e1a6892 1008 timeout = jiffies;
1d4d7744
UH		 1009 if (!cmd->data && cmd->busy_timeout > 9000)
1010 timeout += DIV_ROUND_UP(cmd->busy_timeout, 1000) * HZ + HZ;
3e1a6892
AH		 1011 else
1012 timeout += 10 * HZ;
1013 mod_timer(&host->timer, timeout);
d129bceb
PO		 1014
1015 host->cmd = cmd;
e99783a4 1016 host->busy_handle = 0;
d129bceb 1017
a3c7778f 1018 sdhci_prepare_data(host, cmd);
d129bceb 1019
4e4141a5 1020 sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT);
d129bceb 1021
e89d456f 1022 sdhci_set_transfer_mode(host, cmd);
c7fa9963 1023
d129bceb 1024 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
a3c76eb9 1025 pr_err("%s: Unsupported response type!\n",
d129bceb 1026 mmc_hostname(host->mmc));
17b0429d 1027 cmd->error = -EINVAL;
d129bceb
PO		 1028 tasklet_schedule(&host->finish_tasklet);
1029 return;
1030 }
1031
1032 if (!(cmd->flags & MMC_RSP_PRESENT))
1033 flags = SDHCI_CMD_RESP_NONE;
1034 else if (cmd->flags & MMC_RSP_136)
1035 flags = SDHCI_CMD_RESP_LONG;
1036 else if (cmd->flags & MMC_RSP_BUSY)
1037 flags = SDHCI_CMD_RESP_SHORT_BUSY;
1038 else
1039 flags = SDHCI_CMD_RESP_SHORT;
1040
1041 if (cmd->flags & MMC_RSP_CRC)
1042 flags |= SDHCI_CMD_CRC;
1043 if (cmd->flags & MMC_RSP_OPCODE)
1044 flags |= SDHCI_CMD_INDEX;
b513ea25
AN		 1045
1046 /* CMD19 is special in that the Data Present Select should be set */
069c9f14
G		 1047 if (cmd->data || cmd->opcode == MMC_SEND_TUNING_BLOCK ||
1048 cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200)
d129bceb
PO		 1049 flags |= SDHCI_CMD_DATA;
1050
4e4141a5 1051 sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND);
d129bceb 1052}
c0e55129 1053EXPORT_SYMBOL_GPL(sdhci_send_command);
d129bceb
PO		 1054
1055static void sdhci_finish_command(struct sdhci_host *host)
1056{
1057 int i;
1058
d129bceb
PO		 1059 if (host->cmd->flags & MMC_RSP_PRESENT) {
1060 if (host->cmd->flags & MMC_RSP_136) {
1061 /* CRC is stripped so we need to do some shifting. */
1062 for (i = 0;i < 4;i++) {
4e4141a5 1063 host->cmd->resp[i] = sdhci_readl(host,
d129bceb
PO		 1064 SDHCI_RESPONSE + (3-i)*4) << 8;
1065 if (i != 3)
1066 host->cmd->resp[i] |=
4e4141a5 1067 sdhci_readb(host,
d129bceb
PO		 1068 SDHCI_RESPONSE + (3-i)*4-1);
1069 }
1070 } else {
4e4141a5 1071 host->cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE);
d129bceb
PO		 1072 }
1073 }
1074
6bde8681
AH		 1075 /*
1076 * The host can send and interrupt when the busy state has
1077 * ended, allowing us to wait without wasting CPU cycles.
1078 * The busy signal uses DAT0 so this is similar to waiting
1079 * for data to complete.
1080 *
1081 * Note: The 1.0 specification is a bit ambiguous about this
1082 * feature so there might be some problems with older
1083 * controllers.
1084 */
1085 if (host->cmd->flags & MMC_RSP_BUSY) {
1086 if (host->cmd->data) {
1087 DBG("Cannot wait for busy signal when also doing a data transfer");
1088 } else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ) &&
1089 !host->busy_handle) {
1090 /* Mark that command complete before busy is ended */
1091 host->busy_handle = 1;
1092 host->cmd = NULL;
1093 return;
1094 }
1095 }
1096
e89d456f
AW		 1097 /* Finished CMD23, now send actual command. */
1098 if (host->cmd == host->mrq->sbc) {
1099 host->cmd = NULL;
1100 sdhci_send_command(host, host->mrq->cmd);
1101 } else {
e538fbe8 1102
e89d456f
AW		 1103 /* Processed actual command. */
1104 if (host->data && host->data_early)
1105 sdhci_finish_data(host);
d129bceb 1106
e89d456f
AW		 1107 if (!host->cmd->data)
1108 tasklet_schedule(&host->finish_tasklet);
1109
1110 host->cmd = NULL;
1111 }
d129bceb
PO		 1112}
1113
52983382
KL		 1114static u16 sdhci_get_preset_value(struct sdhci_host *host)
1115{
d975f121 1116 u16 preset = 0;
52983382 1117
d975f121
RK		 1118 switch (host->timing) {
1119 case MMC_TIMING_UHS_SDR12:
52983382
KL		 1120 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1121 break;
d975f121 1122 case MMC_TIMING_UHS_SDR25:
52983382
KL		 1123 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR25);
1124 break;
d975f121 1125 case MMC_TIMING_UHS_SDR50:
52983382
KL		 1126 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR50);
1127 break;
d975f121
RK		 1128 case MMC_TIMING_UHS_SDR104:
1129 case MMC_TIMING_MMC_HS200:
52983382
KL		 1130 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR104);
1131 break;
d975f121 1132 case MMC_TIMING_UHS_DDR50:
0dafa60e 1133 case MMC_TIMING_MMC_DDR52:
52983382
KL		 1134 preset = sdhci_readw(host, SDHCI_PRESET_FOR_DDR50);
1135 break;
e9fb05d5
AH		 1136 case MMC_TIMING_MMC_HS400:
1137 preset = sdhci_readw(host, SDHCI_PRESET_FOR_HS400);
1138 break;
52983382
KL		 1139 default:
1140 pr_warn("%s: Invalid UHS-I mode selected\n",
1141 mmc_hostname(host->mmc));
1142 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1143 break;
1144 }
1145 return preset;
1146}
1147
fb9ee047
LD		 1148u16 sdhci_calc_clk(struct sdhci_host *host, unsigned int clock,
1149 unsigned int *actual_clock)
d129bceb 1150{
c3ed3877 1151 int div = 0; /* Initialized for compiler warning */
df16219f 1152 int real_div = div, clk_mul = 1;
c3ed3877 1153 u16 clk = 0;
5497159c 1154 bool switch_base_clk = false;
d129bceb 1155
85105c53 1156 if (host->version >= SDHCI_SPEC_300) {
da91a8f9 1157 if (host->preset_enabled) {
52983382
KL		 1158 u16 pre_val;
1159
1160 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1161 pre_val = sdhci_get_preset_value(host);
1162 div = (pre_val & SDHCI_PRESET_SDCLK_FREQ_MASK)
1163 >> SDHCI_PRESET_SDCLK_FREQ_SHIFT;
1164 if (host->clk_mul &&
1165 (pre_val & SDHCI_PRESET_CLKGEN_SEL_MASK)) {
1166 clk = SDHCI_PROG_CLOCK_MODE;
1167 real_div = div + 1;
1168 clk_mul = host->clk_mul;
1169 } else {
1170 real_div = max_t(int, 1, div << 1);
1171 }
1172 goto clock_set;
1173 }
1174
c3ed3877
AN		 1175 /*
1176 * Check if the Host Controller supports Programmable Clock
1177 * Mode.
1178 */
1179 if (host->clk_mul) {
52983382
KL		 1180 for (div = 1; div <= 1024; div++) {
1181 if ((host->max_clk * host->clk_mul / div)
1182 <= clock)
1183 break;
1184 }
5497159c 1185 if ((host->max_clk * host->clk_mul / div) <= clock) {
1186 /*
1187 * Set Programmable Clock Mode in the Clock
1188 * Control register.
1189 */
1190 clk = SDHCI_PROG_CLOCK_MODE;
1191 real_div = div;
1192 clk_mul = host->clk_mul;
1193 div--;
1194 } else {
1195 /*
1196 * Divisor can be too small to reach clock
1197 * speed requirement. Then use the base clock.
1198 */
1199 switch_base_clk = true;
1200 }
1201 }
1202
1203 if (!host->clk_mul || switch_base_clk) {
c3ed3877
AN		 1204 /* Version 3.00 divisors must be a multiple of 2. */
1205 if (host->max_clk <= clock)
1206 div = 1;
1207 else {
1208 for (div = 2; div < SDHCI_MAX_DIV_SPEC_300;
1209 div += 2) {
1210 if ((host->max_clk / div) <= clock)
1211 break;
1212 }
85105c53 1213 }
df16219f 1214 real_div = div;
c3ed3877 1215 div >>= 1;
d1955c3a
SG		 1216 if ((host->quirks2 & SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN)
1217 && !div && host->max_clk <= 25000000)
1218 div = 1;
85105c53
ZG		 1219 }
1220 } else {
1221 /* Version 2.00 divisors must be a power of 2. */
0397526d 1222 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
85105c53
ZG		 1223 if ((host->max_clk / div) <= clock)
1224 break;
1225 }
df16219f 1226 real_div = div;
c3ed3877 1227 div >>= 1;
d129bceb 1228 }
d129bceb 1229
52983382 1230clock_set:
03d6f5ff 1231 if (real_div)
fb9ee047 1232 *actual_clock = (host->max_clk * clk_mul) / real_div;
c3ed3877 1233 clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
85105c53
ZG		 1234 clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
1235 << SDHCI_DIVIDER_HI_SHIFT;
fb9ee047
LD		 1236
1237 return clk;
1238}
1239EXPORT_SYMBOL_GPL(sdhci_calc_clk);
1240
1241void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
1242{
1243 u16 clk;
1244 unsigned long timeout;
1245
1246 host->mmc->actual_clock = 0;
1247
1248 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
fb9ee047
LD		 1249
1250 if (clock == 0)
1251 return;
1252
1253 clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock);
1254
d129bceb 1255 clk |= SDHCI_CLOCK_INT_EN;
4e4141a5 1256 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
d129bceb 1257
27f6cb16
CB		 1258 /* Wait max 20 ms */
1259 timeout = 20;
4e4141a5 1260 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
7cb2c76f
PO		 1261 & SDHCI_CLOCK_INT_STABLE)) {
1262 if (timeout == 0) {
2e4456f0
MV		 1263 pr_err("%s: Internal clock never stabilised.\n",
1264 mmc_hostname(host->mmc));
d129bceb
PO		 1265 sdhci_dumpregs(host);
1266 return;
1267 }
7cb2c76f
PO		 1268 timeout--;
1269 mdelay(1);
1270 }
d129bceb
PO		 1271
1272 clk |= SDHCI_CLOCK_CARD_EN;
4e4141a5 1273 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
d129bceb 1274}
1771059c 1275EXPORT_SYMBOL_GPL(sdhci_set_clock);
d129bceb 1276
1dceb041
AH		 1277static void sdhci_set_power_reg(struct sdhci_host *host, unsigned char mode,
1278 unsigned short vdd)
146ad66e 1279{
3a48edc4 1280 struct mmc_host *mmc = host->mmc;
1dceb041
AH		 1281
1282 spin_unlock_irq(&host->lock);
1283 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd);
1284 spin_lock_irq(&host->lock);
1285
1286 if (mode != MMC_POWER_OFF)
1287 sdhci_writeb(host, SDHCI_POWER_ON, SDHCI_POWER_CONTROL);
1288 else
1289 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1290}
1291
1292void sdhci_set_power(struct sdhci_host *host, unsigned char mode,
1293 unsigned short vdd)
1294{
8364248a 1295 u8 pwr = 0;
146ad66e 1296
24fbb3ca
RK		 1297 if (mode != MMC_POWER_OFF) {
1298 switch (1 << vdd) {
ae628903
PO		 1299 case MMC_VDD_165_195:
1300 pwr = SDHCI_POWER_180;
1301 break;
1302 case MMC_VDD_29_30:
1303 case MMC_VDD_30_31:
1304 pwr = SDHCI_POWER_300;
1305 break;
1306 case MMC_VDD_32_33:
1307 case MMC_VDD_33_34:
1308 pwr = SDHCI_POWER_330;
1309 break;
1310 default:
9d5de93f
AH		 1311 WARN(1, "%s: Invalid vdd %#x\n",
1312 mmc_hostname(host->mmc), vdd);
1313 break;
ae628903
PO		 1314 }
1315 }
1316
1317 if (host->pwr == pwr)
e921a8b6 1318 return;
146ad66e 1319
ae628903
PO		 1320 host->pwr = pwr;
1321
1322 if (pwr == 0) {
4e4141a5 1323 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
f0710a55
AH		 1324 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
1325 sdhci_runtime_pm_bus_off(host);
e921a8b6
RK		 1326 } else {
1327 /*
1328 * Spec says that we should clear the power reg before setting
1329 * a new value. Some controllers don't seem to like this though.
1330 */
1331 if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
1332 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
146ad66e 1333
e921a8b6
RK		 1334 /*
1335 * At least the Marvell CaFe chip gets confused if we set the
1336 * voltage and set turn on power at the same time, so set the
1337 * voltage first.
1338 */
1339 if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
1340 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
e08c1694 1341
e921a8b6 1342 pwr |= SDHCI_POWER_ON;
146ad66e 1343
e921a8b6 1344 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
557b0697 1345
e921a8b6
RK		 1346 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
1347 sdhci_runtime_pm_bus_on(host);
f0710a55 1348
e921a8b6
RK		 1349 /*
1350 * Some controllers need an extra 10ms delay of 10ms before
1351 * they can apply clock after applying power
1352 */
1353 if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER)
1354 mdelay(10);
1355 }
1dceb041
AH		 1356}
1357EXPORT_SYMBOL_GPL(sdhci_set_power);
918f4cbd 1358
1dceb041
AH		 1359static void __sdhci_set_power(struct sdhci_host *host, unsigned char mode,
1360 unsigned short vdd)
1361{
1362 struct mmc_host *mmc = host->mmc;
1363
1364 if (host->ops->set_power)
1365 host->ops->set_power(host, mode, vdd);
1366 else if (!IS_ERR(mmc->supply.vmmc))
1367 sdhci_set_power_reg(host, mode, vdd);
1368 else
1369 sdhci_set_power(host, mode, vdd);
146ad66e
PO		 1370}
1371
d129bceb
PO		 1372/*****************************************************************************\
1373 * *
1374 * MMC callbacks *
1375 * *
1376\*****************************************************************************/
1377
1378static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1379{
1380 struct sdhci_host *host;
505a8680 1381 int present;
d129bceb
PO		 1382 unsigned long flags;
1383
1384 host = mmc_priv(mmc);
1385
04e079cf 1386 /* Firstly check card presence */
8d28b7a7 1387 present = mmc->ops->get_cd(mmc);
2836766a 1388
d129bceb
PO		 1389 spin_lock_irqsave(&host->lock, flags);
1390
1391 WARN_ON(host->mrq != NULL);
1392
061d17a6 1393 sdhci_led_activate(host);
e89d456f
AW		 1394
1395 /*
1396 * Ensure we don't send the STOP for non-SET_BLOCK_COUNTED
1397 * requests if Auto-CMD12 is enabled.
1398 */
1399 if (!mrq->sbc && (host->flags & SDHCI_AUTO_CMD12)) {
c4512f79
JH		 1400 if (mrq->stop) {
1401 mrq->data->stop = NULL;
1402 mrq->stop = NULL;
1403 }
1404 }
d129bceb
PO		 1405
1406 host->mrq = mrq;
1407
68d1fb7e 1408 if (!present || host->flags & SDHCI_DEVICE_DEAD) {
17b0429d 1409 host->mrq->cmd->error = -ENOMEDIUM;
d129bceb 1410 tasklet_schedule(&host->finish_tasklet);
cf2b5eea 1411 } else {
8edf6371 1412 if (mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23))
e89d456f
AW		 1413 sdhci_send_command(host, mrq->sbc);
1414 else
1415 sdhci_send_command(host, mrq->cmd);
cf2b5eea 1416 }
d129bceb 1417
5f25a66f 1418 mmiowb();
d129bceb
PO		 1419 spin_unlock_irqrestore(&host->lock, flags);
1420}
1421
2317f56c
RK		 1422void sdhci_set_bus_width(struct sdhci_host *host, int width)
1423{
1424 u8 ctrl;
1425
1426 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1427 if (width == MMC_BUS_WIDTH_8) {
1428 ctrl &= ~SDHCI_CTRL_4BITBUS;
1429 if (host->version >= SDHCI_SPEC_300)
1430 ctrl |= SDHCI_CTRL_8BITBUS;
1431 } else {
1432 if (host->version >= SDHCI_SPEC_300)
1433 ctrl &= ~SDHCI_CTRL_8BITBUS;
1434 if (width == MMC_BUS_WIDTH_4)
1435 ctrl |= SDHCI_CTRL_4BITBUS;
1436 else
1437 ctrl &= ~SDHCI_CTRL_4BITBUS;
1438 }
1439 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1440}
1441EXPORT_SYMBOL_GPL(sdhci_set_bus_width);
1442
96d7b78c
RK		 1443void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing)
1444{
1445 u16 ctrl_2;
1446
1447 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1448 /* Select Bus Speed Mode for host */
1449 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
1450 if ((timing == MMC_TIMING_MMC_HS200) ||
1451 (timing == MMC_TIMING_UHS_SDR104))
1452 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
1453 else if (timing == MMC_TIMING_UHS_SDR12)
1454 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
1455 else if (timing == MMC_TIMING_UHS_SDR25)
1456 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
1457 else if (timing == MMC_TIMING_UHS_SDR50)
1458 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
1459 else if ((timing == MMC_TIMING_UHS_DDR50) ||
1460 (timing == MMC_TIMING_MMC_DDR52))
1461 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
e9fb05d5
AH		 1462 else if (timing == MMC_TIMING_MMC_HS400)
1463 ctrl_2 |= SDHCI_CTRL_HS400; /* Non-standard */
96d7b78c
RK		 1464 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1465}
1466EXPORT_SYMBOL_GPL(sdhci_set_uhs_signaling);
1467
ded97e0b 1468static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
d129bceb 1469{
ded97e0b 1470 struct sdhci_host *host = mmc_priv(mmc);
d129bceb
PO		 1471 unsigned long flags;
1472 u8 ctrl;
1473
d129bceb
PO		 1474 spin_lock_irqsave(&host->lock, flags);
1475
ceb6143b
AH		 1476 if (host->flags & SDHCI_DEVICE_DEAD) {
1477 spin_unlock_irqrestore(&host->lock, flags);
3a48edc4
TK		 1478 if (!IS_ERR(mmc->supply.vmmc) &&
1479 ios->power_mode == MMC_POWER_OFF)
4e743f1f 1480 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
ceb6143b
AH		 1481 return;
1482 }
1e72859e 1483
d129bceb
PO		 1484 /*
1485 * Reset the chip on each power off.
1486 * Should clear out any weird states.
1487 */
1488 if (ios->power_mode == MMC_POWER_OFF) {
4e4141a5 1489 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
7260cf5e 1490 sdhci_reinit(host);
d129bceb
PO		 1491 }
1492
52983382 1493 if (host->version >= SDHCI_SPEC_300 &&
372c4634
DA		 1494 (ios->power_mode == MMC_POWER_UP) &&
1495 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN))
52983382
KL		 1496 sdhci_enable_preset_value(host, false);
1497
373073ef 1498 if (!ios->clock || ios->clock != host->clock) {
1771059c 1499 host->ops->set_clock(host, ios->clock);
373073ef 1500 host->clock = ios->clock;
03d6f5ff
AD		 1501
1502 if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK &&
1503 host->clock) {
1504 host->timeout_clk = host->mmc->actual_clock ?
1505 host->mmc->actual_clock / 1000 :
1506 host->clock / 1000;
1507 host->mmc->max_busy_timeout =
1508 host->ops->get_max_timeout_count ?
1509 host->ops->get_max_timeout_count(host) :
1510 1 << 27;
1511 host->mmc->max_busy_timeout /= host->timeout_clk;
1512 }
373073ef 1513 }
d129bceb 1514
1dceb041 1515 __sdhci_set_power(host, ios->power_mode, ios->vdd);
d129bceb 1516
643a81ff
PR		 1517 if (host->ops->platform_send_init_74_clocks)
1518 host->ops->platform_send_init_74_clocks(host, ios->power_mode);
1519
2317f56c 1520 host->ops->set_bus_width(host, ios->bus_width);
ae6d6c92 1521
15ec4461 1522 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
cd9277c0 1523
3ab9c8da
PR		 1524 if ((ios->timing == MMC_TIMING_SD_HS ||
1525 ios->timing == MMC_TIMING_MMC_HS)
1526 && !(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT))
cd9277c0
PO		 1527 ctrl |= SDHCI_CTRL_HISPD;
1528 else
1529 ctrl &= ~SDHCI_CTRL_HISPD;
1530
d6d50a15 1531 if (host->version >= SDHCI_SPEC_300) {
49c468fc 1532 u16 clk, ctrl_2;
49c468fc
AN		 1533
1534 /* In case of UHS-I modes, set High Speed Enable */
e9fb05d5
AH		 1535 if ((ios->timing == MMC_TIMING_MMC_HS400) ||
1536 (ios->timing == MMC_TIMING_MMC_HS200) ||
bb8175a8 1537 (ios->timing == MMC_TIMING_MMC_DDR52) ||
069c9f14 1538 (ios->timing == MMC_TIMING_UHS_SDR50) ||
49c468fc
AN		 1539 (ios->timing == MMC_TIMING_UHS_SDR104) ||
1540 (ios->timing == MMC_TIMING_UHS_DDR50) ||
dd8df17f 1541 (ios->timing == MMC_TIMING_UHS_SDR25))
49c468fc 1542 ctrl |= SDHCI_CTRL_HISPD;
d6d50a15 1543
da91a8f9 1544 if (!host->preset_enabled) {
758535c4 1545 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d6d50a15
AN		 1546 /*
1547 * We only need to set Driver Strength if the
1548 * preset value enable is not set.
1549 */
da91a8f9 1550 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
d6d50a15
AN		 1551 ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK;
1552 if (ios->drv_type == MMC_SET_DRIVER_TYPE_A)
1553 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A;
43e943a0
PG		 1554 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_B)
1555 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_B;
d6d50a15
AN		 1556 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C)
1557 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C;
43e943a0
PG		 1558 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_D)
1559 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_D;
1560 else {
2e4456f0
MV		 1561 pr_warn("%s: invalid driver type, default to driver type B\n",
1562 mmc_hostname(mmc));
43e943a0
PG		 1563 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_B;
1564 }
d6d50a15
AN		 1565
1566 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
758535c4
AN		 1567 } else {
1568 /*
1569 * According to SDHC Spec v3.00, if the Preset Value
1570 * Enable in the Host Control 2 register is set, we
1571 * need to reset SD Clock Enable before changing High
1572 * Speed Enable to avoid generating clock gliches.
1573 */
758535c4
AN		 1574
1575 /* Reset SD Clock Enable */
1576 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1577 clk &= ~SDHCI_CLOCK_CARD_EN;
1578 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1579
1580 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1581
1582 /* Re-enable SD Clock */
1771059c 1583 host->ops->set_clock(host, host->clock);
d6d50a15 1584 }
49c468fc 1585
49c468fc
AN		 1586 /* Reset SD Clock Enable */
1587 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1588 clk &= ~SDHCI_CLOCK_CARD_EN;
1589 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1590
96d7b78c 1591 host->ops->set_uhs_signaling(host, ios->timing);
d975f121 1592 host->timing = ios->timing;
49c468fc 1593
52983382
KL		 1594 if (!(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN) &&
1595 ((ios->timing == MMC_TIMING_UHS_SDR12) ||
1596 (ios->timing == MMC_TIMING_UHS_SDR25) ||
1597 (ios->timing == MMC_TIMING_UHS_SDR50) ||
1598 (ios->timing == MMC_TIMING_UHS_SDR104) ||
0dafa60e
JZ		 1599 (ios->timing == MMC_TIMING_UHS_DDR50) ||
1600 (ios->timing == MMC_TIMING_MMC_DDR52))) {
52983382
KL		 1601 u16 preset;
1602
1603 sdhci_enable_preset_value(host, true);
1604 preset = sdhci_get_preset_value(host);
1605 ios->drv_type = (preset & SDHCI_PRESET_DRV_MASK)
1606 >> SDHCI_PRESET_DRV_SHIFT;
1607 }
1608
49c468fc 1609 /* Re-enable SD Clock */
1771059c 1610 host->ops->set_clock(host, host->clock);
758535c4
AN		 1611 } else
1612 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d6d50a15 1613
b8352260
LD		 1614 /*
1615 * Some (ENE) controllers go apeshit on some ios operation,
1616 * signalling timeout and CRC errors even on CMD0. Resetting
1617 * it on each ios seems to solve the problem.
1618 */
c63705e1 1619 if (host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
03231f9b 1620 sdhci_do_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
b8352260 1621
5f25a66f 1622 mmiowb();
d129bceb
PO		 1623 spin_unlock_irqrestore(&host->lock, flags);
1624}
1625
ded97e0b 1626static int sdhci_get_cd(struct mmc_host *mmc)
66fd8ad5
AH		 1627{
1628 struct sdhci_host *host = mmc_priv(mmc);
ded97e0b 1629 int gpio_cd = mmc_gpio_get_cd(mmc);
94144a46
KL		 1630
1631 if (host->flags & SDHCI_DEVICE_DEAD)
1632 return 0;
1633
88af5655 1634 /* If nonremovable, assume that the card is always present. */
860951c5 1635 if (!mmc_card_is_removable(host->mmc))
94144a46
KL		 1636 return 1;
1637
88af5655
II		 1638 /*
1639 * Try slot gpio detect, if defined it take precedence
1640 * over build in controller functionality
1641 */
287980e4 1642 if (gpio_cd >= 0)
94144a46
KL		 1643 return !!gpio_cd;
1644
88af5655
II		 1645 /* If polling, assume that the card is always present. */
1646 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
1647 return 1;
1648
94144a46
KL		 1649 /* Host native card detect */
1650 return !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
1651}
1652
66fd8ad5 1653static int sdhci_check_ro(struct sdhci_host *host)
d129bceb 1654{
d129bceb 1655 unsigned long flags;
2dfb579c 1656 int is_readonly;
d129bceb 1657
d129bceb
PO		 1658 spin_lock_irqsave(&host->lock, flags);
1659
1e72859e 1660 if (host->flags & SDHCI_DEVICE_DEAD)
2dfb579c
WS		 1661 is_readonly = 0;
1662 else if (host->ops->get_ro)
1663 is_readonly = host->ops->get_ro(host);
1e72859e 1664 else
2dfb579c
WS		 1665 is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE)
1666 & SDHCI_WRITE_PROTECT);
d129bceb
PO		 1667
1668 spin_unlock_irqrestore(&host->lock, flags);
1669
2dfb579c
WS		 1670 /* This quirk needs to be replaced by a callback-function later */
1671 return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ?
1672 !is_readonly : is_readonly;
d129bceb
PO		 1673}
1674
82b0e23a
TI		 1675#define SAMPLE_COUNT 5
1676
ded97e0b 1677static int sdhci_get_ro(struct mmc_host *mmc)
82b0e23a 1678{
ded97e0b 1679 struct sdhci_host *host = mmc_priv(mmc);
82b0e23a
TI		 1680 int i, ro_count;
1681
82b0e23a 1682 if (!(host->quirks & SDHCI_QUIRK_UNSTABLE_RO_DETECT))
66fd8ad5 1683 return sdhci_check_ro(host);
82b0e23a
TI		 1684
1685 ro_count = 0;
1686 for (i = 0; i < SAMPLE_COUNT; i++) {
66fd8ad5 1687 if (sdhci_check_ro(host)) {
82b0e23a
TI		 1688 if (++ro_count > SAMPLE_COUNT / 2)
1689 return 1;
1690 }
1691 msleep(30);
1692 }
1693 return 0;
1694}
1695
20758b66
AH		 1696static void sdhci_hw_reset(struct mmc_host *mmc)
1697{
1698 struct sdhci_host *host = mmc_priv(mmc);
1699
1700 if (host->ops && host->ops->hw_reset)
1701 host->ops->hw_reset(host);
1702}
1703
66fd8ad5
AH		 1704static void sdhci_enable_sdio_irq_nolock(struct sdhci_host *host, int enable)
1705{
be138554 1706 if (!(host->flags & SDHCI_DEVICE_DEAD)) {
ef104333 1707 if (enable)
b537f94c 1708 host->ier |= SDHCI_INT_CARD_INT;
ef104333 1709 else
b537f94c
RK		 1710 host->ier &= ~SDHCI_INT_CARD_INT;
1711
1712 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
1713 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
ef104333
RK		 1714 mmiowb();
1715 }
66fd8ad5
AH		 1716}
1717
1718static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1719{
1720 struct sdhci_host *host = mmc_priv(mmc);
1721 unsigned long flags;
f75979b7 1722
66fd8ad5 1723 spin_lock_irqsave(&host->lock, flags);
ef104333
RK		 1724 if (enable)
1725 host->flags |= SDHCI_SDIO_IRQ_ENABLED;
1726 else
1727 host->flags &= ~SDHCI_SDIO_IRQ_ENABLED;
1728
66fd8ad5 1729 sdhci_enable_sdio_irq_nolock(host, enable);
f75979b7
PO		 1730 spin_unlock_irqrestore(&host->lock, flags);
1731}
1732
ded97e0b
DA		 1733static int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
1734 struct mmc_ios *ios)
f2119df6 1735{
ded97e0b 1736 struct sdhci_host *host = mmc_priv(mmc);
20b92a30 1737 u16 ctrl;
6231f3de 1738 int ret;
f2119df6 1739
20b92a30
KL		 1740 /*
1741 * Signal Voltage Switching is only applicable for Host Controllers
1742 * v3.00 and above.
1743 */
1744 if (host->version < SDHCI_SPEC_300)
1745 return 0;
6231f3de 1746
f2119df6 1747 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
f2119df6 1748
21f5998f 1749 switch (ios->signal_voltage) {
20b92a30 1750 case MMC_SIGNAL_VOLTAGE_330:
8cb851a4
AH		 1751 if (!(host->flags & SDHCI_SIGNALING_330))
1752 return -EINVAL;
20b92a30
KL		 1753 /* Set 1.8V Signal Enable in the Host Control2 register to 0 */
1754 ctrl &= ~SDHCI_CTRL_VDD_180;
1755 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
f2119df6 1756
3a48edc4
TK		 1757 if (!IS_ERR(mmc->supply.vqmmc)) {
1758 ret = regulator_set_voltage(mmc->supply.vqmmc, 2700000,
1759 3600000);
20b92a30 1760 if (ret) {
6606110d
JP		 1761 pr_warn("%s: Switching to 3.3V signalling voltage failed\n",
1762 mmc_hostname(mmc));
20b92a30
KL		 1763 return -EIO;
1764 }
1765 }
1766 /* Wait for 5ms */
1767 usleep_range(5000, 5500);
f2119df6 1768
20b92a30
KL		 1769 /* 3.3V regulator output should be stable within 5 ms */
1770 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1771 if (!(ctrl & SDHCI_CTRL_VDD_180))
1772 return 0;
6231f3de 1773
6606110d
JP		 1774 pr_warn("%s: 3.3V regulator output did not became stable\n",
1775 mmc_hostname(mmc));
20b92a30
KL		 1776
1777 return -EAGAIN;
1778 case MMC_SIGNAL_VOLTAGE_180:
8cb851a4
AH		 1779 if (!(host->flags & SDHCI_SIGNALING_180))
1780 return -EINVAL;
3a48edc4
TK		 1781 if (!IS_ERR(mmc->supply.vqmmc)) {
1782 ret = regulator_set_voltage(mmc->supply.vqmmc,
20b92a30
KL		 1783 1700000, 1950000);
1784 if (ret) {
6606110d
JP		 1785 pr_warn("%s: Switching to 1.8V signalling voltage failed\n",
1786 mmc_hostname(mmc));
20b92a30
KL		 1787 return -EIO;
1788 }
1789 }
6231f3de 1790
6231f3de
PR		 1791 /*
1792 * Enable 1.8V Signal Enable in the Host Control2
1793 * register
1794 */
20b92a30
KL		 1795 ctrl |= SDHCI_CTRL_VDD_180;
1796 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
6231f3de 1797
9d967a61
VY		 1798 /* Some controller need to do more when switching */
1799 if (host->ops->voltage_switch)
1800 host->ops->voltage_switch(host);
1801
20b92a30
KL		 1802 /* 1.8V regulator output should be stable within 5 ms */
1803 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1804 if (ctrl & SDHCI_CTRL_VDD_180)
1805 return 0;
f2119df6 1806
6606110d
JP		 1807 pr_warn("%s: 1.8V regulator output did not became stable\n",
1808 mmc_hostname(mmc));
f2119df6 1809
20b92a30
KL		 1810 return -EAGAIN;
1811 case MMC_SIGNAL_VOLTAGE_120:
8cb851a4
AH		 1812 if (!(host->flags & SDHCI_SIGNALING_120))
1813 return -EINVAL;
3a48edc4
TK		 1814 if (!IS_ERR(mmc->supply.vqmmc)) {
1815 ret = regulator_set_voltage(mmc->supply.vqmmc, 1100000,
1816 1300000);
20b92a30 1817 if (ret) {
6606110d
JP		 1818 pr_warn("%s: Switching to 1.2V signalling voltage failed\n",
1819 mmc_hostname(mmc));
20b92a30 1820 return -EIO;
f2119df6
AN		 1821 }
1822 }
6231f3de 1823 return 0;
20b92a30 1824 default:
f2119df6
AN		 1825 /* No signal voltage switch required */
1826 return 0;
20b92a30 1827 }
f2119df6
AN		 1828}
1829
20b92a30
KL		 1830static int sdhci_card_busy(struct mmc_host *mmc)
1831{
1832 struct sdhci_host *host = mmc_priv(mmc);
1833 u32 present_state;
1834
e613cc47 1835 /* Check whether DAT[0] is 0 */
20b92a30 1836 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
20b92a30 1837
e613cc47 1838 return !(present_state & SDHCI_DATA_0_LVL_MASK);
20b92a30
KL		 1839}
1840
b5540ce1
AH		 1841static int sdhci_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios)
1842{
1843 struct sdhci_host *host = mmc_priv(mmc);
1844 unsigned long flags;
1845
1846 spin_lock_irqsave(&host->lock, flags);
1847 host->flags |= SDHCI_HS400_TUNING;
1848 spin_unlock_irqrestore(&host->lock, flags);
1849
1850 return 0;
1851}
1852
069c9f14 1853static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode)
b513ea25 1854{
4b6f37d3 1855 struct sdhci_host *host = mmc_priv(mmc);
b513ea25 1856 u16 ctrl;
b513ea25 1857 int tuning_loop_counter = MAX_TUNING_LOOP;
b513ea25 1858 int err = 0;
2b35bd83 1859 unsigned long flags;
38e40bf5 1860 unsigned int tuning_count = 0;
b5540ce1 1861 bool hs400_tuning;
b513ea25 1862
2b35bd83 1863 spin_lock_irqsave(&host->lock, flags);
b513ea25 1864
b5540ce1
AH		 1865 hs400_tuning = host->flags & SDHCI_HS400_TUNING;
1866 host->flags &= ~SDHCI_HS400_TUNING;
1867
38e40bf5
AH		 1868 if (host->tuning_mode == SDHCI_TUNING_MODE_1)
1869 tuning_count = host->tuning_count;
1870
b513ea25 1871 /*
9faac7b9
WY		 1872 * The Host Controller needs tuning in case of SDR104 and DDR50
1873 * mode, and for SDR50 mode when Use Tuning for SDR50 is set in
1874 * the Capabilities register.
069c9f14
G		 1875 * If the Host Controller supports the HS200 mode then the
1876 * tuning function has to be executed.
b513ea25 1877 */
4b6f37d3 1878 switch (host->timing) {
b5540ce1 1879 /* HS400 tuning is done in HS200 mode */
e9fb05d5 1880 case MMC_TIMING_MMC_HS400:
b5540ce1
AH		 1881 err = -EINVAL;
1882 goto out_unlock;
1883
4b6f37d3 1884 case MMC_TIMING_MMC_HS200:
b5540ce1
AH		 1885 /*
1886 * Periodic re-tuning for HS400 is not expected to be needed, so
1887 * disable it here.
1888 */
1889 if (hs400_tuning)
1890 tuning_count = 0;
1891 break;
1892
4b6f37d3 1893 case MMC_TIMING_UHS_SDR104:
9faac7b9 1894 case MMC_TIMING_UHS_DDR50:
4b6f37d3
RK		 1895 break;
1896
1897 case MMC_TIMING_UHS_SDR50:
4228b213 1898 if (host->flags & SDHCI_SDR50_NEEDS_TUNING)
4b6f37d3
RK		 1899 break;
1900 /* FALLTHROUGH */
1901
1902 default:
d519c863 1903 goto out_unlock;
b513ea25
AN		 1904 }
1905
45251812 1906 if (host->ops->platform_execute_tuning) {
2b35bd83 1907 spin_unlock_irqrestore(&host->lock, flags);
45251812 1908 err = host->ops->platform_execute_tuning(host, opcode);
45251812
DA		 1909 return err;
1910 }
1911
4b6f37d3
RK		 1912 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1913 ctrl |= SDHCI_CTRL_EXEC_TUNING;
67d0d04a
VY		 1914 if (host->quirks2 & SDHCI_QUIRK2_TUNING_WORK_AROUND)
1915 ctrl |= SDHCI_CTRL_TUNED_CLK;
b513ea25
AN		 1916 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1917
1918 /*
1919 * As per the Host Controller spec v3.00, tuning command
1920 * generates Buffer Read Ready interrupt, so enable that.
1921 *
1922 * Note: The spec clearly says that when tuning sequence
1923 * is being performed, the controller does not generate
1924 * interrupts other than Buffer Read Ready interrupt. But
1925 * to make sure we don't hit a controller bug, we _only_
1926 * enable Buffer Read Ready interrupt here.
1927 */
b537f94c
RK		 1928 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE);
1929 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE);
b513ea25
AN		 1930
1931 /*
1932 * Issue CMD19 repeatedly till Execute Tuning is set to 0 or the number
1473bdd5 1933 * of loops reaches 40 times.
b513ea25 1934 */
b513ea25
AN		 1935 do {
1936 struct mmc_command cmd = {0};
66fd8ad5 1937 struct mmc_request mrq = {NULL};
b513ea25 1938
069c9f14 1939 cmd.opcode = opcode;
b513ea25
AN		 1940 cmd.arg = 0;
1941 cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
1942 cmd.retries = 0;
1943 cmd.data = NULL;
1944 cmd.error = 0;
1945
7ce45e95
AC		 1946 if (tuning_loop_counter-- == 0)
1947 break;
1948
b513ea25
AN		 1949 mrq.cmd = &cmd;
1950 host->mrq = &mrq;
1951
1952 /*
1953 * In response to CMD19, the card sends 64 bytes of tuning
1954 * block to the Host Controller. So we set the block size
1955 * to 64 here.
1956 */
069c9f14
G		 1957 if (cmd.opcode == MMC_SEND_TUNING_BLOCK_HS200) {
1958 if (mmc->ios.bus_width == MMC_BUS_WIDTH_8)
1959 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 128),
1960 SDHCI_BLOCK_SIZE);
1961 else if (mmc->ios.bus_width == MMC_BUS_WIDTH_4)
1962 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
1963 SDHCI_BLOCK_SIZE);
1964 } else {
1965 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
1966 SDHCI_BLOCK_SIZE);
1967 }
b513ea25
AN		 1968
1969 /*
1970 * The tuning block is sent by the card to the host controller.
1971 * So we set the TRNS_READ bit in the Transfer Mode register.
1972 * This also takes care of setting DMA Enable and Multi Block
1973 * Select in the same register to 0.
1974 */
1975 sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
1976
1977 sdhci_send_command(host, &cmd);
1978
1979 host->cmd = NULL;
1980 host->mrq = NULL;
1981
2b35bd83 1982 spin_unlock_irqrestore(&host->lock, flags);
b513ea25
AN		 1983 /* Wait for Buffer Read Ready interrupt */
1984 wait_event_interruptible_timeout(host->buf_ready_int,
1985 (host->tuning_done == 1),
1986 msecs_to_jiffies(50));
2b35bd83 1987 spin_lock_irqsave(&host->lock, flags);
b513ea25
AN		 1988
1989 if (!host->tuning_done) {
2e4456f0 1990 pr_info(DRIVER_NAME ": Timeout waiting for Buffer Read Ready interrupt during tuning procedure, falling back to fixed sampling clock\n");
b513ea25
AN		 1991 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1992 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
1993 ctrl &= ~SDHCI_CTRL_EXEC_TUNING;
1994 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1995
1996 err = -EIO;
1997 goto out;
1998 }
1999
2000 host->tuning_done = 0;
2001
2002 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
197160d5
NS		 2003
2004 /* eMMC spec does not require a delay between tuning cycles */
2005 if (opcode == MMC_SEND_TUNING_BLOCK)
2006 mdelay(1);
b513ea25
AN		 2007 } while (ctrl & SDHCI_CTRL_EXEC_TUNING);
2008
2009 /*
2010 * The Host Driver has exhausted the maximum number of loops allowed,
2011 * so use fixed sampling frequency.
2012 */
7ce45e95 2013 if (tuning_loop_counter < 0) {
b513ea25
AN		 2014 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
2015 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
7ce45e95
AC		 2016 }
2017 if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) {
2e4456f0 2018 pr_info(DRIVER_NAME ": Tuning procedure failed, falling back to fixed sampling clock\n");
114f2bf6 2019 err = -EIO;
b513ea25
AN		 2020 }
2021
2022out:
38e40bf5 2023 if (tuning_count) {
66c39dfc
AH		 2024 /*
2025 * In case tuning fails, host controllers which support
2026 * re-tuning can try tuning again at a later time, when the
2027 * re-tuning timer expires. So for these controllers, we
2028 * return 0. Since there might be other controllers who do not
2029 * have this capability, we return error for them.
2030 */
2031 err = 0;
cf2b5eea
AN		 2032 }
2033
66c39dfc 2034 host->mmc->retune_period = err ? 0 : tuning_count;
cf2b5eea 2035
b537f94c
RK		 2036 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2037 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
d519c863 2038out_unlock:
2b35bd83 2039 spin_unlock_irqrestore(&host->lock, flags);
b513ea25
AN		 2040 return err;
2041}
2042
cb849648
AH		 2043static int sdhci_select_drive_strength(struct mmc_card *card,
2044 unsigned int max_dtr, int host_drv,
2045 int card_drv, int *drv_type)
2046{
2047 struct sdhci_host *host = mmc_priv(card->host);
2048
2049 if (!host->ops->select_drive_strength)
2050 return 0;
2051
2052 return host->ops->select_drive_strength(host, card, max_dtr, host_drv,
2053 card_drv, drv_type);
2054}
52983382
KL		 2055
2056static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable)
4d55c5a1 2057{
4d55c5a1
AN		 2058 /* Host Controller v3.00 defines preset value registers */
2059 if (host->version < SDHCI_SPEC_300)
2060 return;
2061
4d55c5a1
AN		 2062 /*
2063 * We only enable or disable Preset Value if they are not already
2064 * enabled or disabled respectively. Otherwise, we bail out.
2065 */
da91a8f9
RK		 2066 if (host->preset_enabled != enable) {
2067 u16 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2068
2069 if (enable)
2070 ctrl |= SDHCI_CTRL_PRESET_VAL_ENABLE;
2071 else
2072 ctrl &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
2073
4d55c5a1 2074 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
da91a8f9
RK		 2075
2076 if (enable)
2077 host->flags |= SDHCI_PV_ENABLED;
2078 else
2079 host->flags &= ~SDHCI_PV_ENABLED;
2080
2081 host->preset_enabled = enable;
4d55c5a1 2082 }
66fd8ad5
AH		 2083}
2084
348487cb
HC		 2085static void sdhci_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
2086 int err)
2087{
2088 struct sdhci_host *host = mmc_priv(mmc);
2089 struct mmc_data *data = mrq->data;
2090
f48f039c 2091 if (data->host_cookie != COOKIE_UNMAPPED)
771a3dc2
RK		 2092 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
2093 data->flags & MMC_DATA_WRITE ?
2094 DMA_TO_DEVICE : DMA_FROM_DEVICE);
2095
2096 data->host_cookie = COOKIE_UNMAPPED;
348487cb
HC		 2097}
2098
348487cb
HC		 2099static void sdhci_pre_req(struct mmc_host *mmc, struct mmc_request *mrq,
2100 bool is_first_req)
2101{
2102 struct sdhci_host *host = mmc_priv(mmc);
2103
d31911b9 2104 mrq->data->host_cookie = COOKIE_UNMAPPED;
348487cb
HC		 2105
2106 if (host->flags & SDHCI_REQ_USE_DMA)
94538e51 2107 sdhci_pre_dma_transfer(host, mrq->data, COOKIE_PRE_MAPPED);
348487cb
HC		 2108}
2109
71e69211 2110static void sdhci_card_event(struct mmc_host *mmc)
d129bceb 2111{
71e69211 2112 struct sdhci_host *host = mmc_priv(mmc);
d129bceb 2113 unsigned long flags;
2836766a 2114 int present;
d129bceb 2115
722e1280
CD		 2116 /* First check if client has provided their own card event */
2117 if (host->ops->card_event)
2118 host->ops->card_event(host);
2119
d3940f27 2120 present = mmc->ops->get_cd(mmc);
2836766a 2121
d129bceb
PO		 2122 spin_lock_irqsave(&host->lock, flags);
2123
66fd8ad5 2124 /* Check host->mrq first in case we are runtime suspended */
2836766a 2125 if (host->mrq && !present) {
a3c76eb9 2126 pr_err("%s: Card removed during transfer!\n",
66fd8ad5 2127 mmc_hostname(host->mmc));
a3c76eb9 2128 pr_err("%s: Resetting controller.\n",
66fd8ad5 2129 mmc_hostname(host->mmc));
d129bceb 2130
03231f9b
RK		 2131 sdhci_do_reset(host, SDHCI_RESET_CMD);
2132 sdhci_do_reset(host, SDHCI_RESET_DATA);
d129bceb 2133
66fd8ad5
AH		 2134 host->mrq->cmd->error = -ENOMEDIUM;
2135 tasklet_schedule(&host->finish_tasklet);
d129bceb
PO		 2136 }
2137
2138 spin_unlock_irqrestore(&host->lock, flags);
71e69211
GL		 2139}
2140
2141static const struct mmc_host_ops sdhci_ops = {
2142 .request = sdhci_request,
348487cb
HC		 2143 .post_req = sdhci_post_req,
2144 .pre_req = sdhci_pre_req,
71e69211 2145 .set_ios = sdhci_set_ios,
94144a46 2146 .get_cd = sdhci_get_cd,
71e69211
GL		 2147 .get_ro = sdhci_get_ro,
2148 .hw_reset = sdhci_hw_reset,
2149 .enable_sdio_irq = sdhci_enable_sdio_irq,
2150 .start_signal_voltage_switch = sdhci_start_signal_voltage_switch,
b5540ce1 2151 .prepare_hs400_tuning = sdhci_prepare_hs400_tuning,
71e69211 2152 .execute_tuning = sdhci_execute_tuning,
cb849648 2153 .select_drive_strength = sdhci_select_drive_strength,
71e69211 2154 .card_event = sdhci_card_event,
20b92a30 2155 .card_busy = sdhci_card_busy,
71e69211
GL		 2156};
2157
2158/*****************************************************************************\
2159 * *
2160 * Tasklets *
2161 * *
2162\*****************************************************************************/
2163
d129bceb
PO		 2164static void sdhci_tasklet_finish(unsigned long param)
2165{
2166 struct sdhci_host *host;
2167 unsigned long flags;
2168 struct mmc_request *mrq;
2169
2170 host = (struct sdhci_host*)param;
2171
66fd8ad5
AH		 2172 spin_lock_irqsave(&host->lock, flags);
2173
0c9c99a7
CB		 2174 /*
2175 * If this tasklet gets rescheduled while running, it will
2176 * be run again afterwards but without any active request.
2177 */
66fd8ad5
AH		 2178 if (!host->mrq) {
2179 spin_unlock_irqrestore(&host->lock, flags);
0c9c99a7 2180 return;
66fd8ad5 2181 }
d129bceb
PO		 2182
2183 del_timer(&host->timer);
2184
2185 mrq = host->mrq;
2186
054cedff
RK		 2187 /*
2188 * Always unmap the data buffers if they were mapped by
2189 * sdhci_prepare_data() whenever we finish with a request.
2190 * This avoids leaking DMA mappings on error.
2191 */
2192 if (host->flags & SDHCI_REQ_USE_DMA) {
2193 struct mmc_data *data = mrq->data;
2194
2195 if (data && data->host_cookie == COOKIE_MAPPED) {
2196 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
2197 (data->flags & MMC_DATA_READ) ?
2198 DMA_FROM_DEVICE : DMA_TO_DEVICE);
2199 data->host_cookie = COOKIE_UNMAPPED;
2200 }
2201 }
2202
d129bceb
PO		 2203 /*
2204 * The controller needs a reset of internal state machines
2205 * upon error conditions.
2206 */
1e72859e 2207 if (!(host->flags & SDHCI_DEVICE_DEAD) &&
b7b4d342 2208 ((mrq->cmd && mrq->cmd->error) ||
fce9d33f
AG		 2209 (mrq->sbc && mrq->sbc->error) ||
2210 (mrq->data && ((mrq->data->error && !mrq->data->stop) ||
2211 (mrq->data->stop && mrq->data->stop->error))) ||
2212 (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) {
645289dc
PO		 2213
2214 /* Some controllers need this kick or reset won't work here */
8213af3b 2215 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)
645289dc 2216 /* This is to force an update */
1771059c 2217 host->ops->set_clock(host, host->clock);
645289dc
PO		 2218
2219 /* Spec says we should do both at the same time, but Ricoh
2220 controllers do not like that. */
03231f9b
RK		 2221 sdhci_do_reset(host, SDHCI_RESET_CMD);
2222 sdhci_do_reset(host, SDHCI_RESET_DATA);
d129bceb
PO		 2223 }
2224
2225 host->mrq = NULL;
2226 host->cmd = NULL;
2227 host->data = NULL;
2228
061d17a6 2229 sdhci_led_deactivate(host);
d129bceb 2230
5f25a66f 2231 mmiowb();
d129bceb
PO		 2232 spin_unlock_irqrestore(&host->lock, flags);
2233
2234 mmc_request_done(host->mmc, mrq);
2235}
2236
2237static void sdhci_timeout_timer(unsigned long data)
2238{
2239 struct sdhci_host *host;
2240 unsigned long flags;
2241
2242 host = (struct sdhci_host*)data;
2243
2244 spin_lock_irqsave(&host->lock, flags);
2245
2246 if (host->mrq) {
2e4456f0
MV		 2247 pr_err("%s: Timeout waiting for hardware interrupt.\n",
2248 mmc_hostname(host->mmc));
d129bceb
PO		 2249 sdhci_dumpregs(host);
2250
2251 if (host->data) {
17b0429d 2252 host->data->error = -ETIMEDOUT;
d129bceb
PO		 2253 sdhci_finish_data(host);
2254 } else {
2255 if (host->cmd)
17b0429d 2256 host->cmd->error = -ETIMEDOUT;
d129bceb 2257 else
17b0429d 2258 host->mrq->cmd->error = -ETIMEDOUT;
d129bceb
PO		 2259
2260 tasklet_schedule(&host->finish_tasklet);
2261 }
2262 }
2263
5f25a66f 2264 mmiowb();
d129bceb
PO		 2265 spin_unlock_irqrestore(&host->lock, flags);
2266}
2267
2268/*****************************************************************************\
2269 * *
2270 * Interrupt handling *
2271 * *
2272\*****************************************************************************/
2273
61541397 2274static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask, u32 *mask)
d129bceb 2275{
d129bceb 2276 if (!host->cmd) {
2e4456f0
MV		 2277 pr_err("%s: Got command interrupt 0x%08x even though no command operation was in progress.\n",
2278 mmc_hostname(host->mmc), (unsigned)intmask);
d129bceb
PO		 2279 sdhci_dumpregs(host);
2280 return;
2281 }
2282
ec014cba
RK		 2283 if (intmask & (SDHCI_INT_TIMEOUT | SDHCI_INT_CRC |
2284 SDHCI_INT_END_BIT | SDHCI_INT_INDEX)) {
2285 if (intmask & SDHCI_INT_TIMEOUT)
2286 host->cmd->error = -ETIMEDOUT;
2287 else
2288 host->cmd->error = -EILSEQ;
43b58b36 2289
71fcbda0
RK		 2290 /*
2291 * If this command initiates a data phase and a response
2292 * CRC error is signalled, the card can start transferring
2293 * data - the card may have received the command without
2294 * error. We must not terminate the mmc_request early.
2295 *
2296 * If the card did not receive the command or returned an
2297 * error which prevented it sending data, the data phase
2298 * will time out.
2299 */
2300 if (host->cmd->data &&
2301 (intmask & (SDHCI_INT_CRC | SDHCI_INT_TIMEOUT)) ==
2302 SDHCI_INT_CRC) {
2303 host->cmd = NULL;
2304 return;
2305 }
2306
d129bceb 2307 tasklet_schedule(&host->finish_tasklet);
e809517f
PO		 2308 return;
2309 }
2310
6bde8681
AH		 2311 if ((host->quirks2 & SDHCI_QUIRK2_STOP_WITH_TC) &&
2312 !(host->cmd->flags & MMC_RSP_BUSY) && !host->data &&
2313 host->cmd->opcode == MMC_STOP_TRANSMISSION)
61541397 2314 *mask &= ~SDHCI_INT_DATA_END;
e809517f
PO		 2315
2316 if (intmask & SDHCI_INT_RESPONSE)
43b58b36 2317 sdhci_finish_command(host);
d129bceb
PO		 2318}
2319
0957c333 2320#ifdef CONFIG_MMC_DEBUG
08621b18 2321static void sdhci_adma_show_error(struct sdhci_host *host)
6882a8c0
BD		 2322{
2323 const char *name = mmc_hostname(host->mmc);
1c3d5f6d 2324 void *desc = host->adma_table;
6882a8c0
BD		 2325
2326 sdhci_dumpregs(host);
2327
2328 while (true) {
e57a5f61
AH		 2329 struct sdhci_adma2_64_desc *dma_desc = desc;
2330
2331 if (host->flags & SDHCI_USE_64_BIT_DMA)
2332 DBG("%s: %p: DMA 0x%08x%08x, LEN 0x%04x, Attr=0x%02x\n",
2333 name, desc, le32_to_cpu(dma_desc->addr_hi),
2334 le32_to_cpu(dma_desc->addr_lo),
2335 le16_to_cpu(dma_desc->len),
2336 le16_to_cpu(dma_desc->cmd));
2337 else
2338 DBG("%s: %p: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n",
2339 name, desc, le32_to_cpu(dma_desc->addr_lo),
2340 le16_to_cpu(dma_desc->len),
2341 le16_to_cpu(dma_desc->cmd));
6882a8c0 2342
76fe379a 2343 desc += host->desc_sz;
6882a8c0 2344
0545230f 2345 if (dma_desc->cmd & cpu_to_le16(ADMA2_END))
6882a8c0
BD		 2346 break;
2347 }
2348}
2349#else
08621b18 2350static void sdhci_adma_show_error(struct sdhci_host *host) { }
6882a8c0
BD		 2351#endif
2352
d129bceb
PO		 2353static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
2354{
069c9f14 2355 u32 command;
d129bceb 2356
b513ea25
AN		 2357 /* CMD19 generates _only_ Buffer Read Ready interrupt */
2358 if (intmask & SDHCI_INT_DATA_AVAIL) {
069c9f14
G		 2359 command = SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND));
2360 if (command == MMC_SEND_TUNING_BLOCK ||
2361 command == MMC_SEND_TUNING_BLOCK_HS200) {
b513ea25
AN		 2362 host->tuning_done = 1;
2363 wake_up(&host->buf_ready_int);
2364 return;
2365 }
2366 }
2367
d129bceb
PO		 2368 if (!host->data) {
2369 /*
e809517f
PO		 2370 * The "data complete" interrupt is also used to
2371 * indicate that a busy state has ended. See comment
2372 * above in sdhci_cmd_irq().
d129bceb 2373 */
e809517f 2374 if (host->cmd && (host->cmd->flags & MMC_RSP_BUSY)) {
c5abd5e8
MC		 2375 if (intmask & SDHCI_INT_DATA_TIMEOUT) {
2376 host->cmd->error = -ETIMEDOUT;
2377 tasklet_schedule(&host->finish_tasklet);
2378 return;
2379 }
e809517f 2380 if (intmask & SDHCI_INT_DATA_END) {
e99783a4
CM		 2381 /*
2382 * Some cards handle busy-end interrupt
2383 * before the command completed, so make
2384 * sure we do things in the proper order.
2385 */
2386 if (host->busy_handle)
6bde8681 2387 tasklet_schedule(&host->finish_tasklet);
e99783a4
CM		 2388 else
2389 host->busy_handle = 1;
e809517f
PO		 2390 return;
2391 }
2392 }
d129bceb 2393
2e4456f0
MV		 2394 pr_err("%s: Got data interrupt 0x%08x even though no data operation was in progress.\n",
2395 mmc_hostname(host->mmc), (unsigned)intmask);
d129bceb
PO		 2396 sdhci_dumpregs(host);
2397
2398 return;
2399 }
2400
2401 if (intmask & SDHCI_INT_DATA_TIMEOUT)
17b0429d 2402 host->data->error = -ETIMEDOUT;
22113efd
AL		 2403 else if (intmask & SDHCI_INT_DATA_END_BIT)
2404 host->data->error = -EILSEQ;
2405 else if ((intmask & SDHCI_INT_DATA_CRC) &&
2406 SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))
2407 != MMC_BUS_TEST_R)
17b0429d 2408 host->data->error = -EILSEQ;
6882a8c0 2409 else if (intmask & SDHCI_INT_ADMA_ERROR) {
a3c76eb9 2410 pr_err("%s: ADMA error\n", mmc_hostname(host->mmc));
08621b18 2411 sdhci_adma_show_error(host);
2134a922 2412 host->data->error = -EIO;
a4071fbb
HZ		 2413 if (host->ops->adma_workaround)
2414 host->ops->adma_workaround(host, intmask);
6882a8c0 2415 }
d129bceb 2416
17b0429d 2417 if (host->data->error)
d129bceb
PO		 2418 sdhci_finish_data(host);
2419 else {
a406f5a3 2420 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
d129bceb
PO		 2421 sdhci_transfer_pio(host);
2422
6ba736a1
PO		 2423 /*
2424 * We currently don't do anything fancy with DMA
2425 * boundaries, but as we can't disable the feature
2426 * we need to at least restart the transfer.
f6a03cbf
MV		 2427 *
2428 * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS)
2429 * should return a valid address to continue from, but as
2430 * some controllers are faulty, don't trust them.
6ba736a1 2431 */
f6a03cbf
MV		 2432 if (intmask & SDHCI_INT_DMA_END) {
2433 u32 dmastart, dmanow;
2434 dmastart = sg_dma_address(host->data->sg);
2435 dmanow = dmastart + host->data->bytes_xfered;
2436 /*
2437 * Force update to the next DMA block boundary.
2438 */
2439 dmanow = (dmanow &
2440 ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) +
2441 SDHCI_DEFAULT_BOUNDARY_SIZE;
2442 host->data->bytes_xfered = dmanow - dmastart;
2443 DBG("%s: DMA base 0x%08x, transferred 0x%06x bytes,"
2444 " next 0x%08x\n",
2445 mmc_hostname(host->mmc), dmastart,
2446 host->data->bytes_xfered, dmanow);
2447 sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS);
2448 }
6ba736a1 2449
e538fbe8
PO		 2450 if (intmask & SDHCI_INT_DATA_END) {
2451 if (host->cmd) {
2452 /*
2453 * Data managed to finish before the
2454 * command completed. Make sure we do
2455 * things in the proper order.
2456 */
2457 host->data_early = 1;
2458 } else {
2459 sdhci_finish_data(host);
2460 }
2461 }
d129bceb
PO		 2462 }
2463}
2464
7d12e780 2465static irqreturn_t sdhci_irq(int irq, void *dev_id)
d129bceb 2466{
781e989c 2467 irqreturn_t result = IRQ_NONE;
66fd8ad5 2468 struct sdhci_host *host = dev_id;
41005003 2469 u32 intmask, mask, unexpected = 0;
781e989c 2470 int max_loops = 16;
d129bceb
PO		 2471
2472 spin_lock(&host->lock);
2473
be138554 2474 if (host->runtime_suspended && !sdhci_sdio_irq_enabled(host)) {
66fd8ad5 2475 spin_unlock(&host->lock);
655bca76 2476 return IRQ_NONE;
66fd8ad5
AH		 2477 }
2478
4e4141a5 2479 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
62df67a5 2480 if (!intmask || intmask == 0xffffffff) {
d129bceb
PO		 2481 result = IRQ_NONE;
2482 goto out;
2483 }
2484
41005003
RK		 2485 do {
2486 /* Clear selected interrupts. */
2487 mask = intmask & (SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
2488 SDHCI_INT_BUS_POWER);
2489 sdhci_writel(host, mask, SDHCI_INT_STATUS);
d129bceb 2490
41005003
RK		 2491 DBG("*** %s got interrupt: 0x%08x\n",
2492 mmc_hostname(host->mmc), intmask);
d129bceb 2493
41005003
RK		 2494 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
2495 u32 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
2496 SDHCI_CARD_PRESENT;
d129bceb 2497
41005003
RK		 2498 /*
2499 * There is a observation on i.mx esdhc. INSERT
2500 * bit will be immediately set again when it gets
2501 * cleared, if a card is inserted. We have to mask
2502 * the irq to prevent interrupt storm which will
2503 * freeze the system. And the REMOVE gets the
2504 * same situation.
2505 *
2506 * More testing are needed here to ensure it works
2507 * for other platforms though.
2508 */
b537f94c
RK		 2509 host->ier &= ~(SDHCI_INT_CARD_INSERT |
2510 SDHCI_INT_CARD_REMOVE);
2511 host->ier |= present ? SDHCI_INT_CARD_REMOVE :
2512 SDHCI_INT_CARD_INSERT;
2513 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2514 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
41005003
RK		 2515
2516 sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT |
2517 SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS);
3560db8e
RK		 2518
2519 host->thread_isr |= intmask & (SDHCI_INT_CARD_INSERT |
2520 SDHCI_INT_CARD_REMOVE);
2521 result = IRQ_WAKE_THREAD;
41005003 2522 }
d129bceb 2523
41005003 2524 if (intmask & SDHCI_INT_CMD_MASK)
61541397
AH		 2525 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK,
2526 &intmask);
964f9ce2 2527
41005003
RK		 2528 if (intmask & SDHCI_INT_DATA_MASK)
2529 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
d129bceb 2530
41005003
RK		 2531 if (intmask & SDHCI_INT_BUS_POWER)
2532 pr_err("%s: Card is consuming too much power!\n",
2533 mmc_hostname(host->mmc));
3192a28f 2534
781e989c
RK		 2535 if (intmask & SDHCI_INT_CARD_INT) {
2536 sdhci_enable_sdio_irq_nolock(host, false);
2537 host->thread_isr |= SDHCI_INT_CARD_INT;
2538 result = IRQ_WAKE_THREAD;
2539 }
f75979b7 2540
41005003
RK		 2541 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE |
2542 SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
2543 SDHCI_INT_ERROR | SDHCI_INT_BUS_POWER |
2544 SDHCI_INT_CARD_INT);
f75979b7 2545
41005003
RK		 2546 if (intmask) {
2547 unexpected |= intmask;
2548 sdhci_writel(host, intmask, SDHCI_INT_STATUS);
2549 }
d129bceb 2550
781e989c
RK		 2551 if (result == IRQ_NONE)
2552 result = IRQ_HANDLED;
d129bceb 2553
41005003 2554 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
41005003 2555 } while (intmask && --max_loops);
d129bceb
PO		 2556out:
2557 spin_unlock(&host->lock);
2558
6379b237
AS		 2559 if (unexpected) {
2560 pr_err("%s: Unexpected interrupt 0x%08x.\n",
2561 mmc_hostname(host->mmc), unexpected);
2562 sdhci_dumpregs(host);
2563 }
f75979b7 2564
d129bceb
PO		 2565 return result;
2566}
2567
781e989c
RK		 2568static irqreturn_t sdhci_thread_irq(int irq, void *dev_id)
2569{
2570 struct sdhci_host *host = dev_id;
2571 unsigned long flags;
2572 u32 isr;
2573
2574 spin_lock_irqsave(&host->lock, flags);
2575 isr = host->thread_isr;
2576 host->thread_isr = 0;
2577 spin_unlock_irqrestore(&host->lock, flags);
2578
3560db8e 2579 if (isr & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
d3940f27
AH		 2580 struct mmc_host *mmc = host->mmc;
2581
2582 mmc->ops->card_event(mmc);
2583 mmc_detect_change(mmc, msecs_to_jiffies(200));
3560db8e
RK		 2584 }
2585
781e989c
RK		 2586 if (isr & SDHCI_INT_CARD_INT) {
2587 sdio_run_irqs(host->mmc);
2588
2589 spin_lock_irqsave(&host->lock, flags);
2590 if (host->flags & SDHCI_SDIO_IRQ_ENABLED)
2591 sdhci_enable_sdio_irq_nolock(host, true);
2592 spin_unlock_irqrestore(&host->lock, flags);
2593 }
2594
2595 return isr ? IRQ_HANDLED : IRQ_NONE;
2596}
2597
d129bceb
PO		 2598/*****************************************************************************\
2599 * *
2600 * Suspend/resume *
2601 * *
2602\*****************************************************************************/
2603
2604#ifdef CONFIG_PM
84d62605
LD		 2605/*
2606 * To enable wakeup events, the corresponding events have to be enabled in
2607 * the Interrupt Status Enable register too. See 'Table 1-6: Wakeup Signal
2608 * Table' in the SD Host Controller Standard Specification.
2609 * It is useless to restore SDHCI_INT_ENABLE state in
2610 * sdhci_disable_irq_wakeups() since it will be set by
2611 * sdhci_enable_card_detection() or sdhci_init().
2612 */
ad080d79
KL		 2613void sdhci_enable_irq_wakeups(struct sdhci_host *host)
2614{
2615 u8 val;
2616 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
2617 | SDHCI_WAKE_ON_INT;
84d62605
LD		 2618 u32 irq_val = SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE |
2619 SDHCI_INT_CARD_INT;
ad080d79
KL		 2620
2621 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2622 val |= mask ;
2623 /* Avoid fake wake up */
84d62605 2624 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) {
ad080d79 2625 val &= ~(SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE);
84d62605
LD		 2626 irq_val &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE);
2627 }
ad080d79 2628 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
84d62605 2629 sdhci_writel(host, irq_val, SDHCI_INT_ENABLE);
ad080d79
KL		 2630}
2631EXPORT_SYMBOL_GPL(sdhci_enable_irq_wakeups);
2632
0b10f478 2633static void sdhci_disable_irq_wakeups(struct sdhci_host *host)
ad080d79
KL		 2634{
2635 u8 val;
2636 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
2637 | SDHCI_WAKE_ON_INT;
2638
2639 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2640 val &= ~mask;
2641 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2642}
d129bceb 2643
29495aa0 2644int sdhci_suspend_host(struct sdhci_host *host)
d129bceb 2645{
7260cf5e
AV		 2646 sdhci_disable_card_detection(host);
2647
66c39dfc
AH		 2648 mmc_retune_timer_stop(host->mmc);
2649 mmc_retune_needed(host->mmc);
cf2b5eea 2650
ad080d79 2651 if (!device_may_wakeup(mmc_dev(host->mmc))) {
b537f94c
RK		 2652 host->ier = 0;
2653 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
2654 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
ad080d79
KL		 2655 free_irq(host->irq, host);
2656 } else {
2657 sdhci_enable_irq_wakeups(host);
2658 enable_irq_wake(host->irq);
2659 }
4ee14ec6 2660 return 0;
d129bceb
PO		 2661}
2662
b8c86fc5 2663EXPORT_SYMBOL_GPL(sdhci_suspend_host);
d129bceb 2664
b8c86fc5
PO		 2665int sdhci_resume_host(struct sdhci_host *host)
2666{
d3940f27 2667 struct mmc_host *mmc = host->mmc;
4ee14ec6 2668 int ret = 0;
d129bceb 2669
a13abc7b 2670 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
b8c86fc5
PO		 2671 if (host->ops->enable_dma)
2672 host->ops->enable_dma(host);
2673 }
d129bceb 2674
6308d290
AH		 2675 if ((host->mmc->pm_flags & MMC_PM_KEEP_POWER) &&
2676 (host->quirks2 & SDHCI_QUIRK2_HOST_OFF_CARD_ON)) {
2677 /* Card keeps power but host controller does not */
2678 sdhci_init(host, 0);
2679 host->pwr = 0;
2680 host->clock = 0;
d3940f27 2681 mmc->ops->set_ios(mmc, &mmc->ios);
6308d290
AH		 2682 } else {
2683 sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER));
2684 mmiowb();
2685 }
b8c86fc5 2686
14a7b416
HC		 2687 if (!device_may_wakeup(mmc_dev(host->mmc))) {
2688 ret = request_threaded_irq(host->irq, sdhci_irq,
2689 sdhci_thread_irq, IRQF_SHARED,
2690 mmc_hostname(host->mmc), host);
2691 if (ret)
2692 return ret;
2693 } else {
2694 sdhci_disable_irq_wakeups(host);
2695 disable_irq_wake(host->irq);
2696 }
2697
7260cf5e
AV		 2698 sdhci_enable_card_detection(host);
2699
2f4cbb3d 2700 return ret;
d129bceb
PO		 2701}
2702
b8c86fc5 2703EXPORT_SYMBOL_GPL(sdhci_resume_host);
66fd8ad5 2704
66fd8ad5
AH		 2705int sdhci_runtime_suspend_host(struct sdhci_host *host)
2706{
2707 unsigned long flags;
66fd8ad5 2708
66c39dfc
AH		 2709 mmc_retune_timer_stop(host->mmc);
2710 mmc_retune_needed(host->mmc);
66fd8ad5
AH		 2711
2712 spin_lock_irqsave(&host->lock, flags);
b537f94c
RK		 2713 host->ier &= SDHCI_INT_CARD_INT;
2714 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2715 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
66fd8ad5
AH		 2716 spin_unlock_irqrestore(&host->lock, flags);
2717
781e989c 2718 synchronize_hardirq(host->irq);
66fd8ad5
AH		 2719
2720 spin_lock_irqsave(&host->lock, flags);
2721 host->runtime_suspended = true;
2722 spin_unlock_irqrestore(&host->lock, flags);
2723
8a125bad 2724 return 0;
66fd8ad5
AH		 2725}
2726EXPORT_SYMBOL_GPL(sdhci_runtime_suspend_host);
2727
2728int sdhci_runtime_resume_host(struct sdhci_host *host)
2729{
d3940f27 2730 struct mmc_host *mmc = host->mmc;
66fd8ad5 2731 unsigned long flags;
8a125bad 2732 int host_flags = host->flags;
66fd8ad5
AH		 2733
2734 if (host_flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2735 if (host->ops->enable_dma)
2736 host->ops->enable_dma(host);
2737 }
2738
2739 sdhci_init(host, 0);
2740
2741 /* Force clock and power re-program */
2742 host->pwr = 0;
2743 host->clock = 0;
d3940f27
AH		 2744 mmc->ops->start_signal_voltage_switch(mmc, &mmc->ios);
2745 mmc->ops->set_ios(mmc, &mmc->ios);
66fd8ad5 2746
52983382
KL		 2747 if ((host_flags & SDHCI_PV_ENABLED) &&
2748 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN)) {
2749 spin_lock_irqsave(&host->lock, flags);
2750 sdhci_enable_preset_value(host, true);
2751 spin_unlock_irqrestore(&host->lock, flags);
2752 }
66fd8ad5 2753
66fd8ad5
AH		 2754 spin_lock_irqsave(&host->lock, flags);
2755
2756 host->runtime_suspended = false;
2757
2758 /* Enable SDIO IRQ */
ef104333 2759 if (host->flags & SDHCI_SDIO_IRQ_ENABLED)
66fd8ad5
AH		 2760 sdhci_enable_sdio_irq_nolock(host, true);
2761
2762 /* Enable Card Detection */
2763 sdhci_enable_card_detection(host);
2764
2765 spin_unlock_irqrestore(&host->lock, flags);
2766
8a125bad 2767 return 0;
66fd8ad5
AH		 2768}
2769EXPORT_SYMBOL_GPL(sdhci_runtime_resume_host);
2770
162d6f98 2771#endif /* CONFIG_PM */
66fd8ad5 2772
d129bceb
PO		 2773/*****************************************************************************\
2774 * *
b8c86fc5 2775 * Device allocation/registration *
d129bceb
PO		 2776 * *
2777\*****************************************************************************/
2778
b8c86fc5
PO		 2779struct sdhci_host *sdhci_alloc_host(struct device *dev,
2780 size_t priv_size)
d129bceb 2781{
d129bceb
PO		 2782 struct mmc_host *mmc;
2783 struct sdhci_host *host;
2784
b8c86fc5 2785 WARN_ON(dev == NULL);
d129bceb 2786
b8c86fc5 2787 mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev);
d129bceb 2788 if (!mmc)
b8c86fc5 2789 return ERR_PTR(-ENOMEM);
d129bceb
PO		 2790
2791 host = mmc_priv(mmc);
2792 host->mmc = mmc;
bf60e592
AH		 2793 host->mmc_host_ops = sdhci_ops;
2794 mmc->ops = &host->mmc_host_ops;
d129bceb 2795
8cb851a4
AH		 2796 host->flags = SDHCI_SIGNALING_330;
2797
b8c86fc5
PO		 2798 return host;
2799}
8a4da143 2800
b8c86fc5 2801EXPORT_SYMBOL_GPL(sdhci_alloc_host);
d129bceb 2802
7b91369b
AC		 2803static int sdhci_set_dma_mask(struct sdhci_host *host)
2804{
2805 struct mmc_host *mmc = host->mmc;
2806 struct device *dev = mmc_dev(mmc);
2807 int ret = -EINVAL;
2808
2809 if (host->quirks2 & SDHCI_QUIRK2_BROKEN_64_BIT_DMA)
2810 host->flags &= ~SDHCI_USE_64_BIT_DMA;
2811
2812 /* Try 64-bit mask if hardware is capable of it */
2813 if (host->flags & SDHCI_USE_64_BIT_DMA) {
2814 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64));
2815 if (ret) {
2816 pr_warn("%s: Failed to set 64-bit DMA mask.\n",
2817 mmc_hostname(mmc));
2818 host->flags &= ~SDHCI_USE_64_BIT_DMA;
2819 }
2820 }
2821
2822 /* 32-bit mask as default & fallback */
2823 if (ret) {
2824 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32));
2825 if (ret)
2826 pr_warn("%s: Failed to set 32-bit DMA mask.\n",
2827 mmc_hostname(mmc));
2828 }
2829
2830 return ret;
2831}
2832
6132a3bf
AH		 2833void __sdhci_read_caps(struct sdhci_host *host, u16 *ver, u32 *caps, u32 *caps1)
2834{
2835 u16 v;
2836
2837 if (host->read_caps)
2838 return;
2839
2840 host->read_caps = true;
2841
2842 if (debug_quirks)
2843 host->quirks = debug_quirks;
2844
2845 if (debug_quirks2)
2846 host->quirks2 = debug_quirks2;
2847
2848 sdhci_do_reset(host, SDHCI_RESET_ALL);
2849
2850 v = ver ? *ver : sdhci_readw(host, SDHCI_HOST_VERSION);
2851 host->version = (v & SDHCI_SPEC_VER_MASK) >> SDHCI_SPEC_VER_SHIFT;
2852
2853 if (host->quirks & SDHCI_QUIRK_MISSING_CAPS)
2854 return;
2855
2856 host->caps = caps ? *caps : sdhci_readl(host, SDHCI_CAPABILITIES);
2857
2858 if (host->version < SDHCI_SPEC_300)
2859 return;
2860
2861 host->caps1 = caps1 ? *caps1 : sdhci_readl(host, SDHCI_CAPABILITIES_1);
2862}
2863EXPORT_SYMBOL_GPL(__sdhci_read_caps);
2864
52f5336d 2865int sdhci_setup_host(struct sdhci_host *host)
b8c86fc5
PO		 2866{
2867 struct mmc_host *mmc;
f2119df6
AN		 2868 u32 max_current_caps;
2869 unsigned int ocr_avail;
f5fa92e5 2870 unsigned int override_timeout_clk;
59241757 2871 u32 max_clk;
b8c86fc5 2872 int ret;
d129bceb 2873
b8c86fc5
PO		 2874 WARN_ON(host == NULL);
2875 if (host == NULL)
2876 return -EINVAL;
d129bceb 2877
b8c86fc5 2878 mmc = host->mmc;
d129bceb 2879
6132a3bf 2880 sdhci_read_caps(host);
d129bceb 2881
f5fa92e5
AH		 2882 override_timeout_clk = host->timeout_clk;
2883
85105c53 2884 if (host->version > SDHCI_SPEC_300) {
2e4456f0
MV		 2885 pr_err("%s: Unknown controller version (%d). You may experience problems.\n",
2886 mmc_hostname(mmc), host->version);
4a965505
PO		 2887 }
2888
b8c86fc5 2889 if (host->quirks & SDHCI_QUIRK_FORCE_DMA)
a13abc7b 2890 host->flags |= SDHCI_USE_SDMA;
28da3589 2891 else if (!(host->caps & SDHCI_CAN_DO_SDMA))
a13abc7b 2892 DBG("Controller doesn't have SDMA capability\n");
67435274 2893 else
a13abc7b 2894 host->flags |= SDHCI_USE_SDMA;
d129bceb 2895
b8c86fc5 2896 if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
a13abc7b 2897 (host->flags & SDHCI_USE_SDMA)) {
cee687ce 2898 DBG("Disabling DMA as it is marked broken\n");
a13abc7b 2899 host->flags &= ~SDHCI_USE_SDMA;
7c168e3d
FT		 2900 }
2901
f2119df6 2902 if ((host->version >= SDHCI_SPEC_200) &&
28da3589 2903 (host->caps & SDHCI_CAN_DO_ADMA2))
a13abc7b 2904 host->flags |= SDHCI_USE_ADMA;
2134a922
PO		 2905
2906 if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) &&
2907 (host->flags & SDHCI_USE_ADMA)) {
2908 DBG("Disabling ADMA as it is marked broken\n");
2909 host->flags &= ~SDHCI_USE_ADMA;
2910 }
2911
e57a5f61
AH		 2912 /*
2913 * It is assumed that a 64-bit capable device has set a 64-bit DMA mask
2914 * and *must* do 64-bit DMA. A driver has the opportunity to change
2915 * that during the first call to ->enable_dma(). Similarly
2916 * SDHCI_QUIRK2_BROKEN_64_BIT_DMA must be left to the drivers to
2917 * implement.
2918 */
28da3589 2919 if (host->caps & SDHCI_CAN_64BIT)
e57a5f61
AH		 2920 host->flags |= SDHCI_USE_64_BIT_DMA;
2921
a13abc7b 2922 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
7b91369b
AC		 2923 ret = sdhci_set_dma_mask(host);
2924
2925 if (!ret && host->ops->enable_dma)
2926 ret = host->ops->enable_dma(host);
2927
2928 if (ret) {
2929 pr_warn("%s: No suitable DMA available - falling back to PIO\n",
2930 mmc_hostname(mmc));
2931 host->flags &= ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
2932
2933 ret = 0;
d129bceb
PO		 2934 }
2935 }
2936
e57a5f61
AH		 2937 /* SDMA does not support 64-bit DMA */
2938 if (host->flags & SDHCI_USE_64_BIT_DMA)
2939 host->flags &= ~SDHCI_USE_SDMA;
2940
2134a922 2941 if (host->flags & SDHCI_USE_ADMA) {
e66e61cb
RK		 2942 dma_addr_t dma;
2943 void *buf;
2944
2134a922 2945 /*
76fe379a
AH		 2946 * The DMA descriptor table size is calculated as the maximum
2947 * number of segments times 2, to allow for an alignment
2948 * descriptor for each segment, plus 1 for a nop end descriptor,
2949 * all multipled by the descriptor size.
2134a922 2950 */
e57a5f61
AH		 2951 if (host->flags & SDHCI_USE_64_BIT_DMA) {
2952 host->adma_table_sz = (SDHCI_MAX_SEGS * 2 + 1) *
2953 SDHCI_ADMA2_64_DESC_SZ;
e57a5f61 2954 host->desc_sz = SDHCI_ADMA2_64_DESC_SZ;
e57a5f61
AH		 2955 } else {
2956 host->adma_table_sz = (SDHCI_MAX_SEGS * 2 + 1) *
2957 SDHCI_ADMA2_32_DESC_SZ;
e57a5f61 2958 host->desc_sz = SDHCI_ADMA2_32_DESC_SZ;
e57a5f61 2959 }
e66e61cb 2960
04a5ae6f 2961 host->align_buffer_sz = SDHCI_MAX_SEGS * SDHCI_ADMA2_ALIGN;
e66e61cb
RK		 2962 buf = dma_alloc_coherent(mmc_dev(mmc), host->align_buffer_sz +
2963 host->adma_table_sz, &dma, GFP_KERNEL);
2964 if (!buf) {
6606110d 2965 pr_warn("%s: Unable to allocate ADMA buffers - falling back to standard DMA\n",
2134a922
PO		 2966 mmc_hostname(mmc));
2967 host->flags &= ~SDHCI_USE_ADMA;
e66e61cb
RK		 2968 } else if ((dma + host->align_buffer_sz) &
2969 (SDHCI_ADMA2_DESC_ALIGN - 1)) {
6606110d
JP		 2970 pr_warn("%s: unable to allocate aligned ADMA descriptor\n",
2971 mmc_hostname(mmc));
d1e49f77 2972 host->flags &= ~SDHCI_USE_ADMA;
e66e61cb
RK		 2973 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
2974 host->adma_table_sz, buf, dma);
2975 } else {
2976 host->align_buffer = buf;
2977 host->align_addr = dma;
edd63fcc 2978
e66e61cb
RK		 2979 host->adma_table = buf + host->align_buffer_sz;
2980 host->adma_addr = dma + host->align_buffer_sz;
2981 }
2134a922
PO		 2982 }
2983
7659150c
PO		 2984 /*
2985 * If we use DMA, then it's up to the caller to set the DMA
2986 * mask, but PIO does not need the hw shim so we set a new
2987 * mask here in that case.
2988 */
a13abc7b 2989 if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) {
7659150c 2990 host->dma_mask = DMA_BIT_MASK(64);
4e743f1f 2991 mmc_dev(mmc)->dma_mask = &host->dma_mask;
7659150c 2992 }
d129bceb 2993
c4687d5f 2994 if (host->version >= SDHCI_SPEC_300)
28da3589 2995 host->max_clk = (host->caps & SDHCI_CLOCK_V3_BASE_MASK)
c4687d5f
ZG		 2996 >> SDHCI_CLOCK_BASE_SHIFT;
2997 else
28da3589 2998 host->max_clk = (host->caps & SDHCI_CLOCK_BASE_MASK)
c4687d5f
ZG		 2999 >> SDHCI_CLOCK_BASE_SHIFT;
3000
4240ff0a 3001 host->max_clk *= 1000000;
f27f47ef
AV		 3002 if (host->max_clk == 0 || host->quirks &
3003 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) {
4240ff0a 3004 if (!host->ops->get_max_clock) {
2e4456f0
MV		 3005 pr_err("%s: Hardware doesn't specify base clock frequency.\n",
3006 mmc_hostname(mmc));
eb5c20de
AH		 3007 ret = -ENODEV;
3008 goto undma;
4240ff0a
BD		 3009 }
3010 host->max_clk = host->ops->get_max_clock(host);
8ef1a143 3011 }
d129bceb 3012
c3ed3877
AN		 3013 /*
3014 * In case of Host Controller v3.00, find out whether clock
3015 * multiplier is supported.
3016 */
28da3589 3017 host->clk_mul = (host->caps1 & SDHCI_CLOCK_MUL_MASK) >>
c3ed3877
AN		 3018 SDHCI_CLOCK_MUL_SHIFT;
3019
3020 /*
3021 * In case the value in Clock Multiplier is 0, then programmable
3022 * clock mode is not supported, otherwise the actual clock
3023 * multiplier is one more than the value of Clock Multiplier
3024 * in the Capabilities Register.
3025 */
3026 if (host->clk_mul)
3027 host->clk_mul += 1;
3028
d129bceb
PO		 3029 /*
3030 * Set host parameters.
3031 */
59241757
DA		 3032 max_clk = host->max_clk;
3033
ce5f036b 3034 if (host->ops->get_min_clock)
a9e58f25 3035 mmc->f_min = host->ops->get_min_clock(host);
c3ed3877
AN		 3036 else if (host->version >= SDHCI_SPEC_300) {
3037 if (host->clk_mul) {
3038 mmc->f_min = (host->max_clk * host->clk_mul) / 1024;
59241757 3039 max_clk = host->max_clk * host->clk_mul;
c3ed3877
AN		 3040 } else
3041 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300;
3042 } else
0397526d 3043 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200;
15ec4461 3044
d310ae49 3045 if (!mmc->f_max || mmc->f_max > max_clk)
59241757
DA		 3046 mmc->f_max = max_clk;
3047
28aab053 3048 if (!(host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) {
28da3589 3049 host->timeout_clk = (host->caps & SDHCI_TIMEOUT_CLK_MASK) >>
28aab053
AD		 3050 SDHCI_TIMEOUT_CLK_SHIFT;
3051 if (host->timeout_clk == 0) {
3052 if (host->ops->get_timeout_clock) {
3053 host->timeout_clk =
3054 host->ops->get_timeout_clock(host);
3055 } else {
3056 pr_err("%s: Hardware doesn't specify timeout clock frequency.\n",
3057 mmc_hostname(mmc));
eb5c20de
AH		 3058 ret = -ENODEV;
3059 goto undma;
28aab053 3060 }
272308ca 3061 }
272308ca 3062
28da3589 3063 if (host->caps & SDHCI_TIMEOUT_CLK_UNIT)
28aab053 3064 host->timeout_clk *= 1000;
272308ca 3065
99513624
AH		 3066 if (override_timeout_clk)
3067 host->timeout_clk = override_timeout_clk;
3068
28aab053 3069 mmc->max_busy_timeout = host->ops->get_max_timeout_count ?
a6ff5aeb 3070 host->ops->get_max_timeout_count(host) : 1 << 27;
28aab053
AD		 3071 mmc->max_busy_timeout /= host->timeout_clk;
3072 }
58d1246d 3073
e89d456f 3074 mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_ERASE | MMC_CAP_CMD23;
781e989c 3075 mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD;
e89d456f
AW		 3076
3077 if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12)
3078 host->flags |= SDHCI_AUTO_CMD12;
5fe23c7f 3079
8edf6371 3080 /* Auto-CMD23 stuff only works in ADMA or PIO. */
4f3d3e9b 3081 if ((host->version >= SDHCI_SPEC_300) &&
8edf6371 3082 ((host->flags & SDHCI_USE_ADMA) ||
3bfa6f03
SB		 3083 !(host->flags & SDHCI_USE_SDMA)) &&
3084 !(host->quirks2 & SDHCI_QUIRK2_ACMD23_BROKEN)) {
8edf6371
AW		 3085 host->flags |= SDHCI_AUTO_CMD23;
3086 DBG("%s: Auto-CMD23 available\n", mmc_hostname(mmc));
3087 } else {
3088 DBG("%s: Auto-CMD23 unavailable\n", mmc_hostname(mmc));
3089 }
3090
15ec4461
PR		 3091 /*
3092 * A controller may support 8-bit width, but the board itself
3093 * might not have the pins brought out. Boards that support
3094 * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in
3095 * their platform code before calling sdhci_add_host(), and we
3096 * won't assume 8-bit width for hosts without that CAP.
3097 */
5fe23c7f 3098 if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA))
15ec4461 3099 mmc->caps |= MMC_CAP_4_BIT_DATA;
d129bceb 3100
63ef5d8c
JH		 3101 if (host->quirks2 & SDHCI_QUIRK2_HOST_NO_CMD23)
3102 mmc->caps &= ~MMC_CAP_CMD23;
3103
28da3589 3104 if (host->caps & SDHCI_CAN_DO_HISPD)
a29e7e18 3105 mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
cd9277c0 3106
176d1ed4 3107 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) &&
860951c5 3108 mmc_card_is_removable(mmc) &&
287980e4 3109 mmc_gpio_get_cd(host->mmc) < 0)
68d1fb7e
AV		 3110 mmc->caps |= MMC_CAP_NEEDS_POLL;
3111
3a48edc4 3112 /* If there are external regulators, get them */
eb5c20de
AH		 3113 ret = mmc_regulator_get_supply(mmc);
3114 if (ret == -EPROBE_DEFER)
3115 goto undma;
3a48edc4 3116
6231f3de 3117 /* If vqmmc regulator and no 1.8V signalling, then there's no UHS */
3a48edc4
TK		 3118 if (!IS_ERR(mmc->supply.vqmmc)) {
3119 ret = regulator_enable(mmc->supply.vqmmc);
3120 if (!regulator_is_supported_voltage(mmc->supply.vqmmc, 1700000,
3121 1950000))
28da3589
AH		 3122 host->caps1 &= ~(SDHCI_SUPPORT_SDR104 |
3123 SDHCI_SUPPORT_SDR50 |
3124 SDHCI_SUPPORT_DDR50);
a3361aba
CB		 3125 if (ret) {
3126 pr_warn("%s: Failed to enable vqmmc regulator: %d\n",
3127 mmc_hostname(mmc), ret);
4bb74313 3128 mmc->supply.vqmmc = ERR_PTR(-EINVAL);
a3361aba 3129 }
8363c374 3130 }
6231f3de 3131
28da3589
AH		 3132 if (host->quirks2 & SDHCI_QUIRK2_NO_1_8_V) {
3133 host->caps1 &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
3134 SDHCI_SUPPORT_DDR50);
3135 }
6a66180a 3136
4188bba0 3137 /* Any UHS-I mode in caps implies SDR12 and SDR25 support. */
28da3589
AH		 3138 if (host->caps1 & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
3139 SDHCI_SUPPORT_DDR50))
f2119df6
AN		 3140 mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;
3141
3142 /* SDR104 supports also implies SDR50 support */
28da3589 3143 if (host->caps1 & SDHCI_SUPPORT_SDR104) {
f2119df6 3144 mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50;
156e14b1
GC		 3145 /* SD3.0: SDR104 is supported so (for eMMC) the caps2
3146 * field can be promoted to support HS200.
3147 */
549c0b18 3148 if (!(host->quirks2 & SDHCI_QUIRK2_BROKEN_HS200))
13868bf2 3149 mmc->caps2 |= MMC_CAP2_HS200;
28da3589 3150 } else if (host->caps1 & SDHCI_SUPPORT_SDR50) {
f2119df6 3151 mmc->caps |= MMC_CAP_UHS_SDR50;
28da3589 3152 }
f2119df6 3153
e9fb05d5 3154 if (host->quirks2 & SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 &&
28da3589 3155 (host->caps1 & SDHCI_SUPPORT_HS400))
e9fb05d5
AH		 3156 mmc->caps2 |= MMC_CAP2_HS400;
3157
549c0b18
AH		 3158 if ((mmc->caps2 & MMC_CAP2_HSX00_1_2V) &&
3159 (IS_ERR(mmc->supply.vqmmc) ||
3160 !regulator_is_supported_voltage(mmc->supply.vqmmc, 1100000,
3161 1300000)))
3162 mmc->caps2 &= ~MMC_CAP2_HSX00_1_2V;
3163
28da3589
AH		 3164 if ((host->caps1 & SDHCI_SUPPORT_DDR50) &&
3165 !(host->quirks2 & SDHCI_QUIRK2_BROKEN_DDR50))
f2119df6
AN		 3166 mmc->caps |= MMC_CAP_UHS_DDR50;
3167
069c9f14 3168 /* Does the host need tuning for SDR50? */
28da3589 3169 if (host->caps1 & SDHCI_USE_SDR50_TUNING)
b513ea25
AN		 3170 host->flags |= SDHCI_SDR50_NEEDS_TUNING;
3171
d6d50a15 3172 /* Driver Type(s) (A, C, D) supported by the host */
28da3589 3173 if (host->caps1 & SDHCI_DRIVER_TYPE_A)
d6d50a15 3174 mmc->caps |= MMC_CAP_DRIVER_TYPE_A;
28da3589 3175 if (host->caps1 & SDHCI_DRIVER_TYPE_C)
d6d50a15 3176 mmc->caps |= MMC_CAP_DRIVER_TYPE_C;
28da3589 3177 if (host->caps1 & SDHCI_DRIVER_TYPE_D)
d6d50a15
AN		 3178 mmc->caps |= MMC_CAP_DRIVER_TYPE_D;
3179
cf2b5eea 3180 /* Initial value for re-tuning timer count */
28da3589
AH		 3181 host->tuning_count = (host->caps1 & SDHCI_RETUNING_TIMER_COUNT_MASK) >>
3182 SDHCI_RETUNING_TIMER_COUNT_SHIFT;
cf2b5eea
AN		 3183
3184 /*
3185 * In case Re-tuning Timer is not disabled, the actual value of
3186 * re-tuning timer will be 2 ^ (n - 1).
3187 */
3188 if (host->tuning_count)
3189 host->tuning_count = 1 << (host->tuning_count - 1);
3190
3191 /* Re-tuning mode supported by the Host Controller */
28da3589 3192 host->tuning_mode = (host->caps1 & SDHCI_RETUNING_MODE_MASK) >>
cf2b5eea
AN		 3193 SDHCI_RETUNING_MODE_SHIFT;
3194
8f230f45 3195 ocr_avail = 0;
bad37e1a 3196
f2119df6
AN		 3197 /*
3198 * According to SD Host Controller spec v3.00, if the Host System
3199 * can afford more than 150mA, Host Driver should set XPC to 1. Also
3200 * the value is meaningful only if Voltage Support in the Capabilities
3201 * register is set. The actual current value is 4 times the register
3202 * value.
3203 */
3204 max_current_caps = sdhci_readl(host, SDHCI_MAX_CURRENT);
3a48edc4 3205 if (!max_current_caps && !IS_ERR(mmc->supply.vmmc)) {
ae906037 3206 int curr = regulator_get_current_limit(mmc->supply.vmmc);
bad37e1a
PR		 3207 if (curr > 0) {
3208
3209 /* convert to SDHCI_MAX_CURRENT format */
3210 curr = curr/1000; /* convert to mA */
3211 curr = curr/SDHCI_MAX_CURRENT_MULTIPLIER;
3212
3213 curr = min_t(u32, curr, SDHCI_MAX_CURRENT_LIMIT);
3214 max_current_caps =
3215 (curr << SDHCI_MAX_CURRENT_330_SHIFT) |
3216 (curr << SDHCI_MAX_CURRENT_300_SHIFT) |
3217 (curr << SDHCI_MAX_CURRENT_180_SHIFT);
3218 }
3219 }
f2119df6 3220
28da3589 3221 if (host->caps & SDHCI_CAN_VDD_330) {
8f230f45 3222 ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34;
f2119df6 3223
55c4665e 3224 mmc->max_current_330 = ((max_current_caps &
f2119df6
AN		 3225 SDHCI_MAX_CURRENT_330_MASK) >>
3226 SDHCI_MAX_CURRENT_330_SHIFT) *
3227 SDHCI_MAX_CURRENT_MULTIPLIER;
f2119df6 3228 }
28da3589 3229 if (host->caps & SDHCI_CAN_VDD_300) {
8f230f45 3230 ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31;
f2119df6 3231
55c4665e 3232 mmc->max_current_300 = ((max_current_caps &
f2119df6
AN		 3233 SDHCI_MAX_CURRENT_300_MASK) >>
3234 SDHCI_MAX_CURRENT_300_SHIFT) *
3235 SDHCI_MAX_CURRENT_MULTIPLIER;
f2119df6 3236 }
28da3589 3237 if (host->caps & SDHCI_CAN_VDD_180) {
8f230f45
TI		 3238 ocr_avail |= MMC_VDD_165_195;
3239
55c4665e 3240 mmc->max_current_180 = ((max_current_caps &
f2119df6
AN		 3241 SDHCI_MAX_CURRENT_180_MASK) >>
3242 SDHCI_MAX_CURRENT_180_SHIFT) *
3243 SDHCI_MAX_CURRENT_MULTIPLIER;
f2119df6
AN		 3244 }
3245
5fd26c7e
UH		 3246 /* If OCR set by host, use it instead. */
3247 if (host->ocr_mask)
3248 ocr_avail = host->ocr_mask;
3249
3250 /* If OCR set by external regulators, give it highest prio. */
3a48edc4 3251 if (mmc->ocr_avail)
52221610 3252 ocr_avail = mmc->ocr_avail;
3a48edc4 3253
8f230f45
TI		 3254 mmc->ocr_avail = ocr_avail;
3255 mmc->ocr_avail_sdio = ocr_avail;
3256 if (host->ocr_avail_sdio)
3257 mmc->ocr_avail_sdio &= host->ocr_avail_sdio;
3258 mmc->ocr_avail_sd = ocr_avail;
3259 if (host->ocr_avail_sd)
3260 mmc->ocr_avail_sd &= host->ocr_avail_sd;
3261 else /* normal SD controllers don't support 1.8V */
3262 mmc->ocr_avail_sd &= ~MMC_VDD_165_195;
3263 mmc->ocr_avail_mmc = ocr_avail;
3264 if (host->ocr_avail_mmc)
3265 mmc->ocr_avail_mmc &= host->ocr_avail_mmc;
146ad66e
PO		 3266
3267 if (mmc->ocr_avail == 0) {
2e4456f0
MV		 3268 pr_err("%s: Hardware doesn't report any support voltages.\n",
3269 mmc_hostname(mmc));
eb5c20de
AH		 3270 ret = -ENODEV;
3271 goto unreg;
146ad66e
PO		 3272 }
3273
8cb851a4
AH		 3274 if ((mmc->caps & (MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 |
3275 MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_SDR104 |
3276 MMC_CAP_UHS_DDR50 | MMC_CAP_1_8V_DDR)) ||
3277 (mmc->caps2 & (MMC_CAP2_HS200_1_8V_SDR | MMC_CAP2_HS400_1_8V)))
3278 host->flags |= SDHCI_SIGNALING_180;
3279
3280 if (mmc->caps2 & MMC_CAP2_HSX00_1_2V)
3281 host->flags |= SDHCI_SIGNALING_120;
3282
d129bceb
PO		 3283 spin_lock_init(&host->lock);
3284
3285 /*
2134a922
PO		 3286 * Maximum number of segments. Depends on if the hardware
3287 * can do scatter/gather or not.
d129bceb 3288 */
2134a922 3289 if (host->flags & SDHCI_USE_ADMA)
4fb213f8 3290 mmc->max_segs = SDHCI_MAX_SEGS;
a13abc7b 3291 else if (host->flags & SDHCI_USE_SDMA)
a36274e0 3292 mmc->max_segs = 1;
2134a922 3293 else /* PIO */
4fb213f8 3294 mmc->max_segs = SDHCI_MAX_SEGS;
d129bceb
PO		 3295
3296 /*
ac00531d
AH		 3297 * Maximum number of sectors in one transfer. Limited by SDMA boundary
3298 * size (512KiB). Note some tuning modes impose a 4MiB limit, but this
3299 * is less anyway.
d129bceb 3300 */
55db890a 3301 mmc->max_req_size = 524288;
d129bceb
PO		 3302
3303 /*
3304 * Maximum segment size. Could be one segment with the maximum number
2134a922
PO		 3305 * of bytes. When doing hardware scatter/gather, each entry cannot
3306 * be larger than 64 KiB though.
d129bceb 3307 */
30652aa3
OJ		 3308 if (host->flags & SDHCI_USE_ADMA) {
3309 if (host->quirks & SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC)
3310 mmc->max_seg_size = 65535;
3311 else
3312 mmc->max_seg_size = 65536;
3313 } else {
2134a922 3314 mmc->max_seg_size = mmc->max_req_size;
30652aa3 3315 }
d129bceb 3316
fe4a3c7a
PO		 3317 /*
3318 * Maximum block size. This varies from controller to controller and
3319 * is specified in the capabilities register.
3320 */
0633f654
AV		 3321 if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) {
3322 mmc->max_blk_size = 2;
3323 } else {
28da3589 3324 mmc->max_blk_size = (host->caps & SDHCI_MAX_BLOCK_MASK) >>
0633f654
AV		 3325 SDHCI_MAX_BLOCK_SHIFT;
3326 if (mmc->max_blk_size >= 3) {
6606110d
JP		 3327 pr_warn("%s: Invalid maximum block size, assuming 512 bytes\n",
3328 mmc_hostname(mmc));
0633f654
AV		 3329 mmc->max_blk_size = 0;
3330 }
3331 }
3332
3333 mmc->max_blk_size = 512 << mmc->max_blk_size;
fe4a3c7a 3334
55db890a
PO		 3335 /*
3336 * Maximum block count.
3337 */
1388eefd 3338 mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
55db890a 3339
52f5336d
AH		 3340 return 0;
3341
3342unreg:
3343 if (!IS_ERR(mmc->supply.vqmmc))
3344 regulator_disable(mmc->supply.vqmmc);
3345undma:
3346 if (host->align_buffer)
3347 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
3348 host->adma_table_sz, host->align_buffer,
3349 host->align_addr);
3350 host->adma_table = NULL;
3351 host->align_buffer = NULL;
3352
3353 return ret;
3354}
3355EXPORT_SYMBOL_GPL(sdhci_setup_host);
3356
3357int __sdhci_add_host(struct sdhci_host *host)
3358{
3359 struct mmc_host *mmc = host->mmc;
3360 int ret;
3361
d129bceb
PO		 3362 /*
3363 * Init tasklets.
3364 */
d129bceb
PO		 3365 tasklet_init(&host->finish_tasklet,
3366 sdhci_tasklet_finish, (unsigned long)host);
3367
e4cad1b5 3368 setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host);
d129bceb 3369
250fb7b4 3370 init_waitqueue_head(&host->buf_ready_int);
b513ea25 3371
2af502ca
SG		 3372 sdhci_init(host, 0);
3373
781e989c
RK		 3374 ret = request_threaded_irq(host->irq, sdhci_irq, sdhci_thread_irq,
3375 IRQF_SHARED, mmc_hostname(mmc), host);
0fc81ee3
MB		 3376 if (ret) {
3377 pr_err("%s: Failed to request IRQ %d: %d\n",
3378 mmc_hostname(mmc), host->irq, ret);
8ef1a143 3379 goto untasklet;
0fc81ee3 3380 }
d129bceb 3381
d129bceb
PO		 3382#ifdef CONFIG_MMC_DEBUG
3383 sdhci_dumpregs(host);
3384#endif
3385
061d17a6 3386 ret = sdhci_led_register(host);
0fc81ee3
MB		 3387 if (ret) {
3388 pr_err("%s: Failed to register LED device: %d\n",
3389 mmc_hostname(mmc), ret);
eb5c20de 3390 goto unirq;
0fc81ee3 3391 }
2f730fec 3392
5f25a66f
PO		 3393 mmiowb();
3394
eb5c20de
AH		 3395 ret = mmc_add_host(mmc);
3396 if (ret)
3397 goto unled;
d129bceb 3398
a3c76eb9 3399 pr_info("%s: SDHCI controller on %s [%s] using %s\n",
d1b26863 3400 mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)),
e57a5f61
AH		 3401 (host->flags & SDHCI_USE_ADMA) ?
3402 (host->flags & SDHCI_USE_64_BIT_DMA) ? "ADMA 64-bit" : "ADMA" :
a13abc7b 3403 (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO");
d129bceb 3404
7260cf5e
AV		 3405 sdhci_enable_card_detection(host);
3406
d129bceb
PO		 3407 return 0;
3408
eb5c20de 3409unled:
061d17a6 3410 sdhci_led_unregister(host);
eb5c20de 3411unirq:
03231f9b 3412 sdhci_do_reset(host, SDHCI_RESET_ALL);
b537f94c
RK		 3413 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
3414 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
2f730fec 3415 free_irq(host->irq, host);
8ef1a143 3416untasklet:
d129bceb 3417 tasklet_kill(&host->finish_tasklet);
52f5336d 3418
eb5c20de
AH		 3419 if (!IS_ERR(mmc->supply.vqmmc))
3420 regulator_disable(mmc->supply.vqmmc);
52f5336d 3421
eb5c20de
AH		 3422 if (host->align_buffer)
3423 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
3424 host->adma_table_sz, host->align_buffer,
3425 host->align_addr);
3426 host->adma_table = NULL;
3427 host->align_buffer = NULL;
d129bceb
PO		 3428
3429 return ret;
3430}
52f5336d
AH		 3431EXPORT_SYMBOL_GPL(__sdhci_add_host);
3432
3433int sdhci_add_host(struct sdhci_host *host)
3434{
3435 int ret;
3436
3437 ret = sdhci_setup_host(host);
3438 if (ret)
3439 return ret;
d129bceb 3440
52f5336d
AH		 3441 return __sdhci_add_host(host);
3442}
b8c86fc5 3443EXPORT_SYMBOL_GPL(sdhci_add_host);
d129bceb 3444
1e72859e 3445void sdhci_remove_host(struct sdhci_host *host, int dead)
b8c86fc5 3446{
3a48edc4 3447 struct mmc_host *mmc = host->mmc;
1e72859e
PO		 3448 unsigned long flags;
3449
3450 if (dead) {
3451 spin_lock_irqsave(&host->lock, flags);
3452
3453 host->flags |= SDHCI_DEVICE_DEAD;
3454
3455 if (host->mrq) {
a3c76eb9 3456 pr_err("%s: Controller removed during "
4e743f1f 3457 " transfer!\n", mmc_hostname(mmc));
1e72859e
PO		 3458
3459 host->mrq->cmd->error = -ENOMEDIUM;
3460 tasklet_schedule(&host->finish_tasklet);
3461 }
3462
3463 spin_unlock_irqrestore(&host->lock, flags);
3464 }
3465
7260cf5e
AV		 3466 sdhci_disable_card_detection(host);
3467
4e743f1f 3468 mmc_remove_host(mmc);
d129bceb 3469
061d17a6 3470 sdhci_led_unregister(host);
2f730fec 3471
1e72859e 3472 if (!dead)
03231f9b 3473 sdhci_do_reset(host, SDHCI_RESET_ALL);
d129bceb 3474
b537f94c
RK		 3475 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
3476 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
d129bceb
PO		 3477 free_irq(host->irq, host);
3478
3479 del_timer_sync(&host->timer);
3480
d129bceb 3481 tasklet_kill(&host->finish_tasklet);
2134a922 3482
3a48edc4
TK		 3483 if (!IS_ERR(mmc->supply.vqmmc))
3484 regulator_disable(mmc->supply.vqmmc);
6231f3de 3485
edd63fcc 3486 if (host->align_buffer)
e66e61cb
RK		 3487 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
3488 host->adma_table_sz, host->align_buffer,
3489 host->align_addr);
2134a922 3490
4efaa6fb 3491 host->adma_table = NULL;
2134a922 3492 host->align_buffer = NULL;
d129bceb
PO		 3493}
3494
b8c86fc5 3495EXPORT_SYMBOL_GPL(sdhci_remove_host);
d129bceb 3496
b8c86fc5 3497void sdhci_free_host(struct sdhci_host *host)
d129bceb 3498{
b8c86fc5 3499 mmc_free_host(host->mmc);
d129bceb
PO		 3500}
3501
b8c86fc5 3502EXPORT_SYMBOL_GPL(sdhci_free_host);
d129bceb
PO		 3503
3504/*****************************************************************************\
3505 * *
3506 * Driver init/exit *
3507 * *
3508\*****************************************************************************/
3509
3510static int __init sdhci_drv_init(void)
3511{
a3c76eb9 3512 pr_info(DRIVER_NAME
52fbf9c9 3513 ": Secure Digital Host Controller Interface driver\n");
a3c76eb9 3514 pr_info(DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
d129bceb 3515
b8c86fc5 3516 return 0;
d129bceb
PO		 3517}
3518
3519static void __exit sdhci_drv_exit(void)
3520{
d129bceb
PO		 3521}
3522
3523module_init(sdhci_drv_init);
3524module_exit(sdhci_drv_exit);
3525
df673b22 3526module_param(debug_quirks, uint, 0444);
66fd8ad5 3527module_param(debug_quirks2, uint, 0444);
67435274 3528
32710e8f 3529MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
b8c86fc5 3530MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver");
d129bceb 3531MODULE_LICENSE("GPL");
67435274 3532
df673b22 3533MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");
66fd8ad5 3534MODULE_PARM_DESC(debug_quirks2, "Force certain other quirks.");
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