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mmc: sdhci: Tidy tuning loop
[mirror_ubuntu-artful-kernel.git] / drivers / mmc / host / sdhci.c
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d129bceb 1/*
70f10482 2 * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
d129bceb 3 *
b69c9058 4 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
d129bceb
PO		 5 *
6 * This program is free software; you can redistribute it and/or modify
643f720c
PO		 7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or (at
9 * your option) any later version.
84c46a53
PO		 10 *
11 * Thanks to the following companies for their support:
12 *
13 * - JMicron (hardware and technical support)
d129bceb
PO		 14 */
15
d129bceb
PO		 16#include <linux/delay.h>
17#include <linux/highmem.h>
b8c86fc5 18#include <linux/io.h>
88b47679 19#include <linux/module.h>
d129bceb 20#include <linux/dma-mapping.h>
5a0e3ad6 21#include <linux/slab.h>
11763609 22#include <linux/scatterlist.h>
9bea3c85 23#include <linux/regulator/consumer.h>
66fd8ad5 24#include <linux/pm_runtime.h>
92e0c44b 25#include <linux/of.h>
d129bceb 26
2f730fec
PO		 27#include <linux/leds.h>
28
22113efd 29#include <linux/mmc/mmc.h>
d129bceb 30#include <linux/mmc/host.h>
473b095a 31#include <linux/mmc/card.h>
85cc1c33 32#include <linux/mmc/sdio.h>
bec9d4e5 33#include <linux/mmc/slot-gpio.h>
d129bceb 34
d129bceb
PO		 35#include "sdhci.h"
36
37#define DRIVER_NAME "sdhci"
d129bceb 38
d129bceb 39#define DBG(f, x...) \
c6563178 40 pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
d129bceb 41
b513ea25
AN		 42#define MAX_TUNING_LOOP 40
43
df673b22 44static unsigned int debug_quirks = 0;
66fd8ad5 45static unsigned int debug_quirks2;
67435274 46
d129bceb
PO		 47static void sdhci_finish_data(struct sdhci_host *);
48
52983382 49static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable);
d129bceb
PO		 50
51static void sdhci_dumpregs(struct sdhci_host *host)
52{
a7c53671
CD		 53 pr_err(DRIVER_NAME ": =========== REGISTER DUMP (%s)===========\n",
54 mmc_hostname(host->mmc));
d129bceb 55
a7c53671
CD		 56 pr_err(DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n",
57 sdhci_readl(host, SDHCI_DMA_ADDRESS),
58 sdhci_readw(host, SDHCI_HOST_VERSION));
59 pr_err(DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n",
60 sdhci_readw(host, SDHCI_BLOCK_SIZE),
61 sdhci_readw(host, SDHCI_BLOCK_COUNT));
62 pr_err(DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
63 sdhci_readl(host, SDHCI_ARGUMENT),
64 sdhci_readw(host, SDHCI_TRANSFER_MODE));
65 pr_err(DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n",
66 sdhci_readl(host, SDHCI_PRESENT_STATE),
67 sdhci_readb(host, SDHCI_HOST_CONTROL));
68 pr_err(DRIVER_NAME ": Power: 0x%08x | Blk gap: 0x%08x\n",
69 sdhci_readb(host, SDHCI_POWER_CONTROL),
70 sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL));
71 pr_err(DRIVER_NAME ": Wake-up: 0x%08x | Clock: 0x%08x\n",
72 sdhci_readb(host, SDHCI_WAKE_UP_CONTROL),
73 sdhci_readw(host, SDHCI_CLOCK_CONTROL));
74 pr_err(DRIVER_NAME ": Timeout: 0x%08x | Int stat: 0x%08x\n",
75 sdhci_readb(host, SDHCI_TIMEOUT_CONTROL),
76 sdhci_readl(host, SDHCI_INT_STATUS));
77 pr_err(DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
78 sdhci_readl(host, SDHCI_INT_ENABLE),
79 sdhci_readl(host, SDHCI_SIGNAL_ENABLE));
80 pr_err(DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
81 sdhci_readw(host, SDHCI_ACMD12_ERR),
82 sdhci_readw(host, SDHCI_SLOT_INT_STATUS));
83 pr_err(DRIVER_NAME ": Caps: 0x%08x | Caps_1: 0x%08x\n",
84 sdhci_readl(host, SDHCI_CAPABILITIES),
85 sdhci_readl(host, SDHCI_CAPABILITIES_1));
86 pr_err(DRIVER_NAME ": Cmd: 0x%08x | Max curr: 0x%08x\n",
87 sdhci_readw(host, SDHCI_COMMAND),
88 sdhci_readl(host, SDHCI_MAX_CURRENT));
89 pr_err(DRIVER_NAME ": Host ctl2: 0x%08x\n",
90 sdhci_readw(host, SDHCI_HOST_CONTROL2));
d129bceb 91
e57a5f61
AH		 92 if (host->flags & SDHCI_USE_ADMA) {
93 if (host->flags & SDHCI_USE_64_BIT_DMA)
a7c53671
CD		 94 pr_err(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x%08x\n",
95 readl(host->ioaddr + SDHCI_ADMA_ERROR),
96 readl(host->ioaddr + SDHCI_ADMA_ADDRESS_HI),
97 readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
e57a5f61 98 else
a7c53671
CD		 99 pr_err(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n",
100 readl(host->ioaddr + SDHCI_ADMA_ERROR),
101 readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
e57a5f61 102 }
be3f4ae0 103
a7c53671 104 pr_err(DRIVER_NAME ": ===========================================\n");
d129bceb
PO		 105}
106
107/*****************************************************************************\
108 * *
109 * Low level functions *
110 * *
111\*****************************************************************************/
112
56a590dc
AH		 113static inline bool sdhci_data_line_cmd(struct mmc_command *cmd)
114{
115 return cmd->data || cmd->flags & MMC_RSP_BUSY;
116}
117
7260cf5e
AV		 118static void sdhci_set_card_detection(struct sdhci_host *host, bool enable)
119{
5b4f1f6c 120 u32 present;
7260cf5e 121
c79396c1 122 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) ||
860951c5 123 !mmc_card_is_removable(host->mmc))
66fd8ad5
AH		 124 return;
125
5b4f1f6c
RK		 126 if (enable) {
127 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
128 SDHCI_CARD_PRESENT;
d25928d1 129
5b4f1f6c
RK		 130 host->ier |= present ? SDHCI_INT_CARD_REMOVE :
131 SDHCI_INT_CARD_INSERT;
132 } else {
133 host->ier &= ~(SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT);
134 }
b537f94c
RK		 135
136 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
137 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
7260cf5e
AV		 138}
139
140static void sdhci_enable_card_detection(struct sdhci_host *host)
141{
142 sdhci_set_card_detection(host, true);
143}
144
145static void sdhci_disable_card_detection(struct sdhci_host *host)
146{
147 sdhci_set_card_detection(host, false);
148}
149
02d0b685
UH		 150static void sdhci_runtime_pm_bus_on(struct sdhci_host *host)
151{
152 if (host->bus_on)
153 return;
154 host->bus_on = true;
155 pm_runtime_get_noresume(host->mmc->parent);
156}
157
158static void sdhci_runtime_pm_bus_off(struct sdhci_host *host)
159{
160 if (!host->bus_on)
161 return;
162 host->bus_on = false;
163 pm_runtime_put_noidle(host->mmc->parent);
164}
165
03231f9b 166void sdhci_reset(struct sdhci_host *host, u8 mask)
d129bceb 167{
e16514d8 168 unsigned long timeout;
393c1a34 169
4e4141a5 170 sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
d129bceb 171
f0710a55 172 if (mask & SDHCI_RESET_ALL) {
d129bceb 173 host->clock = 0;
f0710a55
AH		 174 /* Reset-all turns off SD Bus Power */
175 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
176 sdhci_runtime_pm_bus_off(host);
177 }
d129bceb 178
e16514d8
PO		 179 /* Wait max 100 ms */
180 timeout = 100;
181
182 /* hw clears the bit when it's done */
4e4141a5 183 while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
e16514d8 184 if (timeout == 0) {
a3c76eb9 185 pr_err("%s: Reset 0x%x never completed.\n",
e16514d8
PO		 186 mmc_hostname(host->mmc), (int)mask);
187 sdhci_dumpregs(host);
188 return;
189 }
190 timeout--;
191 mdelay(1);
d129bceb 192 }
03231f9b
RK		 193}
194EXPORT_SYMBOL_GPL(sdhci_reset);
195
196static void sdhci_do_reset(struct sdhci_host *host, u8 mask)
197{
198 if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
d3940f27
AH		 199 struct mmc_host *mmc = host->mmc;
200
201 if (!mmc->ops->get_cd(mmc))
03231f9b
RK		 202 return;
203 }
063a9dbb 204
03231f9b 205 host->ops->reset(host, mask);
393c1a34 206
da91a8f9
RK		 207 if (mask & SDHCI_RESET_ALL) {
208 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
209 if (host->ops->enable_dma)
210 host->ops->enable_dma(host);
211 }
212
213 /* Resetting the controller clears many */
214 host->preset_enabled = false;
3abc1e80 215 }
d129bceb
PO		 216}
217
2f4cbb3d 218static void sdhci_init(struct sdhci_host *host, int soft)
d129bceb 219{
d3940f27
AH		 220 struct mmc_host *mmc = host->mmc;
221
2f4cbb3d 222 if (soft)
03231f9b 223 sdhci_do_reset(host, SDHCI_RESET_CMD|SDHCI_RESET_DATA);
2f4cbb3d 224 else
03231f9b 225 sdhci_do_reset(host, SDHCI_RESET_ALL);
d129bceb 226
b537f94c
RK		 227 host->ier = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
228 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT |
229 SDHCI_INT_INDEX | SDHCI_INT_END_BIT | SDHCI_INT_CRC |
230 SDHCI_INT_TIMEOUT | SDHCI_INT_DATA_END |
231 SDHCI_INT_RESPONSE;
232
f37b20eb
DA		 233 if (host->tuning_mode == SDHCI_TUNING_MODE_2 ||
234 host->tuning_mode == SDHCI_TUNING_MODE_3)
235 host->ier |= SDHCI_INT_RETUNE;
236
b537f94c
RK		 237 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
238 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2f4cbb3d
NP		 239
240 if (soft) {
241 /* force clock reconfiguration */
242 host->clock = 0;
d3940f27 243 mmc->ops->set_ios(mmc, &mmc->ios);
2f4cbb3d 244 }
7260cf5e 245}
d129bceb 246
7260cf5e
AV		 247static void sdhci_reinit(struct sdhci_host *host)
248{
2f4cbb3d 249 sdhci_init(host, 0);
7260cf5e 250 sdhci_enable_card_detection(host);
d129bceb
PO		 251}
252
061d17a6 253static void __sdhci_led_activate(struct sdhci_host *host)
d129bceb
PO		 254{
255 u8 ctrl;
256
4e4141a5 257 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
d129bceb 258 ctrl |= SDHCI_CTRL_LED;
4e4141a5 259 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d129bceb
PO		 260}
261
061d17a6 262static void __sdhci_led_deactivate(struct sdhci_host *host)
d129bceb
PO		 263{
264 u8 ctrl;
265
4e4141a5 266 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
d129bceb 267 ctrl &= ~SDHCI_CTRL_LED;
4e4141a5 268 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d129bceb
PO		 269}
270
4f78230f 271#if IS_REACHABLE(CONFIG_LEDS_CLASS)
2f730fec 272static void sdhci_led_control(struct led_classdev *led,
061d17a6 273 enum led_brightness brightness)
2f730fec
PO		 274{
275 struct sdhci_host *host = container_of(led, struct sdhci_host, led);
276 unsigned long flags;
277
278 spin_lock_irqsave(&host->lock, flags);
279
66fd8ad5
AH		 280 if (host->runtime_suspended)
281 goto out;
282
2f730fec 283 if (brightness == LED_OFF)
061d17a6 284 __sdhci_led_deactivate(host);
2f730fec 285 else
061d17a6 286 __sdhci_led_activate(host);
66fd8ad5 287out:
2f730fec
PO		 288 spin_unlock_irqrestore(&host->lock, flags);
289}
061d17a6
AH		 290
291static int sdhci_led_register(struct sdhci_host *host)
292{
293 struct mmc_host *mmc = host->mmc;
294
295 snprintf(host->led_name, sizeof(host->led_name),
296 "%s::", mmc_hostname(mmc));
297
298 host->led.name = host->led_name;
299 host->led.brightness = LED_OFF;
300 host->led.default_trigger = mmc_hostname(mmc);
301 host->led.brightness_set = sdhci_led_control;
302
303 return led_classdev_register(mmc_dev(mmc), &host->led);
304}
305
306static void sdhci_led_unregister(struct sdhci_host *host)
307{
308 led_classdev_unregister(&host->led);
309}
310
311static inline void sdhci_led_activate(struct sdhci_host *host)
312{
313}
314
315static inline void sdhci_led_deactivate(struct sdhci_host *host)
316{
317}
318
319#else
320
321static inline int sdhci_led_register(struct sdhci_host *host)
322{
323 return 0;
324}
325
326static inline void sdhci_led_unregister(struct sdhci_host *host)
327{
328}
329
330static inline void sdhci_led_activate(struct sdhci_host *host)
331{
332 __sdhci_led_activate(host);
333}
334
335static inline void sdhci_led_deactivate(struct sdhci_host *host)
336{
337 __sdhci_led_deactivate(host);
338}
339
2f730fec
PO		 340#endif
341
d129bceb
PO		 342/*****************************************************************************\
343 * *
344 * Core functions *
345 * *
346\*****************************************************************************/
347
a406f5a3 348static void sdhci_read_block_pio(struct sdhci_host *host)
d129bceb 349{
7659150c
PO		 350 unsigned long flags;
351 size_t blksize, len, chunk;
7244b85b 352 u32 uninitialized_var(scratch);
7659150c 353 u8 *buf;
d129bceb 354
a406f5a3 355 DBG("PIO reading\n");
d129bceb 356
a406f5a3 357 blksize = host->data->blksz;
7659150c 358 chunk = 0;
d129bceb 359
7659150c 360 local_irq_save(flags);
d129bceb 361
a406f5a3 362 while (blksize) {
bf3a35ac 363 BUG_ON(!sg_miter_next(&host->sg_miter));
d129bceb 364
7659150c 365 len = min(host->sg_miter.length, blksize);
d129bceb 366
7659150c
PO		 367 blksize -= len;
368 host->sg_miter.consumed = len;
14d836e7 369
7659150c 370 buf = host->sg_miter.addr;
d129bceb 371
7659150c
PO		 372 while (len) {
373 if (chunk == 0) {
4e4141a5 374 scratch = sdhci_readl(host, SDHCI_BUFFER);
7659150c 375 chunk = 4;
a406f5a3 376 }
7659150c
PO		 377
378 *buf = scratch & 0xFF;
379
380 buf++;
381 scratch >>= 8;
382 chunk--;
383 len--;
d129bceb 384 }
a406f5a3 385 }
7659150c
PO		 386
387 sg_miter_stop(&host->sg_miter);
388
389 local_irq_restore(flags);
a406f5a3 390}
d129bceb 391
a406f5a3
PO		 392static void sdhci_write_block_pio(struct sdhci_host *host)
393{
7659150c
PO		 394 unsigned long flags;
395 size_t blksize, len, chunk;
396 u32 scratch;
397 u8 *buf;
d129bceb 398
a406f5a3
PO		 399 DBG("PIO writing\n");
400
401 blksize = host->data->blksz;
7659150c
PO		 402 chunk = 0;
403 scratch = 0;
d129bceb 404
7659150c 405 local_irq_save(flags);
d129bceb 406
a406f5a3 407 while (blksize) {
bf3a35ac 408 BUG_ON(!sg_miter_next(&host->sg_miter));
a406f5a3 409
7659150c
PO		 410 len = min(host->sg_miter.length, blksize);
411
412 blksize -= len;
413 host->sg_miter.consumed = len;
414
415 buf = host->sg_miter.addr;
d129bceb 416
7659150c
PO		 417 while (len) {
418 scratch |= (u32)*buf << (chunk * 8);
419
420 buf++;
421 chunk++;
422 len--;
423
424 if ((chunk == 4) || ((len == 0) && (blksize == 0))) {
4e4141a5 425 sdhci_writel(host, scratch, SDHCI_BUFFER);
7659150c
PO		 426 chunk = 0;
427 scratch = 0;
d129bceb 428 }
d129bceb
PO		 429 }
430 }
7659150c
PO		 431
432 sg_miter_stop(&host->sg_miter);
433
434 local_irq_restore(flags);
a406f5a3
PO		 435}
436
437static void sdhci_transfer_pio(struct sdhci_host *host)
438{
439 u32 mask;
440
7659150c 441 if (host->blocks == 0)
a406f5a3
PO		 442 return;
443
444 if (host->data->flags & MMC_DATA_READ)
445 mask = SDHCI_DATA_AVAILABLE;
446 else
447 mask = SDHCI_SPACE_AVAILABLE;
448
4a3cba32
PO		 449 /*
450 * Some controllers (JMicron JMB38x) mess up the buffer bits
451 * for transfers < 4 bytes. As long as it is just one block,
452 * we can ignore the bits.
453 */
454 if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) &&
455 (host->data->blocks == 1))
456 mask = ~0;
457
4e4141a5 458 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
3e3bf207
AV		 459 if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY)
460 udelay(100);
461
a406f5a3
PO		 462 if (host->data->flags & MMC_DATA_READ)
463 sdhci_read_block_pio(host);
464 else
465 sdhci_write_block_pio(host);
d129bceb 466
7659150c
PO		 467 host->blocks--;
468 if (host->blocks == 0)
a406f5a3 469 break;
a406f5a3 470 }
d129bceb 471
a406f5a3 472 DBG("PIO transfer complete.\n");
d129bceb
PO		 473}
474
48857d9b 475static int sdhci_pre_dma_transfer(struct sdhci_host *host,
c0999b72 476 struct mmc_data *data, int cookie)
48857d9b
RK		 477{
478 int sg_count;
479
94538e51
RK		 480 /*
481 * If the data buffers are already mapped, return the previous
482 * dma_map_sg() result.
483 */
484 if (data->host_cookie == COOKIE_PRE_MAPPED)
48857d9b 485 return data->sg_count;
48857d9b
RK		 486
487 sg_count = dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
488 data->flags & MMC_DATA_WRITE ?
489 DMA_TO_DEVICE : DMA_FROM_DEVICE);
490
491 if (sg_count == 0)
492 return -ENOSPC;
493
494 data->sg_count = sg_count;
c0999b72 495 data->host_cookie = cookie;
48857d9b
RK		 496
497 return sg_count;
498}
499
2134a922
PO		 500static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags)
501{
502 local_irq_save(*flags);
482fce99 503 return kmap_atomic(sg_page(sg)) + sg->offset;
2134a922
PO		 504}
505
506static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags)
507{
482fce99 508 kunmap_atomic(buffer);
2134a922
PO		 509 local_irq_restore(*flags);
510}
511
e57a5f61
AH		 512static void sdhci_adma_write_desc(struct sdhci_host *host, void *desc,
513 dma_addr_t addr, int len, unsigned cmd)
118cd17d 514{
e57a5f61 515 struct sdhci_adma2_64_desc *dma_desc = desc;
118cd17d 516
e57a5f61 517 /* 32-bit and 64-bit descriptors have these members in same position */
0545230f
AH		 518 dma_desc->cmd = cpu_to_le16(cmd);
519 dma_desc->len = cpu_to_le16(len);
e57a5f61
AH		 520 dma_desc->addr_lo = cpu_to_le32((u32)addr);
521
522 if (host->flags & SDHCI_USE_64_BIT_DMA)
523 dma_desc->addr_hi = cpu_to_le32((u64)addr >> 32);
118cd17d
BD		 524}
525
b5ffa674
AH		 526static void sdhci_adma_mark_end(void *desc)
527{
e57a5f61 528 struct sdhci_adma2_64_desc *dma_desc = desc;
b5ffa674 529
e57a5f61 530 /* 32-bit and 64-bit descriptors have 'cmd' in same position */
0545230f 531 dma_desc->cmd |= cpu_to_le16(ADMA2_END);
b5ffa674
AH		 532}
533
60c64762
RK		 534static void sdhci_adma_table_pre(struct sdhci_host *host,
535 struct mmc_data *data, int sg_count)
2134a922 536{
2134a922 537 struct scatterlist *sg;
2134a922 538 unsigned long flags;
acc3ad13
RK		 539 dma_addr_t addr, align_addr;
540 void *desc, *align;
541 char *buffer;
542 int len, offset, i;
2134a922
PO		 543
544 /*
545 * The spec does not specify endianness of descriptor table.
546 * We currently guess that it is LE.
547 */
548
60c64762 549 host->sg_count = sg_count;
2134a922 550
4efaa6fb 551 desc = host->adma_table;
2134a922
PO		 552 align = host->align_buffer;
553
554 align_addr = host->align_addr;
555
556 for_each_sg(data->sg, sg, host->sg_count, i) {
557 addr = sg_dma_address(sg);
558 len = sg_dma_len(sg);
559
560 /*
acc3ad13
RK		 561 * The SDHCI specification states that ADMA addresses must
562 * be 32-bit aligned. If they aren't, then we use a bounce
563 * buffer for the (up to three) bytes that screw up the
2134a922
PO		 564 * alignment.
565 */
04a5ae6f
AH		 566 offset = (SDHCI_ADMA2_ALIGN - (addr & SDHCI_ADMA2_MASK)) &
567 SDHCI_ADMA2_MASK;
2134a922
PO		 568 if (offset) {
569 if (data->flags & MMC_DATA_WRITE) {
570 buffer = sdhci_kmap_atomic(sg, &flags);
571 memcpy(align, buffer, offset);
572 sdhci_kunmap_atomic(buffer, &flags);
573 }
574
118cd17d 575 /* tran, valid */
e57a5f61 576 sdhci_adma_write_desc(host, desc, align_addr, offset,
739d46dc 577 ADMA2_TRAN_VALID);
2134a922
PO		 578
579 BUG_ON(offset > 65536);
580
04a5ae6f
AH		 581 align += SDHCI_ADMA2_ALIGN;
582 align_addr += SDHCI_ADMA2_ALIGN;
2134a922 583
76fe379a 584 desc += host->desc_sz;
2134a922
PO		 585
586 addr += offset;
587 len -= offset;
588 }
589
2134a922
PO		 590 BUG_ON(len > 65536);
591
347ea32d
AH		 592 if (len) {
593 /* tran, valid */
594 sdhci_adma_write_desc(host, desc, addr, len,
595 ADMA2_TRAN_VALID);
596 desc += host->desc_sz;
597 }
2134a922
PO		 598
599 /*
600 * If this triggers then we have a calculation bug
601 * somewhere. :/
602 */
76fe379a 603 WARN_ON((desc - host->adma_table) >= host->adma_table_sz);
2134a922
PO		 604 }
605
70764a90 606 if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) {
acc3ad13 607 /* Mark the last descriptor as the terminating descriptor */
4efaa6fb 608 if (desc != host->adma_table) {
76fe379a 609 desc -= host->desc_sz;
b5ffa674 610 sdhci_adma_mark_end(desc);
70764a90
TA		 611 }
612 } else {
acc3ad13 613 /* Add a terminating entry - nop, end, valid */
e57a5f61 614 sdhci_adma_write_desc(host, desc, 0, 0, ADMA2_NOP_END_VALID);
70764a90 615 }
2134a922
PO		 616}
617
618static void sdhci_adma_table_post(struct sdhci_host *host,
619 struct mmc_data *data)
620{
2134a922
PO		 621 struct scatterlist *sg;
622 int i, size;
1c3d5f6d 623 void *align;
2134a922
PO		 624 char *buffer;
625 unsigned long flags;
626
47fa9613
RK		 627 if (data->flags & MMC_DATA_READ) {
628 bool has_unaligned = false;
de0b65a7 629
47fa9613
RK		 630 /* Do a quick scan of the SG list for any unaligned mappings */
631 for_each_sg(data->sg, sg, host->sg_count, i)
632 if (sg_dma_address(sg) & SDHCI_ADMA2_MASK) {
633 has_unaligned = true;
634 break;
635 }
2134a922 636
47fa9613
RK		 637 if (has_unaligned) {
638 dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
f55c98f7 639 data->sg_len, DMA_FROM_DEVICE);
2134a922 640
47fa9613 641 align = host->align_buffer;
2134a922 642
47fa9613
RK		 643 for_each_sg(data->sg, sg, host->sg_count, i) {
644 if (sg_dma_address(sg) & SDHCI_ADMA2_MASK) {
645 size = SDHCI_ADMA2_ALIGN -
646 (sg_dma_address(sg) & SDHCI_ADMA2_MASK);
647
648 buffer = sdhci_kmap_atomic(sg, &flags);
649 memcpy(buffer, align, size);
650 sdhci_kunmap_atomic(buffer, &flags);
2134a922 651
47fa9613
RK		 652 align += SDHCI_ADMA2_ALIGN;
653 }
2134a922
PO		 654 }
655 }
656 }
2134a922
PO		 657}
658
a3c7778f 659static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd)
d129bceb 660{
1c8cde92 661 u8 count;
a3c7778f 662 struct mmc_data *data = cmd->data;
1c8cde92 663 unsigned target_timeout, current_timeout;
d129bceb 664
ee53ab5d
PO		 665 /*
666 * If the host controller provides us with an incorrect timeout
667 * value, just skip the check and use 0xE. The hardware may take
668 * longer to time out, but that's much better than having a too-short
669 * timeout value.
670 */
11a2f1b7 671 if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL)
ee53ab5d 672 return 0xE;
e538fbe8 673
a3c7778f 674 /* Unspecified timeout, assume max */
1d4d7744 675 if (!data && !cmd->busy_timeout)
a3c7778f 676 return 0xE;
d129bceb 677
a3c7778f
AW		 678 /* timeout in us */
679 if (!data)
1d4d7744 680 target_timeout = cmd->busy_timeout * 1000;
78a2ca27 681 else {
fafcfda9 682 target_timeout = DIV_ROUND_UP(data->timeout_ns, 1000);
7f05538a
RK		 683 if (host->clock && data->timeout_clks) {
684 unsigned long long val;
685
686 /*
687 * data->timeout_clks is in units of clock cycles.
688 * host->clock is in Hz. target_timeout is in us.
689 * Hence, us = 1000000 * cycles / Hz. Round up.
690 */
02265cd6 691 val = 1000000ULL * data->timeout_clks;
7f05538a
RK		 692 if (do_div(val, host->clock))
693 target_timeout++;
694 target_timeout += val;
695 }
78a2ca27 696 }
81b39802 697
1c8cde92
PO		 698 /*
699 * Figure out needed cycles.
700 * We do this in steps in order to fit inside a 32 bit int.
701 * The first step is the minimum timeout, which will have a
702 * minimum resolution of 6 bits:
703 * (1) 2^13*1000 > 2^22,
704 * (2) host->timeout_clk < 2^16
705 * =>
706 * (1) / (2) > 2^6
707 */
708 count = 0;
709 current_timeout = (1 << 13) * 1000 / host->timeout_clk;
710 while (current_timeout < target_timeout) {
711 count++;
712 current_timeout <<= 1;
713 if (count >= 0xF)
714 break;
715 }
716
717 if (count >= 0xF) {
09eeff52
CB		 718 DBG("%s: Too large timeout 0x%x requested for CMD%d!\n",
719 mmc_hostname(host->mmc), count, cmd->opcode);
1c8cde92
PO		 720 count = 0xE;
721 }
722
ee53ab5d
PO		 723 return count;
724}
725
6aa943ab
AV		 726static void sdhci_set_transfer_irqs(struct sdhci_host *host)
727{
728 u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL;
729 u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR;
730
731 if (host->flags & SDHCI_REQ_USE_DMA)
b537f94c 732 host->ier = (host->ier & ~pio_irqs) | dma_irqs;
6aa943ab 733 else
b537f94c
RK		 734 host->ier = (host->ier & ~dma_irqs) | pio_irqs;
735
736 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
737 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
6aa943ab
AV		 738}
739
b45e668a 740static void sdhci_set_timeout(struct sdhci_host *host, struct mmc_command *cmd)
ee53ab5d
PO		 741{
742 u8 count;
b45e668a
AD		 743
744 if (host->ops->set_timeout) {
745 host->ops->set_timeout(host, cmd);
746 } else {
747 count = sdhci_calc_timeout(host, cmd);
748 sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
749 }
750}
751
752static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd)
753{
2134a922 754 u8 ctrl;
a3c7778f 755 struct mmc_data *data = cmd->data;
ee53ab5d 756
56a590dc 757 if (sdhci_data_line_cmd(cmd))
b45e668a 758 sdhci_set_timeout(host, cmd);
a3c7778f
AW		 759
760 if (!data)
ee53ab5d
PO		 761 return;
762
43dea098
AH		 763 WARN_ON(host->data);
764
ee53ab5d
PO		 765 /* Sanity checks */
766 BUG_ON(data->blksz * data->blocks > 524288);
767 BUG_ON(data->blksz > host->mmc->max_blk_size);
768 BUG_ON(data->blocks > 65535);
769
770 host->data = data;
771 host->data_early = 0;
f6a03cbf 772 host->data->bytes_xfered = 0;
ee53ab5d 773
fce14421 774 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2134a922 775 struct scatterlist *sg;
df953925 776 unsigned int length_mask, offset_mask;
a0eaf0f9 777 int i;
2134a922 778
fce14421
RK		 779 host->flags |= SDHCI_REQ_USE_DMA;
780
781 /*
782 * FIXME: This doesn't account for merging when mapping the
783 * scatterlist.
784 *
785 * The assumption here being that alignment and lengths are
786 * the same after DMA mapping to device address space.
787 */
a0eaf0f9 788 length_mask = 0;
df953925 789 offset_mask = 0;
2134a922 790 if (host->flags & SDHCI_USE_ADMA) {
df953925 791 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE) {
a0eaf0f9 792 length_mask = 3;
df953925
RK		 793 /*
794 * As we use up to 3 byte chunks to work
795 * around alignment problems, we need to
796 * check the offset as well.
797 */
798 offset_mask = 3;
799 }
2134a922
PO		 800 } else {
801 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE)
a0eaf0f9 802 length_mask = 3;
df953925
RK		 803 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR)
804 offset_mask = 3;
2134a922
PO		 805 }
806
df953925 807 if (unlikely(length_mask | offset_mask)) {
2134a922 808 for_each_sg(data->sg, sg, data->sg_len, i) {
a0eaf0f9 809 if (sg->length & length_mask) {
2e4456f0 810 DBG("Reverting to PIO because of transfer size (%d)\n",
a0eaf0f9 811 sg->length);
2134a922
PO		 812 host->flags &= ~SDHCI_REQ_USE_DMA;
813 break;
814 }
a0eaf0f9 815 if (sg->offset & offset_mask) {
2e4456f0 816 DBG("Reverting to PIO because of bad alignment\n");
2134a922
PO		 817 host->flags &= ~SDHCI_REQ_USE_DMA;
818 break;
819 }
820 }
821 }
822 }
823
8f1934ce 824 if (host->flags & SDHCI_REQ_USE_DMA) {
c0999b72 825 int sg_cnt = sdhci_pre_dma_transfer(host, data, COOKIE_MAPPED);
60c64762
RK		 826
827 if (sg_cnt <= 0) {
828 /*
829 * This only happens when someone fed
830 * us an invalid request.
831 */
832 WARN_ON(1);
833 host->flags &= ~SDHCI_REQ_USE_DMA;
834 } else if (host->flags & SDHCI_USE_ADMA) {
835 sdhci_adma_table_pre(host, data, sg_cnt);
836
837 sdhci_writel(host, host->adma_addr, SDHCI_ADMA_ADDRESS);
838 if (host->flags & SDHCI_USE_64_BIT_DMA)
839 sdhci_writel(host,
840 (u64)host->adma_addr >> 32,
841 SDHCI_ADMA_ADDRESS_HI);
8f1934ce 842 } else {
60c64762
RK		 843 WARN_ON(sg_cnt != 1);
844 sdhci_writel(host, sg_dma_address(data->sg),
845 SDHCI_DMA_ADDRESS);
8f1934ce
PO		 846 }
847 }
848
2134a922
PO		 849 /*
850 * Always adjust the DMA selection as some controllers
851 * (e.g. JMicron) can't do PIO properly when the selection
852 * is ADMA.
853 */
854 if (host->version >= SDHCI_SPEC_200) {
4e4141a5 855 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
2134a922
PO		 856 ctrl &= ~SDHCI_CTRL_DMA_MASK;
857 if ((host->flags & SDHCI_REQ_USE_DMA) &&
e57a5f61
AH		 858 (host->flags & SDHCI_USE_ADMA)) {
859 if (host->flags & SDHCI_USE_64_BIT_DMA)
860 ctrl |= SDHCI_CTRL_ADMA64;
861 else
862 ctrl |= SDHCI_CTRL_ADMA32;
863 } else {
2134a922 864 ctrl |= SDHCI_CTRL_SDMA;
e57a5f61 865 }
4e4141a5 866 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
c9fddbc4
PO		 867 }
868
8f1934ce 869 if (!(host->flags & SDHCI_REQ_USE_DMA)) {
da60a91d
SAS		 870 int flags;
871
872 flags = SG_MITER_ATOMIC;
873 if (host->data->flags & MMC_DATA_READ)
874 flags |= SG_MITER_TO_SG;
875 else
876 flags |= SG_MITER_FROM_SG;
877 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
7659150c 878 host->blocks = data->blocks;
d129bceb 879 }
c7fa9963 880
6aa943ab
AV		 881 sdhci_set_transfer_irqs(host);
882
f6a03cbf
MV		 883 /* Set the DMA boundary value and block size */
884 sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
885 data->blksz), SDHCI_BLOCK_SIZE);
4e4141a5 886 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
c7fa9963
PO		 887}
888
0293d501
AH		 889static inline bool sdhci_auto_cmd12(struct sdhci_host *host,
890 struct mmc_request *mrq)
891{
20845bef
AH		 892 return !mrq->sbc && (host->flags & SDHCI_AUTO_CMD12) &&
893 !mrq->cap_cmd_during_tfr;
0293d501
AH		 894}
895
c7fa9963 896static void sdhci_set_transfer_mode(struct sdhci_host *host,
e89d456f 897 struct mmc_command *cmd)
c7fa9963 898{
d3fc5d71 899 u16 mode = 0;
e89d456f 900 struct mmc_data *data = cmd->data;
c7fa9963 901
2b558c13 902 if (data == NULL) {
9b8ffea6
VW		 903 if (host->quirks2 &
904 SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD) {
905 sdhci_writew(host, 0x0, SDHCI_TRANSFER_MODE);
906 } else {
2b558c13 907 /* clear Auto CMD settings for no data CMDs */
9b8ffea6
VW		 908 mode = sdhci_readw(host, SDHCI_TRANSFER_MODE);
909 sdhci_writew(host, mode & ~(SDHCI_TRNS_AUTO_CMD12 |
2b558c13 910 SDHCI_TRNS_AUTO_CMD23), SDHCI_TRANSFER_MODE);
9b8ffea6 911 }
c7fa9963 912 return;
2b558c13 913 }
c7fa9963 914
e538fbe8
PO		 915 WARN_ON(!host->data);
916
d3fc5d71
VY		 917 if (!(host->quirks2 & SDHCI_QUIRK2_SUPPORT_SINGLE))
918 mode = SDHCI_TRNS_BLK_CNT_EN;
919
e89d456f 920 if (mmc_op_multi(cmd->opcode) || data->blocks > 1) {
d3fc5d71 921 mode = SDHCI_TRNS_BLK_CNT_EN | SDHCI_TRNS_MULTI;
e89d456f
AW		 922 /*
923 * If we are sending CMD23, CMD12 never gets sent
924 * on successful completion (so no Auto-CMD12).
925 */
0293d501 926 if (sdhci_auto_cmd12(host, cmd->mrq) &&
85cc1c33 927 (cmd->opcode != SD_IO_RW_EXTENDED))
e89d456f 928 mode |= SDHCI_TRNS_AUTO_CMD12;
a4c73aba 929 else if (cmd->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) {
8edf6371 930 mode |= SDHCI_TRNS_AUTO_CMD23;
a4c73aba 931 sdhci_writel(host, cmd->mrq->sbc->arg, SDHCI_ARGUMENT2);
8edf6371 932 }
c4512f79 933 }
8edf6371 934
c7fa9963
PO		 935 if (data->flags & MMC_DATA_READ)
936 mode |= SDHCI_TRNS_READ;
c9fddbc4 937 if (host->flags & SDHCI_REQ_USE_DMA)
c7fa9963
PO		 938 mode |= SDHCI_TRNS_DMA;
939
4e4141a5 940 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
d129bceb
PO		 941}
942
0cc563ce
AH		 943static bool sdhci_needs_reset(struct sdhci_host *host, struct mmc_request *mrq)
944{
945 return (!(host->flags & SDHCI_DEVICE_DEAD) &&
946 ((mrq->cmd && mrq->cmd->error) ||
947 (mrq->sbc && mrq->sbc->error) ||
948 (mrq->data && ((mrq->data->error && !mrq->data->stop) ||
949 (mrq->data->stop && mrq->data->stop->error))) ||
950 (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST)));
951}
952
4e9f8fe5
AH		 953static void __sdhci_finish_mrq(struct sdhci_host *host, struct mmc_request *mrq)
954{
955 int i;
956
957 for (i = 0; i < SDHCI_MAX_MRQS; i++) {
958 if (host->mrqs_done[i] == mrq) {
959 WARN_ON(1);
960 return;
961 }
962 }
963
964 for (i = 0; i < SDHCI_MAX_MRQS; i++) {
965 if (!host->mrqs_done[i]) {
966 host->mrqs_done[i] = mrq;
967 break;
968 }
969 }
970
971 WARN_ON(i >= SDHCI_MAX_MRQS);
972
973 tasklet_schedule(&host->finish_tasklet);
974}
975
a6d3bdd5
AH		 976static void sdhci_finish_mrq(struct sdhci_host *host, struct mmc_request *mrq)
977{
5a8a3fef
AH		 978 if (host->cmd && host->cmd->mrq == mrq)
979 host->cmd = NULL;
980
981 if (host->data_cmd && host->data_cmd->mrq == mrq)
982 host->data_cmd = NULL;
983
984 if (host->data && host->data->mrq == mrq)
985 host->data = NULL;
986
ed1563de
AH		 987 if (sdhci_needs_reset(host, mrq))
988 host->pending_reset = true;
989
4e9f8fe5 990 __sdhci_finish_mrq(host, mrq);
a6d3bdd5
AH		 991}
992
d129bceb
PO		 993static void sdhci_finish_data(struct sdhci_host *host)
994{
33a57adb
AH		 995 struct mmc_command *data_cmd = host->data_cmd;
996 struct mmc_data *data = host->data;
d129bceb 997
d129bceb 998 host->data = NULL;
7c89a3d9 999 host->data_cmd = NULL;
d129bceb 1000
add8913d
RK		 1001 if ((host->flags & (SDHCI_REQ_USE_DMA | SDHCI_USE_ADMA)) ==
1002 (SDHCI_REQ_USE_DMA | SDHCI_USE_ADMA))
1003 sdhci_adma_table_post(host, data);
d129bceb
PO		 1004
1005 /*
c9b74c5b
PO		 1006 * The specification states that the block count register must
1007 * be updated, but it does not specify at what point in the
1008 * data flow. That makes the register entirely useless to read
1009 * back so we have to assume that nothing made it to the card
1010 * in the event of an error.
d129bceb 1011 */
c9b74c5b
PO		 1012 if (data->error)
1013 data->bytes_xfered = 0;
d129bceb 1014 else
c9b74c5b 1015 data->bytes_xfered = data->blksz * data->blocks;
d129bceb 1016
e89d456f
AW		 1017 /*
1018 * Need to send CMD12 if -
1019 * a) open-ended multiblock transfer (no CMD23)
1020 * b) error in multiblock transfer
1021 */
1022 if (data->stop &&
1023 (data->error ||
a4c73aba 1024 !data->mrq->sbc)) {
e89d456f 1025
d129bceb
PO		 1026 /*
1027 * The controller needs a reset of internal state machines
1028 * upon error conditions.
1029 */
17b0429d 1030 if (data->error) {
33a57adb
AH		 1031 if (!host->cmd || host->cmd == data_cmd)
1032 sdhci_do_reset(host, SDHCI_RESET_CMD);
03231f9b 1033 sdhci_do_reset(host, SDHCI_RESET_DATA);
d129bceb
PO		 1034 }
1035
20845bef
AH		 1036 /*
1037 * 'cap_cmd_during_tfr' request must not use the command line
1038 * after mmc_command_done() has been called. It is upper layer's
1039 * responsibility to send the stop command if required.
1040 */
1041 if (data->mrq->cap_cmd_during_tfr) {
1042 sdhci_finish_mrq(host, data->mrq);
1043 } else {
1044 /* Avoid triggering warning in sdhci_send_command() */
1045 host->cmd = NULL;
1046 sdhci_send_command(host, data->stop);
1047 }
a6d3bdd5
AH		 1048 } else {
1049 sdhci_finish_mrq(host, data->mrq);
1050 }
d129bceb
PO		 1051}
1052
d7422fb4
AH		 1053static void sdhci_mod_timer(struct sdhci_host *host, struct mmc_request *mrq,
1054 unsigned long timeout)
1055{
1056 if (sdhci_data_line_cmd(mrq->cmd))
1057 mod_timer(&host->data_timer, timeout);
1058 else
1059 mod_timer(&host->timer, timeout);
1060}
1061
1062static void sdhci_del_timer(struct sdhci_host *host, struct mmc_request *mrq)
1063{
1064 if (sdhci_data_line_cmd(mrq->cmd))
1065 del_timer(&host->data_timer);
1066 else
1067 del_timer(&host->timer);
1068}
1069
c0e55129 1070void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
d129bceb
PO		 1071{
1072 int flags;
fd2208d7 1073 u32 mask;
7cb2c76f 1074 unsigned long timeout;
d129bceb
PO		 1075
1076 WARN_ON(host->cmd);
1077
96776200
RK		 1078 /* Initially, a command has no error */
1079 cmd->error = 0;
1080
fc605f1d
AH		 1081 if ((host->quirks2 & SDHCI_QUIRK2_STOP_WITH_TC) &&
1082 cmd->opcode == MMC_STOP_TRANSMISSION)
1083 cmd->flags |= MMC_RSP_BUSY;
1084
d129bceb 1085 /* Wait max 10 ms */
7cb2c76f 1086 timeout = 10;
fd2208d7
PO		 1087
1088 mask = SDHCI_CMD_INHIBIT;
56a590dc 1089 if (sdhci_data_line_cmd(cmd))
fd2208d7
PO		 1090 mask |= SDHCI_DATA_INHIBIT;
1091
1092 /* We shouldn't wait for data inihibit for stop commands, even
1093 though they might use busy signaling */
a4c73aba 1094 if (cmd->mrq->data && (cmd == cmd->mrq->data->stop))
fd2208d7
PO		 1095 mask &= ~SDHCI_DATA_INHIBIT;
1096
4e4141a5 1097 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
7cb2c76f 1098 if (timeout == 0) {
2e4456f0
MV		 1099 pr_err("%s: Controller never released inhibit bit(s).\n",
1100 mmc_hostname(host->mmc));
d129bceb 1101 sdhci_dumpregs(host);
17b0429d 1102 cmd->error = -EIO;
a6d3bdd5 1103 sdhci_finish_mrq(host, cmd->mrq);
d129bceb
PO		 1104 return;
1105 }
7cb2c76f
PO		 1106 timeout--;
1107 mdelay(1);
1108 }
d129bceb 1109
3e1a6892 1110 timeout = jiffies;
1d4d7744
UH		 1111 if (!cmd->data && cmd->busy_timeout > 9000)
1112 timeout += DIV_ROUND_UP(cmd->busy_timeout, 1000) * HZ + HZ;
3e1a6892
AH		 1113 else
1114 timeout += 10 * HZ;
d7422fb4 1115 sdhci_mod_timer(host, cmd->mrq, timeout);
d129bceb
PO		 1116
1117 host->cmd = cmd;
56a590dc 1118 if (sdhci_data_line_cmd(cmd)) {
7c89a3d9
AH		 1119 WARN_ON(host->data_cmd);
1120 host->data_cmd = cmd;
1121 }
d129bceb 1122
a3c7778f 1123 sdhci_prepare_data(host, cmd);
d129bceb 1124
4e4141a5 1125 sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT);
d129bceb 1126
e89d456f 1127 sdhci_set_transfer_mode(host, cmd);
c7fa9963 1128
d129bceb 1129 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
a3c76eb9 1130 pr_err("%s: Unsupported response type!\n",
d129bceb 1131 mmc_hostname(host->mmc));
17b0429d 1132 cmd->error = -EINVAL;
a6d3bdd5 1133 sdhci_finish_mrq(host, cmd->mrq);
d129bceb
PO		 1134 return;
1135 }
1136
1137 if (!(cmd->flags & MMC_RSP_PRESENT))
1138 flags = SDHCI_CMD_RESP_NONE;
1139 else if (cmd->flags & MMC_RSP_136)
1140 flags = SDHCI_CMD_RESP_LONG;
1141 else if (cmd->flags & MMC_RSP_BUSY)
1142 flags = SDHCI_CMD_RESP_SHORT_BUSY;
1143 else
1144 flags = SDHCI_CMD_RESP_SHORT;
1145
1146 if (cmd->flags & MMC_RSP_CRC)
1147 flags |= SDHCI_CMD_CRC;
1148 if (cmd->flags & MMC_RSP_OPCODE)
1149 flags |= SDHCI_CMD_INDEX;
b513ea25
AN		 1150
1151 /* CMD19 is special in that the Data Present Select should be set */
069c9f14
G		 1152 if (cmd->data || cmd->opcode == MMC_SEND_TUNING_BLOCK ||
1153 cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200)
d129bceb
PO		 1154 flags |= SDHCI_CMD_DATA;
1155
4e4141a5 1156 sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND);
d129bceb 1157}
c0e55129 1158EXPORT_SYMBOL_GPL(sdhci_send_command);
d129bceb
PO		 1159
1160static void sdhci_finish_command(struct sdhci_host *host)
1161{
e0a5640a 1162 struct mmc_command *cmd = host->cmd;
d129bceb
PO		 1163 int i;
1164
e0a5640a
AH		 1165 host->cmd = NULL;
1166
1167 if (cmd->flags & MMC_RSP_PRESENT) {
1168 if (cmd->flags & MMC_RSP_136) {
d129bceb
PO		 1169 /* CRC is stripped so we need to do some shifting. */
1170 for (i = 0;i < 4;i++) {
e0a5640a 1171 cmd->resp[i] = sdhci_readl(host,
d129bceb
PO		 1172 SDHCI_RESPONSE + (3-i)*4) << 8;
1173 if (i != 3)
e0a5640a 1174 cmd->resp[i] |=
4e4141a5 1175 sdhci_readb(host,
d129bceb
PO		 1176 SDHCI_RESPONSE + (3-i)*4-1);
1177 }
1178 } else {
e0a5640a 1179 cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE);
d129bceb
PO		 1180 }
1181 }
1182
20845bef
AH		 1183 if (cmd->mrq->cap_cmd_during_tfr && cmd == cmd->mrq->cmd)
1184 mmc_command_done(host->mmc, cmd->mrq);
1185
6bde8681
AH		 1186 /*
1187 * The host can send and interrupt when the busy state has
1188 * ended, allowing us to wait without wasting CPU cycles.
1189 * The busy signal uses DAT0 so this is similar to waiting
1190 * for data to complete.
1191 *
1192 * Note: The 1.0 specification is a bit ambiguous about this
1193 * feature so there might be some problems with older
1194 * controllers.
1195 */
e0a5640a
AH		 1196 if (cmd->flags & MMC_RSP_BUSY) {
1197 if (cmd->data) {
6bde8681
AH		 1198 DBG("Cannot wait for busy signal when also doing a data transfer");
1199 } else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ) &&
ea968023
AH		 1200 cmd == host->data_cmd) {
1201 /* Command complete before busy is ended */
6bde8681
AH		 1202 return;
1203 }
1204 }
1205
e89d456f 1206 /* Finished CMD23, now send actual command. */
a4c73aba
AH		 1207 if (cmd == cmd->mrq->sbc) {
1208 sdhci_send_command(host, cmd->mrq->cmd);
e89d456f 1209 } else {
e538fbe8 1210
e89d456f
AW		 1211 /* Processed actual command. */
1212 if (host->data && host->data_early)
1213 sdhci_finish_data(host);
d129bceb 1214
e0a5640a 1215 if (!cmd->data)
a6d3bdd5 1216 sdhci_finish_mrq(host, cmd->mrq);
e89d456f 1217 }
d129bceb
PO		 1218}
1219
52983382
KL		 1220static u16 sdhci_get_preset_value(struct sdhci_host *host)
1221{
d975f121 1222 u16 preset = 0;
52983382 1223
d975f121
RK		 1224 switch (host->timing) {
1225 case MMC_TIMING_UHS_SDR12:
52983382
KL		 1226 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1227 break;
d975f121 1228 case MMC_TIMING_UHS_SDR25:
52983382
KL		 1229 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR25);
1230 break;
d975f121 1231 case MMC_TIMING_UHS_SDR50:
52983382
KL		 1232 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR50);
1233 break;
d975f121
RK		 1234 case MMC_TIMING_UHS_SDR104:
1235 case MMC_TIMING_MMC_HS200:
52983382
KL		 1236 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR104);
1237 break;
d975f121 1238 case MMC_TIMING_UHS_DDR50:
0dafa60e 1239 case MMC_TIMING_MMC_DDR52:
52983382
KL		 1240 preset = sdhci_readw(host, SDHCI_PRESET_FOR_DDR50);
1241 break;
e9fb05d5
AH		 1242 case MMC_TIMING_MMC_HS400:
1243 preset = sdhci_readw(host, SDHCI_PRESET_FOR_HS400);
1244 break;
52983382
KL		 1245 default:
1246 pr_warn("%s: Invalid UHS-I mode selected\n",
1247 mmc_hostname(host->mmc));
1248 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1249 break;
1250 }
1251 return preset;
1252}
1253
fb9ee047
LD		 1254u16 sdhci_calc_clk(struct sdhci_host *host, unsigned int clock,
1255 unsigned int *actual_clock)
d129bceb 1256{
c3ed3877 1257 int div = 0; /* Initialized for compiler warning */
df16219f 1258 int real_div = div, clk_mul = 1;
c3ed3877 1259 u16 clk = 0;
5497159c 1260 bool switch_base_clk = false;
d129bceb 1261
85105c53 1262 if (host->version >= SDHCI_SPEC_300) {
da91a8f9 1263 if (host->preset_enabled) {
52983382
KL		 1264 u16 pre_val;
1265
1266 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1267 pre_val = sdhci_get_preset_value(host);
1268 div = (pre_val & SDHCI_PRESET_SDCLK_FREQ_MASK)
1269 >> SDHCI_PRESET_SDCLK_FREQ_SHIFT;
1270 if (host->clk_mul &&
1271 (pre_val & SDHCI_PRESET_CLKGEN_SEL_MASK)) {
1272 clk = SDHCI_PROG_CLOCK_MODE;
1273 real_div = div + 1;
1274 clk_mul = host->clk_mul;
1275 } else {
1276 real_div = max_t(int, 1, div << 1);
1277 }
1278 goto clock_set;
1279 }
1280
c3ed3877
AN		 1281 /*
1282 * Check if the Host Controller supports Programmable Clock
1283 * Mode.
1284 */
1285 if (host->clk_mul) {
52983382
KL		 1286 for (div = 1; div <= 1024; div++) {
1287 if ((host->max_clk * host->clk_mul / div)
1288 <= clock)
1289 break;
1290 }
5497159c 1291 if ((host->max_clk * host->clk_mul / div) <= clock) {
1292 /*
1293 * Set Programmable Clock Mode in the Clock
1294 * Control register.
1295 */
1296 clk = SDHCI_PROG_CLOCK_MODE;
1297 real_div = div;
1298 clk_mul = host->clk_mul;
1299 div--;
1300 } else {
1301 /*
1302 * Divisor can be too small to reach clock
1303 * speed requirement. Then use the base clock.
1304 */
1305 switch_base_clk = true;
1306 }
1307 }
1308
1309 if (!host->clk_mul || switch_base_clk) {
c3ed3877
AN		 1310 /* Version 3.00 divisors must be a multiple of 2. */
1311 if (host->max_clk <= clock)
1312 div = 1;
1313 else {
1314 for (div = 2; div < SDHCI_MAX_DIV_SPEC_300;
1315 div += 2) {
1316 if ((host->max_clk / div) <= clock)
1317 break;
1318 }
85105c53 1319 }
df16219f 1320 real_div = div;
c3ed3877 1321 div >>= 1;
d1955c3a
SG		 1322 if ((host->quirks2 & SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN)
1323 && !div && host->max_clk <= 25000000)
1324 div = 1;
85105c53
ZG		 1325 }
1326 } else {
1327 /* Version 2.00 divisors must be a power of 2. */
0397526d 1328 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
85105c53
ZG		 1329 if ((host->max_clk / div) <= clock)
1330 break;
1331 }
df16219f 1332 real_div = div;
c3ed3877 1333 div >>= 1;
d129bceb 1334 }
d129bceb 1335
52983382 1336clock_set:
03d6f5ff 1337 if (real_div)
fb9ee047 1338 *actual_clock = (host->max_clk * clk_mul) / real_div;
c3ed3877 1339 clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
85105c53
ZG		 1340 clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
1341 << SDHCI_DIVIDER_HI_SHIFT;
fb9ee047
LD		 1342
1343 return clk;
1344}
1345EXPORT_SYMBOL_GPL(sdhci_calc_clk);
1346
fec79673 1347void sdhci_enable_clk(struct sdhci_host *host, u16 clk)
fb9ee047 1348{
fb9ee047
LD		 1349 unsigned long timeout;
1350
d129bceb 1351 clk |= SDHCI_CLOCK_INT_EN;
4e4141a5 1352 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
d129bceb 1353
27f6cb16
CB		 1354 /* Wait max 20 ms */
1355 timeout = 20;
4e4141a5 1356 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
7cb2c76f
PO		 1357 & SDHCI_CLOCK_INT_STABLE)) {
1358 if (timeout == 0) {
2e4456f0
MV		 1359 pr_err("%s: Internal clock never stabilised.\n",
1360 mmc_hostname(host->mmc));
d129bceb
PO		 1361 sdhci_dumpregs(host);
1362 return;
1363 }
7cb2c76f
PO		 1364 timeout--;
1365 mdelay(1);
1366 }
d129bceb
PO		 1367
1368 clk |= SDHCI_CLOCK_CARD_EN;
4e4141a5 1369 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
d129bceb 1370}
fec79673
RH		 1371EXPORT_SYMBOL_GPL(sdhci_enable_clk);
1372
1373void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
1374{
1375 u16 clk;
1376
1377 host->mmc->actual_clock = 0;
1378
1379 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
1380
1381 if (clock == 0)
1382 return;
1383
1384 clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock);
1385 sdhci_enable_clk(host, clk);
1386}
1771059c 1387EXPORT_SYMBOL_GPL(sdhci_set_clock);
d129bceb 1388
1dceb041
AH		 1389static void sdhci_set_power_reg(struct sdhci_host *host, unsigned char mode,
1390 unsigned short vdd)
146ad66e 1391{
3a48edc4 1392 struct mmc_host *mmc = host->mmc;
1dceb041
AH		 1393
1394 spin_unlock_irq(&host->lock);
1395 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd);
1396 spin_lock_irq(&host->lock);
1397
1398 if (mode != MMC_POWER_OFF)
1399 sdhci_writeb(host, SDHCI_POWER_ON, SDHCI_POWER_CONTROL);
1400 else
1401 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1402}
1403
606d3131
AH		 1404void sdhci_set_power_noreg(struct sdhci_host *host, unsigned char mode,
1405 unsigned short vdd)
1dceb041 1406{
8364248a 1407 u8 pwr = 0;
146ad66e 1408
24fbb3ca
RK		 1409 if (mode != MMC_POWER_OFF) {
1410 switch (1 << vdd) {
ae628903
PO		 1411 case MMC_VDD_165_195:
1412 pwr = SDHCI_POWER_180;
1413 break;
1414 case MMC_VDD_29_30:
1415 case MMC_VDD_30_31:
1416 pwr = SDHCI_POWER_300;
1417 break;
1418 case MMC_VDD_32_33:
1419 case MMC_VDD_33_34:
1420 pwr = SDHCI_POWER_330;
1421 break;
1422 default:
9d5de93f
AH		 1423 WARN(1, "%s: Invalid vdd %#x\n",
1424 mmc_hostname(host->mmc), vdd);
1425 break;
ae628903
PO		 1426 }
1427 }
1428
1429 if (host->pwr == pwr)
e921a8b6 1430 return;
146ad66e 1431
ae628903
PO		 1432 host->pwr = pwr;
1433
1434 if (pwr == 0) {
4e4141a5 1435 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
f0710a55
AH		 1436 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
1437 sdhci_runtime_pm_bus_off(host);
e921a8b6
RK		 1438 } else {
1439 /*
1440 * Spec says that we should clear the power reg before setting
1441 * a new value. Some controllers don't seem to like this though.
1442 */
1443 if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
1444 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
146ad66e 1445
e921a8b6
RK		 1446 /*
1447 * At least the Marvell CaFe chip gets confused if we set the
1448 * voltage and set turn on power at the same time, so set the
1449 * voltage first.
1450 */
1451 if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
1452 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
e08c1694 1453
e921a8b6 1454 pwr |= SDHCI_POWER_ON;
146ad66e 1455
e921a8b6 1456 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
557b0697 1457
e921a8b6
RK		 1458 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
1459 sdhci_runtime_pm_bus_on(host);
f0710a55 1460
e921a8b6
RK		 1461 /*
1462 * Some controllers need an extra 10ms delay of 10ms before
1463 * they can apply clock after applying power
1464 */
1465 if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER)
1466 mdelay(10);
1467 }
1dceb041 1468}
606d3131 1469EXPORT_SYMBOL_GPL(sdhci_set_power_noreg);
918f4cbd 1470
606d3131
AH		 1471void sdhci_set_power(struct sdhci_host *host, unsigned char mode,
1472 unsigned short vdd)
1dceb041 1473{
606d3131
AH		 1474 if (IS_ERR(host->mmc->supply.vmmc))
1475 sdhci_set_power_noreg(host, mode, vdd);
1dceb041 1476 else
606d3131 1477 sdhci_set_power_reg(host, mode, vdd);
146ad66e 1478}
606d3131 1479EXPORT_SYMBOL_GPL(sdhci_set_power);
146ad66e 1480
d129bceb
PO		 1481/*****************************************************************************\
1482 * *
1483 * MMC callbacks *
1484 * *
1485\*****************************************************************************/
1486
1487static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1488{
1489 struct sdhci_host *host;
505a8680 1490 int present;
d129bceb
PO		 1491 unsigned long flags;
1492
1493 host = mmc_priv(mmc);
1494
04e079cf 1495 /* Firstly check card presence */
8d28b7a7 1496 present = mmc->ops->get_cd(mmc);
2836766a 1497
d129bceb
PO		 1498 spin_lock_irqsave(&host->lock, flags);
1499
061d17a6 1500 sdhci_led_activate(host);
e89d456f
AW		 1501
1502 /*
1503 * Ensure we don't send the STOP for non-SET_BLOCK_COUNTED
1504 * requests if Auto-CMD12 is enabled.
1505 */
0293d501 1506 if (sdhci_auto_cmd12(host, mrq)) {
c4512f79
JH		 1507 if (mrq->stop) {
1508 mrq->data->stop = NULL;
1509 mrq->stop = NULL;
1510 }
1511 }
d129bceb 1512
68d1fb7e 1513 if (!present || host->flags & SDHCI_DEVICE_DEAD) {
a4c73aba 1514 mrq->cmd->error = -ENOMEDIUM;
a6d3bdd5 1515 sdhci_finish_mrq(host, mrq);
cf2b5eea 1516 } else {
8edf6371 1517 if (mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23))
e89d456f
AW		 1518 sdhci_send_command(host, mrq->sbc);
1519 else
1520 sdhci_send_command(host, mrq->cmd);
cf2b5eea 1521 }
d129bceb 1522
5f25a66f 1523 mmiowb();
d129bceb
PO		 1524 spin_unlock_irqrestore(&host->lock, flags);
1525}
1526
2317f56c
RK		 1527void sdhci_set_bus_width(struct sdhci_host *host, int width)
1528{
1529 u8 ctrl;
1530
1531 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1532 if (width == MMC_BUS_WIDTH_8) {
1533 ctrl &= ~SDHCI_CTRL_4BITBUS;
1534 if (host->version >= SDHCI_SPEC_300)
1535 ctrl |= SDHCI_CTRL_8BITBUS;
1536 } else {
1537 if (host->version >= SDHCI_SPEC_300)
1538 ctrl &= ~SDHCI_CTRL_8BITBUS;
1539 if (width == MMC_BUS_WIDTH_4)
1540 ctrl |= SDHCI_CTRL_4BITBUS;
1541 else
1542 ctrl &= ~SDHCI_CTRL_4BITBUS;
1543 }
1544 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1545}
1546EXPORT_SYMBOL_GPL(sdhci_set_bus_width);
1547
96d7b78c
RK		 1548void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing)
1549{
1550 u16 ctrl_2;
1551
1552 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1553 /* Select Bus Speed Mode for host */
1554 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
1555 if ((timing == MMC_TIMING_MMC_HS200) ||
1556 (timing == MMC_TIMING_UHS_SDR104))
1557 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
1558 else if (timing == MMC_TIMING_UHS_SDR12)
1559 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
1560 else if (timing == MMC_TIMING_UHS_SDR25)
1561 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
1562 else if (timing == MMC_TIMING_UHS_SDR50)
1563 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
1564 else if ((timing == MMC_TIMING_UHS_DDR50) ||
1565 (timing == MMC_TIMING_MMC_DDR52))
1566 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
e9fb05d5
AH		 1567 else if (timing == MMC_TIMING_MMC_HS400)
1568 ctrl_2 |= SDHCI_CTRL_HS400; /* Non-standard */
96d7b78c
RK		 1569 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1570}
1571EXPORT_SYMBOL_GPL(sdhci_set_uhs_signaling);
1572
ded97e0b 1573static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
d129bceb 1574{
ded97e0b 1575 struct sdhci_host *host = mmc_priv(mmc);
d129bceb
PO		 1576 unsigned long flags;
1577 u8 ctrl;
1578
d129bceb
PO		 1579 spin_lock_irqsave(&host->lock, flags);
1580
ceb6143b
AH		 1581 if (host->flags & SDHCI_DEVICE_DEAD) {
1582 spin_unlock_irqrestore(&host->lock, flags);
3a48edc4
TK		 1583 if (!IS_ERR(mmc->supply.vmmc) &&
1584 ios->power_mode == MMC_POWER_OFF)
4e743f1f 1585 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
ceb6143b
AH		 1586 return;
1587 }
1e72859e 1588
d129bceb
PO		 1589 /*
1590 * Reset the chip on each power off.
1591 * Should clear out any weird states.
1592 */
1593 if (ios->power_mode == MMC_POWER_OFF) {
4e4141a5 1594 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
7260cf5e 1595 sdhci_reinit(host);
d129bceb
PO		 1596 }
1597
52983382 1598 if (host->version >= SDHCI_SPEC_300 &&
372c4634
DA		 1599 (ios->power_mode == MMC_POWER_UP) &&
1600 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN))
52983382
KL		 1601 sdhci_enable_preset_value(host, false);
1602
373073ef 1603 if (!ios->clock || ios->clock != host->clock) {
1771059c 1604 host->ops->set_clock(host, ios->clock);
373073ef 1605 host->clock = ios->clock;
03d6f5ff
AD		 1606
1607 if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK &&
1608 host->clock) {
1609 host->timeout_clk = host->mmc->actual_clock ?
1610 host->mmc->actual_clock / 1000 :
1611 host->clock / 1000;
1612 host->mmc->max_busy_timeout =
1613 host->ops->get_max_timeout_count ?
1614 host->ops->get_max_timeout_count(host) :
1615 1 << 27;
1616 host->mmc->max_busy_timeout /= host->timeout_clk;
1617 }
373073ef 1618 }
d129bceb 1619
606d3131
AH		 1620 if (host->ops->set_power)
1621 host->ops->set_power(host, ios->power_mode, ios->vdd);
1622 else
1623 sdhci_set_power(host, ios->power_mode, ios->vdd);
d129bceb 1624
643a81ff
PR		 1625 if (host->ops->platform_send_init_74_clocks)
1626 host->ops->platform_send_init_74_clocks(host, ios->power_mode);
1627
2317f56c 1628 host->ops->set_bus_width(host, ios->bus_width);
ae6d6c92 1629
15ec4461 1630 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
cd9277c0 1631
3ab9c8da 1632 if ((ios->timing == MMC_TIMING_SD_HS ||
273c5414
JC		 1633 ios->timing == MMC_TIMING_MMC_HS ||
1634 ios->timing == MMC_TIMING_MMC_HS400 ||
1635 ios->timing == MMC_TIMING_MMC_HS200 ||
1636 ios->timing == MMC_TIMING_MMC_DDR52 ||
1637 ios->timing == MMC_TIMING_UHS_SDR50 ||
1638 ios->timing == MMC_TIMING_UHS_SDR104 ||
1639 ios->timing == MMC_TIMING_UHS_DDR50 ||
1640 ios->timing == MMC_TIMING_UHS_SDR25)
3ab9c8da 1641 && !(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT))
cd9277c0
PO		 1642 ctrl |= SDHCI_CTRL_HISPD;
1643 else
1644 ctrl &= ~SDHCI_CTRL_HISPD;
1645
d6d50a15 1646 if (host->version >= SDHCI_SPEC_300) {
49c468fc 1647 u16 clk, ctrl_2;
49c468fc 1648
da91a8f9 1649 if (!host->preset_enabled) {
758535c4 1650 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d6d50a15
AN		 1651 /*
1652 * We only need to set Driver Strength if the
1653 * preset value enable is not set.
1654 */
da91a8f9 1655 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
d6d50a15
AN		 1656 ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK;
1657 if (ios->drv_type == MMC_SET_DRIVER_TYPE_A)
1658 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A;
43e943a0
PG		 1659 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_B)
1660 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_B;
d6d50a15
AN		 1661 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C)
1662 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C;
43e943a0
PG		 1663 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_D)
1664 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_D;
1665 else {
2e4456f0
MV		 1666 pr_warn("%s: invalid driver type, default to driver type B\n",
1667 mmc_hostname(mmc));
43e943a0
PG		 1668 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_B;
1669 }
d6d50a15
AN		 1670
1671 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
758535c4
AN		 1672 } else {
1673 /*
1674 * According to SDHC Spec v3.00, if the Preset Value
1675 * Enable in the Host Control 2 register is set, we
1676 * need to reset SD Clock Enable before changing High
1677 * Speed Enable to avoid generating clock gliches.
1678 */
758535c4
AN		 1679
1680 /* Reset SD Clock Enable */
1681 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1682 clk &= ~SDHCI_CLOCK_CARD_EN;
1683 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1684
1685 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1686
1687 /* Re-enable SD Clock */
1771059c 1688 host->ops->set_clock(host, host->clock);
d6d50a15 1689 }
49c468fc 1690
49c468fc
AN		 1691 /* Reset SD Clock Enable */
1692 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1693 clk &= ~SDHCI_CLOCK_CARD_EN;
1694 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1695
96d7b78c 1696 host->ops->set_uhs_signaling(host, ios->timing);
d975f121 1697 host->timing = ios->timing;
49c468fc 1698
52983382
KL		 1699 if (!(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN) &&
1700 ((ios->timing == MMC_TIMING_UHS_SDR12) ||
1701 (ios->timing == MMC_TIMING_UHS_SDR25) ||
1702 (ios->timing == MMC_TIMING_UHS_SDR50) ||
1703 (ios->timing == MMC_TIMING_UHS_SDR104) ||
0dafa60e
JZ		 1704 (ios->timing == MMC_TIMING_UHS_DDR50) ||
1705 (ios->timing == MMC_TIMING_MMC_DDR52))) {
52983382
KL		 1706 u16 preset;
1707
1708 sdhci_enable_preset_value(host, true);
1709 preset = sdhci_get_preset_value(host);
1710 ios->drv_type = (preset & SDHCI_PRESET_DRV_MASK)
1711 >> SDHCI_PRESET_DRV_SHIFT;
1712 }
1713
49c468fc 1714 /* Re-enable SD Clock */
1771059c 1715 host->ops->set_clock(host, host->clock);
758535c4
AN		 1716 } else
1717 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d6d50a15 1718
b8352260
LD		 1719 /*
1720 * Some (ENE) controllers go apeshit on some ios operation,
1721 * signalling timeout and CRC errors even on CMD0. Resetting
1722 * it on each ios seems to solve the problem.
1723 */
c63705e1 1724 if (host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
03231f9b 1725 sdhci_do_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
b8352260 1726
5f25a66f 1727 mmiowb();
d129bceb
PO		 1728 spin_unlock_irqrestore(&host->lock, flags);
1729}
1730
ded97e0b 1731static int sdhci_get_cd(struct mmc_host *mmc)
66fd8ad5
AH		 1732{
1733 struct sdhci_host *host = mmc_priv(mmc);
ded97e0b 1734 int gpio_cd = mmc_gpio_get_cd(mmc);
94144a46
KL		 1735
1736 if (host->flags & SDHCI_DEVICE_DEAD)
1737 return 0;
1738
88af5655 1739 /* If nonremovable, assume that the card is always present. */
860951c5 1740 if (!mmc_card_is_removable(host->mmc))
94144a46
KL		 1741 return 1;
1742
88af5655
II		 1743 /*
1744 * Try slot gpio detect, if defined it take precedence
1745 * over build in controller functionality
1746 */
287980e4 1747 if (gpio_cd >= 0)
94144a46
KL		 1748 return !!gpio_cd;
1749
88af5655
II		 1750 /* If polling, assume that the card is always present. */
1751 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
1752 return 1;
1753
94144a46
KL		 1754 /* Host native card detect */
1755 return !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
1756}
1757
66fd8ad5 1758static int sdhci_check_ro(struct sdhci_host *host)
d129bceb 1759{
d129bceb 1760 unsigned long flags;
2dfb579c 1761 int is_readonly;
d129bceb 1762
d129bceb
PO		 1763 spin_lock_irqsave(&host->lock, flags);
1764
1e72859e 1765 if (host->flags & SDHCI_DEVICE_DEAD)
2dfb579c
WS		 1766 is_readonly = 0;
1767 else if (host->ops->get_ro)
1768 is_readonly = host->ops->get_ro(host);
1e72859e 1769 else
2dfb579c
WS		 1770 is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE)
1771 & SDHCI_WRITE_PROTECT);
d129bceb
PO		 1772
1773 spin_unlock_irqrestore(&host->lock, flags);
1774
2dfb579c
WS		 1775 /* This quirk needs to be replaced by a callback-function later */
1776 return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ?
1777 !is_readonly : is_readonly;
d129bceb
PO		 1778}
1779
82b0e23a
TI		 1780#define SAMPLE_COUNT 5
1781
ded97e0b 1782static int sdhci_get_ro(struct mmc_host *mmc)
82b0e23a 1783{
ded97e0b 1784 struct sdhci_host *host = mmc_priv(mmc);
82b0e23a
TI		 1785 int i, ro_count;
1786
82b0e23a 1787 if (!(host->quirks & SDHCI_QUIRK_UNSTABLE_RO_DETECT))
66fd8ad5 1788 return sdhci_check_ro(host);
82b0e23a
TI		 1789
1790 ro_count = 0;
1791 for (i = 0; i < SAMPLE_COUNT; i++) {
66fd8ad5 1792 if (sdhci_check_ro(host)) {
82b0e23a
TI		 1793 if (++ro_count > SAMPLE_COUNT / 2)
1794 return 1;
1795 }
1796 msleep(30);
1797 }
1798 return 0;
1799}
1800
20758b66
AH		 1801static void sdhci_hw_reset(struct mmc_host *mmc)
1802{
1803 struct sdhci_host *host = mmc_priv(mmc);
1804
1805 if (host->ops && host->ops->hw_reset)
1806 host->ops->hw_reset(host);
1807}
1808
66fd8ad5
AH		 1809static void sdhci_enable_sdio_irq_nolock(struct sdhci_host *host, int enable)
1810{
be138554 1811 if (!(host->flags & SDHCI_DEVICE_DEAD)) {
ef104333 1812 if (enable)
b537f94c 1813 host->ier |= SDHCI_INT_CARD_INT;
ef104333 1814 else
b537f94c
RK		 1815 host->ier &= ~SDHCI_INT_CARD_INT;
1816
1817 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
1818 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
ef104333
RK		 1819 mmiowb();
1820 }
66fd8ad5
AH		 1821}
1822
1823static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1824{
1825 struct sdhci_host *host = mmc_priv(mmc);
1826 unsigned long flags;
f75979b7 1827
66fd8ad5 1828 spin_lock_irqsave(&host->lock, flags);
ef104333
RK		 1829 if (enable)
1830 host->flags |= SDHCI_SDIO_IRQ_ENABLED;
1831 else
1832 host->flags &= ~SDHCI_SDIO_IRQ_ENABLED;
1833
66fd8ad5 1834 sdhci_enable_sdio_irq_nolock(host, enable);
f75979b7
PO		 1835 spin_unlock_irqrestore(&host->lock, flags);
1836}
1837
ded97e0b
DA		 1838static int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
1839 struct mmc_ios *ios)
f2119df6 1840{
ded97e0b 1841 struct sdhci_host *host = mmc_priv(mmc);
20b92a30 1842 u16 ctrl;
6231f3de 1843 int ret;
f2119df6 1844
20b92a30
KL		 1845 /*
1846 * Signal Voltage Switching is only applicable for Host Controllers
1847 * v3.00 and above.
1848 */
1849 if (host->version < SDHCI_SPEC_300)
1850 return 0;
6231f3de 1851
f2119df6 1852 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
f2119df6 1853
21f5998f 1854 switch (ios->signal_voltage) {
20b92a30 1855 case MMC_SIGNAL_VOLTAGE_330:
8cb851a4
AH		 1856 if (!(host->flags & SDHCI_SIGNALING_330))
1857 return -EINVAL;
20b92a30
KL		 1858 /* Set 1.8V Signal Enable in the Host Control2 register to 0 */
1859 ctrl &= ~SDHCI_CTRL_VDD_180;
1860 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
f2119df6 1861
3a48edc4 1862 if (!IS_ERR(mmc->supply.vqmmc)) {
761daa36 1863 ret = mmc_regulator_set_vqmmc(mmc, ios);
20b92a30 1864 if (ret) {
6606110d
JP		 1865 pr_warn("%s: Switching to 3.3V signalling voltage failed\n",
1866 mmc_hostname(mmc));
20b92a30
KL		 1867 return -EIO;
1868 }
1869 }
1870 /* Wait for 5ms */
1871 usleep_range(5000, 5500);
f2119df6 1872
20b92a30
KL		 1873 /* 3.3V regulator output should be stable within 5 ms */
1874 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1875 if (!(ctrl & SDHCI_CTRL_VDD_180))
1876 return 0;
6231f3de 1877
6606110d
JP		 1878 pr_warn("%s: 3.3V regulator output did not became stable\n",
1879 mmc_hostname(mmc));
20b92a30
KL		 1880
1881 return -EAGAIN;
1882 case MMC_SIGNAL_VOLTAGE_180:
8cb851a4
AH		 1883 if (!(host->flags & SDHCI_SIGNALING_180))
1884 return -EINVAL;
3a48edc4 1885 if (!IS_ERR(mmc->supply.vqmmc)) {
761daa36 1886 ret = mmc_regulator_set_vqmmc(mmc, ios);
20b92a30 1887 if (ret) {
6606110d
JP		 1888 pr_warn("%s: Switching to 1.8V signalling voltage failed\n",
1889 mmc_hostname(mmc));
20b92a30
KL		 1890 return -EIO;
1891 }
1892 }
6231f3de 1893
6231f3de
PR		 1894 /*
1895 * Enable 1.8V Signal Enable in the Host Control2
1896 * register
1897 */
20b92a30
KL		 1898 ctrl |= SDHCI_CTRL_VDD_180;
1899 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
6231f3de 1900
9d967a61
VY		 1901 /* Some controller need to do more when switching */
1902 if (host->ops->voltage_switch)
1903 host->ops->voltage_switch(host);
1904
20b92a30
KL		 1905 /* 1.8V regulator output should be stable within 5 ms */
1906 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1907 if (ctrl & SDHCI_CTRL_VDD_180)
1908 return 0;
f2119df6 1909
6606110d
JP		 1910 pr_warn("%s: 1.8V regulator output did not became stable\n",
1911 mmc_hostname(mmc));
f2119df6 1912
20b92a30
KL		 1913 return -EAGAIN;
1914 case MMC_SIGNAL_VOLTAGE_120:
8cb851a4
AH		 1915 if (!(host->flags & SDHCI_SIGNALING_120))
1916 return -EINVAL;
3a48edc4 1917 if (!IS_ERR(mmc->supply.vqmmc)) {
761daa36 1918 ret = mmc_regulator_set_vqmmc(mmc, ios);
20b92a30 1919 if (ret) {
6606110d
JP		 1920 pr_warn("%s: Switching to 1.2V signalling voltage failed\n",
1921 mmc_hostname(mmc));
20b92a30 1922 return -EIO;
f2119df6
AN		 1923 }
1924 }
6231f3de 1925 return 0;
20b92a30 1926 default:
f2119df6
AN		 1927 /* No signal voltage switch required */
1928 return 0;
20b92a30 1929 }
f2119df6
AN		 1930}
1931
20b92a30
KL		 1932static int sdhci_card_busy(struct mmc_host *mmc)
1933{
1934 struct sdhci_host *host = mmc_priv(mmc);
1935 u32 present_state;
1936
e613cc47 1937 /* Check whether DAT[0] is 0 */
20b92a30 1938 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
20b92a30 1939
e613cc47 1940 return !(present_state & SDHCI_DATA_0_LVL_MASK);
20b92a30
KL		 1941}
1942
b5540ce1
AH		 1943static int sdhci_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios)
1944{
1945 struct sdhci_host *host = mmc_priv(mmc);
1946 unsigned long flags;
1947
1948 spin_lock_irqsave(&host->lock, flags);
1949 host->flags |= SDHCI_HS400_TUNING;
1950 spin_unlock_irqrestore(&host->lock, flags);
1951
1952 return 0;
1953}
1954
da4bc4f2
AH		 1955static void sdhci_start_tuning(struct sdhci_host *host)
1956{
1957 u16 ctrl;
1958
1959 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1960 ctrl |= SDHCI_CTRL_EXEC_TUNING;
1961 if (host->quirks2 & SDHCI_QUIRK2_TUNING_WORK_AROUND)
1962 ctrl |= SDHCI_CTRL_TUNED_CLK;
1963 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1964
1965 /*
1966 * As per the Host Controller spec v3.00, tuning command
1967 * generates Buffer Read Ready interrupt, so enable that.
1968 *
1969 * Note: The spec clearly says that when tuning sequence
1970 * is being performed, the controller does not generate
1971 * interrupts other than Buffer Read Ready interrupt. But
1972 * to make sure we don't hit a controller bug, we _only_
1973 * enable Buffer Read Ready interrupt here.
1974 */
1975 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE);
1976 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE);
1977}
1978
1979static void sdhci_end_tuning(struct sdhci_host *host)
1980{
1981 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
1982 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
1983}
1984
1985static void sdhci_reset_tuning(struct sdhci_host *host)
1986{
1987 u16 ctrl;
1988
1989 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1990 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
1991 ctrl &= ~SDHCI_CTRL_EXEC_TUNING;
1992 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1993}
1994
1995static void sdhci_abort_tuning(struct sdhci_host *host, u32 opcode,
1996 unsigned long flags)
1997{
1998 sdhci_reset_tuning(host);
1999
2000 sdhci_do_reset(host, SDHCI_RESET_CMD);
2001 sdhci_do_reset(host, SDHCI_RESET_DATA);
2002
2003 sdhci_end_tuning(host);
2004
2005 spin_unlock_irqrestore(&host->lock, flags);
2006 mmc_abort_tuning(host->mmc, opcode);
2007 spin_lock_irqsave(&host->lock, flags);
2008}
2009
2010/*
2011 * We use sdhci_send_tuning() because mmc_send_tuning() is not a good fit. SDHCI
2012 * tuning command does not have a data payload (or rather the hardware does it
2013 * automatically) so mmc_send_tuning() will return -EIO. Also the tuning command
2014 * interrupt setup is different to other commands and there is no timeout
2015 * interrupt so special handling is needed.
2016 */
2017static void sdhci_send_tuning(struct sdhci_host *host, u32 opcode,
2018 unsigned long flags)
2019{
2020 struct mmc_host *mmc = host->mmc;
2021 struct mmc_command cmd = {0};
2022 struct mmc_request mrq = {NULL};
2023
2024 cmd.opcode = opcode;
2025 cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
2026 cmd.mrq = &mrq;
2027
2028 mrq.cmd = &cmd;
2029 /*
2030 * In response to CMD19, the card sends 64 bytes of tuning
2031 * block to the Host Controller. So we set the block size
2032 * to 64 here.
2033 */
85336109
AH		 2034 if (cmd.opcode == MMC_SEND_TUNING_BLOCK_HS200 &&
2035 mmc->ios.bus_width == MMC_BUS_WIDTH_8)
2036 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 128), SDHCI_BLOCK_SIZE);
2037 else
2038 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64), SDHCI_BLOCK_SIZE);
da4bc4f2
AH		 2039
2040 /*
2041 * The tuning block is sent by the card to the host controller.
2042 * So we set the TRNS_READ bit in the Transfer Mode register.
2043 * This also takes care of setting DMA Enable and Multi Block
2044 * Select in the same register to 0.
2045 */
2046 sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
2047
2048 sdhci_send_command(host, &cmd);
2049
2050 host->cmd = NULL;
2051
2052 sdhci_del_timer(host, &mrq);
2053
2054 host->tuning_done = 0;
2055
2056 spin_unlock_irqrestore(&host->lock, flags);
2057
2058 /* Wait for Buffer Read Ready interrupt */
2059 wait_event_timeout(host->buf_ready_int, (host->tuning_done == 1),
2060 msecs_to_jiffies(50));
2061
2062 spin_lock_irqsave(&host->lock, flags);
2063}
2064
6b11e70b
AH		 2065static void __sdhci_execute_tuning(struct sdhci_host *host, u32 opcode,
2066 unsigned long flags)
2067{
2068 int i;
2069
2070 /*
2071 * Issue opcode repeatedly till Execute Tuning is set to 0 or the number
2072 * of loops reaches 40 times.
2073 */
2074 for (i = 0; i < MAX_TUNING_LOOP; i++) {
2075 u16 ctrl;
2076
2077 sdhci_send_tuning(host, opcode, flags);
2078
2079 if (!host->tuning_done) {
2080 pr_info("%s: Tuning timeout, falling back to fixed sampling clock\n",
2081 mmc_hostname(host->mmc));
2082 sdhci_abort_tuning(host, opcode, flags);
2083 return;
2084 }
2085
2086 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2087 if (!(ctrl & SDHCI_CTRL_EXEC_TUNING)) {
2088 if (ctrl & SDHCI_CTRL_TUNED_CLK)
2089 return; /* Success! */
2090 break;
2091 }
2092
2093 /* eMMC spec does not require a delay between tuning cycles */
2094 if (opcode == MMC_SEND_TUNING_BLOCK)
2095 mdelay(1);
2096 }
2097
2098 pr_info("%s: Tuning failed, falling back to fixed sampling clock\n",
2099 mmc_hostname(host->mmc));
2100 sdhci_reset_tuning(host);
2101}
2102
069c9f14 2103static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode)
b513ea25 2104{
4b6f37d3 2105 struct sdhci_host *host = mmc_priv(mmc);
b513ea25 2106 int err = 0;
2b35bd83 2107 unsigned long flags;
38e40bf5 2108 unsigned int tuning_count = 0;
b5540ce1 2109 bool hs400_tuning;
b513ea25 2110
2b35bd83 2111 spin_lock_irqsave(&host->lock, flags);
b513ea25 2112
b5540ce1
AH		 2113 hs400_tuning = host->flags & SDHCI_HS400_TUNING;
2114 host->flags &= ~SDHCI_HS400_TUNING;
2115
38e40bf5
AH		 2116 if (host->tuning_mode == SDHCI_TUNING_MODE_1)
2117 tuning_count = host->tuning_count;
2118
b513ea25 2119 /*
9faac7b9
WY		 2120 * The Host Controller needs tuning in case of SDR104 and DDR50
2121 * mode, and for SDR50 mode when Use Tuning for SDR50 is set in
2122 * the Capabilities register.
069c9f14
G		 2123 * If the Host Controller supports the HS200 mode then the
2124 * tuning function has to be executed.
b513ea25 2125 */
4b6f37d3 2126 switch (host->timing) {
b5540ce1 2127 /* HS400 tuning is done in HS200 mode */
e9fb05d5 2128 case MMC_TIMING_MMC_HS400:
b5540ce1
AH		 2129 err = -EINVAL;
2130 goto out_unlock;
2131
4b6f37d3 2132 case MMC_TIMING_MMC_HS200:
b5540ce1
AH		 2133 /*
2134 * Periodic re-tuning for HS400 is not expected to be needed, so
2135 * disable it here.
2136 */
2137 if (hs400_tuning)
2138 tuning_count = 0;
2139 break;
2140
4b6f37d3 2141 case MMC_TIMING_UHS_SDR104:
9faac7b9 2142 case MMC_TIMING_UHS_DDR50:
4b6f37d3
RK		 2143 break;
2144
2145 case MMC_TIMING_UHS_SDR50:
4228b213 2146 if (host->flags & SDHCI_SDR50_NEEDS_TUNING)
4b6f37d3
RK		 2147 break;
2148 /* FALLTHROUGH */
2149
2150 default:
d519c863 2151 goto out_unlock;
b513ea25
AN		 2152 }
2153
45251812 2154 if (host->ops->platform_execute_tuning) {
2b35bd83 2155 spin_unlock_irqrestore(&host->lock, flags);
6b11e70b 2156 return host->ops->platform_execute_tuning(host, opcode);
45251812
DA		 2157 }
2158
6b11e70b 2159 host->mmc->retune_period = tuning_count;
b513ea25 2160
6b11e70b 2161 sdhci_start_tuning(host);
da4bc4f2 2162
6b11e70b 2163 __sdhci_execute_tuning(host, opcode, flags);
cf2b5eea 2164
da4bc4f2 2165 sdhci_end_tuning(host);
d519c863 2166out_unlock:
2b35bd83 2167 spin_unlock_irqrestore(&host->lock, flags);
6b11e70b 2168
b513ea25
AN		 2169 return err;
2170}
2171
cb849648
AH		 2172static int sdhci_select_drive_strength(struct mmc_card *card,
2173 unsigned int max_dtr, int host_drv,
2174 int card_drv, int *drv_type)
2175{
2176 struct sdhci_host *host = mmc_priv(card->host);
2177
2178 if (!host->ops->select_drive_strength)
2179 return 0;
2180
2181 return host->ops->select_drive_strength(host, card, max_dtr, host_drv,
2182 card_drv, drv_type);
2183}
52983382
KL		 2184
2185static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable)
4d55c5a1 2186{
4d55c5a1
AN		 2187 /* Host Controller v3.00 defines preset value registers */
2188 if (host->version < SDHCI_SPEC_300)
2189 return;
2190
4d55c5a1
AN		 2191 /*
2192 * We only enable or disable Preset Value if they are not already
2193 * enabled or disabled respectively. Otherwise, we bail out.
2194 */
da91a8f9
RK		 2195 if (host->preset_enabled != enable) {
2196 u16 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2197
2198 if (enable)
2199 ctrl |= SDHCI_CTRL_PRESET_VAL_ENABLE;
2200 else
2201 ctrl &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
2202
4d55c5a1 2203 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
da91a8f9
RK		 2204
2205 if (enable)
2206 host->flags |= SDHCI_PV_ENABLED;
2207 else
2208 host->flags &= ~SDHCI_PV_ENABLED;
2209
2210 host->preset_enabled = enable;
4d55c5a1 2211 }
66fd8ad5
AH		 2212}
2213
348487cb
HC		 2214static void sdhci_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
2215 int err)
2216{
2217 struct sdhci_host *host = mmc_priv(mmc);
2218 struct mmc_data *data = mrq->data;
2219
f48f039c 2220 if (data->host_cookie != COOKIE_UNMAPPED)
771a3dc2
RK		 2221 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
2222 data->flags & MMC_DATA_WRITE ?
2223 DMA_TO_DEVICE : DMA_FROM_DEVICE);
2224
2225 data->host_cookie = COOKIE_UNMAPPED;
348487cb
HC		 2226}
2227
d3c6aac3 2228static void sdhci_pre_req(struct mmc_host *mmc, struct mmc_request *mrq)
348487cb
HC		 2229{
2230 struct sdhci_host *host = mmc_priv(mmc);
2231
d31911b9 2232 mrq->data->host_cookie = COOKIE_UNMAPPED;
348487cb
HC		 2233
2234 if (host->flags & SDHCI_REQ_USE_DMA)
94538e51 2235 sdhci_pre_dma_transfer(host, mrq->data, COOKIE_PRE_MAPPED);
348487cb
HC		 2236}
2237
5d0d11c5
AH		 2238static inline bool sdhci_has_requests(struct sdhci_host *host)
2239{
2240 return host->cmd || host->data_cmd;
2241}
2242
2243static void sdhci_error_out_mrqs(struct sdhci_host *host, int err)
2244{
2245 if (host->data_cmd) {
2246 host->data_cmd->error = err;
2247 sdhci_finish_mrq(host, host->data_cmd->mrq);
2248 }
2249
2250 if (host->cmd) {
2251 host->cmd->error = err;
2252 sdhci_finish_mrq(host, host->cmd->mrq);
2253 }
2254}
2255
71e69211 2256static void sdhci_card_event(struct mmc_host *mmc)
d129bceb 2257{
71e69211 2258 struct sdhci_host *host = mmc_priv(mmc);
d129bceb 2259 unsigned long flags;
2836766a 2260 int present;
d129bceb 2261
722e1280
CD		 2262 /* First check if client has provided their own card event */
2263 if (host->ops->card_event)
2264 host->ops->card_event(host);
2265
d3940f27 2266 present = mmc->ops->get_cd(mmc);
2836766a 2267
d129bceb
PO		 2268 spin_lock_irqsave(&host->lock, flags);
2269
5d0d11c5
AH		 2270 /* Check sdhci_has_requests() first in case we are runtime suspended */
2271 if (sdhci_has_requests(host) && !present) {
a3c76eb9 2272 pr_err("%s: Card removed during transfer!\n",
66fd8ad5 2273 mmc_hostname(host->mmc));
a3c76eb9 2274 pr_err("%s: Resetting controller.\n",
66fd8ad5 2275 mmc_hostname(host->mmc));
d129bceb 2276
03231f9b
RK		 2277 sdhci_do_reset(host, SDHCI_RESET_CMD);
2278 sdhci_do_reset(host, SDHCI_RESET_DATA);
d129bceb 2279
5d0d11c5 2280 sdhci_error_out_mrqs(host, -ENOMEDIUM);
d129bceb
PO		 2281 }
2282
2283 spin_unlock_irqrestore(&host->lock, flags);
71e69211
GL		 2284}
2285
2286static const struct mmc_host_ops sdhci_ops = {
2287 .request = sdhci_request,
348487cb
HC		 2288 .post_req = sdhci_post_req,
2289 .pre_req = sdhci_pre_req,
71e69211 2290 .set_ios = sdhci_set_ios,
94144a46 2291 .get_cd = sdhci_get_cd,
71e69211
GL		 2292 .get_ro = sdhci_get_ro,
2293 .hw_reset = sdhci_hw_reset,
2294 .enable_sdio_irq = sdhci_enable_sdio_irq,
2295 .start_signal_voltage_switch = sdhci_start_signal_voltage_switch,
b5540ce1 2296 .prepare_hs400_tuning = sdhci_prepare_hs400_tuning,
71e69211 2297 .execute_tuning = sdhci_execute_tuning,
cb849648 2298 .select_drive_strength = sdhci_select_drive_strength,
71e69211 2299 .card_event = sdhci_card_event,
20b92a30 2300 .card_busy = sdhci_card_busy,
71e69211
GL		 2301};
2302
2303/*****************************************************************************\
2304 * *
2305 * Tasklets *
2306 * *
2307\*****************************************************************************/
2308
4e9f8fe5 2309static bool sdhci_request_done(struct sdhci_host *host)
d129bceb 2310{
d129bceb
PO		 2311 unsigned long flags;
2312 struct mmc_request *mrq;
4e9f8fe5 2313 int i;
d129bceb 2314
66fd8ad5
AH		 2315 spin_lock_irqsave(&host->lock, flags);
2316
4e9f8fe5
AH		 2317 for (i = 0; i < SDHCI_MAX_MRQS; i++) {
2318 mrq = host->mrqs_done[i];
6ebebeab 2319 if (mrq)
4e9f8fe5 2320 break;
66fd8ad5 2321 }
d129bceb 2322
4e9f8fe5
AH		 2323 if (!mrq) {
2324 spin_unlock_irqrestore(&host->lock, flags);
2325 return true;
2326 }
d129bceb 2327
d7422fb4
AH		 2328 sdhci_del_timer(host, mrq);
2329
054cedff
RK		 2330 /*
2331 * Always unmap the data buffers if they were mapped by
2332 * sdhci_prepare_data() whenever we finish with a request.
2333 * This avoids leaking DMA mappings on error.
2334 */
2335 if (host->flags & SDHCI_REQ_USE_DMA) {
2336 struct mmc_data *data = mrq->data;
2337
2338 if (data && data->host_cookie == COOKIE_MAPPED) {
2339 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
2340 (data->flags & MMC_DATA_READ) ?
2341 DMA_FROM_DEVICE : DMA_TO_DEVICE);
2342 data->host_cookie = COOKIE_UNMAPPED;
2343 }
2344 }
2345
d129bceb
PO		 2346 /*
2347 * The controller needs a reset of internal state machines
2348 * upon error conditions.
2349 */
0cc563ce 2350 if (sdhci_needs_reset(host, mrq)) {
6ebebeab
AH		 2351 /*
2352 * Do not finish until command and data lines are available for
2353 * reset. Note there can only be one other mrq, so it cannot
2354 * also be in mrqs_done, otherwise host->cmd and host->data_cmd
2355 * would both be null.
2356 */
2357 if (host->cmd || host->data_cmd) {
2358 spin_unlock_irqrestore(&host->lock, flags);
2359 return true;
2360 }
2361
645289dc 2362 /* Some controllers need this kick or reset won't work here */
8213af3b 2363 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)
645289dc 2364 /* This is to force an update */
1771059c 2365 host->ops->set_clock(host, host->clock);
645289dc
PO		 2366
2367 /* Spec says we should do both at the same time, but Ricoh
2368 controllers do not like that. */
6ebebeab
AH		 2369 sdhci_do_reset(host, SDHCI_RESET_CMD);
2370 sdhci_do_reset(host, SDHCI_RESET_DATA);
ed1563de
AH		 2371
2372 host->pending_reset = false;
d129bceb
PO		 2373 }
2374
4e9f8fe5
AH		 2375 if (!sdhci_has_requests(host))
2376 sdhci_led_deactivate(host);
d129bceb 2377
6ebebeab
AH		 2378 host->mrqs_done[i] = NULL;
2379
5f25a66f 2380 mmiowb();
d129bceb
PO		 2381 spin_unlock_irqrestore(&host->lock, flags);
2382
2383 mmc_request_done(host->mmc, mrq);
4e9f8fe5
AH		 2384
2385 return false;
2386}
2387
2388static void sdhci_tasklet_finish(unsigned long param)
2389{
2390 struct sdhci_host *host = (struct sdhci_host *)param;
2391
2392 while (!sdhci_request_done(host))
2393 ;
d129bceb
PO		 2394}
2395
2396static void sdhci_timeout_timer(unsigned long data)
2397{
2398 struct sdhci_host *host;
2399 unsigned long flags;
2400
2401 host = (struct sdhci_host*)data;
2402
2403 spin_lock_irqsave(&host->lock, flags);
2404
d7422fb4
AH		 2405 if (host->cmd && !sdhci_data_line_cmd(host->cmd)) {
2406 pr_err("%s: Timeout waiting for hardware cmd interrupt.\n",
2407 mmc_hostname(host->mmc));
2408 sdhci_dumpregs(host);
2409
2410 host->cmd->error = -ETIMEDOUT;
2411 sdhci_finish_mrq(host, host->cmd->mrq);
2412 }
2413
2414 mmiowb();
2415 spin_unlock_irqrestore(&host->lock, flags);
2416}
2417
2418static void sdhci_timeout_data_timer(unsigned long data)
2419{
2420 struct sdhci_host *host;
2421 unsigned long flags;
2422
2423 host = (struct sdhci_host *)data;
2424
2425 spin_lock_irqsave(&host->lock, flags);
2426
2427 if (host->data || host->data_cmd ||
2428 (host->cmd && sdhci_data_line_cmd(host->cmd))) {
2e4456f0
MV		 2429 pr_err("%s: Timeout waiting for hardware interrupt.\n",
2430 mmc_hostname(host->mmc));
d129bceb
PO		 2431 sdhci_dumpregs(host);
2432
2433 if (host->data) {
17b0429d 2434 host->data->error = -ETIMEDOUT;
d129bceb 2435 sdhci_finish_data(host);
d7422fb4
AH		 2436 } else if (host->data_cmd) {
2437 host->data_cmd->error = -ETIMEDOUT;
2438 sdhci_finish_mrq(host, host->data_cmd->mrq);
d129bceb 2439 } else {
d7422fb4
AH		 2440 host->cmd->error = -ETIMEDOUT;
2441 sdhci_finish_mrq(host, host->cmd->mrq);
d129bceb
PO		 2442 }
2443 }
2444
5f25a66f 2445 mmiowb();
d129bceb
PO		 2446 spin_unlock_irqrestore(&host->lock, flags);
2447}
2448
2449/*****************************************************************************\
2450 * *
2451 * Interrupt handling *
2452 * *
2453\*****************************************************************************/
2454
fc605f1d 2455static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask)
d129bceb 2456{
d129bceb 2457 if (!host->cmd) {
ed1563de
AH		 2458 /*
2459 * SDHCI recovers from errors by resetting the cmd and data
2460 * circuits. Until that is done, there very well might be more
2461 * interrupts, so ignore them in that case.
2462 */
2463 if (host->pending_reset)
2464 return;
2e4456f0
MV		 2465 pr_err("%s: Got command interrupt 0x%08x even though no command operation was in progress.\n",
2466 mmc_hostname(host->mmc), (unsigned)intmask);
d129bceb
PO		 2467 sdhci_dumpregs(host);
2468 return;
2469 }
2470
ec014cba
RK		 2471 if (intmask & (SDHCI_INT_TIMEOUT | SDHCI_INT_CRC |
2472 SDHCI_INT_END_BIT | SDHCI_INT_INDEX)) {
2473 if (intmask & SDHCI_INT_TIMEOUT)
2474 host->cmd->error = -ETIMEDOUT;
2475 else
2476 host->cmd->error = -EILSEQ;
43b58b36 2477
71fcbda0
RK		 2478 /*
2479 * If this command initiates a data phase and a response
2480 * CRC error is signalled, the card can start transferring
2481 * data - the card may have received the command without
2482 * error. We must not terminate the mmc_request early.
2483 *
2484 * If the card did not receive the command or returned an
2485 * error which prevented it sending data, the data phase
2486 * will time out.
2487 */
2488 if (host->cmd->data &&
2489 (intmask & (SDHCI_INT_CRC | SDHCI_INT_TIMEOUT)) ==
2490 SDHCI_INT_CRC) {
2491 host->cmd = NULL;
2492 return;
2493 }
2494
a6d3bdd5 2495 sdhci_finish_mrq(host, host->cmd->mrq);
e809517f
PO		 2496 return;
2497 }
2498
e809517f 2499 if (intmask & SDHCI_INT_RESPONSE)
43b58b36 2500 sdhci_finish_command(host);
d129bceb
PO		 2501}
2502
0957c333 2503#ifdef CONFIG_MMC_DEBUG
08621b18 2504static void sdhci_adma_show_error(struct sdhci_host *host)
6882a8c0
BD		 2505{
2506 const char *name = mmc_hostname(host->mmc);
1c3d5f6d 2507 void *desc = host->adma_table;
6882a8c0
BD		 2508
2509 sdhci_dumpregs(host);
2510
2511 while (true) {
e57a5f61
AH		 2512 struct sdhci_adma2_64_desc *dma_desc = desc;
2513
2514 if (host->flags & SDHCI_USE_64_BIT_DMA)
2515 DBG("%s: %p: DMA 0x%08x%08x, LEN 0x%04x, Attr=0x%02x\n",
2516 name, desc, le32_to_cpu(dma_desc->addr_hi),
2517 le32_to_cpu(dma_desc->addr_lo),
2518 le16_to_cpu(dma_desc->len),
2519 le16_to_cpu(dma_desc->cmd));
2520 else
2521 DBG("%s: %p: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n",
2522 name, desc, le32_to_cpu(dma_desc->addr_lo),
2523 le16_to_cpu(dma_desc->len),
2524 le16_to_cpu(dma_desc->cmd));
6882a8c0 2525
76fe379a 2526 desc += host->desc_sz;
6882a8c0 2527
0545230f 2528 if (dma_desc->cmd & cpu_to_le16(ADMA2_END))
6882a8c0
BD		 2529 break;
2530 }
2531}
2532#else
08621b18 2533static void sdhci_adma_show_error(struct sdhci_host *host) { }
6882a8c0
BD		 2534#endif
2535
d129bceb
PO		 2536static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
2537{
069c9f14 2538 u32 command;
d129bceb 2539
b513ea25
AN		 2540 /* CMD19 generates _only_ Buffer Read Ready interrupt */
2541 if (intmask & SDHCI_INT_DATA_AVAIL) {
069c9f14
G		 2542 command = SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND));
2543 if (command == MMC_SEND_TUNING_BLOCK ||
2544 command == MMC_SEND_TUNING_BLOCK_HS200) {
b513ea25
AN		 2545 host->tuning_done = 1;
2546 wake_up(&host->buf_ready_int);
2547 return;
2548 }
2549 }
2550
d129bceb 2551 if (!host->data) {
7c89a3d9
AH		 2552 struct mmc_command *data_cmd = host->data_cmd;
2553
d129bceb 2554 /*
e809517f
PO		 2555 * The "data complete" interrupt is also used to
2556 * indicate that a busy state has ended. See comment
2557 * above in sdhci_cmd_irq().
d129bceb 2558 */
7c89a3d9 2559 if (data_cmd && (data_cmd->flags & MMC_RSP_BUSY)) {
c5abd5e8 2560 if (intmask & SDHCI_INT_DATA_TIMEOUT) {
69b962a6 2561 host->data_cmd = NULL;
7c89a3d9 2562 data_cmd->error = -ETIMEDOUT;
a6d3bdd5 2563 sdhci_finish_mrq(host, data_cmd->mrq);
c5abd5e8
MC		 2564 return;
2565 }
e809517f 2566 if (intmask & SDHCI_INT_DATA_END) {
69b962a6 2567 host->data_cmd = NULL;
e99783a4
CM		 2568 /*
2569 * Some cards handle busy-end interrupt
2570 * before the command completed, so make
2571 * sure we do things in the proper order.
2572 */
ea968023
AH		 2573 if (host->cmd == data_cmd)
2574 return;
2575
a6d3bdd5 2576 sdhci_finish_mrq(host, data_cmd->mrq);
e809517f
PO		 2577 return;
2578 }
2579 }
d129bceb 2580
ed1563de
AH		 2581 /*
2582 * SDHCI recovers from errors by resetting the cmd and data
2583 * circuits. Until that is done, there very well might be more
2584 * interrupts, so ignore them in that case.
2585 */
2586 if (host->pending_reset)
2587 return;
2588
2e4456f0
MV		 2589 pr_err("%s: Got data interrupt 0x%08x even though no data operation was in progress.\n",
2590 mmc_hostname(host->mmc), (unsigned)intmask);
d129bceb
PO		 2591 sdhci_dumpregs(host);
2592
2593 return;
2594 }
2595
2596 if (intmask & SDHCI_INT_DATA_TIMEOUT)
17b0429d 2597 host->data->error = -ETIMEDOUT;
22113efd
AL		 2598 else if (intmask & SDHCI_INT_DATA_END_BIT)
2599 host->data->error = -EILSEQ;
2600 else if ((intmask & SDHCI_INT_DATA_CRC) &&
2601 SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))
2602 != MMC_BUS_TEST_R)
17b0429d 2603 host->data->error = -EILSEQ;
6882a8c0 2604 else if (intmask & SDHCI_INT_ADMA_ERROR) {
a3c76eb9 2605 pr_err("%s: ADMA error\n", mmc_hostname(host->mmc));
08621b18 2606 sdhci_adma_show_error(host);
2134a922 2607 host->data->error = -EIO;
a4071fbb
HZ		 2608 if (host->ops->adma_workaround)
2609 host->ops->adma_workaround(host, intmask);
6882a8c0 2610 }
d129bceb 2611
17b0429d 2612 if (host->data->error)
d129bceb
PO		 2613 sdhci_finish_data(host);
2614 else {
a406f5a3 2615 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
d129bceb
PO		 2616 sdhci_transfer_pio(host);
2617
6ba736a1
PO		 2618 /*
2619 * We currently don't do anything fancy with DMA
2620 * boundaries, but as we can't disable the feature
2621 * we need to at least restart the transfer.
f6a03cbf
MV		 2622 *
2623 * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS)
2624 * should return a valid address to continue from, but as
2625 * some controllers are faulty, don't trust them.
6ba736a1 2626 */
f6a03cbf
MV		 2627 if (intmask & SDHCI_INT_DMA_END) {
2628 u32 dmastart, dmanow;
2629 dmastart = sg_dma_address(host->data->sg);
2630 dmanow = dmastart + host->data->bytes_xfered;
2631 /*
2632 * Force update to the next DMA block boundary.
2633 */
2634 dmanow = (dmanow &
2635 ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) +
2636 SDHCI_DEFAULT_BOUNDARY_SIZE;
2637 host->data->bytes_xfered = dmanow - dmastart;
2638 DBG("%s: DMA base 0x%08x, transferred 0x%06x bytes,"
2639 " next 0x%08x\n",
2640 mmc_hostname(host->mmc), dmastart,
2641 host->data->bytes_xfered, dmanow);
2642 sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS);
2643 }
6ba736a1 2644
e538fbe8 2645 if (intmask & SDHCI_INT_DATA_END) {
7c89a3d9 2646 if (host->cmd == host->data_cmd) {
e538fbe8
PO		 2647 /*
2648 * Data managed to finish before the
2649 * command completed. Make sure we do
2650 * things in the proper order.
2651 */
2652 host->data_early = 1;
2653 } else {
2654 sdhci_finish_data(host);
2655 }
2656 }
d129bceb
PO		 2657 }
2658}
2659
7d12e780 2660static irqreturn_t sdhci_irq(int irq, void *dev_id)
d129bceb 2661{
781e989c 2662 irqreturn_t result = IRQ_NONE;
66fd8ad5 2663 struct sdhci_host *host = dev_id;
41005003 2664 u32 intmask, mask, unexpected = 0;
781e989c 2665 int max_loops = 16;
d129bceb
PO		 2666
2667 spin_lock(&host->lock);
2668
be138554 2669 if (host->runtime_suspended && !sdhci_sdio_irq_enabled(host)) {
66fd8ad5 2670 spin_unlock(&host->lock);
655bca76 2671 return IRQ_NONE;
66fd8ad5
AH		 2672 }
2673
4e4141a5 2674 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
62df67a5 2675 if (!intmask || intmask == 0xffffffff) {
d129bceb
PO		 2676 result = IRQ_NONE;
2677 goto out;
2678 }
2679
41005003
RK		 2680 do {
2681 /* Clear selected interrupts. */
2682 mask = intmask & (SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
2683 SDHCI_INT_BUS_POWER);
2684 sdhci_writel(host, mask, SDHCI_INT_STATUS);
d129bceb 2685
41005003
RK		 2686 DBG("*** %s got interrupt: 0x%08x\n",
2687 mmc_hostname(host->mmc), intmask);
d129bceb 2688
41005003
RK		 2689 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
2690 u32 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
2691 SDHCI_CARD_PRESENT;
d129bceb 2692
41005003
RK		 2693 /*
2694 * There is a observation on i.mx esdhc. INSERT
2695 * bit will be immediately set again when it gets
2696 * cleared, if a card is inserted. We have to mask
2697 * the irq to prevent interrupt storm which will
2698 * freeze the system. And the REMOVE gets the
2699 * same situation.
2700 *
2701 * More testing are needed here to ensure it works
2702 * for other platforms though.
2703 */
b537f94c
RK		 2704 host->ier &= ~(SDHCI_INT_CARD_INSERT |
2705 SDHCI_INT_CARD_REMOVE);
2706 host->ier |= present ? SDHCI_INT_CARD_REMOVE :
2707 SDHCI_INT_CARD_INSERT;
2708 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2709 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
41005003
RK		 2710
2711 sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT |
2712 SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS);
3560db8e
RK		 2713
2714 host->thread_isr |= intmask & (SDHCI_INT_CARD_INSERT |
2715 SDHCI_INT_CARD_REMOVE);
2716 result = IRQ_WAKE_THREAD;
41005003 2717 }
d129bceb 2718
41005003 2719 if (intmask & SDHCI_INT_CMD_MASK)
fc605f1d 2720 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK);
964f9ce2 2721
41005003
RK		 2722 if (intmask & SDHCI_INT_DATA_MASK)
2723 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
d129bceb 2724
41005003
RK		 2725 if (intmask & SDHCI_INT_BUS_POWER)
2726 pr_err("%s: Card is consuming too much power!\n",
2727 mmc_hostname(host->mmc));
3192a28f 2728
f37b20eb
DA		 2729 if (intmask & SDHCI_INT_RETUNE)
2730 mmc_retune_needed(host->mmc);
2731
781e989c
RK		 2732 if (intmask & SDHCI_INT_CARD_INT) {
2733 sdhci_enable_sdio_irq_nolock(host, false);
2734 host->thread_isr |= SDHCI_INT_CARD_INT;
2735 result = IRQ_WAKE_THREAD;
2736 }
f75979b7 2737
41005003
RK		 2738 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE |
2739 SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
2740 SDHCI_INT_ERROR | SDHCI_INT_BUS_POWER |
f37b20eb 2741 SDHCI_INT_RETUNE | SDHCI_INT_CARD_INT);
f75979b7 2742
41005003
RK		 2743 if (intmask) {
2744 unexpected |= intmask;
2745 sdhci_writel(host, intmask, SDHCI_INT_STATUS);
2746 }
d129bceb 2747
781e989c
RK		 2748 if (result == IRQ_NONE)
2749 result = IRQ_HANDLED;
d129bceb 2750
41005003 2751 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
41005003 2752 } while (intmask && --max_loops);
d129bceb
PO		 2753out:
2754 spin_unlock(&host->lock);
2755
6379b237
AS		 2756 if (unexpected) {
2757 pr_err("%s: Unexpected interrupt 0x%08x.\n",
2758 mmc_hostname(host->mmc), unexpected);
2759 sdhci_dumpregs(host);
2760 }
f75979b7 2761
d129bceb
PO		 2762 return result;
2763}
2764
781e989c
RK		 2765static irqreturn_t sdhci_thread_irq(int irq, void *dev_id)
2766{
2767 struct sdhci_host *host = dev_id;
2768 unsigned long flags;
2769 u32 isr;
2770
2771 spin_lock_irqsave(&host->lock, flags);
2772 isr = host->thread_isr;
2773 host->thread_isr = 0;
2774 spin_unlock_irqrestore(&host->lock, flags);
2775
3560db8e 2776 if (isr & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
d3940f27
AH		 2777 struct mmc_host *mmc = host->mmc;
2778
2779 mmc->ops->card_event(mmc);
2780 mmc_detect_change(mmc, msecs_to_jiffies(200));
3560db8e
RK		 2781 }
2782
781e989c
RK		 2783 if (isr & SDHCI_INT_CARD_INT) {
2784 sdio_run_irqs(host->mmc);
2785
2786 spin_lock_irqsave(&host->lock, flags);
2787 if (host->flags & SDHCI_SDIO_IRQ_ENABLED)
2788 sdhci_enable_sdio_irq_nolock(host, true);
2789 spin_unlock_irqrestore(&host->lock, flags);
2790 }
2791
2792 return isr ? IRQ_HANDLED : IRQ_NONE;
2793}
2794
d129bceb
PO		 2795/*****************************************************************************\
2796 * *
2797 * Suspend/resume *
2798 * *
2799\*****************************************************************************/
2800
2801#ifdef CONFIG_PM
84d62605
LD		 2802/*
2803 * To enable wakeup events, the corresponding events have to be enabled in
2804 * the Interrupt Status Enable register too. See 'Table 1-6: Wakeup Signal
2805 * Table' in the SD Host Controller Standard Specification.
2806 * It is useless to restore SDHCI_INT_ENABLE state in
2807 * sdhci_disable_irq_wakeups() since it will be set by
2808 * sdhci_enable_card_detection() or sdhci_init().
2809 */
ad080d79
KL		 2810void sdhci_enable_irq_wakeups(struct sdhci_host *host)
2811{
2812 u8 val;
2813 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
2814 | SDHCI_WAKE_ON_INT;
84d62605
LD		 2815 u32 irq_val = SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE |
2816 SDHCI_INT_CARD_INT;
ad080d79
KL		 2817
2818 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2819 val |= mask ;
2820 /* Avoid fake wake up */
84d62605 2821 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) {
ad080d79 2822 val &= ~(SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE);
84d62605
LD		 2823 irq_val &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE);
2824 }
ad080d79 2825 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
84d62605 2826 sdhci_writel(host, irq_val, SDHCI_INT_ENABLE);
ad080d79
KL		 2827}
2828EXPORT_SYMBOL_GPL(sdhci_enable_irq_wakeups);
2829
0b10f478 2830static void sdhci_disable_irq_wakeups(struct sdhci_host *host)
ad080d79
KL		 2831{
2832 u8 val;
2833 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
2834 | SDHCI_WAKE_ON_INT;
2835
2836 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2837 val &= ~mask;
2838 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2839}
d129bceb 2840
29495aa0 2841int sdhci_suspend_host(struct sdhci_host *host)
d129bceb 2842{
7260cf5e
AV		 2843 sdhci_disable_card_detection(host);
2844
66c39dfc 2845 mmc_retune_timer_stop(host->mmc);
f37b20eb
DA		 2846 if (host->tuning_mode != SDHCI_TUNING_MODE_3)
2847 mmc_retune_needed(host->mmc);
cf2b5eea 2848
ad080d79 2849 if (!device_may_wakeup(mmc_dev(host->mmc))) {
b537f94c
RK		 2850 host->ier = 0;
2851 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
2852 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
ad080d79
KL		 2853 free_irq(host->irq, host);
2854 } else {
2855 sdhci_enable_irq_wakeups(host);
2856 enable_irq_wake(host->irq);
2857 }
4ee14ec6 2858 return 0;
d129bceb
PO		 2859}
2860
b8c86fc5 2861EXPORT_SYMBOL_GPL(sdhci_suspend_host);
d129bceb 2862
b8c86fc5
PO		 2863int sdhci_resume_host(struct sdhci_host *host)
2864{
d3940f27 2865 struct mmc_host *mmc = host->mmc;
4ee14ec6 2866 int ret = 0;
d129bceb 2867
a13abc7b 2868 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
b8c86fc5
PO		 2869 if (host->ops->enable_dma)
2870 host->ops->enable_dma(host);
2871 }
d129bceb 2872
6308d290
AH		 2873 if ((host->mmc->pm_flags & MMC_PM_KEEP_POWER) &&
2874 (host->quirks2 & SDHCI_QUIRK2_HOST_OFF_CARD_ON)) {
2875 /* Card keeps power but host controller does not */
2876 sdhci_init(host, 0);
2877 host->pwr = 0;
2878 host->clock = 0;
d3940f27 2879 mmc->ops->set_ios(mmc, &mmc->ios);
6308d290
AH		 2880 } else {
2881 sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER));
2882 mmiowb();
2883 }
b8c86fc5 2884
14a7b416
HC		 2885 if (!device_may_wakeup(mmc_dev(host->mmc))) {
2886 ret = request_threaded_irq(host->irq, sdhci_irq,
2887 sdhci_thread_irq, IRQF_SHARED,
2888 mmc_hostname(host->mmc), host);
2889 if (ret)
2890 return ret;
2891 } else {
2892 sdhci_disable_irq_wakeups(host);
2893 disable_irq_wake(host->irq);
2894 }
2895
7260cf5e
AV		 2896 sdhci_enable_card_detection(host);
2897
2f4cbb3d 2898 return ret;
d129bceb
PO		 2899}
2900
b8c86fc5 2901EXPORT_SYMBOL_GPL(sdhci_resume_host);
66fd8ad5 2902
66fd8ad5
AH		 2903int sdhci_runtime_suspend_host(struct sdhci_host *host)
2904{
2905 unsigned long flags;
66fd8ad5 2906
66c39dfc 2907 mmc_retune_timer_stop(host->mmc);
f37b20eb
DA		 2908 if (host->tuning_mode != SDHCI_TUNING_MODE_3)
2909 mmc_retune_needed(host->mmc);
66fd8ad5
AH		 2910
2911 spin_lock_irqsave(&host->lock, flags);
b537f94c
RK		 2912 host->ier &= SDHCI_INT_CARD_INT;
2913 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2914 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
66fd8ad5
AH		 2915 spin_unlock_irqrestore(&host->lock, flags);
2916
781e989c 2917 synchronize_hardirq(host->irq);
66fd8ad5
AH		 2918
2919 spin_lock_irqsave(&host->lock, flags);
2920 host->runtime_suspended = true;
2921 spin_unlock_irqrestore(&host->lock, flags);
2922
8a125bad 2923 return 0;
66fd8ad5
AH		 2924}
2925EXPORT_SYMBOL_GPL(sdhci_runtime_suspend_host);
2926
2927int sdhci_runtime_resume_host(struct sdhci_host *host)
2928{
d3940f27 2929 struct mmc_host *mmc = host->mmc;
66fd8ad5 2930 unsigned long flags;
8a125bad 2931 int host_flags = host->flags;
66fd8ad5
AH		 2932
2933 if (host_flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2934 if (host->ops->enable_dma)
2935 host->ops->enable_dma(host);
2936 }
2937
2938 sdhci_init(host, 0);
2939
2940 /* Force clock and power re-program */
2941 host->pwr = 0;
2942 host->clock = 0;
d3940f27
AH		 2943 mmc->ops->start_signal_voltage_switch(mmc, &mmc->ios);
2944 mmc->ops->set_ios(mmc, &mmc->ios);
66fd8ad5 2945
52983382
KL		 2946 if ((host_flags & SDHCI_PV_ENABLED) &&
2947 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN)) {
2948 spin_lock_irqsave(&host->lock, flags);
2949 sdhci_enable_preset_value(host, true);
2950 spin_unlock_irqrestore(&host->lock, flags);
2951 }
66fd8ad5 2952
086b0ddb
AH		 2953 if ((mmc->caps2 & MMC_CAP2_HS400_ES) &&
2954 mmc->ops->hs400_enhanced_strobe)
2955 mmc->ops->hs400_enhanced_strobe(mmc, &mmc->ios);
2956
66fd8ad5
AH		 2957 spin_lock_irqsave(&host->lock, flags);
2958
2959 host->runtime_suspended = false;
2960
2961 /* Enable SDIO IRQ */
ef104333 2962 if (host->flags & SDHCI_SDIO_IRQ_ENABLED)
66fd8ad5
AH		 2963 sdhci_enable_sdio_irq_nolock(host, true);
2964
2965 /* Enable Card Detection */
2966 sdhci_enable_card_detection(host);
2967
2968 spin_unlock_irqrestore(&host->lock, flags);
2969
8a125bad 2970 return 0;
66fd8ad5
AH		 2971}
2972EXPORT_SYMBOL_GPL(sdhci_runtime_resume_host);
2973
162d6f98 2974#endif /* CONFIG_PM */
66fd8ad5 2975
d129bceb
PO		 2976/*****************************************************************************\
2977 * *
b8c86fc5 2978 * Device allocation/registration *
d129bceb
PO		 2979 * *
2980\*****************************************************************************/
2981
b8c86fc5
PO		 2982struct sdhci_host *sdhci_alloc_host(struct device *dev,
2983 size_t priv_size)
d129bceb 2984{
d129bceb
PO		 2985 struct mmc_host *mmc;
2986 struct sdhci_host *host;
2987
b8c86fc5 2988 WARN_ON(dev == NULL);
d129bceb 2989
b8c86fc5 2990 mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev);
d129bceb 2991 if (!mmc)
b8c86fc5 2992 return ERR_PTR(-ENOMEM);
d129bceb
PO		 2993
2994 host = mmc_priv(mmc);
2995 host->mmc = mmc;
bf60e592
AH		 2996 host->mmc_host_ops = sdhci_ops;
2997 mmc->ops = &host->mmc_host_ops;
d129bceb 2998
8cb851a4
AH		 2999 host->flags = SDHCI_SIGNALING_330;
3000
b8c86fc5
PO		 3001 return host;
3002}
8a4da143 3003
b8c86fc5 3004EXPORT_SYMBOL_GPL(sdhci_alloc_host);
d129bceb 3005
7b91369b
AC		 3006static int sdhci_set_dma_mask(struct sdhci_host *host)
3007{
3008 struct mmc_host *mmc = host->mmc;
3009 struct device *dev = mmc_dev(mmc);
3010 int ret = -EINVAL;
3011
3012 if (host->quirks2 & SDHCI_QUIRK2_BROKEN_64_BIT_DMA)
3013 host->flags &= ~SDHCI_USE_64_BIT_DMA;
3014
3015 /* Try 64-bit mask if hardware is capable of it */
3016 if (host->flags & SDHCI_USE_64_BIT_DMA) {
3017 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64));
3018 if (ret) {
3019 pr_warn("%s: Failed to set 64-bit DMA mask.\n",
3020 mmc_hostname(mmc));
3021 host->flags &= ~SDHCI_USE_64_BIT_DMA;
3022 }
3023 }
3024
3025 /* 32-bit mask as default & fallback */
3026 if (ret) {
3027 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32));
3028 if (ret)
3029 pr_warn("%s: Failed to set 32-bit DMA mask.\n",
3030 mmc_hostname(mmc));
3031 }
3032
3033 return ret;
3034}
3035
6132a3bf
AH		 3036void __sdhci_read_caps(struct sdhci_host *host, u16 *ver, u32 *caps, u32 *caps1)
3037{
3038 u16 v;
92e0c44b
ZB		 3039 u64 dt_caps_mask = 0;
3040 u64 dt_caps = 0;
6132a3bf
AH		 3041
3042 if (host->read_caps)
3043 return;
3044
3045 host->read_caps = true;
3046
3047 if (debug_quirks)
3048 host->quirks = debug_quirks;
3049
3050 if (debug_quirks2)
3051 host->quirks2 = debug_quirks2;
3052
3053 sdhci_do_reset(host, SDHCI_RESET_ALL);
3054
92e0c44b
ZB		 3055 of_property_read_u64(mmc_dev(host->mmc)->of_node,
3056 "sdhci-caps-mask", &dt_caps_mask);
3057 of_property_read_u64(mmc_dev(host->mmc)->of_node,
3058 "sdhci-caps", &dt_caps);
3059
6132a3bf
AH		 3060 v = ver ? *ver : sdhci_readw(host, SDHCI_HOST_VERSION);
3061 host->version = (v & SDHCI_SPEC_VER_MASK) >> SDHCI_SPEC_VER_SHIFT;
3062
3063 if (host->quirks & SDHCI_QUIRK_MISSING_CAPS)
3064 return;
3065
92e0c44b
ZB		 3066 if (caps) {
3067 host->caps = *caps;
3068 } else {
3069 host->caps = sdhci_readl(host, SDHCI_CAPABILITIES);
3070 host->caps &= ~lower_32_bits(dt_caps_mask);
3071 host->caps |= lower_32_bits(dt_caps);
3072 }
6132a3bf
AH		 3073
3074 if (host->version < SDHCI_SPEC_300)
3075 return;
3076
92e0c44b
ZB		 3077 if (caps1) {
3078 host->caps1 = *caps1;
3079 } else {
3080 host->caps1 = sdhci_readl(host, SDHCI_CAPABILITIES_1);
3081 host->caps1 &= ~upper_32_bits(dt_caps_mask);
3082 host->caps1 |= upper_32_bits(dt_caps);
3083 }
6132a3bf
AH		 3084}
3085EXPORT_SYMBOL_GPL(__sdhci_read_caps);
3086
52f5336d 3087int sdhci_setup_host(struct sdhci_host *host)
b8c86fc5
PO		 3088{
3089 struct mmc_host *mmc;
f2119df6
AN		 3090 u32 max_current_caps;
3091 unsigned int ocr_avail;
f5fa92e5 3092 unsigned int override_timeout_clk;
59241757 3093 u32 max_clk;
b8c86fc5 3094 int ret;
d129bceb 3095
b8c86fc5
PO		 3096 WARN_ON(host == NULL);
3097 if (host == NULL)
3098 return -EINVAL;
d129bceb 3099
b8c86fc5 3100 mmc = host->mmc;
d129bceb 3101
efba142b
JH		 3102 /*
3103 * If there are external regulators, get them. Note this must be done
3104 * early before resetting the host and reading the capabilities so that
3105 * the host can take the appropriate action if regulators are not
3106 * available.
3107 */
3108 ret = mmc_regulator_get_supply(mmc);
3109 if (ret == -EPROBE_DEFER)
3110 return ret;
3111
6132a3bf 3112 sdhci_read_caps(host);
d129bceb 3113
f5fa92e5
AH		 3114 override_timeout_clk = host->timeout_clk;
3115
85105c53 3116 if (host->version > SDHCI_SPEC_300) {
2e4456f0
MV		 3117 pr_err("%s: Unknown controller version (%d). You may experience problems.\n",
3118 mmc_hostname(mmc), host->version);
4a965505
PO		 3119 }
3120
b8c86fc5 3121 if (host->quirks & SDHCI_QUIRK_FORCE_DMA)
a13abc7b 3122 host->flags |= SDHCI_USE_SDMA;
28da3589 3123 else if (!(host->caps & SDHCI_CAN_DO_SDMA))
a13abc7b 3124 DBG("Controller doesn't have SDMA capability\n");
67435274 3125 else
a13abc7b 3126 host->flags |= SDHCI_USE_SDMA;
d129bceb 3127
b8c86fc5 3128 if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
a13abc7b 3129 (host->flags & SDHCI_USE_SDMA)) {
cee687ce 3130 DBG("Disabling DMA as it is marked broken\n");
a13abc7b 3131 host->flags &= ~SDHCI_USE_SDMA;
7c168e3d
FT		 3132 }
3133
f2119df6 3134 if ((host->version >= SDHCI_SPEC_200) &&
28da3589 3135 (host->caps & SDHCI_CAN_DO_ADMA2))
a13abc7b 3136 host->flags |= SDHCI_USE_ADMA;
2134a922
PO		 3137
3138 if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) &&
3139 (host->flags & SDHCI_USE_ADMA)) {
3140 DBG("Disabling ADMA as it is marked broken\n");
3141 host->flags &= ~SDHCI_USE_ADMA;
3142 }
3143
e57a5f61
AH		 3144 /*
3145 * It is assumed that a 64-bit capable device has set a 64-bit DMA mask
3146 * and *must* do 64-bit DMA. A driver has the opportunity to change
3147 * that during the first call to ->enable_dma(). Similarly
3148 * SDHCI_QUIRK2_BROKEN_64_BIT_DMA must be left to the drivers to
3149 * implement.
3150 */
28da3589 3151 if (host->caps & SDHCI_CAN_64BIT)
e57a5f61
AH		 3152 host->flags |= SDHCI_USE_64_BIT_DMA;
3153
a13abc7b 3154 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
7b91369b
AC		 3155 ret = sdhci_set_dma_mask(host);
3156
3157 if (!ret && host->ops->enable_dma)
3158 ret = host->ops->enable_dma(host);
3159
3160 if (ret) {
3161 pr_warn("%s: No suitable DMA available - falling back to PIO\n",
3162 mmc_hostname(mmc));
3163 host->flags &= ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
3164
3165 ret = 0;
d129bceb
PO		 3166 }
3167 }
3168
e57a5f61
AH		 3169 /* SDMA does not support 64-bit DMA */
3170 if (host->flags & SDHCI_USE_64_BIT_DMA)
3171 host->flags &= ~SDHCI_USE_SDMA;
3172
2134a922 3173 if (host->flags & SDHCI_USE_ADMA) {
e66e61cb
RK		 3174 dma_addr_t dma;
3175 void *buf;
3176
2134a922 3177 /*
76fe379a
AH		 3178 * The DMA descriptor table size is calculated as the maximum
3179 * number of segments times 2, to allow for an alignment
3180 * descriptor for each segment, plus 1 for a nop end descriptor,
3181 * all multipled by the descriptor size.
2134a922 3182 */
e57a5f61
AH		 3183 if (host->flags & SDHCI_USE_64_BIT_DMA) {
3184 host->adma_table_sz = (SDHCI_MAX_SEGS * 2 + 1) *
3185 SDHCI_ADMA2_64_DESC_SZ;
e57a5f61 3186 host->desc_sz = SDHCI_ADMA2_64_DESC_SZ;
e57a5f61
AH		 3187 } else {
3188 host->adma_table_sz = (SDHCI_MAX_SEGS * 2 + 1) *
3189 SDHCI_ADMA2_32_DESC_SZ;
e57a5f61 3190 host->desc_sz = SDHCI_ADMA2_32_DESC_SZ;
e57a5f61 3191 }
e66e61cb 3192
04a5ae6f 3193 host->align_buffer_sz = SDHCI_MAX_SEGS * SDHCI_ADMA2_ALIGN;
e66e61cb
RK		 3194 buf = dma_alloc_coherent(mmc_dev(mmc), host->align_buffer_sz +
3195 host->adma_table_sz, &dma, GFP_KERNEL);
3196 if (!buf) {
6606110d 3197 pr_warn("%s: Unable to allocate ADMA buffers - falling back to standard DMA\n",
2134a922
PO		 3198 mmc_hostname(mmc));
3199 host->flags &= ~SDHCI_USE_ADMA;
e66e61cb
RK		 3200 } else if ((dma + host->align_buffer_sz) &
3201 (SDHCI_ADMA2_DESC_ALIGN - 1)) {
6606110d
JP		 3202 pr_warn("%s: unable to allocate aligned ADMA descriptor\n",
3203 mmc_hostname(mmc));
d1e49f77 3204 host->flags &= ~SDHCI_USE_ADMA;
e66e61cb
RK		 3205 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
3206 host->adma_table_sz, buf, dma);
3207 } else {
3208 host->align_buffer = buf;
3209 host->align_addr = dma;
edd63fcc 3210
e66e61cb
RK		 3211 host->adma_table = buf + host->align_buffer_sz;
3212 host->adma_addr = dma + host->align_buffer_sz;
3213 }
2134a922
PO		 3214 }
3215
7659150c
PO		 3216 /*
3217 * If we use DMA, then it's up to the caller to set the DMA
3218 * mask, but PIO does not need the hw shim so we set a new
3219 * mask here in that case.
3220 */
a13abc7b 3221 if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) {
7659150c 3222 host->dma_mask = DMA_BIT_MASK(64);
4e743f1f 3223 mmc_dev(mmc)->dma_mask = &host->dma_mask;
7659150c 3224 }
d129bceb 3225
c4687d5f 3226 if (host->version >= SDHCI_SPEC_300)
28da3589 3227 host->max_clk = (host->caps & SDHCI_CLOCK_V3_BASE_MASK)
c4687d5f
ZG		 3228 >> SDHCI_CLOCK_BASE_SHIFT;
3229 else
28da3589 3230 host->max_clk = (host->caps & SDHCI_CLOCK_BASE_MASK)
c4687d5f
ZG		 3231 >> SDHCI_CLOCK_BASE_SHIFT;
3232
4240ff0a 3233 host->max_clk *= 1000000;
f27f47ef
AV		 3234 if (host->max_clk == 0 || host->quirks &
3235 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) {
4240ff0a 3236 if (!host->ops->get_max_clock) {
2e4456f0
MV		 3237 pr_err("%s: Hardware doesn't specify base clock frequency.\n",
3238 mmc_hostname(mmc));
eb5c20de
AH		 3239 ret = -ENODEV;
3240 goto undma;
4240ff0a
BD		 3241 }
3242 host->max_clk = host->ops->get_max_clock(host);
8ef1a143 3243 }
d129bceb 3244
c3ed3877
AN		 3245 /*
3246 * In case of Host Controller v3.00, find out whether clock
3247 * multiplier is supported.
3248 */
28da3589 3249 host->clk_mul = (host->caps1 & SDHCI_CLOCK_MUL_MASK) >>
c3ed3877
AN		 3250 SDHCI_CLOCK_MUL_SHIFT;
3251
3252 /*
3253 * In case the value in Clock Multiplier is 0, then programmable
3254 * clock mode is not supported, otherwise the actual clock
3255 * multiplier is one more than the value of Clock Multiplier
3256 * in the Capabilities Register.
3257 */
3258 if (host->clk_mul)
3259 host->clk_mul += 1;
3260
d129bceb
PO		 3261 /*
3262 * Set host parameters.
3263 */
59241757
DA		 3264 max_clk = host->max_clk;
3265
ce5f036b 3266 if (host->ops->get_min_clock)
a9e58f25 3267 mmc->f_min = host->ops->get_min_clock(host);
c3ed3877
AN		 3268 else if (host->version >= SDHCI_SPEC_300) {
3269 if (host->clk_mul) {
3270 mmc->f_min = (host->max_clk * host->clk_mul) / 1024;
59241757 3271 max_clk = host->max_clk * host->clk_mul;
c3ed3877
AN		 3272 } else
3273 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300;
3274 } else
0397526d 3275 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200;
15ec4461 3276
d310ae49 3277 if (!mmc->f_max || mmc->f_max > max_clk)
59241757
DA		 3278 mmc->f_max = max_clk;
3279
28aab053 3280 if (!(host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) {
28da3589 3281 host->timeout_clk = (host->caps & SDHCI_TIMEOUT_CLK_MASK) >>
28aab053
AD		 3282 SDHCI_TIMEOUT_CLK_SHIFT;
3283 if (host->timeout_clk == 0) {
3284 if (host->ops->get_timeout_clock) {
3285 host->timeout_clk =
3286 host->ops->get_timeout_clock(host);
3287 } else {
3288 pr_err("%s: Hardware doesn't specify timeout clock frequency.\n",
3289 mmc_hostname(mmc));
eb5c20de
AH		 3290 ret = -ENODEV;
3291 goto undma;
28aab053 3292 }
272308ca 3293 }
272308ca 3294
28da3589 3295 if (host->caps & SDHCI_TIMEOUT_CLK_UNIT)
28aab053 3296 host->timeout_clk *= 1000;
272308ca 3297
99513624
AH		 3298 if (override_timeout_clk)
3299 host->timeout_clk = override_timeout_clk;
3300
28aab053 3301 mmc->max_busy_timeout = host->ops->get_max_timeout_count ?
a6ff5aeb 3302 host->ops->get_max_timeout_count(host) : 1 << 27;
28aab053
AD		 3303 mmc->max_busy_timeout /= host->timeout_clk;
3304 }
58d1246d 3305
e89d456f 3306 mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_ERASE | MMC_CAP_CMD23;
781e989c 3307 mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD;
e89d456f
AW		 3308
3309 if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12)
3310 host->flags |= SDHCI_AUTO_CMD12;
5fe23c7f 3311
8edf6371 3312 /* Auto-CMD23 stuff only works in ADMA or PIO. */
4f3d3e9b 3313 if ((host->version >= SDHCI_SPEC_300) &&
8edf6371 3314 ((host->flags & SDHCI_USE_ADMA) ||
3bfa6f03
SB		 3315 !(host->flags & SDHCI_USE_SDMA)) &&
3316 !(host->quirks2 & SDHCI_QUIRK2_ACMD23_BROKEN)) {
8edf6371
AW		 3317 host->flags |= SDHCI_AUTO_CMD23;
3318 DBG("%s: Auto-CMD23 available\n", mmc_hostname(mmc));
3319 } else {
3320 DBG("%s: Auto-CMD23 unavailable\n", mmc_hostname(mmc));
3321 }
3322
15ec4461
PR		 3323 /*
3324 * A controller may support 8-bit width, but the board itself
3325 * might not have the pins brought out. Boards that support
3326 * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in
3327 * their platform code before calling sdhci_add_host(), and we
3328 * won't assume 8-bit width for hosts without that CAP.
3329 */
5fe23c7f 3330 if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA))
15ec4461 3331 mmc->caps |= MMC_CAP_4_BIT_DATA;
d129bceb 3332
63ef5d8c
JH		 3333 if (host->quirks2 & SDHCI_QUIRK2_HOST_NO_CMD23)
3334 mmc->caps &= ~MMC_CAP_CMD23;
3335
28da3589 3336 if (host->caps & SDHCI_CAN_DO_HISPD)
a29e7e18 3337 mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
cd9277c0 3338
176d1ed4 3339 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) &&
860951c5 3340 mmc_card_is_removable(mmc) &&
287980e4 3341 mmc_gpio_get_cd(host->mmc) < 0)
68d1fb7e
AV		 3342 mmc->caps |= MMC_CAP_NEEDS_POLL;
3343
6231f3de 3344 /* If vqmmc regulator and no 1.8V signalling, then there's no UHS */
3a48edc4
TK		 3345 if (!IS_ERR(mmc->supply.vqmmc)) {
3346 ret = regulator_enable(mmc->supply.vqmmc);
3347 if (!regulator_is_supported_voltage(mmc->supply.vqmmc, 1700000,
3348 1950000))
28da3589
AH		 3349 host->caps1 &= ~(SDHCI_SUPPORT_SDR104 |
3350 SDHCI_SUPPORT_SDR50 |
3351 SDHCI_SUPPORT_DDR50);
a3361aba
CB		 3352 if (ret) {
3353 pr_warn("%s: Failed to enable vqmmc regulator: %d\n",
3354 mmc_hostname(mmc), ret);
4bb74313 3355 mmc->supply.vqmmc = ERR_PTR(-EINVAL);
a3361aba 3356 }
8363c374 3357 }
6231f3de 3358
28da3589
AH		 3359 if (host->quirks2 & SDHCI_QUIRK2_NO_1_8_V) {
3360 host->caps1 &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
3361 SDHCI_SUPPORT_DDR50);
3362 }
6a66180a 3363
4188bba0 3364 /* Any UHS-I mode in caps implies SDR12 and SDR25 support. */
28da3589
AH		 3365 if (host->caps1 & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
3366 SDHCI_SUPPORT_DDR50))
f2119df6
AN		 3367 mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;
3368
3369 /* SDR104 supports also implies SDR50 support */
28da3589 3370 if (host->caps1 & SDHCI_SUPPORT_SDR104) {
f2119df6 3371 mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50;
156e14b1
GC		 3372 /* SD3.0: SDR104 is supported so (for eMMC) the caps2
3373 * field can be promoted to support HS200.
3374 */
549c0b18 3375 if (!(host->quirks2 & SDHCI_QUIRK2_BROKEN_HS200))
13868bf2 3376 mmc->caps2 |= MMC_CAP2_HS200;
28da3589 3377 } else if (host->caps1 & SDHCI_SUPPORT_SDR50) {
f2119df6 3378 mmc->caps |= MMC_CAP_UHS_SDR50;
28da3589 3379 }
f2119df6 3380
e9fb05d5 3381 if (host->quirks2 & SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 &&
28da3589 3382 (host->caps1 & SDHCI_SUPPORT_HS400))
e9fb05d5
AH		 3383 mmc->caps2 |= MMC_CAP2_HS400;
3384
549c0b18
AH		 3385 if ((mmc->caps2 & MMC_CAP2_HSX00_1_2V) &&
3386 (IS_ERR(mmc->supply.vqmmc) ||
3387 !regulator_is_supported_voltage(mmc->supply.vqmmc, 1100000,
3388 1300000)))
3389 mmc->caps2 &= ~MMC_CAP2_HSX00_1_2V;
3390
28da3589
AH		 3391 if ((host->caps1 & SDHCI_SUPPORT_DDR50) &&
3392 !(host->quirks2 & SDHCI_QUIRK2_BROKEN_DDR50))
f2119df6
AN		 3393 mmc->caps |= MMC_CAP_UHS_DDR50;
3394
069c9f14 3395 /* Does the host need tuning for SDR50? */
28da3589 3396 if (host->caps1 & SDHCI_USE_SDR50_TUNING)
b513ea25
AN		 3397 host->flags |= SDHCI_SDR50_NEEDS_TUNING;
3398
d6d50a15 3399 /* Driver Type(s) (A, C, D) supported by the host */
28da3589 3400 if (host->caps1 & SDHCI_DRIVER_TYPE_A)
d6d50a15 3401 mmc->caps |= MMC_CAP_DRIVER_TYPE_A;
28da3589 3402 if (host->caps1 & SDHCI_DRIVER_TYPE_C)
d6d50a15 3403 mmc->caps |= MMC_CAP_DRIVER_TYPE_C;
28da3589 3404 if (host->caps1 & SDHCI_DRIVER_TYPE_D)
d6d50a15
AN		 3405 mmc->caps |= MMC_CAP_DRIVER_TYPE_D;
3406
cf2b5eea 3407 /* Initial value for re-tuning timer count */
28da3589
AH		 3408 host->tuning_count = (host->caps1 & SDHCI_RETUNING_TIMER_COUNT_MASK) >>
3409 SDHCI_RETUNING_TIMER_COUNT_SHIFT;
cf2b5eea
AN		 3410
3411 /*
3412 * In case Re-tuning Timer is not disabled, the actual value of
3413 * re-tuning timer will be 2 ^ (n - 1).
3414 */
3415 if (host->tuning_count)
3416 host->tuning_count = 1 << (host->tuning_count - 1);
3417
3418 /* Re-tuning mode supported by the Host Controller */
28da3589 3419 host->tuning_mode = (host->caps1 & SDHCI_RETUNING_MODE_MASK) >>
cf2b5eea
AN		 3420 SDHCI_RETUNING_MODE_SHIFT;
3421
8f230f45 3422 ocr_avail = 0;
bad37e1a 3423
f2119df6
AN		 3424 /*
3425 * According to SD Host Controller spec v3.00, if the Host System
3426 * can afford more than 150mA, Host Driver should set XPC to 1. Also
3427 * the value is meaningful only if Voltage Support in the Capabilities
3428 * register is set. The actual current value is 4 times the register
3429 * value.
3430 */
3431 max_current_caps = sdhci_readl(host, SDHCI_MAX_CURRENT);
3a48edc4 3432 if (!max_current_caps && !IS_ERR(mmc->supply.vmmc)) {
ae906037 3433 int curr = regulator_get_current_limit(mmc->supply.vmmc);
bad37e1a
PR		 3434 if (curr > 0) {
3435
3436 /* convert to SDHCI_MAX_CURRENT format */
3437 curr = curr/1000; /* convert to mA */
3438 curr = curr/SDHCI_MAX_CURRENT_MULTIPLIER;
3439
3440 curr = min_t(u32, curr, SDHCI_MAX_CURRENT_LIMIT);
3441 max_current_caps =
3442 (curr << SDHCI_MAX_CURRENT_330_SHIFT) |
3443 (curr << SDHCI_MAX_CURRENT_300_SHIFT) |
3444 (curr << SDHCI_MAX_CURRENT_180_SHIFT);
3445 }
3446 }
f2119df6 3447
28da3589 3448 if (host->caps & SDHCI_CAN_VDD_330) {
8f230f45 3449 ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34;
f2119df6 3450
55c4665e 3451 mmc->max_current_330 = ((max_current_caps &
f2119df6
AN		 3452 SDHCI_MAX_CURRENT_330_MASK) >>
3453 SDHCI_MAX_CURRENT_330_SHIFT) *
3454 SDHCI_MAX_CURRENT_MULTIPLIER;
f2119df6 3455 }
28da3589 3456 if (host->caps & SDHCI_CAN_VDD_300) {
8f230f45 3457 ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31;
f2119df6 3458
55c4665e 3459 mmc->max_current_300 = ((max_current_caps &
f2119df6
AN		 3460 SDHCI_MAX_CURRENT_300_MASK) >>
3461 SDHCI_MAX_CURRENT_300_SHIFT) *
3462 SDHCI_MAX_CURRENT_MULTIPLIER;
f2119df6 3463 }
28da3589 3464 if (host->caps & SDHCI_CAN_VDD_180) {
8f230f45
TI		 3465 ocr_avail |= MMC_VDD_165_195;
3466
55c4665e 3467 mmc->max_current_180 = ((max_current_caps &
f2119df6
AN		 3468 SDHCI_MAX_CURRENT_180_MASK) >>
3469 SDHCI_MAX_CURRENT_180_SHIFT) *
3470 SDHCI_MAX_CURRENT_MULTIPLIER;
f2119df6
AN		 3471 }
3472
5fd26c7e
UH		 3473 /* If OCR set by host, use it instead. */
3474 if (host->ocr_mask)
3475 ocr_avail = host->ocr_mask;
3476
3477 /* If OCR set by external regulators, give it highest prio. */
3a48edc4 3478 if (mmc->ocr_avail)
52221610 3479 ocr_avail = mmc->ocr_avail;
3a48edc4 3480
8f230f45
TI		 3481 mmc->ocr_avail = ocr_avail;
3482 mmc->ocr_avail_sdio = ocr_avail;
3483 if (host->ocr_avail_sdio)
3484 mmc->ocr_avail_sdio &= host->ocr_avail_sdio;
3485 mmc->ocr_avail_sd = ocr_avail;
3486 if (host->ocr_avail_sd)
3487 mmc->ocr_avail_sd &= host->ocr_avail_sd;
3488 else /* normal SD controllers don't support 1.8V */
3489 mmc->ocr_avail_sd &= ~MMC_VDD_165_195;
3490 mmc->ocr_avail_mmc = ocr_avail;
3491 if (host->ocr_avail_mmc)
3492 mmc->ocr_avail_mmc &= host->ocr_avail_mmc;
146ad66e
PO		 3493
3494 if (mmc->ocr_avail == 0) {
2e4456f0
MV		 3495 pr_err("%s: Hardware doesn't report any support voltages.\n",
3496 mmc_hostname(mmc));
eb5c20de
AH		 3497 ret = -ENODEV;
3498 goto unreg;
146ad66e
PO		 3499 }
3500
8cb851a4
AH		 3501 if ((mmc->caps & (MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 |
3502 MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_SDR104 |
3503 MMC_CAP_UHS_DDR50 | MMC_CAP_1_8V_DDR)) ||
3504 (mmc->caps2 & (MMC_CAP2_HS200_1_8V_SDR | MMC_CAP2_HS400_1_8V)))
3505 host->flags |= SDHCI_SIGNALING_180;
3506
3507 if (mmc->caps2 & MMC_CAP2_HSX00_1_2V)
3508 host->flags |= SDHCI_SIGNALING_120;
3509
d129bceb
PO		 3510 spin_lock_init(&host->lock);
3511
3512 /*
2134a922
PO		 3513 * Maximum number of segments. Depends on if the hardware
3514 * can do scatter/gather or not.
d129bceb 3515 */
2134a922 3516 if (host->flags & SDHCI_USE_ADMA)
4fb213f8 3517 mmc->max_segs = SDHCI_MAX_SEGS;
a13abc7b 3518 else if (host->flags & SDHCI_USE_SDMA)
a36274e0 3519 mmc->max_segs = 1;
2134a922 3520 else /* PIO */
4fb213f8 3521 mmc->max_segs = SDHCI_MAX_SEGS;
d129bceb
PO		 3522
3523 /*
ac00531d
AH		 3524 * Maximum number of sectors in one transfer. Limited by SDMA boundary
3525 * size (512KiB). Note some tuning modes impose a 4MiB limit, but this
3526 * is less anyway.
d129bceb 3527 */
55db890a 3528 mmc->max_req_size = 524288;
d129bceb
PO		 3529
3530 /*
3531 * Maximum segment size. Could be one segment with the maximum number
2134a922
PO		 3532 * of bytes. When doing hardware scatter/gather, each entry cannot
3533 * be larger than 64 KiB though.
d129bceb 3534 */
30652aa3
OJ		 3535 if (host->flags & SDHCI_USE_ADMA) {
3536 if (host->quirks & SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC)
3537 mmc->max_seg_size = 65535;
3538 else
3539 mmc->max_seg_size = 65536;
3540 } else {
2134a922 3541 mmc->max_seg_size = mmc->max_req_size;
30652aa3 3542 }
d129bceb 3543
fe4a3c7a
PO		 3544 /*
3545 * Maximum block size. This varies from controller to controller and
3546 * is specified in the capabilities register.
3547 */
0633f654
AV		 3548 if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) {
3549 mmc->max_blk_size = 2;
3550 } else {
28da3589 3551 mmc->max_blk_size = (host->caps & SDHCI_MAX_BLOCK_MASK) >>
0633f654
AV		 3552 SDHCI_MAX_BLOCK_SHIFT;
3553 if (mmc->max_blk_size >= 3) {
6606110d
JP		 3554 pr_warn("%s: Invalid maximum block size, assuming 512 bytes\n",
3555 mmc_hostname(mmc));
0633f654
AV		 3556 mmc->max_blk_size = 0;
3557 }
3558 }
3559
3560 mmc->max_blk_size = 512 << mmc->max_blk_size;
fe4a3c7a 3561
55db890a
PO		 3562 /*
3563 * Maximum block count.
3564 */
1388eefd 3565 mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
55db890a 3566
52f5336d
AH		 3567 return 0;
3568
3569unreg:
3570 if (!IS_ERR(mmc->supply.vqmmc))
3571 regulator_disable(mmc->supply.vqmmc);
3572undma:
3573 if (host->align_buffer)
3574 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
3575 host->adma_table_sz, host->align_buffer,
3576 host->align_addr);
3577 host->adma_table = NULL;
3578 host->align_buffer = NULL;
3579
3580 return ret;
3581}
3582EXPORT_SYMBOL_GPL(sdhci_setup_host);
3583
3584int __sdhci_add_host(struct sdhci_host *host)
3585{
3586 struct mmc_host *mmc = host->mmc;
3587 int ret;
3588
d129bceb
PO		 3589 /*
3590 * Init tasklets.
3591 */
d129bceb
PO		 3592 tasklet_init(&host->finish_tasklet,
3593 sdhci_tasklet_finish, (unsigned long)host);
3594
e4cad1b5 3595 setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host);
d7422fb4
AH		 3596 setup_timer(&host->data_timer, sdhci_timeout_data_timer,
3597 (unsigned long)host);
d129bceb 3598
250fb7b4 3599 init_waitqueue_head(&host->buf_ready_int);
b513ea25 3600
2af502ca
SG		 3601 sdhci_init(host, 0);
3602
781e989c
RK		 3603 ret = request_threaded_irq(host->irq, sdhci_irq, sdhci_thread_irq,
3604 IRQF_SHARED, mmc_hostname(mmc), host);
0fc81ee3
MB		 3605 if (ret) {
3606 pr_err("%s: Failed to request IRQ %d: %d\n",
3607 mmc_hostname(mmc), host->irq, ret);
8ef1a143 3608 goto untasklet;
0fc81ee3 3609 }
d129bceb 3610
d129bceb
PO		 3611#ifdef CONFIG_MMC_DEBUG
3612 sdhci_dumpregs(host);
3613#endif
3614
061d17a6 3615 ret = sdhci_led_register(host);
0fc81ee3
MB		 3616 if (ret) {
3617 pr_err("%s: Failed to register LED device: %d\n",
3618 mmc_hostname(mmc), ret);
eb5c20de 3619 goto unirq;
0fc81ee3 3620 }
2f730fec 3621
5f25a66f
PO		 3622 mmiowb();
3623
eb5c20de
AH		 3624 ret = mmc_add_host(mmc);
3625 if (ret)
3626 goto unled;
d129bceb 3627
a3c76eb9 3628 pr_info("%s: SDHCI controller on %s [%s] using %s\n",
d1b26863 3629 mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)),
e57a5f61
AH		 3630 (host->flags & SDHCI_USE_ADMA) ?
3631 (host->flags & SDHCI_USE_64_BIT_DMA) ? "ADMA 64-bit" : "ADMA" :
a13abc7b 3632 (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO");
d129bceb 3633
7260cf5e
AV		 3634 sdhci_enable_card_detection(host);
3635
d129bceb
PO		 3636 return 0;
3637
eb5c20de 3638unled:
061d17a6 3639 sdhci_led_unregister(host);
eb5c20de 3640unirq:
03231f9b 3641 sdhci_do_reset(host, SDHCI_RESET_ALL);
b537f94c
RK		 3642 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
3643 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
2f730fec 3644 free_irq(host->irq, host);
8ef1a143 3645untasklet:
d129bceb 3646 tasklet_kill(&host->finish_tasklet);
52f5336d 3647
eb5c20de
AH		 3648 if (!IS_ERR(mmc->supply.vqmmc))
3649 regulator_disable(mmc->supply.vqmmc);
52f5336d 3650
eb5c20de
AH		 3651 if (host->align_buffer)
3652 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
3653 host->adma_table_sz, host->align_buffer,
3654 host->align_addr);
3655 host->adma_table = NULL;
3656 host->align_buffer = NULL;
d129bceb
PO		 3657
3658 return ret;
3659}
52f5336d
AH		 3660EXPORT_SYMBOL_GPL(__sdhci_add_host);
3661
3662int sdhci_add_host(struct sdhci_host *host)
3663{
3664 int ret;
3665
3666 ret = sdhci_setup_host(host);
3667 if (ret)
3668 return ret;
d129bceb 3669
52f5336d
AH		 3670 return __sdhci_add_host(host);
3671}
b8c86fc5 3672EXPORT_SYMBOL_GPL(sdhci_add_host);
d129bceb 3673
1e72859e 3674void sdhci_remove_host(struct sdhci_host *host, int dead)
b8c86fc5 3675{
3a48edc4 3676 struct mmc_host *mmc = host->mmc;
1e72859e
PO		 3677 unsigned long flags;
3678
3679 if (dead) {
3680 spin_lock_irqsave(&host->lock, flags);
3681
3682 host->flags |= SDHCI_DEVICE_DEAD;
3683
5d0d11c5 3684 if (sdhci_has_requests(host)) {
a3c76eb9 3685 pr_err("%s: Controller removed during "
4e743f1f 3686 " transfer!\n", mmc_hostname(mmc));
5d0d11c5 3687 sdhci_error_out_mrqs(host, -ENOMEDIUM);
1e72859e
PO		 3688 }
3689
3690 spin_unlock_irqrestore(&host->lock, flags);
3691 }
3692
7260cf5e
AV		 3693 sdhci_disable_card_detection(host);
3694
4e743f1f 3695 mmc_remove_host(mmc);
d129bceb 3696
061d17a6 3697 sdhci_led_unregister(host);
2f730fec 3698
1e72859e 3699 if (!dead)
03231f9b 3700 sdhci_do_reset(host, SDHCI_RESET_ALL);
d129bceb 3701
b537f94c
RK		 3702 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
3703 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
d129bceb
PO		 3704 free_irq(host->irq, host);
3705
3706 del_timer_sync(&host->timer);
d7422fb4 3707 del_timer_sync(&host->data_timer);
d129bceb 3708
d129bceb 3709 tasklet_kill(&host->finish_tasklet);
2134a922 3710
3a48edc4
TK		 3711 if (!IS_ERR(mmc->supply.vqmmc))
3712 regulator_disable(mmc->supply.vqmmc);
6231f3de 3713
edd63fcc 3714 if (host->align_buffer)
e66e61cb
RK		 3715 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
3716 host->adma_table_sz, host->align_buffer,
3717 host->align_addr);
2134a922 3718
4efaa6fb 3719 host->adma_table = NULL;
2134a922 3720 host->align_buffer = NULL;
d129bceb
PO		 3721}
3722
b8c86fc5 3723EXPORT_SYMBOL_GPL(sdhci_remove_host);
d129bceb 3724
b8c86fc5 3725void sdhci_free_host(struct sdhci_host *host)
d129bceb 3726{
b8c86fc5 3727 mmc_free_host(host->mmc);
d129bceb
PO		 3728}
3729
b8c86fc5 3730EXPORT_SYMBOL_GPL(sdhci_free_host);
d129bceb
PO		 3731
3732/*****************************************************************************\
3733 * *
3734 * Driver init/exit *
3735 * *
3736\*****************************************************************************/
3737
3738static int __init sdhci_drv_init(void)
3739{
a3c76eb9 3740 pr_info(DRIVER_NAME
52fbf9c9 3741 ": Secure Digital Host Controller Interface driver\n");
a3c76eb9 3742 pr_info(DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
d129bceb 3743
b8c86fc5 3744 return 0;
d129bceb
PO		 3745}
3746
3747static void __exit sdhci_drv_exit(void)
3748{
d129bceb
PO		 3749}
3750
3751module_init(sdhci_drv_init);
3752module_exit(sdhci_drv_exit);
3753
df673b22 3754module_param(debug_quirks, uint, 0444);
66fd8ad5 3755module_param(debug_quirks2, uint, 0444);
67435274 3756
32710e8f 3757MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
b8c86fc5 3758MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver");
d129bceb 3759MODULE_LICENSE("GPL");
67435274 3760
df673b22 3761MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");
66fd8ad5 3762MODULE_PARM_DESC(debug_quirks2, "Force certain other quirks.");
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