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mmc: sdhci: fix command response CRC error handling
[mirror_ubuntu-artful-kernel.git] / drivers / mmc / host / sdhci.c
CommitLineData
d129bceb 1/*
70f10482 2 * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
d129bceb 3 *
b69c9058 4 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
d129bceb
PO		 5 *
6 * This program is free software; you can redistribute it and/or modify
643f720c
PO		 7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or (at
9 * your option) any later version.
84c46a53
PO		 10 *
11 * Thanks to the following companies for their support:
12 *
13 * - JMicron (hardware and technical support)
d129bceb
PO		 14 */
15
d129bceb
PO		 16#include <linux/delay.h>
17#include <linux/highmem.h>
b8c86fc5 18#include <linux/io.h>
88b47679 19#include <linux/module.h>
d129bceb 20#include <linux/dma-mapping.h>
5a0e3ad6 21#include <linux/slab.h>
11763609 22#include <linux/scatterlist.h>
9bea3c85 23#include <linux/regulator/consumer.h>
66fd8ad5 24#include <linux/pm_runtime.h>
d129bceb 25
2f730fec
PO		 26#include <linux/leds.h>
27
22113efd 28#include <linux/mmc/mmc.h>
d129bceb 29#include <linux/mmc/host.h>
473b095a 30#include <linux/mmc/card.h>
85cc1c33 31#include <linux/mmc/sdio.h>
bec9d4e5 32#include <linux/mmc/slot-gpio.h>
d129bceb 33
d129bceb
PO		 34#include "sdhci.h"
35
36#define DRIVER_NAME "sdhci"
d129bceb 37
d129bceb 38#define DBG(f, x...) \
c6563178 39 pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
d129bceb 40
f9134319
PO		 41#if defined(CONFIG_LEDS_CLASS) || (defined(CONFIG_LEDS_CLASS_MODULE) && \
42 defined(CONFIG_MMC_SDHCI_MODULE))
43#define SDHCI_USE_LEDS_CLASS
44#endif
45
b513ea25
AN		 46#define MAX_TUNING_LOOP 40
47
df673b22 48static unsigned int debug_quirks = 0;
66fd8ad5 49static unsigned int debug_quirks2;
67435274 50
d129bceb
PO		 51static void sdhci_finish_data(struct sdhci_host *);
52
d129bceb 53static void sdhci_finish_command(struct sdhci_host *);
069c9f14 54static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode);
52983382 55static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable);
348487cb 56static int sdhci_pre_dma_transfer(struct sdhci_host *host,
d31911b9 57 struct mmc_data *data);
04e079cf 58static int sdhci_do_get_cd(struct sdhci_host *host);
d129bceb 59
162d6f98 60#ifdef CONFIG_PM
66fd8ad5
AH		 61static int sdhci_runtime_pm_get(struct sdhci_host *host);
62static int sdhci_runtime_pm_put(struct sdhci_host *host);
f0710a55
AH		 63static void sdhci_runtime_pm_bus_on(struct sdhci_host *host);
64static void sdhci_runtime_pm_bus_off(struct sdhci_host *host);
66fd8ad5
AH		 65#else
66static inline int sdhci_runtime_pm_get(struct sdhci_host *host)
67{
68 return 0;
69}
70static inline int sdhci_runtime_pm_put(struct sdhci_host *host)
71{
72 return 0;
73}
f0710a55
AH		 74static void sdhci_runtime_pm_bus_on(struct sdhci_host *host)
75{
76}
77static void sdhci_runtime_pm_bus_off(struct sdhci_host *host)
78{
79}
66fd8ad5
AH		 80#endif
81
d129bceb
PO		 82static void sdhci_dumpregs(struct sdhci_host *host)
83{
a3c76eb9 84 pr_debug(DRIVER_NAME ": =========== REGISTER DUMP (%s)===========\n",
412ab659 85 mmc_hostname(host->mmc));
d129bceb 86
a3c76eb9 87 pr_debug(DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n",
4e4141a5
AV		 88 sdhci_readl(host, SDHCI_DMA_ADDRESS),
89 sdhci_readw(host, SDHCI_HOST_VERSION));
a3c76eb9 90 pr_debug(DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n",
4e4141a5
AV		 91 sdhci_readw(host, SDHCI_BLOCK_SIZE),
92 sdhci_readw(host, SDHCI_BLOCK_COUNT));
a3c76eb9 93 pr_debug(DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
4e4141a5
AV		 94 sdhci_readl(host, SDHCI_ARGUMENT),
95 sdhci_readw(host, SDHCI_TRANSFER_MODE));
a3c76eb9 96 pr_debug(DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n",
4e4141a5
AV		 97 sdhci_readl(host, SDHCI_PRESENT_STATE),
98 sdhci_readb(host, SDHCI_HOST_CONTROL));
a3c76eb9 99 pr_debug(DRIVER_NAME ": Power: 0x%08x | Blk gap: 0x%08x\n",
4e4141a5
AV		 100 sdhci_readb(host, SDHCI_POWER_CONTROL),
101 sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL));
a3c76eb9 102 pr_debug(DRIVER_NAME ": Wake-up: 0x%08x | Clock: 0x%08x\n",
4e4141a5
AV		 103 sdhci_readb(host, SDHCI_WAKE_UP_CONTROL),
104 sdhci_readw(host, SDHCI_CLOCK_CONTROL));
a3c76eb9 105 pr_debug(DRIVER_NAME ": Timeout: 0x%08x | Int stat: 0x%08x\n",
4e4141a5
AV		 106 sdhci_readb(host, SDHCI_TIMEOUT_CONTROL),
107 sdhci_readl(host, SDHCI_INT_STATUS));
a3c76eb9 108 pr_debug(DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
4e4141a5
AV		 109 sdhci_readl(host, SDHCI_INT_ENABLE),
110 sdhci_readl(host, SDHCI_SIGNAL_ENABLE));
a3c76eb9 111 pr_debug(DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
4e4141a5
AV		 112 sdhci_readw(host, SDHCI_ACMD12_ERR),
113 sdhci_readw(host, SDHCI_SLOT_INT_STATUS));
a3c76eb9 114 pr_debug(DRIVER_NAME ": Caps: 0x%08x | Caps_1: 0x%08x\n",
4e4141a5 115 sdhci_readl(host, SDHCI_CAPABILITIES),
e8120ad1 116 sdhci_readl(host, SDHCI_CAPABILITIES_1));
a3c76eb9 117 pr_debug(DRIVER_NAME ": Cmd: 0x%08x | Max curr: 0x%08x\n",
e8120ad1 118 sdhci_readw(host, SDHCI_COMMAND),
4e4141a5 119 sdhci_readl(host, SDHCI_MAX_CURRENT));
a3c76eb9 120 pr_debug(DRIVER_NAME ": Host ctl2: 0x%08x\n",
f2119df6 121 sdhci_readw(host, SDHCI_HOST_CONTROL2));
d129bceb 122
e57a5f61
AH		 123 if (host->flags & SDHCI_USE_ADMA) {
124 if (host->flags & SDHCI_USE_64_BIT_DMA)
125 pr_debug(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x%08x\n",
126 readl(host->ioaddr + SDHCI_ADMA_ERROR),
127 readl(host->ioaddr + SDHCI_ADMA_ADDRESS_HI),
128 readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
129 else
130 pr_debug(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n",
131 readl(host->ioaddr + SDHCI_ADMA_ERROR),
132 readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
133 }
be3f4ae0 134
a3c76eb9 135 pr_debug(DRIVER_NAME ": ===========================================\n");
d129bceb
PO		 136}
137
138/*****************************************************************************\
139 * *
140 * Low level functions *
141 * *
142\*****************************************************************************/
143
7260cf5e
AV		 144static void sdhci_set_card_detection(struct sdhci_host *host, bool enable)
145{
5b4f1f6c 146 u32 present;
7260cf5e 147
c79396c1 148 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) ||
87b87a3f 149 (host->mmc->caps & MMC_CAP_NONREMOVABLE))
66fd8ad5
AH		 150 return;
151
5b4f1f6c
RK		 152 if (enable) {
153 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
154 SDHCI_CARD_PRESENT;
d25928d1 155
5b4f1f6c
RK		 156 host->ier |= present ? SDHCI_INT_CARD_REMOVE :
157 SDHCI_INT_CARD_INSERT;
158 } else {
159 host->ier &= ~(SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT);
160 }
b537f94c
RK		 161
162 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
163 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
7260cf5e
AV		 164}
165
166static void sdhci_enable_card_detection(struct sdhci_host *host)
167{
168 sdhci_set_card_detection(host, true);
169}
170
171static void sdhci_disable_card_detection(struct sdhci_host *host)
172{
173 sdhci_set_card_detection(host, false);
174}
175
03231f9b 176void sdhci_reset(struct sdhci_host *host, u8 mask)
d129bceb 177{
e16514d8 178 unsigned long timeout;
393c1a34 179
4e4141a5 180 sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
d129bceb 181
f0710a55 182 if (mask & SDHCI_RESET_ALL) {
d129bceb 183 host->clock = 0;
f0710a55
AH		 184 /* Reset-all turns off SD Bus Power */
185 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
186 sdhci_runtime_pm_bus_off(host);
187 }
d129bceb 188
e16514d8
PO		 189 /* Wait max 100 ms */
190 timeout = 100;
191
192 /* hw clears the bit when it's done */
4e4141a5 193 while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
e16514d8 194 if (timeout == 0) {
a3c76eb9 195 pr_err("%s: Reset 0x%x never completed.\n",
e16514d8
PO		 196 mmc_hostname(host->mmc), (int)mask);
197 sdhci_dumpregs(host);
198 return;
199 }
200 timeout--;
201 mdelay(1);
d129bceb 202 }
03231f9b
RK		 203}
204EXPORT_SYMBOL_GPL(sdhci_reset);
205
206static void sdhci_do_reset(struct sdhci_host *host, u8 mask)
207{
208 if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
135b0a28 209 if (!sdhci_do_get_cd(host))
03231f9b
RK		 210 return;
211 }
063a9dbb 212
03231f9b 213 host->ops->reset(host, mask);
393c1a34 214
da91a8f9
RK		 215 if (mask & SDHCI_RESET_ALL) {
216 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
217 if (host->ops->enable_dma)
218 host->ops->enable_dma(host);
219 }
220
221 /* Resetting the controller clears many */
222 host->preset_enabled = false;
3abc1e80 223 }
d129bceb
PO		 224}
225
2f4cbb3d
NP		 226static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios);
227
228static void sdhci_init(struct sdhci_host *host, int soft)
d129bceb 229{
2f4cbb3d 230 if (soft)
03231f9b 231 sdhci_do_reset(host, SDHCI_RESET_CMD|SDHCI_RESET_DATA);
2f4cbb3d 232 else
03231f9b 233 sdhci_do_reset(host, SDHCI_RESET_ALL);
d129bceb 234
b537f94c
RK		 235 host->ier = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
236 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT |
237 SDHCI_INT_INDEX | SDHCI_INT_END_BIT | SDHCI_INT_CRC |
238 SDHCI_INT_TIMEOUT | SDHCI_INT_DATA_END |
239 SDHCI_INT_RESPONSE;
240
241 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
242 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2f4cbb3d
NP		 243
244 if (soft) {
245 /* force clock reconfiguration */
246 host->clock = 0;
247 sdhci_set_ios(host->mmc, &host->mmc->ios);
248 }
7260cf5e 249}
d129bceb 250
7260cf5e
AV		 251static void sdhci_reinit(struct sdhci_host *host)
252{
2f4cbb3d 253 sdhci_init(host, 0);
7260cf5e 254 sdhci_enable_card_detection(host);
d129bceb
PO		 255}
256
257static void sdhci_activate_led(struct sdhci_host *host)
258{
259 u8 ctrl;
260
4e4141a5 261 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
d129bceb 262 ctrl |= SDHCI_CTRL_LED;
4e4141a5 263 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d129bceb
PO		 264}
265
266static void sdhci_deactivate_led(struct sdhci_host *host)
267{
268 u8 ctrl;
269
4e4141a5 270 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
d129bceb 271 ctrl &= ~SDHCI_CTRL_LED;
4e4141a5 272 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d129bceb
PO		 273}
274
f9134319 275#ifdef SDHCI_USE_LEDS_CLASS
2f730fec
PO		 276static void sdhci_led_control(struct led_classdev *led,
277 enum led_brightness brightness)
278{
279 struct sdhci_host *host = container_of(led, struct sdhci_host, led);
280 unsigned long flags;
281
282 spin_lock_irqsave(&host->lock, flags);
283
66fd8ad5
AH		 284 if (host->runtime_suspended)
285 goto out;
286
2f730fec
PO		 287 if (brightness == LED_OFF)
288 sdhci_deactivate_led(host);
289 else
290 sdhci_activate_led(host);
66fd8ad5 291out:
2f730fec
PO		 292 spin_unlock_irqrestore(&host->lock, flags);
293}
294#endif
295
d129bceb
PO		 296/*****************************************************************************\
297 * *
298 * Core functions *
299 * *
300\*****************************************************************************/
301
a406f5a3 302static void sdhci_read_block_pio(struct sdhci_host *host)
d129bceb 303{
7659150c
PO		 304 unsigned long flags;
305 size_t blksize, len, chunk;
7244b85b 306 u32 uninitialized_var(scratch);
7659150c 307 u8 *buf;
d129bceb 308
a406f5a3 309 DBG("PIO reading\n");
d129bceb 310
a406f5a3 311 blksize = host->data->blksz;
7659150c 312 chunk = 0;
d129bceb 313
7659150c 314 local_irq_save(flags);
d129bceb 315
a406f5a3 316 while (blksize) {
bf3a35ac 317 BUG_ON(!sg_miter_next(&host->sg_miter));
d129bceb 318
7659150c 319 len = min(host->sg_miter.length, blksize);
d129bceb 320
7659150c
PO		 321 blksize -= len;
322 host->sg_miter.consumed = len;
14d836e7 323
7659150c 324 buf = host->sg_miter.addr;
d129bceb 325
7659150c
PO		 326 while (len) {
327 if (chunk == 0) {
4e4141a5 328 scratch = sdhci_readl(host, SDHCI_BUFFER);
7659150c 329 chunk = 4;
a406f5a3 330 }
7659150c
PO		 331
332 *buf = scratch & 0xFF;
333
334 buf++;
335 scratch >>= 8;
336 chunk--;
337 len--;
d129bceb 338 }
a406f5a3 339 }
7659150c
PO		 340
341 sg_miter_stop(&host->sg_miter);
342
343 local_irq_restore(flags);
a406f5a3 344}
d129bceb 345
a406f5a3
PO		 346static void sdhci_write_block_pio(struct sdhci_host *host)
347{
7659150c
PO		 348 unsigned long flags;
349 size_t blksize, len, chunk;
350 u32 scratch;
351 u8 *buf;
d129bceb 352
a406f5a3
PO		 353 DBG("PIO writing\n");
354
355 blksize = host->data->blksz;
7659150c
PO		 356 chunk = 0;
357 scratch = 0;
d129bceb 358
7659150c 359 local_irq_save(flags);
d129bceb 360
a406f5a3 361 while (blksize) {
bf3a35ac 362 BUG_ON(!sg_miter_next(&host->sg_miter));
a406f5a3 363
7659150c
PO		 364 len = min(host->sg_miter.length, blksize);
365
366 blksize -= len;
367 host->sg_miter.consumed = len;
368
369 buf = host->sg_miter.addr;
d129bceb 370
7659150c
PO		 371 while (len) {
372 scratch |= (u32)*buf << (chunk * 8);
373
374 buf++;
375 chunk++;
376 len--;
377
378 if ((chunk == 4) || ((len == 0) && (blksize == 0))) {
4e4141a5 379 sdhci_writel(host, scratch, SDHCI_BUFFER);
7659150c
PO		 380 chunk = 0;
381 scratch = 0;
d129bceb 382 }
d129bceb
PO		 383 }
384 }
7659150c
PO		 385
386 sg_miter_stop(&host->sg_miter);
387
388 local_irq_restore(flags);
a406f5a3
PO		 389}
390
391static void sdhci_transfer_pio(struct sdhci_host *host)
392{
393 u32 mask;
394
395 BUG_ON(!host->data);
396
7659150c 397 if (host->blocks == 0)
a406f5a3
PO		 398 return;
399
400 if (host->data->flags & MMC_DATA_READ)
401 mask = SDHCI_DATA_AVAILABLE;
402 else
403 mask = SDHCI_SPACE_AVAILABLE;
404
4a3cba32
PO		 405 /*
406 * Some controllers (JMicron JMB38x) mess up the buffer bits
407 * for transfers < 4 bytes. As long as it is just one block,
408 * we can ignore the bits.
409 */
410 if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) &&
411 (host->data->blocks == 1))
412 mask = ~0;
413
4e4141a5 414 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
3e3bf207
AV		 415 if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY)
416 udelay(100);
417
a406f5a3
PO		 418 if (host->data->flags & MMC_DATA_READ)
419 sdhci_read_block_pio(host);
420 else
421 sdhci_write_block_pio(host);
d129bceb 422
7659150c
PO		 423 host->blocks--;
424 if (host->blocks == 0)
a406f5a3 425 break;
a406f5a3 426 }
d129bceb 427
a406f5a3 428 DBG("PIO transfer complete.\n");
d129bceb
PO		 429}
430
2134a922
PO		 431static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags)
432{
433 local_irq_save(*flags);
482fce99 434 return kmap_atomic(sg_page(sg)) + sg->offset;
2134a922
PO		 435}
436
437static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags)
438{
482fce99 439 kunmap_atomic(buffer);
2134a922
PO		 440 local_irq_restore(*flags);
441}
442
e57a5f61
AH		 443static void sdhci_adma_write_desc(struct sdhci_host *host, void *desc,
444 dma_addr_t addr, int len, unsigned cmd)
118cd17d 445{
e57a5f61 446 struct sdhci_adma2_64_desc *dma_desc = desc;
118cd17d 447
e57a5f61 448 /* 32-bit and 64-bit descriptors have these members in same position */
0545230f
AH		 449 dma_desc->cmd = cpu_to_le16(cmd);
450 dma_desc->len = cpu_to_le16(len);
e57a5f61
AH		 451 dma_desc->addr_lo = cpu_to_le32((u32)addr);
452
453 if (host->flags & SDHCI_USE_64_BIT_DMA)
454 dma_desc->addr_hi = cpu_to_le32((u64)addr >> 32);
118cd17d
BD		 455}
456
b5ffa674
AH		 457static void sdhci_adma_mark_end(void *desc)
458{
e57a5f61 459 struct sdhci_adma2_64_desc *dma_desc = desc;
b5ffa674 460
e57a5f61 461 /* 32-bit and 64-bit descriptors have 'cmd' in same position */
0545230f 462 dma_desc->cmd |= cpu_to_le16(ADMA2_END);
b5ffa674
AH		 463}
464
8f1934ce 465static int sdhci_adma_table_pre(struct sdhci_host *host,
2134a922
PO		 466 struct mmc_data *data)
467{
468 int direction;
469
1c3d5f6d
AH		 470 void *desc;
471 void *align;
2134a922
PO		 472 dma_addr_t addr;
473 dma_addr_t align_addr;
474 int len, offset;
475
476 struct scatterlist *sg;
477 int i;
478 char *buffer;
479 unsigned long flags;
480
481 /*
482 * The spec does not specify endianness of descriptor table.
483 * We currently guess that it is LE.
484 */
485
486 if (data->flags & MMC_DATA_READ)
487 direction = DMA_FROM_DEVICE;
488 else
489 direction = DMA_TO_DEVICE;
490
2134a922 491 host->align_addr = dma_map_single(mmc_dev(host->mmc),
76fe379a 492 host->align_buffer, host->align_buffer_sz, direction);
8d8bb39b 493 if (dma_mapping_error(mmc_dev(host->mmc), host->align_addr))
8f1934ce 494 goto fail;
04a5ae6f 495 BUG_ON(host->align_addr & SDHCI_ADMA2_MASK);
2134a922 496
d31911b9 497 host->sg_count = sdhci_pre_dma_transfer(host, data);
348487cb 498 if (host->sg_count < 0)
8f1934ce 499 goto unmap_align;
2134a922 500
4efaa6fb 501 desc = host->adma_table;
2134a922
PO		 502 align = host->align_buffer;
503
504 align_addr = host->align_addr;
505
506 for_each_sg(data->sg, sg, host->sg_count, i) {
507 addr = sg_dma_address(sg);
508 len = sg_dma_len(sg);
509
510 /*
511 * The SDHCI specification states that ADMA
512 * addresses must be 32-bit aligned. If they
513 * aren't, then we use a bounce buffer for
514 * the (up to three) bytes that screw up the
515 * alignment.
516 */
04a5ae6f
AH		 517 offset = (SDHCI_ADMA2_ALIGN - (addr & SDHCI_ADMA2_MASK)) &
518 SDHCI_ADMA2_MASK;
2134a922
PO		 519 if (offset) {
520 if (data->flags & MMC_DATA_WRITE) {
521 buffer = sdhci_kmap_atomic(sg, &flags);
522 memcpy(align, buffer, offset);
523 sdhci_kunmap_atomic(buffer, &flags);
524 }
525
118cd17d 526 /* tran, valid */
e57a5f61 527 sdhci_adma_write_desc(host, desc, align_addr, offset,
739d46dc 528 ADMA2_TRAN_VALID);
2134a922
PO		 529
530 BUG_ON(offset > 65536);
531
04a5ae6f
AH		 532 align += SDHCI_ADMA2_ALIGN;
533 align_addr += SDHCI_ADMA2_ALIGN;
2134a922 534
76fe379a 535 desc += host->desc_sz;
2134a922
PO		 536
537 addr += offset;
538 len -= offset;
539 }
540
2134a922
PO		 541 BUG_ON(len > 65536);
542
347ea32d
AH		 543 if (len) {
544 /* tran, valid */
545 sdhci_adma_write_desc(host, desc, addr, len,
546 ADMA2_TRAN_VALID);
547 desc += host->desc_sz;
548 }
2134a922
PO		 549
550 /*
551 * If this triggers then we have a calculation bug
552 * somewhere. :/
553 */
76fe379a 554 WARN_ON((desc - host->adma_table) >= host->adma_table_sz);
2134a922
PO		 555 }
556
70764a90
TA		 557 if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) {
558 /*
559 * Mark the last descriptor as the terminating descriptor
560 */
4efaa6fb 561 if (desc != host->adma_table) {
76fe379a 562 desc -= host->desc_sz;
b5ffa674 563 sdhci_adma_mark_end(desc);
70764a90
TA		 564 }
565 } else {
566 /*
567 * Add a terminating entry.
568 */
2134a922 569
70764a90 570 /* nop, end, valid */
e57a5f61 571 sdhci_adma_write_desc(host, desc, 0, 0, ADMA2_NOP_END_VALID);
70764a90 572 }
2134a922
PO		 573
574 /*
575 * Resync align buffer as we might have changed it.
576 */
577 if (data->flags & MMC_DATA_WRITE) {
578 dma_sync_single_for_device(mmc_dev(host->mmc),
76fe379a 579 host->align_addr, host->align_buffer_sz, direction);
2134a922
PO		 580 }
581
8f1934ce
PO		 582 return 0;
583
8f1934ce
PO		 584unmap_align:
585 dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
76fe379a 586 host->align_buffer_sz, direction);
8f1934ce
PO		 587fail:
588 return -EINVAL;
2134a922
PO		 589}
590
591static void sdhci_adma_table_post(struct sdhci_host *host,
592 struct mmc_data *data)
593{
594 int direction;
595
596 struct scatterlist *sg;
597 int i, size;
1c3d5f6d 598 void *align;
2134a922
PO		 599 char *buffer;
600 unsigned long flags;
de0b65a7 601 bool has_unaligned;
2134a922
PO		 602
603 if (data->flags & MMC_DATA_READ)
604 direction = DMA_FROM_DEVICE;
605 else
606 direction = DMA_TO_DEVICE;
607
2134a922 608 dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
76fe379a 609 host->align_buffer_sz, direction);
2134a922 610
de0b65a7
RK		 611 /* Do a quick scan of the SG list for any unaligned mappings */
612 has_unaligned = false;
613 for_each_sg(data->sg, sg, host->sg_count, i)
04a5ae6f 614 if (sg_dma_address(sg) & SDHCI_ADMA2_MASK) {
de0b65a7
RK		 615 has_unaligned = true;
616 break;
617 }
618
619 if (has_unaligned && data->flags & MMC_DATA_READ) {
2134a922
PO		 620 dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
621 data->sg_len, direction);
622
623 align = host->align_buffer;
624
625 for_each_sg(data->sg, sg, host->sg_count, i) {
04a5ae6f
AH		 626 if (sg_dma_address(sg) & SDHCI_ADMA2_MASK) {
627 size = SDHCI_ADMA2_ALIGN -
628 (sg_dma_address(sg) & SDHCI_ADMA2_MASK);
2134a922
PO		 629
630 buffer = sdhci_kmap_atomic(sg, &flags);
631 memcpy(buffer, align, size);
632 sdhci_kunmap_atomic(buffer, &flags);
633
04a5ae6f 634 align += SDHCI_ADMA2_ALIGN;
2134a922
PO		 635 }
636 }
637 }
638
d31911b9 639 if (data->host_cookie == COOKIE_MAPPED) {
348487cb
HC		 640 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
641 data->sg_len, direction);
d31911b9
HC		 642 data->host_cookie = COOKIE_UNMAPPED;
643 }
2134a922
PO		 644}
645
a3c7778f 646static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd)
d129bceb 647{
1c8cde92 648 u8 count;
a3c7778f 649 struct mmc_data *data = cmd->data;
1c8cde92 650 unsigned target_timeout, current_timeout;
d129bceb 651
ee53ab5d
PO		 652 /*
653 * If the host controller provides us with an incorrect timeout
654 * value, just skip the check and use 0xE. The hardware may take
655 * longer to time out, but that's much better than having a too-short
656 * timeout value.
657 */
11a2f1b7 658 if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL)
ee53ab5d 659 return 0xE;
e538fbe8 660
a3c7778f 661 /* Unspecified timeout, assume max */
1d4d7744 662 if (!data && !cmd->busy_timeout)
a3c7778f 663 return 0xE;
d129bceb 664
a3c7778f
AW		 665 /* timeout in us */
666 if (!data)
1d4d7744 667 target_timeout = cmd->busy_timeout * 1000;
78a2ca27
AS		 668 else {
669 target_timeout = data->timeout_ns / 1000;
670 if (host->clock)
671 target_timeout += data->timeout_clks / host->clock;
672 }
81b39802 673
1c8cde92
PO		 674 /*
675 * Figure out needed cycles.
676 * We do this in steps in order to fit inside a 32 bit int.
677 * The first step is the minimum timeout, which will have a
678 * minimum resolution of 6 bits:
679 * (1) 2^13*1000 > 2^22,
680 * (2) host->timeout_clk < 2^16
681 * =>
682 * (1) / (2) > 2^6
683 */
684 count = 0;
685 current_timeout = (1 << 13) * 1000 / host->timeout_clk;
686 while (current_timeout < target_timeout) {
687 count++;
688 current_timeout <<= 1;
689 if (count >= 0xF)
690 break;
691 }
692
693 if (count >= 0xF) {
09eeff52
CB		 694 DBG("%s: Too large timeout 0x%x requested for CMD%d!\n",
695 mmc_hostname(host->mmc), count, cmd->opcode);
1c8cde92
PO		 696 count = 0xE;
697 }
698
ee53ab5d
PO		 699 return count;
700}
701
6aa943ab
AV		 702static void sdhci_set_transfer_irqs(struct sdhci_host *host)
703{
704 u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL;
705 u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR;
706
707 if (host->flags & SDHCI_REQ_USE_DMA)
b537f94c 708 host->ier = (host->ier & ~pio_irqs) | dma_irqs;
6aa943ab 709 else
b537f94c
RK		 710 host->ier = (host->ier & ~dma_irqs) | pio_irqs;
711
712 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
713 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
6aa943ab
AV		 714}
715
b45e668a 716static void sdhci_set_timeout(struct sdhci_host *host, struct mmc_command *cmd)
ee53ab5d
PO		 717{
718 u8 count;
b45e668a
AD		 719
720 if (host->ops->set_timeout) {
721 host->ops->set_timeout(host, cmd);
722 } else {
723 count = sdhci_calc_timeout(host, cmd);
724 sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
725 }
726}
727
728static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd)
729{
2134a922 730 u8 ctrl;
a3c7778f 731 struct mmc_data *data = cmd->data;
8f1934ce 732 int ret;
ee53ab5d
PO		 733
734 WARN_ON(host->data);
735
b45e668a
AD		 736 if (data || (cmd->flags & MMC_RSP_BUSY))
737 sdhci_set_timeout(host, cmd);
a3c7778f
AW		 738
739 if (!data)
ee53ab5d
PO		 740 return;
741
742 /* Sanity checks */
743 BUG_ON(data->blksz * data->blocks > 524288);
744 BUG_ON(data->blksz > host->mmc->max_blk_size);
745 BUG_ON(data->blocks > 65535);
746
747 host->data = data;
748 host->data_early = 0;
f6a03cbf 749 host->data->bytes_xfered = 0;
ee53ab5d 750
a13abc7b 751 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))
c9fddbc4
PO		 752 host->flags |= SDHCI_REQ_USE_DMA;
753
2134a922
PO		 754 /*
755 * FIXME: This doesn't account for merging when mapping the
756 * scatterlist.
757 */
758 if (host->flags & SDHCI_REQ_USE_DMA) {
759 int broken, i;
760 struct scatterlist *sg;
761
762 broken = 0;
763 if (host->flags & SDHCI_USE_ADMA) {
764 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
765 broken = 1;
766 } else {
767 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE)
768 broken = 1;
769 }
770
771 if (unlikely(broken)) {
772 for_each_sg(data->sg, sg, data->sg_len, i) {
773 if (sg->length & 0x3) {
2e4456f0 774 DBG("Reverting to PIO because of transfer size (%d)\n",
2134a922
PO		 775 sg->length);
776 host->flags &= ~SDHCI_REQ_USE_DMA;
777 break;
778 }
779 }
780 }
c9fddbc4
PO		 781 }
782
783 /*
784 * The assumption here being that alignment is the same after
785 * translation to device address space.
786 */
2134a922
PO		 787 if (host->flags & SDHCI_REQ_USE_DMA) {
788 int broken, i;
789 struct scatterlist *sg;
790
791 broken = 0;
792 if (host->flags & SDHCI_USE_ADMA) {
793 /*
794 * As we use 3 byte chunks to work around
795 * alignment problems, we need to check this
796 * quirk.
797 */
798 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
799 broken = 1;
800 } else {
801 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR)
802 broken = 1;
803 }
804
805 if (unlikely(broken)) {
806 for_each_sg(data->sg, sg, data->sg_len, i) {
807 if (sg->offset & 0x3) {
2e4456f0 808 DBG("Reverting to PIO because of bad alignment\n");
2134a922
PO		 809 host->flags &= ~SDHCI_REQ_USE_DMA;
810 break;
811 }
812 }
813 }
814 }
815
8f1934ce
PO		 816 if (host->flags & SDHCI_REQ_USE_DMA) {
817 if (host->flags & SDHCI_USE_ADMA) {
818 ret = sdhci_adma_table_pre(host, data);
819 if (ret) {
820 /*
821 * This only happens when someone fed
822 * us an invalid request.
823 */
824 WARN_ON(1);
ebd6d357 825 host->flags &= ~SDHCI_REQ_USE_DMA;
8f1934ce 826 } else {
4e4141a5
AV		 827 sdhci_writel(host, host->adma_addr,
828 SDHCI_ADMA_ADDRESS);
e57a5f61
AH		 829 if (host->flags & SDHCI_USE_64_BIT_DMA)
830 sdhci_writel(host,
831 (u64)host->adma_addr >> 32,
832 SDHCI_ADMA_ADDRESS_HI);
8f1934ce
PO		 833 }
834 } else {
c8b3e02e 835 int sg_cnt;
8f1934ce 836
d31911b9 837 sg_cnt = sdhci_pre_dma_transfer(host, data);
62a7f368 838 if (sg_cnt <= 0) {
8f1934ce
PO		 839 /*
840 * This only happens when someone fed
841 * us an invalid request.
842 */
843 WARN_ON(1);
ebd6d357 844 host->flags &= ~SDHCI_REQ_USE_DMA;
8f1934ce 845 } else {
719a61b4 846 WARN_ON(sg_cnt != 1);
4e4141a5
AV		 847 sdhci_writel(host, sg_dma_address(data->sg),
848 SDHCI_DMA_ADDRESS);
8f1934ce
PO		 849 }
850 }
851 }
852
2134a922
PO		 853 /*
854 * Always adjust the DMA selection as some controllers
855 * (e.g. JMicron) can't do PIO properly when the selection
856 * is ADMA.
857 */
858 if (host->version >= SDHCI_SPEC_200) {
4e4141a5 859 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
2134a922
PO		 860 ctrl &= ~SDHCI_CTRL_DMA_MASK;
861 if ((host->flags & SDHCI_REQ_USE_DMA) &&
e57a5f61
AH		 862 (host->flags & SDHCI_USE_ADMA)) {
863 if (host->flags & SDHCI_USE_64_BIT_DMA)
864 ctrl |= SDHCI_CTRL_ADMA64;
865 else
866 ctrl |= SDHCI_CTRL_ADMA32;
867 } else {
2134a922 868 ctrl |= SDHCI_CTRL_SDMA;
e57a5f61 869 }
4e4141a5 870 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
c9fddbc4
PO		 871 }
872
8f1934ce 873 if (!(host->flags & SDHCI_REQ_USE_DMA)) {
da60a91d
SAS		 874 int flags;
875
876 flags = SG_MITER_ATOMIC;
877 if (host->data->flags & MMC_DATA_READ)
878 flags |= SG_MITER_TO_SG;
879 else
880 flags |= SG_MITER_FROM_SG;
881 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
7659150c 882 host->blocks = data->blocks;
d129bceb 883 }
c7fa9963 884
6aa943ab
AV		 885 sdhci_set_transfer_irqs(host);
886
f6a03cbf
MV		 887 /* Set the DMA boundary value and block size */
888 sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
889 data->blksz), SDHCI_BLOCK_SIZE);
4e4141a5 890 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
c7fa9963
PO		 891}
892
893static void sdhci_set_transfer_mode(struct sdhci_host *host,
e89d456f 894 struct mmc_command *cmd)
c7fa9963 895{
d3fc5d71 896 u16 mode = 0;
e89d456f 897 struct mmc_data *data = cmd->data;
c7fa9963 898
2b558c13 899 if (data == NULL) {
9b8ffea6
VW		 900 if (host->quirks2 &
901 SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD) {
902 sdhci_writew(host, 0x0, SDHCI_TRANSFER_MODE);
903 } else {
2b558c13 904 /* clear Auto CMD settings for no data CMDs */
9b8ffea6
VW		 905 mode = sdhci_readw(host, SDHCI_TRANSFER_MODE);
906 sdhci_writew(host, mode & ~(SDHCI_TRNS_AUTO_CMD12 |
2b558c13 907 SDHCI_TRNS_AUTO_CMD23), SDHCI_TRANSFER_MODE);
9b8ffea6 908 }
c7fa9963 909 return;
2b558c13 910 }
c7fa9963 911
e538fbe8
PO		 912 WARN_ON(!host->data);
913
d3fc5d71
VY		 914 if (!(host->quirks2 & SDHCI_QUIRK2_SUPPORT_SINGLE))
915 mode = SDHCI_TRNS_BLK_CNT_EN;
916
e89d456f 917 if (mmc_op_multi(cmd->opcode) || data->blocks > 1) {
d3fc5d71 918 mode = SDHCI_TRNS_BLK_CNT_EN | SDHCI_TRNS_MULTI;
e89d456f
AW		 919 /*
920 * If we are sending CMD23, CMD12 never gets sent
921 * on successful completion (so no Auto-CMD12).
922 */
85cc1c33
CD		 923 if (!host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD12) &&
924 (cmd->opcode != SD_IO_RW_EXTENDED))
e89d456f 925 mode |= SDHCI_TRNS_AUTO_CMD12;
8edf6371
AW		 926 else if (host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) {
927 mode |= SDHCI_TRNS_AUTO_CMD23;
928 sdhci_writel(host, host->mrq->sbc->arg, SDHCI_ARGUMENT2);
929 }
c4512f79 930 }
8edf6371 931
c7fa9963
PO		 932 if (data->flags & MMC_DATA_READ)
933 mode |= SDHCI_TRNS_READ;
c9fddbc4 934 if (host->flags & SDHCI_REQ_USE_DMA)
c7fa9963
PO		 935 mode |= SDHCI_TRNS_DMA;
936
4e4141a5 937 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
d129bceb
PO		 938}
939
940static void sdhci_finish_data(struct sdhci_host *host)
941{
942 struct mmc_data *data;
d129bceb
PO		 943
944 BUG_ON(!host->data);
945
946 data = host->data;
947 host->data = NULL;
948
c9fddbc4 949 if (host->flags & SDHCI_REQ_USE_DMA) {
2134a922
PO		 950 if (host->flags & SDHCI_USE_ADMA)
951 sdhci_adma_table_post(host, data);
952 else {
d31911b9 953 if (data->host_cookie == COOKIE_MAPPED) {
348487cb
HC		 954 dma_unmap_sg(mmc_dev(host->mmc),
955 data->sg, data->sg_len,
956 (data->flags & MMC_DATA_READ) ?
2134a922 957 DMA_FROM_DEVICE : DMA_TO_DEVICE);
d31911b9
HC		 958 data->host_cookie = COOKIE_UNMAPPED;
959 }
2134a922 960 }
d129bceb
PO		 961 }
962
963 /*
c9b74c5b
PO		 964 * The specification states that the block count register must
965 * be updated, but it does not specify at what point in the
966 * data flow. That makes the register entirely useless to read
967 * back so we have to assume that nothing made it to the card
968 * in the event of an error.
d129bceb 969 */
c9b74c5b
PO		 970 if (data->error)
971 data->bytes_xfered = 0;
d129bceb 972 else
c9b74c5b 973 data->bytes_xfered = data->blksz * data->blocks;
d129bceb 974
e89d456f
AW		 975 /*
976 * Need to send CMD12 if -
977 * a) open-ended multiblock transfer (no CMD23)
978 * b) error in multiblock transfer
979 */
980 if (data->stop &&
981 (data->error ||
982 !host->mrq->sbc)) {
983
d129bceb
PO		 984 /*
985 * The controller needs a reset of internal state machines
986 * upon error conditions.
987 */
17b0429d 988 if (data->error) {
03231f9b
RK		 989 sdhci_do_reset(host, SDHCI_RESET_CMD);
990 sdhci_do_reset(host, SDHCI_RESET_DATA);
d129bceb
PO		 991 }
992
993 sdhci_send_command(host, data->stop);
994 } else
995 tasklet_schedule(&host->finish_tasklet);
996}
997
c0e55129 998void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
d129bceb
PO		 999{
1000 int flags;
fd2208d7 1001 u32 mask;
7cb2c76f 1002 unsigned long timeout;
d129bceb
PO		 1003
1004 WARN_ON(host->cmd);
1005
96776200
RK		 1006 /* Initially, a command has no error */
1007 cmd->error = 0;
1008
d129bceb 1009 /* Wait max 10 ms */
7cb2c76f 1010 timeout = 10;
fd2208d7
PO		 1011
1012 mask = SDHCI_CMD_INHIBIT;
1013 if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
1014 mask |= SDHCI_DATA_INHIBIT;
1015
1016 /* We shouldn't wait for data inihibit for stop commands, even
1017 though they might use busy signaling */
1018 if (host->mrq->data && (cmd == host->mrq->data->stop))
1019 mask &= ~SDHCI_DATA_INHIBIT;
1020
4e4141a5 1021 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
7cb2c76f 1022 if (timeout == 0) {
2e4456f0
MV		 1023 pr_err("%s: Controller never released inhibit bit(s).\n",
1024 mmc_hostname(host->mmc));
d129bceb 1025 sdhci_dumpregs(host);
17b0429d 1026 cmd->error = -EIO;
d129bceb
PO		 1027 tasklet_schedule(&host->finish_tasklet);
1028 return;
1029 }
7cb2c76f
PO		 1030 timeout--;
1031 mdelay(1);
1032 }
d129bceb 1033
3e1a6892 1034 timeout = jiffies;
1d4d7744
UH		 1035 if (!cmd->data && cmd->busy_timeout > 9000)
1036 timeout += DIV_ROUND_UP(cmd->busy_timeout, 1000) * HZ + HZ;
3e1a6892
AH		 1037 else
1038 timeout += 10 * HZ;
1039 mod_timer(&host->timer, timeout);
d129bceb
PO		 1040
1041 host->cmd = cmd;
e99783a4 1042 host->busy_handle = 0;
d129bceb 1043
a3c7778f 1044 sdhci_prepare_data(host, cmd);
d129bceb 1045
4e4141a5 1046 sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT);
d129bceb 1047
e89d456f 1048 sdhci_set_transfer_mode(host, cmd);
c7fa9963 1049
d129bceb 1050 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
a3c76eb9 1051 pr_err("%s: Unsupported response type!\n",
d129bceb 1052 mmc_hostname(host->mmc));
17b0429d 1053 cmd->error = -EINVAL;
d129bceb
PO		 1054 tasklet_schedule(&host->finish_tasklet);
1055 return;
1056 }
1057
1058 if (!(cmd->flags & MMC_RSP_PRESENT))
1059 flags = SDHCI_CMD_RESP_NONE;
1060 else if (cmd->flags & MMC_RSP_136)
1061 flags = SDHCI_CMD_RESP_LONG;
1062 else if (cmd->flags & MMC_RSP_BUSY)
1063 flags = SDHCI_CMD_RESP_SHORT_BUSY;
1064 else
1065 flags = SDHCI_CMD_RESP_SHORT;
1066
1067 if (cmd->flags & MMC_RSP_CRC)
1068 flags |= SDHCI_CMD_CRC;
1069 if (cmd->flags & MMC_RSP_OPCODE)
1070 flags |= SDHCI_CMD_INDEX;
b513ea25
AN		 1071
1072 /* CMD19 is special in that the Data Present Select should be set */
069c9f14
G		 1073 if (cmd->data || cmd->opcode == MMC_SEND_TUNING_BLOCK ||
1074 cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200)
d129bceb
PO		 1075 flags |= SDHCI_CMD_DATA;
1076
4e4141a5 1077 sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND);
d129bceb 1078}
c0e55129 1079EXPORT_SYMBOL_GPL(sdhci_send_command);
d129bceb
PO		 1080
1081static void sdhci_finish_command(struct sdhci_host *host)
1082{
1083 int i;
1084
1085 BUG_ON(host->cmd == NULL);
1086
1087 if (host->cmd->flags & MMC_RSP_PRESENT) {
1088 if (host->cmd->flags & MMC_RSP_136) {
1089 /* CRC is stripped so we need to do some shifting. */
1090 for (i = 0;i < 4;i++) {
4e4141a5 1091 host->cmd->resp[i] = sdhci_readl(host,
d129bceb
PO		 1092 SDHCI_RESPONSE + (3-i)*4) << 8;
1093 if (i != 3)
1094 host->cmd->resp[i] |=
4e4141a5 1095 sdhci_readb(host,
d129bceb
PO		 1096 SDHCI_RESPONSE + (3-i)*4-1);
1097 }
1098 } else {
4e4141a5 1099 host->cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE);
d129bceb
PO		 1100 }
1101 }
1102
e89d456f
AW		 1103 /* Finished CMD23, now send actual command. */
1104 if (host->cmd == host->mrq->sbc) {
1105 host->cmd = NULL;
1106 sdhci_send_command(host, host->mrq->cmd);
1107 } else {
e538fbe8 1108
e89d456f
AW		 1109 /* Processed actual command. */
1110 if (host->data && host->data_early)
1111 sdhci_finish_data(host);
d129bceb 1112
e89d456f
AW		 1113 if (!host->cmd->data)
1114 tasklet_schedule(&host->finish_tasklet);
1115
1116 host->cmd = NULL;
1117 }
d129bceb
PO		 1118}
1119
52983382
KL		 1120static u16 sdhci_get_preset_value(struct sdhci_host *host)
1121{
d975f121 1122 u16 preset = 0;
52983382 1123
d975f121
RK		 1124 switch (host->timing) {
1125 case MMC_TIMING_UHS_SDR12:
52983382
KL		 1126 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1127 break;
d975f121 1128 case MMC_TIMING_UHS_SDR25:
52983382
KL		 1129 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR25);
1130 break;
d975f121 1131 case MMC_TIMING_UHS_SDR50:
52983382
KL		 1132 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR50);
1133 break;
d975f121
RK		 1134 case MMC_TIMING_UHS_SDR104:
1135 case MMC_TIMING_MMC_HS200:
52983382
KL		 1136 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR104);
1137 break;
d975f121 1138 case MMC_TIMING_UHS_DDR50:
0dafa60e 1139 case MMC_TIMING_MMC_DDR52:
52983382
KL		 1140 preset = sdhci_readw(host, SDHCI_PRESET_FOR_DDR50);
1141 break;
e9fb05d5
AH		 1142 case MMC_TIMING_MMC_HS400:
1143 preset = sdhci_readw(host, SDHCI_PRESET_FOR_HS400);
1144 break;
52983382
KL		 1145 default:
1146 pr_warn("%s: Invalid UHS-I mode selected\n",
1147 mmc_hostname(host->mmc));
1148 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1149 break;
1150 }
1151 return preset;
1152}
1153
1771059c 1154void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
d129bceb 1155{
c3ed3877 1156 int div = 0; /* Initialized for compiler warning */
df16219f 1157 int real_div = div, clk_mul = 1;
c3ed3877 1158 u16 clk = 0;
7cb2c76f 1159 unsigned long timeout;
5497159c 1160 bool switch_base_clk = false;
d129bceb 1161
1650d0c7
RK		 1162 host->mmc->actual_clock = 0;
1163
4e4141a5 1164 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
af951761 1165 if (host->quirks2 & SDHCI_QUIRK2_NEED_DELAY_AFTER_INT_CLK_RST)
1166 mdelay(1);
d129bceb
PO		 1167
1168 if (clock == 0)
373073ef 1169 return;
d129bceb 1170
85105c53 1171 if (host->version >= SDHCI_SPEC_300) {
da91a8f9 1172 if (host->preset_enabled) {
52983382
KL		 1173 u16 pre_val;
1174
1175 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1176 pre_val = sdhci_get_preset_value(host);
1177 div = (pre_val & SDHCI_PRESET_SDCLK_FREQ_MASK)
1178 >> SDHCI_PRESET_SDCLK_FREQ_SHIFT;
1179 if (host->clk_mul &&
1180 (pre_val & SDHCI_PRESET_CLKGEN_SEL_MASK)) {
1181 clk = SDHCI_PROG_CLOCK_MODE;
1182 real_div = div + 1;
1183 clk_mul = host->clk_mul;
1184 } else {
1185 real_div = max_t(int, 1, div << 1);
1186 }
1187 goto clock_set;
1188 }
1189
c3ed3877
AN		 1190 /*
1191 * Check if the Host Controller supports Programmable Clock
1192 * Mode.
1193 */
1194 if (host->clk_mul) {
52983382
KL		 1195 for (div = 1; div <= 1024; div++) {
1196 if ((host->max_clk * host->clk_mul / div)
1197 <= clock)
1198 break;
1199 }
5497159c 1200 if ((host->max_clk * host->clk_mul / div) <= clock) {
1201 /*
1202 * Set Programmable Clock Mode in the Clock
1203 * Control register.
1204 */
1205 clk = SDHCI_PROG_CLOCK_MODE;
1206 real_div = div;
1207 clk_mul = host->clk_mul;
1208 div--;
1209 } else {
1210 /*
1211 * Divisor can be too small to reach clock
1212 * speed requirement. Then use the base clock.
1213 */
1214 switch_base_clk = true;
1215 }
1216 }
1217
1218 if (!host->clk_mul || switch_base_clk) {
c3ed3877
AN		 1219 /* Version 3.00 divisors must be a multiple of 2. */
1220 if (host->max_clk <= clock)
1221 div = 1;
1222 else {
1223 for (div = 2; div < SDHCI_MAX_DIV_SPEC_300;
1224 div += 2) {
1225 if ((host->max_clk / div) <= clock)
1226 break;
1227 }
85105c53 1228 }
df16219f 1229 real_div = div;
c3ed3877 1230 div >>= 1;
d1955c3a
SG		 1231 if ((host->quirks2 & SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN)
1232 && !div && host->max_clk <= 25000000)
1233 div = 1;
85105c53
ZG		 1234 }
1235 } else {
1236 /* Version 2.00 divisors must be a power of 2. */
0397526d 1237 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
85105c53
ZG		 1238 if ((host->max_clk / div) <= clock)
1239 break;
1240 }
df16219f 1241 real_div = div;
c3ed3877 1242 div >>= 1;
d129bceb 1243 }
d129bceb 1244
52983382 1245clock_set:
03d6f5ff 1246 if (real_div)
df16219f 1247 host->mmc->actual_clock = (host->max_clk * clk_mul) / real_div;
c3ed3877 1248 clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
85105c53
ZG		 1249 clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
1250 << SDHCI_DIVIDER_HI_SHIFT;
d129bceb 1251 clk |= SDHCI_CLOCK_INT_EN;
4e4141a5 1252 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
d129bceb 1253
27f6cb16
CB		 1254 /* Wait max 20 ms */
1255 timeout = 20;
4e4141a5 1256 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
7cb2c76f
PO		 1257 & SDHCI_CLOCK_INT_STABLE)) {
1258 if (timeout == 0) {
2e4456f0
MV		 1259 pr_err("%s: Internal clock never stabilised.\n",
1260 mmc_hostname(host->mmc));
d129bceb
PO		 1261 sdhci_dumpregs(host);
1262 return;
1263 }
7cb2c76f
PO		 1264 timeout--;
1265 mdelay(1);
1266 }
d129bceb
PO		 1267
1268 clk |= SDHCI_CLOCK_CARD_EN;
4e4141a5 1269 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
d129bceb 1270}
1771059c 1271EXPORT_SYMBOL_GPL(sdhci_set_clock);
d129bceb 1272
24fbb3ca
RK		 1273static void sdhci_set_power(struct sdhci_host *host, unsigned char mode,
1274 unsigned short vdd)
146ad66e 1275{
3a48edc4 1276 struct mmc_host *mmc = host->mmc;
8364248a 1277 u8 pwr = 0;
146ad66e 1278
24fbb3ca
RK		 1279 if (mode != MMC_POWER_OFF) {
1280 switch (1 << vdd) {
ae628903
PO		 1281 case MMC_VDD_165_195:
1282 pwr = SDHCI_POWER_180;
1283 break;
1284 case MMC_VDD_29_30:
1285 case MMC_VDD_30_31:
1286 pwr = SDHCI_POWER_300;
1287 break;
1288 case MMC_VDD_32_33:
1289 case MMC_VDD_33_34:
1290 pwr = SDHCI_POWER_330;
1291 break;
1292 default:
9d5de93f
AH		 1293 WARN(1, "%s: Invalid vdd %#x\n",
1294 mmc_hostname(host->mmc), vdd);
1295 break;
ae628903
PO		 1296 }
1297 }
1298
1299 if (host->pwr == pwr)
e921a8b6 1300 return;
146ad66e 1301
ae628903
PO		 1302 host->pwr = pwr;
1303
1304 if (pwr == 0) {
4e4141a5 1305 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
f0710a55
AH		 1306 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
1307 sdhci_runtime_pm_bus_off(host);
24fbb3ca 1308 vdd = 0;
e921a8b6
RK		 1309 } else {
1310 /*
1311 * Spec says that we should clear the power reg before setting
1312 * a new value. Some controllers don't seem to like this though.
1313 */
1314 if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
1315 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
146ad66e 1316
e921a8b6
RK		 1317 /*
1318 * At least the Marvell CaFe chip gets confused if we set the
1319 * voltage and set turn on power at the same time, so set the
1320 * voltage first.
1321 */
1322 if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
1323 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
e08c1694 1324
e921a8b6 1325 pwr |= SDHCI_POWER_ON;
146ad66e 1326
e921a8b6 1327 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
557b0697 1328
e921a8b6
RK		 1329 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
1330 sdhci_runtime_pm_bus_on(host);
f0710a55 1331
e921a8b6
RK		 1332 /*
1333 * Some controllers need an extra 10ms delay of 10ms before
1334 * they can apply clock after applying power
1335 */
1336 if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER)
1337 mdelay(10);
1338 }
918f4cbd
JZ		 1339
1340 if (!IS_ERR(mmc->supply.vmmc)) {
1341 spin_unlock_irq(&host->lock);
1342 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd);
1343 spin_lock_irq(&host->lock);
1344 }
146ad66e
PO		 1345}
1346
d129bceb
PO		 1347/*****************************************************************************\
1348 * *
1349 * MMC callbacks *
1350 * *
1351\*****************************************************************************/
1352
1353static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1354{
1355 struct sdhci_host *host;
505a8680 1356 int present;
d129bceb
PO		 1357 unsigned long flags;
1358
1359 host = mmc_priv(mmc);
1360
66fd8ad5
AH		 1361 sdhci_runtime_pm_get(host);
1362
04e079cf 1363 /* Firstly check card presence */
8d28b7a7 1364 present = mmc->ops->get_cd(mmc);
2836766a 1365
d129bceb
PO		 1366 spin_lock_irqsave(&host->lock, flags);
1367
1368 WARN_ON(host->mrq != NULL);
1369
f9134319 1370#ifndef SDHCI_USE_LEDS_CLASS
d129bceb 1371 sdhci_activate_led(host);
2f730fec 1372#endif
e89d456f
AW		 1373
1374 /*
1375 * Ensure we don't send the STOP for non-SET_BLOCK_COUNTED
1376 * requests if Auto-CMD12 is enabled.
1377 */
1378 if (!mrq->sbc && (host->flags & SDHCI_AUTO_CMD12)) {
c4512f79
JH		 1379 if (mrq->stop) {
1380 mrq->data->stop = NULL;
1381 mrq->stop = NULL;
1382 }
1383 }
d129bceb
PO		 1384
1385 host->mrq = mrq;
1386
68d1fb7e 1387 if (!present || host->flags & SDHCI_DEVICE_DEAD) {
17b0429d 1388 host->mrq->cmd->error = -ENOMEDIUM;
d129bceb 1389 tasklet_schedule(&host->finish_tasklet);
cf2b5eea 1390 } else {
8edf6371 1391 if (mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23))
e89d456f
AW		 1392 sdhci_send_command(host, mrq->sbc);
1393 else
1394 sdhci_send_command(host, mrq->cmd);
cf2b5eea 1395 }
d129bceb 1396
5f25a66f 1397 mmiowb();
d129bceb
PO		 1398 spin_unlock_irqrestore(&host->lock, flags);
1399}
1400
2317f56c
RK		 1401void sdhci_set_bus_width(struct sdhci_host *host, int width)
1402{
1403 u8 ctrl;
1404
1405 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1406 if (width == MMC_BUS_WIDTH_8) {
1407 ctrl &= ~SDHCI_CTRL_4BITBUS;
1408 if (host->version >= SDHCI_SPEC_300)
1409 ctrl |= SDHCI_CTRL_8BITBUS;
1410 } else {
1411 if (host->version >= SDHCI_SPEC_300)
1412 ctrl &= ~SDHCI_CTRL_8BITBUS;
1413 if (width == MMC_BUS_WIDTH_4)
1414 ctrl |= SDHCI_CTRL_4BITBUS;
1415 else
1416 ctrl &= ~SDHCI_CTRL_4BITBUS;
1417 }
1418 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1419}
1420EXPORT_SYMBOL_GPL(sdhci_set_bus_width);
1421
96d7b78c
RK		 1422void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing)
1423{
1424 u16 ctrl_2;
1425
1426 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1427 /* Select Bus Speed Mode for host */
1428 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
1429 if ((timing == MMC_TIMING_MMC_HS200) ||
1430 (timing == MMC_TIMING_UHS_SDR104))
1431 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
1432 else if (timing == MMC_TIMING_UHS_SDR12)
1433 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
1434 else if (timing == MMC_TIMING_UHS_SDR25)
1435 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
1436 else if (timing == MMC_TIMING_UHS_SDR50)
1437 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
1438 else if ((timing == MMC_TIMING_UHS_DDR50) ||
1439 (timing == MMC_TIMING_MMC_DDR52))
1440 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
e9fb05d5
AH		 1441 else if (timing == MMC_TIMING_MMC_HS400)
1442 ctrl_2 |= SDHCI_CTRL_HS400; /* Non-standard */
96d7b78c
RK		 1443 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1444}
1445EXPORT_SYMBOL_GPL(sdhci_set_uhs_signaling);
1446
66fd8ad5 1447static void sdhci_do_set_ios(struct sdhci_host *host, struct mmc_ios *ios)
d129bceb 1448{
d129bceb
PO		 1449 unsigned long flags;
1450 u8 ctrl;
3a48edc4 1451 struct mmc_host *mmc = host->mmc;
d129bceb 1452
d129bceb
PO		 1453 spin_lock_irqsave(&host->lock, flags);
1454
ceb6143b
AH		 1455 if (host->flags & SDHCI_DEVICE_DEAD) {
1456 spin_unlock_irqrestore(&host->lock, flags);
3a48edc4
TK		 1457 if (!IS_ERR(mmc->supply.vmmc) &&
1458 ios->power_mode == MMC_POWER_OFF)
4e743f1f 1459 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
ceb6143b
AH		 1460 return;
1461 }
1e72859e 1462
d129bceb
PO		 1463 /*
1464 * Reset the chip on each power off.
1465 * Should clear out any weird states.
1466 */
1467 if (ios->power_mode == MMC_POWER_OFF) {
4e4141a5 1468 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
7260cf5e 1469 sdhci_reinit(host);
d129bceb
PO		 1470 }
1471
52983382 1472 if (host->version >= SDHCI_SPEC_300 &&
372c4634
DA		 1473 (ios->power_mode == MMC_POWER_UP) &&
1474 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN))
52983382
KL		 1475 sdhci_enable_preset_value(host, false);
1476
373073ef 1477 if (!ios->clock || ios->clock != host->clock) {
1771059c 1478 host->ops->set_clock(host, ios->clock);
373073ef 1479 host->clock = ios->clock;
03d6f5ff
AD		 1480
1481 if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK &&
1482 host->clock) {
1483 host->timeout_clk = host->mmc->actual_clock ?
1484 host->mmc->actual_clock / 1000 :
1485 host->clock / 1000;
1486 host->mmc->max_busy_timeout =
1487 host->ops->get_max_timeout_count ?
1488 host->ops->get_max_timeout_count(host) :
1489 1 << 27;
1490 host->mmc->max_busy_timeout /= host->timeout_clk;
1491 }
373073ef 1492 }
d129bceb 1493
24fbb3ca 1494 sdhci_set_power(host, ios->power_mode, ios->vdd);
d129bceb 1495
643a81ff
PR		 1496 if (host->ops->platform_send_init_74_clocks)
1497 host->ops->platform_send_init_74_clocks(host, ios->power_mode);
1498
2317f56c 1499 host->ops->set_bus_width(host, ios->bus_width);
ae6d6c92 1500
15ec4461 1501 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
cd9277c0 1502
3ab9c8da
PR		 1503 if ((ios->timing == MMC_TIMING_SD_HS ||
1504 ios->timing == MMC_TIMING_MMC_HS)
1505 && !(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT))
cd9277c0
PO		 1506 ctrl |= SDHCI_CTRL_HISPD;
1507 else
1508 ctrl &= ~SDHCI_CTRL_HISPD;
1509
d6d50a15 1510 if (host->version >= SDHCI_SPEC_300) {
49c468fc 1511 u16 clk, ctrl_2;
49c468fc
AN		 1512
1513 /* In case of UHS-I modes, set High Speed Enable */
e9fb05d5
AH		 1514 if ((ios->timing == MMC_TIMING_MMC_HS400) ||
1515 (ios->timing == MMC_TIMING_MMC_HS200) ||
bb8175a8 1516 (ios->timing == MMC_TIMING_MMC_DDR52) ||
069c9f14 1517 (ios->timing == MMC_TIMING_UHS_SDR50) ||
49c468fc
AN		 1518 (ios->timing == MMC_TIMING_UHS_SDR104) ||
1519 (ios->timing == MMC_TIMING_UHS_DDR50) ||
dd8df17f 1520 (ios->timing == MMC_TIMING_UHS_SDR25))
49c468fc 1521 ctrl |= SDHCI_CTRL_HISPD;
d6d50a15 1522
da91a8f9 1523 if (!host->preset_enabled) {
758535c4 1524 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d6d50a15
AN		 1525 /*
1526 * We only need to set Driver Strength if the
1527 * preset value enable is not set.
1528 */
da91a8f9 1529 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
d6d50a15
AN		 1530 ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK;
1531 if (ios->drv_type == MMC_SET_DRIVER_TYPE_A)
1532 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A;
43e943a0
PG		 1533 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_B)
1534 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_B;
d6d50a15
AN		 1535 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C)
1536 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C;
43e943a0
PG		 1537 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_D)
1538 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_D;
1539 else {
2e4456f0
MV		 1540 pr_warn("%s: invalid driver type, default to driver type B\n",
1541 mmc_hostname(mmc));
43e943a0
PG		 1542 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_B;
1543 }
d6d50a15
AN		 1544
1545 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
758535c4
AN		 1546 } else {
1547 /*
1548 * According to SDHC Spec v3.00, if the Preset Value
1549 * Enable in the Host Control 2 register is set, we
1550 * need to reset SD Clock Enable before changing High
1551 * Speed Enable to avoid generating clock gliches.
1552 */
758535c4
AN		 1553
1554 /* Reset SD Clock Enable */
1555 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1556 clk &= ~SDHCI_CLOCK_CARD_EN;
1557 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1558
1559 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1560
1561 /* Re-enable SD Clock */
1771059c 1562 host->ops->set_clock(host, host->clock);
d6d50a15 1563 }
49c468fc 1564
49c468fc
AN		 1565 /* Reset SD Clock Enable */
1566 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1567 clk &= ~SDHCI_CLOCK_CARD_EN;
1568 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1569
96d7b78c 1570 host->ops->set_uhs_signaling(host, ios->timing);
d975f121 1571 host->timing = ios->timing;
49c468fc 1572
52983382
KL		 1573 if (!(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN) &&
1574 ((ios->timing == MMC_TIMING_UHS_SDR12) ||
1575 (ios->timing == MMC_TIMING_UHS_SDR25) ||
1576 (ios->timing == MMC_TIMING_UHS_SDR50) ||
1577 (ios->timing == MMC_TIMING_UHS_SDR104) ||
0dafa60e
JZ		 1578 (ios->timing == MMC_TIMING_UHS_DDR50) ||
1579 (ios->timing == MMC_TIMING_MMC_DDR52))) {
52983382
KL		 1580 u16 preset;
1581
1582 sdhci_enable_preset_value(host, true);
1583 preset = sdhci_get_preset_value(host);
1584 ios->drv_type = (preset & SDHCI_PRESET_DRV_MASK)
1585 >> SDHCI_PRESET_DRV_SHIFT;
1586 }
1587
49c468fc 1588 /* Re-enable SD Clock */
1771059c 1589 host->ops->set_clock(host, host->clock);
758535c4
AN		 1590 } else
1591 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d6d50a15 1592
b8352260
LD		 1593 /*
1594 * Some (ENE) controllers go apeshit on some ios operation,
1595 * signalling timeout and CRC errors even on CMD0. Resetting
1596 * it on each ios seems to solve the problem.
1597 */
c63705e1 1598 if (host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
03231f9b 1599 sdhci_do_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
b8352260 1600
5f25a66f 1601 mmiowb();
d129bceb
PO		 1602 spin_unlock_irqrestore(&host->lock, flags);
1603}
1604
66fd8ad5
AH		 1605static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1606{
1607 struct sdhci_host *host = mmc_priv(mmc);
1608
1609 sdhci_runtime_pm_get(host);
1610 sdhci_do_set_ios(host, ios);
1611 sdhci_runtime_pm_put(host);
1612}
1613
94144a46
KL		 1614static int sdhci_do_get_cd(struct sdhci_host *host)
1615{
1616 int gpio_cd = mmc_gpio_get_cd(host->mmc);
1617
1618 if (host->flags & SDHCI_DEVICE_DEAD)
1619 return 0;
1620
88af5655
II		 1621 /* If nonremovable, assume that the card is always present. */
1622 if (host->mmc->caps & MMC_CAP_NONREMOVABLE)
94144a46
KL		 1623 return 1;
1624
88af5655
II		 1625 /*
1626 * Try slot gpio detect, if defined it take precedence
1627 * over build in controller functionality
1628 */
94144a46
KL		 1629 if (!IS_ERR_VALUE(gpio_cd))
1630 return !!gpio_cd;
1631
88af5655
II		 1632 /* If polling, assume that the card is always present. */
1633 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
1634 return 1;
1635
94144a46
KL		 1636 /* Host native card detect */
1637 return !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
1638}
1639
1640static int sdhci_get_cd(struct mmc_host *mmc)
1641{
1642 struct sdhci_host *host = mmc_priv(mmc);
1643 int ret;
1644
1645 sdhci_runtime_pm_get(host);
1646 ret = sdhci_do_get_cd(host);
1647 sdhci_runtime_pm_put(host);
1648 return ret;
1649}
1650
66fd8ad5 1651static int sdhci_check_ro(struct sdhci_host *host)
d129bceb 1652{
d129bceb 1653 unsigned long flags;
2dfb579c 1654 int is_readonly;
d129bceb 1655
d129bceb
PO		 1656 spin_lock_irqsave(&host->lock, flags);
1657
1e72859e 1658 if (host->flags & SDHCI_DEVICE_DEAD)
2dfb579c
WS		 1659 is_readonly = 0;
1660 else if (host->ops->get_ro)
1661 is_readonly = host->ops->get_ro(host);
1e72859e 1662 else
2dfb579c
WS		 1663 is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE)
1664 & SDHCI_WRITE_PROTECT);
d129bceb
PO		 1665
1666 spin_unlock_irqrestore(&host->lock, flags);
1667
2dfb579c
WS		 1668 /* This quirk needs to be replaced by a callback-function later */
1669 return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ?
1670 !is_readonly : is_readonly;
d129bceb
PO		 1671}
1672
82b0e23a
TI		 1673#define SAMPLE_COUNT 5
1674
66fd8ad5 1675static int sdhci_do_get_ro(struct sdhci_host *host)
82b0e23a 1676{
82b0e23a
TI		 1677 int i, ro_count;
1678
82b0e23a 1679 if (!(host->quirks & SDHCI_QUIRK_UNSTABLE_RO_DETECT))
66fd8ad5 1680 return sdhci_check_ro(host);
82b0e23a
TI		 1681
1682 ro_count = 0;
1683 for (i = 0; i < SAMPLE_COUNT; i++) {
66fd8ad5 1684 if (sdhci_check_ro(host)) {
82b0e23a
TI		 1685 if (++ro_count > SAMPLE_COUNT / 2)
1686 return 1;
1687 }
1688 msleep(30);
1689 }
1690 return 0;
1691}
1692
20758b66
AH		 1693static void sdhci_hw_reset(struct mmc_host *mmc)
1694{
1695 struct sdhci_host *host = mmc_priv(mmc);
1696
1697 if (host->ops && host->ops->hw_reset)
1698 host->ops->hw_reset(host);
1699}
1700
66fd8ad5 1701static int sdhci_get_ro(struct mmc_host *mmc)
f75979b7 1702{
66fd8ad5
AH		 1703 struct sdhci_host *host = mmc_priv(mmc);
1704 int ret;
f75979b7 1705
66fd8ad5
AH		 1706 sdhci_runtime_pm_get(host);
1707 ret = sdhci_do_get_ro(host);
1708 sdhci_runtime_pm_put(host);
1709 return ret;
1710}
f75979b7 1711
66fd8ad5
AH		 1712static void sdhci_enable_sdio_irq_nolock(struct sdhci_host *host, int enable)
1713{
be138554 1714 if (!(host->flags & SDHCI_DEVICE_DEAD)) {
ef104333 1715 if (enable)
b537f94c 1716 host->ier |= SDHCI_INT_CARD_INT;
ef104333 1717 else
b537f94c
RK		 1718 host->ier &= ~SDHCI_INT_CARD_INT;
1719
1720 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
1721 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
ef104333
RK		 1722 mmiowb();
1723 }
66fd8ad5
AH		 1724}
1725
1726static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1727{
1728 struct sdhci_host *host = mmc_priv(mmc);
1729 unsigned long flags;
f75979b7 1730
ef104333
RK		 1731 sdhci_runtime_pm_get(host);
1732
66fd8ad5 1733 spin_lock_irqsave(&host->lock, flags);
ef104333
RK		 1734 if (enable)
1735 host->flags |= SDHCI_SDIO_IRQ_ENABLED;
1736 else
1737 host->flags &= ~SDHCI_SDIO_IRQ_ENABLED;
1738
66fd8ad5 1739 sdhci_enable_sdio_irq_nolock(host, enable);
f75979b7 1740 spin_unlock_irqrestore(&host->lock, flags);
ef104333
RK		 1741
1742 sdhci_runtime_pm_put(host);
f75979b7
PO		 1743}
1744
20b92a30 1745static int sdhci_do_start_signal_voltage_switch(struct sdhci_host *host,
21f5998f 1746 struct mmc_ios *ios)
f2119df6 1747{
3a48edc4 1748 struct mmc_host *mmc = host->mmc;
20b92a30 1749 u16 ctrl;
6231f3de 1750 int ret;
f2119df6 1751
20b92a30
KL		 1752 /*
1753 * Signal Voltage Switching is only applicable for Host Controllers
1754 * v3.00 and above.
1755 */
1756 if (host->version < SDHCI_SPEC_300)
1757 return 0;
6231f3de 1758
f2119df6 1759 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
f2119df6 1760
21f5998f 1761 switch (ios->signal_voltage) {
20b92a30
KL		 1762 case MMC_SIGNAL_VOLTAGE_330:
1763 /* Set 1.8V Signal Enable in the Host Control2 register to 0 */
1764 ctrl &= ~SDHCI_CTRL_VDD_180;
1765 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
f2119df6 1766
3a48edc4
TK		 1767 if (!IS_ERR(mmc->supply.vqmmc)) {
1768 ret = regulator_set_voltage(mmc->supply.vqmmc, 2700000,
1769 3600000);
20b92a30 1770 if (ret) {
6606110d
JP		 1771 pr_warn("%s: Switching to 3.3V signalling voltage failed\n",
1772 mmc_hostname(mmc));
20b92a30
KL		 1773 return -EIO;
1774 }
1775 }
1776 /* Wait for 5ms */
1777 usleep_range(5000, 5500);
f2119df6 1778
20b92a30
KL		 1779 /* 3.3V regulator output should be stable within 5 ms */
1780 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1781 if (!(ctrl & SDHCI_CTRL_VDD_180))
1782 return 0;
6231f3de 1783
6606110d
JP		 1784 pr_warn("%s: 3.3V regulator output did not became stable\n",
1785 mmc_hostname(mmc));
20b92a30
KL		 1786
1787 return -EAGAIN;
1788 case MMC_SIGNAL_VOLTAGE_180:
3a48edc4
TK		 1789 if (!IS_ERR(mmc->supply.vqmmc)) {
1790 ret = regulator_set_voltage(mmc->supply.vqmmc,
20b92a30
KL		 1791 1700000, 1950000);
1792 if (ret) {
6606110d
JP		 1793 pr_warn("%s: Switching to 1.8V signalling voltage failed\n",
1794 mmc_hostname(mmc));
20b92a30
KL		 1795 return -EIO;
1796 }
1797 }
6231f3de 1798
6231f3de
PR		 1799 /*
1800 * Enable 1.8V Signal Enable in the Host Control2
1801 * register
1802 */
20b92a30
KL		 1803 ctrl |= SDHCI_CTRL_VDD_180;
1804 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
6231f3de 1805
9d967a61
VY		 1806 /* Some controller need to do more when switching */
1807 if (host->ops->voltage_switch)
1808 host->ops->voltage_switch(host);
1809
20b92a30
KL		 1810 /* 1.8V regulator output should be stable within 5 ms */
1811 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1812 if (ctrl & SDHCI_CTRL_VDD_180)
1813 return 0;
f2119df6 1814
6606110d
JP		 1815 pr_warn("%s: 1.8V regulator output did not became stable\n",
1816 mmc_hostname(mmc));
f2119df6 1817
20b92a30
KL		 1818 return -EAGAIN;
1819 case MMC_SIGNAL_VOLTAGE_120:
3a48edc4
TK		 1820 if (!IS_ERR(mmc->supply.vqmmc)) {
1821 ret = regulator_set_voltage(mmc->supply.vqmmc, 1100000,
1822 1300000);
20b92a30 1823 if (ret) {
6606110d
JP		 1824 pr_warn("%s: Switching to 1.2V signalling voltage failed\n",
1825 mmc_hostname(mmc));
20b92a30 1826 return -EIO;
f2119df6
AN		 1827 }
1828 }
6231f3de 1829 return 0;
20b92a30 1830 default:
f2119df6
AN		 1831 /* No signal voltage switch required */
1832 return 0;
20b92a30 1833 }
f2119df6
AN		 1834}
1835
66fd8ad5 1836static int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
21f5998f 1837 struct mmc_ios *ios)
66fd8ad5
AH		 1838{
1839 struct sdhci_host *host = mmc_priv(mmc);
1840 int err;
1841
1842 if (host->version < SDHCI_SPEC_300)
1843 return 0;
1844 sdhci_runtime_pm_get(host);
21f5998f 1845 err = sdhci_do_start_signal_voltage_switch(host, ios);
66fd8ad5
AH		 1846 sdhci_runtime_pm_put(host);
1847 return err;
1848}
1849
20b92a30
KL		 1850static int sdhci_card_busy(struct mmc_host *mmc)
1851{
1852 struct sdhci_host *host = mmc_priv(mmc);
1853 u32 present_state;
1854
1855 sdhci_runtime_pm_get(host);
1856 /* Check whether DAT[3:0] is 0000 */
1857 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
1858 sdhci_runtime_pm_put(host);
1859
1860 return !(present_state & SDHCI_DATA_LVL_MASK);
1861}
1862
b5540ce1
AH		 1863static int sdhci_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios)
1864{
1865 struct sdhci_host *host = mmc_priv(mmc);
1866 unsigned long flags;
1867
1868 spin_lock_irqsave(&host->lock, flags);
1869 host->flags |= SDHCI_HS400_TUNING;
1870 spin_unlock_irqrestore(&host->lock, flags);
1871
1872 return 0;
1873}
1874
069c9f14 1875static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode)
b513ea25 1876{
4b6f37d3 1877 struct sdhci_host *host = mmc_priv(mmc);
b513ea25 1878 u16 ctrl;
b513ea25 1879 int tuning_loop_counter = MAX_TUNING_LOOP;
b513ea25 1880 int err = 0;
2b35bd83 1881 unsigned long flags;
38e40bf5 1882 unsigned int tuning_count = 0;
b5540ce1 1883 bool hs400_tuning;
b513ea25 1884
66fd8ad5 1885 sdhci_runtime_pm_get(host);
2b35bd83 1886 spin_lock_irqsave(&host->lock, flags);
b513ea25 1887
b5540ce1
AH		 1888 hs400_tuning = host->flags & SDHCI_HS400_TUNING;
1889 host->flags &= ~SDHCI_HS400_TUNING;
1890
38e40bf5
AH		 1891 if (host->tuning_mode == SDHCI_TUNING_MODE_1)
1892 tuning_count = host->tuning_count;
1893
b513ea25 1894 /*
9faac7b9
WY		 1895 * The Host Controller needs tuning in case of SDR104 and DDR50
1896 * mode, and for SDR50 mode when Use Tuning for SDR50 is set in
1897 * the Capabilities register.
069c9f14
G		 1898 * If the Host Controller supports the HS200 mode then the
1899 * tuning function has to be executed.
b513ea25 1900 */
4b6f37d3 1901 switch (host->timing) {
b5540ce1 1902 /* HS400 tuning is done in HS200 mode */
e9fb05d5 1903 case MMC_TIMING_MMC_HS400:
b5540ce1
AH		 1904 err = -EINVAL;
1905 goto out_unlock;
1906
4b6f37d3 1907 case MMC_TIMING_MMC_HS200:
b5540ce1
AH		 1908 /*
1909 * Periodic re-tuning for HS400 is not expected to be needed, so
1910 * disable it here.
1911 */
1912 if (hs400_tuning)
1913 tuning_count = 0;
1914 break;
1915
4b6f37d3 1916 case MMC_TIMING_UHS_SDR104:
9faac7b9 1917 case MMC_TIMING_UHS_DDR50:
4b6f37d3
RK		 1918 break;
1919
1920 case MMC_TIMING_UHS_SDR50:
1921 if (host->flags & SDHCI_SDR50_NEEDS_TUNING ||
1922 host->flags & SDHCI_SDR104_NEEDS_TUNING)
1923 break;
1924 /* FALLTHROUGH */
1925
1926 default:
d519c863 1927 goto out_unlock;
b513ea25
AN		 1928 }
1929
45251812 1930 if (host->ops->platform_execute_tuning) {
2b35bd83 1931 spin_unlock_irqrestore(&host->lock, flags);
45251812
DA		 1932 err = host->ops->platform_execute_tuning(host, opcode);
1933 sdhci_runtime_pm_put(host);
1934 return err;
1935 }
1936
4b6f37d3
RK		 1937 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1938 ctrl |= SDHCI_CTRL_EXEC_TUNING;
67d0d04a
VY		 1939 if (host->quirks2 & SDHCI_QUIRK2_TUNING_WORK_AROUND)
1940 ctrl |= SDHCI_CTRL_TUNED_CLK;
b513ea25
AN		 1941 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1942
1943 /*
1944 * As per the Host Controller spec v3.00, tuning command
1945 * generates Buffer Read Ready interrupt, so enable that.
1946 *
1947 * Note: The spec clearly says that when tuning sequence
1948 * is being performed, the controller does not generate
1949 * interrupts other than Buffer Read Ready interrupt. But
1950 * to make sure we don't hit a controller bug, we _only_
1951 * enable Buffer Read Ready interrupt here.
1952 */
b537f94c
RK		 1953 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE);
1954 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE);
b513ea25
AN		 1955
1956 /*
1957 * Issue CMD19 repeatedly till Execute Tuning is set to 0 or the number
1958 * of loops reaches 40 times or a timeout of 150ms occurs.
1959 */
b513ea25
AN		 1960 do {
1961 struct mmc_command cmd = {0};
66fd8ad5 1962 struct mmc_request mrq = {NULL};
b513ea25 1963
069c9f14 1964 cmd.opcode = opcode;
b513ea25
AN		 1965 cmd.arg = 0;
1966 cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
1967 cmd.retries = 0;
1968 cmd.data = NULL;
1969 cmd.error = 0;
1970
7ce45e95
AC		 1971 if (tuning_loop_counter-- == 0)
1972 break;
1973
b513ea25
AN		 1974 mrq.cmd = &cmd;
1975 host->mrq = &mrq;
1976
1977 /*
1978 * In response to CMD19, the card sends 64 bytes of tuning
1979 * block to the Host Controller. So we set the block size
1980 * to 64 here.
1981 */
069c9f14
G		 1982 if (cmd.opcode == MMC_SEND_TUNING_BLOCK_HS200) {
1983 if (mmc->ios.bus_width == MMC_BUS_WIDTH_8)
1984 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 128),
1985 SDHCI_BLOCK_SIZE);
1986 else if (mmc->ios.bus_width == MMC_BUS_WIDTH_4)
1987 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
1988 SDHCI_BLOCK_SIZE);
1989 } else {
1990 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
1991 SDHCI_BLOCK_SIZE);
1992 }
b513ea25
AN		 1993
1994 /*
1995 * The tuning block is sent by the card to the host controller.
1996 * So we set the TRNS_READ bit in the Transfer Mode register.
1997 * This also takes care of setting DMA Enable and Multi Block
1998 * Select in the same register to 0.
1999 */
2000 sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
2001
2002 sdhci_send_command(host, &cmd);
2003
2004 host->cmd = NULL;
2005 host->mrq = NULL;
2006
2b35bd83 2007 spin_unlock_irqrestore(&host->lock, flags);
b513ea25
AN		 2008 /* Wait for Buffer Read Ready interrupt */
2009 wait_event_interruptible_timeout(host->buf_ready_int,
2010 (host->tuning_done == 1),
2011 msecs_to_jiffies(50));
2b35bd83 2012 spin_lock_irqsave(&host->lock, flags);
b513ea25
AN		 2013
2014 if (!host->tuning_done) {
2e4456f0 2015 pr_info(DRIVER_NAME ": Timeout waiting for Buffer Read Ready interrupt during tuning procedure, falling back to fixed sampling clock\n");
b513ea25
AN		 2016 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2017 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
2018 ctrl &= ~SDHCI_CTRL_EXEC_TUNING;
2019 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2020
2021 err = -EIO;
2022 goto out;
2023 }
2024
2025 host->tuning_done = 0;
2026
2027 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
197160d5
NS		 2028
2029 /* eMMC spec does not require a delay between tuning cycles */
2030 if (opcode == MMC_SEND_TUNING_BLOCK)
2031 mdelay(1);
b513ea25
AN		 2032 } while (ctrl & SDHCI_CTRL_EXEC_TUNING);
2033
2034 /*
2035 * The Host Driver has exhausted the maximum number of loops allowed,
2036 * so use fixed sampling frequency.
2037 */
7ce45e95 2038 if (tuning_loop_counter < 0) {
b513ea25
AN		 2039 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
2040 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
7ce45e95
AC		 2041 }
2042 if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) {
2e4456f0 2043 pr_info(DRIVER_NAME ": Tuning procedure failed, falling back to fixed sampling clock\n");
114f2bf6 2044 err = -EIO;
b513ea25
AN		 2045 }
2046
2047out:
38e40bf5 2048 if (tuning_count) {
66c39dfc
AH		 2049 /*
2050 * In case tuning fails, host controllers which support
2051 * re-tuning can try tuning again at a later time, when the
2052 * re-tuning timer expires. So for these controllers, we
2053 * return 0. Since there might be other controllers who do not
2054 * have this capability, we return error for them.
2055 */
2056 err = 0;
cf2b5eea
AN		 2057 }
2058
66c39dfc 2059 host->mmc->retune_period = err ? 0 : tuning_count;
cf2b5eea 2060
b537f94c
RK		 2061 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2062 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
d519c863 2063out_unlock:
2b35bd83 2064 spin_unlock_irqrestore(&host->lock, flags);
66fd8ad5 2065 sdhci_runtime_pm_put(host);
b513ea25
AN		 2066
2067 return err;
2068}
2069
cb849648
AH		 2070static int sdhci_select_drive_strength(struct mmc_card *card,
2071 unsigned int max_dtr, int host_drv,
2072 int card_drv, int *drv_type)
2073{
2074 struct sdhci_host *host = mmc_priv(card->host);
2075
2076 if (!host->ops->select_drive_strength)
2077 return 0;
2078
2079 return host->ops->select_drive_strength(host, card, max_dtr, host_drv,
2080 card_drv, drv_type);
2081}
52983382
KL		 2082
2083static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable)
4d55c5a1 2084{
4d55c5a1
AN		 2085 /* Host Controller v3.00 defines preset value registers */
2086 if (host->version < SDHCI_SPEC_300)
2087 return;
2088
4d55c5a1
AN		 2089 /*
2090 * We only enable or disable Preset Value if they are not already
2091 * enabled or disabled respectively. Otherwise, we bail out.
2092 */
da91a8f9
RK		 2093 if (host->preset_enabled != enable) {
2094 u16 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2095
2096 if (enable)
2097 ctrl |= SDHCI_CTRL_PRESET_VAL_ENABLE;
2098 else
2099 ctrl &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
2100
4d55c5a1 2101 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
da91a8f9
RK		 2102
2103 if (enable)
2104 host->flags |= SDHCI_PV_ENABLED;
2105 else
2106 host->flags &= ~SDHCI_PV_ENABLED;
2107
2108 host->preset_enabled = enable;
4d55c5a1 2109 }
66fd8ad5
AH		 2110}
2111
348487cb
HC		 2112static void sdhci_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
2113 int err)
2114{
2115 struct sdhci_host *host = mmc_priv(mmc);
2116 struct mmc_data *data = mrq->data;
2117
2118 if (host->flags & SDHCI_REQ_USE_DMA) {
d31911b9
HC		 2119 if (data->host_cookie == COOKIE_GIVEN ||
2120 data->host_cookie == COOKIE_MAPPED)
348487cb
HC		 2121 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
2122 data->flags & MMC_DATA_WRITE ?
2123 DMA_TO_DEVICE : DMA_FROM_DEVICE);
d31911b9 2124 data->host_cookie = COOKIE_UNMAPPED;
348487cb
HC		 2125 }
2126}
2127
2128static int sdhci_pre_dma_transfer(struct sdhci_host *host,
d31911b9 2129 struct mmc_data *data)
348487cb
HC		 2130{
2131 int sg_count;
2132
d31911b9
HC		 2133 if (data->host_cookie == COOKIE_MAPPED) {
2134 data->host_cookie = COOKIE_GIVEN;
2135 return data->sg_count;
348487cb
HC		 2136 }
2137
d31911b9 2138 WARN_ON(data->host_cookie == COOKIE_GIVEN);
348487cb 2139
d31911b9
HC		 2140 sg_count = dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
2141 data->flags & MMC_DATA_WRITE ?
2142 DMA_TO_DEVICE : DMA_FROM_DEVICE);
348487cb
HC		 2143
2144 if (sg_count == 0)
d31911b9 2145 return -ENOSPC;
348487cb 2146
d31911b9
HC		 2147 data->sg_count = sg_count;
2148 data->host_cookie = COOKIE_MAPPED;
348487cb
HC		 2149
2150 return sg_count;
2151}
2152
2153static void sdhci_pre_req(struct mmc_host *mmc, struct mmc_request *mrq,
2154 bool is_first_req)
2155{
2156 struct sdhci_host *host = mmc_priv(mmc);
2157
d31911b9 2158 mrq->data->host_cookie = COOKIE_UNMAPPED;
348487cb
HC		 2159
2160 if (host->flags & SDHCI_REQ_USE_DMA)
d31911b9 2161 sdhci_pre_dma_transfer(host, mrq->data);
348487cb
HC		 2162}
2163
71e69211 2164static void sdhci_card_event(struct mmc_host *mmc)
d129bceb 2165{
71e69211 2166 struct sdhci_host *host = mmc_priv(mmc);
d129bceb 2167 unsigned long flags;
2836766a 2168 int present;
d129bceb 2169
722e1280
CD		 2170 /* First check if client has provided their own card event */
2171 if (host->ops->card_event)
2172 host->ops->card_event(host);
2173
2836766a
KK		 2174 present = sdhci_do_get_cd(host);
2175
d129bceb
PO		 2176 spin_lock_irqsave(&host->lock, flags);
2177
66fd8ad5 2178 /* Check host->mrq first in case we are runtime suspended */
2836766a 2179 if (host->mrq && !present) {
a3c76eb9 2180 pr_err("%s: Card removed during transfer!\n",
66fd8ad5 2181 mmc_hostname(host->mmc));
a3c76eb9 2182 pr_err("%s: Resetting controller.\n",
66fd8ad5 2183 mmc_hostname(host->mmc));
d129bceb 2184
03231f9b
RK		 2185 sdhci_do_reset(host, SDHCI_RESET_CMD);
2186 sdhci_do_reset(host, SDHCI_RESET_DATA);
d129bceb 2187
66fd8ad5
AH		 2188 host->mrq->cmd->error = -ENOMEDIUM;
2189 tasklet_schedule(&host->finish_tasklet);
d129bceb
PO		 2190 }
2191
2192 spin_unlock_irqrestore(&host->lock, flags);
71e69211
GL		 2193}
2194
2195static const struct mmc_host_ops sdhci_ops = {
2196 .request = sdhci_request,
348487cb
HC		 2197 .post_req = sdhci_post_req,
2198 .pre_req = sdhci_pre_req,
71e69211 2199 .set_ios = sdhci_set_ios,
94144a46 2200 .get_cd = sdhci_get_cd,
71e69211
GL		 2201 .get_ro = sdhci_get_ro,
2202 .hw_reset = sdhci_hw_reset,
2203 .enable_sdio_irq = sdhci_enable_sdio_irq,
2204 .start_signal_voltage_switch = sdhci_start_signal_voltage_switch,
b5540ce1 2205 .prepare_hs400_tuning = sdhci_prepare_hs400_tuning,
71e69211 2206 .execute_tuning = sdhci_execute_tuning,
cb849648 2207 .select_drive_strength = sdhci_select_drive_strength,
71e69211 2208 .card_event = sdhci_card_event,
20b92a30 2209 .card_busy = sdhci_card_busy,
71e69211
GL		 2210};
2211
2212/*****************************************************************************\
2213 * *
2214 * Tasklets *
2215 * *
2216\*****************************************************************************/
2217
d129bceb
PO		 2218static void sdhci_tasklet_finish(unsigned long param)
2219{
2220 struct sdhci_host *host;
2221 unsigned long flags;
2222 struct mmc_request *mrq;
2223
2224 host = (struct sdhci_host*)param;
2225
66fd8ad5
AH		 2226 spin_lock_irqsave(&host->lock, flags);
2227
0c9c99a7
CB		 2228 /*
2229 * If this tasklet gets rescheduled while running, it will
2230 * be run again afterwards but without any active request.
2231 */
66fd8ad5
AH		 2232 if (!host->mrq) {
2233 spin_unlock_irqrestore(&host->lock, flags);
0c9c99a7 2234 return;
66fd8ad5 2235 }
d129bceb
PO		 2236
2237 del_timer(&host->timer);
2238
2239 mrq = host->mrq;
2240
d129bceb
PO		 2241 /*
2242 * The controller needs a reset of internal state machines
2243 * upon error conditions.
2244 */
1e72859e 2245 if (!(host->flags & SDHCI_DEVICE_DEAD) &&
b7b4d342 2246 ((mrq->cmd && mrq->cmd->error) ||
fce9d33f
AG		 2247 (mrq->sbc && mrq->sbc->error) ||
2248 (mrq->data && ((mrq->data->error && !mrq->data->stop) ||
2249 (mrq->data->stop && mrq->data->stop->error))) ||
2250 (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) {
645289dc
PO		 2251
2252 /* Some controllers need this kick or reset won't work here */
8213af3b 2253 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)
645289dc 2254 /* This is to force an update */
1771059c 2255 host->ops->set_clock(host, host->clock);
645289dc
PO		 2256
2257 /* Spec says we should do both at the same time, but Ricoh
2258 controllers do not like that. */
03231f9b
RK		 2259 sdhci_do_reset(host, SDHCI_RESET_CMD);
2260 sdhci_do_reset(host, SDHCI_RESET_DATA);
d129bceb
PO		 2261 }
2262
2263 host->mrq = NULL;
2264 host->cmd = NULL;
2265 host->data = NULL;
2266
f9134319 2267#ifndef SDHCI_USE_LEDS_CLASS
d129bceb 2268 sdhci_deactivate_led(host);
2f730fec 2269#endif
d129bceb 2270
5f25a66f 2271 mmiowb();
d129bceb
PO		 2272 spin_unlock_irqrestore(&host->lock, flags);
2273
2274 mmc_request_done(host->mmc, mrq);
66fd8ad5 2275 sdhci_runtime_pm_put(host);
d129bceb
PO		 2276}
2277
2278static void sdhci_timeout_timer(unsigned long data)
2279{
2280 struct sdhci_host *host;
2281 unsigned long flags;
2282
2283 host = (struct sdhci_host*)data;
2284
2285 spin_lock_irqsave(&host->lock, flags);
2286
2287 if (host->mrq) {
2e4456f0
MV		 2288 pr_err("%s: Timeout waiting for hardware interrupt.\n",
2289 mmc_hostname(host->mmc));
d129bceb
PO		 2290 sdhci_dumpregs(host);
2291
2292 if (host->data) {
17b0429d 2293 host->data->error = -ETIMEDOUT;
d129bceb
PO		 2294 sdhci_finish_data(host);
2295 } else {
2296 if (host->cmd)
17b0429d 2297 host->cmd->error = -ETIMEDOUT;
d129bceb 2298 else
17b0429d 2299 host->mrq->cmd->error = -ETIMEDOUT;
d129bceb
PO		 2300
2301 tasklet_schedule(&host->finish_tasklet);
2302 }
2303 }
2304
5f25a66f 2305 mmiowb();
d129bceb
PO		 2306 spin_unlock_irqrestore(&host->lock, flags);
2307}
2308
2309/*****************************************************************************\
2310 * *
2311 * Interrupt handling *
2312 * *
2313\*****************************************************************************/
2314
61541397 2315static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask, u32 *mask)
d129bceb
PO		 2316{
2317 BUG_ON(intmask == 0);
2318
2319 if (!host->cmd) {
2e4456f0
MV		 2320 pr_err("%s: Got command interrupt 0x%08x even though no command operation was in progress.\n",
2321 mmc_hostname(host->mmc), (unsigned)intmask);
d129bceb
PO		 2322 sdhci_dumpregs(host);
2323 return;
2324 }
2325
ec014cba
RK		 2326 if (intmask & (SDHCI_INT_TIMEOUT | SDHCI_INT_CRC |
2327 SDHCI_INT_END_BIT | SDHCI_INT_INDEX)) {
2328 if (intmask & SDHCI_INT_TIMEOUT)
2329 host->cmd->error = -ETIMEDOUT;
2330 else
2331 host->cmd->error = -EILSEQ;
43b58b36 2332
71fcbda0
RK		 2333 /*
2334 * If this command initiates a data phase and a response
2335 * CRC error is signalled, the card can start transferring
2336 * data - the card may have received the command without
2337 * error. We must not terminate the mmc_request early.
2338 *
2339 * If the card did not receive the command or returned an
2340 * error which prevented it sending data, the data phase
2341 * will time out.
2342 */
2343 if (host->cmd->data &&
2344 (intmask & (SDHCI_INT_CRC | SDHCI_INT_TIMEOUT)) ==
2345 SDHCI_INT_CRC) {
2346 host->cmd = NULL;
2347 return;
2348 }
2349
d129bceb 2350 tasklet_schedule(&host->finish_tasklet);
e809517f
PO		 2351 return;
2352 }
2353
2354 /*
2355 * The host can send and interrupt when the busy state has
2356 * ended, allowing us to wait without wasting CPU cycles.
2357 * Unfortunately this is overloaded on the "data complete"
2358 * interrupt, so we need to take some care when handling
2359 * it.
2360 *
2361 * Note: The 1.0 specification is a bit ambiguous about this
2362 * feature so there might be some problems with older
2363 * controllers.
2364 */
2365 if (host->cmd->flags & MMC_RSP_BUSY) {
2366 if (host->cmd->data)
2e4456f0 2367 DBG("Cannot wait for busy signal when also doing a data transfer");
e99783a4
CM		 2368 else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ)
2369 && !host->busy_handle) {
2370 /* Mark that command complete before busy is ended */
2371 host->busy_handle = 1;
e809517f 2372 return;
e99783a4 2373 }
f945405c
BD		 2374
2375 /* The controller does not support the end-of-busy IRQ,
2376 * fall through and take the SDHCI_INT_RESPONSE */
61541397
AH		 2377 } else if ((host->quirks2 & SDHCI_QUIRK2_STOP_WITH_TC) &&
2378 host->cmd->opcode == MMC_STOP_TRANSMISSION && !host->data) {
2379 *mask &= ~SDHCI_INT_DATA_END;
e809517f
PO		 2380 }
2381
2382 if (intmask & SDHCI_INT_RESPONSE)
43b58b36 2383 sdhci_finish_command(host);
d129bceb
PO		 2384}
2385
0957c333 2386#ifdef CONFIG_MMC_DEBUG
08621b18 2387static void sdhci_adma_show_error(struct sdhci_host *host)
6882a8c0
BD		 2388{
2389 const char *name = mmc_hostname(host->mmc);
1c3d5f6d 2390 void *desc = host->adma_table;
6882a8c0
BD		 2391
2392 sdhci_dumpregs(host);
2393
2394 while (true) {
e57a5f61
AH		 2395 struct sdhci_adma2_64_desc *dma_desc = desc;
2396
2397 if (host->flags & SDHCI_USE_64_BIT_DMA)
2398 DBG("%s: %p: DMA 0x%08x%08x, LEN 0x%04x, Attr=0x%02x\n",
2399 name, desc, le32_to_cpu(dma_desc->addr_hi),
2400 le32_to_cpu(dma_desc->addr_lo),
2401 le16_to_cpu(dma_desc->len),
2402 le16_to_cpu(dma_desc->cmd));
2403 else
2404 DBG("%s: %p: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n",
2405 name, desc, le32_to_cpu(dma_desc->addr_lo),
2406 le16_to_cpu(dma_desc->len),
2407 le16_to_cpu(dma_desc->cmd));
6882a8c0 2408
76fe379a 2409 desc += host->desc_sz;
6882a8c0 2410
0545230f 2411 if (dma_desc->cmd & cpu_to_le16(ADMA2_END))
6882a8c0
BD		 2412 break;
2413 }
2414}
2415#else
08621b18 2416static void sdhci_adma_show_error(struct sdhci_host *host) { }
6882a8c0
BD		 2417#endif
2418
d129bceb
PO		 2419static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
2420{
069c9f14 2421 u32 command;
d129bceb
PO		 2422 BUG_ON(intmask == 0);
2423
b513ea25
AN		 2424 /* CMD19 generates _only_ Buffer Read Ready interrupt */
2425 if (intmask & SDHCI_INT_DATA_AVAIL) {
069c9f14
G		 2426 command = SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND));
2427 if (command == MMC_SEND_TUNING_BLOCK ||
2428 command == MMC_SEND_TUNING_BLOCK_HS200) {
b513ea25
AN		 2429 host->tuning_done = 1;
2430 wake_up(&host->buf_ready_int);
2431 return;
2432 }
2433 }
2434
d129bceb
PO		 2435 if (!host->data) {
2436 /*
e809517f
PO		 2437 * The "data complete" interrupt is also used to
2438 * indicate that a busy state has ended. See comment
2439 * above in sdhci_cmd_irq().
d129bceb 2440 */
e809517f 2441 if (host->cmd && (host->cmd->flags & MMC_RSP_BUSY)) {
c5abd5e8
MC		 2442 if (intmask & SDHCI_INT_DATA_TIMEOUT) {
2443 host->cmd->error = -ETIMEDOUT;
2444 tasklet_schedule(&host->finish_tasklet);
2445 return;
2446 }
e809517f 2447 if (intmask & SDHCI_INT_DATA_END) {
e99783a4
CM		 2448 /*
2449 * Some cards handle busy-end interrupt
2450 * before the command completed, so make
2451 * sure we do things in the proper order.
2452 */
2453 if (host->busy_handle)
2454 sdhci_finish_command(host);
2455 else
2456 host->busy_handle = 1;
e809517f
PO		 2457 return;
2458 }
2459 }
d129bceb 2460
2e4456f0
MV		 2461 pr_err("%s: Got data interrupt 0x%08x even though no data operation was in progress.\n",
2462 mmc_hostname(host->mmc), (unsigned)intmask);
d129bceb
PO		 2463 sdhci_dumpregs(host);
2464
2465 return;
2466 }
2467
2468 if (intmask & SDHCI_INT_DATA_TIMEOUT)
17b0429d 2469 host->data->error = -ETIMEDOUT;
22113efd
AL		 2470 else if (intmask & SDHCI_INT_DATA_END_BIT)
2471 host->data->error = -EILSEQ;
2472 else if ((intmask & SDHCI_INT_DATA_CRC) &&
2473 SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))
2474 != MMC_BUS_TEST_R)
17b0429d 2475 host->data->error = -EILSEQ;
6882a8c0 2476 else if (intmask & SDHCI_INT_ADMA_ERROR) {
a3c76eb9 2477 pr_err("%s: ADMA error\n", mmc_hostname(host->mmc));
08621b18 2478 sdhci_adma_show_error(host);
2134a922 2479 host->data->error = -EIO;
a4071fbb
HZ		 2480 if (host->ops->adma_workaround)
2481 host->ops->adma_workaround(host, intmask);
6882a8c0 2482 }
d129bceb 2483
17b0429d 2484 if (host->data->error)
d129bceb
PO		 2485 sdhci_finish_data(host);
2486 else {
a406f5a3 2487 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
d129bceb
PO		 2488 sdhci_transfer_pio(host);
2489
6ba736a1
PO		 2490 /*
2491 * We currently don't do anything fancy with DMA
2492 * boundaries, but as we can't disable the feature
2493 * we need to at least restart the transfer.
f6a03cbf
MV		 2494 *
2495 * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS)
2496 * should return a valid address to continue from, but as
2497 * some controllers are faulty, don't trust them.
6ba736a1 2498 */
f6a03cbf
MV		 2499 if (intmask & SDHCI_INT_DMA_END) {
2500 u32 dmastart, dmanow;
2501 dmastart = sg_dma_address(host->data->sg);
2502 dmanow = dmastart + host->data->bytes_xfered;
2503 /*
2504 * Force update to the next DMA block boundary.
2505 */
2506 dmanow = (dmanow &
2507 ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) +
2508 SDHCI_DEFAULT_BOUNDARY_SIZE;
2509 host->data->bytes_xfered = dmanow - dmastart;
2510 DBG("%s: DMA base 0x%08x, transferred 0x%06x bytes,"
2511 " next 0x%08x\n",
2512 mmc_hostname(host->mmc), dmastart,
2513 host->data->bytes_xfered, dmanow);
2514 sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS);
2515 }
6ba736a1 2516
e538fbe8
PO		 2517 if (intmask & SDHCI_INT_DATA_END) {
2518 if (host->cmd) {
2519 /*
2520 * Data managed to finish before the
2521 * command completed. Make sure we do
2522 * things in the proper order.
2523 */
2524 host->data_early = 1;
2525 } else {
2526 sdhci_finish_data(host);
2527 }
2528 }
d129bceb
PO		 2529 }
2530}
2531
7d12e780 2532static irqreturn_t sdhci_irq(int irq, void *dev_id)
d129bceb 2533{
781e989c 2534 irqreturn_t result = IRQ_NONE;
66fd8ad5 2535 struct sdhci_host *host = dev_id;
41005003 2536 u32 intmask, mask, unexpected = 0;
781e989c 2537 int max_loops = 16;
d129bceb
PO		 2538
2539 spin_lock(&host->lock);
2540
be138554 2541 if (host->runtime_suspended && !sdhci_sdio_irq_enabled(host)) {
66fd8ad5 2542 spin_unlock(&host->lock);
655bca76 2543 return IRQ_NONE;
66fd8ad5
AH		 2544 }
2545
4e4141a5 2546 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
62df67a5 2547 if (!intmask || intmask == 0xffffffff) {
d129bceb
PO		 2548 result = IRQ_NONE;
2549 goto out;
2550 }
2551
41005003
RK		 2552 do {
2553 /* Clear selected interrupts. */
2554 mask = intmask & (SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
2555 SDHCI_INT_BUS_POWER);
2556 sdhci_writel(host, mask, SDHCI_INT_STATUS);
d129bceb 2557
41005003
RK		 2558 DBG("*** %s got interrupt: 0x%08x\n",
2559 mmc_hostname(host->mmc), intmask);
d129bceb 2560
41005003
RK		 2561 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
2562 u32 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
2563 SDHCI_CARD_PRESENT;
d129bceb 2564
41005003
RK		 2565 /*
2566 * There is a observation on i.mx esdhc. INSERT
2567 * bit will be immediately set again when it gets
2568 * cleared, if a card is inserted. We have to mask
2569 * the irq to prevent interrupt storm which will
2570 * freeze the system. And the REMOVE gets the
2571 * same situation.
2572 *
2573 * More testing are needed here to ensure it works
2574 * for other platforms though.
2575 */
b537f94c
RK		 2576 host->ier &= ~(SDHCI_INT_CARD_INSERT |
2577 SDHCI_INT_CARD_REMOVE);
2578 host->ier |= present ? SDHCI_INT_CARD_REMOVE :
2579 SDHCI_INT_CARD_INSERT;
2580 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2581 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
41005003
RK		 2582
2583 sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT |
2584 SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS);
3560db8e
RK		 2585
2586 host->thread_isr |= intmask & (SDHCI_INT_CARD_INSERT |
2587 SDHCI_INT_CARD_REMOVE);
2588 result = IRQ_WAKE_THREAD;
41005003 2589 }
d129bceb 2590
41005003 2591 if (intmask & SDHCI_INT_CMD_MASK)
61541397
AH		 2592 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK,
2593 &intmask);
964f9ce2 2594
41005003
RK		 2595 if (intmask & SDHCI_INT_DATA_MASK)
2596 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
d129bceb 2597
41005003
RK		 2598 if (intmask & SDHCI_INT_BUS_POWER)
2599 pr_err("%s: Card is consuming too much power!\n",
2600 mmc_hostname(host->mmc));
3192a28f 2601
781e989c
RK		 2602 if (intmask & SDHCI_INT_CARD_INT) {
2603 sdhci_enable_sdio_irq_nolock(host, false);
2604 host->thread_isr |= SDHCI_INT_CARD_INT;
2605 result = IRQ_WAKE_THREAD;
2606 }
f75979b7 2607
41005003
RK		 2608 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE |
2609 SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
2610 SDHCI_INT_ERROR | SDHCI_INT_BUS_POWER |
2611 SDHCI_INT_CARD_INT);
f75979b7 2612
41005003
RK		 2613 if (intmask) {
2614 unexpected |= intmask;
2615 sdhci_writel(host, intmask, SDHCI_INT_STATUS);
2616 }
d129bceb 2617
781e989c
RK		 2618 if (result == IRQ_NONE)
2619 result = IRQ_HANDLED;
d129bceb 2620
41005003 2621 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
41005003 2622 } while (intmask && --max_loops);
d129bceb
PO		 2623out:
2624 spin_unlock(&host->lock);
2625
6379b237
AS		 2626 if (unexpected) {
2627 pr_err("%s: Unexpected interrupt 0x%08x.\n",
2628 mmc_hostname(host->mmc), unexpected);
2629 sdhci_dumpregs(host);
2630 }
f75979b7 2631
d129bceb
PO		 2632 return result;
2633}
2634
781e989c
RK		 2635static irqreturn_t sdhci_thread_irq(int irq, void *dev_id)
2636{
2637 struct sdhci_host *host = dev_id;
2638 unsigned long flags;
2639 u32 isr;
2640
2641 spin_lock_irqsave(&host->lock, flags);
2642 isr = host->thread_isr;
2643 host->thread_isr = 0;
2644 spin_unlock_irqrestore(&host->lock, flags);
2645
3560db8e
RK		 2646 if (isr & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
2647 sdhci_card_event(host->mmc);
2648 mmc_detect_change(host->mmc, msecs_to_jiffies(200));
2649 }
2650
781e989c
RK		 2651 if (isr & SDHCI_INT_CARD_INT) {
2652 sdio_run_irqs(host->mmc);
2653
2654 spin_lock_irqsave(&host->lock, flags);
2655 if (host->flags & SDHCI_SDIO_IRQ_ENABLED)
2656 sdhci_enable_sdio_irq_nolock(host, true);
2657 spin_unlock_irqrestore(&host->lock, flags);
2658 }
2659
2660 return isr ? IRQ_HANDLED : IRQ_NONE;
2661}
2662
d129bceb
PO		 2663/*****************************************************************************\
2664 * *
2665 * Suspend/resume *
2666 * *
2667\*****************************************************************************/
2668
2669#ifdef CONFIG_PM
ad080d79
KL		 2670void sdhci_enable_irq_wakeups(struct sdhci_host *host)
2671{
2672 u8 val;
2673 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
2674 | SDHCI_WAKE_ON_INT;
2675
2676 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2677 val |= mask ;
2678 /* Avoid fake wake up */
2679 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
2680 val &= ~(SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE);
2681 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2682}
2683EXPORT_SYMBOL_GPL(sdhci_enable_irq_wakeups);
2684
0b10f478 2685static void sdhci_disable_irq_wakeups(struct sdhci_host *host)
ad080d79
KL		 2686{
2687 u8 val;
2688 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
2689 | SDHCI_WAKE_ON_INT;
2690
2691 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2692 val &= ~mask;
2693 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2694}
d129bceb 2695
29495aa0 2696int sdhci_suspend_host(struct sdhci_host *host)
d129bceb 2697{
7260cf5e
AV		 2698 sdhci_disable_card_detection(host);
2699
66c39dfc
AH		 2700 mmc_retune_timer_stop(host->mmc);
2701 mmc_retune_needed(host->mmc);
cf2b5eea 2702
ad080d79 2703 if (!device_may_wakeup(mmc_dev(host->mmc))) {
b537f94c
RK		 2704 host->ier = 0;
2705 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
2706 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
ad080d79
KL		 2707 free_irq(host->irq, host);
2708 } else {
2709 sdhci_enable_irq_wakeups(host);
2710 enable_irq_wake(host->irq);
2711 }
4ee14ec6 2712 return 0;
d129bceb
PO		 2713}
2714
b8c86fc5 2715EXPORT_SYMBOL_GPL(sdhci_suspend_host);
d129bceb 2716
b8c86fc5
PO		 2717int sdhci_resume_host(struct sdhci_host *host)
2718{
4ee14ec6 2719 int ret = 0;
d129bceb 2720
a13abc7b 2721 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
b8c86fc5
PO		 2722 if (host->ops->enable_dma)
2723 host->ops->enable_dma(host);
2724 }
d129bceb 2725
6308d290
AH		 2726 if ((host->mmc->pm_flags & MMC_PM_KEEP_POWER) &&
2727 (host->quirks2 & SDHCI_QUIRK2_HOST_OFF_CARD_ON)) {
2728 /* Card keeps power but host controller does not */
2729 sdhci_init(host, 0);
2730 host->pwr = 0;
2731 host->clock = 0;
2732 sdhci_do_set_ios(host, &host->mmc->ios);
2733 } else {
2734 sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER));
2735 mmiowb();
2736 }
b8c86fc5 2737
14a7b416
HC		 2738 if (!device_may_wakeup(mmc_dev(host->mmc))) {
2739 ret = request_threaded_irq(host->irq, sdhci_irq,
2740 sdhci_thread_irq, IRQF_SHARED,
2741 mmc_hostname(host->mmc), host);
2742 if (ret)
2743 return ret;
2744 } else {
2745 sdhci_disable_irq_wakeups(host);
2746 disable_irq_wake(host->irq);
2747 }
2748
7260cf5e
AV		 2749 sdhci_enable_card_detection(host);
2750
2f4cbb3d 2751 return ret;
d129bceb
PO		 2752}
2753
b8c86fc5 2754EXPORT_SYMBOL_GPL(sdhci_resume_host);
66fd8ad5
AH		 2755
2756static int sdhci_runtime_pm_get(struct sdhci_host *host)
2757{
2758 return pm_runtime_get_sync(host->mmc->parent);
2759}
2760
2761static int sdhci_runtime_pm_put(struct sdhci_host *host)
2762{
2763 pm_runtime_mark_last_busy(host->mmc->parent);
2764 return pm_runtime_put_autosuspend(host->mmc->parent);
2765}
2766
f0710a55
AH		 2767static void sdhci_runtime_pm_bus_on(struct sdhci_host *host)
2768{
5c671c41 2769 if (host->bus_on)
f0710a55
AH		 2770 return;
2771 host->bus_on = true;
2772 pm_runtime_get_noresume(host->mmc->parent);
2773}
2774
2775static void sdhci_runtime_pm_bus_off(struct sdhci_host *host)
2776{
5c671c41 2777 if (!host->bus_on)
f0710a55
AH		 2778 return;
2779 host->bus_on = false;
2780 pm_runtime_put_noidle(host->mmc->parent);
2781}
2782
66fd8ad5
AH		 2783int sdhci_runtime_suspend_host(struct sdhci_host *host)
2784{
2785 unsigned long flags;
66fd8ad5 2786
66c39dfc
AH		 2787 mmc_retune_timer_stop(host->mmc);
2788 mmc_retune_needed(host->mmc);
66fd8ad5
AH		 2789
2790 spin_lock_irqsave(&host->lock, flags);
b537f94c
RK		 2791 host->ier &= SDHCI_INT_CARD_INT;
2792 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2793 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
66fd8ad5
AH		 2794 spin_unlock_irqrestore(&host->lock, flags);
2795
781e989c 2796 synchronize_hardirq(host->irq);
66fd8ad5
AH		 2797
2798 spin_lock_irqsave(&host->lock, flags);
2799 host->runtime_suspended = true;
2800 spin_unlock_irqrestore(&host->lock, flags);
2801
8a125bad 2802 return 0;
66fd8ad5
AH		 2803}
2804EXPORT_SYMBOL_GPL(sdhci_runtime_suspend_host);
2805
2806int sdhci_runtime_resume_host(struct sdhci_host *host)
2807{
2808 unsigned long flags;
8a125bad 2809 int host_flags = host->flags;
66fd8ad5
AH		 2810
2811 if (host_flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2812 if (host->ops->enable_dma)
2813 host->ops->enable_dma(host);
2814 }
2815
2816 sdhci_init(host, 0);
2817
2818 /* Force clock and power re-program */
2819 host->pwr = 0;
2820 host->clock = 0;
3396e736 2821 sdhci_do_start_signal_voltage_switch(host, &host->mmc->ios);
66fd8ad5
AH		 2822 sdhci_do_set_ios(host, &host->mmc->ios);
2823
52983382
KL		 2824 if ((host_flags & SDHCI_PV_ENABLED) &&
2825 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN)) {
2826 spin_lock_irqsave(&host->lock, flags);
2827 sdhci_enable_preset_value(host, true);
2828 spin_unlock_irqrestore(&host->lock, flags);
2829 }
66fd8ad5 2830
66fd8ad5
AH		 2831 spin_lock_irqsave(&host->lock, flags);
2832
2833 host->runtime_suspended = false;
2834
2835 /* Enable SDIO IRQ */
ef104333 2836 if (host->flags & SDHCI_SDIO_IRQ_ENABLED)
66fd8ad5
AH		 2837 sdhci_enable_sdio_irq_nolock(host, true);
2838
2839 /* Enable Card Detection */
2840 sdhci_enable_card_detection(host);
2841
2842 spin_unlock_irqrestore(&host->lock, flags);
2843
8a125bad 2844 return 0;
66fd8ad5
AH		 2845}
2846EXPORT_SYMBOL_GPL(sdhci_runtime_resume_host);
2847
162d6f98 2848#endif /* CONFIG_PM */
66fd8ad5 2849
d129bceb
PO		 2850/*****************************************************************************\
2851 * *
b8c86fc5 2852 * Device allocation/registration *
d129bceb
PO		 2853 * *
2854\*****************************************************************************/
2855
b8c86fc5
PO		 2856struct sdhci_host *sdhci_alloc_host(struct device *dev,
2857 size_t priv_size)
d129bceb 2858{
d129bceb
PO		 2859 struct mmc_host *mmc;
2860 struct sdhci_host *host;
2861
b8c86fc5 2862 WARN_ON(dev == NULL);
d129bceb 2863
b8c86fc5 2864 mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev);
d129bceb 2865 if (!mmc)
b8c86fc5 2866 return ERR_PTR(-ENOMEM);
d129bceb
PO		 2867
2868 host = mmc_priv(mmc);
2869 host->mmc = mmc;
bf60e592
AH		 2870 host->mmc_host_ops = sdhci_ops;
2871 mmc->ops = &host->mmc_host_ops;
d129bceb 2872
b8c86fc5
PO		 2873 return host;
2874}
8a4da143 2875
b8c86fc5 2876EXPORT_SYMBOL_GPL(sdhci_alloc_host);
d129bceb 2877
b8c86fc5
PO		 2878int sdhci_add_host(struct sdhci_host *host)
2879{
2880 struct mmc_host *mmc;
bd6a8c30 2881 u32 caps[2] = {0, 0};
f2119df6
AN		 2882 u32 max_current_caps;
2883 unsigned int ocr_avail;
f5fa92e5 2884 unsigned int override_timeout_clk;
59241757 2885 u32 max_clk;
b8c86fc5 2886 int ret;
d129bceb 2887
b8c86fc5
PO		 2888 WARN_ON(host == NULL);
2889 if (host == NULL)
2890 return -EINVAL;
d129bceb 2891
b8c86fc5 2892 mmc = host->mmc;
d129bceb 2893
b8c86fc5
PO		 2894 if (debug_quirks)
2895 host->quirks = debug_quirks;
66fd8ad5
AH		 2896 if (debug_quirks2)
2897 host->quirks2 = debug_quirks2;
d129bceb 2898
f5fa92e5
AH		 2899 override_timeout_clk = host->timeout_clk;
2900
03231f9b 2901 sdhci_do_reset(host, SDHCI_RESET_ALL);
d96649ed 2902
4e4141a5 2903 host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
2134a922
PO		 2904 host->version = (host->version & SDHCI_SPEC_VER_MASK)
2905 >> SDHCI_SPEC_VER_SHIFT;
85105c53 2906 if (host->version > SDHCI_SPEC_300) {
2e4456f0
MV		 2907 pr_err("%s: Unknown controller version (%d). You may experience problems.\n",
2908 mmc_hostname(mmc), host->version);
4a965505
PO		 2909 }
2910
f2119df6 2911 caps[0] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ? host->caps :
ccc92c23 2912 sdhci_readl(host, SDHCI_CAPABILITIES);
d129bceb 2913
bd6a8c30
PR		 2914 if (host->version >= SDHCI_SPEC_300)
2915 caps[1] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ?
2916 host->caps1 :
2917 sdhci_readl(host, SDHCI_CAPABILITIES_1);
f2119df6 2918
b8c86fc5 2919 if (host->quirks & SDHCI_QUIRK_FORCE_DMA)
a13abc7b 2920 host->flags |= SDHCI_USE_SDMA;
f2119df6 2921 else if (!(caps[0] & SDHCI_CAN_DO_SDMA))
a13abc7b 2922 DBG("Controller doesn't have SDMA capability\n");
67435274 2923 else
a13abc7b 2924 host->flags |= SDHCI_USE_SDMA;
d129bceb 2925
b8c86fc5 2926 if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
a13abc7b 2927 (host->flags & SDHCI_USE_SDMA)) {
cee687ce 2928 DBG("Disabling DMA as it is marked broken\n");
a13abc7b 2929 host->flags &= ~SDHCI_USE_SDMA;
7c168e3d
FT		 2930 }
2931
f2119df6
AN		 2932 if ((host->version >= SDHCI_SPEC_200) &&
2933 (caps[0] & SDHCI_CAN_DO_ADMA2))
a13abc7b 2934 host->flags |= SDHCI_USE_ADMA;
2134a922
PO		 2935
2936 if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) &&
2937 (host->flags & SDHCI_USE_ADMA)) {
2938 DBG("Disabling ADMA as it is marked broken\n");
2939 host->flags &= ~SDHCI_USE_ADMA;
2940 }
2941
e57a5f61
AH		 2942 /*
2943 * It is assumed that a 64-bit capable device has set a 64-bit DMA mask
2944 * and *must* do 64-bit DMA. A driver has the opportunity to change
2945 * that during the first call to ->enable_dma(). Similarly
2946 * SDHCI_QUIRK2_BROKEN_64_BIT_DMA must be left to the drivers to
2947 * implement.
2948 */
5eaa7476 2949 if (caps[0] & SDHCI_CAN_64BIT)
e57a5f61
AH		 2950 host->flags |= SDHCI_USE_64_BIT_DMA;
2951
a13abc7b 2952 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
b8c86fc5
PO		 2953 if (host->ops->enable_dma) {
2954 if (host->ops->enable_dma(host)) {
6606110d 2955 pr_warn("%s: No suitable DMA available - falling back to PIO\n",
b8c86fc5 2956 mmc_hostname(mmc));
a13abc7b
RR		 2957 host->flags &=
2958 ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
b8c86fc5 2959 }
d129bceb
PO		 2960 }
2961 }
2962
e57a5f61
AH		 2963 /* SDMA does not support 64-bit DMA */
2964 if (host->flags & SDHCI_USE_64_BIT_DMA)
2965 host->flags &= ~SDHCI_USE_SDMA;
2966
2134a922
PO		 2967 if (host->flags & SDHCI_USE_ADMA) {
2968 /*
76fe379a
AH		 2969 * The DMA descriptor table size is calculated as the maximum
2970 * number of segments times 2, to allow for an alignment
2971 * descriptor for each segment, plus 1 for a nop end descriptor,
2972 * all multipled by the descriptor size.
2134a922 2973 */
e57a5f61
AH		 2974 if (host->flags & SDHCI_USE_64_BIT_DMA) {
2975 host->adma_table_sz = (SDHCI_MAX_SEGS * 2 + 1) *
2976 SDHCI_ADMA2_64_DESC_SZ;
e57a5f61 2977 host->desc_sz = SDHCI_ADMA2_64_DESC_SZ;
e57a5f61
AH		 2978 } else {
2979 host->adma_table_sz = (SDHCI_MAX_SEGS * 2 + 1) *
2980 SDHCI_ADMA2_32_DESC_SZ;
e57a5f61 2981 host->desc_sz = SDHCI_ADMA2_32_DESC_SZ;
e57a5f61 2982 }
4efaa6fb 2983 host->adma_table = dma_alloc_coherent(mmc_dev(mmc),
76fe379a 2984 host->adma_table_sz,
4efaa6fb
AH		 2985 &host->adma_addr,
2986 GFP_KERNEL);
04a5ae6f 2987 host->align_buffer_sz = SDHCI_MAX_SEGS * SDHCI_ADMA2_ALIGN;
76fe379a 2988 host->align_buffer = kmalloc(host->align_buffer_sz, GFP_KERNEL);
4efaa6fb 2989 if (!host->adma_table || !host->align_buffer) {
7ac02036
PF		 2990 if (host->adma_table)
2991 dma_free_coherent(mmc_dev(mmc),
2992 host->adma_table_sz,
2993 host->adma_table,
2994 host->adma_addr);
2134a922 2995 kfree(host->align_buffer);
6606110d 2996 pr_warn("%s: Unable to allocate ADMA buffers - falling back to standard DMA\n",
2134a922
PO		 2997 mmc_hostname(mmc));
2998 host->flags &= ~SDHCI_USE_ADMA;
4efaa6fb 2999 host->adma_table = NULL;
d1e49f77 3000 host->align_buffer = NULL;
04a5ae6f 3001 } else if (host->adma_addr & (SDHCI_ADMA2_DESC_ALIGN - 1)) {
6606110d
JP		 3002 pr_warn("%s: unable to allocate aligned ADMA descriptor\n",
3003 mmc_hostname(mmc));
d1e49f77 3004 host->flags &= ~SDHCI_USE_ADMA;
76fe379a 3005 dma_free_coherent(mmc_dev(mmc), host->adma_table_sz,
4efaa6fb 3006 host->adma_table, host->adma_addr);
d1e49f77 3007 kfree(host->align_buffer);
4efaa6fb 3008 host->adma_table = NULL;
d1e49f77 3009 host->align_buffer = NULL;
2134a922
PO		 3010 }
3011 }
3012
7659150c
PO		 3013 /*
3014 * If we use DMA, then it's up to the caller to set the DMA
3015 * mask, but PIO does not need the hw shim so we set a new
3016 * mask here in that case.
3017 */
a13abc7b 3018 if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) {
7659150c 3019 host->dma_mask = DMA_BIT_MASK(64);
4e743f1f 3020 mmc_dev(mmc)->dma_mask = &host->dma_mask;
7659150c 3021 }
d129bceb 3022
c4687d5f 3023 if (host->version >= SDHCI_SPEC_300)
f2119df6 3024 host->max_clk = (caps[0] & SDHCI_CLOCK_V3_BASE_MASK)
c4687d5f
ZG		 3025 >> SDHCI_CLOCK_BASE_SHIFT;
3026 else
f2119df6 3027 host->max_clk = (caps[0] & SDHCI_CLOCK_BASE_MASK)
c4687d5f
ZG		 3028 >> SDHCI_CLOCK_BASE_SHIFT;
3029
4240ff0a 3030 host->max_clk *= 1000000;
f27f47ef
AV		 3031 if (host->max_clk == 0 || host->quirks &
3032 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) {
4240ff0a 3033 if (!host->ops->get_max_clock) {
2e4456f0
MV		 3034 pr_err("%s: Hardware doesn't specify base clock frequency.\n",
3035 mmc_hostname(mmc));
4240ff0a
BD		 3036 return -ENODEV;
3037 }
3038 host->max_clk = host->ops->get_max_clock(host);
8ef1a143 3039 }
d129bceb 3040
c3ed3877
AN		 3041 /*
3042 * In case of Host Controller v3.00, find out whether clock
3043 * multiplier is supported.
3044 */
3045 host->clk_mul = (caps[1] & SDHCI_CLOCK_MUL_MASK) >>
3046 SDHCI_CLOCK_MUL_SHIFT;
3047
3048 /*
3049 * In case the value in Clock Multiplier is 0, then programmable
3050 * clock mode is not supported, otherwise the actual clock
3051 * multiplier is one more than the value of Clock Multiplier
3052 * in the Capabilities Register.
3053 */
3054 if (host->clk_mul)
3055 host->clk_mul += 1;
3056
d129bceb
PO		 3057 /*
3058 * Set host parameters.
3059 */
59241757
DA		 3060 max_clk = host->max_clk;
3061
ce5f036b 3062 if (host->ops->get_min_clock)
a9e58f25 3063 mmc->f_min = host->ops->get_min_clock(host);
c3ed3877
AN		 3064 else if (host->version >= SDHCI_SPEC_300) {
3065 if (host->clk_mul) {
3066 mmc->f_min = (host->max_clk * host->clk_mul) / 1024;
59241757 3067 max_clk = host->max_clk * host->clk_mul;
c3ed3877
AN		 3068 } else
3069 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300;
3070 } else
0397526d 3071 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200;
15ec4461 3072
59241757
DA		 3073 if (!mmc->f_max || (mmc->f_max && (mmc->f_max > max_clk)))
3074 mmc->f_max = max_clk;
3075
28aab053
AD		 3076 if (!(host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) {
3077 host->timeout_clk = (caps[0] & SDHCI_TIMEOUT_CLK_MASK) >>
3078 SDHCI_TIMEOUT_CLK_SHIFT;
3079 if (host->timeout_clk == 0) {
3080 if (host->ops->get_timeout_clock) {
3081 host->timeout_clk =
3082 host->ops->get_timeout_clock(host);
3083 } else {
3084 pr_err("%s: Hardware doesn't specify timeout clock frequency.\n",
3085 mmc_hostname(mmc));
3086 return -ENODEV;
3087 }
272308ca 3088 }
272308ca 3089
28aab053
AD		 3090 if (caps[0] & SDHCI_TIMEOUT_CLK_UNIT)
3091 host->timeout_clk *= 1000;
272308ca 3092
28aab053 3093 mmc->max_busy_timeout = host->ops->get_max_timeout_count ?
a6ff5aeb 3094 host->ops->get_max_timeout_count(host) : 1 << 27;
28aab053
AD		 3095 mmc->max_busy_timeout /= host->timeout_clk;
3096 }
58d1246d 3097
f5fa92e5
AH		 3098 if (override_timeout_clk)
3099 host->timeout_clk = override_timeout_clk;
3100
e89d456f 3101 mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_ERASE | MMC_CAP_CMD23;
781e989c 3102 mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD;
e89d456f
AW		 3103
3104 if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12)
3105 host->flags |= SDHCI_AUTO_CMD12;
5fe23c7f 3106
8edf6371 3107 /* Auto-CMD23 stuff only works in ADMA or PIO. */
4f3d3e9b 3108 if ((host->version >= SDHCI_SPEC_300) &&
8edf6371 3109 ((host->flags & SDHCI_USE_ADMA) ||
3bfa6f03
SB		 3110 !(host->flags & SDHCI_USE_SDMA)) &&
3111 !(host->quirks2 & SDHCI_QUIRK2_ACMD23_BROKEN)) {
8edf6371
AW		 3112 host->flags |= SDHCI_AUTO_CMD23;
3113 DBG("%s: Auto-CMD23 available\n", mmc_hostname(mmc));
3114 } else {
3115 DBG("%s: Auto-CMD23 unavailable\n", mmc_hostname(mmc));
3116 }
3117
15ec4461
PR		 3118 /*
3119 * A controller may support 8-bit width, but the board itself
3120 * might not have the pins brought out. Boards that support
3121 * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in
3122 * their platform code before calling sdhci_add_host(), and we
3123 * won't assume 8-bit width for hosts without that CAP.
3124 */
5fe23c7f 3125 if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA))
15ec4461 3126 mmc->caps |= MMC_CAP_4_BIT_DATA;
d129bceb 3127
63ef5d8c
JH		 3128 if (host->quirks2 & SDHCI_QUIRK2_HOST_NO_CMD23)
3129 mmc->caps &= ~MMC_CAP_CMD23;
3130
f2119df6 3131 if (caps[0] & SDHCI_CAN_DO_HISPD)
a29e7e18 3132 mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
cd9277c0 3133
176d1ed4 3134 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) &&
c31d22eb
II		 3135 !(mmc->caps & MMC_CAP_NONREMOVABLE) &&
3136 IS_ERR_VALUE(mmc_gpio_get_cd(host->mmc)))
68d1fb7e
AV		 3137 mmc->caps |= MMC_CAP_NEEDS_POLL;
3138
3a48edc4
TK		 3139 /* If there are external regulators, get them */
3140 if (mmc_regulator_get_supply(mmc) == -EPROBE_DEFER)
3141 return -EPROBE_DEFER;
3142
6231f3de 3143 /* If vqmmc regulator and no 1.8V signalling, then there's no UHS */
3a48edc4
TK		 3144 if (!IS_ERR(mmc->supply.vqmmc)) {
3145 ret = regulator_enable(mmc->supply.vqmmc);
3146 if (!regulator_is_supported_voltage(mmc->supply.vqmmc, 1700000,
3147 1950000))
8363c374
KL		 3148 caps[1] &= ~(SDHCI_SUPPORT_SDR104 |
3149 SDHCI_SUPPORT_SDR50 |
3150 SDHCI_SUPPORT_DDR50);
a3361aba
CB		 3151 if (ret) {
3152 pr_warn("%s: Failed to enable vqmmc regulator: %d\n",
3153 mmc_hostname(mmc), ret);
4bb74313 3154 mmc->supply.vqmmc = ERR_PTR(-EINVAL);
a3361aba 3155 }
8363c374 3156 }
6231f3de 3157
6a66180a
DD		 3158 if (host->quirks2 & SDHCI_QUIRK2_NO_1_8_V)
3159 caps[1] &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
3160 SDHCI_SUPPORT_DDR50);
3161
4188bba0
AC		 3162 /* Any UHS-I mode in caps implies SDR12 and SDR25 support. */
3163 if (caps[1] & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
3164 SDHCI_SUPPORT_DDR50))
f2119df6
AN		 3165 mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;
3166
3167 /* SDR104 supports also implies SDR50 support */
156e14b1 3168 if (caps[1] & SDHCI_SUPPORT_SDR104) {
f2119df6 3169 mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50;
156e14b1
GC		 3170 /* SD3.0: SDR104 is supported so (for eMMC) the caps2
3171 * field can be promoted to support HS200.
3172 */
549c0b18 3173 if (!(host->quirks2 & SDHCI_QUIRK2_BROKEN_HS200))
13868bf2 3174 mmc->caps2 |= MMC_CAP2_HS200;
156e14b1 3175 } else if (caps[1] & SDHCI_SUPPORT_SDR50)
f2119df6
AN		 3176 mmc->caps |= MMC_CAP_UHS_SDR50;
3177
e9fb05d5
AH		 3178 if (host->quirks2 & SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 &&
3179 (caps[1] & SDHCI_SUPPORT_HS400))
3180 mmc->caps2 |= MMC_CAP2_HS400;
3181
549c0b18
AH		 3182 if ((mmc->caps2 & MMC_CAP2_HSX00_1_2V) &&
3183 (IS_ERR(mmc->supply.vqmmc) ||
3184 !regulator_is_supported_voltage(mmc->supply.vqmmc, 1100000,
3185 1300000)))
3186 mmc->caps2 &= ~MMC_CAP2_HSX00_1_2V;
3187
9107ebbf
MC		 3188 if ((caps[1] & SDHCI_SUPPORT_DDR50) &&
3189 !(host->quirks2 & SDHCI_QUIRK2_BROKEN_DDR50))
f2119df6
AN		 3190 mmc->caps |= MMC_CAP_UHS_DDR50;
3191
069c9f14 3192 /* Does the host need tuning for SDR50? */
b513ea25
AN		 3193 if (caps[1] & SDHCI_USE_SDR50_TUNING)
3194 host->flags |= SDHCI_SDR50_NEEDS_TUNING;
3195
156e14b1 3196 /* Does the host need tuning for SDR104 / HS200? */
069c9f14 3197 if (mmc->caps2 & MMC_CAP2_HS200)
156e14b1 3198 host->flags |= SDHCI_SDR104_NEEDS_TUNING;
069c9f14 3199
d6d50a15
AN		 3200 /* Driver Type(s) (A, C, D) supported by the host */
3201 if (caps[1] & SDHCI_DRIVER_TYPE_A)
3202 mmc->caps |= MMC_CAP_DRIVER_TYPE_A;
3203 if (caps[1] & SDHCI_DRIVER_TYPE_C)
3204 mmc->caps |= MMC_CAP_DRIVER_TYPE_C;
3205 if (caps[1] & SDHCI_DRIVER_TYPE_D)
3206 mmc->caps |= MMC_CAP_DRIVER_TYPE_D;
3207
cf2b5eea
AN		 3208 /* Initial value for re-tuning timer count */
3209 host->tuning_count = (caps[1] & SDHCI_RETUNING_TIMER_COUNT_MASK) >>
3210 SDHCI_RETUNING_TIMER_COUNT_SHIFT;
3211
3212 /*
3213 * In case Re-tuning Timer is not disabled, the actual value of
3214 * re-tuning timer will be 2 ^ (n - 1).
3215 */
3216 if (host->tuning_count)
3217 host->tuning_count = 1 << (host->tuning_count - 1);
3218
3219 /* Re-tuning mode supported by the Host Controller */
3220 host->tuning_mode = (caps[1] & SDHCI_RETUNING_MODE_MASK) >>
3221 SDHCI_RETUNING_MODE_SHIFT;
3222
8f230f45 3223 ocr_avail = 0;
bad37e1a 3224
f2119df6
AN		 3225 /*
3226 * According to SD Host Controller spec v3.00, if the Host System
3227 * can afford more than 150mA, Host Driver should set XPC to 1. Also
3228 * the value is meaningful only if Voltage Support in the Capabilities
3229 * register is set. The actual current value is 4 times the register
3230 * value.
3231 */
3232 max_current_caps = sdhci_readl(host, SDHCI_MAX_CURRENT);
3a48edc4 3233 if (!max_current_caps && !IS_ERR(mmc->supply.vmmc)) {
ae906037 3234 int curr = regulator_get_current_limit(mmc->supply.vmmc);
bad37e1a
PR		 3235 if (curr > 0) {
3236
3237 /* convert to SDHCI_MAX_CURRENT format */
3238 curr = curr/1000; /* convert to mA */
3239 curr = curr/SDHCI_MAX_CURRENT_MULTIPLIER;
3240
3241 curr = min_t(u32, curr, SDHCI_MAX_CURRENT_LIMIT);
3242 max_current_caps =
3243 (curr << SDHCI_MAX_CURRENT_330_SHIFT) |
3244 (curr << SDHCI_MAX_CURRENT_300_SHIFT) |
3245 (curr << SDHCI_MAX_CURRENT_180_SHIFT);
3246 }
3247 }
f2119df6
AN		 3248
3249 if (caps[0] & SDHCI_CAN_VDD_330) {
8f230f45 3250 ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34;
f2119df6 3251
55c4665e 3252 mmc->max_current_330 = ((max_current_caps &
f2119df6
AN		 3253 SDHCI_MAX_CURRENT_330_MASK) >>
3254 SDHCI_MAX_CURRENT_330_SHIFT) *
3255 SDHCI_MAX_CURRENT_MULTIPLIER;
f2119df6
AN		 3256 }
3257 if (caps[0] & SDHCI_CAN_VDD_300) {
8f230f45 3258 ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31;
f2119df6 3259
55c4665e 3260 mmc->max_current_300 = ((max_current_caps &
f2119df6
AN		 3261 SDHCI_MAX_CURRENT_300_MASK) >>
3262 SDHCI_MAX_CURRENT_300_SHIFT) *
3263 SDHCI_MAX_CURRENT_MULTIPLIER;
f2119df6
AN		 3264 }
3265 if (caps[0] & SDHCI_CAN_VDD_180) {
8f230f45
TI		 3266 ocr_avail |= MMC_VDD_165_195;
3267
55c4665e 3268 mmc->max_current_180 = ((max_current_caps &
f2119df6
AN		 3269 SDHCI_MAX_CURRENT_180_MASK) >>
3270 SDHCI_MAX_CURRENT_180_SHIFT) *
3271 SDHCI_MAX_CURRENT_MULTIPLIER;
f2119df6
AN		 3272 }
3273
5fd26c7e
UH		 3274 /* If OCR set by host, use it instead. */
3275 if (host->ocr_mask)
3276 ocr_avail = host->ocr_mask;
3277
3278 /* If OCR set by external regulators, give it highest prio. */
3a48edc4 3279 if (mmc->ocr_avail)
52221610 3280 ocr_avail = mmc->ocr_avail;
3a48edc4 3281
8f230f45
TI		 3282 mmc->ocr_avail = ocr_avail;
3283 mmc->ocr_avail_sdio = ocr_avail;
3284 if (host->ocr_avail_sdio)
3285 mmc->ocr_avail_sdio &= host->ocr_avail_sdio;
3286 mmc->ocr_avail_sd = ocr_avail;
3287 if (host->ocr_avail_sd)
3288 mmc->ocr_avail_sd &= host->ocr_avail_sd;
3289 else /* normal SD controllers don't support 1.8V */
3290 mmc->ocr_avail_sd &= ~MMC_VDD_165_195;
3291 mmc->ocr_avail_mmc = ocr_avail;
3292 if (host->ocr_avail_mmc)
3293 mmc->ocr_avail_mmc &= host->ocr_avail_mmc;
146ad66e
PO		 3294
3295 if (mmc->ocr_avail == 0) {
2e4456f0
MV		 3296 pr_err("%s: Hardware doesn't report any support voltages.\n",
3297 mmc_hostname(mmc));
b8c86fc5 3298 return -ENODEV;
146ad66e
PO		 3299 }
3300
d129bceb
PO		 3301 spin_lock_init(&host->lock);
3302
3303 /*
2134a922
PO		 3304 * Maximum number of segments. Depends on if the hardware
3305 * can do scatter/gather or not.
d129bceb 3306 */
2134a922 3307 if (host->flags & SDHCI_USE_ADMA)
4fb213f8 3308 mmc->max_segs = SDHCI_MAX_SEGS;
a13abc7b 3309 else if (host->flags & SDHCI_USE_SDMA)
a36274e0 3310 mmc->max_segs = 1;
2134a922 3311 else /* PIO */
4fb213f8 3312 mmc->max_segs = SDHCI_MAX_SEGS;
d129bceb
PO		 3313
3314 /*
ac00531d
AH		 3315 * Maximum number of sectors in one transfer. Limited by SDMA boundary
3316 * size (512KiB). Note some tuning modes impose a 4MiB limit, but this
3317 * is less anyway.
d129bceb 3318 */
55db890a 3319 mmc->max_req_size = 524288;
d129bceb
PO		 3320
3321 /*
3322 * Maximum segment size. Could be one segment with the maximum number
2134a922
PO		 3323 * of bytes. When doing hardware scatter/gather, each entry cannot
3324 * be larger than 64 KiB though.
d129bceb 3325 */
30652aa3
OJ		 3326 if (host->flags & SDHCI_USE_ADMA) {
3327 if (host->quirks & SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC)
3328 mmc->max_seg_size = 65535;
3329 else
3330 mmc->max_seg_size = 65536;
3331 } else {
2134a922 3332 mmc->max_seg_size = mmc->max_req_size;
30652aa3 3333 }
d129bceb 3334
fe4a3c7a
PO		 3335 /*
3336 * Maximum block size. This varies from controller to controller and
3337 * is specified in the capabilities register.
3338 */
0633f654
AV		 3339 if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) {
3340 mmc->max_blk_size = 2;
3341 } else {
f2119df6 3342 mmc->max_blk_size = (caps[0] & SDHCI_MAX_BLOCK_MASK) >>
0633f654
AV		 3343 SDHCI_MAX_BLOCK_SHIFT;
3344 if (mmc->max_blk_size >= 3) {
6606110d
JP		 3345 pr_warn("%s: Invalid maximum block size, assuming 512 bytes\n",
3346 mmc_hostname(mmc));
0633f654
AV		 3347 mmc->max_blk_size = 0;
3348 }
3349 }
3350
3351 mmc->max_blk_size = 512 << mmc->max_blk_size;
fe4a3c7a 3352
55db890a
PO		 3353 /*
3354 * Maximum block count.
3355 */
1388eefd 3356 mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
55db890a 3357
d129bceb
PO		 3358 /*
3359 * Init tasklets.
3360 */
d129bceb
PO		 3361 tasklet_init(&host->finish_tasklet,
3362 sdhci_tasklet_finish, (unsigned long)host);
3363
e4cad1b5 3364 setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host);
d129bceb 3365
250fb7b4 3366 init_waitqueue_head(&host->buf_ready_int);
b513ea25 3367
2af502ca
SG		 3368 sdhci_init(host, 0);
3369
781e989c
RK		 3370 ret = request_threaded_irq(host->irq, sdhci_irq, sdhci_thread_irq,
3371 IRQF_SHARED, mmc_hostname(mmc), host);
0fc81ee3
MB		 3372 if (ret) {
3373 pr_err("%s: Failed to request IRQ %d: %d\n",
3374 mmc_hostname(mmc), host->irq, ret);
8ef1a143 3375 goto untasklet;
0fc81ee3 3376 }
d129bceb 3377
d129bceb
PO		 3378#ifdef CONFIG_MMC_DEBUG
3379 sdhci_dumpregs(host);
3380#endif
3381
f9134319 3382#ifdef SDHCI_USE_LEDS_CLASS
5dbace0c
HS		 3383 snprintf(host->led_name, sizeof(host->led_name),
3384 "%s::", mmc_hostname(mmc));
3385 host->led.name = host->led_name;
2f730fec
PO		 3386 host->led.brightness = LED_OFF;
3387 host->led.default_trigger = mmc_hostname(mmc);
3388 host->led.brightness_set = sdhci_led_control;
3389
b8c86fc5 3390 ret = led_classdev_register(mmc_dev(mmc), &host->led);
0fc81ee3
MB		 3391 if (ret) {
3392 pr_err("%s: Failed to register LED device: %d\n",
3393 mmc_hostname(mmc), ret);
2f730fec 3394 goto reset;
0fc81ee3 3395 }
2f730fec
PO		 3396#endif
3397
5f25a66f
PO		 3398 mmiowb();
3399
d129bceb
PO		 3400 mmc_add_host(mmc);
3401
a3c76eb9 3402 pr_info("%s: SDHCI controller on %s [%s] using %s\n",
d1b26863 3403 mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)),
e57a5f61
AH		 3404 (host->flags & SDHCI_USE_ADMA) ?
3405 (host->flags & SDHCI_USE_64_BIT_DMA) ? "ADMA 64-bit" : "ADMA" :
a13abc7b 3406 (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO");
d129bceb 3407
7260cf5e
AV		 3408 sdhci_enable_card_detection(host);
3409
d129bceb
PO		 3410 return 0;
3411
f9134319 3412#ifdef SDHCI_USE_LEDS_CLASS
2f730fec 3413reset:
03231f9b 3414 sdhci_do_reset(host, SDHCI_RESET_ALL);
b537f94c
RK		 3415 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
3416 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
2f730fec
PO		 3417 free_irq(host->irq, host);
3418#endif
8ef1a143 3419untasklet:
d129bceb 3420 tasklet_kill(&host->finish_tasklet);
d129bceb
PO		 3421
3422 return ret;
3423}
3424
b8c86fc5 3425EXPORT_SYMBOL_GPL(sdhci_add_host);
d129bceb 3426
1e72859e 3427void sdhci_remove_host(struct sdhci_host *host, int dead)
b8c86fc5 3428{
3a48edc4 3429 struct mmc_host *mmc = host->mmc;
1e72859e
PO		 3430 unsigned long flags;
3431
3432 if (dead) {
3433 spin_lock_irqsave(&host->lock, flags);
3434
3435 host->flags |= SDHCI_DEVICE_DEAD;
3436
3437 if (host->mrq) {
a3c76eb9 3438 pr_err("%s: Controller removed during "
4e743f1f 3439 " transfer!\n", mmc_hostname(mmc));
1e72859e
PO		 3440
3441 host->mrq->cmd->error = -ENOMEDIUM;
3442 tasklet_schedule(&host->finish_tasklet);
3443 }
3444
3445 spin_unlock_irqrestore(&host->lock, flags);
3446 }
3447
7260cf5e
AV		 3448 sdhci_disable_card_detection(host);
3449
4e743f1f 3450 mmc_remove_host(mmc);
d129bceb 3451
f9134319 3452#ifdef SDHCI_USE_LEDS_CLASS
2f730fec
PO		 3453 led_classdev_unregister(&host->led);
3454#endif
3455
1e72859e 3456 if (!dead)
03231f9b 3457 sdhci_do_reset(host, SDHCI_RESET_ALL);
d129bceb 3458
b537f94c
RK		 3459 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
3460 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
d129bceb
PO		 3461 free_irq(host->irq, host);
3462
3463 del_timer_sync(&host->timer);
3464
d129bceb 3465 tasklet_kill(&host->finish_tasklet);
2134a922 3466
3a48edc4
TK		 3467 if (!IS_ERR(mmc->supply.vqmmc))
3468 regulator_disable(mmc->supply.vqmmc);
6231f3de 3469
4efaa6fb 3470 if (host->adma_table)
76fe379a 3471 dma_free_coherent(mmc_dev(mmc), host->adma_table_sz,
4efaa6fb 3472 host->adma_table, host->adma_addr);
2134a922
PO		 3473 kfree(host->align_buffer);
3474
4efaa6fb 3475 host->adma_table = NULL;
2134a922 3476 host->align_buffer = NULL;
d129bceb
PO		 3477}
3478
b8c86fc5 3479EXPORT_SYMBOL_GPL(sdhci_remove_host);
d129bceb 3480
b8c86fc5 3481void sdhci_free_host(struct sdhci_host *host)
d129bceb 3482{
b8c86fc5 3483 mmc_free_host(host->mmc);
d129bceb
PO		 3484}
3485
b8c86fc5 3486EXPORT_SYMBOL_GPL(sdhci_free_host);
d129bceb
PO		 3487
3488/*****************************************************************************\
3489 * *
3490 * Driver init/exit *
3491 * *
3492\*****************************************************************************/
3493
3494static int __init sdhci_drv_init(void)
3495{
a3c76eb9 3496 pr_info(DRIVER_NAME
52fbf9c9 3497 ": Secure Digital Host Controller Interface driver\n");
a3c76eb9 3498 pr_info(DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
d129bceb 3499
b8c86fc5 3500 return 0;
d129bceb
PO		 3501}
3502
3503static void __exit sdhci_drv_exit(void)
3504{
d129bceb
PO		 3505}
3506
3507module_init(sdhci_drv_init);
3508module_exit(sdhci_drv_exit);
3509
df673b22 3510module_param(debug_quirks, uint, 0444);
66fd8ad5 3511module_param(debug_quirks2, uint, 0444);
67435274 3512
32710e8f 3513MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
b8c86fc5 3514MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver");
d129bceb 3515MODULE_LICENSE("GPL");
67435274 3516
df673b22 3517MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");
66fd8ad5 3518MODULE_PARM_DESC(debug_quirks2, "Force certain other quirks.");
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